From a36986a501978084491148a8f2b860b2e374d452 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 5 Jun 2017 14:33:46 +0200 Subject: [PATCH] gen/fhdl/verilog: list available clock domains on keyerror --- litex/gen/fhdl/verilog.py | 3 +++ 1 file changed, 3 insertions(+) diff --git a/litex/gen/fhdl/verilog.py b/litex/gen/fhdl/verilog.py index 1fb6024b..d5aef8d6 100644 --- a/litex/gen/fhdl/verilog.py +++ b/litex/gen/fhdl/verilog.py @@ -339,6 +339,9 @@ def convert(f, ios=None, name="top", f.clock_domains.append(cd) ios |= {cd.clk, cd.rst} else: + print("available clock domains:") + for f in f.clock_domains: + print(f.name) raise KeyError("Unresolved clock domain: '"+cd_name+"'") f = lower_complex_slices(f) -- 2.30.2