From a37574ccbfe047c09a60bb6ee68b7b5e2ef61337 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 23 Jul 2019 14:52:14 -0700 Subject: [PATCH] Fix muxAB logic --- passes/pmgen/ice40_dsp.pmg | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/passes/pmgen/ice40_dsp.pmg b/passes/pmgen/ice40_dsp.pmg index 24247d3cf..4b566f0a6 100644 --- a/passes/pmgen/ice40_dsp.pmg +++ b/passes/pmgen/ice40_dsp.pmg @@ -187,10 +187,9 @@ code clock clock_pol sigO sigCD sigCD_signed // Loading value into output register is not // supported unless using accumulator - if (muxAB && sigCD != sigO) { - if (muxAB != addAB) + if (muxAB) { + if (sigCD != sigO) reject; - if (muxA) sigCD = port(muxAB, \B); else if (muxB) -- 2.30.2