From a3816096a723844888aec4197786ce93512394db Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sat, 28 Sep 2019 00:55:08 +0200 Subject: [PATCH] cores/cpu: define CPUS and simplify instance --- litex/soc/cores/cpu/__init__.py | 12 ++++++++++++ litex/soc/integration/soc_core.py | 20 ++------------------ 2 files changed, 14 insertions(+), 18 deletions(-) diff --git a/litex/soc/cores/cpu/__init__.py b/litex/soc/cores/cpu/__init__.py index 202f994e..e19a0c50 100644 --- a/litex/soc/cores/cpu/__init__.py +++ b/litex/soc/cores/cpu/__init__.py @@ -11,6 +11,18 @@ from litex.soc.cores.cpu.minerva import Minerva from litex.soc.cores.cpu.rocket import RocketRV64 from litex.soc.cores.cpu.serv import SERV +# CPUS --------------------------------------------------------------------------------------------- + +CPUS = { + "lm32" : LM32, + "mor1kx" : MOR1KX, + "picorv32" : PicoRV32, + "vexriscv" : VexRiscv, + "minerva" : Minerva, + "rocket" : RocketRV64, + "serv" : SERV +} + # CPU Variants/Extensions Definition --------------------------------------------------------------- CPU_VARIANTS = { diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py index 5ddd8238..915c0e6e 100644 --- a/litex/soc/integration/soc_core.py +++ b/litex/soc/integration/soc_core.py @@ -264,25 +264,9 @@ class SoCCore(Module): if cpu_variant is not None: self.config["CPU_VARIANT"] = str(cpu_variant.split('+')[0]).upper() # CPU selection / instance - if cpu_type == "lm32": - self.add_cpu(cpu.lm32.LM32(platform, self.cpu_reset_address, self.cpu_variant)) - elif cpu_type == "mor1kx" or cpu_type == "or1k": - if cpu_type == "or1k": - deprecated_warning("SoCCore's \"cpu-type\" to \"mor1kx\"") - self.add_cpu(cpu.mor1kx.MOR1KX(platform, self.cpu_reset_address, self.cpu_variant)) - elif cpu_type == "picorv32": - self.add_cpu(cpu.picorv32.PicoRV32(platform, self.cpu_reset_address, self.cpu_variant)) - elif cpu_type == "vexriscv": - self.add_cpu(cpu.vexriscv.VexRiscv(platform, self.cpu_reset_address, self.cpu_variant)) - elif cpu_type == "minerva": - self.add_cpu(cpu.minerva.Minerva(platform, self.cpu_reset_address, self.cpu_variant)) - elif cpu_type == "rocket": - self.add_cpu(cpu.rocket.RocketRV64(platform, self.cpu_reset_address, self.cpu_variant)) - elif cpu_type == "serv": - self.add_cpu(cpu.serv.SERV(platform, self.cpu_reset_address, self.cpu_variant)) - self.add_constant("UART_POLLING", None) - else: + if cpu_type not in cpu.CPUS.keys(): raise ValueError("Unsupported CPU type: {}".format(cpu_type)) + self.add_cpu(cpu.CPUS[cpu_type](platform, self.cpu_reset_address, self.cpu_variant)) # Add Instruction/Data buses as Wisbone masters self.add_wb_master(self.cpu.ibus) -- 2.30.2