From a3857aac940437c18a46d518929ea7e78ac7e61e Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Wed, 27 May 2020 11:06:51 +1000 Subject: [PATCH] litedram: Add an L2 cache with store queue This adds a cache between the wishbone and litedram with the following features (at this point, it's still evolving) - 128 bytes line width in order to have a reasonable amount of litedram pipelining on the 128-bit wide data port. - Configurable geometry otherwise - Stores are acked immediately on wishbone whether hit or miss (minus a 2 cycles delay if there's a previous load response in the way) and sent to LiteDRAM via 8 entries (configurable) store queue Signed-off-by: Benjamin Herrenschmidt --- Makefile | 2 +- litedram/extras/wave.gtkw | 122 ++ litedram/extras/wave.opt | 84 + litedram/extras/wrapper-mw-init.vhdl | 1129 +++++++++++--- litedram/gen-src/sdram_init/include/system.h | 6 +- litedram/generated/arty/litedram_core.init | 1375 +++++++++-------- litedram/generated/arty/litedram_core.v | 2 +- .../generated/nexys-video/litedram_core.init | 1375 +++++++++-------- .../generated/nexys-video/litedram_core.v | 2 +- litedram/generated/sim/litedram_core.init | 351 +++-- litedram/generated/sim/litedram_core.v | 2 +- microwatt.core | 1 + sync_fifo.vhdl | 163 ++ 13 files changed, 2900 insertions(+), 1714 deletions(-) create mode 100644 litedram/extras/wave.gtkw create mode 100644 litedram/extras/wave.opt create mode 100644 sync_fifo.vhdl diff --git a/Makefile b/Makefile index ea7181c..9ed6ff8 100644 --- a/Makefile +++ b/Makefile @@ -50,7 +50,7 @@ core_files = decode_types.vhdl common.vhdl wishbone_types.vhdl fetch1.vhdl \ loadstore1.vhdl mmu.vhdl dcache.vhdl writeback.vhdl core_debug.vhdl \ core.vhdl -soc_files = wishbone_arbiter.vhdl wishbone_bram_wrapper.vhdl \ +soc_files = wishbone_arbiter.vhdl wishbone_bram_wrapper.vhdl sync_fifo.vhdl \ wishbone_debug_master.vhdl xics.vhdl syscon.vhdl soc.vhdl soc_sim_files = sim_console.vhdl sim_uart.vhdl sim_bram_helpers.vhdl \ diff --git a/litedram/extras/wave.gtkw b/litedram/extras/wave.gtkw new file mode 100644 index 0000000..e0d0637 --- /dev/null +++ b/litedram/extras/wave.gtkw @@ -0,0 +1,122 @@ +[*] +[*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI +[*] Sat May 30 08:37:38 2020 +[*] +[dumpfile] "/home/ANT.AMAZON.COM/benh/hackplace/microwatt/foo.ghw" +[dumpfile_mtime] "Sat May 30 08:35:43 2020" +[dumpfile_size] 1424191 +[savefile] "/home/ANT.AMAZON.COM/benh/hackplace/microwatt/litedram/extras/wave.gtkw" +[timestart] 677520000 +[size] 2509 1371 +[pos] -1 -1 +*-24.000000 642355000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[treeopen] top. +[treeopen] top.core_dram_tb. +[treeopen] top.core_dram_tb.dram. +[sst_width] 301 +[signals_width] 366 +[sst_expanded] 1 +[sst_vpaned_height] 410 +@28 +top.core_dram_tb.dram.system_clk +@200 +-wb_in +@22 +#{top.core_dram_tb.dram.wb_in.adr[31:0]} top.core_dram_tb.dram.wb_in.adr[31] top.core_dram_tb.dram.wb_in.adr[30] top.core_dram_tb.dram.wb_in.adr[29] top.core_dram_tb.dram.wb_in.adr[28] top.core_dram_tb.dram.wb_in.adr[27] top.core_dram_tb.dram.wb_in.adr[26] top.core_dram_tb.dram.wb_in.adr[25] top.core_dram_tb.dram.wb_in.adr[24] top.core_dram_tb.dram.wb_in.adr[23] top.core_dram_tb.dram.wb_in.adr[22] top.core_dram_tb.dram.wb_in.adr[21] top.core_dram_tb.dram.wb_in.adr[20] top.core_dram_tb.dram.wb_in.adr[19] top.core_dram_tb.dram.wb_in.adr[18] top.core_dram_tb.dram.wb_in.adr[17] top.core_dram_tb.dram.wb_in.adr[16] top.core_dram_tb.dram.wb_in.adr[15] top.core_dram_tb.dram.wb_in.adr[14] top.core_dram_tb.dram.wb_in.adr[13] top.core_dram_tb.dram.wb_in.adr[12] top.core_dram_tb.dram.wb_in.adr[11] top.core_dram_tb.dram.wb_in.adr[10] top.core_dram_tb.dram.wb_in.adr[9] top.core_dram_tb.dram.wb_in.adr[8] top.core_dram_tb.dram.wb_in.adr[7] top.core_dram_tb.dram.wb_in.adr[6] top.core_dram_tb.dram.wb_in.adr[5] top.core_dram_tb.dram.wb_in.adr[4] top.core_dram_tb.dram.wb_in.adr[3] top.core_dram_tb.dram.wb_in.adr[2] top.core_dram_tb.dram.wb_in.adr[1] top.core_dram_tb.dram.wb_in.adr[0] +@28 +top.core_dram_tb.dram.wb_in.cyc +@22 +#{top.core_dram_tb.dram.wb_in.dat[63:0]} top.core_dram_tb.dram.wb_in.dat[63] top.core_dram_tb.dram.wb_in.dat[62] top.core_dram_tb.dram.wb_in.dat[61] top.core_dram_tb.dram.wb_in.dat[60] top.core_dram_tb.dram.wb_in.dat[59] top.core_dram_tb.dram.wb_in.dat[58] top.core_dram_tb.dram.wb_in.dat[57] top.core_dram_tb.dram.wb_in.dat[56] top.core_dram_tb.dram.wb_in.dat[55] top.core_dram_tb.dram.wb_in.dat[54] top.core_dram_tb.dram.wb_in.dat[53] top.core_dram_tb.dram.wb_in.dat[52] top.core_dram_tb.dram.wb_in.dat[51] top.core_dram_tb.dram.wb_in.dat[50] top.core_dram_tb.dram.wb_in.dat[49] top.core_dram_tb.dram.wb_in.dat[48] top.core_dram_tb.dram.wb_in.dat[47] top.core_dram_tb.dram.wb_in.dat[46] top.core_dram_tb.dram.wb_in.dat[45] top.core_dram_tb.dram.wb_in.dat[44] top.core_dram_tb.dram.wb_in.dat[43] top.core_dram_tb.dram.wb_in.dat[42] top.core_dram_tb.dram.wb_in.dat[41] top.core_dram_tb.dram.wb_in.dat[40] top.core_dram_tb.dram.wb_in.dat[39] top.core_dram_tb.dram.wb_in.dat[38] top.core_dram_tb.dram.wb_in.dat[37] top.core_dram_tb.dram.wb_in.dat[36] top.core_dram_tb.dram.wb_in.dat[35] top.core_dram_tb.dram.wb_in.dat[34] top.core_dram_tb.dram.wb_in.dat[33] top.core_dram_tb.dram.wb_in.dat[32] top.core_dram_tb.dram.wb_in.dat[31] top.core_dram_tb.dram.wb_in.dat[30] top.core_dram_tb.dram.wb_in.dat[29] top.core_dram_tb.dram.wb_in.dat[28] top.core_dram_tb.dram.wb_in.dat[27] top.core_dram_tb.dram.wb_in.dat[26] top.core_dram_tb.dram.wb_in.dat[25] top.core_dram_tb.dram.wb_in.dat[24] top.core_dram_tb.dram.wb_in.dat[23] top.core_dram_tb.dram.wb_in.dat[22] top.core_dram_tb.dram.wb_in.dat[21] top.core_dram_tb.dram.wb_in.dat[20] top.core_dram_tb.dram.wb_in.dat[19] top.core_dram_tb.dram.wb_in.dat[18] top.core_dram_tb.dram.wb_in.dat[17] top.core_dram_tb.dram.wb_in.dat[16] top.core_dram_tb.dram.wb_in.dat[15] top.core_dram_tb.dram.wb_in.dat[14] top.core_dram_tb.dram.wb_in.dat[13] top.core_dram_tb.dram.wb_in.dat[12] top.core_dram_tb.dram.wb_in.dat[11] top.core_dram_tb.dram.wb_in.dat[10] top.core_dram_tb.dram.wb_in.dat[9] top.core_dram_tb.dram.wb_in.dat[8] top.core_dram_tb.dram.wb_in.dat[7] top.core_dram_tb.dram.wb_in.dat[6] top.core_dram_tb.dram.wb_in.dat[5] top.core_dram_tb.dram.wb_in.dat[4] top.core_dram_tb.dram.wb_in.dat[3] top.core_dram_tb.dram.wb_in.dat[2] top.core_dram_tb.dram.wb_in.dat[1] top.core_dram_tb.dram.wb_in.dat[0] +#{top.core_dram_tb.dram.wb_in.sel[7:0]} top.core_dram_tb.dram.wb_in.sel[7] top.core_dram_tb.dram.wb_in.sel[6] top.core_dram_tb.dram.wb_in.sel[5] top.core_dram_tb.dram.wb_in.sel[4] top.core_dram_tb.dram.wb_in.sel[3] top.core_dram_tb.dram.wb_in.sel[2] top.core_dram_tb.dram.wb_in.sel[1] top.core_dram_tb.dram.wb_in.sel[0] +@28 +top.core_dram_tb.dram.wb_in.stb +top.core_dram_tb.dram.wb_in.we +@200 +- +-wb_out +@28 +top.core_dram_tb.dram.wb_out.ack +@22 +#{top.core_dram_tb.dram.wb_out.dat[63:0]} top.core_dram_tb.dram.wb_out.dat[63] top.core_dram_tb.dram.wb_out.dat[62] top.core_dram_tb.dram.wb_out.dat[61] top.core_dram_tb.dram.wb_out.dat[60] top.core_dram_tb.dram.wb_out.dat[59] top.core_dram_tb.dram.wb_out.dat[58] top.core_dram_tb.dram.wb_out.dat[57] top.core_dram_tb.dram.wb_out.dat[56] top.core_dram_tb.dram.wb_out.dat[55] top.core_dram_tb.dram.wb_out.dat[54] top.core_dram_tb.dram.wb_out.dat[53] top.core_dram_tb.dram.wb_out.dat[52] top.core_dram_tb.dram.wb_out.dat[51] top.core_dram_tb.dram.wb_out.dat[50] top.core_dram_tb.dram.wb_out.dat[49] top.core_dram_tb.dram.wb_out.dat[48] top.core_dram_tb.dram.wb_out.dat[47] top.core_dram_tb.dram.wb_out.dat[46] top.core_dram_tb.dram.wb_out.dat[45] top.core_dram_tb.dram.wb_out.dat[44] top.core_dram_tb.dram.wb_out.dat[43] top.core_dram_tb.dram.wb_out.dat[42] top.core_dram_tb.dram.wb_out.dat[41] top.core_dram_tb.dram.wb_out.dat[40] top.core_dram_tb.dram.wb_out.dat[39] top.core_dram_tb.dram.wb_out.dat[38] top.core_dram_tb.dram.wb_out.dat[37] top.core_dram_tb.dram.wb_out.dat[36] top.core_dram_tb.dram.wb_out.dat[35] top.core_dram_tb.dram.wb_out.dat[34] top.core_dram_tb.dram.wb_out.dat[33] top.core_dram_tb.dram.wb_out.dat[32] top.core_dram_tb.dram.wb_out.dat[31] top.core_dram_tb.dram.wb_out.dat[30] top.core_dram_tb.dram.wb_out.dat[29] top.core_dram_tb.dram.wb_out.dat[28] top.core_dram_tb.dram.wb_out.dat[27] top.core_dram_tb.dram.wb_out.dat[26] top.core_dram_tb.dram.wb_out.dat[25] top.core_dram_tb.dram.wb_out.dat[24] top.core_dram_tb.dram.wb_out.dat[23] top.core_dram_tb.dram.wb_out.dat[22] top.core_dram_tb.dram.wb_out.dat[21] top.core_dram_tb.dram.wb_out.dat[20] top.core_dram_tb.dram.wb_out.dat[19] top.core_dram_tb.dram.wb_out.dat[18] top.core_dram_tb.dram.wb_out.dat[17] top.core_dram_tb.dram.wb_out.dat[16] top.core_dram_tb.dram.wb_out.dat[15] top.core_dram_tb.dram.wb_out.dat[14] top.core_dram_tb.dram.wb_out.dat[13] top.core_dram_tb.dram.wb_out.dat[12] top.core_dram_tb.dram.wb_out.dat[11] top.core_dram_tb.dram.wb_out.dat[10] top.core_dram_tb.dram.wb_out.dat[9] top.core_dram_tb.dram.wb_out.dat[8] top.core_dram_tb.dram.wb_out.dat[7] top.core_dram_tb.dram.wb_out.dat[6] top.core_dram_tb.dram.wb_out.dat[5] top.core_dram_tb.dram.wb_out.dat[4] top.core_dram_tb.dram.wb_out.dat[3] top.core_dram_tb.dram.wb_out.dat[2] top.core_dram_tb.dram.wb_out.dat[1] top.core_dram_tb.dram.wb_out.dat[0] +@28 +top.core_dram_tb.dram.wb_out.stall +@200 +- +-wb_req +@22 +#{top.core_dram_tb.dram.wb_req.adr[31:0]} top.core_dram_tb.dram.wb_req.adr[31] top.core_dram_tb.dram.wb_req.adr[30] top.core_dram_tb.dram.wb_req.adr[29] top.core_dram_tb.dram.wb_req.adr[28] top.core_dram_tb.dram.wb_req.adr[27] top.core_dram_tb.dram.wb_req.adr[26] top.core_dram_tb.dram.wb_req.adr[25] top.core_dram_tb.dram.wb_req.adr[24] top.core_dram_tb.dram.wb_req.adr[23] top.core_dram_tb.dram.wb_req.adr[22] top.core_dram_tb.dram.wb_req.adr[21] top.core_dram_tb.dram.wb_req.adr[20] top.core_dram_tb.dram.wb_req.adr[19] top.core_dram_tb.dram.wb_req.adr[18] top.core_dram_tb.dram.wb_req.adr[17] top.core_dram_tb.dram.wb_req.adr[16] top.core_dram_tb.dram.wb_req.adr[15] top.core_dram_tb.dram.wb_req.adr[14] top.core_dram_tb.dram.wb_req.adr[13] top.core_dram_tb.dram.wb_req.adr[12] top.core_dram_tb.dram.wb_req.adr[11] top.core_dram_tb.dram.wb_req.adr[10] top.core_dram_tb.dram.wb_req.adr[9] top.core_dram_tb.dram.wb_req.adr[8] top.core_dram_tb.dram.wb_req.adr[7] top.core_dram_tb.dram.wb_req.adr[6] top.core_dram_tb.dram.wb_req.adr[5] top.core_dram_tb.dram.wb_req.adr[4] top.core_dram_tb.dram.wb_req.adr[3] top.core_dram_tb.dram.wb_req.adr[2] top.core_dram_tb.dram.wb_req.adr[1] top.core_dram_tb.dram.wb_req.adr[0] +@28 +top.core_dram_tb.dram.wb_req.cyc +@22 +#{top.core_dram_tb.dram.wb_req.dat[63:0]} top.core_dram_tb.dram.wb_req.dat[63] top.core_dram_tb.dram.wb_req.dat[62] top.core_dram_tb.dram.wb_req.dat[61] top.core_dram_tb.dram.wb_req.dat[60] top.core_dram_tb.dram.wb_req.dat[59] top.core_dram_tb.dram.wb_req.dat[58] top.core_dram_tb.dram.wb_req.dat[57] top.core_dram_tb.dram.wb_req.dat[56] top.core_dram_tb.dram.wb_req.dat[55] top.core_dram_tb.dram.wb_req.dat[54] top.core_dram_tb.dram.wb_req.dat[53] top.core_dram_tb.dram.wb_req.dat[52] top.core_dram_tb.dram.wb_req.dat[51] top.core_dram_tb.dram.wb_req.dat[50] top.core_dram_tb.dram.wb_req.dat[49] top.core_dram_tb.dram.wb_req.dat[48] top.core_dram_tb.dram.wb_req.dat[47] top.core_dram_tb.dram.wb_req.dat[46] top.core_dram_tb.dram.wb_req.dat[45] top.core_dram_tb.dram.wb_req.dat[44] top.core_dram_tb.dram.wb_req.dat[43] top.core_dram_tb.dram.wb_req.dat[42] top.core_dram_tb.dram.wb_req.dat[41] top.core_dram_tb.dram.wb_req.dat[40] top.core_dram_tb.dram.wb_req.dat[39] top.core_dram_tb.dram.wb_req.dat[38] top.core_dram_tb.dram.wb_req.dat[37] top.core_dram_tb.dram.wb_req.dat[36] top.core_dram_tb.dram.wb_req.dat[35] top.core_dram_tb.dram.wb_req.dat[34] top.core_dram_tb.dram.wb_req.dat[33] top.core_dram_tb.dram.wb_req.dat[32] top.core_dram_tb.dram.wb_req.dat[31] top.core_dram_tb.dram.wb_req.dat[30] top.core_dram_tb.dram.wb_req.dat[29] top.core_dram_tb.dram.wb_req.dat[28] top.core_dram_tb.dram.wb_req.dat[27] top.core_dram_tb.dram.wb_req.dat[26] top.core_dram_tb.dram.wb_req.dat[25] top.core_dram_tb.dram.wb_req.dat[24] top.core_dram_tb.dram.wb_req.dat[23] top.core_dram_tb.dram.wb_req.dat[22] top.core_dram_tb.dram.wb_req.dat[21] top.core_dram_tb.dram.wb_req.dat[20] top.core_dram_tb.dram.wb_req.dat[19] top.core_dram_tb.dram.wb_req.dat[18] top.core_dram_tb.dram.wb_req.dat[17] top.core_dram_tb.dram.wb_req.dat[16] top.core_dram_tb.dram.wb_req.dat[15] top.core_dram_tb.dram.wb_req.dat[14] top.core_dram_tb.dram.wb_req.dat[13] top.core_dram_tb.dram.wb_req.dat[12] top.core_dram_tb.dram.wb_req.dat[11] top.core_dram_tb.dram.wb_req.dat[10] top.core_dram_tb.dram.wb_req.dat[9] top.core_dram_tb.dram.wb_req.dat[8] top.core_dram_tb.dram.wb_req.dat[7] top.core_dram_tb.dram.wb_req.dat[6] top.core_dram_tb.dram.wb_req.dat[5] top.core_dram_tb.dram.wb_req.dat[4] top.core_dram_tb.dram.wb_req.dat[3] top.core_dram_tb.dram.wb_req.dat[2] top.core_dram_tb.dram.wb_req.dat[1] top.core_dram_tb.dram.wb_req.dat[0] +#{top.core_dram_tb.dram.wb_req.sel[7:0]} top.core_dram_tb.dram.wb_req.sel[7] top.core_dram_tb.dram.wb_req.sel[6] top.core_dram_tb.dram.wb_req.sel[5] top.core_dram_tb.dram.wb_req.sel[4] top.core_dram_tb.dram.wb_req.sel[3] top.core_dram_tb.dram.wb_req.sel[2] top.core_dram_tb.dram.wb_req.sel[1] top.core_dram_tb.dram.wb_req.sel[0] +@28 +top.core_dram_tb.dram.wb_req.stb +top.core_dram_tb.dram.wb_req.we +@200 +- +-user_port +@28 +top.core_dram_tb.dram.user_port0_rdata_ready +top.core_dram_tb.dram.user_port0_rdata_valid +top.core_dram_tb.dram.user_port0_wdata_ready +top.core_dram_tb.dram.user_port0_wdata_valid +top.core_dram_tb.dram.user_port0_cmd_we +top.core_dram_tb.dram.user_port0_cmd_ready +top.core_dram_tb.dram.user_port0_cmd_valid +@22 +#{top.core_dram_tb.dram.user_port0_rdata_data[127:0]} top.core_dram_tb.dram.user_port0_rdata_data[127] top.core_dram_tb.dram.user_port0_rdata_data[126] top.core_dram_tb.dram.user_port0_rdata_data[125] top.core_dram_tb.dram.user_port0_rdata_data[124] top.core_dram_tb.dram.user_port0_rdata_data[123] top.core_dram_tb.dram.user_port0_rdata_data[122] top.core_dram_tb.dram.user_port0_rdata_data[121] top.core_dram_tb.dram.user_port0_rdata_data[120] top.core_dram_tb.dram.user_port0_rdata_data[119] top.core_dram_tb.dram.user_port0_rdata_data[118] top.core_dram_tb.dram.user_port0_rdata_data[117] top.core_dram_tb.dram.user_port0_rdata_data[116] top.core_dram_tb.dram.user_port0_rdata_data[115] top.core_dram_tb.dram.user_port0_rdata_data[114] top.core_dram_tb.dram.user_port0_rdata_data[113] top.core_dram_tb.dram.user_port0_rdata_data[112] top.core_dram_tb.dram.user_port0_rdata_data[111] top.core_dram_tb.dram.user_port0_rdata_data[110] top.core_dram_tb.dram.user_port0_rdata_data[109] top.core_dram_tb.dram.user_port0_rdata_data[108] top.core_dram_tb.dram.user_port0_rdata_data[107] top.core_dram_tb.dram.user_port0_rdata_data[106] top.core_dram_tb.dram.user_port0_rdata_data[105] top.core_dram_tb.dram.user_port0_rdata_data[104] top.core_dram_tb.dram.user_port0_rdata_data[103] top.core_dram_tb.dram.user_port0_rdata_data[102] top.core_dram_tb.dram.user_port0_rdata_data[101] top.core_dram_tb.dram.user_port0_rdata_data[100] top.core_dram_tb.dram.user_port0_rdata_data[99] top.core_dram_tb.dram.user_port0_rdata_data[98] top.core_dram_tb.dram.user_port0_rdata_data[97] top.core_dram_tb.dram.user_port0_rdata_data[96] top.core_dram_tb.dram.user_port0_rdata_data[95] top.core_dram_tb.dram.user_port0_rdata_data[94] top.core_dram_tb.dram.user_port0_rdata_data[93] top.core_dram_tb.dram.user_port0_rdata_data[92] top.core_dram_tb.dram.user_port0_rdata_data[91] top.core_dram_tb.dram.user_port0_rdata_data[90] top.core_dram_tb.dram.user_port0_rdata_data[89] top.core_dram_tb.dram.user_port0_rdata_data[88] top.core_dram_tb.dram.user_port0_rdata_data[87] top.core_dram_tb.dram.user_port0_rdata_data[86] top.core_dram_tb.dram.user_port0_rdata_data[85] top.core_dram_tb.dram.user_port0_rdata_data[84] top.core_dram_tb.dram.user_port0_rdata_data[83] top.core_dram_tb.dram.user_port0_rdata_data[82] top.core_dram_tb.dram.user_port0_rdata_data[81] top.core_dram_tb.dram.user_port0_rdata_data[80] top.core_dram_tb.dram.user_port0_rdata_data[79] top.core_dram_tb.dram.user_port0_rdata_data[78] top.core_dram_tb.dram.user_port0_rdata_data[77] top.core_dram_tb.dram.user_port0_rdata_data[76] top.core_dram_tb.dram.user_port0_rdata_data[75] top.core_dram_tb.dram.user_port0_rdata_data[74] top.core_dram_tb.dram.user_port0_rdata_data[73] top.core_dram_tb.dram.user_port0_rdata_data[72] top.core_dram_tb.dram.user_port0_rdata_data[71] top.core_dram_tb.dram.user_port0_rdata_data[70] top.core_dram_tb.dram.user_port0_rdata_data[69] top.core_dram_tb.dram.user_port0_rdata_data[68] top.core_dram_tb.dram.user_port0_rdata_data[67] top.core_dram_tb.dram.user_port0_rdata_data[66] top.core_dram_tb.dram.user_port0_rdata_data[65] top.core_dram_tb.dram.user_port0_rdata_data[64] top.core_dram_tb.dram.user_port0_rdata_data[63] top.core_dram_tb.dram.user_port0_rdata_data[62] top.core_dram_tb.dram.user_port0_rdata_data[61] top.core_dram_tb.dram.user_port0_rdata_data[60] top.core_dram_tb.dram.user_port0_rdata_data[59] top.core_dram_tb.dram.user_port0_rdata_data[58] top.core_dram_tb.dram.user_port0_rdata_data[57] top.core_dram_tb.dram.user_port0_rdata_data[56] top.core_dram_tb.dram.user_port0_rdata_data[55] top.core_dram_tb.dram.user_port0_rdata_data[54] top.core_dram_tb.dram.user_port0_rdata_data[53] top.core_dram_tb.dram.user_port0_rdata_data[52] top.core_dram_tb.dram.user_port0_rdata_data[51] top.core_dram_tb.dram.user_port0_rdata_data[50] top.core_dram_tb.dram.user_port0_rdata_data[49] top.core_dram_tb.dram.user_port0_rdata_data[48] top.core_dram_tb.dram.user_port0_rdata_data[47] top.core_dram_tb.dram.user_port0_rdata_data[46] top.core_dram_tb.dram.user_port0_rdata_data[45] top.core_dram_tb.dram.user_port0_rdata_data[44] top.core_dram_tb.dram.user_port0_rdata_data[43] top.core_dram_tb.dram.user_port0_rdata_data[42] top.core_dram_tb.dram.user_port0_rdata_data[41] top.core_dram_tb.dram.user_port0_rdata_data[40] top.core_dram_tb.dram.user_port0_rdata_data[39] top.core_dram_tb.dram.user_port0_rdata_data[38] top.core_dram_tb.dram.user_port0_rdata_data[37] top.core_dram_tb.dram.user_port0_rdata_data[36] top.core_dram_tb.dram.user_port0_rdata_data[35] top.core_dram_tb.dram.user_port0_rdata_data[34] top.core_dram_tb.dram.user_port0_rdata_data[33] top.core_dram_tb.dram.user_port0_rdata_data[32] top.core_dram_tb.dram.user_port0_rdata_data[31] top.core_dram_tb.dram.user_port0_rdata_data[30] top.core_dram_tb.dram.user_port0_rdata_data[29] top.core_dram_tb.dram.user_port0_rdata_data[28] top.core_dram_tb.dram.user_port0_rdata_data[27] top.core_dram_tb.dram.user_port0_rdata_data[26] top.core_dram_tb.dram.user_port0_rdata_data[25] top.core_dram_tb.dram.user_port0_rdata_data[24] top.core_dram_tb.dram.user_port0_rdata_data[23] top.core_dram_tb.dram.user_port0_rdata_data[22] top.core_dram_tb.dram.user_port0_rdata_data[21] top.core_dram_tb.dram.user_port0_rdata_data[20] top.core_dram_tb.dram.user_port0_rdata_data[19] top.core_dram_tb.dram.user_port0_rdata_data[18] top.core_dram_tb.dram.user_port0_rdata_data[17] top.core_dram_tb.dram.user_port0_rdata_data[16] top.core_dram_tb.dram.user_port0_rdata_data[15] top.core_dram_tb.dram.user_port0_rdata_data[14] top.core_dram_tb.dram.user_port0_rdata_data[13] top.core_dram_tb.dram.user_port0_rdata_data[12] top.core_dram_tb.dram.user_port0_rdata_data[11] top.core_dram_tb.dram.user_port0_rdata_data[10] top.core_dram_tb.dram.user_port0_rdata_data[9] top.core_dram_tb.dram.user_port0_rdata_data[8] top.core_dram_tb.dram.user_port0_rdata_data[7] top.core_dram_tb.dram.user_port0_rdata_data[6] top.core_dram_tb.dram.user_port0_rdata_data[5] top.core_dram_tb.dram.user_port0_rdata_data[4] top.core_dram_tb.dram.user_port0_rdata_data[3] top.core_dram_tb.dram.user_port0_rdata_data[2] top.core_dram_tb.dram.user_port0_rdata_data[1] top.core_dram_tb.dram.user_port0_rdata_data[0] +#{top.core_dram_tb.dram.user_port0_wdata_data[127:0]} top.core_dram_tb.dram.user_port0_wdata_data[127] top.core_dram_tb.dram.user_port0_wdata_data[126] top.core_dram_tb.dram.user_port0_wdata_data[125] top.core_dram_tb.dram.user_port0_wdata_data[124] top.core_dram_tb.dram.user_port0_wdata_data[123] top.core_dram_tb.dram.user_port0_wdata_data[122] top.core_dram_tb.dram.user_port0_wdata_data[121] top.core_dram_tb.dram.user_port0_wdata_data[120] top.core_dram_tb.dram.user_port0_wdata_data[119] top.core_dram_tb.dram.user_port0_wdata_data[118] top.core_dram_tb.dram.user_port0_wdata_data[117] top.core_dram_tb.dram.user_port0_wdata_data[116] top.core_dram_tb.dram.user_port0_wdata_data[115] top.core_dram_tb.dram.user_port0_wdata_data[114] top.core_dram_tb.dram.user_port0_wdata_data[113] top.core_dram_tb.dram.user_port0_wdata_data[112] top.core_dram_tb.dram.user_port0_wdata_data[111] top.core_dram_tb.dram.user_port0_wdata_data[110] top.core_dram_tb.dram.user_port0_wdata_data[109] top.core_dram_tb.dram.user_port0_wdata_data[108] top.core_dram_tb.dram.user_port0_wdata_data[107] top.core_dram_tb.dram.user_port0_wdata_data[106] top.core_dram_tb.dram.user_port0_wdata_data[105] top.core_dram_tb.dram.user_port0_wdata_data[104] top.core_dram_tb.dram.user_port0_wdata_data[103] top.core_dram_tb.dram.user_port0_wdata_data[102] top.core_dram_tb.dram.user_port0_wdata_data[101] top.core_dram_tb.dram.user_port0_wdata_data[100] top.core_dram_tb.dram.user_port0_wdata_data[99] top.core_dram_tb.dram.user_port0_wdata_data[98] top.core_dram_tb.dram.user_port0_wdata_data[97] top.core_dram_tb.dram.user_port0_wdata_data[96] top.core_dram_tb.dram.user_port0_wdata_data[95] top.core_dram_tb.dram.user_port0_wdata_data[94] top.core_dram_tb.dram.user_port0_wdata_data[93] top.core_dram_tb.dram.user_port0_wdata_data[92] top.core_dram_tb.dram.user_port0_wdata_data[91] top.core_dram_tb.dram.user_port0_wdata_data[90] top.core_dram_tb.dram.user_port0_wdata_data[89] top.core_dram_tb.dram.user_port0_wdata_data[88] top.core_dram_tb.dram.user_port0_wdata_data[87] top.core_dram_tb.dram.user_port0_wdata_data[86] top.core_dram_tb.dram.user_port0_wdata_data[85] top.core_dram_tb.dram.user_port0_wdata_data[84] top.core_dram_tb.dram.user_port0_wdata_data[83] top.core_dram_tb.dram.user_port0_wdata_data[82] top.core_dram_tb.dram.user_port0_wdata_data[81] top.core_dram_tb.dram.user_port0_wdata_data[80] top.core_dram_tb.dram.user_port0_wdata_data[79] top.core_dram_tb.dram.user_port0_wdata_data[78] top.core_dram_tb.dram.user_port0_wdata_data[77] top.core_dram_tb.dram.user_port0_wdata_data[76] top.core_dram_tb.dram.user_port0_wdata_data[75] top.core_dram_tb.dram.user_port0_wdata_data[74] top.core_dram_tb.dram.user_port0_wdata_data[73] top.core_dram_tb.dram.user_port0_wdata_data[72] top.core_dram_tb.dram.user_port0_wdata_data[71] top.core_dram_tb.dram.user_port0_wdata_data[70] top.core_dram_tb.dram.user_port0_wdata_data[69] top.core_dram_tb.dram.user_port0_wdata_data[68] top.core_dram_tb.dram.user_port0_wdata_data[67] top.core_dram_tb.dram.user_port0_wdata_data[66] top.core_dram_tb.dram.user_port0_wdata_data[65] top.core_dram_tb.dram.user_port0_wdata_data[64] top.core_dram_tb.dram.user_port0_wdata_data[63] top.core_dram_tb.dram.user_port0_wdata_data[62] top.core_dram_tb.dram.user_port0_wdata_data[61] top.core_dram_tb.dram.user_port0_wdata_data[60] top.core_dram_tb.dram.user_port0_wdata_data[59] top.core_dram_tb.dram.user_port0_wdata_data[58] top.core_dram_tb.dram.user_port0_wdata_data[57] top.core_dram_tb.dram.user_port0_wdata_data[56] top.core_dram_tb.dram.user_port0_wdata_data[55] top.core_dram_tb.dram.user_port0_wdata_data[54] top.core_dram_tb.dram.user_port0_wdata_data[53] top.core_dram_tb.dram.user_port0_wdata_data[52] top.core_dram_tb.dram.user_port0_wdata_data[51] top.core_dram_tb.dram.user_port0_wdata_data[50] top.core_dram_tb.dram.user_port0_wdata_data[49] top.core_dram_tb.dram.user_port0_wdata_data[48] top.core_dram_tb.dram.user_port0_wdata_data[47] top.core_dram_tb.dram.user_port0_wdata_data[46] top.core_dram_tb.dram.user_port0_wdata_data[45] top.core_dram_tb.dram.user_port0_wdata_data[44] top.core_dram_tb.dram.user_port0_wdata_data[43] top.core_dram_tb.dram.user_port0_wdata_data[42] top.core_dram_tb.dram.user_port0_wdata_data[41] top.core_dram_tb.dram.user_port0_wdata_data[40] top.core_dram_tb.dram.user_port0_wdata_data[39] top.core_dram_tb.dram.user_port0_wdata_data[38] top.core_dram_tb.dram.user_port0_wdata_data[37] top.core_dram_tb.dram.user_port0_wdata_data[36] top.core_dram_tb.dram.user_port0_wdata_data[35] top.core_dram_tb.dram.user_port0_wdata_data[34] top.core_dram_tb.dram.user_port0_wdata_data[33] top.core_dram_tb.dram.user_port0_wdata_data[32] top.core_dram_tb.dram.user_port0_wdata_data[31] top.core_dram_tb.dram.user_port0_wdata_data[30] top.core_dram_tb.dram.user_port0_wdata_data[29] top.core_dram_tb.dram.user_port0_wdata_data[28] top.core_dram_tb.dram.user_port0_wdata_data[27] top.core_dram_tb.dram.user_port0_wdata_data[26] top.core_dram_tb.dram.user_port0_wdata_data[25] top.core_dram_tb.dram.user_port0_wdata_data[24] top.core_dram_tb.dram.user_port0_wdata_data[23] top.core_dram_tb.dram.user_port0_wdata_data[22] top.core_dram_tb.dram.user_port0_wdata_data[21] top.core_dram_tb.dram.user_port0_wdata_data[20] top.core_dram_tb.dram.user_port0_wdata_data[19] top.core_dram_tb.dram.user_port0_wdata_data[18] top.core_dram_tb.dram.user_port0_wdata_data[17] top.core_dram_tb.dram.user_port0_wdata_data[16] top.core_dram_tb.dram.user_port0_wdata_data[15] top.core_dram_tb.dram.user_port0_wdata_data[14] top.core_dram_tb.dram.user_port0_wdata_data[13] top.core_dram_tb.dram.user_port0_wdata_data[12] top.core_dram_tb.dram.user_port0_wdata_data[11] top.core_dram_tb.dram.user_port0_wdata_data[10] top.core_dram_tb.dram.user_port0_wdata_data[9] top.core_dram_tb.dram.user_port0_wdata_data[8] top.core_dram_tb.dram.user_port0_wdata_data[7] top.core_dram_tb.dram.user_port0_wdata_data[6] top.core_dram_tb.dram.user_port0_wdata_data[5] top.core_dram_tb.dram.user_port0_wdata_data[4] top.core_dram_tb.dram.user_port0_wdata_data[3] top.core_dram_tb.dram.user_port0_wdata_data[2] top.core_dram_tb.dram.user_port0_wdata_data[1] top.core_dram_tb.dram.user_port0_wdata_data[0] +#{top.core_dram_tb.dram.user_port0_wdata_we[15:0]} top.core_dram_tb.dram.user_port0_wdata_we[15] top.core_dram_tb.dram.user_port0_wdata_we[14] top.core_dram_tb.dram.user_port0_wdata_we[13] top.core_dram_tb.dram.user_port0_wdata_we[12] top.core_dram_tb.dram.user_port0_wdata_we[11] top.core_dram_tb.dram.user_port0_wdata_we[10] top.core_dram_tb.dram.user_port0_wdata_we[9] top.core_dram_tb.dram.user_port0_wdata_we[8] top.core_dram_tb.dram.user_port0_wdata_we[7] top.core_dram_tb.dram.user_port0_wdata_we[6] top.core_dram_tb.dram.user_port0_wdata_we[5] top.core_dram_tb.dram.user_port0_wdata_we[4] top.core_dram_tb.dram.user_port0_wdata_we[3] top.core_dram_tb.dram.user_port0_wdata_we[2] top.core_dram_tb.dram.user_port0_wdata_we[1] top.core_dram_tb.dram.user_port0_wdata_we[0] +#{top.core_dram_tb.dram.user_port0_cmd_addr[23:0]} top.core_dram_tb.dram.user_port0_cmd_addr[23] top.core_dram_tb.dram.user_port0_cmd_addr[22] top.core_dram_tb.dram.user_port0_cmd_addr[21] top.core_dram_tb.dram.user_port0_cmd_addr[20] top.core_dram_tb.dram.user_port0_cmd_addr[19] top.core_dram_tb.dram.user_port0_cmd_addr[18] top.core_dram_tb.dram.user_port0_cmd_addr[17] top.core_dram_tb.dram.user_port0_cmd_addr[16] top.core_dram_tb.dram.user_port0_cmd_addr[15] top.core_dram_tb.dram.user_port0_cmd_addr[14] top.core_dram_tb.dram.user_port0_cmd_addr[13] top.core_dram_tb.dram.user_port0_cmd_addr[12] top.core_dram_tb.dram.user_port0_cmd_addr[11] top.core_dram_tb.dram.user_port0_cmd_addr[10] top.core_dram_tb.dram.user_port0_cmd_addr[9] top.core_dram_tb.dram.user_port0_cmd_addr[8] top.core_dram_tb.dram.user_port0_cmd_addr[7] top.core_dram_tb.dram.user_port0_cmd_addr[6] top.core_dram_tb.dram.user_port0_cmd_addr[5] top.core_dram_tb.dram.user_port0_cmd_addr[4] top.core_dram_tb.dram.user_port0_cmd_addr[3] top.core_dram_tb.dram.user_port0_cmd_addr[2] top.core_dram_tb.dram.user_port0_cmd_addr[1] top.core_dram_tb.dram.user_port0_cmd_addr[0] +@200 +- +-storeq +@28 +top.core_dram_tb.dram.accept_store +top.core_dram_tb.dram.storeq_wr_valid +top.core_dram_tb.dram.storeq_wr_ready +@22 +#{top.core_dram_tb.dram.storeq_wr_data[79:0]} top.core_dram_tb.dram.storeq_wr_data[79] top.core_dram_tb.dram.storeq_wr_data[78] top.core_dram_tb.dram.storeq_wr_data[77] top.core_dram_tb.dram.storeq_wr_data[76] top.core_dram_tb.dram.storeq_wr_data[75] top.core_dram_tb.dram.storeq_wr_data[74] top.core_dram_tb.dram.storeq_wr_data[73] top.core_dram_tb.dram.storeq_wr_data[72] top.core_dram_tb.dram.storeq_wr_data[71] top.core_dram_tb.dram.storeq_wr_data[70] top.core_dram_tb.dram.storeq_wr_data[69] top.core_dram_tb.dram.storeq_wr_data[68] top.core_dram_tb.dram.storeq_wr_data[67] top.core_dram_tb.dram.storeq_wr_data[66] top.core_dram_tb.dram.storeq_wr_data[65] top.core_dram_tb.dram.storeq_wr_data[64] top.core_dram_tb.dram.storeq_wr_data[63] top.core_dram_tb.dram.storeq_wr_data[62] top.core_dram_tb.dram.storeq_wr_data[61] top.core_dram_tb.dram.storeq_wr_data[60] top.core_dram_tb.dram.storeq_wr_data[59] top.core_dram_tb.dram.storeq_wr_data[58] top.core_dram_tb.dram.storeq_wr_data[57] top.core_dram_tb.dram.storeq_wr_data[56] top.core_dram_tb.dram.storeq_wr_data[55] top.core_dram_tb.dram.storeq_wr_data[54] top.core_dram_tb.dram.storeq_wr_data[53] top.core_dram_tb.dram.storeq_wr_data[52] top.core_dram_tb.dram.storeq_wr_data[51] top.core_dram_tb.dram.storeq_wr_data[50] top.core_dram_tb.dram.storeq_wr_data[49] top.core_dram_tb.dram.storeq_wr_data[48] top.core_dram_tb.dram.storeq_wr_data[47] top.core_dram_tb.dram.storeq_wr_data[46] top.core_dram_tb.dram.storeq_wr_data[45] top.core_dram_tb.dram.storeq_wr_data[44] top.core_dram_tb.dram.storeq_wr_data[43] top.core_dram_tb.dram.storeq_wr_data[42] top.core_dram_tb.dram.storeq_wr_data[41] top.core_dram_tb.dram.storeq_wr_data[40] top.core_dram_tb.dram.storeq_wr_data[39] top.core_dram_tb.dram.storeq_wr_data[38] top.core_dram_tb.dram.storeq_wr_data[37] top.core_dram_tb.dram.storeq_wr_data[36] top.core_dram_tb.dram.storeq_wr_data[35] top.core_dram_tb.dram.storeq_wr_data[34] top.core_dram_tb.dram.storeq_wr_data[33] top.core_dram_tb.dram.storeq_wr_data[32] top.core_dram_tb.dram.storeq_wr_data[31] top.core_dram_tb.dram.storeq_wr_data[30] top.core_dram_tb.dram.storeq_wr_data[29] top.core_dram_tb.dram.storeq_wr_data[28] top.core_dram_tb.dram.storeq_wr_data[27] top.core_dram_tb.dram.storeq_wr_data[26] top.core_dram_tb.dram.storeq_wr_data[25] top.core_dram_tb.dram.storeq_wr_data[24] top.core_dram_tb.dram.storeq_wr_data[23] top.core_dram_tb.dram.storeq_wr_data[22] top.core_dram_tb.dram.storeq_wr_data[21] top.core_dram_tb.dram.storeq_wr_data[20] top.core_dram_tb.dram.storeq_wr_data[19] top.core_dram_tb.dram.storeq_wr_data[18] top.core_dram_tb.dram.storeq_wr_data[17] top.core_dram_tb.dram.storeq_wr_data[16] top.core_dram_tb.dram.storeq_wr_data[15] top.core_dram_tb.dram.storeq_wr_data[14] top.core_dram_tb.dram.storeq_wr_data[13] top.core_dram_tb.dram.storeq_wr_data[12] top.core_dram_tb.dram.storeq_wr_data[11] top.core_dram_tb.dram.storeq_wr_data[10] top.core_dram_tb.dram.storeq_wr_data[9] top.core_dram_tb.dram.storeq_wr_data[8] top.core_dram_tb.dram.storeq_wr_data[7] top.core_dram_tb.dram.storeq_wr_data[6] top.core_dram_tb.dram.storeq_wr_data[5] top.core_dram_tb.dram.storeq_wr_data[4] top.core_dram_tb.dram.storeq_wr_data[3] top.core_dram_tb.dram.storeq_wr_data[2] top.core_dram_tb.dram.storeq_wr_data[1] top.core_dram_tb.dram.storeq_wr_data[0] +@28 +top.core_dram_tb.dram.storeq_rd_valid +top.core_dram_tb.dram.storeq_rd_ready +@22 +#{top.core_dram_tb.dram.storeq_rd_data[79:0]} top.core_dram_tb.dram.storeq_rd_data[79] top.core_dram_tb.dram.storeq_rd_data[78] top.core_dram_tb.dram.storeq_rd_data[77] top.core_dram_tb.dram.storeq_rd_data[76] top.core_dram_tb.dram.storeq_rd_data[75] top.core_dram_tb.dram.storeq_rd_data[74] top.core_dram_tb.dram.storeq_rd_data[73] top.core_dram_tb.dram.storeq_rd_data[72] top.core_dram_tb.dram.storeq_rd_data[71] top.core_dram_tb.dram.storeq_rd_data[70] top.core_dram_tb.dram.storeq_rd_data[69] top.core_dram_tb.dram.storeq_rd_data[68] top.core_dram_tb.dram.storeq_rd_data[67] top.core_dram_tb.dram.storeq_rd_data[66] top.core_dram_tb.dram.storeq_rd_data[65] top.core_dram_tb.dram.storeq_rd_data[64] top.core_dram_tb.dram.storeq_rd_data[63] top.core_dram_tb.dram.storeq_rd_data[62] top.core_dram_tb.dram.storeq_rd_data[61] top.core_dram_tb.dram.storeq_rd_data[60] top.core_dram_tb.dram.storeq_rd_data[59] top.core_dram_tb.dram.storeq_rd_data[58] top.core_dram_tb.dram.storeq_rd_data[57] top.core_dram_tb.dram.storeq_rd_data[56] top.core_dram_tb.dram.storeq_rd_data[55] top.core_dram_tb.dram.storeq_rd_data[54] top.core_dram_tb.dram.storeq_rd_data[53] top.core_dram_tb.dram.storeq_rd_data[52] top.core_dram_tb.dram.storeq_rd_data[51] top.core_dram_tb.dram.storeq_rd_data[50] top.core_dram_tb.dram.storeq_rd_data[49] top.core_dram_tb.dram.storeq_rd_data[48] top.core_dram_tb.dram.storeq_rd_data[47] top.core_dram_tb.dram.storeq_rd_data[46] top.core_dram_tb.dram.storeq_rd_data[45] top.core_dram_tb.dram.storeq_rd_data[44] top.core_dram_tb.dram.storeq_rd_data[43] top.core_dram_tb.dram.storeq_rd_data[42] top.core_dram_tb.dram.storeq_rd_data[41] top.core_dram_tb.dram.storeq_rd_data[40] top.core_dram_tb.dram.storeq_rd_data[39] top.core_dram_tb.dram.storeq_rd_data[38] top.core_dram_tb.dram.storeq_rd_data[37] top.core_dram_tb.dram.storeq_rd_data[36] top.core_dram_tb.dram.storeq_rd_data[35] top.core_dram_tb.dram.storeq_rd_data[34] top.core_dram_tb.dram.storeq_rd_data[33] top.core_dram_tb.dram.storeq_rd_data[32] top.core_dram_tb.dram.storeq_rd_data[31] top.core_dram_tb.dram.storeq_rd_data[30] top.core_dram_tb.dram.storeq_rd_data[29] top.core_dram_tb.dram.storeq_rd_data[28] top.core_dram_tb.dram.storeq_rd_data[27] top.core_dram_tb.dram.storeq_rd_data[26] top.core_dram_tb.dram.storeq_rd_data[25] top.core_dram_tb.dram.storeq_rd_data[24] top.core_dram_tb.dram.storeq_rd_data[23] top.core_dram_tb.dram.storeq_rd_data[22] top.core_dram_tb.dram.storeq_rd_data[21] top.core_dram_tb.dram.storeq_rd_data[20] top.core_dram_tb.dram.storeq_rd_data[19] top.core_dram_tb.dram.storeq_rd_data[18] top.core_dram_tb.dram.storeq_rd_data[17] top.core_dram_tb.dram.storeq_rd_data[16] top.core_dram_tb.dram.storeq_rd_data[15] top.core_dram_tb.dram.storeq_rd_data[14] top.core_dram_tb.dram.storeq_rd_data[13] top.core_dram_tb.dram.storeq_rd_data[12] top.core_dram_tb.dram.storeq_rd_data[11] top.core_dram_tb.dram.storeq_rd_data[10] top.core_dram_tb.dram.storeq_rd_data[9] top.core_dram_tb.dram.storeq_rd_data[8] top.core_dram_tb.dram.storeq_rd_data[7] top.core_dram_tb.dram.storeq_rd_data[6] top.core_dram_tb.dram.storeq_rd_data[5] top.core_dram_tb.dram.storeq_rd_data[4] top.core_dram_tb.dram.storeq_rd_data[3] top.core_dram_tb.dram.storeq_rd_data[2] top.core_dram_tb.dram.storeq_rd_data[1] top.core_dram_tb.dram.storeq_rd_data[0] +@200 +- +-misc +@420 +top.core_dram_tb.dram.req_op +top.core_dram_tb.dram.state +@200 +- +@201 +-sync_fifo +@28 +top.core_dram_tb.dram.store_queue.empty +top.core_dram_tb.dram.store_queue.full +@420 +top.core_dram_tb.dram.store_queue.op_next +top.core_dram_tb.dram.store_queue.op_prev +@28 +top.core_dram_tb.dram.store_queue.pop +top.core_dram_tb.dram.store_queue.push +@22 +#{top.core_dram_tb.dram.store_queue.rd_data[79:0]} top.core_dram_tb.dram.store_queue.rd_data[79] top.core_dram_tb.dram.store_queue.rd_data[78] top.core_dram_tb.dram.store_queue.rd_data[77] top.core_dram_tb.dram.store_queue.rd_data[76] top.core_dram_tb.dram.store_queue.rd_data[75] top.core_dram_tb.dram.store_queue.rd_data[74] top.core_dram_tb.dram.store_queue.rd_data[73] top.core_dram_tb.dram.store_queue.rd_data[72] top.core_dram_tb.dram.store_queue.rd_data[71] top.core_dram_tb.dram.store_queue.rd_data[70] top.core_dram_tb.dram.store_queue.rd_data[69] top.core_dram_tb.dram.store_queue.rd_data[68] top.core_dram_tb.dram.store_queue.rd_data[67] top.core_dram_tb.dram.store_queue.rd_data[66] top.core_dram_tb.dram.store_queue.rd_data[65] top.core_dram_tb.dram.store_queue.rd_data[64] top.core_dram_tb.dram.store_queue.rd_data[63] top.core_dram_tb.dram.store_queue.rd_data[62] top.core_dram_tb.dram.store_queue.rd_data[61] top.core_dram_tb.dram.store_queue.rd_data[60] top.core_dram_tb.dram.store_queue.rd_data[59] top.core_dram_tb.dram.store_queue.rd_data[58] top.core_dram_tb.dram.store_queue.rd_data[57] top.core_dram_tb.dram.store_queue.rd_data[56] top.core_dram_tb.dram.store_queue.rd_data[55] top.core_dram_tb.dram.store_queue.rd_data[54] top.core_dram_tb.dram.store_queue.rd_data[53] top.core_dram_tb.dram.store_queue.rd_data[52] top.core_dram_tb.dram.store_queue.rd_data[51] top.core_dram_tb.dram.store_queue.rd_data[50] top.core_dram_tb.dram.store_queue.rd_data[49] top.core_dram_tb.dram.store_queue.rd_data[48] top.core_dram_tb.dram.store_queue.rd_data[47] top.core_dram_tb.dram.store_queue.rd_data[46] top.core_dram_tb.dram.store_queue.rd_data[45] top.core_dram_tb.dram.store_queue.rd_data[44] top.core_dram_tb.dram.store_queue.rd_data[43] top.core_dram_tb.dram.store_queue.rd_data[42] top.core_dram_tb.dram.store_queue.rd_data[41] top.core_dram_tb.dram.store_queue.rd_data[40] top.core_dram_tb.dram.store_queue.rd_data[39] top.core_dram_tb.dram.store_queue.rd_data[38] top.core_dram_tb.dram.store_queue.rd_data[37] top.core_dram_tb.dram.store_queue.rd_data[36] top.core_dram_tb.dram.store_queue.rd_data[35] top.core_dram_tb.dram.store_queue.rd_data[34] top.core_dram_tb.dram.store_queue.rd_data[33] top.core_dram_tb.dram.store_queue.rd_data[32] top.core_dram_tb.dram.store_queue.rd_data[31] top.core_dram_tb.dram.store_queue.rd_data[30] top.core_dram_tb.dram.store_queue.rd_data[29] top.core_dram_tb.dram.store_queue.rd_data[28] top.core_dram_tb.dram.store_queue.rd_data[27] top.core_dram_tb.dram.store_queue.rd_data[26] top.core_dram_tb.dram.store_queue.rd_data[25] top.core_dram_tb.dram.store_queue.rd_data[24] top.core_dram_tb.dram.store_queue.rd_data[23] top.core_dram_tb.dram.store_queue.rd_data[22] top.core_dram_tb.dram.store_queue.rd_data[21] top.core_dram_tb.dram.store_queue.rd_data[20] top.core_dram_tb.dram.store_queue.rd_data[19] top.core_dram_tb.dram.store_queue.rd_data[18] top.core_dram_tb.dram.store_queue.rd_data[17] top.core_dram_tb.dram.store_queue.rd_data[16] top.core_dram_tb.dram.store_queue.rd_data[15] top.core_dram_tb.dram.store_queue.rd_data[14] top.core_dram_tb.dram.store_queue.rd_data[13] top.core_dram_tb.dram.store_queue.rd_data[12] top.core_dram_tb.dram.store_queue.rd_data[11] top.core_dram_tb.dram.store_queue.rd_data[10] top.core_dram_tb.dram.store_queue.rd_data[9] top.core_dram_tb.dram.store_queue.rd_data[8] top.core_dram_tb.dram.store_queue.rd_data[7] top.core_dram_tb.dram.store_queue.rd_data[6] top.core_dram_tb.dram.store_queue.rd_data[5] top.core_dram_tb.dram.store_queue.rd_data[4] top.core_dram_tb.dram.store_queue.rd_data[3] top.core_dram_tb.dram.store_queue.rd_data[2] top.core_dram_tb.dram.store_queue.rd_data[1] top.core_dram_tb.dram.store_queue.rd_data[0] +@420 +top.core_dram_tb.dram.store_queue.rd_idx +top.core_dram_tb.dram.store_queue.rd_next +@28 +top.core_dram_tb.dram.store_queue.rd_ready +top.core_dram_tb.dram.store_queue.rd_valid +@22 +#{top.core_dram_tb.dram.store_queue.wr_data[79:0]} top.core_dram_tb.dram.store_queue.wr_data[79] top.core_dram_tb.dram.store_queue.wr_data[78] top.core_dram_tb.dram.store_queue.wr_data[77] top.core_dram_tb.dram.store_queue.wr_data[76] top.core_dram_tb.dram.store_queue.wr_data[75] top.core_dram_tb.dram.store_queue.wr_data[74] top.core_dram_tb.dram.store_queue.wr_data[73] top.core_dram_tb.dram.store_queue.wr_data[72] top.core_dram_tb.dram.store_queue.wr_data[71] top.core_dram_tb.dram.store_queue.wr_data[70] top.core_dram_tb.dram.store_queue.wr_data[69] top.core_dram_tb.dram.store_queue.wr_data[68] top.core_dram_tb.dram.store_queue.wr_data[67] top.core_dram_tb.dram.store_queue.wr_data[66] top.core_dram_tb.dram.store_queue.wr_data[65] top.core_dram_tb.dram.store_queue.wr_data[64] top.core_dram_tb.dram.store_queue.wr_data[63] top.core_dram_tb.dram.store_queue.wr_data[62] top.core_dram_tb.dram.store_queue.wr_data[61] top.core_dram_tb.dram.store_queue.wr_data[60] top.core_dram_tb.dram.store_queue.wr_data[59] top.core_dram_tb.dram.store_queue.wr_data[58] top.core_dram_tb.dram.store_queue.wr_data[57] top.core_dram_tb.dram.store_queue.wr_data[56] top.core_dram_tb.dram.store_queue.wr_data[55] top.core_dram_tb.dram.store_queue.wr_data[54] top.core_dram_tb.dram.store_queue.wr_data[53] top.core_dram_tb.dram.store_queue.wr_data[52] top.core_dram_tb.dram.store_queue.wr_data[51] top.core_dram_tb.dram.store_queue.wr_data[50] top.core_dram_tb.dram.store_queue.wr_data[49] top.core_dram_tb.dram.store_queue.wr_data[48] top.core_dram_tb.dram.store_queue.wr_data[47] top.core_dram_tb.dram.store_queue.wr_data[46] top.core_dram_tb.dram.store_queue.wr_data[45] top.core_dram_tb.dram.store_queue.wr_data[44] top.core_dram_tb.dram.store_queue.wr_data[43] top.core_dram_tb.dram.store_queue.wr_data[42] top.core_dram_tb.dram.store_queue.wr_data[41] top.core_dram_tb.dram.store_queue.wr_data[40] top.core_dram_tb.dram.store_queue.wr_data[39] top.core_dram_tb.dram.store_queue.wr_data[38] top.core_dram_tb.dram.store_queue.wr_data[37] top.core_dram_tb.dram.store_queue.wr_data[36] top.core_dram_tb.dram.store_queue.wr_data[35] top.core_dram_tb.dram.store_queue.wr_data[34] top.core_dram_tb.dram.store_queue.wr_data[33] top.core_dram_tb.dram.store_queue.wr_data[32] top.core_dram_tb.dram.store_queue.wr_data[31] top.core_dram_tb.dram.store_queue.wr_data[30] top.core_dram_tb.dram.store_queue.wr_data[29] top.core_dram_tb.dram.store_queue.wr_data[28] top.core_dram_tb.dram.store_queue.wr_data[27] top.core_dram_tb.dram.store_queue.wr_data[26] top.core_dram_tb.dram.store_queue.wr_data[25] top.core_dram_tb.dram.store_queue.wr_data[24] top.core_dram_tb.dram.store_queue.wr_data[23] top.core_dram_tb.dram.store_queue.wr_data[22] top.core_dram_tb.dram.store_queue.wr_data[21] top.core_dram_tb.dram.store_queue.wr_data[20] top.core_dram_tb.dram.store_queue.wr_data[19] top.core_dram_tb.dram.store_queue.wr_data[18] top.core_dram_tb.dram.store_queue.wr_data[17] top.core_dram_tb.dram.store_queue.wr_data[16] top.core_dram_tb.dram.store_queue.wr_data[15] top.core_dram_tb.dram.store_queue.wr_data[14] top.core_dram_tb.dram.store_queue.wr_data[13] top.core_dram_tb.dram.store_queue.wr_data[12] top.core_dram_tb.dram.store_queue.wr_data[11] top.core_dram_tb.dram.store_queue.wr_data[10] top.core_dram_tb.dram.store_queue.wr_data[9] top.core_dram_tb.dram.store_queue.wr_data[8] top.core_dram_tb.dram.store_queue.wr_data[7] top.core_dram_tb.dram.store_queue.wr_data[6] top.core_dram_tb.dram.store_queue.wr_data[5] top.core_dram_tb.dram.store_queue.wr_data[4] top.core_dram_tb.dram.store_queue.wr_data[3] top.core_dram_tb.dram.store_queue.wr_data[2] top.core_dram_tb.dram.store_queue.wr_data[1] top.core_dram_tb.dram.store_queue.wr_data[0] +@420 +top.core_dram_tb.dram.store_queue.wr_idx +top.core_dram_tb.dram.store_queue.wr_next +@28 +top.core_dram_tb.dram.store_queue.wr_ready +top.core_dram_tb.dram.store_queue.wr_valid +[pattern_trace] 1 +[pattern_trace] 0 diff --git a/litedram/extras/wave.opt b/litedram/extras/wave.opt new file mode 100644 index 0000000..f147269 --- /dev/null +++ b/litedram/extras/wave.opt @@ -0,0 +1,84 @@ +$ version 1.1 + +# Signals in entities : +/core_dram_tb/dram/rst +/core_dram_tb/dram/system_clk +/core_dram_tb/dram/system_reset +/core_dram_tb/dram/wb_in +/core_dram_tb/dram/wb_out +/core_dram_tb/dram/user_port0_cmd_valid +/core_dram_tb/dram/user_port0_cmd_ready +/core_dram_tb/dram/user_port0_cmd_we +/core_dram_tb/dram/user_port0_cmd_addr +/core_dram_tb/dram/user_port0_wdata_valid +/core_dram_tb/dram/user_port0_wdata_ready +/core_dram_tb/dram/user_port0_wdata_we +/core_dram_tb/dram/user_port0_wdata_data +/core_dram_tb/dram/user_port0_rdata_valid +/core_dram_tb/dram/user_port0_rdata_ready +/core_dram_tb/dram/user_port0_rdata_data +/core_dram_tb/dram/cache_tags +/core_dram_tb/dram/cache_valids +/core_dram_tb/dram/storeq_rd_ready +/core_dram_tb/dram/storeq_rd_valid +/core_dram_tb/dram/storeq_rd_data +/core_dram_tb/dram/storeq_wr_ready +/core_dram_tb/dram/storeq_wr_valid +/core_dram_tb/dram/storeq_wr_data +/core_dram_tb/dram/accept_store +/core_dram_tb/dram/state +/core_dram_tb/dram/wb_req +/core_dram_tb/dram/store_queued +/core_dram_tb/dram/read_ack_0 +/core_dram_tb/dram/read_ack_1 +/core_dram_tb/dram/read_ad3_0 +/core_dram_tb/dram/read_ad3_1 +/core_dram_tb/dram/read_way_0 +/core_dram_tb/dram/read_way_1 +/core_dram_tb/dram/req_index +/core_dram_tb/dram/req_row +/core_dram_tb/dram/req_hit_way +/core_dram_tb/dram/req_tag +/core_dram_tb/dram/req_op +/core_dram_tb/dram/req_laddr +/core_dram_tb/dram/req_ad3 +/core_dram_tb/dram/req_we +/core_dram_tb/dram/req_wdata +/core_dram_tb/dram/store_way +/core_dram_tb/dram/store_index +/core_dram_tb/dram/store_row +/core_dram_tb/dram/cache_out +/core_dram_tb/dram/plru_victim +/core_dram_tb/dram/replace_way +/core_dram_tb/dram/rams/do_read +/core_dram_tb/dram/rams/do_write +/core_dram_tb/dram/rams/rd_addr +/core_dram_tb/dram/rams/wr_addr +/core_dram_tb/dram/rams/wr_data +/core_dram_tb/dram/rams/wr_sel +/core_dram_tb/dram/rams/wr_sel_m +/core_dram_tb/dram/rams/dout +/core_dram_tb/dram/rams/way/clk +/core_dram_tb/dram/rams/way/rd_en +/core_dram_tb/dram/rams/way/rd_addr +/core_dram_tb/dram/rams/way/rd_data +/core_dram_tb/dram/rams/way/wr_sel +/core_dram_tb/dram/rams/way/wr_addr +/core_dram_tb/dram/rams/way/wr_data +/core_dram_tb/dram/rams/way/rd_data0 +/core_dram_tb/dram/store_queue/wr_ready +/core_dram_tb/dram/store_queue/wr_valid +/core_dram_tb/dram/store_queue/wr_data +/core_dram_tb/dram/store_queue/rd_ready +/core_dram_tb/dram/store_queue/rd_valid +/core_dram_tb/dram/store_queue/rd_data +/core_dram_tb/dram/store_queue/rd_idx +/core_dram_tb/dram/store_queue/rd_next +/core_dram_tb/dram/store_queue/wr_idx +/core_dram_tb/dram/store_queue/wr_next +/core_dram_tb/dram/store_queue/op_prev +/core_dram_tb/dram/store_queue/op_next +/core_dram_tb/dram/store_queue/full +/core_dram_tb/dram/store_queue/empty +/core_dram_tb/dram/store_queue/push +/core_dram_tb/dram/store_queue/pop diff --git a/litedram/extras/wrapper-mw-init.vhdl b/litedram/extras/wrapper-mw-init.vhdl index 47f0a6f..6bd3636 100644 --- a/litedram/extras/wrapper-mw-init.vhdl +++ b/litedram/extras/wrapper-mw-init.vhdl @@ -5,131 +5,147 @@ use std.textio.all; library work; use work.wishbone_types.all; +use work.utils.all; +use work.helpers.all; entity litedram_wrapper is generic ( DRAM_ABITS : positive; DRAM_ALINES : positive; + -- Pseudo-ROM payload PAYLOAD_SIZE : natural; PAYLOAD_FILE : string; + + -- L2 cache -- + + -- Line size in bytes + LINE_SIZE : positive := 128; + -- Number of lines in a set + NUM_LINES : positive := 32; + -- Number of ways + NUM_WAYS : positive := 4; + -- Max number of stores in the queue + STOREQ_DEPTH : positive := 8; + -- Don't send loads until all pending stores acked in litedram + NO_LS_OVERLAP : boolean := false; + -- Debug - LITEDRAM_TRACE : boolean := false - ); + LITEDRAM_TRACE : boolean := false; + TRACE : boolean := false + ); port( - -- LiteDRAM generates the system clock and reset - -- from the input clkin - clk_in : in std_ulogic; - rst : in std_ulogic; - system_clk : out std_ulogic; - system_reset : out std_ulogic; - core_alt_reset : out std_ulogic; - pll_locked : out std_ulogic; - - -- Wishbone ports: - wb_in : in wishbone_master_out; - wb_out : out wishbone_slave_out; - wb_ctrl_in : in wb_io_master_out; - wb_ctrl_out : out wb_io_slave_out; - wb_ctrl_is_csr : in std_ulogic; - wb_ctrl_is_init : in std_ulogic; - - -- Init core serial debug - serial_tx : out std_ulogic; - serial_rx : in std_ulogic; - - -- Misc - init_done : out std_ulogic; - init_error : out std_ulogic; - - -- DRAM wires - ddram_a : out std_ulogic_vector(DRAM_ALINES-1 downto 0); - ddram_ba : out std_ulogic_vector(2 downto 0); - ddram_ras_n : out std_ulogic; - ddram_cas_n : out std_ulogic; - ddram_we_n : out std_ulogic; - ddram_cs_n : out std_ulogic; - ddram_dm : out std_ulogic_vector(1 downto 0); - ddram_dq : inout std_ulogic_vector(15 downto 0); - ddram_dqs_p : inout std_ulogic_vector(1 downto 0); - ddram_dqs_n : inout std_ulogic_vector(1 downto 0); - ddram_clk_p : out std_ulogic; - ddram_clk_n : out std_ulogic; - ddram_cke : out std_ulogic; - ddram_odt : out std_ulogic; - ddram_reset_n : out std_ulogic - ); + -- LiteDRAM generates the system clock and reset + -- from the input clkin + clk_in : in std_ulogic; + rst : in std_ulogic; + system_clk : out std_ulogic; + system_reset : out std_ulogic; + core_alt_reset : out std_ulogic; + pll_locked : out std_ulogic; + + -- Wishbone ports: + wb_in : in wishbone_master_out; + wb_out : out wishbone_slave_out; + wb_ctrl_in : in wb_io_master_out; + wb_ctrl_out : out wb_io_slave_out; + wb_ctrl_is_csr : in std_ulogic; + wb_ctrl_is_init : in std_ulogic; + + -- Init core serial debug + serial_tx : out std_ulogic; + serial_rx : in std_ulogic; + + -- Misc + init_done : out std_ulogic; + init_error : out std_ulogic; + + -- DRAM wires + ddram_a : out std_ulogic_vector(DRAM_ALINES-1 downto 0); + ddram_ba : out std_ulogic_vector(2 downto 0); + ddram_ras_n : out std_ulogic; + ddram_cas_n : out std_ulogic; + ddram_we_n : out std_ulogic; + ddram_cs_n : out std_ulogic; + ddram_dm : out std_ulogic_vector(1 downto 0); + ddram_dq : inout std_ulogic_vector(15 downto 0); + ddram_dqs_p : inout std_ulogic_vector(1 downto 0); + ddram_dqs_n : inout std_ulogic_vector(1 downto 0); + ddram_clk_p : out std_ulogic; + ddram_clk_n : out std_ulogic; + ddram_cke : out std_ulogic; + ddram_odt : out std_ulogic; + ddram_reset_n : out std_ulogic + ); end entity litedram_wrapper; architecture behaviour of litedram_wrapper is component litedram_core port ( - clk : in std_ulogic; - rst : in std_ulogic; - pll_locked : out std_ulogic; - ddram_a : out std_ulogic_vector(DRAM_ALINES-1 downto 0); - ddram_ba : out std_ulogic_vector(2 downto 0); - ddram_ras_n : out std_ulogic; - ddram_cas_n : out std_ulogic; - ddram_we_n : out std_ulogic; - ddram_cs_n : out std_ulogic; - ddram_dm : out std_ulogic_vector(1 downto 0); - ddram_dq : inout std_ulogic_vector(15 downto 0); - ddram_dqs_p : inout std_ulogic_vector(1 downto 0); - ddram_dqs_n : inout std_ulogic_vector(1 downto 0); - ddram_clk_p : out std_ulogic; - ddram_clk_n : out std_ulogic; - ddram_cke : out std_ulogic; - ddram_odt : out std_ulogic; - ddram_reset_n : out std_ulogic; - init_done : out std_ulogic; - init_error : out std_ulogic; - user_clk : out std_ulogic; - user_rst : out std_ulogic; - wb_ctrl_adr : in std_ulogic_vector(29 downto 0); - wb_ctrl_dat_w : in std_ulogic_vector(31 downto 0); - wb_ctrl_dat_r : out std_ulogic_vector(31 downto 0); - wb_ctrl_sel : in std_ulogic_vector(3 downto 0); - wb_ctrl_cyc : in std_ulogic; - wb_ctrl_stb : in std_ulogic; - wb_ctrl_ack : out std_ulogic; - wb_ctrl_we : in std_ulogic; - wb_ctrl_cti : in std_ulogic_vector(2 downto 0); - wb_ctrl_bte : in std_ulogic_vector(1 downto 0); - wb_ctrl_err : out std_ulogic; - user_port_native_0_cmd_valid : in std_ulogic; - user_port_native_0_cmd_ready : out std_ulogic; - user_port_native_0_cmd_we : in std_ulogic; - user_port_native_0_cmd_addr : in std_ulogic_vector(DRAM_ABITS-1 downto 0); - user_port_native_0_wdata_valid : in std_ulogic; - user_port_native_0_wdata_ready : out std_ulogic; - user_port_native_0_wdata_we : in std_ulogic_vector(15 downto 0); - user_port_native_0_wdata_data : in std_ulogic_vector(127 downto 0); - user_port_native_0_rdata_valid : out std_ulogic; - user_port_native_0_rdata_ready : in std_ulogic; - user_port_native_0_rdata_data : out std_ulogic_vector(127 downto 0) - ); + clk : in std_ulogic; + rst : in std_ulogic; + pll_locked : out std_ulogic; + ddram_a : out std_ulogic_vector(DRAM_ALINES-1 downto 0); + ddram_ba : out std_ulogic_vector(2 downto 0); + ddram_ras_n : out std_ulogic; + ddram_cas_n : out std_ulogic; + ddram_we_n : out std_ulogic; + ddram_cs_n : out std_ulogic; + ddram_dm : out std_ulogic_vector(1 downto 0); + ddram_dq : inout std_ulogic_vector(15 downto 0); + ddram_dqs_p : inout std_ulogic_vector(1 downto 0); + ddram_dqs_n : inout std_ulogic_vector(1 downto 0); + ddram_clk_p : out std_ulogic; + ddram_clk_n : out std_ulogic; + ddram_cke : out std_ulogic; + ddram_odt : out std_ulogic; + ddram_reset_n : out std_ulogic; + init_done : out std_ulogic; + init_error : out std_ulogic; + user_clk : out std_ulogic; + user_rst : out std_ulogic; + wb_ctrl_adr : in std_ulogic_vector(29 downto 0); + wb_ctrl_dat_w : in std_ulogic_vector(31 downto 0); + wb_ctrl_dat_r : out std_ulogic_vector(31 downto 0); + wb_ctrl_sel : in std_ulogic_vector(3 downto 0); + wb_ctrl_cyc : in std_ulogic; + wb_ctrl_stb : in std_ulogic; + wb_ctrl_ack : out std_ulogic; + wb_ctrl_we : in std_ulogic; + wb_ctrl_cti : in std_ulogic_vector(2 downto 0); + wb_ctrl_bte : in std_ulogic_vector(1 downto 0); + wb_ctrl_err : out std_ulogic; + user_port_native_0_cmd_valid : in std_ulogic; + user_port_native_0_cmd_ready : out std_ulogic; + user_port_native_0_cmd_we : in std_ulogic; + user_port_native_0_cmd_addr : in std_ulogic_vector(DRAM_ABITS-1 downto 0); + user_port_native_0_wdata_valid : in std_ulogic; + user_port_native_0_wdata_ready : out std_ulogic; + user_port_native_0_wdata_we : in std_ulogic_vector(15 downto 0); + user_port_native_0_wdata_data : in std_ulogic_vector(127 downto 0); + user_port_native_0_rdata_valid : out std_ulogic; + user_port_native_0_rdata_ready : in std_ulogic; + user_port_native_0_rdata_data : out std_ulogic_vector(127 downto 0) + ); end component; - signal user_port0_cmd_valid : std_ulogic; - signal user_port0_cmd_ready : std_ulogic; - signal user_port0_cmd_we : std_ulogic; - signal user_port0_cmd_addr : std_ulogic_vector(DRAM_ABITS-1 downto 0); - signal user_port0_wdata_valid : std_ulogic; - signal user_port0_wdata_ready : std_ulogic; - signal user_port0_wdata_we : std_ulogic_vector(15 downto 0); - signal user_port0_wdata_data : std_ulogic_vector(127 downto 0); - signal user_port0_rdata_valid : std_ulogic; - signal user_port0_rdata_ready : std_ulogic; - signal user_port0_rdata_data : std_ulogic_vector(127 downto 0); - - signal ad3 : std_ulogic; + signal user_port0_cmd_valid : std_ulogic; + signal user_port0_cmd_ready : std_ulogic; + signal user_port0_cmd_we : std_ulogic; + signal user_port0_cmd_addr : std_ulogic_vector(DRAM_ABITS-1 downto 0); + signal user_port0_wdata_valid : std_ulogic; + signal user_port0_wdata_ready : std_ulogic; + signal user_port0_wdata_we : std_ulogic_vector(15 downto 0); + signal user_port0_wdata_data : std_ulogic_vector(127 downto 0); + signal user_port0_rdata_valid : std_ulogic; + signal user_port0_rdata_ready : std_ulogic; + signal user_port0_rdata_data : std_ulogic_vector(127 downto 0); signal wb_ctrl_adr : std_ulogic_vector(29 downto 0); signal wb_ctrl_dat_w : std_ulogic_vector(31 downto 0); signal wb_ctrl_dat_r : std_ulogic_vector(31 downto 0); signal wb_ctrl_sel : std_ulogic_vector(3 downto 0); - signal wb_ctrl_cyc : std_ulogic; + signal wb_ctrl_cyc : std_ulogic := '0'; signal wb_ctrl_stb : std_ulogic; signal wb_ctrl_ack : std_ulogic; signal wb_ctrl_we : std_ulogic; @@ -137,11 +153,239 @@ architecture behaviour of litedram_wrapper is signal wb_init_in : wb_io_master_out; signal wb_init_out : wb_io_slave_out; - type state_t is (CMD, MWRITE, MREAD); + -- DRAM data port width + constant DRAM_DBITS : natural := 128; + constant DRAM_SBITS : natural := (DRAM_DBITS / 8); + + -- BRAM organisation: We never access more than wishbone_data_bits at + -- a time so to save resources we make the array only that wide, and + -- use consecutive indices for to make a cache "line" + -- + -- ROW_SIZE is the width in bytes of the BRAM (based on litedram, so 128-bits) + constant ROW_SIZE : natural := DRAM_DBITS / 8; + -- ROW_PER_LINE is the number of row (litedram transactions) in a line + constant ROW_PER_LINE : natural := LINE_SIZE / ROW_SIZE; + -- BRAM_ROWS is the number of rows in BRAM needed to represent the full + -- dcache + constant BRAM_ROWS : natural := NUM_LINES * ROW_PER_LINE; + + -- Bit fields counts in the address + + -- ROW_BITS is the number of bits to select a row + constant ROW_BITS : natural := log2(BRAM_ROWS); + -- ROW_LINEBITS is the number of bits to select a row within a line + constant ROW_LINEBITS : natural := log2(ROW_PER_LINE); + -- LINE_OFF_BITS is the number of bits for the offset in a cache line + constant LINE_OFF_BITS : natural := log2(LINE_SIZE); + -- ROW_OFF_BITS is the number of bits for the offset in a row + constant ROW_OFF_BITS : natural := log2(ROW_SIZE); + -- REAL_ADDR_BITS is the number of real address bits that we store + constant REAL_ADDR_BITS : positive := DRAM_ABITS + ROW_OFF_BITS; + -- INDEX_BITS is the number if bits to select a cache line + constant INDEX_BITS : natural := log2(NUM_LINES); + -- SET_SIZE_BITS is the log base 2 of the set size + constant SET_SIZE_BITS : natural := LINE_OFF_BITS + INDEX_BITS; + -- TAG_BITS is the number of bits of the tag part of the address + constant TAG_BITS : natural := REAL_ADDR_BITS - SET_SIZE_BITS; + -- WAY_BITS is the number of bits to select a way + constant WAY_BITS : natural := log2(NUM_WAYS); + + subtype row_t is integer range 0 to BRAM_ROWS-1; + subtype index_t is integer range 0 to NUM_LINES-1; + subtype way_t is integer range 0 to NUM_WAYS-1; + + -- The cache data BRAM organized as described above for each way + subtype cache_row_t is std_ulogic_vector(DRAM_DBITS-1 downto 0); + + -- The cache tags LUTRAM has a row per set. Vivado is a pain and will + -- not handle a clean (commented) definition of the cache tags as a 3d + -- memory. For now, work around it by putting all the tags + subtype cache_tag_t is std_logic_vector(TAG_BITS-1 downto 0); +-- type cache_tags_set_t is array(way_t) of cache_tag_t; +-- type cache_tags_array_t is array(index_t) of cache_tags_set_t; + constant TAG_RAM_WIDTH : natural := TAG_BITS * NUM_WAYS; + subtype cache_tags_set_t is std_logic_vector(TAG_RAM_WIDTH-1 downto 0); + type cache_tags_array_t is array(index_t) of cache_tags_set_t; + + -- The cache valid bits + subtype cache_way_valids_t is std_ulogic_vector(NUM_WAYS-1 downto 0); + type cache_valids_t is array(index_t) of cache_way_valids_t; + + -- Storage. Hopefully "cache_rows" is a BRAM, the rest is LUTs + signal cache_tags : cache_tags_array_t; + signal cache_valids : cache_valids_t; + + attribute ram_style : string; + attribute ram_style of cache_tags : signal is "distributed"; + + -- + -- Store queue signals + -- + -- We store a single wishbone dword per entry (64-bit) but all + -- 16 sel bits for the DRAM. + -- XXX Investigate storing only AD3 and 8 sel bits if it's better + constant STOREQ_BITS : positive := wishbone_data_bits + DRAM_SBITS; + + signal storeq_rd_ready : std_ulogic; + signal storeq_rd_valid : std_ulogic; + signal storeq_rd_data : std_ulogic_vector(STOREQ_BITS-1 downto 0); + signal storeq_wr_ready : std_ulogic; + signal storeq_wr_valid : std_ulogic; + signal storeq_wr_data : std_ulogic_vector(STOREQ_BITS-1 downto 0); + + -- + -- Cache management signals + -- + + -- Cache state machine + type state_t is (IDLE, -- Normal load hit processing + REFILL_WAIT_ACK); -- Cache refill wait ack signal state : state_t; + -- Latched WB request. + signal wb_req : wishbone_master_out := wishbone_master_out_init; + + -- Read pipeline (to handle cache RAM latency) + signal read_ack_0 : std_ulogic; + signal read_ack_1 : std_ulogic; + signal read_ad3_0 : std_ulogic; + signal read_ad3_1 : std_ulogic; + signal read_way_0 : way_t; + signal read_way_1 : way_t; + + -- Async signals decoding latched request + type req_op_t is (OP_NONE, + OP_LOAD_HIT, + OP_LOAD_MISS, + OP_STORE_HIT, + OP_STORE_MISS); + + signal req_index : index_t; + signal req_row : row_t; + signal req_hit_way : way_t; + signal req_tag : cache_tag_t; + signal req_op : req_op_t; + signal req_laddr : std_ulogic_vector(REAL_ADDR_BITS-1 downto 0); + signal req_ad3 : std_ulogic; + signal req_we : std_ulogic_vector(DRAM_SBITS-1 downto 0); + signal req_wdata : std_ulogic_vector(DRAM_DBITS-1 downto 0); + signal accept_store : std_ulogic; + + -- Line refill command signals and latches + signal refill_cmd_valid : std_ulogic; + signal refill_cmd_addr : std_ulogic_vector(DRAM_ABITS-1 downto 0); + signal refill_way : way_t; + signal refill_index : index_t; + signal refill_row : row_t; + + -- Cache RAM interface + type cache_ram_out_t is array(way_t) of cache_row_t; + signal cache_out : cache_ram_out_t; + + -- PLRU output interface + type plru_out_t is array(index_t) of std_ulogic_vector(WAY_BITS-1 downto 0); + signal plru_victim : plru_out_t; + + -- + -- Helper functions to decode incoming requests + -- + + -- Return the cache line index (tag index) for an address + function get_index(addr: wishbone_addr_type) return index_t is + begin + return to_integer(unsigned(addr(SET_SIZE_BITS - 1 downto LINE_OFF_BITS))); + end; + + -- Return the cache row index (data memory) for an address + function get_row(addr: std_ulogic_vector(REAL_ADDR_BITS-1 downto 0)) return row_t is + begin + return to_integer(unsigned(addr(SET_SIZE_BITS - 1 downto ROW_OFF_BITS))); + end; + + -- Returns whether this is the last row of a line. It takes a DRAM address + function is_last_row_addr(addr: std_ulogic_vector(REAL_ADDR_BITS-1 downto ROW_OFF_BITS)) + return boolean is + constant ones : std_ulogic_vector(ROW_LINEBITS-1 downto 0) := (others => '1'); + begin + return addr(LINE_OFF_BITS-1 downto ROW_OFF_BITS) = ones; + end; + + -- Returns whether this is the last row of a line + function is_last_row(row: row_t) return boolean is + variable row_v : std_ulogic_vector(ROW_BITS-1 downto 0); + constant ones : std_ulogic_vector(ROW_LINEBITS-1 downto 0) := (others => '1'); + begin + row_v := std_ulogic_vector(to_unsigned(row, ROW_BITS)); + return row_v(ROW_LINEBITS-1 downto 0) = ones; + end; + + -- Return the address of the next row in the current cache line. It takes a + -- DRAM address + function next_row_addr(addr: std_ulogic_vector(REAL_ADDR_BITS-1 downto ROW_OFF_BITS)) + return std_ulogic_vector is + variable row_idx : std_ulogic_vector(ROW_LINEBITS-1 downto 0); + variable result : std_ulogic_vector(REAL_ADDR_BITS-1 downto ROW_OFF_BITS); + begin + -- Is there no simpler way in VHDL to generate that 3 bits adder ? + row_idx := addr(LINE_OFF_BITS-1 downto ROW_OFF_BITS); + row_idx := std_ulogic_vector(unsigned(row_idx) + 1); + result := addr; + result(LINE_OFF_BITS-1 downto ROW_OFF_BITS) := row_idx; + return result; + end; + + -- Return the next row in the current cache line. We use a dedicated + -- function in order to limit the size of the generated adder to be + -- only the bits within a cache line (3 bits with default settings) + -- + function next_row(row: row_t) return row_t is + variable row_v : std_ulogic_vector(ROW_BITS-1 downto 0); + variable row_idx : std_ulogic_vector(ROW_LINEBITS-1 downto 0); + variable result : std_ulogic_vector(ROW_BITS-1 downto 0); + begin + row_v := std_ulogic_vector(to_unsigned(row, ROW_BITS)); + row_idx := row_v(ROW_LINEBITS-1 downto 0); + row_v(ROW_LINEBITS-1 downto 0) := std_ulogic_vector(unsigned(row_idx) + 1); + return to_integer(unsigned(row_v)); + end; + + -- Get the tag value from the address + function get_tag(addr: wishbone_addr_type) return cache_tag_t is + begin + return addr(REAL_ADDR_BITS - 1 downto SET_SIZE_BITS); + end; + + -- Read a tag from a tag memory row + function read_tag(way: way_t; tagset: cache_tags_set_t) return cache_tag_t is + begin + return tagset((way+1) * TAG_BITS - 1 downto way * TAG_BITS); + end; + + -- Write a tag to tag memory row + procedure write_tag(way: in way_t; tagset: inout cache_tags_set_t; + tag: cache_tag_t) is + begin + tagset((way+1) * TAG_BITS - 1 downto way * TAG_BITS) := tag; + end; + begin + -- Sanity checks + assert LINE_SIZE mod ROW_SIZE = 0 report "LINE_SIZE not multiple of ROW_SIZE" severity FAILURE; + assert ispow2(LINE_SIZE) report "LINE_SIZE not power of 2" severity FAILURE; + assert ispow2(NUM_LINES) report "NUM_LINES not power of 2" severity FAILURE; + assert ispow2(ROW_PER_LINE) report "ROW_PER_LINE not power of 2" severity FAILURE; + assert (ROW_BITS = INDEX_BITS + ROW_LINEBITS) + report "geometry bits don't add up" severity FAILURE; + assert (LINE_OFF_BITS = ROW_OFF_BITS + ROW_LINEBITS) + report "geometry bits don't add up" severity FAILURE; + assert (REAL_ADDR_BITS = TAG_BITS + INDEX_BITS + LINE_OFF_BITS) + report "geometry bits don't add up" severity FAILURE; + assert (REAL_ADDR_BITS = TAG_BITS + ROW_BITS + ROW_OFF_BITS) + report "geometry bits don't add up" severity FAILURE; + assert (128 = DRAM_DBITS) + report "Can't yet handle a DRAM width that isn't 128-bits" severity FAILURE; + -- alternate core reset address set when DRAM is not initialized. core_alt_reset <= not init_done; @@ -170,15 +414,35 @@ begin wb_init_in.stb <= wb_ctrl_in.stb; wb_init_in.cyc <= wb_ctrl_in.cyc and wb_ctrl_is_init; - -- DRAM CSR IN signals - wb_ctrl_adr <= x"0000" & wb_ctrl_in.adr(15 downto 2); - wb_ctrl_dat_w <= wb_ctrl_in.dat; - wb_ctrl_sel <= wb_ctrl_in.sel; - wb_ctrl_we <= wb_ctrl_in.we; - wb_ctrl_cyc <= wb_ctrl_in.cyc and wb_ctrl_is_csr; - wb_ctrl_stb <= wb_ctrl_in.stb and wb_ctrl_is_csr; + -- DRAM CSR IN signals. Extra latch to help with timing + csr_latch: process(system_clk) + begin + if rising_edge(system_clk) then + if system_reset = '1' then + wb_ctrl_cyc <= '0'; + wb_ctrl_stb <= '0'; + else + -- XXX Maybe only update addr when cyc = '1' to save power ? + wb_ctrl_adr <= x"0000" & wb_ctrl_in.adr(15 downto 2); + wb_ctrl_dat_w <= wb_ctrl_in.dat; + wb_ctrl_sel <= wb_ctrl_in.sel; + wb_ctrl_we <= wb_ctrl_in.we; + wb_ctrl_cyc <= wb_ctrl_in.cyc and wb_ctrl_is_csr; + wb_ctrl_stb <= wb_ctrl_in.stb and wb_ctrl_is_csr; + + -- Clear stb on ack otherwise the memory will latch + -- the write twice which breaks levelling. On the next + -- cycle we will latch an updated stb that takes the + -- ack into account. + if wb_ctrl_ack = '1' then + wb_ctrl_stb <= '0'; + end if; + end if; + end if; + end process; - -- Ctrl bus wishbone OUT signals + -- Ctrl bus wishbone OUT signals. XXX Consider adding latch on + -- CSR response to help timing wb_ctrl_out.ack <= wb_ctrl_ack when wb_ctrl_is_csr = '1' else wb_init_out.ack; wb_ctrl_out.dat <= wb_ctrl_dat_r when wb_ctrl_is_csr = '1' @@ -186,60 +450,535 @@ begin wb_ctrl_out.stall <= wb_init_out.stall when wb_ctrl_is_init else '0' when wb_ctrl_in.cyc = '0' else not wb_ctrl_ack; + + -- Generate a cache RAM for each way + rams: for i in 0 to NUM_WAYS-1 generate + signal do_read : std_ulogic; + signal do_write : std_ulogic; + signal rd_addr : std_ulogic_vector(ROW_BITS-1 downto 0); + signal wr_addr : std_ulogic_vector(ROW_BITS-1 downto 0); + signal wr_data : std_ulogic_vector(DRAM_DBITS-1 downto 0); + signal wr_sel : std_ulogic_vector(ROW_SIZE-1 downto 0); + signal wr_sel_m : std_ulogic_vector(ROW_SIZE-1 downto 0); + signal dout : cache_row_t; + begin + way: entity work.cache_ram + generic map ( + ROW_BITS => ROW_BITS, + WIDTH => DRAM_DBITS, + ADD_BUF => true + ) + port map ( + clk => system_clk, + rd_en => do_read, + rd_addr => rd_addr, + rd_data => dout, + wr_sel => wr_sel_m, + wr_addr => wr_addr, + wr_data => wr_data + ); + process(all) + begin + -- + -- Read port + -- + do_read <= '1'; + cache_out(i) <= dout; + rd_addr <= std_ulogic_vector(to_unsigned(req_row, ROW_BITS)); + + -- + -- Write mux: cache refills from DRAM or writes from Wishbone + -- + if state = IDLE then + -- Write from wishbone + wr_addr <= std_ulogic_vector(to_unsigned(req_row, ROW_BITS)); + wr_data <= req_wdata; + wr_sel <= req_we; + else + -- Refill from DRAM + wr_data <= user_port0_rdata_data; + wr_sel <= (others => '1'); + wr_addr <= std_ulogic_vector(to_unsigned(refill_row, ROW_BITS)); + end if; + + -- + -- Write enable logic + -- + do_write <= '0'; + if req_op = OP_STORE_HIT and req_hit_way = i then + do_write <= '1'; + elsif user_port0_rdata_valid = '1' and refill_way = i then + do_write <= '1'; + end if; + + -- Mask write selects with do_write since BRAM doesn't always + -- have a global write-enable (Vivado generates TDP instead + -- of SDP when using one, thus doubling cache BRAM usage). + for i in 0 to ROW_SIZE-1 loop + wr_sel_m(i) <= wr_sel(i) and do_write; + end loop; + + if TRACE and rising_edge(system_clk) then + if do_write = '1' then + report "cache write way:" & integer'image(i) & + " addr:" & to_hstring(wr_addr) & + " sel:" & to_hstring(wr_sel_m) & + " data:" & to_hstring(wr_data); + end if; + end if; + end process; + end generate; + + -- Generate PLRUs + maybe_plrus: if NUM_WAYS > 1 generate + begin + plrus: for i in 0 to NUM_LINES-1 generate + -- PLRU interface + signal plru_acc : std_ulogic_vector(WAY_BITS-1 downto 0); + signal plru_acc_en : std_ulogic; + signal plru_out : std_ulogic_vector(WAY_BITS-1 downto 0); + begin + plru : entity work.plru + generic map ( + BITS => WAY_BITS + ) + port map ( + clk => system_clk, + rst => system_reset, + acc => plru_acc, + acc_en => plru_acc_en, + lru => plru_out + ); + + process(req_index, req_op, req_hit_way, plru_out) + begin + -- PLRU interface + if (req_op = OP_LOAD_HIT or + req_op = OP_STORE_HIT) and req_index = i then + plru_acc_en <= '1'; + else + plru_acc_en <= '0'; + end if; + plru_acc <= std_ulogic_vector(to_unsigned(req_hit_way, WAY_BITS)); + plru_victim(i) <= plru_out; + end process; + end generate; + end generate; + + -- + -- Wishbone interface: + -- + -- - Incoming wishbone request latch (to help with timing) + -- - Read response pipeline (to match BRAM output buffer delay) + -- - Stall generation + -- + -- XXX TODO: Properly handle cyc drops before all acks are sent... + -- + request_latch: process(system_clk) + begin + if rising_edge(system_clk) then + -- We can latch a new request if we are idle (for now). We also + -- latch the absence of request. This is a pipeline that takes + -- one per-cycle unless non-IDLE. + -- + if wb_out.stall = '0' then + -- Avoid constantly updating addr/data for unrelated requests + if wb_in.cyc = '1' then + wb_req <= wb_in; + else + wb_req.cyc <= wb_in.cyc; + wb_req.stb <= wb_in.stb; + end if; + + if TRACE then + if wb_in.cyc = '1' and wb_in.stb = '1' then + report "latch new wb req ! addr:" & to_hstring(wb_in.adr) & + " we:" & std_ulogic'image(wb_in.we) & + " sel:" & to_hstring(wb_in.sel); + end if; + end if; + end if; + end if; + end process; + + -- + -- + -- Read response pipeline + -- + -- XXX Might have to put store acks in there too (see comment in wb_response) + read_pipe: process(system_clk) + begin + if rising_edge(system_clk) then + read_ack_0 <= '1' when req_op = OP_LOAD_HIT else '0'; + read_ad3_0 <= req_ad3; + read_way_0 <= req_hit_way; + + read_ack_1 <= read_ack_0; + read_ad3_1 <= read_ad3_0; + read_way_1 <= read_way_0; + + if TRACE then + if req_op = OP_LOAD_HIT then + report "Load hit addr:" & to_hstring(wb_req.adr) & + " idx:" & integer'image(req_index) & + " tag:" & to_hstring(req_tag) & + " way:" & integer'image(req_hit_way); + elsif req_op = OP_LOAD_MISS then + report "Load miss addr:" & to_hstring(wb_req.adr); + end if; + if read_ack_0 = '1' then + report "read data:" & to_hstring(cache_out(read_way_0)); + end if; + end if; + end if; + end process; + + wb_reponse: process(all) + variable rdata : std_ulogic_vector(DRAM_DBITS-1 downto 0); + variable store_done : std_ulogic; + begin + -- Can we accept a store ? This is set when IDLE and the store + -- queue & command queue are not full. + -- + -- Note: This is only used to control the WB request latch, stall + -- and store "early complete". We don't want to use this to control + -- cmd_valid to DRAM as this would create a circular dependency inside + -- LiteDRAM as cmd_ready I think is driven from cmd_valid. + -- + -- The state machine that controls the command queue must thus + -- reproduce this logic at least partially. + -- + -- Note also that user_port0_cmd_ready from LiteDRAM is combinational + -- from user_port0_cmd_valid. IE. we won't know that LiteDRAM cannot + -- accept a command until we try to send one. + -- + if state = IDLE then + accept_store <= user_port0_cmd_ready and storeq_wr_ready; + + -- Corner case !!! The read acks pipeline takes two extra cycles + -- which means a store ack can collide with a previous load hit + -- ack. Thus we stall stores if we have a load ack pending. + if read_ack_0 = '1' or read_ack_1 = '1' then + accept_store <= '0'; + end if; + else + accept_store <= '0'; + end if; + + -- Generate stalls. For loads, we stall if we are going to take a load + -- miss or are in the middle of a refill. For stores, if we can't + -- accept it. + case state is + when IDLE => + case req_op is + when OP_LOAD_MISS => + wb_out.stall <= '1'; + when OP_STORE_MISS | OP_STORE_HIT => + wb_out.stall <= not accept_store; + when others => + wb_out.stall <= '0'; + end case; + when REFILL_WAIT_ACK => + wb_out.stall <= '1'; + end case; + + -- Data out mux + rdata := cache_out(read_way_1); + wb_out.dat <= rdata(127 downto 64) when read_ad3_1 = '1' else rdata(63 downto 0); + + -- Early-complete stores on wishbone. + if req_op = OP_STORE_HIT or req_op = OP_STORE_MISS then + store_done := accept_store; + else + store_done := '0'; + end if; + + -- Generate ACKs on read hits and store complete + -- + -- XXXX TODO: This can happen on store right behind loads ! + -- This probably need to be fixed by putting store acks in + -- the same pipeline as the read acks. TOOD: Create a testbench + -- to exercise those corner cases as the core can't yet. + -- + wb_out.ack <= read_ack_1 or store_done; + assert read_ack_0 = '0' or store_done = '0' report + "Read ack and store ack collision !" + severity failure; + end process; + + -- + -- Cache request decode + -- + request_decode: process(all) + variable valid : std_ulogic; + variable is_hit : std_ulogic; + variable hit_way : way_t; + begin + -- Extract line, row and tag from request + req_index <= get_index(wb_req.adr); + req_row <= get_row(wb_req.adr(REAL_ADDR_BITS-1 downto 0)); + req_tag <= get_tag(wb_req.adr); + + -- Calculate address of beginning of cache line, will be + -- used for cache miss processing if needed + req_laddr <= wb_req.adr(REAL_ADDR_BITS - 1 downto LINE_OFF_BITS) & + (LINE_OFF_BITS-1 downto 0 => '0'); + + + -- Do we have a valid request in the WB latch ? + if state = IDLE then + valid := wb_req.cyc and wb_req.stb; + else + valid := '0'; + end if; + + -- Store signals + req_ad3 <= wb_req.adr(3); + req_wdata <= wb_req.dat & wb_req.dat; + req_we <= wb_req.sel & "00000000" when req_ad3 = '1' else + "00000000" & wb_req.sel; + + -- Test if pending request is a hit on any way + hit_way := 0; + is_hit := '0'; + for i in way_t loop + if valid = '1' and cache_valids(req_index)(i) = '1' then + if read_tag(i, cache_tags(req_index)) = req_tag then + hit_way := i; + is_hit := '1'; + end if; + end if; + end loop; + + -- Generate the req op. We only allow OP_LOAD_* when in the + -- IDLE state as our PLRU and ACK generation rely on this, + -- stores are allowed in IDLE state. + -- + req_op <= OP_NONE; + if valid = '1' then + if wb_req.we = '1' then + if is_hit = '1' then + req_op <= OP_STORE_HIT; + else + req_op <= OP_STORE_MISS; + end if; + else + if is_hit = '1' then + req_op <= OP_LOAD_HIT; + else + req_op <= OP_LOAD_MISS; + end if; + end if; + end if; + req_hit_way <= hit_way; + end process; + -- - -- Data bus wishbone to LiteDRAM native port + -- Store queue -- - -- Address bit 3 selects the top or bottom half of the data - -- bus (64-bit wishbone vs. 128-bit DRAM interface) + -- For now, queue up to 16 stores + store_queue: entity work.sync_fifo + generic map ( + DEPTH => STOREQ_DEPTH, + WIDTH => STOREQ_BITS + ) + port map ( + clk => system_clk, + reset => system_reset, + rd_ready => storeq_rd_ready, + rd_valid => storeq_rd_valid, + rd_data => storeq_rd_data, + wr_ready => storeq_wr_ready, + wr_valid => storeq_wr_valid, + wr_data => storeq_wr_data + ); + + storeq_control : process(all) + variable stq_data : wishbone_data_type; + variable stq_sel : std_ulogic_vector(DRAM_SBITS-1 downto 0); + begin + storeq_wr_data <= wb_req.dat & req_we; + + -- Only accept store if we can send a command + if req_op = OP_STORE_HIT or req_op = OP_STORE_MISS then + storeq_wr_valid <= user_port0_cmd_ready; + else + storeq_wr_valid <= '0'; + end if; + + stq_data := storeq_rd_data(storeq_rd_data'left downto DRAM_SBITS); + stq_sel := storeq_rd_data(DRAM_SBITS-1 downto 0); + user_port0_wdata_data <= stq_data & stq_data; + user_port0_wdata_we <= stq_sel; + user_port0_wdata_valid <= storeq_rd_valid; + storeq_rd_ready <= user_port0_wdata_ready; + + if TRACE then + if rising_edge(system_clk) then + if req_op = OP_STORE_HIT then + report "Store hit to:" & + to_hstring(wb_req.adr(DRAM_ABITS+3 downto 0)) & + " data:" & to_hstring(req_wdata) & + " we:" & to_hstring(req_we) & + " V:" & std_ulogic'image(accept_store); + else + report "Store miss to:" & + to_hstring(wb_req.adr(DRAM_ABITS+3 downto 0)) & + " data:" & to_hstring(req_wdata) & + " we:" & to_hstring(req_we) & + " V:" & std_ulogic'image(accept_store); + end if; + if storeq_wr_valid = '1' and storeq_wr_ready = '1' then + report "storeq push " & to_hstring(storeq_wr_data); + end if; + if storeq_rd_valid = '1' and storeq_rd_ready = '1' then + report "storeq pop " & to_hstring(storeq_rd_data); + end if; + end if; + end if; + end process; + + -- LiteDRAM command mux + dram_commands: process(all) + begin + if state = IDLE and (req_op = OP_STORE_HIT or req_op = OP_STORE_MISS) then + -- For stores, forward signals directly. Only send command if + -- the FIFO can accept a store + user_port0_cmd_addr <= wb_req.adr(DRAM_ABITS+3 downto 4); + user_port0_cmd_we <= '1'; + user_port0_cmd_valid <= storeq_wr_ready; + else + -- For loads, we route via a latch controlled by the refill machine + user_port0_cmd_addr <= refill_cmd_addr; + user_port0_cmd_valid <= refill_cmd_valid; + user_port0_cmd_we <= '0'; + end if; + user_port0_rdata_ready <= '1'; -- Always 1 + end process; + + -- LiteDRAM refill machine -- - -- XXX TODO: Figure out how to pipeline this + -- This handles the cache line refills -- - ad3 <= wb_in.adr(3); - - -- Wishbone port IN signals - user_port0_cmd_valid <= wb_in.cyc and wb_in.stb when state = CMD else '0'; - user_port0_cmd_we <= wb_in.we when state = CMD else '0'; - user_port0_wdata_valid <= '1' when state = MWRITE else '0'; - user_port0_rdata_ready <= '1' when state = MREAD else '0'; - user_port0_cmd_addr <= wb_in.adr(DRAM_ABITS+3 downto 4); - user_port0_wdata_data <= wb_in.dat & wb_in.dat; - user_port0_wdata_we <= wb_in.sel & "00000000" when ad3 = '1' else - "00000000" & wb_in.sel; - - -- Wishbone OUT signals - wb_out.ack <= user_port0_wdata_ready when state = MWRITE else - user_port0_rdata_valid when state = MREAD else '0'; - - wb_out.dat <= user_port0_rdata_data(127 downto 64) when ad3 = '1' else - user_port0_rdata_data(63 downto 0); - - -- We don't do pipelining yet. - wb_out.stall <= '0' when wb_in.cyc = '0' else not wb_out.ack; - - -- DRAM user port State machine - sm: process(system_clk) + refill_machine : process(system_clk) + variable tagset : cache_tags_set_t; + variable cmds_done : boolean; + variable replace_way : way_t; + variable wait_qdrain : boolean; begin - - if rising_edge(system_clk) then - if system_reset = '1' then - state <= CMD; - else - case state is - when CMD => - if (user_port0_cmd_ready and user_port0_cmd_valid) = '1' then - state <= MWRITE when wb_in.we = '1' else MREAD; - end if; - when MWRITE => - if user_port0_wdata_ready = '1' then - state <= CMD; - end if; - when MREAD => - if user_port0_rdata_valid = '1' then - state <= CMD; - end if; + if rising_edge(system_clk) then + -- On reset, clear all valid bits to force misses + if system_reset = '1' then + for i in index_t loop + cache_valids(i) <= (others => '0'); + end loop; + state <= IDLE; + refill_cmd_valid <= '0'; + else + -- Main state machine + case state is + when IDLE => + assert refill_cmd_valid = '0' report "refill cmd valid in IDLE state !" + severity failure; + + -- If NO_LS_OVERLAP is set, disallow a load miss if the store + -- queue still has data in it. + wait_qdrain := false; + if NO_LS_OVERLAP then + wait_qdrain := storeq_rd_valid = '1'; + end if; + + -- We need to read a cache line + if req_op = OP_LOAD_MISS and not wait_qdrain then + -- Grab way to replace + replace_way := to_integer(unsigned(plru_victim(req_index))); + + -- Force misses on that way while refilling that line + cache_valids(req_index)(replace_way) <= '0'; + + -- Store new tag in selected way + for i in 0 to NUM_WAYS-1 loop + if i = replace_way then + tagset := cache_tags(req_index); + write_tag(i, tagset, req_tag); + cache_tags(req_index) <= tagset; + end if; + end loop; + + -- Keep track of our index and way for subsequent stores + refill_index <= req_index; + refill_way <= replace_way; + refill_row <= get_row(req_laddr); + + -- Prep for first DRAM read + -- + -- XXX TODO: We could start a cycle early here by using + -- combo logic to generate the first command in + -- "dram_commands". In fact, we could make refill_cmd_addr + -- only contain the "counter" bits and wire it with the + -- other bits from req_laddr. + refill_cmd_addr <= req_laddr(DRAM_ABITS+3 downto 4); + refill_cmd_valid <= '1'; + + if TRACE then + report "refill addr " & to_hstring(req_laddr); + end if; + + -- Track that we had one request sent + state <= REFILL_WAIT_ACK; + end if; + + when REFILL_WAIT_ACK => + -- Commands are all sent if user_port0_cmd_valid is 0 + cmds_done := refill_cmd_valid = '0'; + + -- If we are still sending requests, was one accepted ? + if user_port0_cmd_ready = '1' and not cmds_done then + -- That was the last word ? We are done sending. Clear + -- command valid and set cmds_done so we can handle an + -- eventual last ack on the same cycle. + -- + if TRACE then + report "got refill cmd ack !"; + end if; + if is_last_row_addr(refill_cmd_addr) then + refill_cmd_valid <= '0'; + cmds_done := true; + if TRACE then + report "all refill cmds done !"; + end if; + else + -- Calculate the next row address + refill_cmd_addr <= next_row_addr(refill_cmd_addr); + if TRACE then + report "refill addr " & + to_hstring(next_row_addr(refill_cmd_addr)); + end if; + end if; + end if; + + -- Incoming read data processing + if user_port0_rdata_valid = '1' then + if TRACE then + report "got refill data ack !"; + end if; + -- Check for completion + if cmds_done and is_last_row(refill_row) then + if TRACE then + report "all refill data done !"; + end if; + -- Cache line is now valid + cache_valids(refill_index)(refill_way) <= '1'; + -- We are done + state <= IDLE; + end if; + + -- Increment store row counter + refill_row <= next_row(refill_row); + end if; end case; - end if; - end if; + end if; + end if; end process; may_trace: if LITEDRAM_TRACE generate @@ -250,29 +989,29 @@ begin end generate; litedram: litedram_core - port map( - clk => clk_in, - rst => rst, - pll_locked => pll_locked, - ddram_a => ddram_a, - ddram_ba => ddram_ba, - ddram_ras_n => ddram_ras_n, - ddram_cas_n => ddram_cas_n, - ddram_we_n => ddram_we_n, - ddram_cs_n => ddram_cs_n, - ddram_dm => ddram_dm, - ddram_dq => ddram_dq, - ddram_dqs_p => ddram_dqs_p, - ddram_dqs_n => ddram_dqs_n, - ddram_clk_p => ddram_clk_p, - ddram_clk_n => ddram_clk_n, - ddram_cke => ddram_cke, - ddram_odt => ddram_odt, - ddram_reset_n => ddram_reset_n, - init_done => init_done, - init_error => init_error, - user_clk => system_clk, - user_rst => system_reset, + port map( + clk => clk_in, + rst => rst, + pll_locked => pll_locked, + ddram_a => ddram_a, + ddram_ba => ddram_ba, + ddram_ras_n => ddram_ras_n, + ddram_cas_n => ddram_cas_n, + ddram_we_n => ddram_we_n, + ddram_cs_n => ddram_cs_n, + ddram_dm => ddram_dm, + ddram_dq => ddram_dq, + ddram_dqs_p => ddram_dqs_p, + ddram_dqs_n => ddram_dqs_n, + ddram_clk_p => ddram_clk_p, + ddram_clk_n => ddram_clk_n, + ddram_cke => ddram_cke, + ddram_odt => ddram_odt, + ddram_reset_n => ddram_reset_n, + init_done => init_done, + init_error => init_error, + user_clk => system_clk, + user_rst => system_reset, wb_ctrl_adr => wb_ctrl_adr, wb_ctrl_dat_w => wb_ctrl_dat_w, wb_ctrl_dat_r => wb_ctrl_dat_r, @@ -284,17 +1023,17 @@ begin wb_ctrl_cti => "000", wb_ctrl_bte => "00", wb_ctrl_err => open, - user_port_native_0_cmd_valid => user_port0_cmd_valid, - user_port_native_0_cmd_ready => user_port0_cmd_ready, - user_port_native_0_cmd_we => user_port0_cmd_we, - user_port_native_0_cmd_addr => user_port0_cmd_addr, - user_port_native_0_wdata_valid => user_port0_wdata_valid, - user_port_native_0_wdata_ready => user_port0_wdata_ready, - user_port_native_0_wdata_we => user_port0_wdata_we, - user_port_native_0_wdata_data => user_port0_wdata_data, - user_port_native_0_rdata_valid => user_port0_rdata_valid, - user_port_native_0_rdata_ready => user_port0_rdata_ready, - user_port_native_0_rdata_data => user_port0_rdata_data - ); + user_port_native_0_cmd_valid => user_port0_cmd_valid, + user_port_native_0_cmd_ready => user_port0_cmd_ready, + user_port_native_0_cmd_we => user_port0_cmd_we, + user_port_native_0_cmd_addr => user_port0_cmd_addr, + user_port_native_0_wdata_valid => user_port0_wdata_valid, + user_port_native_0_wdata_ready => user_port0_wdata_ready, + user_port_native_0_wdata_we => user_port0_wdata_we, + user_port_native_0_wdata_data => user_port0_wdata_data, + user_port_native_0_rdata_valid => user_port0_rdata_valid, + user_port_native_0_rdata_ready => user_port0_rdata_ready, + user_port_native_0_rdata_data => user_port0_rdata_data + ); end architecture behaviour; diff --git a/litedram/gen-src/sdram_init/include/system.h b/litedram/gen-src/sdram_init/include/system.h index b980427..6d4068c 100644 --- a/litedram/gen-src/sdram_init/include/system.h +++ b/litedram/gen-src/sdram_init/include/system.h @@ -9,9 +9,9 @@ #define CONFIG_CPU_NOP "nop" #ifdef __SIM__ -#define MEMTEST_BUS_SIZE 16 -#define MEMTEST_DATA_SIZE 16 -#define MEMTEST_ADDR_SIZE 16 +#define MEMTEST_BUS_SIZE 512//16 +#define MEMTEST_DATA_SIZE 1024//16 +#define MEMTEST_ADDR_SIZE 128//16 #define CONFIG_SIM_DISABLE_DELAYS #endif diff --git a/litedram/generated/arty/litedram_core.init b/litedram/generated/arty/litedram_core.init index bbad64d..e53fc04 100644 --- a/litedram/generated/arty/litedram_core.init +++ b/litedram/generated/arty/litedram_core.init @@ -510,7 +510,7 @@ a64b5a7d14004a39 0000000000000000 0000000000000000 0000000000000000 -3842a1003c4c0001 +3842a2003c4c0001 fbc1fff07c0802a6 f8010010fbe1fff8 3be10020f821fe91 @@ -519,11 +519,11 @@ f8c101a838800140 38c101987c651b78 7fe3fb78f8e101b0 f92101c0f90101b8 -48001739f94101c8 +480017a5f94101c8 7c7e1b7860000000 -480012517fe3fb78 +480012bd7fe3fb78 3821017060000000 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(0d16e03) & LiteX (564d731a) on 2020-05-30 20:25:53 //-------------------------------------------------------------------------------- module litedram_core( input wire clk, diff --git a/litedram/generated/nexys-video/litedram_core.init b/litedram/generated/nexys-video/litedram_core.init index bbad64d..e53fc04 100644 --- a/litedram/generated/nexys-video/litedram_core.init +++ b/litedram/generated/nexys-video/litedram_core.init @@ -510,7 +510,7 @@ a64b5a7d14004a39 0000000000000000 0000000000000000 0000000000000000 -3842a1003c4c0001 +3842a2003c4c0001 fbc1fff07c0802a6 f8010010fbe1fff8 3be10020f821fe91 @@ -519,11 +519,11 @@ f8c101a838800140 38c101987c651b78 7fe3fb78f8e101b0 f92101c0f90101b8 -48001739f94101c8 +480017a5f94101c8 7c7e1b7860000000 -480012517fe3fb78 +480012bd7fe3fb78 3821017060000000 -48001cf87fc3f378 +48001d647fc3f378 0100000000000000 4e80002000000280 0000000000000000 @@ -531,67 +531,67 @@ f92101c0f90101b8 4e8000204c00012c 0000000000000000 3c4c000100000000 -7c0802a63842a05c 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a/litedram/generated/sim/litedram_core.init b/litedram/generated/sim/litedram_core.init index 8cd34d7..e257d32 100644 --- a/litedram/generated/sim/litedram_core.init +++ b/litedram/generated/sim/litedram_core.init @@ -510,7 +510,7 @@ a64b5a7d14004a39 0000000000000000 0000000000000000 0000000000000000 -384296003c4c0001 +384297003c4c0001 fbc1fff07c0802a6 f8010010fbe1fff8 3be10020f821fe91 @@ -519,11 +519,11 @@ f8c101a838800140 38c101987c651b78 7fe3fb78f8e101b0 f92101c0f90101b8 -48000da5f94101c8 +48000d65f94101c8 7c7e1b7860000000 -480008bd7fe3fb78 +4800087d7fe3fb78 3821017060000000 -480013647fc3f378 +480013247fc3f378 0100000000000000 4e80002000000280 0000000000000000 @@ -531,67 +531,67 @@ f92101c0f90101b8 4e8000204c00012c 0000000000000000 3c4c000100000000 -7c0802a63842955c +7c0802a63842965c 7d800026fbe1fff8 91810008f8010010 -480007b1f821ff91 +48000771f821ff91 3c62ffff60000000 -4bffff3538637de8 +4bffff3538637ca8 548400023880ffff 7c8026ea7c0004ac 3fe0c0003c62ffff -63ff000838637e08 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-4bfffaed3860000f +4bfffb2d3860000f 7c0004ac39200006 3b8000017d20ef2a 7f80f72a7c0004ac -4bfffacd3860000f +4bfffb0d3860000f 7c0004ac39200920 7c0004ac7d20ef2a 3860000f7fe0f72a -392004004bfffab1 +392004004bfffaf1 7d20ef2a7c0004ac 7fe0f72a7c0004ac -4bfffa9538600003 -4bfffb294bfffad5 +4bfffad538600003 +4bfffb694bfffb15 4082001c2c230000 7f80df2a7c0004ac 7f80d72a7c0004ac @@ -780,27 +772,27 @@ f821ff713f804000 4bffffec38600001 0100000000000000 3c4c000100000680 -3d20c00038428d94 +3d20c00038428ed4 6129200060000000 -f92280b879290020 +f922801079290020 612900203d20c000 7c0004ac79290020 3d40001c7d204eea 7d295392614a2000 -394a0018e94280b8 +394a0018e9428010 7c0004ac3929ffff 4e8000207d2057ea 0000000000000000 3c4c000100000000 -6000000038428d34 -39290010e92280b8 +6000000038428e74 +39290010e9228010 7d204eea7c0004ac 4082ffe871290008 -e94280b85469063e +e94280105469063e 7d2057ea7c0004ac 000000004e800020 0000000000000000 -38428cf03c4c0001 +38428e303c4c0001 fbc1fff07c0802a6 3bc3fffffbe1fff8 f821ffd1f8010010 @@ -874,7 +866,7 @@ f924000039290002 7c6307b43863ffe0 000000004e800020 0000000000000000 -38428aa03c4c0001 +38428be03c4c0001 3d2037367c0802a6 612935347d908026 65293332792907c6 @@ -908,7 +900,7 @@ fbfd00007fe9fa14 4bfffff07d29f392 0300000000000000 3c4c000100000580 -7c0802a638428994 +7c0802a638428ad4 f821ffb1480006e9 7c7f1b78eb630000 7cbd2b787c9c2378 @@ -924,7 +916,7 @@ f821ffb1480006e9 4bffffb8f93f0000 0100000000000000 3c4c000100000580 -7c0802a638428914 +7c0802a638428a54 f821ffa148000661 7c9b23787c7d1b78 388000007ca32b78 @@ -955,16 +947,16 @@ e95d00009b270000 f95d0000394a0001 000000004bffffa8 0000078001000000 -384288183c4c0001 +384289583c4c0001 480005397c0802a6 7c741b79f821fed1 38600000f8610060 2fa4000041820068 39210040419e0060 -3ac4ffff60000000 +3ac4ffff3e42ffff f92100703b410020 3ae0000060000000 -3a428068392280b0 +3a527fc039228008 f92100783ba10060 ebc1006089250000 419e00102fa90000 @@ -1196,16 +1188,35 @@ e8010010ebc1fff0 20676e69746f6f42 415244206d6f7266 0000000a2e2e2e4d +20747365746d656d +000a2e2e2e737562 +7830203a7375625b +7830203a5d783025 +2073762078383025 +000a783830257830 +257830207375625b +257830203a5d7830 +3020737620783830 +00000a7838302578 20747365746d654d 6c69616620737562 252f6425203a6465 73726f7272652064 000000000000000a -20747365746d654d -6961662061746164 -2f6425203a64656c -726f727265206425 -0000000000000a73 +20747365746d656d +0a2e2e2e61746164 +0000000000000000 +783020617461645b +7830203a5d783025 +2073762078383025 +000a783830257830 +20747365746d656d +0a2e2e2e72646461 +0000000000000000 +783020726464615b +7830203a5d783025 +2073762078383025 +000a783830257830 20747365746d654d 6961662072646461 2f6425203a64656c diff --git a/litedram/generated/sim/litedram_core.v b/litedram/generated/sim/litedram_core.v index b92a59c..bdb7dff 100644 --- a/litedram/generated/sim/litedram_core.v +++ b/litedram/generated/sim/litedram_core.v @@ -1,5 +1,5 @@ //-------------------------------------------------------------------------------- -// Auto-generated by Migen (0d16e03) & LiteX (564d731a) on 2020-05-26 20:37:42 +// Auto-generated by Migen (0d16e03) & LiteX (564d731a) on 2020-05-30 20:25:57 //-------------------------------------------------------------------------------- module litedram_core( input wire clk, diff --git a/microwatt.core b/microwatt.core index 8dc5a12..fb26f63 100644 --- a/microwatt.core +++ b/microwatt.core @@ -48,6 +48,7 @@ filesets: - soc.vhdl - xics.vhdl - syscon.vhdl + - sync_fifo.vhdl file_type : vhdlSource-2008 fpga: diff --git a/sync_fifo.vhdl b/sync_fifo.vhdl new file mode 100644 index 0000000..79a4deb --- /dev/null +++ b/sync_fifo.vhdl @@ -0,0 +1,163 @@ +-- Synchronous FIFO with a protocol similar to AXI +-- +-- The outputs are generated combinationally from the inputs +-- in order to allow for back-to-back transfers with the type +-- of flow control used by busses lite AXI, pipelined WB or +-- LiteDRAM native port when the FIFO is full. +-- +-- That means that care needs to be taken by the user not to +-- generate the inputs combinationally from the outputs otherwise +-- it would create a logic loop. +-- +-- If breaking that loop is required, a stash buffer could be +-- added to break the flow control "loop" between the read and +-- the write port. +-- +library ieee; +use ieee.std_logic_1164.all; + +library work; +use work.utils.all; + +entity sync_fifo is + generic( + -- Fifo depth in entries + DEPTH : natural := 64; + + -- Fifo width in bits + WIDTH : natural := 32; + + -- When INIT_ZERO is set, the memory is pre-initialized to 0's + INIT_ZERO : boolean := false + ); + port( + -- Control lines: + clk : in std_ulogic; + reset : in std_ulogic; + + -- Write port + wr_ready : out std_ulogic; + wr_valid : in std_ulogic; + wr_data : in std_ulogic_vector(WIDTH - 1 downto 0); + + -- Read port + rd_ready : in std_ulogic; + rd_valid : out std_ulogic; + rd_data : out std_ulogic_vector(WIDTH - 1 downto 0) + ); +end entity sync_fifo; + +architecture behaviour of sync_fifo is + + subtype data_t is std_ulogic_vector(WIDTH - 1 downto 0); + type memory_t is array(0 to DEPTH - 1) of data_t; + + function init_mem return memory_t is + variable m : memory_t; + begin + if INIT_ZERO then + for i in 0 to DEPTH - 1 loop + m(i) := (others => '0'); + end loop; + end if; + return m; + end function; + + signal memory : memory_t := init_mem; + + subtype index_t is integer range 0 to DEPTH - 1; + signal rd_idx : index_t; + signal rd_next : index_t; + signal wr_idx : index_t; + signal wr_next : index_t; + + function next_index(idx : index_t) return index_t is + variable r : index_t; + begin + if ispow2(DEPTH) then + r := (idx + 1) mod DEPTH; + else + r := idx + 1; + if r = DEPTH then + r := 0; + end if; + end if; + return r; + end function; + + type op_t is (OP_POP, OP_PUSH); + signal op_prev : op_t := OP_POP; + signal op_next : op_t; + + signal full, empty : std_ulogic; + signal push, pop : std_ulogic; +begin + + -- Current state at last clock edge + empty <= '1' when rd_idx = wr_idx and op_prev = OP_POP else '0'; + full <= '1' when rd_idx = wr_idx and op_prev = OP_PUSH else '0'; + + -- We can accept new data if we aren't full or we are but + -- the read port is going to accept data this cycle + wr_ready <= rd_ready or not full; + + -- We can provide data if we aren't empty or we are but + -- the write port is going to provide data this cycle + rd_valid <= wr_valid or not empty; + + -- Internal control signals + push <= wr_ready and wr_valid; + pop <= rd_ready and rd_valid; + + -- Next state + rd_next <= next_index(rd_idx) when pop = '1' else rd_idx; + wr_next <= next_index(wr_idx) when push = '1' else wr_idx; + with push & pop select op_next <= + OP_PUSH when "10", + OP_POP when "01", + op_prev when others; + + -- Read port output + rd_data <= memory(rd_idx) when empty = '0' else wr_data; + + -- Read counter + reader: process(clk) + begin + if rising_edge(clk) then + if reset = '1' then + rd_idx <= 0; + else + rd_idx <= rd_next; + end if; + end if; + end process; + + -- Write counter and memory write + producer: process(clk) + begin + if rising_edge(clk) then + if reset = '1' then + wr_idx <= 0; + else + wr_idx <= wr_next; + + if push = '1' then + memory(wr_idx) <= wr_data; + end if; + end if; + end if; + end process; + + -- Previous op latch used for generating empty/full + op: process(clk) + begin + if rising_edge(clk) then + if reset = '1' then + op_prev <= OP_POP; + else + op_prev <= op_next; + end if; + end if; + end process; + +end architecture behaviour; -- 2.30.2