From a386fb004bfd7b07ff8951f6c7d66df23ef88285 Mon Sep 17 00:00:00 2001 From: Dmitry Selyutin Date: Fri, 11 Nov 2022 22:24:00 +0300 Subject: [PATCH] power_insn: support subvector length specifiers --- src/openpower/decoder/power_insn.py | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/src/openpower/decoder/power_insn.py b/src/openpower/decoder/power_insn.py index 120e92cb..b98fac4d 100644 --- a/src/openpower/decoder/power_insn.py +++ b/src/openpower/decoder/power_insn.py @@ -2480,6 +2480,22 @@ class SpecifierWidth(Specifier): insn.prefix.rm.elwidth = self.value +@_dataclasses.dataclass(eq=True, frozen=True) +class SpecifierSubVL(Specifier): + value: int + + @classmethod + def match(cls, desc, record): + value = {"vec2": 1, "vec3": 2, "vec4": 3}.get(desc) + if value is None: + return None + + return cls(record=record, value=value) + + def assemble(self, insn): + insn.prefix.rm.subvl = self.value + + class SVP64Instruction(PrefixedInstruction): """SVP64 instruction: https://libre-soc.org/openpower/sv/svp64/""" class Prefix(PrefixedInstruction.Prefix): @@ -2506,6 +2522,7 @@ class SVP64Instruction(PrefixedInstruction): def specifier(cls, desc, record): specifiers = ( SpecifierWidth, + SpecifierSubVL, ) for spec_cls in specifiers: -- 2.30.2