From a38ae503ff3a88852bcf27cc8b56ff110595081b Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Thu, 10 Oct 2019 00:38:03 +1100 Subject: [PATCH] cache_ram: Add write-enables They will be needed by the dcache Signed-off-by: Benjamin Herrenschmidt --- cache_ram.vhdl | 25 +++++++++++++++++++++++-- icache.vhdl | 1 + 2 files changed, 24 insertions(+), 2 deletions(-) diff --git a/cache_ram.vhdl b/cache_ram.vhdl index e0ffd17..346c6fe 100644 --- a/cache_ram.vhdl +++ b/cache_ram.vhdl @@ -6,7 +6,8 @@ use ieee.math_real.all; entity cache_ram is generic( ROW_BITS : integer := 16; - WIDTH : integer := 64 + WIDTH : integer := 64; + TRACE : boolean := false ); port( @@ -15,6 +16,7 @@ entity cache_ram is rd_addr : in std_logic_vector(ROW_BITS - 1 downto 0); rd_data : out std_logic_vector(WIDTH - 1 downto 0); wr_en : in std_logic; + wr_sel : in std_logic_vector(WIDTH/8 - 1 downto 0); wr_addr : in std_logic_vector(ROW_BITS - 1 downto 0); wr_data : in std_logic_vector(WIDTH - 1 downto 0) ); @@ -33,13 +35,32 @@ architecture rtl of cache_ram is begin process(clk) + variable lbit : integer range 0 to WIDTH - 1; + variable mbit : integer range 0 to WIDTH - 1; + variable widx : integer range 0 to SIZE - 1; begin if rising_edge(clk) then if wr_en = '1' then - ram(to_integer(unsigned(wr_addr))) <= wr_data; + if TRACE then + report "write a:" & to_hstring(wr_addr) & + " sel:" & to_hstring(wr_sel) & + " dat:" & to_hstring(wr_data); + end if; + for i in 0 to WIDTH/8-1 loop + lbit := i * 8; + mbit := lbit + 7; + widx := to_integer(unsigned(wr_addr)); + if wr_sel(i) = '1' then + ram(widx)(mbit downto lbit) <= wr_data(mbit downto lbit); + end if; + end loop; end if; if rd_en = '1' then rd_data <= ram(to_integer(unsigned(rd_addr))); + if TRACE then + report "read a:" & to_hstring(rd_addr) & + " dat:" & to_hstring(ram(to_integer(unsigned(rd_addr)))); + end if; end if; end if; end process; diff --git a/icache.vhdl b/icache.vhdl index 89e491e..804b648 100644 --- a/icache.vhdl +++ b/icache.vhdl @@ -290,6 +290,7 @@ begin rd_addr => rd_addr, rd_data => dout, wr_en => do_write, + wr_sel => (others => '1'), wr_addr => wr_addr, wr_data => wishbone_in.dat ); -- 2.30.2