From a3b9692a68e88bbe3e32e0dbbd30c5e20f3800b7 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 20 Mar 2014 13:40:01 +0100
Subject: [PATCH] Fixed mapping of Verific WIDE_DFFRS operator

---
 frontends/verific/verific.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index cf72b7819..7411e9434 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -466,9 +466,9 @@ static bool import_netlist_instance_cells(RTLIL::Module *module, std::map<Net*,
 	if (inst->Type() == OPER_WIDE_DFFRS) {
 		RTLIL::SigSpec sig_set = operatorInport(inst, "set", net_map);
 		RTLIL::SigSpec sig_reset = operatorInport(inst, "reset", net_map);
-		if (sig_set.is_fully_const() && !sig_set.as_bool() && sig_set.is_fully_const() && !sig_set.as_bool()) {
+		if (sig_set.is_fully_const() && !sig_set.as_bool() && sig_reset.is_fully_const() && !sig_reset.as_bool())
 			module->addDff(RTLIL::escape_id(inst->Name()), net_map.at(inst->GetClock()), IN, OUT);
-		} else
+		else
 			module->addDffsr(RTLIL::escape_id(inst->Name()), net_map.at(inst->GetClock()), sig_set, sig_reset, IN, OUT);
 		return true;
 	}
-- 
2.30.2