From a3d348cca75ec7c2b7d24e1ea98cd54ec65c0c87 Mon Sep 17 00:00:00 2001 From: Timothy Hayes Date: Fri, 18 Oct 2019 16:53:59 +0100 Subject: [PATCH] mem-ruby: MESI_Three_Level fix L1 MRU absence The L1 cache is updating the MRU tag after acessing a cache line. This patch updates MRU for cases when the L0 cache loads/stores a line from/to the L1 cache. Change-Id: I1f0ccef26b3c7614dc865a38c39145840dabfd01 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24258 Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com> Reviewed-by: Giacomo Travaglini Maintainer: Giacomo Travaglini --- src/mem/ruby/protocol/MESI_Three_Level-L1cache.sm | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/mem/ruby/protocol/MESI_Three_Level-L1cache.sm b/src/mem/ruby/protocol/MESI_Three_Level-L1cache.sm index a2f2d807b..eec07ca31 100644 --- a/src/mem/ruby/protocol/MESI_Three_Level-L1cache.sm +++ b/src/mem/ruby/protocol/MESI_Three_Level-L1cache.sm @@ -617,6 +617,8 @@ machine(MachineType:L1Cache, "MESI Directory L1 Cache CMP") out_msg.DataBlk := cache_entry.DataBlk; out_msg.MessageSize := MessageSizeType:Response_Data; } + + cache.setMRU(address); } action(hh_xdata_to_l0, "\h", desc="If not prefetch, notify sequencer that store completed.") { @@ -633,6 +635,8 @@ machine(MachineType:L1Cache, "MESI Directory L1 Cache CMP") //cache_entry.Dirty := true; } + + cache.setMRU(address); } action(h_stale_data_to_l0, "hs", desc="If not prefetch, send data to the L0 cache.") { -- 2.30.2