From a3ff19afa1a297c2f74fb75aa078c855e41bad91 Mon Sep 17 00:00:00 2001 From: lkcl Date: Sat, 30 Apr 2022 21:20:15 +0100 Subject: [PATCH] --- openpower/sv/svp64/appendix.mdwn | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn index 5bccb480e..4ef3ab880 100644 --- a/openpower/sv/svp64/appendix.mdwn +++ b/openpower/sv/svp64/appendix.mdwn @@ -70,7 +70,8 @@ CPU ISA. Vectorisation of the VSX Packed SIMD system makes no sense whatsoever, the sole exceptions potentially being any operations with 128-bit -operands such as `vrlq` (Rotate Quad Word). +operands such as `vrlq` (Rotate Quad Word) and `xsaddqp` (Scalar +Quad-precision Add). SV effectively *replaces* VSX requiring far less instructions, and provides, at the very minimum, predication (which VSX was designed without). Thus all VSX Major Opcodes - all of them - are "unused" and must raise -- 2.30.2