From a4183eba69f645a89b3bd865fcf4032ff4a02985 Mon Sep 17 00:00:00 2001 From: whitequark Date: Fri, 21 Dec 2018 23:55:02 +0000 Subject: [PATCH] hdl.mem: use more informative signal naming for ports. --- nmigen/hdl/mem.py | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/nmigen/hdl/mem.py b/nmigen/hdl/mem.py index 3467a2b..48ad40a 100644 --- a/nmigen/hdl/mem.py +++ b/nmigen/hdl/mem.py @@ -68,10 +68,12 @@ class ReadPort: self.synchronous = synchronous self.transparent = transparent - self.addr = Signal(max=memory.depth) - self.data = Signal(memory.width) + self.addr = Signal(max=memory.depth, + name="{}_r_addr".format(memory.name)) + self.data = Signal(memory.width, + name="{}_r_data".format(memory.name)) if synchronous and not transparent: - self.en = Signal() + self.en = Signal(name="{}_r_en".format(memory.name)) else: self.en = Const(1) @@ -131,9 +133,12 @@ class WritePort: self.priority = priority self.granularity = granularity - self.addr = Signal(max=memory.depth) - self.data = Signal(memory.width) - self.en = Signal(memory.width // granularity) + self.addr = Signal(max=memory.depth, + name="{}_w_addr".format(memory.name)) + self.data = Signal(memory.width, + name="{}_w_data".format(memory.name)) + self.en = Signal(memory.width // granularity, + name="{}_w_en".format(memory.name)) def get_fragment(self, platform): f = Instance("$memwr", -- 2.30.2