From a42c2eb59cbce50b0cae93f4b44c8d9a2ecd1de7 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 11 May 2020 19:18:29 +0100 Subject: [PATCH] comments from discussion https://bugs.libre-soc.org/show_bug.cgi?id=305#c43 --- src/soc/alu/input_stage.py | 3 +++ src/soc/alu/test/test_pipe_caller.py | 4 ++++ 2 files changed, 7 insertions(+) diff --git a/src/soc/alu/input_stage.py b/src/soc/alu/input_stage.py index 389954b5..37bc3317 100644 --- a/src/soc/alu/input_stage.py +++ b/src/soc/alu/input_stage.py @@ -38,6 +38,9 @@ class ALUInputStage(PipeModBase): ##### operand B ##### + # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43 + # remove this, just do self.o.b.eq(self.i.b) and move the + # immediate-detection into set_alu_inputs in the unit test # If there's an immediate, set the B operand to that with m.If(self.i.ctx.op.imm_data.imm_ok & ~(self.i.ctx.op.insn_type == InternalOp.OP_RLC)): diff --git a/src/soc/alu/test/test_pipe_caller.py b/src/soc/alu/test/test_pipe_caller.py index 6e6a69b2..55ce27d4 100644 --- a/src/soc/alu/test/test_pipe_caller.py +++ b/src/soc/alu/test/test_pipe_caller.py @@ -27,6 +27,10 @@ def get_rec_width(rec): def set_alu_inputs(alu, dec2, sim): inputs = [] + # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43 + # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok)) + # and place it into data_i.b + reg3_ok = yield dec2.e.read_reg3.ok if reg3_ok: reg3_sel = yield dec2.e.read_reg3.data -- 2.30.2