From a4370ecefa5bdf117361521627a2bf224bdef94d Mon Sep 17 00:00:00 2001 From: lkcl Date: Thu, 23 Jun 2022 12:41:41 +0100 Subject: [PATCH] --- openpower/sv/mv.vec.mdwn | 44 ++-------------------------------------- 1 file changed, 2 insertions(+), 42 deletions(-) diff --git a/openpower/sv/mv.vec.mdwn b/openpower/sv/mv.vec.mdwn index a95b9ba1e..9c510ee6c 100644 --- a/openpower/sv/mv.vec.mdwn +++ b/openpower/sv/mv.vec.mdwn @@ -75,47 +75,7 @@ room within the reserved bits of `svremap` as well. Also used on [[sv/mv.swizzle]] -`RM-2P-1S1D-PU` Mode is applicable to all mv operations +`RM-2P-1S1D-PU` Mode, described in [[svp64/appendix]] +is applicable to all mv operations (fmv etc) and to Indexed LD/ST. -The usual RM-2P-1S1D is reduced from EXTRA3 to EXTRA2, making -room for 2 extra bits that enable either "packing" or "unpacking" -on the subvectors vec2/3/4. - -Illustrating a -"normal" SVP64 operation with `SUBVL!=1:` (assuming no elwidth overrides): - - def index(): - for i in range(VL): - for j in range(SUBVL): - yield i*SUBVL+j - - for idx in index(): - operation_on(RA+idx) - -For pack/unpack (again, no elwidth overrides): - - # yield an outer-SUBVL or inner VL loop with SUBVL - def index_p(outer): - if outer: - for j in range(SUBVL): - for i in range(VL): - yield i+VL*j - else: - for i in range(VL): - for j in range(SUBVL): - yield i*SUBVL+j - - # walk through both source and dest indices simultaneously - for src_idx, dst_idx in zip(index_p(PACK), index_p(UNPACK)): - move_operation(RT+dst_idx, RA+src_idx) - -"yield" from python is used here for simplicity and clarity. -The two Finite State Machines for the generation of the source -and destination element offsets progress incrementally in -lock-step. - -Setting of both `PACK_en` and `UNPACK_en` is neither prohibited nor -`UNDEFINED` because the reordering is fully deterministic, and -additional REMAP reordering may be applied. For Matrix this would -give potentially up to 4 Dimensions of reordering. -- 2.30.2