From a445cb35bdf607857742a322576cd9763b1d67ea Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Wed, 15 Jan 2020 10:47:17 +0100 Subject: [PATCH] aco: do not combine additions of DS instructions on GFX6 MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit The offset field doesn't work as expected on GFX6. Signed-off-by: Samuel Pitoiset Reviewed-by: Daniel Schürmann Part-of: --- src/amd/compiler/aco_optimizer.cpp | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/amd/compiler/aco_optimizer.cpp b/src/amd/compiler/aco_optimizer.cpp index 224918c172f..d8e42d88b7d 100644 --- a/src/amd/compiler/aco_optimizer.cpp +++ b/src/amd/compiler/aco_optimizer.cpp @@ -787,7 +787,11 @@ void label_instruction(opt_ctx &ctx, Block& block, aco_ptr& instr) DS_instruction *ds = static_cast(instr.get()); Temp base; uint32_t offset; - if (i == 0 && parse_base_offset(ctx, instr.get(), i, &base, &offset) && base.regClass() == instr->operands[i].regClass() && instr->opcode != aco_opcode::ds_swizzle_b32) { + bool has_usable_ds_offset = ctx.program->chip_class >= GFX7; + if (has_usable_ds_offset && + i == 0 && parse_base_offset(ctx, instr.get(), i, &base, &offset) && + base.regClass() == instr->operands[i].regClass() && + instr->opcode != aco_opcode::ds_swizzle_b32) { if (instr->opcode == aco_opcode::ds_write2_b32 || instr->opcode == aco_opcode::ds_read2_b32 || instr->opcode == aco_opcode::ds_write2_b64 || instr->opcode == aco_opcode::ds_read2_b64) { if (offset % 4 == 0 && -- 2.30.2