From a4515c3066bf93362cf06379a2f71ef4ca5ef9df Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Thu, 10 Dec 2020 02:07:59 +0000
Subject: [PATCH]

---
 openpower/sv/svp_rewrite/svp64/discussion.mdwn | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/openpower/sv/svp_rewrite/svp64/discussion.mdwn b/openpower/sv/svp_rewrite/svp64/discussion.mdwn
index 5999ec4c1..291613aa1 100644
--- a/openpower/sv/svp_rewrite/svp64/discussion.mdwn
+++ b/openpower/sv/svp_rewrite/svp64/discussion.mdwn
@@ -27,6 +27,22 @@ something like:
 * psrc / pdst - predicate mask selector and inversion
 * vspec - 3 bit src / dest scalar-vector extension
 
+# standard arith ops (single predication)
+
+these are of the form res = op(src1, src2, ...)
+
+| 0   1 | 2 3 | 5    | 6  8 | 13 20 |
+| ----- | --- | ---- | ---- | ----- |
+| subvl | ew  | ptyp | pred | vspec |
+
+
+* subvl - 1 to 4 scalar / vec2 / vec3 / vec4
+* ew - DEFAULT / 8 / 16 /32 element width
+* ptyp - predication INT / CR
+* pred - predicate mask selector and inversion
+* vspec - 2/3 bit src / dest scalar-vector extension
+
+For 2 op (dest/src1/src2) the tag may be 2 bits.  for 3 op (dest/src1/2/3) the vspec may be 2 bits per reg.
 
 # Notes about Swizzle
 
-- 
2.30.2