From a46b23e136f56e1bb44065d260b49c24b656bd8b Mon Sep 17 00:00:00 2001 From: Ramana Radhakrishnan Date: Fri, 9 Oct 2015 10:53:31 +0000 Subject: [PATCH] [Patch PR target/67366 1/2] [ARM] - Add movmisalignhi / si patterns This adds movmisalignhi and movmisalignsi expanders when unaligned access is allowed by the architecture. This allows the mid-end to expand to misaligned loads and stored. Compared code generated for the Linux kernel and it changes code generation for a handful of files all for the better basically by reducing the stack usage. Tested by : 1. armhf bootstrap and regression test - no regressions. 2.. arm-none-eabi cross build and regression test for {-marm/-march=armv7-a/-mfpu=vfpv3-d16/-mfloat-abi=softfp} {-mthumb/-march=armv8-a/-mfpu=crypto-neon-fp-armv8/-mfloat-abi=hard} {-marm/-mcpu=arm7tdmi/-mfloat-abi=soft} {-mthumb/-mcpu=arm7tdmi/-mfloat-abi=soft} Will apply to trunk once 2/2 is approved. regards Ramana 2015-10-09 Ramana Radhakrishnan PR target/67366 * config/arm/arm.md (movmisalign): New. * config/arm/iterators.md (HSI): New. From-SVN: r228643 --- gcc/ChangeLog | 6 ++++++ gcc/config/arm/arm.md | 35 +++++++++++++++++++++++++++++++++++ gcc/config/arm/iterators.md | 3 +++ 3 files changed, 44 insertions(+) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 108cbdf5cf2..8f096c7b4b0 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2015-10-09 Ramana Radhakrishnan + + PR target/67366 + * config/arm/arm.md (movmisalign): New. + * config/arm/iterators.md (HSI): New. + 2015-10-09 Richard Biener PR tree-optimization/67891 diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index c5985bbb506..02e147ec4a4 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -11504,6 +11504,41 @@ }" ) +;; movmisalign patterns for HImode and SImode. +(define_expand "movmisalign" + [(match_operand:HSI 0 "general_operand") + (match_operand:HSI 1 "general_operand")] + "unaligned_access" +{ + /* This pattern is not permitted to fail during expansion: if both arguments + are non-registers (e.g. memory := constant), force operand 1 into a + register. */ + rtx (* gen_unaligned_load)(rtx, rtx); + rtx tmp_dest = operands[0]; + if (!s_register_operand (operands[0], mode) + && !s_register_operand (operands[1], mode)) + operands[1] = force_reg (mode, operands[1]); + + if (mode == HImode) + { + gen_unaligned_load = gen_unaligned_loadhiu; + tmp_dest = gen_reg_rtx (SImode); + } + else + gen_unaligned_load = gen_unaligned_loadsi; + + if (MEM_P (operands[1])) + { + emit_insn (gen_unaligned_load (tmp_dest, operands[1])); + if (mode == HImode) + emit_move_insn (operands[0], gen_lowpart (HImode, tmp_dest)); + } + else + emit_insn (gen_unaligned_store (operands[0], operands[1])); + + DONE; +}) + ;; Vector bits common to IWMMXT and Neon (include "vec-common.md") ;; Load the Intel Wireless Multimedia Extension patterns diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md index 47cc1eebecd..6a541251ed1 100644 --- a/gcc/config/arm/iterators.md +++ b/gcc/config/arm/iterators.md @@ -33,6 +33,9 @@ ;; A list of integer modes that are up to one word long (define_mode_iterator QHSI [QI HI SI]) +;; A list of integer modes that are half and one word long +(define_mode_iterator HSI [HI SI]) + ;; A list of integer modes that are less than a word (define_mode_iterator NARROW [QI HI]) -- 2.30.2