From a475f1534312a5672b5cc73356625b8dc42829df Mon Sep 17 00:00:00 2001 From: Srinath Parvathaneni Date: Tue, 17 Mar 2020 14:21:50 +0000 Subject: [PATCH] [ARM][GCC][4/1x]: MVE intrinsics with unary operand. This patch supports following MVE ACLE intrinsics with unary operand. vctp16q, vctp32q, vctp64q, vctp8q, vpnot. Please refer to M-profile Vector Extension (MVE) intrinsics [1] for more details. [1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics There are few conflicts in defining the machine registers, resolved by re-ordering VPR_REGNUM, APSRQ_REGNUM and APSRGE_REGNUM. 2020-03-17 Andre Vieira Mihail Ionescu Srinath Parvathaneni * config/arm/arm-builtins.c (hi_UP): Define mode. * config/arm/arm.h (IS_VPR_REGNUM): Move. * config/arm/arm.md (VPR_REGNUM): Define before APSRQ_REGNUM. (APSRQ_REGNUM): Modify. (APSRGE_REGNUM): Modify. * config/arm/arm_mve.h (vctp16q): Define macro. (vctp32q): Likewise. (vctp64q): Likewise. (vctp8q): Likewise. (vpnot): Likewise. (__arm_vctp16q): Define intrinsic. (__arm_vctp32q): Likewise. (__arm_vctp64q): Likewise. (__arm_vctp8q): Likewise. (__arm_vpnot): Likewise. * config/arm/arm_mve_builtins.def (UNOP_UNONE_UNONE): Use builtin qualifier. * config/arm/mve.md (mve_vctpqhi): Define RTL pattern. (mve_vpnothi): Likewise. gcc/testsuite/ChangeLog: 2020-03-17 Andre Vieira Mihail Ionescu Srinath Parvathaneni * gcc.target/arm/mve/intrinsics/vctp16q.c: New test. * gcc.target/arm/mve/intrinsics/vctp32q.c: Likewise. * gcc.target/arm/mve/intrinsics/vctp64q.c: Likewise. * gcc.target/arm/mve/intrinsics/vctp8q.c: Likewise. * gcc.target/arm/mve/intrinsics/vpnot.c: Likewise. --- gcc/ChangeLog | 24 +++++++++++ gcc/config/arm/arm-builtins.c | 1 + gcc/config/arm/arm_mve.h | 40 +++++++++++++++++++ gcc/config/arm/arm_mve_builtins.def | 5 +++ gcc/config/arm/mve.md | 34 +++++++++++++++- gcc/testsuite/ChangeLog | 10 +++++ .../gcc.target/arm/mve/intrinsics/vctp16q.c | 22 ++++++++++ .../gcc.target/arm/mve/intrinsics/vctp32q.c | 22 ++++++++++ .../gcc.target/arm/mve/intrinsics/vctp64q.c | 22 ++++++++++ .../gcc.target/arm/mve/intrinsics/vctp8q.c | 22 ++++++++++ .../gcc.target/arm/mve/intrinsics/vpnot.c | 22 ++++++++++ 11 files changed, 223 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp16q.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp32q.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp64q.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp8q.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpnot.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 8f7b261ca9d..501484cc0ba 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,27 @@ +2020-03-17 Andre Vieira + Mihail Ionescu + Srinath Parvathaneni + + * config/arm/arm-builtins.c (hi_UP): Define mode. + * config/arm/arm.h (IS_VPR_REGNUM): Move. + * config/arm/arm.md (VPR_REGNUM): Define before APSRQ_REGNUM. + (APSRQ_REGNUM): Modify. + (APSRGE_REGNUM): Modify. + * config/arm/arm_mve.h (vctp16q): Define macro. + (vctp32q): Likewise. + (vctp64q): Likewise. + (vctp8q): Likewise. + (vpnot): Likewise. + (__arm_vctp16q): Define intrinsic. + (__arm_vctp32q): Likewise. + (__arm_vctp64q): Likewise. + (__arm_vctp8q): Likewise. + (__arm_vpnot): Likewise. + * config/arm/arm_mve_builtins.def (UNOP_UNONE_UNONE): Use builtin + qualifier. + * config/arm/mve.md (mve_vctpqhi): Define RTL pattern. + (mve_vpnothi): Likewise. + 2020-03-17 Andre Vieira Mihail Ionescu Srinath Parvathaneni diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c index b8656b82651..81d6546027c 100644 --- a/gcc/config/arm/arm-builtins.c +++ b/gcc/config/arm/arm-builtins.c @@ -415,6 +415,7 @@ arm_set_sat_qualifiers[SIMD_MAX_BUILTIN_ARGS] #define hf_UP E_HFmode #define bf_UP E_BFmode #define si_UP E_SImode +#define hi_UP E_HImode #define void_UP E_VOIDmode #define sf_UP E_SFmode #define UP(X) X##_UP diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h index 912849f0acd..7f94e11c0ea 100644 --- a/gcc/config/arm/arm_mve.h +++ b/gcc/config/arm/arm_mve.h @@ -192,6 +192,11 @@ typedef struct { uint8x16_t val[4]; } uint8x16x4_t; #define vcvtmq_u32_f32(__a) __arm_vcvtmq_u32_f32(__a) #define vcvtaq_u16_f16(__a) __arm_vcvtaq_u16_f16(__a) #define vcvtaq_u32_f32(__a) __arm_vcvtaq_u32_f32(__a) +#define vctp16q(__a) __arm_vctp16q(__a) +#define vctp32q(__a) __arm_vctp32q(__a) +#define vctp64q(__a) __arm_vctp64q(__a) +#define vctp8q(__a) __arm_vctp8q(__a) +#define vpnot(__a) __arm_vpnot(__a) #endif __extension__ extern __inline void @@ -703,6 +708,41 @@ __arm_vaddlvq_u32 (uint32x4_t __a) return __builtin_mve_vaddlvq_uv4si (__a); } +__extension__ extern __inline int64_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vctp16q (uint32_t __a) +{ + return __builtin_mve_vctp16qhi (__a); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vctp32q (uint32_t __a) +{ + return __builtin_mve_vctp32qhi (__a); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vctp64q (uint32_t __a) +{ + return __builtin_mve_vctp64qhi (__a); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vctp8q (uint32_t __a) +{ + return __builtin_mve_vctp8qhi (__a); +} + +__extension__ extern __inline mve_pred16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vpnot (mve_pred16_t __a) +{ + return __builtin_mve_vpnothi (__a); +} + #if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */ __extension__ extern __inline void diff --git a/gcc/config/arm/arm_mve_builtins.def b/gcc/config/arm/arm_mve_builtins.def index 44807d6e8c4..5d569696545 100644 --- a/gcc/config/arm/arm_mve_builtins.def +++ b/gcc/config/arm/arm_mve_builtins.def @@ -71,3 +71,8 @@ VAR2 (UNOP_UNONE_NONE, vcvtaq_u, v8hi, v4si) VAR2 (UNOP_UNONE_IMM, vmvnq_n_u, v8hi, v4si) VAR1 (UNOP_UNONE_UNONE, vrev16q_u, v16qi) VAR1 (UNOP_UNONE_UNONE, vaddlvq_u, v4si) +VAR1 (UNOP_UNONE_UNONE, vctp16q, hi) +VAR1 (UNOP_UNONE_UNONE, vctp32q, hi) +VAR1 (UNOP_UNONE_UNONE, vctp64q, hi) +VAR1 (UNOP_UNONE_UNONE, vctp8q, hi) +VAR1 (UNOP_UNONE_UNONE, vpnot, hi) diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index dafdc1cf16e..2f997e8f80b 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -36,7 +36,7 @@ VREV32Q_U VREV32Q_S VMOVLTQ_U VMOVLTQ_S VMOVLBQ_S VMOVLBQ_U VCVTQ_FROM_F_S VCVTQ_FROM_F_U VCVTPQ_S VCVTPQ_U VCVTNQ_S VCVTNQ_U VCVTMQ_S VCVTMQ_U - VADDLVQ_U]) + VADDLVQ_U VCTP8Q VCTP16Q VCTP32Q VCTP64Q VPNOT]) (define_mode_attr MVE_CNVT [(V8HI "V8HF") (V4SI "V4SF") (V8HF "V8HI") (V4SF "V4SI")]) @@ -54,6 +54,9 @@ (VCLZQ_U "u") (VCLZQ_S "s") (VREV32Q_U "u") (VREV32Q_S "s") (VADDLVQ_U "u") (VADDLVQ_S "s")]) +(define_int_attr mode1 [(VCTP8Q "8") (VCTP16Q "16") (VCTP32Q "32") + (VCTP64Q "64")]) + (define_int_iterator VCVTQ_TO_F [VCVTQ_TO_F_S VCVTQ_TO_F_U]) (define_int_iterator VMVNQ_N [VMVNQ_N_U VMVNQ_N_S]) (define_int_iterator VREV64Q [VREV64Q_S VREV64Q_U]) @@ -71,6 +74,7 @@ (define_int_iterator VCVTNQ [VCVTNQ_S VCVTNQ_U]) (define_int_iterator VCVTMQ [VCVTMQ_S VCVTMQ_U]) (define_int_iterator VADDLVQ [VADDLVQ_U VADDLVQ_S]) +(define_int_iterator VCTPQ [VCTP8Q VCTP16Q VCTP32Q VCTP64Q]) (define_insn "*mve_mov" [(set (match_operand:MVE_types 0 "nonimmediate_operand" "=w,w,r,w,w,r,w,Us") @@ -655,3 +659,31 @@ "vaddlv.32 %Q0, %R0, %q1" [(set_attr "type" "mve_move") ]) + +;; +;; [vctp8q vctp16q vctp32q vctp64q]) +;; +(define_insn "mve_vctpqhi" + [ + (set (match_operand:HI 0 "vpr_register_operand" "=Up") + (unspec:HI [(match_operand:SI 1 "s_register_operand" "r")] + VCTPQ)) + ] + "TARGET_HAVE_MVE" + "vctp. %1" + [(set_attr "type" "mve_move") +]) + +;; +;; [vpnot]) +;; +(define_insn "mve_vpnothi" + [ + (set (match_operand:HI 0 "vpr_register_operand" "=Up") + (unspec:HI [(match_operand:HI 1 "vpr_register_operand" "0")] + VPNOT)) + ] + "TARGET_HAVE_MVE" + "vpnot" + [(set_attr "type" "mve_move") +]) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index b360cff2484..de68c54e6b4 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,13 @@ +2020-03-17 Andre Vieira + Mihail Ionescu + Srinath Parvathaneni + + * gcc.target/arm/mve/intrinsics/vctp16q.c: New test. + * gcc.target/arm/mve/intrinsics/vctp32q.c: Likewise. + * gcc.target/arm/mve/intrinsics/vctp64q.c: Likewise. + * gcc.target/arm/mve/intrinsics/vctp8q.c: Likewise. + * gcc.target/arm/mve/intrinsics/vpnot.c: Likewise. + 2020-03-17 Andre Vieira Mihail Ionescu Srinath Parvathaneni diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp16q.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp16q.c new file mode 100644 index 00000000000..52a6b52725f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp16q.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (uint32_t a) +{ + return vctp16q (a); +} + +/* { dg-final { scan-assembler "vctp.16" } } */ + +mve_pred16_t +foo1 (uint32_t a) +{ + return vctp16q (a); +} + +/* { dg-final { scan-assembler "vctp.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp32q.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp32q.c new file mode 100644 index 00000000000..703518a4d9c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp32q.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (uint32_t a) +{ + return vctp32q (a); +} + +/* { dg-final { scan-assembler "vctp.32" } } */ + +mve_pred16_t +foo1 (uint32_t a) +{ + return vctp32q (a); +} + +/* { dg-final { scan-assembler "vctp.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp64q.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp64q.c new file mode 100644 index 00000000000..2f83a2249ee --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp64q.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (uint32_t a) +{ + return vctp64q (a); +} + +/* { dg-final { scan-assembler "vctp.64" } } */ + +mve_pred16_t +foo1 (uint32_t a) +{ + return vctp64q (a); +} + +/* { dg-final { scan-assembler "vctp.64" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp8q.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp8q.c new file mode 100644 index 00000000000..ed696ac86e6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp8q.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (uint32_t a) +{ + return vctp8q (a); +} + +/* { dg-final { scan-assembler "vctp.8" } } */ + +mve_pred16_t +foo1 (uint32_t a) +{ + return vctp8q (a); +} + +/* { dg-final { scan-assembler "vctp.8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpnot.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpnot.c new file mode 100644 index 00000000000..7e08b1b90fe --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpnot.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +mve_pred16_t +foo (mve_pred16_t a) +{ + return vpnot (a); +} + +/* { dg-final { scan-assembler "vpnot" } } */ + +mve_pred16_t +foo1 (mve_pred16_t a) +{ + return vpnot (a); +} + +/* { dg-final { scan-assembler "vpnot" } } */ -- 2.30.2