From a48ff4e856722fc33e7494def2a9adad31ae9467 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 16 May 2019 07:58:48 +0100
Subject: [PATCH] experiment lock out of registers in read vector

---
 src/experiment/compalu.py | 4 ++--
 src/experiment/cscore.py  | 9 ++++-----
 src/scoreboard/fn_unit.py | 2 +-
 3 files changed, 7 insertions(+), 8 deletions(-)

diff --git a/src/experiment/compalu.py b/src/experiment/compalu.py
index 12e6a92f..d03a8d2c 100644
--- a/src/experiment/compalu.py
+++ b/src/experiment/compalu.py
@@ -53,8 +53,8 @@ class ComputationUnitNoDelay(Elaboratable):
         # outputs
         m.d.comb += self.busy_o.eq(opc_l.q) # busy out
 
-        with m.If(src_l.q & (self.counter == 0)):
-            m.d.sync += self.counter.eq(2)
+        with m.If(req_l.qn & opc_l.q & (self.counter == 0)):
+            m.d.sync += self.counter.eq(3)
         with m.If(self.counter > 0):
             m.d.sync += self.counter.eq(self.counter - 1)
         with m.If((self.counter == 1) | (self.counter == 0)):
diff --git a/src/experiment/cscore.py b/src/experiment/cscore.py
index ae44fb72..bdbf8ace 100644
--- a/src/experiment/cscore.py
+++ b/src/experiment/cscore.py
@@ -131,9 +131,9 @@ class Scoreboard(Elaboratable):
                      regdecode.src1_i.eq(self.int_src1_i),
                      regdecode.src2_i.eq(self.int_src2_i),
                      regdecode.enable_i.eq(1),
-                     issueunit.i.dest_i.eq(regdecode.dest_o),
                      self.issue_o.eq(issueunit.issue_o)
                     ]
+        m.d.sync += issueunit.i.dest_i.eq(regdecode.dest_o),
         self.int_insn_i = issueunit.i.insn_i # enabled by instruction decode
 
         # connect global rd/wr pending vectors
@@ -339,7 +339,7 @@ def scoreboard_sim(dut, alusim):
                 dest = 3
             else:
                 src1 = 5
-                src2 = 4
+                src2 = 3
                 dest = 7
 
             #op = (i+1) % 2
@@ -355,7 +355,6 @@ def scoreboard_sim(dut, alusim):
                 yield from print_reg(dut, [3,4,5])
                 for i in range(len(dut.int_insn_i)):
                     yield dut.int_insn_i[i].eq(0)
-                yield
                 break
             print ("busy",)
             yield from print_reg(dut, [3,4,5])
@@ -395,8 +394,8 @@ def explore_groups(dut):
 
 
 def test_scoreboard():
-    dut = Scoreboard(32, 8)
-    alusim = RegSim(32, 8)
+    dut = Scoreboard(16, 8)
+    alusim = RegSim(16, 8)
     vl = rtlil.convert(dut, ports=dut.ports())
     with open("test_scoreboard.il", "w") as f:
         f.write(vl)
diff --git a/src/scoreboard/fn_unit.py b/src/scoreboard/fn_unit.py
index 3edabbde..fc05a9af 100644
--- a/src/scoreboard/fn_unit.py
+++ b/src/scoreboard/fn_unit.py
@@ -171,7 +171,7 @@ class FnUnit(Elaboratable):
         g_wr_v = Signal(self.reg_width, reset_less=True)
         g_wr = Signal(reset_less=True)
         wo = Signal(reset_less=True)
-        m.d.comb += g_wr_v.eq(g_pend_i & xx_pend_o)
+        m.d.comb += g_wr_v.eq(g_pend_i & xx_pend_o & self.rd_pend_o)
         m.d.comb += g_wr.eq(~g_wr_v.bool())
         m.d.comb += wo.eq(g_wr & rd_l.qn & self.req_rel_i & shadown)
         m.d.comb += writable_o.eq(wo)
-- 
2.30.2