From a493e05d5ba09bb438e2817908be89c728d425e1 Mon Sep 17 00:00:00 2001 From: Alexandre Oliva Date: Tue, 2 Feb 2021 00:31:44 -0300 Subject: [PATCH] introduce -msvp64 for libre-soc vector extensions --- gcc/config/rs6000/altivec.md | 2 +- gcc/config/rs6000/constraints.md | 15 + gcc/config/rs6000/predicates.md | 12 + gcc/config/rs6000/rs6000-c.c | 3 + gcc/config/rs6000/rs6000-cpus.def | 1 + gcc/config/rs6000/rs6000-modes.def | 35 ++ gcc/config/rs6000/rs6000.c | 185 +++++- gcc/config/rs6000/rs6000.h | 936 +++++++++++++++++++++++------ gcc/config/rs6000/rs6000.md | 45 +- gcc/config/rs6000/rs6000.opt | 4 + gcc/config/rs6000/svp64.md | 270 +++++++++ gcc/config/rs6000/t-rs6000 | 3 +- gcc/config/rs6000/vector.md | 2 +- gcc/doc/invoke.texi | 8 +- 14 files changed, 1304 insertions(+), 217 deletions(-) create mode 100644 gcc/config/rs6000/svp64.md diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index 27a269b9e72..ce2680454c5 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -500,7 +500,7 @@ ;; Simple binary operations. ;; add -(define_insn "add3" +(define_insn "@altivec_add3" [(set (match_operand:VI2 0 "register_operand" "=v") (plus:VI2 (match_operand:VI2 1 "register_operand" "v") (match_operand:VI2 2 "register_operand" "v")))] diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md index 561ce9797af..72d419990ed 100644 --- a/gcc/config/rs6000/constraints.md +++ b/gcc/config/rs6000/constraints.md @@ -99,6 +99,21 @@ "@internal Like @code{b}, if @option{-mpowerpc64} is used; otherwise, @code{NO_REGS}.") +(define_register_constraint "wI" "SVP64_GENERAL_REGS" + "A general-purpose svp64 register.") + +(define_register_constraint "wH" "SVP64_FLOAT_REGS" + "A floating-point svp64 register.") + +(define_register_constraint "wV" "SVP64_VL_REGS" + "The svp64 vector length register.") + +(define_register_constraint "wC" "SVP64_CR_REGS" + "A condition svp64 register.") + +(define_register_constraint "wP" "SVP64_BITPRED_REGS" + "A general-purpose register that can be used as an svp64 vector predicate.") + ;; wB needs ISA 2.07 VUPKHSW (define_constraint "wB" "@internal Signed 5-bit constant integer that can be loaded into an diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md index bd26c62b3a4..aec7e7ea3ab 100644 --- a/gcc/config/rs6000/predicates.md +++ b/gcc/config/rs6000/predicates.md @@ -1904,3 +1904,15 @@ { return address_is_prefixed (XEXP (op, 0), mode, NON_PREFIXED_DEFAULT); }) + +;; Return true if the operand is the VL register, or an immediate that +;; can be loaded into it. +(define_predicate "svp64_vector_length" + (match_code "const_int,reg") +{ + if (GET_CODE (op) == CONST_INT) + return INTVAL (op) >= 1 && INTVAL (op) <= 64; + if (GET_CODE (op) == REG) + return REGNO (op) == SVP64VL_REGNO || !reload_completed; + gcc_unreachable (); +}) diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c index 06b3bc0df33..39ba569bbb0 100644 --- a/gcc/config/rs6000/rs6000-c.c +++ b/gcc/config/rs6000/rs6000-c.c @@ -602,6 +602,9 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags, /* Whether pc-relative code is being generated. */ if ((flags & OPTION_MASK_PCREL) != 0) rs6000_define_or_undefine_macro (define_p, "__PCREL__"); + + if ((flags & OPTION_MASK_SVP64) != 0) + rs6000_define_or_undefine_macro (define_p, "__SVP64__"); } void diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def index f0cf79e2982..de90badc2f1 100644 --- a/gcc/config/rs6000/rs6000-cpus.def +++ b/gcc/config/rs6000/rs6000-cpus.def @@ -158,6 +158,7 @@ | OPTION_MASK_RECIP_PRECISION \ | OPTION_MASK_SOFT_FLOAT \ | OPTION_MASK_STRICT_ALIGN_OPTIONAL \ + | OPTION_MASK_SVP64 \ | OPTION_MASK_VSX) #endif diff --git a/gcc/config/rs6000/rs6000-modes.def b/gcc/config/rs6000/rs6000-modes.def index e6f0806eb59..b5958568596 100644 --- a/gcc/config/rs6000/rs6000-modes.def +++ b/gcc/config/rs6000/rs6000-modes.def @@ -78,6 +78,41 @@ VECTOR_MODES (FLOAT, 32); /* V16HF V8SF V4DF */ VECTOR_MODE (FLOAT, SF, 2); /* V2SF */ VECTOR_MODE (INT, SI, 2); /* V2SI */ +/* SVP64 vector modes, with MAXVL capped at 64. */ +/* 1-reg, 8-byte widths. */ +/* VECTOR_MODE (FLOAT, HF, 4); *//* V4HF */ +VECTOR_MODE (FLOAT, DF, 1); /* V1DF */ +VECTOR_MODE (INT, QI, 8); /* V8QI */ +VECTOR_MODE (INT, HI, 4); /* V4HI */ +VECTOR_MODE (INT, DI, 1); /* V1DI */ +/* 2-reg, 16-byte widths covered above: */ + /* V8HF V4SF V2DF V16QI V8HI V4SI V2DI */ +/* 4-reg, 32-byte widths covered above. */ + /* V16HF V8SF V4DF V32QI V16HI V8SI V4DI */ +/* 8-reg, 64-byte widths. */ +/* VECTOR_MODE (FLOAT, HF, 32); *//* V32HF */ +VECTOR_MODE (FLOAT, SF, 16); /* V16SF */ +VECTOR_MODE (FLOAT, DF, 8); /* V8DF */ +VECTOR_MODE (INT, QI, 64); /* V64QI */ +VECTOR_MODE (INT, HI, 32); /* V32HI */ +VECTOR_MODE (INT, SI, 16); /* V16SI */ +VECTOR_MODE (INT, DI, 8); /* V8DI */ +/* 16-reg, 128-byte widths. */ +/* VECTOR_MODE (FLOAT, HF, 64); *//* V64HF */ +VECTOR_MODE (FLOAT, SF, 32); /* V32SF */ +VECTOR_MODE (FLOAT, DF, 16); /* V16DF */ +VECTOR_MODE (INT, HI, 64); /* V64HI */ +VECTOR_MODE (INT, SI, 32); /* V32SI */ +VECTOR_MODE (INT, DI, 16); /* V16DI */ +/* 32-reg, 256-byte widths. */ +VECTOR_MODE (FLOAT, SF, 64); /* V64SF */ +VECTOR_MODE (FLOAT, DF, 32); /* V32DF */ +VECTOR_MODE (INT, SI, 64); /* V64SI */ +VECTOR_MODE (INT, DI, 32); /* V32DI */ +/* 64-reg, 512-byte widths. */ +VECTOR_MODE (FLOAT, DF, 64); /* V64DF */ +VECTOR_MODE (INT, DI, 64); /* V64DI */ + /* Replacement for TImode that only is allowed in GPRs. We also use PTImode for quad memory atomic operations to force getting an even/odd register combination. */ diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 108a01990f9..991da1f9fc0 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -1205,11 +1205,35 @@ char rs6000_reg_names[][8] = "8", "9", "10", "11", "12", "13", "14", "15", "16", "17", "18", "19", "20", "21", "22", "23", "24", "25", "26", "27", "28", "29", "30", "31", + "32", "33", "34", "35", "36", "37", "38", "39", + "40", "41", "42", "43", "44", "45", "46", "47", + "48", "49", "50", "51", "52", "53", "54", "55", + "56", "57", "58", "59", "60", "61", "62", "63", + "64", "65", "66", "67", "68", "69", "70", "71", + "72", "73", "74", "75", "76", "77", "78", "79", + "80", "81", "82", "83", "84", "85", "86", "87", + "88", "89", "90", "91", "92", "93", "94", "95", + "96", "97", "98", "99","100","101","102","103", + "104","105","106","107","108","109","110","111", + "112","113","114","115","116","117","118","119", + "120","121","122","123","124","125","126","127", /* FPRs */ "0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "10", "11", "12", "13", "14", "15", "16", "17", "18", "19", "20", "21", "22", "23", "24", "25", "26", "27", "28", "29", "30", "31", + "32", "33", "34", "35", "36", "37", "38", "39", + "40", "41", "42", "43", "44", "45", "46", "47", + "48", "49", "50", "51", "52", "53", "54", "55", + "56", "57", "58", "59", "60", "61", "62", "63", + "64", "65", "66", "67", "68", "69", "70", "71", + "72", "73", "74", "75", "76", "77", "78", "79", + "80", "81", "82", "83", "84", "85", "86", "87", + "88", "89", "90", "91", "92", "93", "94", "95", + "96", "97", "98", "99","100","101","102","103", + "104","105","106","107","108","109","110","111", + "112","113","114","115","116","117","118","119", + "120","121","122","123","124","125","126","127", /* VRs */ "0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "10", "11", "12", "13", "14", "15", @@ -1219,34 +1243,88 @@ char rs6000_reg_names[][8] = "lr", "ctr", "ca", "ap", /* cr0..cr7 */ "0", "1", "2", "3", "4", "5", "6", "7", + "8", "9", "10", "11", "12", "13", "14", "15", + "16", "17", "18", "19", "20", "21", "22", "23", + "24", "25", "26", "27", "28", "29", "30", "31", + "32", "33", "34", "35", "36", "37", "38", "39", + "40", "41", "42", "43", "44", "45", "46", "47", + "48", "49", "50", "51", "52", "53", "54", "55", + "56", "57", "58", "59", "60", "61", "62", "63", + "64", "65", "66", "67", "68", "69", "70", "71", + "72", "73", "74", "75", "76", "77", "78", "79", + "80", "81", "82", "83", "84", "85", "86", "87", + "88", "89", "90", "91", "92", "93", "94", "95", + "96", "97", "98", "99","100","101","102","103", + "104","105","106","107","108","109","110","111", + "112","113","114","115","116","117","118","119", + "120","121","122","123","124","125","126","127", /* vrsave vscr sfp */ - "vrsave", "vscr", "sfp", + "vrsave", "vscr", "sfp", "vl", }; #ifdef TARGET_REGNAMES static const char alt_reg_names[][8] = { /* GPRs */ - "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", - "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", - "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23", - "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31", + "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", + "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", + "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23", + "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31", + "%r32", "%r33", "%r34", "%r35", "%r36", "%r37", "%r38", "%r39", + "%r40", "%r41", "%r42", "%r43", "%r44", "%r45", "%r46", "%r47", + "%r48", "%r49", "%r50", "%r51", "%r52", "%r53", "%r54", "%r55", + "%r56", "%r57", "%r58", "%r59", "%r60", "%r61", "%r62", "%r63", + "%r64", "%r65", "%r66", "%r67", "%r68", "%r69", "%r70", "%r71", + "%r72", "%r73", "%r74", "%r75", "%r76", "%r77", "%r78", "%r79", + "%r80", "%r81", "%r82", "%r83", "%r84", "%r85", "%r86", "%r87", + "%r88", "%r89", "%r90", "%r91", "%r92", "%r93", "%r94", "%r95", + "%r96", "%r97", "%r98", "%r99", "%r100", "%r101", "%r102", "%r103", + "%r104", "%r105", "%r106", "%r107", "%r108", "%r109", "%r110", "%r111", + "%r112", "%r113", "%r114", "%r115", "%r116", "%r117", "%r118", "%r119", + "%r120", "%r121", "%r122", "%r123", "%r124", "%r125", "%r126", "%r127", /* FPRs */ - "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", - "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", - "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", - "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31", + "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", + "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", + "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", + "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31", + "%f32", "%f33", "%f34", "%f35", "%f36", "%f37", "%f38", "%f39", + "%f40", "%f41", "%f42", "%f43", "%f44", "%f45", "%f46", "%f47", + "%f48", "%f49", "%f50", "%f51", "%f52", "%f53", "%f54", "%f55", + "%f56", "%f57", "%f58", "%f59", "%f60", "%f61", "%f62", "%f63", + "%f64", "%f65", "%f66", "%f67", "%f68", "%f69", "%f70", "%f71", + "%f72", "%f73", "%f74", "%f75", "%f76", "%f77", "%f78", "%f79", + "%f80", "%f81", "%f82", "%f83", "%f84", "%f85", "%f86", "%f87", + "%f88", "%f89", "%f90", "%f91", "%f92", "%f93", "%f94", "%f95", + "%f96", "%f97", "%f98", "%f99", "%f100", "%f101", "%f102", "%f103", + "%f104", "%f105", "%f106", "%f107", "%f108", "%f109", "%f110", "%f111", + "%f112", "%f113", "%f114", "%f115", "%f116", "%f117", "%f118", "%f119", + "%f120", "%f121", "%f122", "%f123", "%f124", "%f125", "%f126", "%f127", /* VRs */ - "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7", - "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15", - "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23", - "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31", + "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7", + "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15", + "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23", + "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31", /* lr ctr ca ap */ - "lr", "ctr", "ca", "ap", - /* cr0..cr7 */ - "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7", - /* vrsave vscr sfp */ - "vrsave", "vscr", "sfp", + "lr", "ctr", "ca", "ap", + /* cr0..cr127 */ + "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7", + "%cr8", "%cr9", "%cr10", "%cr11", "%cr12", "%cr13", "%cr14", "%cr15", + "%cr16", "%cr17", "%cr18", "%cr19", "%cr20", "%cr21", "%cr22", "%cr23", + "%cr24", "%cr25", "%cr26", "%cr27", "%cr28", "%cr29", "%cr30", "%cr31", + "%cr32", "%cr33", "%cr34", "%cr35", "%cr36", "%cr37", "%cr38", "%cr39", + "%cr40", "%cr41", "%cr42", "%cr43", "%cr44", "%cr45", "%cr46", "%cr47", + "%cr48", "%cr49", "%cr50", "%cr51", "%cr52", "%cr53", "%cr54", "%cr55", + "%cr56", "%cr57", "%cr58", "%cr59", "%cr60", "%cr61", "%cr62", "%cr63", + "%cr64", "%cr65", "%cr66", "%cr67", "%cr68", "%cr69", "%cr70", "%cr71", + "%cr72", "%cr73", "%cr74", "%cr75", "%cr76", "%cr77", "%cr78", "%cr79", + "%cr80", "%cr81", "%cr82", "%cr83", "%cr84", "%cr85", "%cr86", "%cr87", + "%cr88", "%cr89", "%cr90", "%cr91", "%cr92", "%cr93", "%cr94", "%cr95", + "%cr96", "%cr97", "%cr98", "%cr99","%cr100","%cr101","%cr102","%cr103", + "%cr104","%cr105","%cr106","%cr107","%cr108","%cr109","%cr110","%cr111", + "%cr112","%cr113","%cr114","%cr115","%cr116","%cr117","%cr118","%cr119", + "%cr120","%cr121","%cr122","%cr123","%cr124","%cr125","%cr126","%cr127", + /* vrsave vscr sfp vl */ + "vrsave", "vscr", "sfp", "vl", }; #endif @@ -2767,6 +2845,14 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) rs6000_regno_regclass[ARG_POINTER_REGNUM] = BASE_REGS; rs6000_regno_regclass[FRAME_POINTER_REGNUM] = BASE_REGS; + for (r = LAST_GPR_REGNO + 1; r <= LAST_SVP64GPR_REGNO; ++r) + rs6000_regno_regclass[r] = SVP64_GENERAL_REGS; + for (r = LAST_FPR_REGNO + 1; r <= LAST_SVP64FPR_REGNO; ++r) + rs6000_regno_regclass[r] = SVP64_FLOAT_REGS; + for (r = MAX_CR_REGNO + 1; r <= MAX_SVP64CR_REGNO; ++r) + rs6000_regno_regclass[r] = SVP64_CR_REGS; + rs6000_regno_regclass[(int)SVP64VL_REGNO] = SVP64_VL_REGS; + /* Precalculate register class to simpler reload register class. We don't need all of the register classes that are combinations of different classes, just the simple ones that have constraint letters. */ @@ -2980,7 +3066,11 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) /* Set up the reload helper and direct move functions. */ if (TARGET_VSX || TARGET_ALTIVEC) { - if (TARGET_64BIT) + if (TARGET_SVP64) + { + /* Do nothing for now. */ + } + else if (TARGET_64BIT) { reg_addr[V16QImode].reload_store = CODE_FOR_reload_v16qi_di_store; reg_addr[V16QImode].reload_load = CODE_FOR_reload_v16qi_di_load; @@ -3168,7 +3258,7 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) else if (c == ALTIVEC_REGS) reg_size = UNITS_PER_ALTIVEC_WORD; - else if (c == FLOAT_REGS) + else if (c == FLOAT_REGS || c == SVP64_FLOAT_REGS) reg_size = UNITS_PER_FP_WORD; else @@ -9783,7 +9873,7 @@ rs6000_conditional_register_usage (void) /* Conditionally disable FPRs. */ if (TARGET_SOFT_FLOAT) - for (i = FIRST_FPR_REGNO; i <= LAST_FPR_REGNO; i++) + for (i = FIRST_FPR_REGNO; i <= LAST_SVP64FPR_REGNO; i++) fixed_regs[i] = call_used_regs[i] = 1; /* The TOC register is not killed across calls in a way that is @@ -9825,6 +9915,19 @@ rs6000_conditional_register_usage (void) for (i = FIRST_ALTIVEC_REGNO + 20; i < FIRST_ALTIVEC_REGNO + 32; ++i) fixed_regs[i] = call_used_regs[i] = 1; } + + if (!TARGET_SVP64) + { + for (i = LAST_GPR_REGNO + 1; i <= LAST_SVP64GPR_REGNO; i++) + fixed_regs[i] = call_used_regs[i] = 1; + for (i = LAST_FPR_REGNO + 1; i <= LAST_SVP64FPR_REGNO; i++) + fixed_regs[i] = call_used_regs[i] = 1; + for (i = MAX_CR_REGNO + 1; i <= MAX_SVP64CR_REGNO; i++) + fixed_regs[i] = call_used_regs[i] = 1; + + i = SVP64VL_REGNO; + fixed_regs[i] = call_used_regs[i] = 1; + } } @@ -12688,6 +12791,19 @@ rs6000_preferred_reload_class (rtx x, enum reg_class rclass) && (reg_addr[mode].addr_mask[RELOAD_REG_FPR] & RELOAD_REG_VALID) == 0) return NO_REGS; +#define SVP64_REG_CLASS_P(CLASS) \ + ( (CLASS) == SVP64_GENERAL_REGS \ + || (CLASS) == SVP64_FLOAT_REGS \ + || (CLASS) == SVP64_VL_REGS \ + || (CLASS) == SVP64_CR_REGS \ + || (CLASS) == SVP64_BITPRED_REGS) + if (TARGET_SVP64 && SVP64_REG_CLASS_P (rclass) && GET_CODE (x) != PLUS) + { + if (is_constant || MEM_P (x)) + return NO_REGS; + return rclass; + } + /* For VSX, see if we should prefer FLOAT_REGS or ALTIVEC_REGS. Do not allow the reloading of address expressions using PLUS into floating point registers. */ @@ -23427,6 +23543,14 @@ rs6000_compute_pressure_classes (enum reg_class *pressure_classes) pressure_classes[n++] = CR_REGS; pressure_classes[n++] = SPECIAL_REGS; + if (TARGET_SVP64) + { + pressure_classes[n++] = SVP64_GENERAL_REGS; + pressure_classes[n++] = SVP64_FLOAT_REGS; + pressure_classes[n++] = SVP64_VL_REGS; + pressure_classes[n++] = SVP64_CR_REGS; + } + return n; } @@ -23556,6 +23680,15 @@ rs6000_dbx_register_number (unsigned int regno, unsigned int format) if (regno == FIRST_ALTIVEC_REGNO) return 100; + if (regno > LAST_GPR_REGNO && regno <= LAST_SVP64GPR_REGNO) + return regno - (LAST_GPR_REGNO + 1) + 1500; + if (regno > LAST_FPR_REGNO && regno <= LAST_SVP64FPR_REGNO) + return regno - (LAST_FPR_REGNO + 1) + 1600; + if (regno > MAX_CR_REGNO && regno <= MAX_SVP64CR_REGNO) + return regno - (MAX_CR_REGNO + 1) + 1700; + if (regno == SVP64VL_REGNO) + return 1699; + gcc_unreachable (); #endif } @@ -23589,6 +23722,15 @@ rs6000_dbx_register_number (unsigned int regno, unsigned int format) if (regno == FIRST_ALTIVEC_REGNO) return 64; + if (regno > LAST_GPR_REGNO && regno <= LAST_SVP64GPR_REGNO) + return regno - (LAST_GPR_REGNO + 1) + 1500; + if (regno > LAST_FPR_REGNO && regno <= LAST_SVP64FPR_REGNO) + return regno - (LAST_FPR_REGNO + 1) + 1600; + if (regno > MAX_CR_REGNO && regno <= MAX_SVP64CR_REGNO) + return regno - (MAX_CR_REGNO + 1) + 1700; + if (regno == SVP64VL_REGNO) + return 1699; + gcc_unreachable (); } @@ -23806,6 +23948,7 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] = { "recip-precision", OPTION_MASK_RECIP_PRECISION, false, true }, { "save-toc-indirect", OPTION_MASK_SAVE_TOC_INDIRECT, false, true }, { "string", 0, false, true }, + { "svp64", OPTION_MASK_SVP64, false, true }, { "update", OPTION_MASK_NO_UPDATE, true , true }, { "vsx", OPTION_MASK_VSX, false, true }, #ifdef OPTION_MASK_64BIT diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index f8a02c8a850..5e834aad2a5 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -822,7 +822,8 @@ enum data_align { align_abi, align_opt, align_both }; RS/6000 has 32 fixed-point registers, 32 floating-point registers, a count register, a link register, and 8 condition register fields, which we view here as separate registers. AltiVec adds 32 vector - registers and a VRsave register. + registers and a VRsave register. SVP64 extends fixed-point, + floating-point and condition register files to 128 registers each. In addition, the difference between the frame and argument pointers is a function of the number of registers saved, so we need to have a @@ -837,7 +838,7 @@ enum data_align { align_abi, align_opt, align_both }; Another pseudo (not included in DWARF_FRAME_REGISTERS) is soft frame pointer, which is eventually eliminated in favor of SP or FP. */ -#define FIRST_PSEUDO_REGISTER 111 +#define FIRST_PSEUDO_REGISTER 424 /* The SVP64 registers are not call-saved, so the unwinder doesn't have to deal with them. If this grows, System.OS_Interface.Alternate_Stack_Size in the @@ -868,18 +869,37 @@ enum data_align { align_abi, align_opt, align_both }; {/* GPRs */ \ 0, 1, FIXED_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ /* FPRs */ \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ /* VRs */ \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ /* lr ctr ca ap */ \ 0, 0, 1, 1, \ - /* cr0..cr7 */ \ - 0, 0, 0, 0, 0, 0, 0, 0, \ - /* vrsave vscr sfp */ \ - 1, 1, 1 \ + /* cr0..cr63 */ \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + /* vrsave vscr sfp vl */ \ + 1, 1, 1, 1 \ } /* Like `CALL_USED_REGISTERS' except this macro doesn't require that @@ -892,18 +912,37 @@ enum data_align { align_abi, align_opt, align_both }; {/* GPRs */ \ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ /* FPRs */ \ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ /* VRs */ \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ /* lr ctr ca ap */ \ 1, 1, 1, 1, \ - /* cr0..cr7 */ \ - 1, 1, 0, 0, 0, 1, 1, 1, \ + /* cr0..cr63 */ \ + 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ /* vrsave vscr sfp */ \ - 0, 0, 0 \ + 0, 0, 0, 1 \ } #define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1) @@ -961,29 +1000,71 @@ enum data_align { align_abi, align_opt, align_both }; #endif #define REG_ALLOC_ORDER \ - {32, \ - /* move fr13 (ie 45) later, so if we need TFmode, it does */ \ + {128, \ + /* move fr13 (ie 141) later, so if we need TFmode, it does */\ /* not use fr14 which is a saved register. */ \ - 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, 45, \ - 33, \ - 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \ - 50, 49, 48, 47, 46, \ - 100, 107, 105, 106, 101, 104, 103, 102, \ + 140, 139, 138, 137, 136, 135, 134, 133, 132, 131, 130, 141, \ + 129, \ + 159, 158, 157, 156, 155, 154, 153, 152, 151, 150, \ + 149, 148, 147, 146, 145, 144, 143, 142, \ + 292, 299, 297, 298, 293, 296, 295, 294, \ MAYBE_R2_AVAILABLE \ 9, 10, 8, 7, 6, 5, 4, \ 3, EARLY_R12 11, 0, \ 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, \ 18, 17, 16, 15, 14, 13, LATE_R12 \ - 97, 96, \ - 1, MAYBE_R2_FIXED 99, 98, \ + 289, 288, \ + 1, MAYBE_R2_FIXED 291, 290, \ /* AltiVec registers. */ \ - 64, 65, \ - 77, 76, 75, 74, 73, 72, 71, 70, 69, 68, 67, \ - 66, \ - 83, 82, 81, 80, 79, 78, \ - 95, 94, 93, 92, 91, 90, 89, 88, 87, 86, 85, 84, \ - 108, 109, \ - 110 \ + 256, 257, \ + 269, 268, 267, 266, 265, 264, 263, 262, 261, 260, 259, \ + 258, \ + 275, 274, 273, 272, 271, 270, \ + 287, 286, 285, 284, 283, 282, 281, 280, 279, 278, 277, 276, \ + 420, 421, \ + 422, 423, \ + /* SVP64 extended GPR. */ \ + 32, 33, 34, 35, 36, 37, 38, 39, \ + 40, 41, 42, 43, 44, 45, 46, 47, \ + 48, 49, 50, 51, 52, 53, 54, 55, \ + 56, 57, 58, 59, 60, 61, 62, 63, \ + 64, 65, 66, 67, 68, 69, 70, 71, \ + 72, 73, 74, 75, 76, 77, 78, 79, \ + 80, 81, 82, 83, 84, 85, 86, 87, \ + 88, 89, 90, 91, 92, 93, 94, 95, \ + 96, 97, 98, 99, 100, 101, 102, 103, \ + 104, 105, 106, 107, 108, 109, 110, 111, \ + 112, 113, 114, 115, 116, 117, 118, 119, \ + 120, 121, 122, 123, 124, 125, 126, 127, \ + /* SVP64 extended FPR. */ \ + 160, 161, 162, 163, 164, 165, 166, 167, \ + 168, 169, 170, 171, 172, 173, 174, 175, \ + 176, 177, 178, 179, 180, 181, 182, 183, \ + 184, 185, 186, 187, 188, 189, 190, 191, \ + 192, 193, 194, 195, 196, 197, 198, 199, \ + 200, 201, 202, 203, 204, 205, 206, 207, \ + 208, 209, 210, 211, 212, 213, 214, 215, \ + 216, 217, 218, 219, 220, 221, 222, 223, \ + 224, 225, 226, 227, 228, 229, 230, 231, \ + 232, 233, 234, 235, 236, 237, 238, 239, \ + 240, 241, 242, 243, 244, 245, 246, 247, \ + 248, 249, 250, 251, 252, 253, 254, 255, \ + /* SVP64 extended CR. */ \ + 300, 301, 302, 303, 304, 305, 306, 307, \ + 308, 309, 310, 311, 312, 313, 314, 315, \ + 316, 317, 318, 319, 320, 321, 322, 323, \ + 324, 325, 326, 327, 328, 329, 330, 331, \ + 332, 333, 334, 335, 336, 337, 338, 339, \ + 340, 341, 342, 343, 344, 345, 346, 347, \ + 348, 349, 350, 351, 352, 353, 354, 355, \ + 356, 357, 358, 359, 360, 361, 362, 363, \ + 364, 365, 366, 367, 368, 369, 370, 371, \ + 372, 373, 374, 375, 376, 377, 378, 379, \ + 380, 381, 382, 383, 384, 385, 386, 387, \ + 388, 389, 390, 391, 392, 393, 394, 395, \ + 396, 397, 398, 399, 400, 401, 402, 403, \ + 404, 405, 406, 407, 408, 409, 410, 411, \ + 412, 413, 414, 415, 416, 417, 418, 419, \ } /* True if register is floating-point. */ @@ -1024,6 +1105,25 @@ enum data_align { align_abi, align_opt, align_both }; (INT_REGNO_P (N) || ALTIVEC_REGNO_P (N) \ || (TARGET_VSX && FP_REGNO_P (N))) \ +/* SVP64 general-purpose register file. */ +#define SVP64_GPR_REGNO_P(N) \ + ((N) >= FIRST_GPR_REGNO && (N) <= LAST_SVP64GPR_REGNO) +/* SVP64 general-purpose register file extension. */ +#define SVP64_GPR_XREGNO_P(N) \ + (SVP64_GPR_REGNO_P (N) && !INT_REGNO_P (N)) +/* SVP64 floating-point register file. */ +#define SVP64_FPR_REGNO_P(N) \ + ((N) >= FIRST_FPR_REGNO && (N) <= LAST_SVP64FPR_REGNO) +/* SVP64 float-point register file extension. */ +#define SVP64_FPR_XREGNO_P(N) \ + (SVP64_FPR_REGNO_P (N) && !FP_REGNO_P (N)) +/* SVP64 condition register file. */ +#define SVP64_CR_REGNO_P(N) \ + ((N) >= FIRST_CR0_REGNO && (N) <= MAX_SVP64CR_REGNO) +/* SVP64 condition register file extension. */ +#define SVP64_CR_XREGNO_P(N) \ + (SVP64_CR_REGNO_P (N) && !CR_REGNO_P (N)) + /* When setting up caller-save slots (MODE == VOIDmode) ensure we allocate enough space to account for vectors in FP regs. However, TFmode/TDmode should not use VSX instructions to do a caller save. */ @@ -1092,10 +1192,10 @@ enum data_align { align_abi, align_opt, align_both }; #define HARD_FRAME_POINTER_REGNUM 31 /* Base register for access to local variables of the function. */ -// #define FRAME_POINTER_REGNUM 110 +// #define FRAME_POINTER_REGNUM 422 /* Base register for access to arguments of the function. */ -// #define ARG_POINTER_REGNUM 99 +// #define ARG_POINTER_REGNUM 291 /* Place to put static chain when calling a function that requires it. */ #define STATIC_CHAIN_REGNUM 11 @@ -1156,6 +1256,11 @@ enum reg_class CR_REGS, NON_FLOAT_REGS, CA_REGS, + SVP64_GENERAL_REGS, + SVP64_FLOAT_REGS, + SVP64_VL_REGS, + SVP64_CR_REGS, + SVP64_BITPRED_REGS, ALL_REGS, LIM_REG_CLASSES }; @@ -1185,6 +1290,11 @@ enum reg_class "CR_REGS", \ "NON_FLOAT_REGS", \ "CA_REGS", \ + "SVP64_GENERAL_REGS", \ + "SVP64_FLOAT_REGS", \ + "SVP64_VL_REGS", \ + "SVP64_CR_REGS", \ + "SVP64_BITPRED_REGS", \ "ALL_REGS" \ } @@ -1194,46 +1304,137 @@ enum reg_class #define REG_CLASS_CONTENTS \ { \ + /* layout: \ + 0xrrrrrrrr, 0xrrrrrrrr, 0xrrrrrrrr, 0xrrrrrrrr, \ + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, \ + 0xvvvvvvvv, 0xcccccccs, 0xcccccccc, 0xcccccccc, \ + 0xcccccccc, 0x000000sc }, \ + */ \ /* NO_REGS. */ \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ + 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ + 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ + 0x00000000, 0x00000000 }, \ /* BASE_REGS. */ \ - { 0xfffffffe, 0x00000000, 0x00000000, 0x00004008 }, \ + { 0xfffffffe, 0x00000000, 0x00000000, 0x00000000, \ + 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ + 0x00000000, 0x00000008, 0x00000000, 0x00000000, \ + 0x00000000, 0x00000040 }, \ /* GENERAL_REGS. */ \ - { 0xffffffff, 0x00000000, 0x00000000, 0x00004008 }, \ + { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, \ + 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ + 0x00000000, 0x00000008, 0x00000000, 0x00000000, \ + 0x00000000, 0x00000040 }, \ /* FLOAT_REGS. */ \ - { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ + 0xffffffff, 0x00000000, 0x00000000, 0x00000000, \ + 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ + 0x00000000, 0x00000000 }, \ /* ALTIVEC_REGS. */ \ - { 0x00000000, 0x00000000, 0xffffffff, 0x00000000 }, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ + 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ + 0xffffffff, 0x00000000, 0x00000000, 0x00000000, \ + 0x00000000, 0x00000000 }, \ /* VSX_REGS. */ \ - { 0x00000000, 0xffffffff, 0xffffffff, 0x00000000 }, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ + 0xffffffff, 0x00000000, 0x00000000, 0x00000000, \ + 0xffffffff, 0x00000000, 0x00000000, 0x00000000, \ + 0x00000000, 0x00000000 }, \ /* VRSAVE_REGS. */ \ - { 0x00000000, 0x00000000, 0x00000000, 0x00001000 }, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ + 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ + 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ + 0x00000000, 0x00000010 }, \ /* VSCR_REGS. */ \ - { 0x00000000, 0x00000000, 0x00000000, 0x00002000 }, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ + 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ + 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ + 0x00000000, 0x00000020 }, \ /* GEN_OR_FLOAT_REGS. */ \ - { 0xffffffff, 0xffffffff, 0x00000000, 0x00004008 }, \ + { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, \ + 0xffffffff, 0x00000000, 0x00000000, 0x00000000, \ + 0x00000000, 0x00000008, 0x00000000, 0x00000000, \ + 0x00000000, 0x00000040 }, \ /* GEN_OR_VSX_REGS. */ \ - { 0xffffffff, 0xffffffff, 0xffffffff, 0x00004008 }, \ + { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, \ + 0xffffffff, 0x00000000, 0x00000000, 0x00000000, \ + 0xffffffff, 0x00000008, 0x00000000, 0x00000000, \ + 0x00000000, 0x00000040 }, \ /* LINK_REGS. */ \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000001 }, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ + 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ + 0x00000000, 0x00000001, 0x00000000, 0x00000000, \ + 0x00000000, 0x00000000 }, \ /* CTR_REGS. */ \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000002 }, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ + 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ + 0x00000000, 0x00000002, 0x00000000, 0x00000000, \ + 0x00000000, 0x00000000 }, \ /* LINK_OR_CTR_REGS. */ \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000003 }, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ + 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ + 0x00000000, 0x00000003, 0x00000000, 0x00000000, \ + 0x00000000, 0x00000000 }, \ /* SPECIAL_REGS. */ \ - { 0x00000000, 0x00000000, 0x00000000, 0x00001003 }, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ + 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ + 0x00000000, 0x00000003, 0x00000000, 0x00000000, \ + 0x00000000, 0x00000010 }, \ /* SPEC_OR_GEN_REGS. */ \ - { 0xffffffff, 0x00000000, 0x00000000, 0x0000500b }, \ + { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, \ + 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ + 0x00000000, 0x0000000b, 0x00000000, 0x00000000, \ + 0x00000000, 0x00000050 }, \ /* CR0_REGS. */ \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000010 }, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ + 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ + 0x00000000, 0x00000010, 0x00000000, 0x00000000, \ + 0x00000000, 0x00000000 }, \ /* CR_REGS. */ \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000ff0 }, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ + 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ + 0x00000000, 0x00000ff0, 0x00000000, 0x00000000, \ + 0x00000000, 0x00000000 }, \ /* NON_FLOAT_REGS. */ \ - { 0xffffffff, 0x00000000, 0x00000000, 0x00004ffb }, \ + { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, \ + 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ + 0x00000000, 0xfffffffb, 0xffffffff, 0xffffffff, \ + 0xffffffff, 0x0000004f }, \ /* CA_REGS. */ \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000004 }, \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ + 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ + 0x00000000, 0x00000004, 0x00000000, 0x00000000, \ + 0x00000000, 0x00000000 }, \ + /* SVP64_GENERAL_REGS. */ \ + { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, \ + 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ + 0x00000000, 0x00000008, 0x00000000, 0x00000000, \ + 0x00000000, 0x00000040 }, \ + /* SVP64_FLOAT_REGS. */ \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, \ + 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ + 0x00000000, 0x00000000 }, \ + /* SVP64_VL_REGS. */ \ + { 0x40002008, 0x00000000, 0x00000000, 0x00000000, \ + 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ + 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ + 0x00000000, 0x00000080 }, \ + /* SVP64_CR_REGS. */ \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ + 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ + 0x00000000, 0xfffffff0, 0xffffffff, 0xffffffff, \ + 0xffffffff, 0x0000000f }, \ + /* SVP64_BITPRED_REGS. */ \ + { 0x40002008, 0x00000000, 0x00000000, 0x00000000, \ + 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ + 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ + 0x00000000, 0x00000000 }, \ /* ALL_REGS. */ \ - { 0xffffffff, 0xffffffff, 0xffffffff, 0x00007fff } \ + { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, \ + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, \ + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, \ + 0xffffffff, 0x000000ff }, \ } /* The same information, inverted: @@ -2047,144 +2248,535 @@ extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */ &rs6000_reg_names[29][0], /* r29 */ \ &rs6000_reg_names[30][0], /* r30 */ \ &rs6000_reg_names[31][0], /* r31 */ \ + &rs6000_reg_names[32][0], /* r32 */ \ + &rs6000_reg_names[33][0], /* r33 */ \ + &rs6000_reg_names[34][0], /* r34 */ \ + &rs6000_reg_names[35][0], /* r35 */ \ + &rs6000_reg_names[36][0], /* r36 */ \ + &rs6000_reg_names[37][0], /* r37 */ \ + &rs6000_reg_names[38][0], /* r38 */ \ + &rs6000_reg_names[39][0], /* r39 */ \ + &rs6000_reg_names[40][0], /* r40 */ \ + &rs6000_reg_names[41][0], /* r41 */ \ + &rs6000_reg_names[42][0], /* r42 */ \ + &rs6000_reg_names[43][0], /* r43 */ \ + &rs6000_reg_names[44][0], /* r44 */ \ + &rs6000_reg_names[45][0], /* r45 */ \ + &rs6000_reg_names[46][0], /* r46 */ \ + &rs6000_reg_names[47][0], /* r47 */ \ + &rs6000_reg_names[48][0], /* r48 */ \ + &rs6000_reg_names[49][0], /* r49 */ \ + &rs6000_reg_names[50][0], /* r50 */ \ + &rs6000_reg_names[51][0], /* r51 */ \ + &rs6000_reg_names[52][0], /* r52 */ \ + &rs6000_reg_names[53][0], /* r53 */ \ + &rs6000_reg_names[54][0], /* r54 */ \ + &rs6000_reg_names[55][0], /* r55 */ \ + &rs6000_reg_names[56][0], /* r56 */ \ + &rs6000_reg_names[57][0], /* r57 */ \ + &rs6000_reg_names[58][0], /* r58 */ \ + &rs6000_reg_names[59][0], /* r59 */ \ + &rs6000_reg_names[60][0], /* r60 */ \ + &rs6000_reg_names[61][0], /* r61 */ \ + &rs6000_reg_names[62][0], /* r62 */ \ + &rs6000_reg_names[63][0], /* r63 */ \ + &rs6000_reg_names[64][0], /* r64 */ \ + &rs6000_reg_names[65][0], /* r65 */ \ + &rs6000_reg_names[66][0], /* r66 */ \ + &rs6000_reg_names[67][0], /* r67 */ \ + &rs6000_reg_names[68][0], /* r68 */ \ + &rs6000_reg_names[69][0], /* r69 */ \ + &rs6000_reg_names[70][0], /* r70 */ \ + &rs6000_reg_names[71][0], /* r71 */ \ + &rs6000_reg_names[72][0], /* r72 */ \ + &rs6000_reg_names[73][0], /* r73 */ \ + &rs6000_reg_names[74][0], /* r74 */ \ + &rs6000_reg_names[75][0], /* r75 */ \ + &rs6000_reg_names[76][0], /* r76 */ \ + &rs6000_reg_names[77][0], /* r77 */ \ + &rs6000_reg_names[78][0], /* r78 */ \ + &rs6000_reg_names[79][0], /* r79 */ \ + &rs6000_reg_names[80][0], /* r80 */ \ + &rs6000_reg_names[81][0], /* r81 */ \ + &rs6000_reg_names[82][0], /* r82 */ \ + &rs6000_reg_names[83][0], /* r83 */ \ + &rs6000_reg_names[84][0], /* r84 */ \ + &rs6000_reg_names[85][0], /* r85 */ \ + &rs6000_reg_names[86][0], /* r86 */ \ + &rs6000_reg_names[87][0], /* r87 */ \ + &rs6000_reg_names[88][0], /* r88 */ \ + &rs6000_reg_names[89][0], /* r89 */ \ + &rs6000_reg_names[90][0], /* r90 */ \ + &rs6000_reg_names[91][0], /* r91 */ \ + &rs6000_reg_names[92][0], /* r92 */ \ + &rs6000_reg_names[93][0], /* r93 */ \ + &rs6000_reg_names[94][0], /* r94 */ \ + &rs6000_reg_names[95][0], /* r95 */ \ + &rs6000_reg_names[96][0], /* r96 */ \ + &rs6000_reg_names[97][0], /* r97 */ \ + &rs6000_reg_names[98][0], /* r98 */ \ + &rs6000_reg_names[99][0], /* r99 */ \ + &rs6000_reg_names[100][0], /* r100 */ \ + &rs6000_reg_names[101][0], /* r101 */ \ + &rs6000_reg_names[102][0], /* r102 */ \ + &rs6000_reg_names[103][0], /* r103 */ \ + &rs6000_reg_names[104][0], /* r104 */ \ + &rs6000_reg_names[105][0], /* r105 */ \ + &rs6000_reg_names[106][0], /* r106 */ \ + &rs6000_reg_names[107][0], /* r107 */ \ + &rs6000_reg_names[108][0], /* r108 */ \ + &rs6000_reg_names[109][0], /* r109 */ \ + &rs6000_reg_names[110][0], /* r110 */ \ + &rs6000_reg_names[111][0], /* r111 */ \ + &rs6000_reg_names[112][0], /* r112 */ \ + &rs6000_reg_names[113][0], /* r113 */ \ + &rs6000_reg_names[114][0], /* r114 */ \ + &rs6000_reg_names[115][0], /* r115 */ \ + &rs6000_reg_names[116][0], /* r116 */ \ + &rs6000_reg_names[117][0], /* r117 */ \ + &rs6000_reg_names[118][0], /* r118 */ \ + &rs6000_reg_names[119][0], /* r119 */ \ + &rs6000_reg_names[120][0], /* r120 */ \ + &rs6000_reg_names[121][0], /* r121 */ \ + &rs6000_reg_names[122][0], /* r122 */ \ + &rs6000_reg_names[123][0], /* r123 */ \ + &rs6000_reg_names[124][0], /* r124 */ \ + &rs6000_reg_names[125][0], /* r125 */ \ + &rs6000_reg_names[126][0], /* r126 */ \ + &rs6000_reg_names[127][0], /* r127 */ \ \ - &rs6000_reg_names[32][0], /* fr0 */ \ - &rs6000_reg_names[33][0], /* fr1 */ \ - &rs6000_reg_names[34][0], /* fr2 */ \ - &rs6000_reg_names[35][0], /* fr3 */ \ - &rs6000_reg_names[36][0], /* fr4 */ \ - &rs6000_reg_names[37][0], /* fr5 */ \ - &rs6000_reg_names[38][0], /* fr6 */ \ - &rs6000_reg_names[39][0], /* fr7 */ \ - &rs6000_reg_names[40][0], /* fr8 */ \ - &rs6000_reg_names[41][0], /* fr9 */ \ - &rs6000_reg_names[42][0], /* fr10 */ \ - &rs6000_reg_names[43][0], /* fr11 */ \ - &rs6000_reg_names[44][0], /* fr12 */ \ - &rs6000_reg_names[45][0], /* fr13 */ \ - &rs6000_reg_names[46][0], /* fr14 */ \ - &rs6000_reg_names[47][0], /* fr15 */ \ - &rs6000_reg_names[48][0], /* fr16 */ \ - &rs6000_reg_names[49][0], /* fr17 */ \ - &rs6000_reg_names[50][0], /* fr18 */ \ - &rs6000_reg_names[51][0], /* fr19 */ \ - &rs6000_reg_names[52][0], /* fr20 */ \ - &rs6000_reg_names[53][0], /* fr21 */ \ - &rs6000_reg_names[54][0], /* fr22 */ \ - &rs6000_reg_names[55][0], /* fr23 */ \ - &rs6000_reg_names[56][0], /* fr24 */ \ - &rs6000_reg_names[57][0], /* fr25 */ \ - &rs6000_reg_names[58][0], /* fr26 */ \ - &rs6000_reg_names[59][0], /* fr27 */ \ - &rs6000_reg_names[60][0], /* fr28 */ \ - &rs6000_reg_names[61][0], /* fr29 */ \ - &rs6000_reg_names[62][0], /* fr30 */ \ - &rs6000_reg_names[63][0], /* fr31 */ \ + &rs6000_reg_names[128][0], /* fr0 */ \ + &rs6000_reg_names[129][0], /* fr1 */ \ + &rs6000_reg_names[130][0], /* fr2 */ \ + &rs6000_reg_names[131][0], /* fr3 */ \ + &rs6000_reg_names[132][0], /* fr4 */ \ + &rs6000_reg_names[133][0], /* fr5 */ \ + &rs6000_reg_names[134][0], /* fr6 */ \ + &rs6000_reg_names[135][0], /* fr7 */ \ + &rs6000_reg_names[136][0], /* fr8 */ \ + &rs6000_reg_names[137][0], /* fr9 */ \ + &rs6000_reg_names[138][0], /* fr10 */ \ + &rs6000_reg_names[139][0], /* fr11 */ \ + &rs6000_reg_names[140][0], /* fr12 */ \ + &rs6000_reg_names[141][0], /* fr13 */ \ + &rs6000_reg_names[142][0], /* fr14 */ \ + &rs6000_reg_names[143][0], /* fr15 */ \ + &rs6000_reg_names[144][0], /* fr16 */ \ + &rs6000_reg_names[145][0], /* fr17 */ \ + &rs6000_reg_names[146][0], /* fr18 */ \ + &rs6000_reg_names[147][0], /* fr19 */ \ + &rs6000_reg_names[148][0], /* fr20 */ \ + &rs6000_reg_names[149][0], /* fr21 */ \ + &rs6000_reg_names[150][0], /* fr22 */ \ + &rs6000_reg_names[151][0], /* fr23 */ \ + &rs6000_reg_names[152][0], /* fr24 */ \ + &rs6000_reg_names[153][0], /* fr25 */ \ + &rs6000_reg_names[154][0], /* fr26 */ \ + &rs6000_reg_names[155][0], /* fr27 */ \ + &rs6000_reg_names[156][0], /* fr28 */ \ + &rs6000_reg_names[157][0], /* fr29 */ \ + &rs6000_reg_names[158][0], /* fr30 */ \ + &rs6000_reg_names[159][0], /* fr31 */ \ + &rs6000_reg_names[160][0], /* fr32 */ \ + &rs6000_reg_names[161][0], /* fr33 */ \ + &rs6000_reg_names[162][0], /* fr34 */ \ + &rs6000_reg_names[163][0], /* fr35 */ \ + &rs6000_reg_names[164][0], /* fr36 */ \ + &rs6000_reg_names[165][0], /* fr37 */ \ + &rs6000_reg_names[166][0], /* fr38 */ \ + &rs6000_reg_names[167][0], /* fr39 */ \ + &rs6000_reg_names[168][0], /* fr40 */ \ + &rs6000_reg_names[169][0], /* fr41 */ \ + &rs6000_reg_names[170][0], /* fr42 */ \ + &rs6000_reg_names[171][0], /* fr43 */ \ + &rs6000_reg_names[172][0], /* fr44 */ \ + &rs6000_reg_names[173][0], /* fr45 */ \ + &rs6000_reg_names[174][0], /* fr46 */ \ + &rs6000_reg_names[175][0], /* fr47 */ \ + &rs6000_reg_names[176][0], /* fr48 */ \ + &rs6000_reg_names[177][0], /* fr49 */ \ + &rs6000_reg_names[178][0], /* fr50 */ \ + &rs6000_reg_names[179][0], /* fr51 */ \ + &rs6000_reg_names[180][0], /* fr52 */ \ + &rs6000_reg_names[181][0], /* fr53 */ \ + &rs6000_reg_names[182][0], /* fr54 */ \ + &rs6000_reg_names[183][0], /* fr55 */ \ + &rs6000_reg_names[184][0], /* fr56 */ \ + &rs6000_reg_names[185][0], /* fr57 */ \ + &rs6000_reg_names[186][0], /* fr58 */ \ + &rs6000_reg_names[187][0], /* fr59 */ \ + &rs6000_reg_names[188][0], /* fr60 */ \ + &rs6000_reg_names[189][0], /* fr61 */ \ + &rs6000_reg_names[190][0], /* fr62 */ \ + &rs6000_reg_names[191][0], /* fr63 */ \ + &rs6000_reg_names[192][0], /* fr64 */ \ + &rs6000_reg_names[193][0], /* fr65 */ \ + &rs6000_reg_names[194][0], /* fr66 */ \ + &rs6000_reg_names[195][0], /* fr67 */ \ + &rs6000_reg_names[196][0], /* fr68 */ \ + &rs6000_reg_names[197][0], /* fr69 */ \ + &rs6000_reg_names[198][0], /* fr70 */ \ + &rs6000_reg_names[199][0], /* fr71 */ \ + &rs6000_reg_names[200][0], /* fr72 */ \ + &rs6000_reg_names[201][0], /* fr73 */ \ + &rs6000_reg_names[202][0], /* fr74 */ \ + &rs6000_reg_names[203][0], /* fr75 */ \ + &rs6000_reg_names[204][0], /* fr76 */ \ + &rs6000_reg_names[205][0], /* fr77 */ \ + &rs6000_reg_names[206][0], /* fr78 */ \ + &rs6000_reg_names[207][0], /* fr79 */ \ + &rs6000_reg_names[208][0], /* fr80 */ \ + &rs6000_reg_names[209][0], /* fr81 */ \ + &rs6000_reg_names[210][0], /* fr82 */ \ + &rs6000_reg_names[211][0], /* fr83 */ \ + &rs6000_reg_names[212][0], /* fr84 */ \ + &rs6000_reg_names[213][0], /* fr85 */ \ + &rs6000_reg_names[214][0], /* fr86 */ \ + &rs6000_reg_names[215][0], /* fr87 */ \ + &rs6000_reg_names[216][0], /* fr88 */ \ + &rs6000_reg_names[217][0], /* fr89 */ \ + &rs6000_reg_names[218][0], /* fr90 */ \ + &rs6000_reg_names[219][0], /* fr91 */ \ + &rs6000_reg_names[220][0], /* fr92 */ \ + &rs6000_reg_names[221][0], /* fr93 */ \ + &rs6000_reg_names[222][0], /* fr94 */ \ + &rs6000_reg_names[223][0], /* fr95 */ \ + &rs6000_reg_names[224][0], /* fr96 */ \ + &rs6000_reg_names[225][0], /* fr97 */ \ + &rs6000_reg_names[226][0], /* fr98 */ \ + &rs6000_reg_names[227][0], /* fr99 */ \ + &rs6000_reg_names[228][0], /* fr100 */ \ + &rs6000_reg_names[229][0], /* fr101 */ \ + &rs6000_reg_names[230][0], /* fr102 */ \ + &rs6000_reg_names[231][0], /* fr103 */ \ + &rs6000_reg_names[232][0], /* fr104 */ \ + &rs6000_reg_names[233][0], /* fr105 */ \ + &rs6000_reg_names[234][0], /* fr106 */ \ + &rs6000_reg_names[235][0], /* fr107 */ \ + &rs6000_reg_names[236][0], /* fr108 */ \ + &rs6000_reg_names[237][0], /* fr109 */ \ + &rs6000_reg_names[238][0], /* fr110 */ \ + &rs6000_reg_names[239][0], /* fr111 */ \ + &rs6000_reg_names[240][0], /* fr112 */ \ + &rs6000_reg_names[241][0], /* fr113 */ \ + &rs6000_reg_names[242][0], /* fr114 */ \ + &rs6000_reg_names[243][0], /* fr115 */ \ + &rs6000_reg_names[244][0], /* fr116 */ \ + &rs6000_reg_names[245][0], /* fr117 */ \ + &rs6000_reg_names[246][0], /* fr118 */ \ + &rs6000_reg_names[247][0], /* fr119 */ \ + &rs6000_reg_names[248][0], /* fr120 */ \ + &rs6000_reg_names[249][0], /* fr121 */ \ + &rs6000_reg_names[250][0], /* fr122 */ \ + &rs6000_reg_names[251][0], /* fr123 */ \ + &rs6000_reg_names[252][0], /* fr124 */ \ + &rs6000_reg_names[253][0], /* fr125 */ \ + &rs6000_reg_names[254][0], /* fr126 */ \ + &rs6000_reg_names[255][0], /* fr127 */ \ \ - &rs6000_reg_names[64][0], /* vr0 */ \ - &rs6000_reg_names[65][0], /* vr1 */ \ - &rs6000_reg_names[66][0], /* vr2 */ \ - &rs6000_reg_names[67][0], /* vr3 */ \ - &rs6000_reg_names[68][0], /* vr4 */ \ - &rs6000_reg_names[69][0], /* vr5 */ \ - &rs6000_reg_names[70][0], /* vr6 */ \ - &rs6000_reg_names[71][0], /* vr7 */ \ - &rs6000_reg_names[72][0], /* vr8 */ \ - &rs6000_reg_names[73][0], /* vr9 */ \ - &rs6000_reg_names[74][0], /* vr10 */ \ - &rs6000_reg_names[75][0], /* vr11 */ \ - &rs6000_reg_names[76][0], /* vr12 */ \ - &rs6000_reg_names[77][0], /* vr13 */ \ - &rs6000_reg_names[78][0], /* vr14 */ \ - &rs6000_reg_names[79][0], /* vr15 */ \ - &rs6000_reg_names[80][0], /* vr16 */ \ - &rs6000_reg_names[81][0], /* vr17 */ \ - &rs6000_reg_names[82][0], /* vr18 */ \ - &rs6000_reg_names[83][0], /* vr19 */ \ - &rs6000_reg_names[84][0], /* vr20 */ \ - &rs6000_reg_names[85][0], /* vr21 */ \ - &rs6000_reg_names[86][0], /* vr22 */ \ - &rs6000_reg_names[87][0], /* vr23 */ \ - &rs6000_reg_names[88][0], /* vr24 */ \ - &rs6000_reg_names[89][0], /* vr25 */ \ - &rs6000_reg_names[90][0], /* vr26 */ \ - &rs6000_reg_names[91][0], /* vr27 */ \ - &rs6000_reg_names[92][0], /* vr28 */ \ - &rs6000_reg_names[93][0], /* vr29 */ \ - &rs6000_reg_names[94][0], /* vr30 */ \ - &rs6000_reg_names[95][0], /* vr31 */ \ + &rs6000_reg_names[256][0], /* vr0 */ \ + &rs6000_reg_names[257][0], /* vr1 */ \ + &rs6000_reg_names[258][0], /* vr2 */ \ + &rs6000_reg_names[259][0], /* vr3 */ \ + &rs6000_reg_names[260][0], /* vr4 */ \ + &rs6000_reg_names[261][0], /* vr5 */ \ + &rs6000_reg_names[262][0], /* vr6 */ \ + &rs6000_reg_names[263][0], /* vr7 */ \ + &rs6000_reg_names[264][0], /* vr8 */ \ + &rs6000_reg_names[265][0], /* vr9 */ \ + &rs6000_reg_names[266][0], /* vr10 */ \ + &rs6000_reg_names[267][0], /* vr11 */ \ + &rs6000_reg_names[268][0], /* vr12 */ \ + &rs6000_reg_names[269][0], /* vr13 */ \ + &rs6000_reg_names[270][0], /* vr14 */ \ + &rs6000_reg_names[271][0], /* vr15 */ \ + &rs6000_reg_names[272][0], /* vr16 */ \ + &rs6000_reg_names[273][0], /* vr17 */ \ + &rs6000_reg_names[274][0], /* vr18 */ \ + &rs6000_reg_names[275][0], /* vr19 */ \ + &rs6000_reg_names[276][0], /* vr20 */ \ + &rs6000_reg_names[277][0], /* vr21 */ \ + &rs6000_reg_names[278][0], /* vr22 */ \ + &rs6000_reg_names[279][0], /* vr23 */ \ + &rs6000_reg_names[280][0], /* vr24 */ \ + &rs6000_reg_names[281][0], /* vr25 */ \ + &rs6000_reg_names[282][0], /* vr26 */ \ + &rs6000_reg_names[283][0], /* vr27 */ \ + &rs6000_reg_names[284][0], /* vr28 */ \ + &rs6000_reg_names[285][0], /* vr29 */ \ + &rs6000_reg_names[286][0], /* vr30 */ \ + &rs6000_reg_names[287][0], /* vr31 */ \ \ - &rs6000_reg_names[96][0], /* lr */ \ - &rs6000_reg_names[97][0], /* ctr */ \ - &rs6000_reg_names[98][0], /* ca */ \ - &rs6000_reg_names[99][0], /* ap */ \ + &rs6000_reg_names[288][0], /* lr */ \ + &rs6000_reg_names[289][0], /* ctr */ \ + &rs6000_reg_names[290][0], /* ca */ \ + &rs6000_reg_names[291][0], /* ap */ \ \ - &rs6000_reg_names[100][0], /* cr0 */ \ - &rs6000_reg_names[101][0], /* cr1 */ \ - &rs6000_reg_names[102][0], /* cr2 */ \ - &rs6000_reg_names[103][0], /* cr3 */ \ - &rs6000_reg_names[104][0], /* cr4 */ \ - &rs6000_reg_names[105][0], /* cr5 */ \ - &rs6000_reg_names[106][0], /* cr6 */ \ - &rs6000_reg_names[107][0], /* cr7 */ \ + &rs6000_reg_names[292][0], /* cr0 */ \ + &rs6000_reg_names[293][0], /* cr1 */ \ + &rs6000_reg_names[294][0], /* cr2 */ \ + &rs6000_reg_names[295][0], /* cr3 */ \ + &rs6000_reg_names[296][0], /* cr4 */ \ + &rs6000_reg_names[297][0], /* cr5 */ \ + &rs6000_reg_names[298][0], /* cr6 */ \ + &rs6000_reg_names[299][0], /* cr7 */ \ + &rs6000_reg_names[300][0], /* cr8 */ \ + &rs6000_reg_names[301][0], /* cr9 */ \ + &rs6000_reg_names[302][0], /* cr10 */ \ + &rs6000_reg_names[303][0], /* cr11 */ \ + &rs6000_reg_names[304][0], /* cr12 */ \ + &rs6000_reg_names[305][0], /* cr13 */ \ + &rs6000_reg_names[306][0], /* cr14 */ \ + &rs6000_reg_names[307][0], /* cr15 */ \ + &rs6000_reg_names[308][0], /* cr16 */ \ + &rs6000_reg_names[309][0], /* cr17 */ \ + &rs6000_reg_names[310][0], /* cr18 */ \ + &rs6000_reg_names[311][0], /* cr19 */ \ + &rs6000_reg_names[312][0], /* cr20 */ \ + &rs6000_reg_names[313][0], /* cr21 */ \ + &rs6000_reg_names[314][0], /* cr22 */ \ + &rs6000_reg_names[315][0], /* cr23 */ \ + &rs6000_reg_names[316][0], /* cr24 */ \ + &rs6000_reg_names[317][0], /* cr25 */ \ + &rs6000_reg_names[318][0], /* cr26 */ \ + &rs6000_reg_names[319][0], /* cr27 */ \ + &rs6000_reg_names[320][0], /* cr28 */ \ + &rs6000_reg_names[321][0], /* cr29 */ \ + &rs6000_reg_names[322][0], /* cr30 */ \ + &rs6000_reg_names[323][0], /* cr31 */ \ + &rs6000_reg_names[324][0], /* cr32 */ \ + &rs6000_reg_names[325][0], /* cr33 */ \ + &rs6000_reg_names[326][0], /* cr34 */ \ + &rs6000_reg_names[327][0], /* cr35 */ \ + &rs6000_reg_names[328][0], /* cr36 */ \ + &rs6000_reg_names[329][0], /* cr37 */ \ + &rs6000_reg_names[330][0], /* cr38 */ \ + &rs6000_reg_names[331][0], /* cr39 */ \ + &rs6000_reg_names[332][0], /* cr40 */ \ + &rs6000_reg_names[333][0], /* cr41 */ \ + &rs6000_reg_names[334][0], /* cr42 */ \ + &rs6000_reg_names[335][0], /* cr43 */ \ + &rs6000_reg_names[336][0], /* cr44 */ \ + &rs6000_reg_names[337][0], /* cr45 */ \ + &rs6000_reg_names[338][0], /* cr46 */ \ + &rs6000_reg_names[339][0], /* cr47 */ \ + &rs6000_reg_names[340][0], /* cr48 */ \ + &rs6000_reg_names[341][0], /* cr49 */ \ + &rs6000_reg_names[342][0], /* cr50 */ \ + &rs6000_reg_names[343][0], /* cr51 */ \ + &rs6000_reg_names[344][0], /* cr52 */ \ + &rs6000_reg_names[345][0], /* cr53 */ \ + &rs6000_reg_names[346][0], /* cr54 */ \ + &rs6000_reg_names[347][0], /* cr55 */ \ + &rs6000_reg_names[348][0], /* cr56 */ \ + &rs6000_reg_names[349][0], /* cr57 */ \ + &rs6000_reg_names[350][0], /* cr58 */ \ + &rs6000_reg_names[351][0], /* cr59 */ \ + &rs6000_reg_names[352][0], /* cr60 */ \ + &rs6000_reg_names[353][0], /* cr61 */ \ + &rs6000_reg_names[354][0], /* cr62 */ \ + &rs6000_reg_names[355][0], /* cr63 */ \ + &rs6000_reg_names[356][0], /* cr64 */ \ + &rs6000_reg_names[357][0], /* cr65 */ \ + &rs6000_reg_names[358][0], /* cr66 */ \ + &rs6000_reg_names[359][0], /* cr67 */ \ + &rs6000_reg_names[360][0], /* cr68 */ \ + &rs6000_reg_names[361][0], /* cr69 */ \ + &rs6000_reg_names[362][0], /* cr70 */ \ + &rs6000_reg_names[363][0], /* cr71 */ \ + &rs6000_reg_names[364][0], /* cr72 */ \ + &rs6000_reg_names[365][0], /* cr73 */ \ + &rs6000_reg_names[366][0], /* cr74 */ \ + &rs6000_reg_names[367][0], /* cr75 */ \ + &rs6000_reg_names[368][0], /* cr76 */ \ + &rs6000_reg_names[369][0], /* cr77 */ \ + &rs6000_reg_names[370][0], /* cr78 */ \ + &rs6000_reg_names[371][0], /* cr79 */ \ + &rs6000_reg_names[372][0], /* cr80 */ \ + &rs6000_reg_names[373][0], /* cr81 */ \ + &rs6000_reg_names[374][0], /* cr82 */ \ + &rs6000_reg_names[375][0], /* cr83 */ \ + &rs6000_reg_names[376][0], /* cr84 */ \ + &rs6000_reg_names[377][0], /* cr85 */ \ + &rs6000_reg_names[378][0], /* cr86 */ \ + &rs6000_reg_names[379][0], /* cr87 */ \ + &rs6000_reg_names[380][0], /* cr88 */ \ + &rs6000_reg_names[381][0], /* cr89 */ \ + &rs6000_reg_names[382][0], /* cr90 */ \ + &rs6000_reg_names[383][0], /* cr91 */ \ + &rs6000_reg_names[384][0], /* cr92 */ \ + &rs6000_reg_names[385][0], /* cr93 */ \ + &rs6000_reg_names[386][0], /* cr94 */ \ + &rs6000_reg_names[387][0], /* cr95 */ \ + &rs6000_reg_names[388][0], /* cr96 */ \ + &rs6000_reg_names[389][0], /* cr97 */ \ + &rs6000_reg_names[390][0], /* cr98 */ \ + &rs6000_reg_names[391][0], /* cr99 */ \ + &rs6000_reg_names[392][0], /* cr100 */ \ + &rs6000_reg_names[393][0], /* cr101 */ \ + &rs6000_reg_names[394][0], /* cr102 */ \ + &rs6000_reg_names[395][0], /* cr103 */ \ + &rs6000_reg_names[396][0], /* cr104 */ \ + &rs6000_reg_names[397][0], /* cr105 */ \ + &rs6000_reg_names[398][0], /* cr106 */ \ + &rs6000_reg_names[399][0], /* cr107 */ \ + &rs6000_reg_names[400][0], /* cr108 */ \ + &rs6000_reg_names[401][0], /* cr109 */ \ + &rs6000_reg_names[402][0], /* cr110 */ \ + &rs6000_reg_names[403][0], /* cr111 */ \ + &rs6000_reg_names[404][0], /* cr112 */ \ + &rs6000_reg_names[405][0], /* cr113 */ \ + &rs6000_reg_names[406][0], /* cr114 */ \ + &rs6000_reg_names[407][0], /* cr115 */ \ + &rs6000_reg_names[408][0], /* cr116 */ \ + &rs6000_reg_names[409][0], /* cr117 */ \ + &rs6000_reg_names[410][0], /* cr118 */ \ + &rs6000_reg_names[411][0], /* cr119 */ \ + &rs6000_reg_names[412][0], /* cr120 */ \ + &rs6000_reg_names[413][0], /* cr121 */ \ + &rs6000_reg_names[414][0], /* cr122 */ \ + &rs6000_reg_names[415][0], /* cr123 */ \ + &rs6000_reg_names[416][0], /* cr124 */ \ + &rs6000_reg_names[417][0], /* cr125 */ \ + &rs6000_reg_names[418][0], /* cr126 */ \ + &rs6000_reg_names[419][0], /* cr127 */ \ \ - &rs6000_reg_names[108][0], /* vrsave */ \ - &rs6000_reg_names[109][0], /* vscr */ \ + &rs6000_reg_names[420][0], /* vrsave */ \ + &rs6000_reg_names[421][0], /* vscr */ \ \ - &rs6000_reg_names[110][0] /* sfp */ \ + &rs6000_reg_names[422][0], /* sfp */ \ + &rs6000_reg_names[423][0], /* vl */ \ } /* Table of additional register names to use in user input. */ #define ADDITIONAL_REGISTER_NAMES \ - {{"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3}, \ - {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7}, \ - {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11}, \ - {"r12", 12}, {"r13", 13}, {"r14", 14}, {"r15", 15}, \ - {"r16", 16}, {"r17", 17}, {"r18", 18}, {"r19", 19}, \ - {"r20", 20}, {"r21", 21}, {"r22", 22}, {"r23", 23}, \ - {"r24", 24}, {"r25", 25}, {"r26", 26}, {"r27", 27}, \ - {"r28", 28}, {"r29", 29}, {"r30", 30}, {"r31", 31}, \ - {"fr0", 32}, {"fr1", 33}, {"fr2", 34}, {"fr3", 35}, \ - {"fr4", 36}, {"fr5", 37}, {"fr6", 38}, {"fr7", 39}, \ - {"fr8", 40}, {"fr9", 41}, {"fr10", 42}, {"fr11", 43}, \ - {"fr12", 44}, {"fr13", 45}, {"fr14", 46}, {"fr15", 47}, \ - {"fr16", 48}, {"fr17", 49}, {"fr18", 50}, {"fr19", 51}, \ - {"fr20", 52}, {"fr21", 53}, {"fr22", 54}, {"fr23", 55}, \ - {"fr24", 56}, {"fr25", 57}, {"fr26", 58}, {"fr27", 59}, \ - {"fr28", 60}, {"fr29", 61}, {"fr30", 62}, {"fr31", 63}, \ - {"v0", 64}, {"v1", 65}, {"v2", 66}, {"v3", 67}, \ - {"v4", 68}, {"v5", 69}, {"v6", 70}, {"v7", 71}, \ - {"v8", 72}, {"v9", 73}, {"v10", 74}, {"v11", 75}, \ - {"v12", 76}, {"v13", 77}, {"v14", 78}, {"v15", 79}, \ - {"v16", 80}, {"v17", 81}, {"v18", 82}, {"v19", 83}, \ - {"v20", 84}, {"v21", 85}, {"v22", 86}, {"v23", 87}, \ - {"v24", 88}, {"v25", 89}, {"v26", 90}, {"v27", 91}, \ - {"v28", 92}, {"v29", 93}, {"v30", 94}, {"v31", 95}, \ - {"vrsave", 108}, {"vscr", 109}, \ - /* no additional names for: lr, ctr, ap */ \ - {"cr0", 100},{"cr1", 101},{"cr2", 102},{"cr3", 103}, \ - {"cr4", 104},{"cr5", 105},{"cr6", 106},{"cr7", 107}, \ - {"cc", 100},{"sp", 1}, {"toc", 2}, \ + {{"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3}, \ + {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7}, \ + {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11}, \ + {"r12", 12}, {"r13", 13}, {"r14", 14}, {"r15", 15}, \ + {"r16", 16}, {"r17", 17}, {"r18", 18}, {"r19", 19}, \ + {"r20", 20}, {"r21", 21}, {"r22", 22}, {"r23", 23}, \ + {"r24", 24}, {"r25", 25}, {"r26", 26}, {"r27", 27}, \ + {"r28", 28}, {"r29", 29}, {"r30", 30}, {"r31", 31}, \ + {"r32", 32}, {"r33", 33}, {"r34", 34}, {"r35", 35}, \ + {"r36", 36}, {"r37", 37}, {"r38", 38}, {"r39", 39}, \ + {"r40", 40}, {"r41", 41}, {"r42", 42}, {"r43", 43}, \ + {"r44", 44}, {"r45", 45}, {"r46", 46}, {"r47", 47}, \ + {"r48", 48}, {"r49", 49}, {"r50", 50}, {"r51", 51}, \ + {"r52", 52}, {"r53", 53}, {"r54", 54}, {"r55", 55}, \ + {"r56", 56}, {"r57", 57}, {"r58", 58}, {"r59", 59}, \ + {"r60", 60}, {"r61", 61}, {"r62", 62}, {"r63", 63}, \ + {"r64", 64}, {"r65", 65}, {"r66", 66}, {"r67", 67}, \ + {"r68", 68}, {"r69", 69}, {"r70", 70}, {"r71", 71}, \ + {"r72", 72}, {"r73", 73}, {"r74", 74}, {"r75", 75}, \ + {"r76", 76}, {"r77", 77}, {"r78", 78}, {"r79", 79}, \ + {"r80", 80}, {"r81", 81}, {"r82", 82}, {"r83", 83}, \ + {"r84", 84}, {"r85", 85}, {"r86", 86}, {"r87", 87}, \ + {"r88", 88}, {"r89", 89}, {"r90", 90}, {"r91", 91}, \ + {"r92", 92}, {"r93", 93}, {"r94", 94}, {"r95", 95}, \ + {"r96", 96}, {"r97", 97}, {"r98", 98}, {"r99", 99}, \ + {"r100", 100}, {"r101", 101}, {"r102", 102}, {"r103", 103}, \ + {"r104", 104}, {"r105", 105}, {"r106", 106}, {"r107", 107}, \ + {"r108", 108}, {"r109", 109}, {"r110", 110}, {"r111", 111}, \ + {"r112", 112}, {"r113", 113}, {"r114", 114}, {"r115", 115}, \ + {"r116", 116}, {"r117", 117}, {"r118", 118}, {"r119", 119}, \ + {"r120", 120}, {"r121", 121}, {"r122", 122}, {"r123", 123}, \ + {"r124", 124}, {"r125", 125}, {"r126", 126}, {"r127", 127}, \ + {"fr0", 128}, {"fr1", 129}, {"fr2", 130}, {"fr3", 131}, \ + {"fr4", 132}, {"fr5", 133}, {"fr6", 134}, {"fr7", 135}, \ + {"fr8", 136}, {"fr9", 137}, {"fr10", 138}, {"fr11", 139}, \ + {"fr12", 140}, {"fr13", 141}, {"fr14", 142}, {"fr15", 143}, \ + {"fr16", 144}, {"fr17", 145}, {"fr18", 146}, {"fr19", 147}, \ + {"fr20", 148}, {"fr21", 149}, {"fr22", 150}, {"fr23", 151}, \ + {"fr24", 152}, {"fr25", 153}, {"fr26", 154}, {"fr27", 155}, \ + {"fr28", 156}, {"fr29", 157}, {"fr30", 158}, {"fr31", 159}, \ + {"fr32", 160}, {"fr33", 161}, {"fr34", 162}, {"fr35", 163}, \ + {"fr36", 164}, {"fr37", 165}, {"fr38", 166}, {"fr39", 167}, \ + {"fr40", 168}, {"fr41", 169}, {"fr42", 170}, {"fr43", 171}, \ + {"fr44", 172}, {"fr45", 173}, {"fr46", 174}, {"fr47", 175}, \ + {"fr48", 176}, {"fr49", 177}, {"fr50", 178}, {"fr51", 179}, \ + {"fr52", 180}, {"fr53", 181}, {"fr54", 182}, {"fr55", 183}, \ + {"fr56", 184}, {"fr57", 185}, {"fr58", 186}, {"fr59", 187}, \ + {"fr60", 188}, {"fr61", 189}, {"fr62", 190}, {"fr63", 191}, \ + {"fr64", 192}, {"fr65", 193}, {"fr66", 194}, {"fr67", 195}, \ + {"fr68", 196}, {"fr69", 197}, {"fr70", 198}, {"fr71", 199}, \ + {"fr72", 200}, {"fr73", 201}, {"fr74", 202}, {"fr75", 203}, \ + {"fr76", 204}, {"fr77", 205}, {"fr78", 206}, {"fr79", 207}, \ + {"fr80", 208}, {"fr81", 209}, {"fr82", 210}, {"fr83", 211}, \ + {"fr84", 212}, {"fr85", 213}, {"fr86", 214}, {"fr87", 215}, \ + {"fr88", 216}, {"fr89", 217}, {"fr90", 218}, {"fr91", 219}, \ + {"fr92", 220}, {"fr93", 221}, {"fr94", 222}, {"fr95", 223}, \ + {"fr96", 224}, {"fr97", 225}, {"fr98", 226}, {"fr99", 227}, \ + {"fr100",228}, {"fr101",229}, {"fr102",230}, {"fr103",231}, \ + {"fr104",232}, {"fr105",233}, {"fr106",234}, {"fr107",235}, \ + {"fr108",236}, {"fr109",237}, {"fr110",238}, {"fr111",239}, \ + {"fr112",240}, {"fr113",241}, {"fr114",242}, {"fr115",243}, \ + {"fr116",244}, {"fr117",245}, {"fr118",246}, {"fr119",247}, \ + {"fr120",248}, {"fr121",249}, {"fr122",250}, {"fr123",251}, \ + {"fr124",252}, {"fr125",253}, {"fr126",254}, {"fr127",255}, \ + {"v0", 256}, {"v1", 257}, {"v2", 258}, {"v3", 259}, \ + {"v4", 260}, {"v5", 261}, {"v6", 262}, {"v7", 263}, \ + {"v8", 264}, {"v9", 265}, {"v10", 266}, {"v11", 267}, \ + {"v12", 268}, {"v13", 269}, {"v14", 270}, {"v15", 271}, \ + {"v16", 272}, {"v17", 273}, {"v18", 274}, {"v19", 275}, \ + {"v20", 276}, {"v21", 277}, {"v22", 278}, {"v23", 279}, \ + {"v24", 280}, {"v25", 281}, {"v26", 282}, {"v27", 283}, \ + {"v28", 284}, {"v29", 285}, {"v30", 286}, {"v31", 287}, \ + {"vrsave", 356}, {"vscr", 357}, \ /* CA is only part of XER, but we do not model the other parts (yet). */ \ - {"xer", 98}, \ + {"xer", 290}, \ + {"cc", 292}, {"sp", 1}, {"toc", 2}, \ + /* no additional names for: lr, ctr, ap */ \ + {"cr0", 292}, {"cr1", 293}, {"cr2", 294}, {"cr3", 295}, \ + {"cr4", 296}, {"cr5", 297}, {"cr6", 298}, {"cr7", 299}, \ + {"cr8", 300}, {"cr9", 301}, {"cr10", 302}, {"cr11", 303}, \ + {"cr12", 304}, {"cr13", 305}, {"cr14", 306}, {"cr15", 307}, \ + {"cr16", 308}, {"cr17", 309}, {"cr18", 310}, {"cr19", 311}, \ + {"cr20", 312}, {"cr21", 313}, {"cr22", 314}, {"cr23", 315}, \ + {"cr24", 316}, {"cr25", 317}, {"cr26", 318}, {"cr27", 319}, \ + {"cr28", 320}, {"cr29", 321}, {"cr30", 322}, {"cr31", 323}, \ + {"cr32", 324}, {"cr33", 325}, {"cr34", 326}, {"cr35", 327}, \ + {"cr36", 328}, {"cr37", 329}, {"cr38", 330}, {"cr39", 331}, \ + {"cr40", 332}, {"cr41", 333}, {"cr42", 334}, {"cr43", 335}, \ + {"cr44", 336}, {"cr45", 337}, {"cr46", 338}, {"cr47", 339}, \ + {"cr48", 340}, {"cr49", 341}, {"cr50", 342}, {"cr51", 343}, \ + {"cr52", 344}, {"cr53", 345}, {"cr54", 346}, {"cr55", 347}, \ + {"cr56", 348}, {"cr57", 349}, {"cr58", 350}, {"cr59", 351}, \ + {"cr60", 352}, {"cr61", 353}, {"cr62", 354}, {"cr63", 355}, \ + {"cr64", 356}, {"cr65", 357}, {"cr66", 358}, {"cr67", 359}, \ + {"cr68", 360}, {"cr69", 361}, {"cr70", 362}, {"cr71", 363}, \ + {"cr72", 364}, {"cr73", 365}, {"cr74", 366}, {"cr75", 367}, \ + {"cr76", 368}, {"cr77", 369}, {"cr78", 370}, {"cr79", 371}, \ + {"cr80", 372}, {"cr81", 373}, {"cr82", 374}, {"cr83", 375}, \ + {"cr84", 376}, {"cr85", 377}, {"cr86", 378}, {"cr87", 379}, \ + {"cr88", 380}, {"cr89", 381}, {"cr90", 382}, {"cr91", 383}, \ + {"cr92", 384}, {"cr93", 385}, {"cr94", 386}, {"cr95", 387}, \ + {"cr96", 388}, {"cr97", 389}, {"cr98", 390}, {"cr99", 391}, \ + {"cr100",392}, {"cr101",393}, {"cr102",394}, {"cr103",395}, \ + {"cr104",396}, {"cr105",397}, {"cr106",398}, {"cr107",399}, \ + {"cr108",400}, {"cr109",401}, {"cr110",402}, {"cr111",403}, \ + {"cr112",404}, {"cr113",405}, {"cr114",406}, {"cr115",407}, \ + {"cr116",408}, {"cr117",409}, {"cr118",410}, {"cr119",411}, \ + {"cr120",412}, {"cr121",413}, {"cr122",414}, {"cr123",415}, \ + {"cr124",416}, {"cr125",417}, {"cr126",418}, {"cr127",419}, \ /* VSX registers overlaid on top of FR, Altivec registers */ \ - {"vs0", 32}, {"vs1", 33}, {"vs2", 34}, {"vs3", 35}, \ - {"vs4", 36}, {"vs5", 37}, {"vs6", 38}, {"vs7", 39}, \ - {"vs8", 40}, {"vs9", 41}, {"vs10", 42}, {"vs11", 43}, \ - {"vs12", 44}, {"vs13", 45}, {"vs14", 46}, {"vs15", 47}, \ - {"vs16", 48}, {"vs17", 49}, {"vs18", 50}, {"vs19", 51}, \ - {"vs20", 52}, {"vs21", 53}, {"vs22", 54}, {"vs23", 55}, \ - {"vs24", 56}, {"vs25", 57}, {"vs26", 58}, {"vs27", 59}, \ - {"vs28", 60}, {"vs29", 61}, {"vs30", 62}, {"vs31", 63}, \ - {"vs32", 64}, {"vs33", 65}, {"vs34", 66}, {"vs35", 67}, \ - {"vs36", 68}, {"vs37", 69}, {"vs38", 70}, {"vs39", 71}, \ - {"vs40", 72}, {"vs41", 73}, {"vs42", 74}, {"vs43", 75}, \ - {"vs44", 76}, {"vs45", 77}, {"vs46", 78}, {"vs47", 79}, \ - {"vs48", 80}, {"vs49", 81}, {"vs50", 82}, {"vs51", 83}, \ - {"vs52", 84}, {"vs53", 85}, {"vs54", 86}, {"vs55", 87}, \ - {"vs56", 88}, {"vs57", 89}, {"vs58", 90}, {"vs59", 91}, \ - {"vs60", 92}, {"vs61", 93}, {"vs62", 94}, {"vs63", 95}, \ + {"vs0", 128}, {"vs1", 129}, {"vs2", 130}, {"vs3", 131}, \ + {"vs4", 132}, {"vs5", 133}, {"vs6", 134}, {"vs7", 135}, \ + {"vs8", 136}, {"vs9", 137}, {"vs10", 138}, {"vs11", 139}, \ + {"vs12", 140}, {"vs13", 141}, {"vs14", 142}, {"vs15", 143}, \ + {"vs16", 144}, {"vs17", 145}, {"vs18", 146}, {"vs19", 147}, \ + {"vs20", 148}, {"vs21", 149}, {"vs22", 150}, {"vs23", 151}, \ + {"vs24", 152}, {"vs25", 153}, {"vs26", 154}, {"vs27", 155}, \ + {"vs28", 156}, {"vs29", 157}, {"vs30", 158}, {"vs31", 159}, \ + {"vs32", 160}, {"vs33", 161}, {"vs34", 162}, {"vs35", 163}, \ + {"vs36", 164}, {"vs37", 165}, {"vs38", 166}, {"vs39", 167}, \ + {"vs40", 168}, {"vs41", 169}, {"vs42", 170}, {"vs43", 171}, \ + {"vs44", 172}, {"vs45", 173}, {"vs46", 174}, {"vs47", 175}, \ + {"vs48", 176}, {"vs49", 177}, {"vs50", 178}, {"vs51", 179}, \ + {"vs52", 180}, {"vs53", 181}, {"vs54", 182}, {"vs55", 183}, \ + {"vs56", 184}, {"vs57", 185}, {"vs58", 186}, {"vs59", 187}, \ + {"vs60", 188}, {"vs61", 189}, {"vs62", 190}, {"vs63", 191}, \ } /* This is how to output an element of a case-vector that is relative. */ diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index a1315523fec..5f1293024b5 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -31,26 +31,30 @@ (STATIC_CHAIN_REGNUM 11) (HARD_FRAME_POINTER_REGNUM 31) (LAST_GPR_REGNO 31) - (FIRST_FPR_REGNO 32) - (LAST_FPR_REGNO 63) - (FIRST_ALTIVEC_REGNO 64) - (LAST_ALTIVEC_REGNO 95) - (LR_REGNO 96) - (CTR_REGNO 97) - (CA_REGNO 98) - (ARG_POINTER_REGNUM 99) - (CR0_REGNO 100) - (CR1_REGNO 101) - (CR2_REGNO 102) - (CR3_REGNO 103) - (CR4_REGNO 104) - (CR5_REGNO 105) - (CR6_REGNO 106) - (CR7_REGNO 107) - (MAX_CR_REGNO 107) - (VRSAVE_REGNO 108) - (VSCR_REGNO 109) - (FRAME_POINTER_REGNUM 110) + (LAST_SVP64GPR_REGNO 127) + (FIRST_FPR_REGNO 128) + (LAST_FPR_REGNO 159) + (LAST_SVP64FPR_REGNO 255) + (FIRST_ALTIVEC_REGNO 256) + (LAST_ALTIVEC_REGNO 287) + (LR_REGNO 288) + (CTR_REGNO 289) + (CA_REGNO 290) + (ARG_POINTER_REGNUM 291) + (CR0_REGNO 292) + (CR1_REGNO 293) + (CR2_REGNO 294) + (CR3_REGNO 295) + (CR4_REGNO 296) + (CR5_REGNO 297) + (CR6_REGNO 298) + (CR7_REGNO 299) + (MAX_CR_REGNO 299) + (MAX_SVP64CR_REGNO 419) + (VRSAVE_REGNO 420) + (VSCR_REGNO 421) + (FRAME_POINTER_REGNUM 422) + (SVP64VL_REGNO 423) ]) ;; @@ -413,6 +417,7 @@ (include "cell.md") (include "a2.md") (include "titan.md") +(include "svp64.md") (include "predicates.md") (include "constraints.md") diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt index ae9e91e77cc..db2b29858f9 100644 --- a/gcc/config/rs6000/rs6000.opt +++ b/gcc/config/rs6000/rs6000.opt @@ -545,6 +545,10 @@ mpower9-minmax Target Undocumented Mask(P9_MINMAX) Var(rs6000_isa_flags) Use the new min/max instructions defined in ISA 3.0. +msvp64 +Target Mask(SVP64) Var(rs6000_isa_flags) +Use the Libre-SOC svp64 vector extensions for ISA 3.0. + mtoc-fusion Target Undocumented Mask(TOC_FUSION) Var(rs6000_isa_flags) Fuse medium/large code model toc references with the memory instruction. diff --git a/gcc/config/rs6000/svp64.md b/gcc/config/rs6000/svp64.md new file mode 100644 index 00000000000..567a1260e5c --- /dev/null +++ b/gcc/config/rs6000/svp64.md @@ -0,0 +1,270 @@ +;; Libre-SOC svp64 extensions for ISA 3.0B. +;; Copyright (C) 2021 Free Software Foundation, Inc. +;; +;; This file is part of GCC. + +;; GCC is free software; you can redistribute it and/or modify it +;; under the terms of the GNU General Public License as published +;; by the Free Software Foundation; either version 3, or (at your +;; option) any later version. + +;; GCC is distributed in the hope that it will be useful, but WITHOUT +;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +;; License for more details. + +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; . + +(define_mode_iterator SVP64VI [ + V64DI V64SI V64HI V64QI + V32DI V32SI V32HI V32QI + V16DI V16SI V16HI V16QI + V8DI V8SI V8HI V8QI + V4DI V4SI V4HI + V2DI V2SI + V1DI + ]) + +(define_mode_iterator SVP64VDI [V1DI V2DI V4DI V8DI V16DI V32DI V64DI]) +(define_mode_iterator SVP64VSI [V2SI V4SI V8SI V16SI V32SI V64SI]) +(define_mode_iterator SVP64VHI [V4HI V8HI V16HI V32HI V64HI]) +(define_mode_iterator SVP64VQI [V8QI V16QI V32QI V64QI]) + +(define_mode_iterator SVP64VF [ + V64DF V64SF ; V64HF + V32DF V32SF ; V32HF + V16DF V16SF ; V16HF + V8DF V8SF ; V8HF + V4DF V4SF ; V4HF + V2DF V2SF + V1DF + ]) + +(define_mode_iterator SVP64VDF [V1DF V2DF V4DF V8DF V16DF V32DF V64DF]) +(define_mode_iterator SVP64VSF [V2SF V4SF V8SF V16SF V32SF V64SF]) + +(define_mode_iterator SVP64VIF [ + V64DI V64SI V64HI V64QI + V32DI V32SI V32HI V32QI + V16DI V16SI V16HI V16QI + V8DI V8SI V8HI V8QI + V4DI V4SI V4HI + V2DI V2SI + V1DI + V64DF V64SF ; V64HF + V32DF V32SF ; V32HF + V16DF V16SF ; V16HF + V8DF V8SF ; V8HF + V4DF V4SF ; V4HF + V2DF V2SF + V1DF + ]) + +(define_mode_iterator SVP64VIF_M [ + V64DI V64SI V64HI V64QI + V32DI V32SI V32HI V32QI + V16DI V16SI V16HI V16QI + V8DI V8SI V8HI V8QI + V4DI V4SI V4HI + V2DI V2SI + V1DI + V64DF V64SF ; V64HF + V32DF V32SF ; V32HF + V16DF V16SF ; V16HF + V8DF V8SF ; V8HF + V4DF V4SF ; V4HF + V2DF V2SF + V1DF + ; Other modes covered by VEC_M that we should forward. + V1TI KF + ]) + +(define_expand "mov" + [(parallel + [(set (match_operand:SVP64VIF_M 0 "nonimmediate_operand") + (match_operand:SVP64VIF_M 1 "any_operand")) + (use (match_dup 2))])] + "TARGET_SVP64 || VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)" +{ + if (!TARGET_SVP64 || mode == V1TImode || mode == KFmode) + { + emit_insn (gen_altivec_mov (mode, operands[0], operands[1])); + DONE; + } + operands[2] = GEN_INT (GET_MODE_NUNITS (mode)); + if (CONSTANT_P (operands[1])) + operands[1] = force_const_mem (mode, operands[1]); + if (can_create_pseudo_p () + && !(register_operand (operands[0], mode) + || register_operand (operands[1], mode))) + operands[1] = force_reg (mode, operands[1]); +}) + +(define_insn "*mov" + [(parallel + [(set (match_operand:SVP64VDI 0 "nonimmediate_operand" "=wI,&wI,wI,m") + (match_operand:SVP64VDI 1 "any_operand" "0,wI,m,wI")) + (use (match_operand:QI 2 "svp64_vector_length" "iwV,iwV,iwV,iwV"))])] + "TARGET_SVP64 + && (register_operand (operands[0], mode) + || register_operand (operands[1], mode))" + "@ + nop + sv.mv %0.v,%1.v + sv.ld%U0%X0 %0.v,%1.v + sv.std%U1%X1 %1.v,%0.v" + [(set_attr "type" "*,*,load,store") + (set_attr "length" "4,8,8,8")]) + +(define_insn "*mov" + [(parallel + [(set (match_operand:SVP64VSI 0 "nonimmediate_operand" "=wI,&wI,wI,m") + (match_operand:SVP64VSI 1 "any_operand" "0,wI,m,wI")) + (use (match_operand:QI 2 "svp64_vector_length" "iwV,iwV,iwV,iwV"))])] + "TARGET_SVP64 + && (register_operand (operands[0], mode) + || register_operand (operands[1], mode))" + "@ + nop + sv.mv/elwidth=w/src_elwidth=w %0.v,%1.v + sv.lwz%U0%X0 %0.v,%1.v + sv.stw%U1%X1 %1.v,%0.v" + [(set_attr "type" "*,*,load,store") + (set_attr "length" "4,8,8,8")]) + +(define_insn "*mov" + [(parallel + [(set (match_operand:SVP64VHI 0 "nonimmediate_operand" "=wI,&wI,wI,m") + (match_operand:SVP64VHI 1 "any_operand" "0,wI,m,wI")) + (use (match_operand:QI 2 "svp64_vector_length" "iwV,iwV,iwV,iwV"))])] + "TARGET_SVP64 + && (register_operand (operands[0], mode) + || register_operand (operands[1], mode))" + "@ + nop + sv.mv/elwidth=h/src_elwidth=h %0.v,%1.v + sv.lhz%U1%X1 %0.v,%1.v + sv.sth%U0%X0 %1.v,%0.v" + [(set_attr "type" "*,*,load,store") + (set_attr "length" "4,8,8,8")]) + +(define_insn "*mov" + [(parallel + [(set (match_operand:SVP64VQI 0 "nonimmediate_operand" "=wI,&wI,wI,m") + (match_operand:SVP64VQI 1 "any_operand" "0,wI,m,wI")) + (use (match_operand:QI 2 "svp64_vector_length" "iwV,iwV,iwV,iwV"))])] + "TARGET_SVP64 + && (register_operand (operands[0], mode) + || register_operand (operands[1], mode))" + "@ + nop + sv.mv/elwidth=b/src_elwidth=b %0.v,%1.v + sv.lbz%U1%X1 %0.v,%1.v + sv.stb%U0%X0 %1.v,%0.v" + [(set_attr "type" "*,*,load,store") + (set_attr "length" "4,8,8,8")]) + +(define_insn "*mov" + [(parallel + [(set (match_operand:SVP64VDF 0 "nonimmediate_operand" "=wH,&wH,wH,m,!wI,!wI,!wI,m") + (match_operand:SVP64VDF 1 "any_operand" "0,wH,m,wH,0,!wI,m,!wI")) + (use (match_operand:QI 2 "svp64_vector_length" "iwV,iwV,iwV,iwV,iwV,iwV,iwV,iwV"))])] + "TARGET_SVP64 + && (register_operand (operands[0], mode) + || register_operand (operands[1], mode))" + "@ + nop + sv.fmr %0.v,%1.v + sv.lfd%U0%X0 %0.v,%1.v + sv.stfd%U1%X1 %1.v,%0.v + nop + sv.mv/elwidth=w/src_elwidth=w %0.v,%1.v + sv.lwz%U0%X0 %0.v,%1.v + sv.stw%U1%X1 %1.v,%0.v" + [(set_attr "type" "*,fpsimple,fpload,fpstore,*,*,load,store") + (set_attr "length" "4,8,8,8,4,8,8,8")]) + +(define_insn "*mov" + [(parallel + [(set (match_operand:SVP64VSF 0 "nonimmediate_operand" "=wH,&wH,wH,m,!wI,!wI,!wI,m") + (match_operand:SVP64VSF 1 "any_operand" "0,wH,m,wH,0,!wI,m,!wI")) + (use (match_operand:QI 2 "svp64_vector_length" "iwV,iwV,iwV,iwV,iwV,iwV,iwV,iwV"))])] + "TARGET_SVP64 + && (register_operand (operands[0], mode) + || register_operand (operands[1], mode))" + "@ + nop + sv.fmr/elwidth=f32/src_elwidth=f32 %0.v,%1.v + sv.lfs%U0%X0 %0.v,%1.v + sv.stfs%U1%X1 %1.v,%0.v + nop + sv.mv/elwidth=w/src_elwidth=w %0.v,%1.v + sv.lwz%U0%X0 %0.v,%1.v + sv.stw%U1%X1 %1.v,%0.v" + [(set_attr "type" "*,fpsimple,fpload,fpstore,*,*,load,store") + (set_attr "length" "4,8,8,8,4,8,8,8")]) + +(define_expand "add3" + [(parallel + [(set (match_operand:SVP64VI 0 "gpc_reg_operand") + (plus:SVP64VI (match_operand:SVP64VI 1 "gpc_reg_operand") + (match_operand:SVP64VI 2 "gpc_reg_operand"))) + (use (match_dup 3))])] + "TARGET_SVP64 /* || , i.e. */ + || (mode == V2DImode + ? VECTOR_UNIT_P8_VECTOR_P (mode) + : VECTOR_UNIT_ALTIVEC_P (mode))" +{ + if (!TARGET_SVP64) + { + emit_insn (gen_altivec_add3 (mode, operands[0], operands[1], operands[2])); + DONE; + } + operands[3] = GEN_INT (GET_MODE_NUNITS (mode)); +}) + +(define_insn "*add3" + [(parallel + [(set (match_operand:SVP64VDI 0 "gpc_reg_operand" "=wI,&wI") + (plus:SVP64VDI (match_operand:SVP64VDI 1 "gpc_reg_operand" "%0,wI") + (match_operand:SVP64VDI 2 "gpc_reg_operand" "wI,wI"))) + (use (match_operand:QI 3 "svp64_vector_length" "iwV,iwV"))])] + "TARGET_SVP64" + "sv.add %0.v,%1.v,%2.v" + [(set_attr "type" "add") + (set_attr "length" "8")]) + +(define_insn "*add3" + [(parallel + [(set (match_operand:SVP64VSI 0 "gpc_reg_operand" "=wI,&wI") + (plus:SVP64VSI (match_operand:SVP64VSI 1 "gpc_reg_operand" "%0,wI") + (match_operand:SVP64VSI 2 "gpc_reg_operand" "wI,wI"))) + (use (match_operand:QI 3 "svp64_vector_length" "iwV,iwV"))])] + "TARGET_SVP64" + "sv.add/elwidth=w/src_elwidth=w %0.v,%1.v,%2.v" + [(set_attr "type" "add") + (set_attr "length" "8")]) + +(define_insn "*add3" + [(parallel + [(set (match_operand:SVP64VHI 0 "gpc_reg_operand" "=wI,&wI") + (plus:SVP64VHI (match_operand:SVP64VHI 1 "gpc_reg_operand" "%0,wI") + (match_operand:SVP64VHI 2 "gpc_reg_operand" "wI,wI"))) + (use (match_operand:QI 3 "svp64_vector_length" "iwV,iwV"))])] + "TARGET_SVP64" + "sv.add/elwidth=h/src_elwidth=h %0.v,%1.v,%2.v" + [(set_attr "type" "add") + (set_attr "length" "8")]) + +(define_insn "*add3" + [(parallel + [(set (match_operand:SVP64VQI 0 "gpc_reg_operand" "=wI,&wI") + (plus:SVP64VQI (match_operand:SVP64VQI 1 "gpc_reg_operand" "%0,wI") + (match_operand:SVP64VQI 2 "gpc_reg_operand" "wI,wI"))) + (use (match_operand:QI 3 "svp64_vector_length" "iwV,iwV"))])] + "TARGET_SVP64" + "sv.add/elwidth=q/src_elwidth=q %0.v,%1.v,%2.v" + [(set_attr "type" "add") + (set_attr "length" "8")]) diff --git a/gcc/config/rs6000/t-rs6000 b/gcc/config/rs6000/t-rs6000 index 1541a653738..a92be035b4e 100644 --- a/gcc/config/rs6000/t-rs6000 +++ b/gcc/config/rs6000/t-rs6000 @@ -90,4 +90,5 @@ MD_INCLUDES = $(srcdir)/config/rs6000/rs64.md \ $(srcdir)/config/rs6000/crypto.md \ $(srcdir)/config/rs6000/htm.md \ $(srcdir)/config/rs6000/dfp.md \ - $(srcdir)/config/rs6000/fusion.md + $(srcdir)/config/rs6000/fusion.md \ + $(srcdir)/config/rs6000/svp64.md diff --git a/gcc/config/rs6000/vector.md b/gcc/config/rs6000/vector.md index e5191bd1424..1049bc65d5b 100644 --- a/gcc/config/rs6000/vector.md +++ b/gcc/config/rs6000/vector.md @@ -116,7 +116,7 @@ ;; Vector move instructions. Little-endian VSX loads and stores require ;; special handling to circumvent "element endianness." -(define_expand "mov" +(define_expand "@altivec_mov" [(set (match_operand:VEC_M 0 "nonimmediate_operand") (match_operand:VEC_M 1 "any_operand"))] "VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)" diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index ea315f1be58..e706aacb052 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -1183,7 +1183,7 @@ See RS/6000 and PowerPC Options. -mtune=@var{cpu-type} @gol -mcmodel=@var{code-model} @gol -mpowerpc64 @gol --maltivec -mno-altivec @gol +-maltivec -mno-altivec -msvp64 -mno-svp64 @gol -mpowerpc-gpopt -mno-powerpc-gpopt @gol -mpowerpc-gfxopt -mno-powerpc-gfxopt @gol -mmfcrf -mno-mfcrf -mpopcntb -mno-popcntb -mpopcntd -mno-popcntd @gol @@ -27044,6 +27044,12 @@ vector register when targeting a big-endian platform, and identifies the rightmost element in a vector register when targeting a little-endian platform. +@item -msvp64 +@itemx -mno-svp64 +@opindex msvp64 +@opindex mno-svp64 +Enable Libre-SOC's SVP64 vector extensions. + @item -mvrsave @itemx -mno-vrsave @opindex mvrsave -- 2.30.2