From a49ecc4331a373b9a63a836ca2523db63f88d1e7 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Sat, 10 Dec 2011 20:25:24 +0100 Subject: [PATCH] fhdl: pad support in fragments --- migen/fhdl/structure.py | 11 ++++++++--- migen/fhdl/verilog.py | 2 ++ 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/migen/fhdl/structure.py b/migen/fhdl/structure.py index a1a49526..d00de9ed 100644 --- a/migen/fhdl/structure.py +++ b/migen/fhdl/structure.py @@ -194,15 +194,20 @@ class Instance: return id(self) class Fragment: - def __init__(self, comb=StatementList(), sync=StatementList(), instances=[]): + def __init__(self, comb=StatementList(), sync=StatementList(), instances=[], pads=set()): self.comb = _sl(comb) self.sync = _sl(sync) self.instances = instances + self.pads = pads def __add__(self, other): - return Fragment(self.comb.l + other.comb.l, self.sync.l + other.sync.l, self.instances + other.instances) + return Fragment(self.comb.l + other.comb.l, + self.sync.l + other.sync.l, + self.instances + other.instances, + self.pads | other.pads) def __iadd__(self, other): self.comb.l += other.comb.l self.sync.l += other.sync.l self.instances += other.instances - return self \ No newline at end of file + self.pads |= other.pads + return self diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py index 7f386cb8..8fa9c480 100644 --- a/migen/fhdl/verilog.py +++ b/migen/fhdl/verilog.py @@ -118,6 +118,8 @@ def Convert(f, ios=set(), name="top", clkname="sys_clk", rstname="sys_rst"): clks = Signal(name=clkname) rsts = Signal(name=rstname) + + ios |= f.pads sigs = ListSignals(f) targets = ListTargets(f) -- 2.30.2