From a4ac3fad7a9a6c48fdde3d42e35b113bbd03eacf Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Sat, 27 Jun 2009 00:29:12 -0700
Subject: [PATCH] ARM: Write a function for printing mnemonics and predicates.

---
 src/arch/arm/insts/branch.cc      | 11 ++---
 src/arch/arm/insts/mem.cc         |  8 +++-
 src/arch/arm/insts/pred_inst.cc   |  4 +-
 src/arch/arm/insts/static_inst.cc | 68 +++++++++++++++++++++++++++++--
 src/arch/arm/insts/static_inst.hh |  3 ++
 5 files changed, 78 insertions(+), 16 deletions(-)

diff --git a/src/arch/arm/insts/branch.cc b/src/arch/arm/insts/branch.cc
index 5160994f4..39ad041c8 100644
--- a/src/arch/arm/insts/branch.cc
+++ b/src/arch/arm/insts/branch.cc
@@ -70,7 +70,7 @@ Branch::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
     std::stringstream ss;
 
-    ccprintf(ss, "%-10s ", mnemonic);
+    printMnemonic(ss);
 
     Addr target = pc + 8 + disp;
 
@@ -87,13 +87,10 @@ std::string
 BranchExchange::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
     std::stringstream ss;
-
-    ccprintf(ss, "%-10s ", mnemonic);
-
+    printMnemonic(ss);
     if (_numSrcRegs > 0) {
         printReg(ss, _srcRegIdx[0]);
     }
-
     return ss.str();
 }
 
@@ -101,9 +98,7 @@ std::string
 Jump::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
     std::stringstream ss;
-
-    ccprintf(ss, "%-10s ", mnemonic);
-
+    printMnemonic(ss);
     return ss.str();
 }
 }
diff --git a/src/arch/arm/insts/mem.cc b/src/arch/arm/insts/mem.cc
index e5e91a9ea..7909330aa 100644
--- a/src/arch/arm/insts/mem.cc
+++ b/src/arch/arm/insts/mem.cc
@@ -35,12 +35,16 @@ namespace ArmISA
 std::string
 Memory::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
-    return csprintf("%-10s", mnemonic);
+    std::stringstream ss;
+    printMnemonic(ss);
+    return ss.str();
 }
 
 std::string
 MemoryNoDisp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
-    return csprintf("%-10s", mnemonic);
+    std::stringstream ss;
+    printMnemonic(ss);
+    return ss.str();
 }
 }
diff --git a/src/arch/arm/insts/pred_inst.cc b/src/arch/arm/insts/pred_inst.cc
index 416815aa8..7fd891b19 100644
--- a/src/arch/arm/insts/pred_inst.cc
+++ b/src/arch/arm/insts/pred_inst.cc
@@ -35,9 +35,7 @@ std::string
 PredOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
     std::stringstream ss;
-
-    ccprintf(ss, "%-10s ", mnemonic);
-
+    printMnemonic(ss);
     if (_numDestRegs > 0) {
         printReg(ss, _destRegIdx[0]);
     }
diff --git a/src/arch/arm/insts/static_inst.cc b/src/arch/arm/insts/static_inst.cc
index 1a7853f2c..6b641d8bb 100644
--- a/src/arch/arm/insts/static_inst.cc
+++ b/src/arch/arm/insts/static_inst.cc
@@ -245,14 +245,76 @@ ArmStaticInst::printReg(std::ostream &os, int reg) const
     }
 }
 
+void
+ArmStaticInst::printMnemonic(std::ostream &os,
+                             const std::string &suffix,
+                             bool withPred) const
+{
+    os << "  " << mnemonic;
+    if (withPred) {
+        unsigned condCode = machInst.condCode;
+        switch (condCode) {
+          case COND_EQ:
+            os << "eq";
+            break;
+          case COND_NE:
+            os << "ne";
+            break;
+          case COND_CS:
+            os << "cs";
+            break;
+          case COND_CC:
+            os << "cc";
+            break;
+          case COND_MI:
+            os << "mi";
+            break;
+          case COND_PL:
+            os << "pl";
+            break;
+          case COND_VS:
+            os << "vs";
+            break;
+          case COND_VC:
+            os << "vc";
+            break;
+          case COND_HI:
+            os << "hi";
+            break;
+          case COND_LS:
+            os << "ls";
+            break;
+          case COND_GE:
+            os << "ge";
+            break;
+          case COND_LT:
+            os << "lt";
+            break;
+          case COND_GT:
+            os << "gt";
+            break;
+          case COND_LE:
+            os << "le";
+            break;
+          case COND_AL:
+            // This one is implicit.
+            break;
+          case COND_NV:
+            os << "nv";
+            break;
+          default:
+            panic("Unrecognized condition code %d.\n", condCode);
+        }
+        os << suffix << "   ";
+    }
+}
+
 std::string
 ArmStaticInst::generateDisassembly(Addr pc,
                                    const SymbolTable *symtab) const
 {
     std::stringstream ss;
-
-    ccprintf(ss, "%-10s ", mnemonic);
-
+    printMnemonic(ss);
     return ss.str();
 }
 }
diff --git a/src/arch/arm/insts/static_inst.hh b/src/arch/arm/insts/static_inst.hh
index 6321f0de9..ca4cb0f64 100644
--- a/src/arch/arm/insts/static_inst.hh
+++ b/src/arch/arm/insts/static_inst.hh
@@ -62,6 +62,9 @@ class ArmStaticInst : public StaticInst
     /// Print a register name for disassembly given the unique
     /// dependence tag number (FP or int).
     void printReg(std::ostream &os, int reg) const;
+    void printMnemonic(std::ostream &os,
+                       const std::string &suffix = "",
+                       bool withPred = true) const;
 
     std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
 };
-- 
2.30.2