From a4ac6b9543939ffea583be44cfba1141bdaeb7e6 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 3 Dec 2020 18:30:12 +0000 Subject: [PATCH] very weird bug where CoreToChip.buildChip cannot find gpio_o(8) --- experiments9/non_generated/full_core_ls180.il | 54778 ++++++++-------- 1 file changed, 28144 insertions(+), 26634 deletions(-) diff --git a/experiments9/non_generated/full_core_ls180.il b/experiments9/non_generated/full_core_ls180.il index 3d746a3..1a1e970 100644 --- a/experiments9/non_generated/full_core_ls180.il +++ b/experiments9/non_generated/full_core_ls180.il @@ -220710,2600 +220710,2698 @@ module \logical_pipe2 connect { \output_logical_op__insn \output_logical_op__data_len \output_logical_op__is_signed \output_logical_op__is_32bit \output_logical_op__output_carry \output_logical_op__write_cr0 \output_logical_op__invert_out \output_logical_op__input_carry \output_logical_op__zero_a \output_logical_op__invert_in \output_logical_op__oe__ok \output_logical_op__oe__oe \output_logical_op__rc__ok \output_logical_op__rc__rc \output_logical_op__imm_data__ok \output_logical_op__imm_data__data \output_logical_op__fn_unit \output_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } connect \output_muxid \muxid end -attribute \src "ls180.v:4.1-10732.10" +attribute \src "ls180.v:4.1-10831.10" attribute \cells_not_processed 1 module \ls180 - attribute \src "ls180.v:10160.1-10170.4" - wire width 7 $0$memwr$\mem$ls180.v:10162$1_ADDR[6:0]$2759 - attribute \src "ls180.v:10160.1-10170.4" - wire width 32 $0$memwr$\mem$ls180.v:10162$1_DATA[31:0]$2760 - attribute \src "ls180.v:10160.1-10170.4" - wire width 32 $0$memwr$\mem$ls180.v:10162$1_EN[31:0]$2761 - attribute \src "ls180.v:10160.1-10170.4" - wire width 7 $0$memwr$\mem$ls180.v:10164$2_ADDR[6:0]$2762 - attribute \src "ls180.v:10160.1-10170.4" - wire width 32 $0$memwr$\mem$ls180.v:10164$2_DATA[31:0]$2763 - attribute \src "ls180.v:10160.1-10170.4" - wire width 32 $0$memwr$\mem$ls180.v:10164$2_EN[31:0]$2764 - attribute \src "ls180.v:10160.1-10170.4" - wire width 7 $0$memwr$\mem$ls180.v:10166$3_ADDR[6:0]$2765 - attribute \src "ls180.v:10160.1-10170.4" - wire width 32 $0$memwr$\mem$ls180.v:10166$3_DATA[31:0]$2766 - attribute \src "ls180.v:10160.1-10170.4" - wire width 32 $0$memwr$\mem$ls180.v:10166$3_EN[31:0]$2767 - attribute \src "ls180.v:10160.1-10170.4" - wire width 7 $0$memwr$\mem$ls180.v:10168$4_ADDR[6:0]$2768 - attribute \src "ls180.v:10160.1-10170.4" - wire width 32 $0$memwr$\mem$ls180.v:10168$4_DATA[31:0]$2769 - attribute \src "ls180.v:10160.1-10170.4" - wire width 32 $0$memwr$\mem$ls180.v:10168$4_EN[31:0]$2770 - attribute \src "ls180.v:10180.1-10190.4" - wire width 7 $0$memwr$\mem_1$ls180.v:10182$5_ADDR[6:0]$2773 - attribute \src "ls180.v:10180.1-10190.4" - wire width 32 $0$memwr$\mem_1$ls180.v:10182$5_DATA[31:0]$2774 - attribute \src "ls180.v:10180.1-10190.4" - wire width 32 $0$memwr$\mem_1$ls180.v:10182$5_EN[31:0]$2775 - attribute \src "ls180.v:10180.1-10190.4" - wire width 7 $0$memwr$\mem_1$ls180.v:10184$6_ADDR[6:0]$2776 - attribute \src "ls180.v:10180.1-10190.4" - wire width 32 $0$memwr$\mem_1$ls180.v:10184$6_DATA[31:0]$2777 - attribute \src "ls180.v:10180.1-10190.4" - wire width 32 $0$memwr$\mem_1$ls180.v:10184$6_EN[31:0]$2778 - attribute \src "ls180.v:10180.1-10190.4" - wire width 7 $0$memwr$\mem_1$ls180.v:10186$7_ADDR[6:0]$2779 - attribute \src "ls180.v:10180.1-10190.4" - wire width 32 $0$memwr$\mem_1$ls180.v:10186$7_DATA[31:0]$2780 - attribute \src "ls180.v:10180.1-10190.4" - wire width 32 $0$memwr$\mem_1$ls180.v:10186$7_EN[31:0]$2781 - attribute \src "ls180.v:10180.1-10190.4" - wire width 7 $0$memwr$\mem_1$ls180.v:10188$8_ADDR[6:0]$2782 - attribute \src "ls180.v:10180.1-10190.4" - wire width 32 $0$memwr$\mem_1$ls180.v:10188$8_DATA[31:0]$2783 - attribute \src "ls180.v:10180.1-10190.4" - wire width 32 $0$memwr$\mem_1$ls180.v:10188$8_EN[31:0]$2784 - attribute \src "ls180.v:10200.1-10210.4" - wire width 7 $0$memwr$\mem_2$ls180.v:10202$9_ADDR[6:0]$2787 - attribute \src "ls180.v:10200.1-10210.4" - wire width 32 $0$memwr$\mem_2$ls180.v:10202$9_DATA[31:0]$2788 - attribute \src "ls180.v:10200.1-10210.4" - wire width 32 $0$memwr$\mem_2$ls180.v:10202$9_EN[31:0]$2789 - attribute \src "ls180.v:10200.1-10210.4" - wire width 7 $0$memwr$\mem_2$ls180.v:10204$10_ADDR[6:0]$2790 - attribute \src "ls180.v:10200.1-10210.4" - wire width 32 $0$memwr$\mem_2$ls180.v:10204$10_DATA[31:0]$2791 - attribute \src "ls180.v:10200.1-10210.4" - wire width 32 $0$memwr$\mem_2$ls180.v:10204$10_EN[31:0]$2792 - attribute \src "ls180.v:10200.1-10210.4" - wire width 7 $0$memwr$\mem_2$ls180.v:10206$11_ADDR[6:0]$2793 - attribute \src "ls180.v:10200.1-10210.4" - wire width 32 $0$memwr$\mem_2$ls180.v:10206$11_DATA[31:0]$2794 - attribute \src "ls180.v:10200.1-10210.4" - wire width 32 $0$memwr$\mem_2$ls180.v:10206$11_EN[31:0]$2795 - attribute \src "ls180.v:10200.1-10210.4" - wire width 7 $0$memwr$\mem_2$ls180.v:10208$12_ADDR[6:0]$2796 - attribute \src "ls180.v:10200.1-10210.4" - wire width 32 $0$memwr$\mem_2$ls180.v:10208$12_DATA[31:0]$2797 - attribute \src "ls180.v:10200.1-10210.4" - wire width 32 $0$memwr$\mem_2$ls180.v:10208$12_EN[31:0]$2798 - attribute \src "ls180.v:10220.1-10230.4" - wire width 7 $0$memwr$\mem_3$ls180.v:10222$13_ADDR[6:0]$2801 - attribute \src "ls180.v:10220.1-10230.4" - wire width 32 $0$memwr$\mem_3$ls180.v:10222$13_DATA[31:0]$2802 - attribute \src "ls180.v:10220.1-10230.4" - wire width 32 $0$memwr$\mem_3$ls180.v:10222$13_EN[31:0]$2803 - attribute \src "ls180.v:10220.1-10230.4" - wire width 7 $0$memwr$\mem_3$ls180.v:10224$14_ADDR[6:0]$2804 - attribute \src "ls180.v:10220.1-10230.4" - wire width 32 $0$memwr$\mem_3$ls180.v:10224$14_DATA[31:0]$2805 - attribute \src "ls180.v:10220.1-10230.4" - wire width 32 $0$memwr$\mem_3$ls180.v:10224$14_EN[31:0]$2806 - attribute \src "ls180.v:10220.1-10230.4" - wire width 7 $0$memwr$\mem_3$ls180.v:10226$15_ADDR[6:0]$2807 - attribute \src "ls180.v:10220.1-10230.4" - wire width 32 $0$memwr$\mem_3$ls180.v:10226$15_DATA[31:0]$2808 - attribute \src "ls180.v:10220.1-10230.4" - wire width 32 $0$memwr$\mem_3$ls180.v:10226$15_EN[31:0]$2809 - attribute \src "ls180.v:10220.1-10230.4" - wire width 7 $0$memwr$\mem_3$ls180.v:10228$16_ADDR[6:0]$2810 - attribute \src "ls180.v:10220.1-10230.4" - wire width 32 $0$memwr$\mem_3$ls180.v:10228$16_DATA[31:0]$2811 - attribute \src "ls180.v:10220.1-10230.4" - wire width 32 $0$memwr$\mem_3$ls180.v:10228$16_EN[31:0]$2812 - attribute \src "ls180.v:10240.1-10244.4" - wire width 3 $0$memwr$\storage$ls180.v:10242$17_ADDR[2:0]$2815 - attribute \src "ls180.v:10240.1-10244.4" - wire width 25 $0$memwr$\storage$ls180.v:10242$17_DATA[24:0]$2816 - attribute \src "ls180.v:10240.1-10244.4" - wire width 25 $0$memwr$\storage$ls180.v:10242$17_EN[24:0]$2817 - attribute \src "ls180.v:10254.1-10258.4" - wire width 3 $0$memwr$\storage_1$ls180.v:10256$18_ADDR[2:0]$2822 - attribute \src "ls180.v:10254.1-10258.4" - wire width 25 $0$memwr$\storage_1$ls180.v:10256$18_DATA[24:0]$2823 - attribute \src "ls180.v:10254.1-10258.4" - wire width 25 $0$memwr$\storage_1$ls180.v:10256$18_EN[24:0]$2824 - attribute \src "ls180.v:10268.1-10272.4" - wire width 3 $0$memwr$\storage_2$ls180.v:10270$19_ADDR[2:0]$2829 - attribute \src "ls180.v:10268.1-10272.4" - wire width 25 $0$memwr$\storage_2$ls180.v:10270$19_DATA[24:0]$2830 - attribute \src "ls180.v:10268.1-10272.4" - wire width 25 $0$memwr$\storage_2$ls180.v:10270$19_EN[24:0]$2831 - attribute \src "ls180.v:10282.1-10286.4" - wire width 3 $0$memwr$\storage_3$ls180.v:10284$20_ADDR[2:0]$2836 - attribute \src "ls180.v:10282.1-10286.4" - wire width 25 $0$memwr$\storage_3$ls180.v:10284$20_DATA[24:0]$2837 - attribute \src "ls180.v:10282.1-10286.4" - wire width 25 $0$memwr$\storage_3$ls180.v:10284$20_EN[24:0]$2838 - attribute \src "ls180.v:10297.1-10301.4" - wire width 4 $0$memwr$\storage_4$ls180.v:10299$21_ADDR[3:0]$2843 - attribute \src "ls180.v:10297.1-10301.4" - wire width 10 $0$memwr$\storage_4$ls180.v:10299$21_DATA[9:0]$2844 - attribute \src "ls180.v:10297.1-10301.4" - wire width 10 $0$memwr$\storage_4$ls180.v:10299$21_EN[9:0]$2845 - attribute \src "ls180.v:10314.1-10318.4" - wire width 4 $0$memwr$\storage_5$ls180.v:10316$22_ADDR[3:0]$2850 - attribute \src "ls180.v:10314.1-10318.4" - wire width 10 $0$memwr$\storage_5$ls180.v:10316$22_DATA[9:0]$2851 - attribute \src "ls180.v:10314.1-10318.4" - wire width 10 $0$memwr$\storage_5$ls180.v:10316$22_EN[9:0]$2852 - attribute \src "ls180.v:10330.1-10334.4" - wire width 5 $0$memwr$\storage_6$ls180.v:10332$23_ADDR[4:0]$2857 - attribute \src "ls180.v:10330.1-10334.4" - wire width 10 $0$memwr$\storage_6$ls180.v:10332$23_DATA[9:0]$2858 - attribute \src "ls180.v:10330.1-10334.4" - wire width 10 $0$memwr$\storage_6$ls180.v:10332$23_EN[9:0]$2859 - attribute \src "ls180.v:10344.1-10348.4" - wire width 5 $0$memwr$\storage_7$ls180.v:10346$24_ADDR[4:0]$2864 - attribute \src "ls180.v:10344.1-10348.4" - wire width 10 $0$memwr$\storage_7$ls180.v:10346$24_DATA[9:0]$2865 - attribute \src "ls180.v:10344.1-10348.4" - wire width 10 $0$memwr$\storage_7$ls180.v:10346$24_EN[9:0]$2866 - attribute \src "ls180.v:3297.1-3390.4" + attribute \src "ls180.v:10227.1-10245.4" + wire width 6 $0$memwr$\mem$ls180.v:10229$1_ADDR[5:0]$2826 + attribute \src "ls180.v:10227.1-10245.4" + wire width 64 $0$memwr$\mem$ls180.v:10229$1_DATA[63:0]$2827 + attribute \src "ls180.v:10227.1-10245.4" + wire width 64 $0$memwr$\mem$ls180.v:10229$1_EN[63:0]$2828 + attribute \src "ls180.v:10227.1-10245.4" + wire width 6 $0$memwr$\mem$ls180.v:10231$2_ADDR[5:0]$2829 + attribute \src "ls180.v:10227.1-10245.4" + wire width 64 $0$memwr$\mem$ls180.v:10231$2_DATA[63:0]$2830 + attribute \src "ls180.v:10227.1-10245.4" + wire width 64 $0$memwr$\mem$ls180.v:10231$2_EN[63:0]$2831 + attribute \src "ls180.v:10227.1-10245.4" + wire width 6 $0$memwr$\mem$ls180.v:10233$3_ADDR[5:0]$2832 + attribute \src "ls180.v:10227.1-10245.4" + wire width 64 $0$memwr$\mem$ls180.v:10233$3_DATA[63:0]$2833 + attribute \src "ls180.v:10227.1-10245.4" + wire width 64 $0$memwr$\mem$ls180.v:10233$3_EN[63:0]$2834 + attribute \src "ls180.v:10227.1-10245.4" + wire width 6 $0$memwr$\mem$ls180.v:10235$4_ADDR[5:0]$2835 + attribute \src "ls180.v:10227.1-10245.4" + wire width 64 $0$memwr$\mem$ls180.v:10235$4_DATA[63:0]$2836 + attribute \src "ls180.v:10227.1-10245.4" + wire width 64 $0$memwr$\mem$ls180.v:10235$4_EN[63:0]$2837 + attribute \src "ls180.v:10227.1-10245.4" + wire width 6 $0$memwr$\mem$ls180.v:10237$5_ADDR[5:0]$2838 + attribute \src "ls180.v:10227.1-10245.4" + wire width 64 $0$memwr$\mem$ls180.v:10237$5_DATA[63:0]$2839 + attribute \src "ls180.v:10227.1-10245.4" + wire width 64 $0$memwr$\mem$ls180.v:10237$5_EN[63:0]$2840 + attribute \src "ls180.v:10227.1-10245.4" + wire width 6 $0$memwr$\mem$ls180.v:10239$6_ADDR[5:0]$2841 + attribute \src "ls180.v:10227.1-10245.4" + wire width 64 $0$memwr$\mem$ls180.v:10239$6_DATA[63:0]$2842 + attribute \src "ls180.v:10227.1-10245.4" + wire width 64 $0$memwr$\mem$ls180.v:10239$6_EN[63:0]$2843 + attribute \src "ls180.v:10227.1-10245.4" + wire width 6 $0$memwr$\mem$ls180.v:10241$7_ADDR[5:0]$2844 + attribute \src "ls180.v:10227.1-10245.4" + wire width 64 $0$memwr$\mem$ls180.v:10241$7_DATA[63:0]$2845 + attribute \src "ls180.v:10227.1-10245.4" + wire width 64 $0$memwr$\mem$ls180.v:10241$7_EN[63:0]$2846 + attribute \src "ls180.v:10227.1-10245.4" + wire width 6 $0$memwr$\mem$ls180.v:10243$8_ADDR[5:0]$2847 + attribute \src "ls180.v:10227.1-10245.4" + wire width 64 $0$memwr$\mem$ls180.v:10243$8_DATA[63:0]$2848 + attribute \src "ls180.v:10227.1-10245.4" + wire width 64 $0$memwr$\mem$ls180.v:10243$8_EN[63:0]$2849 + attribute \src "ls180.v:10255.1-10273.4" + wire width 6 $0$memwr$\mem_1$ls180.v:10257$9_ADDR[5:0]$2852 + attribute \src "ls180.v:10255.1-10273.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10257$9_DATA[63:0]$2853 + attribute \src "ls180.v:10255.1-10273.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10257$9_EN[63:0]$2854 + attribute \src "ls180.v:10255.1-10273.4" + wire width 6 $0$memwr$\mem_1$ls180.v:10259$10_ADDR[5:0]$2855 + attribute \src "ls180.v:10255.1-10273.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10259$10_DATA[63:0]$2856 + attribute \src "ls180.v:10255.1-10273.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10259$10_EN[63:0]$2857 + attribute \src "ls180.v:10255.1-10273.4" + wire width 6 $0$memwr$\mem_1$ls180.v:10261$11_ADDR[5:0]$2858 + attribute \src "ls180.v:10255.1-10273.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10261$11_DATA[63:0]$2859 + attribute \src "ls180.v:10255.1-10273.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10261$11_EN[63:0]$2860 + attribute \src "ls180.v:10255.1-10273.4" + wire width 6 $0$memwr$\mem_1$ls180.v:10263$12_ADDR[5:0]$2861 + attribute \src "ls180.v:10255.1-10273.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10263$12_DATA[63:0]$2862 + attribute \src "ls180.v:10255.1-10273.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10263$12_EN[63:0]$2863 + attribute \src "ls180.v:10255.1-10273.4" + wire width 6 $0$memwr$\mem_1$ls180.v:10265$13_ADDR[5:0]$2864 + attribute \src "ls180.v:10255.1-10273.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10265$13_DATA[63:0]$2865 + attribute \src "ls180.v:10255.1-10273.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10265$13_EN[63:0]$2866 + attribute \src "ls180.v:10255.1-10273.4" + wire width 6 $0$memwr$\mem_1$ls180.v:10267$14_ADDR[5:0]$2867 + attribute \src "ls180.v:10255.1-10273.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10267$14_DATA[63:0]$2868 + attribute \src "ls180.v:10255.1-10273.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10267$14_EN[63:0]$2869 + attribute \src "ls180.v:10255.1-10273.4" + wire width 6 $0$memwr$\mem_1$ls180.v:10269$15_ADDR[5:0]$2870 + attribute \src "ls180.v:10255.1-10273.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10269$15_DATA[63:0]$2871 + attribute \src "ls180.v:10255.1-10273.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10269$15_EN[63:0]$2872 + attribute \src "ls180.v:10255.1-10273.4" + wire width 6 $0$memwr$\mem_1$ls180.v:10271$16_ADDR[5:0]$2873 + attribute \src "ls180.v:10255.1-10273.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10271$16_DATA[63:0]$2874 + attribute \src "ls180.v:10255.1-10273.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10271$16_EN[63:0]$2875 + attribute \src "ls180.v:10283.1-10301.4" + wire width 6 $0$memwr$\mem_2$ls180.v:10285$17_ADDR[5:0]$2878 + attribute \src "ls180.v:10283.1-10301.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10285$17_DATA[63:0]$2879 + attribute \src "ls180.v:10283.1-10301.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10285$17_EN[63:0]$2880 + attribute \src "ls180.v:10283.1-10301.4" + wire width 6 $0$memwr$\mem_2$ls180.v:10287$18_ADDR[5:0]$2881 + attribute \src "ls180.v:10283.1-10301.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10287$18_DATA[63:0]$2882 + attribute \src "ls180.v:10283.1-10301.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10287$18_EN[63:0]$2883 + attribute \src "ls180.v:10283.1-10301.4" + wire width 6 $0$memwr$\mem_2$ls180.v:10289$19_ADDR[5:0]$2884 + attribute \src "ls180.v:10283.1-10301.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10289$19_DATA[63:0]$2885 + attribute \src "ls180.v:10283.1-10301.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10289$19_EN[63:0]$2886 + attribute \src "ls180.v:10283.1-10301.4" + wire width 6 $0$memwr$\mem_2$ls180.v:10291$20_ADDR[5:0]$2887 + attribute \src "ls180.v:10283.1-10301.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10291$20_DATA[63:0]$2888 + attribute \src "ls180.v:10283.1-10301.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10291$20_EN[63:0]$2889 + attribute \src "ls180.v:10283.1-10301.4" + wire width 6 $0$memwr$\mem_2$ls180.v:10293$21_ADDR[5:0]$2890 + attribute \src "ls180.v:10283.1-10301.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10293$21_DATA[63:0]$2891 + attribute \src "ls180.v:10283.1-10301.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10293$21_EN[63:0]$2892 + attribute \src "ls180.v:10283.1-10301.4" + wire width 6 $0$memwr$\mem_2$ls180.v:10295$22_ADDR[5:0]$2893 + attribute \src "ls180.v:10283.1-10301.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10295$22_DATA[63:0]$2894 + attribute \src "ls180.v:10283.1-10301.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10295$22_EN[63:0]$2895 + attribute \src "ls180.v:10283.1-10301.4" + wire width 6 $0$memwr$\mem_2$ls180.v:10297$23_ADDR[5:0]$2896 + attribute \src "ls180.v:10283.1-10301.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10297$23_DATA[63:0]$2897 + attribute \src "ls180.v:10283.1-10301.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10297$23_EN[63:0]$2898 + attribute \src "ls180.v:10283.1-10301.4" + wire width 6 $0$memwr$\mem_2$ls180.v:10299$24_ADDR[5:0]$2899 + attribute \src "ls180.v:10283.1-10301.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10299$24_DATA[63:0]$2900 + attribute \src "ls180.v:10283.1-10301.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10299$24_EN[63:0]$2901 + attribute \src "ls180.v:10311.1-10329.4" + wire width 6 $0$memwr$\mem_3$ls180.v:10313$25_ADDR[5:0]$2904 + attribute \src "ls180.v:10311.1-10329.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10313$25_DATA[63:0]$2905 + attribute \src "ls180.v:10311.1-10329.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10313$25_EN[63:0]$2906 + attribute \src "ls180.v:10311.1-10329.4" + wire width 6 $0$memwr$\mem_3$ls180.v:10315$26_ADDR[5:0]$2907 + attribute \src "ls180.v:10311.1-10329.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10315$26_DATA[63:0]$2908 + attribute \src "ls180.v:10311.1-10329.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10315$26_EN[63:0]$2909 + attribute \src "ls180.v:10311.1-10329.4" + wire width 6 $0$memwr$\mem_3$ls180.v:10317$27_ADDR[5:0]$2910 + attribute \src "ls180.v:10311.1-10329.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10317$27_DATA[63:0]$2911 + attribute \src "ls180.v:10311.1-10329.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10317$27_EN[63:0]$2912 + attribute \src "ls180.v:10311.1-10329.4" + wire width 6 $0$memwr$\mem_3$ls180.v:10319$28_ADDR[5:0]$2913 + attribute \src "ls180.v:10311.1-10329.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10319$28_DATA[63:0]$2914 + attribute \src "ls180.v:10311.1-10329.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10319$28_EN[63:0]$2915 + attribute \src "ls180.v:10311.1-10329.4" + wire width 6 $0$memwr$\mem_3$ls180.v:10321$29_ADDR[5:0]$2916 + attribute \src "ls180.v:10311.1-10329.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10321$29_DATA[63:0]$2917 + attribute \src "ls180.v:10311.1-10329.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10321$29_EN[63:0]$2918 + attribute \src "ls180.v:10311.1-10329.4" + wire width 6 $0$memwr$\mem_3$ls180.v:10323$30_ADDR[5:0]$2919 + attribute \src "ls180.v:10311.1-10329.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10323$30_DATA[63:0]$2920 + attribute \src "ls180.v:10311.1-10329.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10323$30_EN[63:0]$2921 + attribute \src "ls180.v:10311.1-10329.4" + wire width 6 $0$memwr$\mem_3$ls180.v:10325$31_ADDR[5:0]$2922 + attribute \src "ls180.v:10311.1-10329.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10325$31_DATA[63:0]$2923 + attribute \src "ls180.v:10311.1-10329.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10325$31_EN[63:0]$2924 + attribute \src "ls180.v:10311.1-10329.4" + wire width 6 $0$memwr$\mem_3$ls180.v:10327$32_ADDR[5:0]$2925 + attribute \src "ls180.v:10311.1-10329.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10327$32_DATA[63:0]$2926 + attribute \src "ls180.v:10311.1-10329.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10327$32_EN[63:0]$2927 + attribute \src "ls180.v:10339.1-10343.4" + wire width 3 $0$memwr$\storage$ls180.v:10341$33_ADDR[2:0]$2930 + attribute \src "ls180.v:10339.1-10343.4" + wire width 25 $0$memwr$\storage$ls180.v:10341$33_DATA[24:0]$2931 + attribute \src "ls180.v:10339.1-10343.4" + wire width 25 $0$memwr$\storage$ls180.v:10341$33_EN[24:0]$2932 + attribute \src "ls180.v:10353.1-10357.4" + wire width 3 $0$memwr$\storage_1$ls180.v:10355$34_ADDR[2:0]$2937 + attribute \src "ls180.v:10353.1-10357.4" + wire width 25 $0$memwr$\storage_1$ls180.v:10355$34_DATA[24:0]$2938 + attribute \src "ls180.v:10353.1-10357.4" + wire width 25 $0$memwr$\storage_1$ls180.v:10355$34_EN[24:0]$2939 + attribute \src "ls180.v:10367.1-10371.4" + wire width 3 $0$memwr$\storage_2$ls180.v:10369$35_ADDR[2:0]$2944 + attribute \src "ls180.v:10367.1-10371.4" + wire width 25 $0$memwr$\storage_2$ls180.v:10369$35_DATA[24:0]$2945 + attribute \src "ls180.v:10367.1-10371.4" + wire width 25 $0$memwr$\storage_2$ls180.v:10369$35_EN[24:0]$2946 + attribute \src "ls180.v:10381.1-10385.4" + wire width 3 $0$memwr$\storage_3$ls180.v:10383$36_ADDR[2:0]$2951 + attribute \src "ls180.v:10381.1-10385.4" + wire width 25 $0$memwr$\storage_3$ls180.v:10383$36_DATA[24:0]$2952 + attribute \src "ls180.v:10381.1-10385.4" + wire width 25 $0$memwr$\storage_3$ls180.v:10383$36_EN[24:0]$2953 + attribute \src "ls180.v:10396.1-10400.4" + wire width 4 $0$memwr$\storage_4$ls180.v:10398$37_ADDR[3:0]$2958 + attribute \src "ls180.v:10396.1-10400.4" + wire width 10 $0$memwr$\storage_4$ls180.v:10398$37_DATA[9:0]$2959 + attribute \src "ls180.v:10396.1-10400.4" + wire width 10 $0$memwr$\storage_4$ls180.v:10398$37_EN[9:0]$2960 + attribute \src "ls180.v:10413.1-10417.4" + wire width 4 $0$memwr$\storage_5$ls180.v:10415$38_ADDR[3:0]$2965 + attribute \src "ls180.v:10413.1-10417.4" + wire width 10 $0$memwr$\storage_5$ls180.v:10415$38_DATA[9:0]$2966 + attribute \src "ls180.v:10413.1-10417.4" + wire width 10 $0$memwr$\storage_5$ls180.v:10415$38_EN[9:0]$2967 + attribute \src "ls180.v:10429.1-10433.4" + wire width 5 $0$memwr$\storage_6$ls180.v:10431$39_ADDR[4:0]$2972 + attribute \src "ls180.v:10429.1-10433.4" + wire width 10 $0$memwr$\storage_6$ls180.v:10431$39_DATA[9:0]$2973 + attribute \src "ls180.v:10429.1-10433.4" + wire width 10 $0$memwr$\storage_6$ls180.v:10431$39_EN[9:0]$2974 + attribute \src "ls180.v:10443.1-10447.4" + wire width 5 $0$memwr$\storage_7$ls180.v:10445$40_ADDR[4:0]$2979 + attribute \src "ls180.v:10443.1-10447.4" + wire width 10 $0$memwr$\storage_7$ls180.v:10445$40_DATA[9:0]$2980 + attribute \src "ls180.v:10443.1-10447.4" + wire width 10 $0$memwr$\storage_7$ls180.v:10445$40_EN[9:0]$2981 + attribute \src "ls180.v:3326.1-3419.4" wire width 3 $0\builder_bankmachine0_next_state[2:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 3 $0\builder_bankmachine0_state[2:0] - attribute \src "ls180.v:3454.1-3547.4" + attribute \src "ls180.v:3483.1-3576.4" wire width 3 $0\builder_bankmachine1_next_state[2:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 3 $0\builder_bankmachine1_state[2:0] - attribute \src "ls180.v:3611.1-3704.4" + attribute \src "ls180.v:3640.1-3733.4" wire width 3 $0\builder_bankmachine2_next_state[2:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 3 $0\builder_bankmachine2_state[2:0] - attribute \src "ls180.v:3768.1-3861.4" + attribute \src "ls180.v:3797.1-3890.4" wire width 3 $0\builder_bankmachine3_next_state[2:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 3 $0\builder_bankmachine3_state[2:0] - attribute \src "ls180.v:6618.1-6634.4" + attribute \src "ls180.v:6670.1-6686.4" wire $0\builder_comb_rhs_array_muxed0[0:0] - attribute \src "ls180.v:6839.1-6855.4" + attribute \src "ls180.v:6891.1-6907.4" wire $0\builder_comb_rhs_array_muxed10[0:0] - attribute \src "ls180.v:6856.1-6872.4" + attribute \src "ls180.v:6908.1-6924.4" wire $0\builder_comb_rhs_array_muxed11[0:0] - attribute \src "ls180.v:6924.1-6931.4" + attribute \src "ls180.v:6976.1-6983.4" wire width 22 $0\builder_comb_rhs_array_muxed12[21:0] - attribute \src "ls180.v:6932.1-6939.4" + attribute \src "ls180.v:6984.1-6991.4" wire $0\builder_comb_rhs_array_muxed13[0:0] - attribute \src "ls180.v:6940.1-6947.4" + attribute \src "ls180.v:6992.1-6999.4" wire $0\builder_comb_rhs_array_muxed14[0:0] - attribute \src "ls180.v:6948.1-6955.4" + attribute \src "ls180.v:7000.1-7007.4" wire width 22 $0\builder_comb_rhs_array_muxed15[21:0] - attribute \src "ls180.v:6956.1-6963.4" + attribute \src "ls180.v:7008.1-7015.4" wire $0\builder_comb_rhs_array_muxed16[0:0] - attribute \src "ls180.v:6964.1-6971.4" + attribute \src "ls180.v:7016.1-7023.4" wire $0\builder_comb_rhs_array_muxed17[0:0] - attribute \src "ls180.v:6972.1-6979.4" + attribute \src "ls180.v:7024.1-7031.4" wire width 22 $0\builder_comb_rhs_array_muxed18[21:0] - attribute \src "ls180.v:6980.1-6987.4" + attribute \src "ls180.v:7032.1-7039.4" wire $0\builder_comb_rhs_array_muxed19[0:0] - attribute \src "ls180.v:6635.1-6651.4" + attribute \src "ls180.v:6687.1-6703.4" wire width 13 $0\builder_comb_rhs_array_muxed1[12:0] - attribute \src "ls180.v:6988.1-6995.4" + attribute \src "ls180.v:7040.1-7047.4" wire $0\builder_comb_rhs_array_muxed20[0:0] - attribute \src "ls180.v:6996.1-7003.4" + attribute \src "ls180.v:7048.1-7055.4" wire width 22 $0\builder_comb_rhs_array_muxed21[21:0] - attribute \src "ls180.v:7004.1-7011.4" + attribute \src "ls180.v:7056.1-7063.4" wire $0\builder_comb_rhs_array_muxed22[0:0] - attribute \src "ls180.v:7012.1-7019.4" + attribute \src "ls180.v:7064.1-7071.4" wire $0\builder_comb_rhs_array_muxed23[0:0] - attribute \src "ls180.v:7020.1-7039.4" + attribute \src "ls180.v:7072.1-7091.4" wire width 32 $0\builder_comb_rhs_array_muxed24[31:0] - attribute \src "ls180.v:7040.1-7059.4" - wire width 32 $0\builder_comb_rhs_array_muxed25[31:0] - attribute \src "ls180.v:7060.1-7079.4" - wire width 4 $0\builder_comb_rhs_array_muxed26[3:0] - attribute \src "ls180.v:7080.1-7099.4" + attribute \src "ls180.v:7092.1-7111.4" + wire width 64 $0\builder_comb_rhs_array_muxed25[63:0] + attribute \src "ls180.v:7112.1-7131.4" + wire width 8 $0\builder_comb_rhs_array_muxed26[7:0] + attribute \src "ls180.v:7132.1-7151.4" wire $0\builder_comb_rhs_array_muxed27[0:0] - attribute \src "ls180.v:7100.1-7119.4" + attribute \src "ls180.v:7152.1-7171.4" wire $0\builder_comb_rhs_array_muxed28[0:0] - attribute \src "ls180.v:7120.1-7139.4" + attribute \src "ls180.v:7172.1-7191.4" wire $0\builder_comb_rhs_array_muxed29[0:0] - attribute \src "ls180.v:6652.1-6668.4" + attribute \src "ls180.v:6704.1-6720.4" wire width 2 $0\builder_comb_rhs_array_muxed2[1:0] - attribute \src "ls180.v:7140.1-7159.4" + attribute \src "ls180.v:7192.1-7211.4" wire width 3 $0\builder_comb_rhs_array_muxed30[2:0] - attribute \src "ls180.v:7160.1-7179.4" + attribute \src "ls180.v:7212.1-7231.4" wire width 2 $0\builder_comb_rhs_array_muxed31[1:0] - attribute \src "ls180.v:6669.1-6685.4" + attribute \src "ls180.v:6721.1-6737.4" wire $0\builder_comb_rhs_array_muxed3[0:0] - attribute \src "ls180.v:6686.1-6702.4" + attribute \src "ls180.v:6738.1-6754.4" wire $0\builder_comb_rhs_array_muxed4[0:0] - attribute \src "ls180.v:6703.1-6719.4" + attribute \src "ls180.v:6755.1-6771.4" wire $0\builder_comb_rhs_array_muxed5[0:0] - attribute \src "ls180.v:6771.1-6787.4" + attribute \src "ls180.v:6823.1-6839.4" wire $0\builder_comb_rhs_array_muxed6[0:0] - attribute \src "ls180.v:6788.1-6804.4" + attribute \src "ls180.v:6840.1-6856.4" wire width 13 $0\builder_comb_rhs_array_muxed7[12:0] - attribute \src "ls180.v:6805.1-6821.4" + attribute \src "ls180.v:6857.1-6873.4" wire width 2 $0\builder_comb_rhs_array_muxed8[1:0] - attribute \src "ls180.v:6822.1-6838.4" + attribute \src "ls180.v:6874.1-6890.4" wire $0\builder_comb_rhs_array_muxed9[0:0] - attribute \src "ls180.v:6720.1-6736.4" + attribute \src "ls180.v:6772.1-6788.4" wire $0\builder_comb_t_array_muxed0[0:0] - attribute \src "ls180.v:6737.1-6753.4" + attribute \src "ls180.v:6789.1-6805.4" wire $0\builder_comb_t_array_muxed1[0:0] - attribute \src "ls180.v:6754.1-6770.4" + attribute \src "ls180.v:6806.1-6822.4" wire $0\builder_comb_t_array_muxed2[0:0] - attribute \src "ls180.v:6873.1-6889.4" + attribute \src "ls180.v:6925.1-6941.4" wire $0\builder_comb_t_array_muxed3[0:0] - attribute \src "ls180.v:6890.1-6906.4" + attribute \src "ls180.v:6942.1-6958.4" wire $0\builder_comb_t_array_muxed4[0:0] - attribute \src "ls180.v:6907.1-6923.4" + attribute \src "ls180.v:6959.1-6975.4" wire $0\builder_comb_t_array_muxed5[0:0] - attribute \src "ls180.v:2831.1-2877.4" + attribute \src "ls180.v:2844.1-2890.4" wire $0\builder_converter0_next_state[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\builder_converter0_state[0:0] - attribute \src "ls180.v:2891.1-2937.4" + attribute \src "ls180.v:2904.1-2950.4" wire $0\builder_converter1_next_state[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\builder_converter1_state[0:0] - attribute \src "ls180.v:2951.1-2997.4" + attribute \src "ls180.v:2964.1-3010.4" wire $0\builder_converter2_next_state[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\builder_converter2_state[0:0] - attribute \src "ls180.v:4114.1-4160.4" + attribute \src "ls180.v:4143.1-4189.4" wire $0\builder_converter_next_state[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\builder_converter_state[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 20 $0\builder_count[19:0] - attribute \src "ls180.v:5858.1-5869.4" + attribute \src "ls180.v:5910.1-5921.4" wire $0\builder_error[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 3 $0\builder_grant[2:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 8 $0\builder_interface0_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 8 $0\builder_interface10_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 8 $0\builder_interface11_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 8 $0\builder_interface12_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 8 $0\builder_interface13_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 8 $0\builder_interface14_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 8 $0\builder_interface1_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 8 $0\builder_interface2_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 8 $0\builder_interface3_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 8 $0\builder_interface4_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 8 $0\builder_interface5_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 8 $0\builder_interface6_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 8 $0\builder_interface7_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 8 $0\builder_interface8_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 8 $0\builder_interface9_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 14 $0\builder_libresocsim_adr[13:0] - attribute \src "ls180.v:5720.1-5756.4" + attribute \src "ls180.v:5772.1-5808.4" wire width 14 $0\builder_libresocsim_adr_next_value1[13:0] - attribute \src "ls180.v:5720.1-5756.4" + attribute \src "ls180.v:5772.1-5808.4" wire $0\builder_libresocsim_adr_next_value_ce1[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:1931.5-1931.55" + wire $0\builder_libresocsim_converted_interface_ack[0:0] + attribute \src "ls180.v:1927.12-1927.65" + wire width 64 $0\builder_libresocsim_converted_interface_dat_r[63:0] + attribute \src "ls180.v:1935.5-1935.55" + wire $0\builder_libresocsim_converted_interface_err[0:0] + attribute \src "ls180.v:7584.1-10223.4" wire width 8 $0\builder_libresocsim_dat_w[7:0] - attribute \src "ls180.v:5720.1-5756.4" + attribute \src "ls180.v:5772.1-5808.4" wire width 8 $0\builder_libresocsim_dat_w_next_value0[7:0] - attribute \src "ls180.v:5720.1-5756.4" + attribute \src "ls180.v:5772.1-5808.4" wire $0\builder_libresocsim_dat_w_next_value_ce0[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\builder_libresocsim_we[0:0] - attribute \src "ls180.v:5720.1-5756.4" + attribute \src "ls180.v:5772.1-5808.4" wire $0\builder_libresocsim_we_next_value2[0:0] - attribute \src "ls180.v:5720.1-5756.4" + attribute \src "ls180.v:5772.1-5808.4" wire $0\builder_libresocsim_we_next_value_ce2[0:0] - attribute \src "ls180.v:5720.1-5756.4" + attribute \src "ls180.v:5772.1-5808.4" wire $0\builder_libresocsim_wishbone_ack[0:0] - attribute \src "ls180.v:5720.1-5756.4" + attribute \src "ls180.v:1917.12-1917.52" + wire width 30 $0\builder_libresocsim_wishbone_adr[29:0] + attribute \src "ls180.v:1921.5-1921.44" + wire $0\builder_libresocsim_wishbone_cyc[0:0] + attribute \src "ls180.v:5772.1-5808.4" wire width 32 $0\builder_libresocsim_wishbone_dat_r[31:0] + attribute \src "ls180.v:1918.12-1918.54" + wire width 32 $0\builder_libresocsim_wishbone_dat_w[31:0] + attribute \src "ls180.v:1920.11-1920.50" + wire width 4 $0\builder_libresocsim_wishbone_sel[3:0] attribute \src "ls180.v:1922.5-1922.44" - wire $0\builder_libresocsim_wishbone_err[0:0] - attribute \src "ls180.v:1811.5-1811.27" + wire $0\builder_libresocsim_wishbone_stb[0:0] + attribute \src "ls180.v:1924.5-1924.43" + wire $0\builder_libresocsim_wishbone_we[0:0] + attribute \src "ls180.v:1816.5-1816.27" wire $0\builder_locked0[0:0] - attribute \src "ls180.v:1812.5-1812.27" + attribute \src "ls180.v:1817.5-1817.27" wire $0\builder_locked1[0:0] - attribute \src "ls180.v:1813.5-1813.27" + attribute \src "ls180.v:1818.5-1818.27" wire $0\builder_locked2[0:0] - attribute \src "ls180.v:1814.5-1814.27" + attribute \src "ls180.v:1819.5-1819.27" wire $0\builder_locked3[0:0] - attribute \src "ls180.v:3986.1-4058.4" + attribute \src "ls180.v:4015.1-4087.4" wire width 3 $0\builder_multiplexer_next_state[2:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 3 $0\builder_multiplexer_state[2:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\builder_multiregimpl0_regs0[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\builder_multiregimpl0_regs1[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\builder_multiregimpl10_regs0[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\builder_multiregimpl10_regs1[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\builder_multiregimpl11_regs0[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\builder_multiregimpl11_regs1[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\builder_multiregimpl12_regs0[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\builder_multiregimpl12_regs1[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\builder_multiregimpl13_regs0[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\builder_multiregimpl13_regs1[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\builder_multiregimpl14_regs0[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\builder_multiregimpl14_regs1[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\builder_multiregimpl15_regs0[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\builder_multiregimpl15_regs1[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\builder_multiregimpl16_regs0[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\builder_multiregimpl16_regs1[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\builder_multiregimpl1_regs0[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\builder_multiregimpl1_regs1[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\builder_multiregimpl2_regs0[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\builder_multiregimpl2_regs1[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\builder_multiregimpl3_regs0[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\builder_multiregimpl3_regs1[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\builder_multiregimpl4_regs0[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\builder_multiregimpl4_regs1[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\builder_multiregimpl5_regs0[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\builder_multiregimpl5_regs1[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\builder_multiregimpl6_regs0[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\builder_multiregimpl6_regs1[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\builder_multiregimpl7_regs0[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\builder_multiregimpl7_regs1[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\builder_multiregimpl8_regs0[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\builder_multiregimpl8_regs1[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\builder_multiregimpl9_regs0[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\builder_multiregimpl9_regs1[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\builder_new_master_rdata_valid0[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\builder_new_master_rdata_valid1[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\builder_new_master_rdata_valid2[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\builder_new_master_rdata_valid3[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\builder_new_master_wdata_ready[0:0] - attribute \src "ls180.v:5720.1-5756.4" + attribute \src "ls180.v:5772.1-5808.4" wire width 2 $0\builder_next_state[1:0] - attribute \src "ls180.v:3203.1-3233.4" + attribute \src "ls180.v:3232.1-3262.4" wire width 2 $0\builder_refresher_next_state[1:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 2 $0\builder_refresher_state[1:0] - attribute \src "ls180.v:5530.1-5569.4" + attribute \src "ls180.v:5570.1-5609.4" wire width 2 $0\builder_sdblock2memdma_next_state[1:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 2 $0\builder_sdblock2memdma_state[1:0] - attribute \src "ls180.v:5097.1-5176.4" + attribute \src "ls180.v:5137.1-5216.4" wire $0\builder_sdcore_crcupstreaminserter_next_state[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\builder_sdcore_crcupstreaminserter_state[0:0] - attribute \src "ls180.v:5279.1-5469.4" + attribute \src "ls180.v:5319.1-5509.4" wire width 3 $0\builder_sdcore_fsm_next_state[2:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 3 $0\builder_sdcore_fsm_state[2:0] - attribute \src "ls180.v:5589.1-5626.4" + attribute \src "ls180.v:5629.1-5666.4" wire $0\builder_sdmem2blockdma_fsm_next_state[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\builder_sdmem2blockdma_fsm_state[0:0] - attribute \src "ls180.v:5627.1-5663.4" + attribute \src "ls180.v:5667.1-5703.4" wire width 2 $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 2 $0\builder_sdmem2blockdma_resetinserter_state[1:0] - attribute \src "ls180.v:4772.1-4844.4" + attribute \src "ls180.v:4812.1-4884.4" wire width 3 $0\builder_sdphy_fsm_next_state[2:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 3 $0\builder_sdphy_fsm_state[2:0] - attribute \src "ls180.v:4617.1-4710.4" + attribute \src "ls180.v:4657.1-4750.4" wire width 3 $0\builder_sdphy_sdphycmdr_next_state[2:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 3 $0\builder_sdphy_sdphycmdr_state[2:0] - attribute \src "ls180.v:4507.1-4583.4" + attribute \src "ls180.v:4547.1-4623.4" wire width 2 $0\builder_sdphy_sdphycmdw_next_state[1:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 2 $0\builder_sdphy_sdphycmdw_state[1:0] - attribute \src "ls180.v:4744.1-4771.4" + attribute \src "ls180.v:4784.1-4811.4" wire $0\builder_sdphy_sdphycrcr_next_state[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\builder_sdphy_sdphycrcr_state[0:0] - attribute \src "ls180.v:4878.1-4979.4" + attribute \src "ls180.v:4918.1-5019.4" wire width 3 $0\builder_sdphy_sdphydatar_next_state[2:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 3 $0\builder_sdphy_sdphydatar_state[2:0] - attribute \src "ls180.v:4473.1-4506.4" + attribute \src "ls180.v:4513.1-4546.4" wire $0\builder_sdphy_sdphyinit_next_state[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\builder_sdphy_sdphyinit_state[0:0] - attribute \src "ls180.v:5858.1-5869.4" + attribute \src "ls180.v:5910.1-5921.4" wire $0\builder_shared_ack[0:0] - attribute \src "ls180.v:5858.1-5869.4" + attribute \src "ls180.v:5910.1-5921.4" wire width 32 $0\builder_shared_dat_r[31:0] - attribute \src "ls180.v:5781.1-5791.4" + attribute \src "ls180.v:5833.1-5843.4" wire width 8 $0\builder_slave_sel[7:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 8 $0\builder_slave_sel_r[7:0] - attribute \src "ls180.v:4304.1-4352.4" + attribute \src "ls180.v:4344.1-4392.4" wire width 2 $0\builder_spimaster0_next_state[1:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 2 $0\builder_spimaster0_state[1:0] - attribute \src "ls180.v:4363.1-4411.4" + attribute \src "ls180.v:4403.1-4451.4" wire width 2 $0\builder_spimaster1_next_state[1:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 2 $0\builder_spimaster1_state[1:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 2 $0\builder_state[1:0] - attribute \src "ls180.v:7299.1-7327.4" + attribute \src "ls180.v:7351.1-7379.4" wire $0\builder_sync_f_array_muxed0[0:0] - attribute \src "ls180.v:7328.1-7356.4" + attribute \src "ls180.v:7380.1-7408.4" wire $0\builder_sync_f_array_muxed1[0:0] - attribute \src "ls180.v:7180.1-7196.4" + attribute \src "ls180.v:7232.1-7248.4" wire width 2 $0\builder_sync_rhs_array_muxed0[1:0] - attribute \src "ls180.v:7197.1-7213.4" + attribute \src "ls180.v:7249.1-7265.4" wire width 13 $0\builder_sync_rhs_array_muxed1[12:0] - attribute \src "ls180.v:7214.1-7230.4" + attribute \src "ls180.v:7266.1-7282.4" wire $0\builder_sync_rhs_array_muxed2[0:0] - attribute \src "ls180.v:7231.1-7247.4" + attribute \src "ls180.v:7283.1-7299.4" wire $0\builder_sync_rhs_array_muxed3[0:0] - attribute \src "ls180.v:7248.1-7264.4" + attribute \src "ls180.v:7300.1-7316.4" wire $0\builder_sync_rhs_array_muxed4[0:0] - attribute \src "ls180.v:7265.1-7281.4" + attribute \src "ls180.v:7317.1-7333.4" wire $0\builder_sync_rhs_array_muxed5[0:0] - attribute \src "ls180.v:7282.1-7298.4" + attribute \src "ls180.v:7334.1-7350.4" wire $0\builder_sync_rhs_array_muxed6[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:4323.1-4327.4" + wire width 16 $0\gpio_o[15:0] + attribute \src "ls180.v:4328.1-4332.4" + wire width 16 $0\gpio_oe[15:0] + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_cmd_consumed[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" + wire $0\main_converter0_counter[0:0] + attribute \src "ls180.v:2844.1-2890.4" + wire $0\main_converter0_counter_converter0_next_value[0:0] + attribute \src "ls180.v:2844.1-2890.4" + wire $0\main_converter0_counter_converter0_next_value_ce[0:0] + attribute \src "ls180.v:7584.1-10223.4" + wire width 64 $0\main_converter0_dat_r[63:0] + attribute \src "ls180.v:2844.1-2890.4" + wire $0\main_converter0_skip[0:0] + attribute \src "ls180.v:7584.1-10223.4" + wire $0\main_converter1_counter[0:0] + attribute \src "ls180.v:2904.1-2950.4" + wire $0\main_converter1_counter_converter1_next_value[0:0] + attribute \src "ls180.v:2904.1-2950.4" + wire $0\main_converter1_counter_converter1_next_value_ce[0:0] + attribute \src "ls180.v:7584.1-10223.4" + wire width 64 $0\main_converter1_dat_r[63:0] + attribute \src "ls180.v:2904.1-2950.4" + wire $0\main_converter1_skip[0:0] + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_converter_counter[0:0] - attribute \src "ls180.v:4114.1-4160.4" + attribute \src "ls180.v:4143.1-4189.4" wire $0\main_converter_counter_converter_next_value[0:0] - attribute \src "ls180.v:4114.1-4160.4" + attribute \src "ls180.v:4143.1-4189.4" wire $0\main_converter_counter_converter_next_value_ce[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 32 $0\main_converter_dat_r[31:0] - attribute \src "ls180.v:4114.1-4160.4" + attribute \src "ls180.v:4143.1-4189.4" wire $0\main_converter_skip[0:0] - attribute \src "ls180.v:7457.1-7527.4" + attribute \src "ls180.v:7512.1-7582.4" wire width 16 $0\main_dfi_p0_rddata[15:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_dfi_p0_rddata_valid[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 24 $0\main_dummy[23:0] - attribute \src "ls180.v:7529.1-10156.4" - wire $0\main_gpio_oe_re[0:0] - attribute \src "ls180.v:7529.1-10156.4" - wire width 16 $0\main_gpio_oe_storage[15:0] - attribute \src "ls180.v:7529.1-10156.4" - wire $0\main_gpio_out_re[0:0] - attribute \src "ls180.v:7529.1-10156.4" - wire width 16 $0\main_gpio_out_storage[15:0] - attribute \src "ls180.v:7414.1-7432.4" - wire width 16 $0\main_gpio_status[15:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:1023.12-1023.53" + wire width 16 $0\main_gpiotristateasic0_oe_storage[15:0] + attribute \src "ls180.v:1025.12-1025.54" + wire width 16 $0\main_gpiotristateasic0_out_storage[15:0] + attribute \src "ls180.v:7466.1-7476.4" + wire width 16 $0\main_gpiotristateasic0_status[15:0] + attribute \src "ls180.v:7584.1-10223.4" + wire $0\main_gpiotristateasic1_oe_re[0:0] + attribute \src "ls180.v:7584.1-10223.4" + wire width 16 $0\main_gpiotristateasic1_oe_storage[15:0] + attribute \src "ls180.v:7584.1-10223.4" + wire $0\main_gpiotristateasic1_out_re[0:0] + attribute \src "ls180.v:7584.1-10223.4" + wire width 16 $0\main_gpiotristateasic1_out_storage[15:0] + attribute \src "ls180.v:7477.1-7487.4" + wire width 16 $0\main_gpiotristateasic1_status[15:0] + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_i2c_re[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 3 $0\main_i2c_storage[2:0] - attribute \src "ls180.v:7453.1-7455.4" + attribute \src "ls180.v:7508.1-7510.4" wire $0\main_int_rst[0:0] - attribute \src "ls180.v:1599.11-1599.41" + attribute \src "ls180.v:1604.11-1604.41" wire width 2 $0\main_interface0_bus_bte[1:0] - attribute \src "ls180.v:1598.11-1598.41" + attribute \src "ls180.v:1603.11-1603.41" wire width 3 $0\main_interface0_bus_cti[2:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:2844.1-2890.4" + wire $0\main_interface0_converted_interface_ack[0:0] + attribute \src "ls180.v:257.5-257.51" + wire $0\main_interface0_converted_interface_err[0:0] + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_interface0_ram_bus_ack[0:0] - attribute \src "ls180.v:255.5-255.39" + attribute \src "ls180.v:212.5-212.39" wire $0\main_interface0_ram_bus_err[0:0] - attribute \src "ls180.v:5589.1-5626.4" + attribute \src "ls180.v:5629.1-5666.4" wire width 32 $0\main_interface1_bus_adr[31:0] - attribute \src "ls180.v:1690.11-1690.41" + attribute \src "ls180.v:1695.11-1695.41" wire width 2 $0\main_interface1_bus_bte[1:0] - attribute \src "ls180.v:1689.11-1689.41" + attribute \src "ls180.v:1694.11-1694.41" wire width 3 $0\main_interface1_bus_cti[2:0] - attribute \src "ls180.v:5589.1-5626.4" + attribute \src "ls180.v:5629.1-5666.4" wire $0\main_interface1_bus_cyc[0:0] - attribute \src "ls180.v:1682.12-1682.45" - wire width 32 $0\main_interface1_bus_dat_w[31:0] - attribute \src "ls180.v:5589.1-5626.4" - wire width 4 $0\main_interface1_bus_sel[3:0] - attribute \src "ls180.v:5589.1-5626.4" + attribute \src "ls180.v:1687.12-1687.45" + wire width 64 $0\main_interface1_bus_dat_w[63:0] + attribute \src "ls180.v:5629.1-5666.4" + wire width 8 $0\main_interface1_bus_sel[7:0] + attribute \src "ls180.v:5629.1-5666.4" wire $0\main_interface1_bus_stb[0:0] - attribute \src "ls180.v:5589.1-5626.4" + attribute \src "ls180.v:5629.1-5666.4" wire $0\main_interface1_bus_we[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:2904.1-2950.4" + wire $0\main_interface1_converted_interface_ack[0:0] + attribute \src "ls180.v:272.5-272.51" + wire $0\main_interface1_converted_interface_err[0:0] + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_interface1_ram_bus_ack[0:0] - attribute \src "ls180.v:270.5-270.39" + attribute \src "ls180.v:227.5-227.39" wire $0\main_interface1_ram_bus_err[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_interface2_ram_bus_ack[0:0] - attribute \src "ls180.v:285.5-285.39" + attribute \src "ls180.v:242.5-242.39" wire $0\main_interface2_ram_bus_err[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 32 $0\main_libresocsim_bus_errors[31:0] - attribute \src "ls180.v:7529.1-10156.4" - wire $0\main_libresocsim_converter0_counter[0:0] - attribute \src "ls180.v:2831.1-2877.4" - wire $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] - attribute \src "ls180.v:2831.1-2877.4" - wire $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] - attribute \src "ls180.v:7529.1-10156.4" - wire width 64 $0\main_libresocsim_converter0_dat_r[63:0] - attribute \src "ls180.v:2831.1-2877.4" - wire $0\main_libresocsim_converter0_skip[0:0] - attribute \src "ls180.v:7529.1-10156.4" - wire $0\main_libresocsim_converter1_counter[0:0] - attribute \src "ls180.v:2891.1-2937.4" - wire $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] - attribute \src "ls180.v:2891.1-2937.4" - wire $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] - attribute \src "ls180.v:7529.1-10156.4" - wire width 64 $0\main_libresocsim_converter1_dat_r[63:0] - attribute \src "ls180.v:2891.1-2937.4" - wire $0\main_libresocsim_converter1_skip[0:0] - attribute \src "ls180.v:7529.1-10156.4" - wire $0\main_libresocsim_converter2_counter[0:0] - attribute \src "ls180.v:2951.1-2997.4" - wire $0\main_libresocsim_converter2_counter_converter2_next_value[0:0] - attribute \src "ls180.v:2951.1-2997.4" - wire $0\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] - attribute \src "ls180.v:7529.1-10156.4" - wire width 64 $0\main_libresocsim_converter2_dat_r[63:0] - attribute \src "ls180.v:2951.1-2997.4" - wire $0\main_libresocsim_converter2_skip[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_libresocsim_en_re[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_libresocsim_en_storage[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_libresocsim_eventmanager_re[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_libresocsim_eventmanager_storage[0:0] - attribute \src "ls180.v:2831.1-2877.4" - wire width 30 $0\main_libresocsim_interface0_converted_interface_adr[29:0] - attribute \src "ls180.v:167.11-167.69" - wire width 2 $0\main_libresocsim_interface0_converted_interface_bte[1:0] - attribute \src "ls180.v:166.11-166.69" - wire width 3 $0\main_libresocsim_interface0_converted_interface_cti[2:0] - attribute \src "ls180.v:2831.1-2877.4" - wire $0\main_libresocsim_interface0_converted_interface_cyc[0:0] - attribute \src "ls180.v:2819.1-2829.4" - wire width 32 $0\main_libresocsim_interface0_converted_interface_dat_w[31:0] - attribute \src "ls180.v:2831.1-2877.4" - wire width 4 $0\main_libresocsim_interface0_converted_interface_sel[3:0] - attribute \src "ls180.v:2831.1-2877.4" - wire $0\main_libresocsim_interface0_converted_interface_stb[0:0] - attribute \src "ls180.v:2831.1-2877.4" - wire $0\main_libresocsim_interface0_converted_interface_we[0:0] - attribute \src "ls180.v:2891.1-2937.4" - wire width 30 $0\main_libresocsim_interface1_converted_interface_adr[29:0] - attribute \src "ls180.v:182.11-182.69" - wire width 2 $0\main_libresocsim_interface1_converted_interface_bte[1:0] - attribute \src "ls180.v:181.11-181.69" - wire width 3 $0\main_libresocsim_interface1_converted_interface_cti[2:0] - attribute \src "ls180.v:2891.1-2937.4" - wire $0\main_libresocsim_interface1_converted_interface_cyc[0:0] - attribute \src "ls180.v:2879.1-2889.4" - wire width 32 $0\main_libresocsim_interface1_converted_interface_dat_w[31:0] - attribute \src "ls180.v:2891.1-2937.4" - wire width 4 $0\main_libresocsim_interface1_converted_interface_sel[3:0] - attribute \src "ls180.v:2891.1-2937.4" - wire $0\main_libresocsim_interface1_converted_interface_stb[0:0] - attribute \src "ls180.v:2891.1-2937.4" - wire $0\main_libresocsim_interface1_converted_interface_we[0:0] - attribute \src "ls180.v:2951.1-2997.4" - wire width 30 $0\main_libresocsim_interface2_converted_interface_adr[29:0] - attribute \src "ls180.v:197.11-197.69" - wire width 2 $0\main_libresocsim_interface2_converted_interface_bte[1:0] - attribute \src "ls180.v:196.11-196.69" - wire width 3 $0\main_libresocsim_interface2_converted_interface_cti[2:0] - attribute \src "ls180.v:2951.1-2997.4" - wire $0\main_libresocsim_interface2_converted_interface_cyc[0:0] - attribute \src "ls180.v:2939.1-2949.4" - wire width 32 $0\main_libresocsim_interface2_converted_interface_dat_w[31:0] - attribute \src "ls180.v:2951.1-2997.4" - wire width 4 $0\main_libresocsim_interface2_converted_interface_sel[3:0] - attribute \src "ls180.v:2951.1-2997.4" - wire $0\main_libresocsim_interface2_converted_interface_stb[0:0] - attribute \src "ls180.v:2951.1-2997.4" - wire $0\main_libresocsim_interface2_converted_interface_we[0:0] - attribute \src "ls180.v:2891.1-2937.4" - wire $0\main_libresocsim_libresoc_dbus_ack[0:0] - attribute \src "ls180.v:74.5-74.46" - wire $0\main_libresocsim_libresoc_dbus_err[0:0] - attribute \src "ls180.v:2831.1-2877.4" - wire $0\main_libresocsim_libresoc_ibus_ack[0:0] - attribute \src "ls180.v:83.5-83.46" - wire $0\main_libresocsim_libresoc_ibus_err[0:0] - attribute \src "ls180.v:2812.1-2817.4" + attribute \src "ls180.v:75.11-75.52" + wire width 2 $0\main_libresocsim_libresoc_dbus_bte[1:0] + attribute \src "ls180.v:74.11-74.52" + wire width 3 $0\main_libresocsim_libresoc_dbus_cti[2:0] + attribute \src "ls180.v:86.11-86.52" + wire width 2 $0\main_libresocsim_libresoc_ibus_bte[1:0] + attribute \src "ls180.v:85.11-85.52" + wire width 3 $0\main_libresocsim_libresoc_ibus_cti[2:0] + attribute \src "ls180.v:2825.1-2830.4" wire width 16 $0\main_libresocsim_libresoc_interrupt[15:0] - attribute \src "ls180.v:2951.1-2997.4" - wire $0\main_libresocsim_libresoc_jtag_wb_ack[0:0] - attribute \src "ls180.v:114.5-114.49" - wire $0\main_libresocsim_libresoc_jtag_wb_err[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:115.11-115.55" + wire width 2 $0\main_libresocsim_libresoc_jtag_wb_bte[1:0] + attribute \src "ls180.v:114.11-114.55" + wire width 3 $0\main_libresocsim_libresoc_jtag_wb_cti[2:0] + attribute \src "ls180.v:2844.1-2890.4" + wire width 30 $0\main_libresocsim_libresoc_xics_icp_adr[29:0] + attribute \src "ls180.v:2844.1-2890.4" + wire $0\main_libresocsim_libresoc_xics_icp_cyc[0:0] + attribute \src "ls180.v:2832.1-2842.4" + wire width 32 $0\main_libresocsim_libresoc_xics_icp_dat_w[31:0] + attribute \src "ls180.v:2844.1-2890.4" + wire width 4 $0\main_libresocsim_libresoc_xics_icp_sel[3:0] + attribute \src "ls180.v:2844.1-2890.4" + wire $0\main_libresocsim_libresoc_xics_icp_stb[0:0] + attribute \src "ls180.v:2844.1-2890.4" + wire $0\main_libresocsim_libresoc_xics_icp_we[0:0] + attribute \src "ls180.v:2904.1-2950.4" + wire width 30 $0\main_libresocsim_libresoc_xics_ics_adr[29:0] + attribute \src "ls180.v:2904.1-2950.4" + wire $0\main_libresocsim_libresoc_xics_ics_cyc[0:0] + attribute \src "ls180.v:2892.1-2902.4" + wire width 32 $0\main_libresocsim_libresoc_xics_ics_dat_w[31:0] + attribute \src "ls180.v:2904.1-2950.4" + wire width 4 $0\main_libresocsim_libresoc_xics_ics_sel[3:0] + attribute \src "ls180.v:2904.1-2950.4" + wire $0\main_libresocsim_libresoc_xics_ics_stb[0:0] + attribute \src "ls180.v:2904.1-2950.4" + wire $0\main_libresocsim_libresoc_xics_ics_we[0:0] + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_libresocsim_load_re[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 32 $0\main_libresocsim_load_storage[31:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_libresocsim_ram_bus_ack[0:0] - attribute \src "ls180.v:213.5-213.40" + attribute \src "ls180.v:170.5-170.40" wire $0\main_libresocsim_ram_bus_err[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_libresocsim_reload_re[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 32 $0\main_libresocsim_reload_storage[31:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_libresocsim_reset_re[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_libresocsim_reset_storage[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_libresocsim_scratch_re[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 32 $0\main_libresocsim_scratch_storage[31:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_libresocsim_update_value_re[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_libresocsim_update_value_storage[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 32 $0\main_libresocsim_value[31:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 32 $0\main_libresocsim_value_status[31:0] - attribute \src "ls180.v:3000.1-3006.4" - wire width 4 $0\main_libresocsim_we[3:0] - attribute \src "ls180.v:3012.1-3017.4" + attribute \src "ls180.v:3013.1-3023.4" + wire width 8 $0\main_libresocsim_we[7:0] + attribute \src "ls180.v:3029.1-3034.4" wire $0\main_libresocsim_zero_clear[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_libresocsim_zero_old_trigger[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_libresocsim_zero_pending[0:0] - attribute \src "ls180.v:4114.1-4160.4" + attribute \src "ls180.v:4143.1-4189.4" wire width 30 $0\main_litedram_wb_adr[29:0] - attribute \src "ls180.v:4114.1-4160.4" + attribute \src "ls180.v:4143.1-4189.4" wire $0\main_litedram_wb_cyc[0:0] - attribute \src "ls180.v:4102.1-4112.4" + attribute \src "ls180.v:4131.1-4141.4" wire width 16 $0\main_litedram_wb_dat_w[15:0] - attribute \src "ls180.v:4114.1-4160.4" + attribute \src "ls180.v:4143.1-4189.4" wire width 2 $0\main_litedram_wb_sel[1:0] - attribute \src "ls180.v:4114.1-4160.4" + attribute \src "ls180.v:4143.1-4189.4" wire $0\main_litedram_wb_stb[0:0] - attribute \src "ls180.v:4114.1-4160.4" + attribute \src "ls180.v:4143.1-4189.4" wire $0\main_litedram_wb_we[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 32 $0\main_pwm0_counter[31:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_pwm0_enable_re[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_pwm0_enable_storage[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_pwm0_period_re[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 32 $0\main_pwm0_period_storage[31:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_pwm0_width_re[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 32 $0\main_pwm0_width_storage[31:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 32 $0\main_pwm1_counter[31:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_pwm1_enable_re[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_pwm1_enable_storage[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_pwm1_period_re[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 32 $0\main_pwm1_period_storage[31:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_pwm1_width_re[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 32 $0\main_pwm1_width_storage[31:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 3 $0\main_rddata_en[2:0] - attribute \src "ls180.v:7529.1-10156.4" - wire width 2 $0\main_sdblock2mem_converter_demux[1:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" + wire width 3 $0\main_sdblock2mem_converter_demux[2:0] + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdblock2mem_converter_source_first[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdblock2mem_converter_source_last[0:0] - attribute \src "ls180.v:7529.1-10156.4" - wire width 32 $0\main_sdblock2mem_converter_source_payload_data[31:0] - attribute \src "ls180.v:7529.1-10156.4" - wire width 3 $0\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" + wire width 64 $0\main_sdblock2mem_converter_source_payload_data[63:0] + attribute \src "ls180.v:7584.1-10223.4" + wire width 4 $0\main_sdblock2mem_converter_source_payload_valid_token_count[3:0] + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdblock2mem_converter_strobe_all[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 5 $0\main_sdblock2mem_fifo_consume[4:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 6 $0\main_sdblock2mem_fifo_level[5:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 5 $0\main_sdblock2mem_fifo_produce[4:0] - attribute \src "ls180.v:1623.5-1623.41" + attribute \src "ls180.v:1628.5-1628.41" wire $0\main_sdblock2mem_fifo_replace[0:0] - attribute \src "ls180.v:5497.1-5504.4" + attribute \src "ls180.v:5537.1-5544.4" wire width 5 $0\main_sdblock2mem_fifo_wrport_adr[4:0] - attribute \src "ls180.v:5530.1-5569.4" + attribute \src "ls180.v:5570.1-5609.4" wire width 32 $0\main_sdblock2mem_sink_sink_payload_address[31:0] - attribute \src "ls180.v:5530.1-5569.4" - wire width 32 $0\main_sdblock2mem_sink_sink_payload_data1[31:0] - attribute \src "ls180.v:5530.1-5569.4" + attribute \src "ls180.v:5570.1-5609.4" + wire width 64 $0\main_sdblock2mem_sink_sink_payload_data1[63:0] + attribute \src "ls180.v:5570.1-5609.4" wire $0\main_sdblock2mem_sink_sink_valid1[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdblock2mem_wishbonedmawriter_base_re[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 64 $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdblock2mem_wishbonedmawriter_length_re[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 32 $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 32 $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] - attribute \src "ls180.v:5530.1-5569.4" + attribute \src "ls180.v:5570.1-5609.4" wire width 32 $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] - attribute \src "ls180.v:5530.1-5569.4" + attribute \src "ls180.v:5570.1-5609.4" wire $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] - attribute \src "ls180.v:5530.1-5569.4" + attribute \src "ls180.v:5570.1-5609.4" wire $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] - attribute \src "ls180.v:5530.1-5569.4" + attribute \src "ls180.v:5570.1-5609.4" wire $0\main_sdblock2mem_wishbonedmawriter_status[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdcore_block_count_re[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 32 $0\main_sdcore_block_count_storage[31:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdcore_block_length_re[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 10 $0\main_sdcore_block_length_storage[9:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdcore_cmd_argument_re[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 32 $0\main_sdcore_cmd_argument_storage[31:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdcore_cmd_command_re[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 32 $0\main_sdcore_cmd_command_storage[31:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 3 $0\main_sdcore_cmd_count[2:0] - attribute \src "ls180.v:5279.1-5469.4" + attribute \src "ls180.v:5319.1-5509.4" wire width 3 $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] - attribute \src "ls180.v:5279.1-5469.4" + attribute \src "ls180.v:5319.1-5509.4" wire $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdcore_cmd_done[0:0] - attribute \src "ls180.v:5279.1-5469.4" + attribute \src "ls180.v:5319.1-5509.4" wire $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] - attribute \src "ls180.v:5279.1-5469.4" + attribute \src "ls180.v:5319.1-5509.4" wire $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdcore_cmd_error[0:0] - attribute \src "ls180.v:5279.1-5469.4" + attribute \src "ls180.v:5319.1-5509.4" wire $0\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] - attribute \src "ls180.v:5279.1-5469.4" + attribute \src "ls180.v:5319.1-5509.4" wire $0\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 128 $0\main_sdcore_cmd_response_status[127:0] - attribute \src "ls180.v:5279.1-5469.4" + attribute \src "ls180.v:5319.1-5509.4" wire width 128 $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] - attribute \src "ls180.v:5279.1-5469.4" + attribute \src "ls180.v:5319.1-5509.4" wire $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] - attribute \src "ls180.v:1432.5-1432.34" + attribute \src "ls180.v:1437.5-1437.34" wire $0\main_sdcore_cmd_send_w[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdcore_cmd_timeout[0:0] - attribute \src "ls180.v:5279.1-5469.4" + attribute \src "ls180.v:5319.1-5509.4" wire $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] - attribute \src "ls180.v:5279.1-5469.4" + attribute \src "ls180.v:5319.1-5509.4" wire $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 4 $0\main_sdcore_crc16_checker_cnt[3:0] - attribute \src "ls180.v:5185.1-5192.4" + attribute \src "ls180.v:5225.1-5232.4" wire $0\main_sdcore_crc16_checker_crc0_clr[0:0] - attribute \src "ls180.v:5241.1-5248.4" + attribute \src "ls180.v:5281.1-5288.4" wire width 16 $0\main_sdcore_crc16_checker_crc0_crc[15:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 16 $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] - attribute \src "ls180.v:5195.1-5202.4" + attribute \src "ls180.v:5235.1-5242.4" wire $0\main_sdcore_crc16_checker_crc1_clr[0:0] - attribute \src "ls180.v:5251.1-5258.4" + attribute \src "ls180.v:5291.1-5298.4" wire width 16 $0\main_sdcore_crc16_checker_crc1_crc[15:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 16 $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] - attribute \src "ls180.v:5205.1-5212.4" + attribute \src "ls180.v:5245.1-5252.4" wire $0\main_sdcore_crc16_checker_crc2_clr[0:0] - attribute \src "ls180.v:5261.1-5268.4" + attribute \src "ls180.v:5301.1-5308.4" wire width 16 $0\main_sdcore_crc16_checker_crc2_crc[15:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 16 $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] - attribute \src "ls180.v:5215.1-5222.4" + attribute \src "ls180.v:5255.1-5262.4" wire $0\main_sdcore_crc16_checker_crc3_clr[0:0] - attribute \src "ls180.v:5271.1-5278.4" + attribute \src "ls180.v:5311.1-5318.4" wire width 16 $0\main_sdcore_crc16_checker_crc3_crc[15:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 16 $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 16 $0\main_sdcore_crc16_checker_crctmp0[15:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 16 $0\main_sdcore_crc16_checker_crctmp1[15:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 16 $0\main_sdcore_crc16_checker_crctmp2[15:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 16 $0\main_sdcore_crc16_checker_crctmp3[15:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 16 $0\main_sdcore_crc16_checker_fifo0[15:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 16 $0\main_sdcore_crc16_checker_fifo1[15:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 16 $0\main_sdcore_crc16_checker_fifo2[15:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 16 $0\main_sdcore_crc16_checker_fifo3[15:0] - attribute \src "ls180.v:5279.1-5469.4" + attribute \src "ls180.v:5319.1-5509.4" wire $0\main_sdcore_crc16_checker_sink_first[0:0] - attribute \src "ls180.v:5279.1-5469.4" + attribute \src "ls180.v:5319.1-5509.4" wire $0\main_sdcore_crc16_checker_sink_last[0:0] - attribute \src "ls180.v:5279.1-5469.4" + attribute \src "ls180.v:5319.1-5509.4" wire width 8 $0\main_sdcore_crc16_checker_sink_payload_data[7:0] - attribute \src "ls180.v:5230.1-5237.4" + attribute \src "ls180.v:5270.1-5277.4" wire $0\main_sdcore_crc16_checker_sink_ready[0:0] - attribute \src "ls180.v:5279.1-5469.4" + attribute \src "ls180.v:5319.1-5509.4" wire $0\main_sdcore_crc16_checker_sink_valid[0:0] - attribute \src "ls180.v:1538.5-1538.50" + attribute \src "ls180.v:1543.5-1543.50" wire $0\main_sdcore_crc16_checker_source_first[0:0] - attribute \src "ls180.v:5224.1-5229.4" + attribute \src "ls180.v:5264.1-5269.4" wire $0\main_sdcore_crc16_checker_source_valid[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 8 $0\main_sdcore_crc16_checker_val[7:0] - attribute \src "ls180.v:5177.1-5182.4" + attribute \src "ls180.v:5217.1-5222.4" wire $0\main_sdcore_crc16_checker_valid[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 3 $0\main_sdcore_crc16_inserter_cnt[2:0] - attribute \src "ls180.v:5097.1-5176.4" + attribute \src "ls180.v:5137.1-5216.4" wire width 3 $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] - attribute \src "ls180.v:5097.1-5176.4" + attribute \src "ls180.v:5137.1-5216.4" wire $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] - attribute \src "ls180.v:5059.1-5066.4" + attribute \src "ls180.v:5099.1-5106.4" wire width 16 $0\main_sdcore_crc16_inserter_crc0_crc[15:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 16 $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] - attribute \src "ls180.v:5069.1-5076.4" + attribute \src "ls180.v:5109.1-5116.4" wire width 16 $0\main_sdcore_crc16_inserter_crc1_crc[15:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 16 $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] - attribute \src "ls180.v:5079.1-5086.4" + attribute \src "ls180.v:5119.1-5126.4" wire width 16 $0\main_sdcore_crc16_inserter_crc2_crc[15:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 16 $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] - attribute \src "ls180.v:5089.1-5096.4" + attribute \src "ls180.v:5129.1-5136.4" wire width 16 $0\main_sdcore_crc16_inserter_crc3_crc[15:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 16 $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 16 $0\main_sdcore_crc16_inserter_crctmp0[15:0] - attribute \src "ls180.v:5097.1-5176.4" + attribute \src "ls180.v:5137.1-5216.4" wire width 16 $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] - attribute \src "ls180.v:5097.1-5176.4" + attribute \src "ls180.v:5137.1-5216.4" wire $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 16 $0\main_sdcore_crc16_inserter_crctmp1[15:0] - attribute \src "ls180.v:5097.1-5176.4" + attribute \src "ls180.v:5137.1-5216.4" wire width 16 $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] - attribute \src "ls180.v:5097.1-5176.4" + attribute \src "ls180.v:5137.1-5216.4" wire $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 16 $0\main_sdcore_crc16_inserter_crctmp2[15:0] - attribute \src "ls180.v:5097.1-5176.4" + attribute \src "ls180.v:5137.1-5216.4" wire width 16 $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] - attribute \src "ls180.v:5097.1-5176.4" + attribute \src "ls180.v:5137.1-5216.4" wire $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 16 $0\main_sdcore_crc16_inserter_crctmp3[15:0] - attribute \src "ls180.v:5097.1-5176.4" + attribute \src "ls180.v:5137.1-5216.4" wire width 16 $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] - attribute \src "ls180.v:5097.1-5176.4" + attribute \src "ls180.v:5137.1-5216.4" wire $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] - attribute \src "ls180.v:5097.1-5176.4" + attribute \src "ls180.v:5137.1-5216.4" wire $0\main_sdcore_crc16_inserter_sink_ready[0:0] - attribute \src "ls180.v:1495.5-1495.51" + attribute \src "ls180.v:1500.5-1500.51" wire $0\main_sdcore_crc16_inserter_source_first[0:0] - attribute \src "ls180.v:5097.1-5176.4" + attribute \src "ls180.v:5137.1-5216.4" wire $0\main_sdcore_crc16_inserter_source_last[0:0] - attribute \src "ls180.v:5097.1-5176.4" + attribute \src "ls180.v:5137.1-5216.4" wire width 8 $0\main_sdcore_crc16_inserter_source_payload_data[7:0] - attribute \src "ls180.v:5279.1-5469.4" + attribute \src "ls180.v:5319.1-5509.4" wire $0\main_sdcore_crc16_inserter_source_ready[0:0] - attribute \src "ls180.v:5097.1-5176.4" + attribute \src "ls180.v:5137.1-5216.4" wire $0\main_sdcore_crc16_inserter_source_valid[0:0] - attribute \src "ls180.v:5037.1-5044.4" + attribute \src "ls180.v:5077.1-5084.4" wire width 7 $0\main_sdcore_crc7_inserter_crc[6:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 7 $0\main_sdcore_crc7_inserter_crcreg0[6:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 32 $0\main_sdcore_data_count[31:0] - attribute \src "ls180.v:5279.1-5469.4" + attribute \src "ls180.v:5319.1-5509.4" wire width 32 $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] - attribute \src "ls180.v:5279.1-5469.4" + attribute \src "ls180.v:5319.1-5509.4" wire $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdcore_data_done[0:0] - attribute \src "ls180.v:5279.1-5469.4" + attribute \src "ls180.v:5319.1-5509.4" wire $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] - attribute \src "ls180.v:5279.1-5469.4" + attribute \src "ls180.v:5319.1-5509.4" wire $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdcore_data_error[0:0] - attribute \src "ls180.v:5279.1-5469.4" + attribute \src "ls180.v:5319.1-5509.4" wire $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] - attribute \src "ls180.v:5279.1-5469.4" + attribute \src "ls180.v:5319.1-5509.4" wire $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdcore_data_timeout[0:0] - attribute \src "ls180.v:5279.1-5469.4" + attribute \src "ls180.v:5319.1-5509.4" wire $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] - attribute \src "ls180.v:5279.1-5469.4" + attribute \src "ls180.v:5319.1-5509.4" wire $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] - attribute \src "ls180.v:7529.1-10156.4" - wire width 2 $0\main_sdmem2block_converter_mux[1:0] - attribute \src "ls180.v:5675.1-5691.4" + attribute \src "ls180.v:7584.1-10223.4" + wire width 3 $0\main_sdmem2block_converter_mux[2:0] + attribute \src "ls180.v:5715.1-5743.4" wire width 8 $0\main_sdmem2block_converter_source_payload_data[7:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdmem2block_dma_base_re[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 64 $0\main_sdmem2block_dma_base_storage[63:0] - attribute \src "ls180.v:7529.1-10156.4" - wire width 32 $0\main_sdmem2block_dma_data[31:0] - attribute \src "ls180.v:5589.1-5626.4" - wire width 32 $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] - attribute \src "ls180.v:5589.1-5626.4" + attribute \src "ls180.v:7584.1-10223.4" + wire width 64 $0\main_sdmem2block_dma_data[63:0] + attribute \src "ls180.v:5629.1-5666.4" + wire width 64 $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[63:0] + attribute \src "ls180.v:5629.1-5666.4" wire $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] - attribute \src "ls180.v:5627.1-5663.4" + attribute \src "ls180.v:5667.1-5703.4" wire $0\main_sdmem2block_dma_done_status[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdmem2block_dma_enable_re[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdmem2block_dma_enable_storage[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdmem2block_dma_length_re[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 32 $0\main_sdmem2block_dma_length_storage[31:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdmem2block_dma_loop_re[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdmem2block_dma_loop_storage[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 32 $0\main_sdmem2block_dma_offset[31:0] - attribute \src "ls180.v:5627.1-5663.4" + attribute \src "ls180.v:5667.1-5703.4" wire width 32 $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] - attribute \src "ls180.v:5627.1-5663.4" + attribute \src "ls180.v:5667.1-5703.4" wire $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] - attribute \src "ls180.v:5627.1-5663.4" + attribute \src "ls180.v:5667.1-5703.4" wire $0\main_sdmem2block_dma_sink_last[0:0] - attribute \src "ls180.v:5627.1-5663.4" + attribute \src "ls180.v:5667.1-5703.4" wire width 32 $0\main_sdmem2block_dma_sink_payload_address[31:0] - attribute \src "ls180.v:5589.1-5626.4" + attribute \src "ls180.v:5629.1-5666.4" wire $0\main_sdmem2block_dma_sink_ready[0:0] - attribute \src "ls180.v:5627.1-5663.4" + attribute \src "ls180.v:5667.1-5703.4" wire $0\main_sdmem2block_dma_sink_valid[0:0] - attribute \src "ls180.v:1703.5-1703.45" + attribute \src "ls180.v:1708.5-1708.45" wire $0\main_sdmem2block_dma_source_first[0:0] - attribute \src "ls180.v:5589.1-5626.4" + attribute \src "ls180.v:5629.1-5666.4" wire $0\main_sdmem2block_dma_source_last[0:0] - attribute \src "ls180.v:5589.1-5626.4" - wire width 32 $0\main_sdmem2block_dma_source_payload_data[31:0] - attribute \src "ls180.v:5589.1-5626.4" + attribute \src "ls180.v:5629.1-5666.4" + wire width 64 $0\main_sdmem2block_dma_source_payload_data[63:0] + attribute \src "ls180.v:5629.1-5666.4" wire $0\main_sdmem2block_dma_source_valid[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 5 $0\main_sdmem2block_fifo_consume[4:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 6 $0\main_sdmem2block_fifo_level[5:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 5 $0\main_sdmem2block_fifo_produce[4:0] - attribute \src "ls180.v:1759.5-1759.41" + attribute \src "ls180.v:1764.5-1764.41" wire $0\main_sdmem2block_fifo_replace[0:0] - attribute \src "ls180.v:5705.1-5712.4" + attribute \src "ls180.v:5757.1-5764.4" wire width 5 $0\main_sdmem2block_fifo_wrport_adr[4:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdphy_clocker_clk0[0:0] - attribute \src "ls180.v:4443.1-4471.4" + attribute \src "ls180.v:4483.1-4511.4" wire $0\main_sdphy_clocker_clk1[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdphy_clocker_clk_d[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 9 $0\main_sdphy_clocker_clks[8:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdphy_clocker_re[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 9 $0\main_sdphy_clocker_storage[8:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdphy_cmdr_cmdr_buf_source_first[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdphy_cmdr_cmdr_buf_source_last[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 8 $0\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 3 $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] - attribute \src "ls180.v:1224.5-1224.53" + attribute \src "ls180.v:1229.5-1229.53" wire $0\main_sdphy_cmdr_cmdr_converter_sink_first[0:0] - attribute \src "ls180.v:1225.5-1225.52" + attribute \src "ls180.v:1230.5-1230.52" wire $0\main_sdphy_cmdr_cmdr_converter_sink_last[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 8 $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 4 $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] - attribute \src "ls180.v:1205.5-1205.46" + attribute \src "ls180.v:1210.5-1210.46" wire $0\main_sdphy_cmdr_cmdr_pads_in_ready[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdphy_cmdr_cmdr_reset[0:0] - attribute \src "ls180.v:4617.1-4710.4" + attribute \src "ls180.v:4657.1-4750.4" wire $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] - attribute \src "ls180.v:4617.1-4710.4" + attribute \src "ls180.v:4657.1-4750.4" wire $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdphy_cmdr_cmdr_run[0:0] - attribute \src "ls180.v:4617.1-4710.4" + attribute \src "ls180.v:4657.1-4750.4" wire $0\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 8 $0\main_sdphy_cmdr_count[7:0] - attribute \src "ls180.v:4617.1-4710.4" + attribute \src "ls180.v:4657.1-4750.4" wire width 8 $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] - attribute \src "ls180.v:4617.1-4710.4" + attribute \src "ls180.v:4657.1-4750.4" wire $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] - attribute \src "ls180.v:1178.5-1178.49" + attribute \src "ls180.v:1183.5-1183.49" wire $0\main_sdphy_cmdr_pads_in_pads_in_first[0:0] - attribute \src "ls180.v:1179.5-1179.48" + attribute \src "ls180.v:1184.5-1184.48" wire $0\main_sdphy_cmdr_pads_in_pads_in_last[0:0] - attribute \src "ls180.v:1180.5-1180.55" + attribute \src "ls180.v:1185.5-1185.55" wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_clk[0:0] - attribute \src "ls180.v:1182.5-1182.57" + attribute \src "ls180.v:1187.5-1187.57" wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o[0:0] - attribute \src "ls180.v:1183.5-1183.58" + attribute \src "ls180.v:1188.5-1188.58" wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe[0:0] - attribute \src "ls180.v:1185.11-1185.64" + attribute \src "ls180.v:1190.11-1190.64" wire width 4 $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_o[3:0] - attribute \src "ls180.v:1186.5-1186.59" + attribute \src "ls180.v:1191.5-1191.59" wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_oe[0:0] - attribute \src "ls180.v:4617.1-4710.4" + attribute \src "ls180.v:4657.1-4750.4" wire $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] - attribute \src "ls180.v:4617.1-4710.4" + attribute \src "ls180.v:4657.1-4750.4" wire $0\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:4617.1-4710.4" + attribute \src "ls180.v:4657.1-4750.4" wire $0\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:1191.11-1191.57" + attribute \src "ls180.v:1196.11-1196.57" wire width 4 $0\main_sdphy_cmdr_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:1192.5-1192.52" + attribute \src "ls180.v:1197.5-1197.52" wire $0\main_sdphy_cmdr_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:5279.1-5469.4" + attribute \src "ls180.v:5319.1-5509.4" wire $0\main_sdphy_cmdr_sink_last[0:0] - attribute \src "ls180.v:5279.1-5469.4" + attribute \src "ls180.v:5319.1-5509.4" wire width 8 $0\main_sdphy_cmdr_sink_payload_length[7:0] - attribute \src "ls180.v:4617.1-4710.4" + attribute \src "ls180.v:4657.1-4750.4" wire $0\main_sdphy_cmdr_sink_ready[0:0] - attribute \src "ls180.v:5279.1-5469.4" + attribute \src "ls180.v:5319.1-5509.4" wire $0\main_sdphy_cmdr_sink_valid[0:0] - attribute \src "ls180.v:4617.1-4710.4" + attribute \src "ls180.v:4657.1-4750.4" wire $0\main_sdphy_cmdr_source_last[0:0] - attribute \src "ls180.v:4617.1-4710.4" + attribute \src "ls180.v:4657.1-4750.4" wire width 8 $0\main_sdphy_cmdr_source_payload_data[7:0] - attribute \src "ls180.v:4617.1-4710.4" + attribute \src "ls180.v:4657.1-4750.4" wire width 3 $0\main_sdphy_cmdr_source_payload_status[2:0] - attribute \src "ls180.v:5279.1-5469.4" + attribute \src "ls180.v:5319.1-5509.4" wire $0\main_sdphy_cmdr_source_ready[0:0] - attribute \src "ls180.v:4617.1-4710.4" + attribute \src "ls180.v:4657.1-4750.4" wire $0\main_sdphy_cmdr_source_valid[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 32 $0\main_sdphy_cmdr_timeout[31:0] - attribute \src "ls180.v:4617.1-4710.4" + attribute \src "ls180.v:4657.1-4750.4" wire width 32 $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] - attribute \src "ls180.v:4617.1-4710.4" + attribute \src "ls180.v:4657.1-4750.4" wire $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 8 $0\main_sdphy_cmdw_count[7:0] - attribute \src "ls180.v:4507.1-4583.4" + attribute \src "ls180.v:4547.1-4623.4" wire width 8 $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] - attribute \src "ls180.v:4507.1-4583.4" + attribute \src "ls180.v:4547.1-4623.4" wire $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] - attribute \src "ls180.v:4507.1-4583.4" + attribute \src "ls180.v:4547.1-4623.4" wire $0\main_sdphy_cmdw_done[0:0] - attribute \src "ls180.v:4507.1-4583.4" + attribute \src "ls180.v:4547.1-4623.4" wire $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] - attribute \src "ls180.v:4507.1-4583.4" + attribute \src "ls180.v:4547.1-4623.4" wire $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:4507.1-4583.4" + attribute \src "ls180.v:4547.1-4623.4" wire $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:1168.11-1168.57" + attribute \src "ls180.v:1173.11-1173.57" wire width 4 $0\main_sdphy_cmdw_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:1169.5-1169.52" + attribute \src "ls180.v:1174.5-1174.52" wire $0\main_sdphy_cmdw_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:5279.1-5469.4" + attribute \src "ls180.v:5319.1-5509.4" wire $0\main_sdphy_cmdw_sink_last[0:0] - attribute \src "ls180.v:5279.1-5469.4" + attribute \src "ls180.v:5319.1-5509.4" wire width 8 $0\main_sdphy_cmdw_sink_payload_data[7:0] - attribute \src "ls180.v:4507.1-4583.4" + attribute \src "ls180.v:4547.1-4623.4" wire $0\main_sdphy_cmdw_sink_ready[0:0] - attribute \src "ls180.v:5279.1-5469.4" + attribute \src "ls180.v:5319.1-5509.4" wire $0\main_sdphy_cmdw_sink_valid[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 10 $0\main_sdphy_datar_count[9:0] - attribute \src "ls180.v:4878.1-4979.4" + attribute \src "ls180.v:4918.1-5019.4" wire width 10 $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] - attribute \src "ls180.v:4878.1-4979.4" + attribute \src "ls180.v:4918.1-5019.4" wire $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdphy_datar_datar_buf_source_first[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdphy_datar_datar_buf_source_last[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 8 $0\main_sdphy_datar_datar_buf_source_payload_data[7:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdphy_datar_datar_buf_source_valid[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdphy_datar_datar_converter_demux[0:0] - attribute \src "ls180.v:1380.5-1380.55" + attribute \src "ls180.v:1385.5-1385.55" wire $0\main_sdphy_datar_datar_converter_sink_first[0:0] - attribute \src "ls180.v:1381.5-1381.54" + attribute \src "ls180.v:1386.5-1386.54" wire $0\main_sdphy_datar_datar_converter_sink_last[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdphy_datar_datar_converter_source_first[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdphy_datar_datar_converter_source_last[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 8 $0\main_sdphy_datar_datar_converter_source_payload_data[7:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 2 $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdphy_datar_datar_converter_strobe_all[0:0] - attribute \src "ls180.v:1361.5-1361.48" + attribute \src "ls180.v:1366.5-1366.48" wire $0\main_sdphy_datar_datar_pads_in_ready[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdphy_datar_datar_reset[0:0] - attribute \src "ls180.v:4878.1-4979.4" + attribute \src "ls180.v:4918.1-5019.4" wire $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] - attribute \src "ls180.v:4878.1-4979.4" + attribute \src "ls180.v:4918.1-5019.4" wire $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdphy_datar_datar_run[0:0] - attribute \src "ls180.v:4878.1-4979.4" + attribute \src "ls180.v:4918.1-5019.4" wire $0\main_sdphy_datar_datar_source_source_ready0[0:0] - attribute \src "ls180.v:1332.5-1332.50" + attribute \src "ls180.v:1337.5-1337.50" wire $0\main_sdphy_datar_pads_in_pads_in_first[0:0] - attribute \src "ls180.v:1333.5-1333.49" + attribute \src "ls180.v:1338.5-1338.49" wire $0\main_sdphy_datar_pads_in_pads_in_last[0:0] - attribute \src "ls180.v:1334.5-1334.56" + attribute \src "ls180.v:1339.5-1339.56" wire $0\main_sdphy_datar_pads_in_pads_in_payload_clk[0:0] - attribute \src "ls180.v:1336.5-1336.58" + attribute \src "ls180.v:1341.5-1341.58" wire $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_o[0:0] - attribute \src "ls180.v:1337.5-1337.59" + attribute \src "ls180.v:1342.5-1342.59" wire $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_oe[0:0] - attribute \src "ls180.v:1339.11-1339.65" + attribute \src "ls180.v:1344.11-1344.65" wire width 4 $0\main_sdphy_datar_pads_in_pads_in_payload_data_o[3:0] - attribute \src "ls180.v:1340.5-1340.60" + attribute \src "ls180.v:1345.5-1345.60" wire $0\main_sdphy_datar_pads_in_pads_in_payload_data_oe[0:0] - attribute \src "ls180.v:4878.1-4979.4" + attribute \src "ls180.v:4918.1-5019.4" wire $0\main_sdphy_datar_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1343.5-1343.51" + attribute \src "ls180.v:1348.5-1348.51" wire $0\main_sdphy_datar_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:1344.5-1344.52" + attribute \src "ls180.v:1349.5-1349.52" wire $0\main_sdphy_datar_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:1345.11-1345.58" + attribute \src "ls180.v:1350.11-1350.58" wire width 4 $0\main_sdphy_datar_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:1346.5-1346.53" + attribute \src "ls180.v:1351.5-1351.53" wire $0\main_sdphy_datar_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:5279.1-5469.4" + attribute \src "ls180.v:5319.1-5509.4" wire $0\main_sdphy_datar_sink_last[0:0] - attribute \src "ls180.v:5279.1-5469.4" + attribute \src "ls180.v:5319.1-5509.4" wire width 10 $0\main_sdphy_datar_sink_payload_block_length[9:0] - attribute \src "ls180.v:4878.1-4979.4" + attribute \src "ls180.v:4918.1-5019.4" wire $0\main_sdphy_datar_sink_ready[0:0] - attribute \src "ls180.v:5279.1-5469.4" + attribute \src "ls180.v:5319.1-5509.4" wire $0\main_sdphy_datar_sink_valid[0:0] - attribute \src "ls180.v:1353.5-1353.41" + attribute \src "ls180.v:1358.5-1358.41" wire $0\main_sdphy_datar_source_first[0:0] - attribute \src "ls180.v:4878.1-4979.4" + attribute \src "ls180.v:4918.1-5019.4" wire $0\main_sdphy_datar_source_last[0:0] - attribute \src "ls180.v:4878.1-4979.4" + attribute \src "ls180.v:4918.1-5019.4" wire width 8 $0\main_sdphy_datar_source_payload_data[7:0] - attribute \src "ls180.v:4878.1-4979.4" + attribute \src "ls180.v:4918.1-5019.4" wire width 3 $0\main_sdphy_datar_source_payload_status[2:0] - attribute \src "ls180.v:5279.1-5469.4" + attribute \src "ls180.v:5319.1-5509.4" wire $0\main_sdphy_datar_source_ready[0:0] - attribute \src "ls180.v:4878.1-4979.4" + attribute \src "ls180.v:4918.1-5019.4" wire $0\main_sdphy_datar_source_valid[0:0] - attribute \src "ls180.v:4878.1-4979.4" + attribute \src "ls180.v:4918.1-5019.4" wire $0\main_sdphy_datar_stop[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 32 $0\main_sdphy_datar_timeout[31:0] - attribute \src "ls180.v:4878.1-4979.4" + attribute \src "ls180.v:4918.1-5019.4" wire width 32 $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] - attribute \src "ls180.v:4878.1-4979.4" + attribute \src "ls180.v:4918.1-5019.4" wire $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 8 $0\main_sdphy_dataw_count[7:0] - attribute \src "ls180.v:4772.1-4844.4" + attribute \src "ls180.v:4812.1-4884.4" wire width 8 $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] - attribute \src "ls180.v:4772.1-4844.4" + attribute \src "ls180.v:4812.1-4884.4" wire $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdphy_dataw_crcr_buf_source_first[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdphy_dataw_crcr_buf_source_last[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 8 $0\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 3 $0\main_sdphy_dataw_crcr_converter_demux[2:0] - attribute \src "ls180.v:1302.5-1302.54" + attribute \src "ls180.v:1307.5-1307.54" wire $0\main_sdphy_dataw_crcr_converter_sink_first[0:0] - attribute \src "ls180.v:1303.5-1303.53" + attribute \src "ls180.v:1308.5-1308.53" wire $0\main_sdphy_dataw_crcr_converter_sink_last[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdphy_dataw_crcr_converter_source_first[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdphy_dataw_crcr_converter_source_last[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 8 $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 4 $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] - attribute \src "ls180.v:1283.5-1283.47" + attribute \src "ls180.v:1288.5-1288.47" wire $0\main_sdphy_dataw_crcr_pads_in_ready[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdphy_dataw_crcr_reset[0:0] - attribute \src "ls180.v:4744.1-4771.4" + attribute \src "ls180.v:4784.1-4811.4" wire $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] - attribute \src "ls180.v:4744.1-4771.4" + attribute \src "ls180.v:4784.1-4811.4" wire $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdphy_dataw_crcr_run[0:0] - attribute \src "ls180.v:4744.1-4771.4" + attribute \src "ls180.v:4784.1-4811.4" wire $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] - attribute \src "ls180.v:4744.1-4771.4" + attribute \src "ls180.v:4784.1-4811.4" wire $0\main_sdphy_dataw_error[0:0] - attribute \src "ls180.v:1270.5-1270.50" + attribute \src "ls180.v:1275.5-1275.50" wire $0\main_sdphy_dataw_pads_in_pads_in_first[0:0] - attribute \src "ls180.v:1271.5-1271.49" + attribute \src "ls180.v:1276.5-1276.49" wire $0\main_sdphy_dataw_pads_in_pads_in_last[0:0] - attribute \src "ls180.v:1272.5-1272.56" + attribute \src "ls180.v:1277.5-1277.56" wire $0\main_sdphy_dataw_pads_in_pads_in_payload_clk[0:0] - attribute \src "ls180.v:1273.5-1273.58" + attribute \src "ls180.v:1278.5-1278.58" wire $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_i[0:0] - attribute \src "ls180.v:1274.5-1274.58" + attribute \src "ls180.v:1279.5-1279.58" wire $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_o[0:0] - attribute \src "ls180.v:1275.5-1275.59" + attribute \src "ls180.v:1280.5-1280.59" wire $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe[0:0] - attribute \src "ls180.v:1276.11-1276.65" + attribute \src "ls180.v:1281.11-1281.65" wire width 4 $0\main_sdphy_dataw_pads_in_pads_in_payload_data_i[3:0] - attribute \src "ls180.v:1277.11-1277.65" + attribute \src "ls180.v:1282.11-1282.65" wire width 4 $0\main_sdphy_dataw_pads_in_pads_in_payload_data_o[3:0] - attribute \src "ls180.v:1278.5-1278.60" + attribute \src "ls180.v:1283.5-1283.60" wire $0\main_sdphy_dataw_pads_in_pads_in_payload_data_oe[0:0] - attribute \src "ls180.v:1268.5-1268.50" + attribute \src "ls180.v:1273.5-1273.50" wire $0\main_sdphy_dataw_pads_in_pads_in_valid[0:0] - attribute \src "ls180.v:4772.1-4844.4" + attribute \src "ls180.v:4812.1-4884.4" wire $0\main_sdphy_dataw_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1257.5-1257.51" + attribute \src "ls180.v:1262.5-1262.51" wire $0\main_sdphy_dataw_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:1258.5-1258.52" + attribute \src "ls180.v:1263.5-1263.52" wire $0\main_sdphy_dataw_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:4772.1-4844.4" + attribute \src "ls180.v:4812.1-4884.4" wire width 4 $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:4772.1-4844.4" + attribute \src "ls180.v:4812.1-4884.4" wire $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:5279.1-5469.4" + attribute \src "ls180.v:5319.1-5509.4" wire $0\main_sdphy_dataw_sink_first[0:0] - attribute \src "ls180.v:5279.1-5469.4" + attribute \src "ls180.v:5319.1-5509.4" wire $0\main_sdphy_dataw_sink_last[0:0] - attribute \src "ls180.v:5279.1-5469.4" + attribute \src "ls180.v:5319.1-5509.4" wire width 8 $0\main_sdphy_dataw_sink_payload_data[7:0] - attribute \src "ls180.v:4772.1-4844.4" + attribute \src "ls180.v:4812.1-4884.4" wire $0\main_sdphy_dataw_sink_ready[0:0] - attribute \src "ls180.v:5279.1-5469.4" + attribute \src "ls180.v:5319.1-5509.4" wire $0\main_sdphy_dataw_sink_valid[0:0] - attribute \src "ls180.v:4772.1-4844.4" + attribute \src "ls180.v:4812.1-4884.4" wire $0\main_sdphy_dataw_start[0:0] - attribute \src "ls180.v:4772.1-4844.4" + attribute \src "ls180.v:4812.1-4884.4" wire $0\main_sdphy_dataw_stop[0:0] - attribute \src "ls180.v:4744.1-4771.4" + attribute \src "ls180.v:4784.1-4811.4" wire $0\main_sdphy_dataw_valid[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 8 $0\main_sdphy_init_count[7:0] - attribute \src "ls180.v:4473.1-4506.4" + attribute \src "ls180.v:4513.1-4546.4" wire width 8 $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] - attribute \src "ls180.v:4473.1-4506.4" + attribute \src "ls180.v:4513.1-4546.4" wire $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] - attribute \src "ls180.v:1150.5-1150.40" + attribute \src "ls180.v:1155.5-1155.40" wire $0\main_sdphy_init_initialize_w[0:0] - attribute \src "ls180.v:4473.1-4506.4" + attribute \src "ls180.v:4513.1-4546.4" wire $0\main_sdphy_init_pads_out_payload_clk[0:0] - attribute \src "ls180.v:4473.1-4506.4" + attribute \src "ls180.v:4513.1-4546.4" wire $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:4473.1-4506.4" + attribute \src "ls180.v:4513.1-4546.4" wire $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:4473.1-4506.4" + attribute \src "ls180.v:4513.1-4546.4" wire width 4 $0\main_sdphy_init_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:4473.1-4506.4" + attribute \src "ls180.v:4513.1-4546.4" wire $0\main_sdphy_init_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:7457.1-7527.4" + attribute \src "ls180.v:7512.1-7582.4" wire $0\main_sdphy_sdpads_cmd_i[0:0] - attribute \src "ls180.v:7457.1-7527.4" + attribute \src "ls180.v:7512.1-7582.4" wire width 4 $0\main_sdphy_sdpads_data_i[3:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdram_address_re[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 13 $0\main_sdram_address_storage[12:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdram_baddress_re[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 2 $0\main_sdram_baddress_storage[1:0] - attribute \src "ls180.v:3259.1-3266.4" + attribute \src "ls180.v:3288.1-3295.4" wire $0\main_sdram_bankmachine0_auto_precharge[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 3 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 4 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 3 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:490.5-490.64" + attribute \src "ls180.v:477.5-477.64" wire $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] - attribute \src "ls180.v:473.5-473.67" + attribute \src "ls180.v:460.5-460.67" wire $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] - attribute \src "ls180.v:474.5-474.66" + attribute \src "ls180.v:461.5-461.66" wire $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] - attribute \src "ls180.v:3281.1-3288.4" + attribute \src "ls180.v:3310.1-3317.4" wire width 3 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 22 $0\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:3248.1-3255.4" + attribute \src "ls180.v:3277.1-3284.4" wire width 13 $0\main_sdram_bankmachine0_cmd_payload_a[12:0] - attribute \src "ls180.v:3297.1-3390.4" + attribute \src "ls180.v:3326.1-3419.4" wire $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] - attribute \src "ls180.v:3297.1-3390.4" + attribute \src "ls180.v:3326.1-3419.4" wire $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:3297.1-3390.4" + attribute \src "ls180.v:3326.1-3419.4" wire $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0] - attribute \src "ls180.v:3297.1-3390.4" + attribute \src "ls180.v:3326.1-3419.4" wire $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] - attribute \src "ls180.v:3297.1-3390.4" + attribute \src "ls180.v:3326.1-3419.4" wire $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] - attribute \src "ls180.v:3297.1-3390.4" + attribute \src "ls180.v:3326.1-3419.4" wire $0\main_sdram_bankmachine0_cmd_payload_we[0:0] - attribute \src "ls180.v:3946.1-3954.4" + attribute \src "ls180.v:3975.1-3983.4" wire $0\main_sdram_bankmachine0_cmd_ready[0:0] - attribute \src "ls180.v:3297.1-3390.4" + attribute \src "ls180.v:3326.1-3419.4" wire $0\main_sdram_bankmachine0_cmd_valid[0:0] - attribute \src "ls180.v:3297.1-3390.4" + attribute \src "ls180.v:3326.1-3419.4" wire $0\main_sdram_bankmachine0_refresh_gnt[0:0] - attribute \src "ls180.v:3297.1-3390.4" + attribute \src "ls180.v:3326.1-3419.4" wire $0\main_sdram_bankmachine0_req_rdata_valid[0:0] - attribute \src "ls180.v:3297.1-3390.4" + attribute \src "ls180.v:3326.1-3419.4" wire $0\main_sdram_bankmachine0_req_wdata_ready[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 13 $0\main_sdram_bankmachine0_row[12:0] - attribute \src "ls180.v:3297.1-3390.4" + attribute \src "ls180.v:3326.1-3419.4" wire $0\main_sdram_bankmachine0_row_close[0:0] - attribute \src "ls180.v:3297.1-3390.4" + attribute \src "ls180.v:3326.1-3419.4" wire $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:3297.1-3390.4" + attribute \src "ls180.v:3326.1-3419.4" wire $0\main_sdram_bankmachine0_row_open[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdram_bankmachine0_row_opened[0:0] - attribute \src "ls180.v:532.32-532.76" + attribute \src "ls180.v:519.32-519.76" wire $0\main_sdram_bankmachine0_trascon_ready[0:0] - attribute \src "ls180.v:530.32-530.75" + attribute \src "ls180.v:517.32-517.75" wire $0\main_sdram_bankmachine0_trccon_ready[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 3 $0\main_sdram_bankmachine0_twtpcon_count[2:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdram_bankmachine0_twtpcon_ready[0:0] - attribute \src "ls180.v:3416.1-3423.4" + attribute \src "ls180.v:3445.1-3452.4" wire $0\main_sdram_bankmachine1_auto_precharge[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 3 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 4 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 3 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:572.5-572.64" + attribute \src "ls180.v:559.5-559.64" wire $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] - attribute \src "ls180.v:555.5-555.67" + attribute \src "ls180.v:542.5-542.67" wire $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] - attribute \src "ls180.v:556.5-556.66" + attribute \src "ls180.v:543.5-543.66" wire $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] - attribute \src "ls180.v:3438.1-3445.4" + attribute \src "ls180.v:3467.1-3474.4" wire width 3 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 22 $0\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:3405.1-3412.4" + attribute \src "ls180.v:3434.1-3441.4" wire width 13 $0\main_sdram_bankmachine1_cmd_payload_a[12:0] - attribute \src "ls180.v:3454.1-3547.4" + attribute \src "ls180.v:3483.1-3576.4" wire $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] - attribute \src "ls180.v:3454.1-3547.4" + attribute \src "ls180.v:3483.1-3576.4" wire $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:3454.1-3547.4" + attribute \src "ls180.v:3483.1-3576.4" wire $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] - attribute \src "ls180.v:3454.1-3547.4" + attribute \src "ls180.v:3483.1-3576.4" wire $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] - attribute \src "ls180.v:3454.1-3547.4" + attribute \src "ls180.v:3483.1-3576.4" wire $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] - attribute \src "ls180.v:3454.1-3547.4" + attribute \src "ls180.v:3483.1-3576.4" wire $0\main_sdram_bankmachine1_cmd_payload_we[0:0] - attribute \src "ls180.v:3955.1-3963.4" + attribute \src "ls180.v:3984.1-3992.4" wire $0\main_sdram_bankmachine1_cmd_ready[0:0] - attribute \src "ls180.v:3454.1-3547.4" + attribute \src "ls180.v:3483.1-3576.4" wire $0\main_sdram_bankmachine1_cmd_valid[0:0] - attribute \src "ls180.v:3454.1-3547.4" + attribute \src "ls180.v:3483.1-3576.4" wire $0\main_sdram_bankmachine1_refresh_gnt[0:0] - attribute \src "ls180.v:3454.1-3547.4" + attribute \src "ls180.v:3483.1-3576.4" wire $0\main_sdram_bankmachine1_req_rdata_valid[0:0] - attribute \src "ls180.v:3454.1-3547.4" + attribute \src "ls180.v:3483.1-3576.4" wire $0\main_sdram_bankmachine1_req_wdata_ready[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 13 $0\main_sdram_bankmachine1_row[12:0] - attribute \src "ls180.v:3454.1-3547.4" + attribute \src "ls180.v:3483.1-3576.4" wire $0\main_sdram_bankmachine1_row_close[0:0] - attribute \src "ls180.v:3454.1-3547.4" + attribute \src "ls180.v:3483.1-3576.4" wire $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:3454.1-3547.4" + attribute \src "ls180.v:3483.1-3576.4" wire $0\main_sdram_bankmachine1_row_open[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdram_bankmachine1_row_opened[0:0] - attribute \src "ls180.v:614.32-614.76" + attribute \src "ls180.v:601.32-601.76" wire $0\main_sdram_bankmachine1_trascon_ready[0:0] - attribute \src "ls180.v:612.32-612.75" + attribute \src "ls180.v:599.32-599.75" wire $0\main_sdram_bankmachine1_trccon_ready[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 3 $0\main_sdram_bankmachine1_twtpcon_count[2:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdram_bankmachine1_twtpcon_ready[0:0] - attribute \src "ls180.v:3573.1-3580.4" + attribute \src "ls180.v:3602.1-3609.4" wire $0\main_sdram_bankmachine2_auto_precharge[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 3 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 4 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 3 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:654.5-654.64" + attribute \src "ls180.v:641.5-641.64" wire $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] - attribute \src "ls180.v:637.5-637.67" + attribute \src "ls180.v:624.5-624.67" wire $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] - attribute \src "ls180.v:638.5-638.66" + attribute \src "ls180.v:625.5-625.66" wire $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] - attribute \src "ls180.v:3595.1-3602.4" + attribute \src "ls180.v:3624.1-3631.4" wire width 3 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 22 $0\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:3562.1-3569.4" + attribute \src "ls180.v:3591.1-3598.4" wire width 13 $0\main_sdram_bankmachine2_cmd_payload_a[12:0] - attribute \src "ls180.v:3611.1-3704.4" + attribute \src "ls180.v:3640.1-3733.4" wire $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] - attribute \src "ls180.v:3611.1-3704.4" + attribute \src "ls180.v:3640.1-3733.4" wire $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:3611.1-3704.4" + attribute \src "ls180.v:3640.1-3733.4" wire $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] - attribute \src "ls180.v:3611.1-3704.4" + attribute \src "ls180.v:3640.1-3733.4" wire $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] - attribute \src "ls180.v:3611.1-3704.4" + attribute \src "ls180.v:3640.1-3733.4" wire $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] - attribute \src "ls180.v:3611.1-3704.4" + attribute \src "ls180.v:3640.1-3733.4" wire $0\main_sdram_bankmachine2_cmd_payload_we[0:0] - attribute \src "ls180.v:3964.1-3972.4" + attribute \src "ls180.v:3993.1-4001.4" wire $0\main_sdram_bankmachine2_cmd_ready[0:0] - attribute \src "ls180.v:3611.1-3704.4" + attribute \src "ls180.v:3640.1-3733.4" wire $0\main_sdram_bankmachine2_cmd_valid[0:0] - attribute \src "ls180.v:3611.1-3704.4" + attribute \src "ls180.v:3640.1-3733.4" wire $0\main_sdram_bankmachine2_refresh_gnt[0:0] - attribute \src "ls180.v:3611.1-3704.4" + attribute \src "ls180.v:3640.1-3733.4" wire $0\main_sdram_bankmachine2_req_rdata_valid[0:0] - attribute \src "ls180.v:3611.1-3704.4" + attribute \src "ls180.v:3640.1-3733.4" wire $0\main_sdram_bankmachine2_req_wdata_ready[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 13 $0\main_sdram_bankmachine2_row[12:0] - attribute \src "ls180.v:3611.1-3704.4" + attribute \src "ls180.v:3640.1-3733.4" wire $0\main_sdram_bankmachine2_row_close[0:0] - attribute \src "ls180.v:3611.1-3704.4" + attribute \src "ls180.v:3640.1-3733.4" wire $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:3611.1-3704.4" + attribute \src "ls180.v:3640.1-3733.4" wire $0\main_sdram_bankmachine2_row_open[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdram_bankmachine2_row_opened[0:0] - attribute \src "ls180.v:696.32-696.76" + attribute \src "ls180.v:683.32-683.76" wire $0\main_sdram_bankmachine2_trascon_ready[0:0] - attribute \src "ls180.v:694.32-694.75" + attribute \src "ls180.v:681.32-681.75" wire $0\main_sdram_bankmachine2_trccon_ready[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 3 $0\main_sdram_bankmachine2_twtpcon_count[2:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdram_bankmachine2_twtpcon_ready[0:0] - attribute \src "ls180.v:3730.1-3737.4" + attribute \src "ls180.v:3759.1-3766.4" wire $0\main_sdram_bankmachine3_auto_precharge[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 3 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 4 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 3 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:736.5-736.64" + attribute \src "ls180.v:723.5-723.64" wire $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] - attribute \src "ls180.v:719.5-719.67" + attribute \src "ls180.v:706.5-706.67" wire $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] - attribute \src "ls180.v:720.5-720.66" + attribute \src "ls180.v:707.5-707.66" wire $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] - attribute \src "ls180.v:3752.1-3759.4" + attribute \src "ls180.v:3781.1-3788.4" wire width 3 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 22 $0\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:3719.1-3726.4" + attribute \src "ls180.v:3748.1-3755.4" wire width 13 $0\main_sdram_bankmachine3_cmd_payload_a[12:0] - attribute \src "ls180.v:3768.1-3861.4" + attribute \src "ls180.v:3797.1-3890.4" wire $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] - attribute \src "ls180.v:3768.1-3861.4" + attribute \src "ls180.v:3797.1-3890.4" wire $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:3768.1-3861.4" + attribute \src "ls180.v:3797.1-3890.4" wire $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] - attribute \src "ls180.v:3768.1-3861.4" + attribute \src "ls180.v:3797.1-3890.4" wire $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] - attribute \src "ls180.v:3768.1-3861.4" + attribute \src "ls180.v:3797.1-3890.4" wire $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] - attribute \src "ls180.v:3768.1-3861.4" + attribute \src "ls180.v:3797.1-3890.4" wire $0\main_sdram_bankmachine3_cmd_payload_we[0:0] - attribute \src "ls180.v:3973.1-3981.4" + attribute \src "ls180.v:4002.1-4010.4" wire $0\main_sdram_bankmachine3_cmd_ready[0:0] - attribute \src "ls180.v:3768.1-3861.4" + attribute \src "ls180.v:3797.1-3890.4" wire $0\main_sdram_bankmachine3_cmd_valid[0:0] - attribute \src "ls180.v:3768.1-3861.4" + attribute \src "ls180.v:3797.1-3890.4" wire $0\main_sdram_bankmachine3_refresh_gnt[0:0] - attribute \src "ls180.v:3768.1-3861.4" + attribute \src "ls180.v:3797.1-3890.4" wire $0\main_sdram_bankmachine3_req_rdata_valid[0:0] - attribute \src "ls180.v:3768.1-3861.4" + attribute \src "ls180.v:3797.1-3890.4" wire $0\main_sdram_bankmachine3_req_wdata_ready[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 13 $0\main_sdram_bankmachine3_row[12:0] - attribute \src "ls180.v:3768.1-3861.4" + attribute \src "ls180.v:3797.1-3890.4" wire $0\main_sdram_bankmachine3_row_close[0:0] - attribute \src "ls180.v:3768.1-3861.4" + attribute \src "ls180.v:3797.1-3890.4" wire $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:3768.1-3861.4" + attribute \src "ls180.v:3797.1-3890.4" wire $0\main_sdram_bankmachine3_row_open[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdram_bankmachine3_row_opened[0:0] - attribute \src "ls180.v:778.32-778.76" + attribute \src "ls180.v:765.32-765.76" wire $0\main_sdram_bankmachine3_trascon_ready[0:0] - attribute \src "ls180.v:776.32-776.75" + attribute \src "ls180.v:763.32-763.75" wire $0\main_sdram_bankmachine3_trccon_ready[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 3 $0\main_sdram_bankmachine3_twtpcon_count[2:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdram_bankmachine3_twtpcon_ready[0:0] - attribute \src "ls180.v:3895.1-3900.4" + attribute \src "ls180.v:3924.1-3929.4" wire $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] - attribute \src "ls180.v:3901.1-3906.4" + attribute \src "ls180.v:3930.1-3935.4" wire $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] - attribute \src "ls180.v:3907.1-3912.4" + attribute \src "ls180.v:3936.1-3941.4" wire $0\main_sdram_choose_cmd_cmd_payload_we[0:0] - attribute \src "ls180.v:786.5-786.43" + attribute \src "ls180.v:773.5-773.43" wire $0\main_sdram_choose_cmd_cmd_ready[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 2 $0\main_sdram_choose_cmd_grant[1:0] - attribute \src "ls180.v:3881.1-3887.4" + attribute \src "ls180.v:3910.1-3916.4" wire width 4 $0\main_sdram_choose_cmd_valids[3:0] - attribute \src "ls180.v:784.5-784.48" + attribute \src "ls180.v:771.5-771.48" wire $0\main_sdram_choose_cmd_want_activates[0:0] - attribute \src "ls180.v:783.5-783.43" + attribute \src "ls180.v:770.5-770.43" wire $0\main_sdram_choose_cmd_want_cmds[0:0] - attribute \src "ls180.v:781.5-781.44" + attribute \src "ls180.v:768.5-768.44" wire $0\main_sdram_choose_cmd_want_reads[0:0] - attribute \src "ls180.v:782.5-782.45" + attribute \src "ls180.v:769.5-769.45" wire $0\main_sdram_choose_cmd_want_writes[0:0] - attribute \src "ls180.v:3928.1-3933.4" + attribute \src "ls180.v:3957.1-3962.4" wire $0\main_sdram_choose_req_cmd_payload_cas[0:0] - attribute \src "ls180.v:3934.1-3939.4" + attribute \src "ls180.v:3963.1-3968.4" wire $0\main_sdram_choose_req_cmd_payload_ras[0:0] - attribute \src "ls180.v:3940.1-3945.4" + attribute \src "ls180.v:3969.1-3974.4" wire $0\main_sdram_choose_req_cmd_payload_we[0:0] - attribute \src "ls180.v:3986.1-4058.4" + attribute \src "ls180.v:4015.1-4087.4" wire $0\main_sdram_choose_req_cmd_ready[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 2 $0\main_sdram_choose_req_grant[1:0] - attribute \src "ls180.v:3914.1-3920.4" + attribute \src "ls180.v:3943.1-3949.4" wire width 4 $0\main_sdram_choose_req_valids[3:0] - attribute \src "ls180.v:3986.1-4058.4" + attribute \src "ls180.v:4015.1-4087.4" wire $0\main_sdram_choose_req_want_activates[0:0] - attribute \src "ls180.v:3986.1-4058.4" + attribute \src "ls180.v:4015.1-4087.4" wire $0\main_sdram_choose_req_want_reads[0:0] - attribute \src "ls180.v:3986.1-4058.4" + attribute \src "ls180.v:4015.1-4087.4" wire $0\main_sdram_choose_req_want_writes[0:0] - attribute \src "ls180.v:3203.1-3233.4" + attribute \src "ls180.v:3232.1-3262.4" wire $0\main_sdram_cmd_last[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 13 $0\main_sdram_cmd_payload_a[12:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 2 $0\main_sdram_cmd_payload_ba[1:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdram_cmd_payload_cas[0:0] - attribute \src "ls180.v:434.5-434.42" + attribute \src "ls180.v:421.5-421.42" wire $0\main_sdram_cmd_payload_is_read[0:0] - attribute \src "ls180.v:435.5-435.43" + attribute \src "ls180.v:422.5-422.43" wire $0\main_sdram_cmd_payload_is_write[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdram_cmd_payload_ras[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdram_cmd_payload_we[0:0] - attribute \src "ls180.v:3986.1-4058.4" + attribute \src "ls180.v:4015.1-4087.4" wire $0\main_sdram_cmd_ready[0:0] - attribute \src "ls180.v:3203.1-3233.4" + attribute \src "ls180.v:3232.1-3262.4" wire $0\main_sdram_cmd_valid[0:0] - attribute \src "ls180.v:370.5-370.38" + attribute \src "ls180.v:357.5-357.38" wire $0\main_sdram_command_issue_w[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdram_command_re[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 6 $0\main_sdram_command_storage[5:0] - attribute \src "ls180.v:419.5-419.35" + attribute \src "ls180.v:406.5-406.35" wire $0\main_sdram_dfi_p0_act_n[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 13 $0\main_sdram_dfi_p0_address[12:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 2 $0\main_sdram_dfi_p0_bank[1:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdram_dfi_p0_cas_n[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdram_dfi_p0_cs_n[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdram_dfi_p0_ras_n[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdram_dfi_p0_rddata_en[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdram_dfi_p0_we_n[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdram_dfi_p0_wrdata_en[0:0] - attribute \src "ls180.v:3986.1-4058.4" + attribute \src "ls180.v:4015.1-4087.4" wire $0\main_sdram_en0[0:0] - attribute \src "ls180.v:3986.1-4058.4" + attribute \src "ls180.v:4015.1-4087.4" wire $0\main_sdram_en1[0:0] - attribute \src "ls180.v:4082.1-4095.4" + attribute \src "ls180.v:4111.1-4124.4" wire width 16 $0\main_sdram_interface_wdata[15:0] - attribute \src "ls180.v:4082.1-4095.4" + attribute \src "ls180.v:4111.1-4124.4" wire width 2 $0\main_sdram_interface_wdata_we[1:0] - attribute \src "ls180.v:320.5-320.36" + attribute \src "ls180.v:307.5-307.36" wire $0\main_sdram_inti_p0_act_n[0:0] - attribute \src "ls180.v:3144.1-3160.4" + attribute \src "ls180.v:3173.1-3189.4" wire $0\main_sdram_inti_p0_cas_n[0:0] - attribute \src "ls180.v:3144.1-3160.4" + attribute \src "ls180.v:3173.1-3189.4" wire $0\main_sdram_inti_p0_cs_n[0:0] - attribute \src "ls180.v:3144.1-3160.4" + attribute \src "ls180.v:3173.1-3189.4" wire $0\main_sdram_inti_p0_ras_n[0:0] - attribute \src "ls180.v:3086.1-3140.4" + attribute \src "ls180.v:3115.1-3169.4" wire width 16 $0\main_sdram_inti_p0_rddata[15:0] - attribute \src "ls180.v:3086.1-3140.4" + attribute \src "ls180.v:3115.1-3169.4" wire $0\main_sdram_inti_p0_rddata_valid[0:0] - attribute \src "ls180.v:3144.1-3160.4" + attribute \src "ls180.v:3173.1-3189.4" wire $0\main_sdram_inti_p0_we_n[0:0] - attribute \src "ls180.v:3086.1-3140.4" + attribute \src "ls180.v:3115.1-3169.4" wire $0\main_sdram_master_p0_act_n[0:0] - attribute \src "ls180.v:3086.1-3140.4" + attribute \src "ls180.v:3115.1-3169.4" wire width 13 $0\main_sdram_master_p0_address[12:0] - attribute \src "ls180.v:3086.1-3140.4" + attribute \src "ls180.v:3115.1-3169.4" wire width 2 $0\main_sdram_master_p0_bank[1:0] - attribute \src "ls180.v:3086.1-3140.4" + attribute \src "ls180.v:3115.1-3169.4" wire $0\main_sdram_master_p0_cas_n[0:0] - attribute \src "ls180.v:3086.1-3140.4" + attribute \src "ls180.v:3115.1-3169.4" wire $0\main_sdram_master_p0_cke[0:0] - attribute \src "ls180.v:3086.1-3140.4" + attribute \src "ls180.v:3115.1-3169.4" wire $0\main_sdram_master_p0_cs_n[0:0] - attribute \src "ls180.v:3086.1-3140.4" + attribute \src "ls180.v:3115.1-3169.4" wire $0\main_sdram_master_p0_odt[0:0] - attribute \src "ls180.v:3086.1-3140.4" + attribute \src "ls180.v:3115.1-3169.4" wire $0\main_sdram_master_p0_ras_n[0:0] - attribute \src "ls180.v:3086.1-3140.4" + attribute \src "ls180.v:3115.1-3169.4" wire $0\main_sdram_master_p0_rddata_en[0:0] - attribute \src "ls180.v:3086.1-3140.4" + attribute \src "ls180.v:3115.1-3169.4" wire $0\main_sdram_master_p0_reset_n[0:0] - attribute \src "ls180.v:3086.1-3140.4" + attribute \src "ls180.v:3115.1-3169.4" wire $0\main_sdram_master_p0_we_n[0:0] - attribute \src "ls180.v:3086.1-3140.4" + attribute \src "ls180.v:3115.1-3169.4" wire width 16 $0\main_sdram_master_p0_wrdata[15:0] - attribute \src "ls180.v:3086.1-3140.4" + attribute \src "ls180.v:3115.1-3169.4" wire $0\main_sdram_master_p0_wrdata_en[0:0] - attribute \src "ls180.v:3086.1-3140.4" + attribute \src "ls180.v:3115.1-3169.4" wire width 2 $0\main_sdram_master_p0_wrdata_mask[1:0] - attribute \src "ls180.v:817.12-817.36" + attribute \src "ls180.v:804.12-804.36" wire width 13 $0\main_sdram_nop_a[12:0] - attribute \src "ls180.v:818.11-818.35" + attribute \src "ls180.v:805.11-805.35" wire width 2 $0\main_sdram_nop_ba[1:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdram_postponer_count[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdram_postponer_req_o[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdram_re[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdram_sequencer_count[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 4 $0\main_sdram_sequencer_counter[3:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdram_sequencer_done1[0:0] - attribute \src "ls180.v:3203.1-3233.4" + attribute \src "ls180.v:3232.1-3262.4" wire $0\main_sdram_sequencer_start0[0:0] - attribute \src "ls180.v:3086.1-3140.4" + attribute \src "ls180.v:3115.1-3169.4" wire width 16 $0\main_sdram_slave_p0_rddata[15:0] - attribute \src "ls180.v:3086.1-3140.4" + attribute \src "ls180.v:3115.1-3169.4" wire $0\main_sdram_slave_p0_rddata_valid[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 16 $0\main_sdram_status[15:0] - attribute \src "ls180.v:820.5-820.31" + attribute \src "ls180.v:807.5-807.31" wire $0\main_sdram_steerer0[0:0] - attribute \src "ls180.v:821.5-821.31" + attribute \src "ls180.v:808.5-808.31" wire $0\main_sdram_steerer1[0:0] - attribute \src "ls180.v:3986.1-4058.4" + attribute \src "ls180.v:4015.1-4087.4" wire width 2 $0\main_sdram_steerer_sel[1:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 4 $0\main_sdram_storage[3:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdram_tccdcon_count[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdram_tccdcon_ready[0:0] - attribute \src "ls180.v:825.32-825.63" + attribute \src "ls180.v:812.32-812.63" wire $0\main_sdram_tfawcon_ready[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 5 $0\main_sdram_time0[4:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 4 $0\main_sdram_time1[3:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 10 $0\main_sdram_timer_count1[9:0] - attribute \src "ls180.v:823.32-823.63" + attribute \src "ls180.v:810.32-810.63" wire $0\main_sdram_trrdcon_ready[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 3 $0\main_sdram_twtrcon_count[2:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdram_twtrcon_ready[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_sdram_wrdata_re[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 16 $0\main_sdram_wrdata_storage[15:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:2964.1-3010.4" + wire $0\main_socbushandler_converted_interface_ack[0:0] + attribute \src "ls180.v:859.5-859.54" + wire $0\main_socbushandler_converted_interface_err[0:0] + attribute \src "ls180.v:7584.1-10223.4" + wire $0\main_socbushandler_counter[0:0] + attribute \src "ls180.v:2964.1-3010.4" + wire $0\main_socbushandler_counter_converter2_next_value[0:0] + attribute \src "ls180.v:2964.1-3010.4" + wire $0\main_socbushandler_counter_converter2_next_value_ce[0:0] + attribute \src "ls180.v:7584.1-10223.4" + wire width 64 $0\main_socbushandler_dat_r[63:0] + attribute \src "ls180.v:2964.1-3010.4" + wire $0\main_socbushandler_skip[0:0] + attribute \src "ls180.v:7584.1-10223.4" wire width 16 $0\main_spimaster11_storage[15:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_spimaster12_re[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 8 $0\main_spimaster16_storage[7:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_spimaster17_re[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_spimaster1_re[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 16 $0\main_spimaster1_storage[15:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_spimaster21_storage[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_spimaster22_re[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_spimaster23_storage[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_spimaster24_re[0:0] - attribute \src "ls180.v:4304.1-4352.4" + attribute \src "ls180.v:4344.1-4392.4" wire $0\main_spimaster25_clk_enable[0:0] - attribute \src "ls180.v:4304.1-4352.4" + attribute \src "ls180.v:4344.1-4392.4" wire $0\main_spimaster26_cs_enable[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 3 $0\main_spimaster27_count[2:0] - attribute \src "ls180.v:4304.1-4352.4" + attribute \src "ls180.v:4344.1-4392.4" wire width 3 $0\main_spimaster27_count_spimaster0_next_value[2:0] - attribute \src "ls180.v:4304.1-4352.4" + attribute \src "ls180.v:4344.1-4392.4" wire $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] - attribute \src "ls180.v:4304.1-4352.4" + attribute \src "ls180.v:4344.1-4392.4" wire $0\main_spimaster28_mosi_latch[0:0] - attribute \src "ls180.v:4304.1-4352.4" + attribute \src "ls180.v:4344.1-4392.4" wire $0\main_spimaster29_miso_latch[0:0] - attribute \src "ls180.v:4304.1-4352.4" + attribute \src "ls180.v:4344.1-4392.4" wire $0\main_spimaster2_done[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 16 $0\main_spimaster30_clk_divider[15:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 8 $0\main_spimaster33_mosi_data[7:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 3 $0\main_spimaster34_mosi_sel[2:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 8 $0\main_spimaster35_miso_data[7:0] - attribute \src "ls180.v:4304.1-4352.4" + attribute \src "ls180.v:4344.1-4392.4" wire $0\main_spimaster3_irq[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 8 $0\main_spimaster5_miso[7:0] - attribute \src "ls180.v:1041.12-1041.47" + attribute \src "ls180.v:1046.12-1046.47" wire width 16 $0\main_spimaster8_clk_divider[15:0] - attribute \src "ls180.v:6383.1-6388.4" + attribute \src "ls180.v:6435.1-6440.4" wire $0\main_spimaster9_start[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 16 $0\main_spisdcard_clk_divider1[15:0] - attribute \src "ls180.v:4363.1-4411.4" + attribute \src "ls180.v:4403.1-4451.4" wire $0\main_spisdcard_clk_enable[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_spisdcard_control_re[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 16 $0\main_spisdcard_control_storage[15:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 3 $0\main_spisdcard_count[2:0] - attribute \src "ls180.v:4363.1-4411.4" + attribute \src "ls180.v:4403.1-4451.4" wire width 3 $0\main_spisdcard_count_spimaster1_next_value[2:0] - attribute \src "ls180.v:4363.1-4411.4" + attribute \src "ls180.v:4403.1-4451.4" wire $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] - attribute \src "ls180.v:4363.1-4411.4" + attribute \src "ls180.v:4403.1-4451.4" wire $0\main_spisdcard_cs_enable[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_spisdcard_cs_re[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_spisdcard_cs_storage[0:0] - attribute \src "ls180.v:4363.1-4411.4" + attribute \src "ls180.v:4403.1-4451.4" wire $0\main_spisdcard_done0[0:0] - attribute \src "ls180.v:4363.1-4411.4" + attribute \src "ls180.v:4403.1-4451.4" wire $0\main_spisdcard_irq[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_spisdcard_loopback_re[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_spisdcard_loopback_storage[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 8 $0\main_spisdcard_miso[7:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 8 $0\main_spisdcard_miso_data[7:0] - attribute \src "ls180.v:4363.1-4411.4" + attribute \src "ls180.v:4403.1-4451.4" wire $0\main_spisdcard_miso_latch[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 8 $0\main_spisdcard_mosi_data[7:0] - attribute \src "ls180.v:4363.1-4411.4" + attribute \src "ls180.v:4403.1-4451.4" wire $0\main_spisdcard_mosi_latch[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_spisdcard_mosi_re[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 3 $0\main_spisdcard_mosi_sel[2:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 8 $0\main_spisdcard_mosi_storage[7:0] - attribute \src "ls180.v:6429.1-6434.4" + attribute \src "ls180.v:6481.1-6486.4" wire $0\main_spisdcard_start1[0:0] - attribute \src "ls180.v:3021.1-3027.4" - wire width 4 $0\main_sram0_we[3:0] - attribute \src "ls180.v:3031.1-3037.4" - wire width 4 $0\main_sram1_we[3:0] - attribute \src "ls180.v:3041.1-3047.4" - wire width 4 $0\main_sram2_we[3:0] - attribute \src "ls180.v:4222.1-4226.4" + attribute \src "ls180.v:3038.1-3048.4" + wire width 8 $0\main_sram0_we[7:0] + attribute \src "ls180.v:3052.1-3062.4" + wire width 8 $0\main_sram1_we[7:0] + attribute \src "ls180.v:3066.1-3076.4" + wire width 8 $0\main_sram2_we[7:0] + attribute \src "ls180.v:4251.1-4255.4" wire width 2 $0\main_uart_eventmanager_pending_w[1:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_uart_eventmanager_re[0:0] - attribute \src "ls180.v:4211.1-4215.4" + attribute \src "ls180.v:4240.1-4244.4" wire width 2 $0\main_uart_eventmanager_status_w[1:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 2 $0\main_uart_eventmanager_storage[1:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 32 $0\main_uart_phy_phase_accumulator_rx[31:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 32 $0\main_uart_phy_phase_accumulator_tx[31:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_uart_phy_re[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 4 $0\main_uart_phy_rx_bitcount[3:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_uart_phy_rx_busy[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_uart_phy_rx_r[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 8 $0\main_uart_phy_rx_reg[7:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_uart_phy_sink_ready[0:0] - attribute \src "ls180.v:896.5-896.38" + attribute \src "ls180.v:895.5-895.38" wire $0\main_uart_phy_source_first[0:0] - attribute \src "ls180.v:897.5-897.37" + attribute \src "ls180.v:896.5-896.37" wire $0\main_uart_phy_source_last[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 8 $0\main_uart_phy_source_payload_data[7:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_uart_phy_source_valid[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 32 $0\main_uart_phy_storage[31:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 4 $0\main_uart_phy_tx_bitcount[3:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_uart_phy_tx_busy[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 8 $0\main_uart_phy_tx_reg[7:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_uart_phy_uart_clk_rxen[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_uart_phy_uart_clk_txen[0:0] - attribute \src "ls180.v:1023.5-1023.27" + attribute \src "ls180.v:1022.5-1022.27" wire $0\main_uart_reset[0:0] - attribute \src "ls180.v:4216.1-4221.4" + attribute \src "ls180.v:4245.1-4250.4" wire $0\main_uart_rx_clear[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 4 $0\main_uart_rx_fifo_consume[3:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 5 $0\main_uart_rx_fifo_level0[4:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 4 $0\main_uart_rx_fifo_produce[3:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_uart_rx_fifo_readable[0:0] - attribute \src "ls180.v:1005.5-1005.37" + attribute \src "ls180.v:1004.5-1004.37" wire $0\main_uart_rx_fifo_replace[0:0] - attribute \src "ls180.v:4274.1-4281.4" + attribute \src "ls180.v:4303.1-4310.4" wire width 4 $0\main_uart_rx_fifo_wrport_adr[3:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_uart_rx_old_trigger[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_uart_rx_pending[0:0] - attribute \src "ls180.v:4205.1-4210.4" + attribute \src "ls180.v:4234.1-4239.4" wire $0\main_uart_tx_clear[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 4 $0\main_uart_tx_fifo_consume[3:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 5 $0\main_uart_tx_fifo_level0[4:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 4 $0\main_uart_tx_fifo_produce[3:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_uart_tx_fifo_readable[0:0] - attribute \src "ls180.v:968.5-968.37" + attribute \src "ls180.v:967.5-967.37" wire $0\main_uart_tx_fifo_replace[0:0] - attribute \src "ls180.v:951.5-951.40" + attribute \src "ls180.v:950.5-950.40" wire $0\main_uart_tx_fifo_sink_first[0:0] - attribute \src "ls180.v:952.5-952.39" + attribute \src "ls180.v:951.5-951.39" wire $0\main_uart_tx_fifo_sink_last[0:0] - attribute \src "ls180.v:4244.1-4251.4" + attribute \src "ls180.v:4273.1-4280.4" wire width 4 $0\main_uart_tx_fifo_wrport_adr[3:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_uart_tx_old_trigger[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_uart_tx_pending[0:0] - attribute \src "ls180.v:4114.1-4160.4" + attribute \src "ls180.v:4143.1-4189.4" wire $0\main_wb_sdram_ack[0:0] - attribute \src "ls180.v:864.5-864.29" - wire $0\main_wb_sdram_err[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:2964.1-3010.4" + wire width 30 $0\main_wb_sdram_adr[29:0] + attribute \src "ls180.v:2964.1-3010.4" + wire $0\main_wb_sdram_cyc[0:0] + attribute \src "ls180.v:2952.1-2962.4" + wire width 32 $0\main_wb_sdram_dat_w[31:0] + attribute \src "ls180.v:2964.1-3010.4" + wire width 4 $0\main_wb_sdram_sel[3:0] + attribute \src "ls180.v:2964.1-3010.4" + wire $0\main_wb_sdram_stb[0:0] + attribute \src "ls180.v:2964.1-3010.4" + wire $0\main_wb_sdram_we[0:0] + attribute \src "ls180.v:7584.1-10223.4" wire $0\main_wdata_consumed[0:0] - attribute \src "ls180.v:10160.1-10170.4" - wire width 7 $0\memadr[6:0] - attribute \src "ls180.v:10180.1-10190.4" - wire width 7 $0\memadr_1[6:0] - attribute \src "ls180.v:10200.1-10210.4" - wire width 7 $0\memadr_2[6:0] - attribute \src "ls180.v:10220.1-10230.4" - wire width 7 $0\memadr_3[6:0] - attribute \src "ls180.v:10240.1-10244.4" + attribute \src "ls180.v:10227.1-10245.4" + wire width 6 $0\memadr[5:0] + attribute \src "ls180.v:10255.1-10273.4" + wire width 6 $0\memadr_1[5:0] + attribute \src "ls180.v:10283.1-10301.4" + wire width 6 $0\memadr_2[5:0] + attribute \src "ls180.v:10311.1-10329.4" + wire width 6 $0\memadr_3[5:0] + attribute \src "ls180.v:10339.1-10343.4" wire width 25 $0\memdat[24:0] - attribute \src "ls180.v:10254.1-10258.4" + attribute \src "ls180.v:10353.1-10357.4" wire width 25 $0\memdat_1[24:0] - attribute \src "ls180.v:10268.1-10272.4" + attribute \src "ls180.v:10367.1-10371.4" wire width 25 $0\memdat_2[24:0] - attribute \src "ls180.v:10282.1-10286.4" + attribute \src "ls180.v:10381.1-10385.4" wire width 25 $0\memdat_3[24:0] - attribute \src "ls180.v:10297.1-10301.4" + attribute \src "ls180.v:10396.1-10400.4" wire width 10 $0\memdat_4[9:0] - attribute \src "ls180.v:10303.1-10306.4" + attribute \src "ls180.v:10402.1-10405.4" wire width 10 $0\memdat_5[9:0] - attribute \src "ls180.v:10314.1-10318.4" + attribute \src "ls180.v:10413.1-10417.4" wire width 10 $0\memdat_6[9:0] - attribute \src "ls180.v:10320.1-10323.4" + attribute \src "ls180.v:10419.1-10422.4" wire width 10 $0\memdat_7[9:0] - attribute \src "ls180.v:10330.1-10334.4" + attribute \src "ls180.v:10429.1-10433.4" wire width 10 $0\memdat_8[9:0] - attribute \src "ls180.v:10344.1-10348.4" + attribute \src "ls180.v:10443.1-10447.4" wire width 10 $0\memdat_9[9:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire width 2 $0\pwm[1:0] - attribute \src "ls180.v:7457.1-7527.4" + attribute \src "ls180.v:7512.1-7582.4" wire $0\sdcard_clk[0:0] - attribute \src "ls180.v:7457.1-7527.4" + attribute \src "ls180.v:7512.1-7582.4" wire $0\sdcard_cmd_o[0:0] - attribute \src "ls180.v:7457.1-7527.4" + attribute \src "ls180.v:7512.1-7582.4" wire $0\sdcard_cmd_oe[0:0] - attribute \src "ls180.v:7457.1-7527.4" + attribute \src "ls180.v:7512.1-7582.4" wire width 4 $0\sdcard_data_o[3:0] - attribute \src "ls180.v:7457.1-7527.4" + attribute \src "ls180.v:7512.1-7582.4" wire $0\sdcard_data_oe[0:0] - attribute \src "ls180.v:7457.1-7527.4" + attribute \src "ls180.v:7512.1-7582.4" wire width 13 $0\sdram_a[12:0] - attribute \src "ls180.v:7457.1-7527.4" + attribute \src "ls180.v:7512.1-7582.4" wire width 2 $0\sdram_ba[1:0] - attribute \src "ls180.v:7457.1-7527.4" + attribute \src "ls180.v:7512.1-7582.4" wire $0\sdram_cas_n[0:0] - attribute \src "ls180.v:7457.1-7527.4" + attribute \src "ls180.v:7512.1-7582.4" wire $0\sdram_cke[0:0] - attribute \src "ls180.v:7457.1-7527.4" + attribute \src "ls180.v:7512.1-7582.4" wire $0\sdram_clock[0:0] - attribute \src "ls180.v:7457.1-7527.4" + attribute \src "ls180.v:7512.1-7582.4" wire $0\sdram_cs_n[0:0] - attribute \src "ls180.v:7457.1-7527.4" + attribute \src "ls180.v:7512.1-7582.4" wire width 2 $0\sdram_dm[1:0] - attribute \src "ls180.v:7457.1-7527.4" + attribute \src "ls180.v:7512.1-7582.4" wire width 16 $0\sdram_dq_o[15:0] - attribute \src "ls180.v:7457.1-7527.4" + attribute \src "ls180.v:7512.1-7582.4" wire $0\sdram_dq_oe[0:0] - attribute \src "ls180.v:7457.1-7527.4" + attribute \src "ls180.v:7512.1-7582.4" wire $0\sdram_ras_n[0:0] - attribute \src "ls180.v:7457.1-7527.4" + attribute \src "ls180.v:7512.1-7582.4" wire $0\sdram_we_n[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\spimaster_clk[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\spimaster_cs_n[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\spimaster_mosi[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\spisdcard_clk[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\spisdcard_cs_n[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\spisdcard_mosi[0:0] - attribute \src "ls180.v:7529.1-10156.4" + attribute \src "ls180.v:7584.1-10223.4" wire $0\uart_tx[0:0] - attribute \src "ls180.v:1790.11-1790.49" + attribute \src "ls180.v:1795.11-1795.49" wire width 3 $1\builder_bankmachine0_next_state[2:0] - attribute \src "ls180.v:1789.11-1789.44" + attribute \src "ls180.v:1794.11-1794.44" wire width 3 $1\builder_bankmachine0_state[2:0] - attribute \src "ls180.v:1792.11-1792.49" + attribute \src "ls180.v:1797.11-1797.49" wire width 3 $1\builder_bankmachine1_next_state[2:0] - attribute \src "ls180.v:1791.11-1791.44" + attribute \src "ls180.v:1796.11-1796.44" wire width 3 $1\builder_bankmachine1_state[2:0] - attribute \src "ls180.v:1794.11-1794.49" + attribute \src "ls180.v:1799.11-1799.49" wire width 3 $1\builder_bankmachine2_next_state[2:0] - attribute \src "ls180.v:1793.11-1793.44" + attribute \src "ls180.v:1798.11-1798.44" wire width 3 $1\builder_bankmachine2_state[2:0] - attribute \src "ls180.v:1796.11-1796.49" + attribute \src "ls180.v:1801.11-1801.49" wire width 3 $1\builder_bankmachine3_next_state[2:0] - attribute \src "ls180.v:1795.11-1795.44" + attribute \src "ls180.v:1800.11-1800.44" wire width 3 $1\builder_bankmachine3_state[2:0] - attribute \src "ls180.v:2641.5-2641.41" + attribute \src "ls180.v:2654.5-2654.41" wire $1\builder_comb_rhs_array_muxed0[0:0] - attribute \src "ls180.v:2654.5-2654.42" + attribute \src "ls180.v:2667.5-2667.42" wire $1\builder_comb_rhs_array_muxed10[0:0] - attribute \src "ls180.v:2655.5-2655.42" + attribute \src "ls180.v:2668.5-2668.42" wire $1\builder_comb_rhs_array_muxed11[0:0] - attribute \src "ls180.v:2659.12-2659.50" + attribute \src "ls180.v:2672.12-2672.50" wire width 22 $1\builder_comb_rhs_array_muxed12[21:0] - attribute \src "ls180.v:2660.5-2660.42" + attribute \src "ls180.v:2673.5-2673.42" wire $1\builder_comb_rhs_array_muxed13[0:0] - attribute \src "ls180.v:2661.5-2661.42" + attribute \src "ls180.v:2674.5-2674.42" wire $1\builder_comb_rhs_array_muxed14[0:0] - attribute \src "ls180.v:2662.12-2662.50" + attribute \src "ls180.v:2675.12-2675.50" wire width 22 $1\builder_comb_rhs_array_muxed15[21:0] - attribute \src "ls180.v:2663.5-2663.42" + attribute \src "ls180.v:2676.5-2676.42" wire $1\builder_comb_rhs_array_muxed16[0:0] - attribute \src "ls180.v:2664.5-2664.42" + attribute \src "ls180.v:2677.5-2677.42" wire $1\builder_comb_rhs_array_muxed17[0:0] - attribute \src "ls180.v:2665.12-2665.50" + attribute \src "ls180.v:2678.12-2678.50" wire width 22 $1\builder_comb_rhs_array_muxed18[21:0] - attribute \src "ls180.v:2666.5-2666.42" + attribute \src "ls180.v:2679.5-2679.42" wire $1\builder_comb_rhs_array_muxed19[0:0] - attribute \src "ls180.v:2642.12-2642.49" + attribute \src "ls180.v:2655.12-2655.49" wire width 13 $1\builder_comb_rhs_array_muxed1[12:0] - attribute \src "ls180.v:2667.5-2667.42" + attribute \src "ls180.v:2680.5-2680.42" wire $1\builder_comb_rhs_array_muxed20[0:0] - attribute \src "ls180.v:2668.12-2668.50" + attribute \src "ls180.v:2681.12-2681.50" wire width 22 $1\builder_comb_rhs_array_muxed21[21:0] - attribute \src "ls180.v:2669.5-2669.42" + attribute \src "ls180.v:2682.5-2682.42" wire $1\builder_comb_rhs_array_muxed22[0:0] - attribute \src "ls180.v:2670.5-2670.42" + attribute \src "ls180.v:2683.5-2683.42" wire $1\builder_comb_rhs_array_muxed23[0:0] - attribute \src "ls180.v:2671.12-2671.50" + attribute \src "ls180.v:2684.12-2684.50" wire width 32 $1\builder_comb_rhs_array_muxed24[31:0] - attribute \src "ls180.v:2672.12-2672.50" - wire width 32 $1\builder_comb_rhs_array_muxed25[31:0] - attribute \src "ls180.v:2673.11-2673.48" - wire width 4 $1\builder_comb_rhs_array_muxed26[3:0] - attribute \src "ls180.v:2674.5-2674.42" + attribute \src "ls180.v:2685.12-2685.50" + wire width 64 $1\builder_comb_rhs_array_muxed25[63:0] + attribute \src "ls180.v:2686.11-2686.48" + wire width 8 $1\builder_comb_rhs_array_muxed26[7:0] + attribute \src "ls180.v:2687.5-2687.42" wire $1\builder_comb_rhs_array_muxed27[0:0] - attribute \src "ls180.v:2675.5-2675.42" + attribute \src "ls180.v:2688.5-2688.42" wire $1\builder_comb_rhs_array_muxed28[0:0] - attribute \src "ls180.v:2676.5-2676.42" + attribute \src "ls180.v:2689.5-2689.42" wire $1\builder_comb_rhs_array_muxed29[0:0] - attribute \src "ls180.v:2643.11-2643.47" + attribute \src "ls180.v:2656.11-2656.47" wire width 2 $1\builder_comb_rhs_array_muxed2[1:0] - attribute \src "ls180.v:2677.11-2677.48" + attribute \src "ls180.v:2690.11-2690.48" wire width 3 $1\builder_comb_rhs_array_muxed30[2:0] - attribute \src "ls180.v:2678.11-2678.48" + attribute \src "ls180.v:2691.11-2691.48" wire width 2 $1\builder_comb_rhs_array_muxed31[1:0] - attribute \src "ls180.v:2644.5-2644.41" + attribute \src "ls180.v:2657.5-2657.41" wire $1\builder_comb_rhs_array_muxed3[0:0] - attribute \src "ls180.v:2645.5-2645.41" + attribute \src "ls180.v:2658.5-2658.41" wire $1\builder_comb_rhs_array_muxed4[0:0] - attribute \src "ls180.v:2646.5-2646.41" + attribute \src "ls180.v:2659.5-2659.41" wire $1\builder_comb_rhs_array_muxed5[0:0] - attribute \src "ls180.v:2650.5-2650.41" + attribute \src "ls180.v:2663.5-2663.41" wire $1\builder_comb_rhs_array_muxed6[0:0] - attribute \src "ls180.v:2651.12-2651.49" + attribute \src "ls180.v:2664.12-2664.49" wire width 13 $1\builder_comb_rhs_array_muxed7[12:0] - attribute \src "ls180.v:2652.11-2652.47" + attribute \src "ls180.v:2665.11-2665.47" wire width 2 $1\builder_comb_rhs_array_muxed8[1:0] - attribute \src "ls180.v:2653.5-2653.41" + attribute \src "ls180.v:2666.5-2666.41" wire $1\builder_comb_rhs_array_muxed9[0:0] - attribute \src "ls180.v:2647.5-2647.39" + attribute \src "ls180.v:2660.5-2660.39" wire $1\builder_comb_t_array_muxed0[0:0] - attribute \src "ls180.v:2648.5-2648.39" + attribute \src "ls180.v:2661.5-2661.39" wire $1\builder_comb_t_array_muxed1[0:0] - attribute \src "ls180.v:2649.5-2649.39" + attribute \src "ls180.v:2662.5-2662.39" wire $1\builder_comb_t_array_muxed2[0:0] - attribute \src "ls180.v:2656.5-2656.39" + attribute \src "ls180.v:2669.5-2669.39" wire $1\builder_comb_t_array_muxed3[0:0] - attribute \src "ls180.v:2657.5-2657.39" + attribute \src "ls180.v:2670.5-2670.39" wire $1\builder_comb_t_array_muxed4[0:0] - attribute \src "ls180.v:2658.5-2658.39" + attribute \src "ls180.v:2671.5-2671.39" wire $1\builder_comb_t_array_muxed5[0:0] - attribute \src "ls180.v:1776.5-1776.41" + attribute \src "ls180.v:1781.5-1781.41" wire $1\builder_converter0_next_state[0:0] - attribute \src "ls180.v:1775.5-1775.36" + attribute \src "ls180.v:1780.5-1780.36" wire $1\builder_converter0_state[0:0] - attribute \src "ls180.v:1780.5-1780.41" + attribute \src "ls180.v:1785.5-1785.41" wire $1\builder_converter1_next_state[0:0] - attribute \src "ls180.v:1779.5-1779.36" + attribute \src "ls180.v:1784.5-1784.36" wire $1\builder_converter1_state[0:0] - attribute \src "ls180.v:1784.5-1784.41" + attribute \src "ls180.v:1789.5-1789.41" wire $1\builder_converter2_next_state[0:0] - attribute \src "ls180.v:1783.5-1783.36" + attribute \src "ls180.v:1788.5-1788.36" wire $1\builder_converter2_state[0:0] - attribute \src "ls180.v:1821.5-1821.40" + attribute \src "ls180.v:1826.5-1826.40" wire $1\builder_converter_next_state[0:0] - attribute \src "ls180.v:1820.5-1820.35" + attribute \src "ls180.v:1825.5-1825.35" wire $1\builder_converter_state[0:0] - attribute \src "ls180.v:1941.12-1941.39" + attribute \src "ls180.v:1954.12-1954.39" wire width 20 $1\builder_count[19:0] - attribute \src "ls180.v:1938.5-1938.25" + attribute \src "ls180.v:1951.5-1951.25" wire $1\builder_error[0:0] - attribute \src "ls180.v:1935.11-1935.31" + attribute \src "ls180.v:1948.11-1948.31" wire width 3 $1\builder_grant[2:0] - attribute \src "ls180.v:1945.11-1945.51" + attribute \src "ls180.v:1958.11-1958.51" wire width 8 $1\builder_interface0_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2447.11-2447.52" + attribute \src "ls180.v:2460.11-2460.52" wire width 8 $1\builder_interface10_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2480.11-2480.52" + attribute \src "ls180.v:2493.11-2493.52" wire width 8 $1\builder_interface11_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2521.11-2521.52" + attribute \src "ls180.v:2534.11-2534.52" wire width 8 $1\builder_interface12_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2586.11-2586.52" + attribute \src "ls180.v:2599.11-2599.52" wire width 8 $1\builder_interface13_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2611.11-2611.52" + attribute \src "ls180.v:2624.11-2624.52" wire width 8 $1\builder_interface14_bank_bus_dat_r[7:0] - attribute \src "ls180.v:1986.11-1986.51" + attribute \src "ls180.v:1999.11-1999.51" wire width 8 $1\builder_interface1_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2015.11-2015.51" - wire width 8 $1\builder_interface2_bank_bus_dat_r[7:0] attribute \src "ls180.v:2028.11-2028.51" + wire width 8 $1\builder_interface2_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2041.11-2041.51" wire width 8 $1\builder_interface3_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2069.11-2069.51" + attribute \src "ls180.v:2082.11-2082.51" wire width 8 $1\builder_interface4_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2110.11-2110.51" + attribute \src "ls180.v:2123.11-2123.51" wire width 8 $1\builder_interface5_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2175.11-2175.51" + attribute \src "ls180.v:2188.11-2188.51" wire width 8 $1\builder_interface6_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2308.11-2308.51" + attribute \src "ls180.v:2321.11-2321.51" wire width 8 $1\builder_interface7_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2389.11-2389.51" + attribute \src "ls180.v:2402.11-2402.51" wire width 8 $1\builder_interface8_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2406.11-2406.51" + attribute \src "ls180.v:2419.11-2419.51" wire width 8 $1\builder_interface9_bank_bus_dat_r[7:0] - attribute \src "ls180.v:1908.12-1908.43" + attribute \src "ls180.v:1913.12-1913.43" wire width 14 $1\builder_libresocsim_adr[13:0] - attribute \src "ls180.v:2637.12-2637.55" + attribute \src "ls180.v:2650.12-2650.55" wire width 14 $1\builder_libresocsim_adr_next_value1[13:0] - attribute \src "ls180.v:2638.5-2638.50" + attribute \src "ls180.v:2651.5-2651.50" wire $1\builder_libresocsim_adr_next_value_ce1[0:0] - attribute \src "ls180.v:1910.11-1910.43" + attribute \src "ls180.v:1915.11-1915.43" wire width 8 $1\builder_libresocsim_dat_w[7:0] - attribute \src "ls180.v:2635.11-2635.55" + attribute \src "ls180.v:2648.11-2648.55" wire width 8 $1\builder_libresocsim_dat_w_next_value0[7:0] - attribute \src "ls180.v:2636.5-2636.52" + attribute \src "ls180.v:2649.5-2649.52" wire $1\builder_libresocsim_dat_w_next_value_ce0[0:0] - attribute \src "ls180.v:1909.5-1909.34" + attribute \src "ls180.v:1914.5-1914.34" wire $1\builder_libresocsim_we[0:0] - attribute \src "ls180.v:2639.5-2639.46" + attribute \src "ls180.v:2652.5-2652.46" wire $1\builder_libresocsim_we_next_value2[0:0] - attribute \src "ls180.v:2640.5-2640.49" + attribute \src "ls180.v:2653.5-2653.49" wire $1\builder_libresocsim_we_next_value_ce2[0:0] - attribute \src "ls180.v:1918.5-1918.44" + attribute \src "ls180.v:1923.5-1923.44" wire $1\builder_libresocsim_wishbone_ack[0:0] - attribute \src "ls180.v:1914.12-1914.54" + attribute \src "ls180.v:1919.12-1919.54" wire width 32 $1\builder_libresocsim_wishbone_dat_r[31:0] - attribute \src "ls180.v:1798.11-1798.48" + attribute \src "ls180.v:1803.11-1803.48" wire width 3 $1\builder_multiplexer_next_state[2:0] - attribute \src "ls180.v:1797.11-1797.43" + attribute \src "ls180.v:1802.11-1802.43" wire width 3 $1\builder_multiplexer_state[2:0] - attribute \src "ls180.v:2744.32-2744.66" + attribute \src "ls180.v:2757.32-2757.66" wire $1\builder_multiregimpl0_regs0[0:0] - attribute \src "ls180.v:2745.32-2745.66" + attribute \src "ls180.v:2758.32-2758.66" wire $1\builder_multiregimpl0_regs1[0:0] - attribute \src "ls180.v:2764.32-2764.67" + attribute \src "ls180.v:2777.32-2777.67" wire $1\builder_multiregimpl10_regs0[0:0] - attribute \src "ls180.v:2765.32-2765.67" + attribute \src "ls180.v:2778.32-2778.67" wire $1\builder_multiregimpl10_regs1[0:0] - attribute \src "ls180.v:2766.32-2766.67" + attribute \src "ls180.v:2779.32-2779.67" wire $1\builder_multiregimpl11_regs0[0:0] - attribute \src "ls180.v:2767.32-2767.67" + attribute \src "ls180.v:2780.32-2780.67" wire $1\builder_multiregimpl11_regs1[0:0] - attribute \src "ls180.v:2768.32-2768.67" + attribute \src "ls180.v:2781.32-2781.67" wire $1\builder_multiregimpl12_regs0[0:0] - attribute \src "ls180.v:2769.32-2769.67" + attribute \src "ls180.v:2782.32-2782.67" wire $1\builder_multiregimpl12_regs1[0:0] - attribute \src "ls180.v:2770.32-2770.67" + attribute \src "ls180.v:2783.32-2783.67" wire $1\builder_multiregimpl13_regs0[0:0] - attribute \src "ls180.v:2771.32-2771.67" + attribute \src "ls180.v:2784.32-2784.67" wire $1\builder_multiregimpl13_regs1[0:0] - attribute \src "ls180.v:2772.32-2772.67" + attribute \src "ls180.v:2785.32-2785.67" wire $1\builder_multiregimpl14_regs0[0:0] - attribute \src "ls180.v:2773.32-2773.67" + attribute \src "ls180.v:2786.32-2786.67" wire $1\builder_multiregimpl14_regs1[0:0] - attribute \src "ls180.v:2774.32-2774.67" + attribute \src "ls180.v:2787.32-2787.67" wire $1\builder_multiregimpl15_regs0[0:0] - attribute \src "ls180.v:2775.32-2775.67" + attribute \src "ls180.v:2788.32-2788.67" wire $1\builder_multiregimpl15_regs1[0:0] - attribute \src "ls180.v:2776.32-2776.67" + attribute \src "ls180.v:2789.32-2789.67" wire $1\builder_multiregimpl16_regs0[0:0] - attribute \src "ls180.v:2777.32-2777.67" + attribute \src "ls180.v:2790.32-2790.67" wire $1\builder_multiregimpl16_regs1[0:0] - attribute \src "ls180.v:2746.32-2746.66" + attribute \src "ls180.v:2759.32-2759.66" wire $1\builder_multiregimpl1_regs0[0:0] - attribute \src "ls180.v:2747.32-2747.66" + attribute \src "ls180.v:2760.32-2760.66" wire $1\builder_multiregimpl1_regs1[0:0] - attribute \src "ls180.v:2748.32-2748.66" + attribute \src "ls180.v:2761.32-2761.66" wire $1\builder_multiregimpl2_regs0[0:0] - attribute \src "ls180.v:2749.32-2749.66" + attribute \src "ls180.v:2762.32-2762.66" wire $1\builder_multiregimpl2_regs1[0:0] - attribute \src "ls180.v:2750.32-2750.66" + attribute \src "ls180.v:2763.32-2763.66" wire $1\builder_multiregimpl3_regs0[0:0] - attribute \src "ls180.v:2751.32-2751.66" + attribute \src "ls180.v:2764.32-2764.66" wire $1\builder_multiregimpl3_regs1[0:0] - attribute \src "ls180.v:2752.32-2752.66" + attribute \src "ls180.v:2765.32-2765.66" wire $1\builder_multiregimpl4_regs0[0:0] - attribute \src "ls180.v:2753.32-2753.66" + attribute \src "ls180.v:2766.32-2766.66" wire $1\builder_multiregimpl4_regs1[0:0] - attribute \src "ls180.v:2754.32-2754.66" + attribute \src "ls180.v:2767.32-2767.66" wire $1\builder_multiregimpl5_regs0[0:0] - attribute \src "ls180.v:2755.32-2755.66" + attribute \src "ls180.v:2768.32-2768.66" wire $1\builder_multiregimpl5_regs1[0:0] - attribute \src "ls180.v:2756.32-2756.66" + attribute \src "ls180.v:2769.32-2769.66" wire $1\builder_multiregimpl6_regs0[0:0] - attribute \src "ls180.v:2757.32-2757.66" + attribute \src "ls180.v:2770.32-2770.66" wire $1\builder_multiregimpl6_regs1[0:0] - attribute \src "ls180.v:2758.32-2758.66" + attribute \src "ls180.v:2771.32-2771.66" wire $1\builder_multiregimpl7_regs0[0:0] - attribute \src "ls180.v:2759.32-2759.66" + attribute \src "ls180.v:2772.32-2772.66" wire $1\builder_multiregimpl7_regs1[0:0] - attribute \src "ls180.v:2760.32-2760.66" + attribute \src "ls180.v:2773.32-2773.66" wire $1\builder_multiregimpl8_regs0[0:0] - attribute \src "ls180.v:2761.32-2761.66" + attribute \src "ls180.v:2774.32-2774.66" wire $1\builder_multiregimpl8_regs1[0:0] - attribute \src "ls180.v:2762.32-2762.66" + attribute \src "ls180.v:2775.32-2775.66" wire $1\builder_multiregimpl9_regs0[0:0] - attribute \src "ls180.v:2763.32-2763.66" + attribute \src "ls180.v:2776.32-2776.66" wire $1\builder_multiregimpl9_regs1[0:0] - attribute \src "ls180.v:1816.5-1816.43" + attribute \src "ls180.v:1821.5-1821.43" wire $1\builder_new_master_rdata_valid0[0:0] - attribute \src "ls180.v:1817.5-1817.43" + attribute \src "ls180.v:1822.5-1822.43" wire $1\builder_new_master_rdata_valid1[0:0] - attribute \src "ls180.v:1818.5-1818.43" + attribute \src "ls180.v:1823.5-1823.43" wire $1\builder_new_master_rdata_valid2[0:0] - attribute \src "ls180.v:1819.5-1819.43" + attribute \src "ls180.v:1824.5-1824.43" wire $1\builder_new_master_rdata_valid3[0:0] - attribute \src "ls180.v:1815.5-1815.42" + attribute \src "ls180.v:1820.5-1820.42" wire $1\builder_new_master_wdata_ready[0:0] - attribute \src "ls180.v:2634.11-2634.36" + attribute \src "ls180.v:2647.11-2647.36" wire width 2 $1\builder_next_state[1:0] - attribute \src "ls180.v:1788.11-1788.46" + attribute \src "ls180.v:1793.11-1793.46" wire width 2 $1\builder_refresher_next_state[1:0] - attribute \src "ls180.v:1787.11-1787.41" + attribute \src "ls180.v:1792.11-1792.41" wire width 2 $1\builder_refresher_state[1:0] - attribute \src "ls180.v:1897.11-1897.51" + attribute \src "ls180.v:1902.11-1902.51" wire width 2 $1\builder_sdblock2memdma_next_state[1:0] - attribute \src "ls180.v:1896.11-1896.46" + attribute \src "ls180.v:1901.11-1901.46" wire width 2 $1\builder_sdblock2memdma_state[1:0] - attribute \src "ls180.v:1865.5-1865.57" + attribute \src "ls180.v:1870.5-1870.57" wire $1\builder_sdcore_crcupstreaminserter_next_state[0:0] - attribute \src "ls180.v:1864.5-1864.52" + attribute \src "ls180.v:1869.5-1869.52" wire $1\builder_sdcore_crcupstreaminserter_state[0:0] - attribute \src "ls180.v:1877.11-1877.47" + attribute \src "ls180.v:1882.11-1882.47" wire width 3 $1\builder_sdcore_fsm_next_state[2:0] - attribute \src "ls180.v:1876.11-1876.42" + attribute \src "ls180.v:1881.11-1881.42" wire width 3 $1\builder_sdcore_fsm_state[2:0] - attribute \src "ls180.v:1901.5-1901.49" + attribute \src "ls180.v:1906.5-1906.49" wire $1\builder_sdmem2blockdma_fsm_next_state[0:0] - attribute \src "ls180.v:1900.5-1900.44" + attribute \src "ls180.v:1905.5-1905.44" wire $1\builder_sdmem2blockdma_fsm_state[0:0] - attribute \src "ls180.v:1905.11-1905.65" + attribute \src "ls180.v:1910.11-1910.65" wire width 2 $1\builder_sdmem2blockdma_resetinserter_next_state[1:0] - attribute \src "ls180.v:1904.11-1904.60" + attribute \src "ls180.v:1909.11-1909.60" wire width 2 $1\builder_sdmem2blockdma_resetinserter_state[1:0] - attribute \src "ls180.v:1853.11-1853.46" + attribute \src "ls180.v:1858.11-1858.46" wire width 3 $1\builder_sdphy_fsm_next_state[2:0] - attribute \src "ls180.v:1852.11-1852.41" + attribute \src "ls180.v:1857.11-1857.41" wire width 3 $1\builder_sdphy_fsm_state[2:0] - attribute \src "ls180.v:1841.11-1841.52" + attribute \src "ls180.v:1846.11-1846.52" wire width 3 $1\builder_sdphy_sdphycmdr_next_state[2:0] - attribute \src "ls180.v:1840.11-1840.47" + attribute \src "ls180.v:1845.11-1845.47" wire width 3 $1\builder_sdphy_sdphycmdr_state[2:0] - attribute \src "ls180.v:1837.11-1837.52" + attribute \src "ls180.v:1842.11-1842.52" wire width 2 $1\builder_sdphy_sdphycmdw_next_state[1:0] - attribute \src "ls180.v:1836.11-1836.47" + attribute \src "ls180.v:1841.11-1841.47" wire width 2 $1\builder_sdphy_sdphycmdw_state[1:0] - attribute \src "ls180.v:1849.5-1849.46" + attribute \src "ls180.v:1854.5-1854.46" wire $1\builder_sdphy_sdphycrcr_next_state[0:0] - attribute \src "ls180.v:1848.5-1848.41" + attribute \src "ls180.v:1853.5-1853.41" wire $1\builder_sdphy_sdphycrcr_state[0:0] - attribute \src "ls180.v:1857.11-1857.53" + attribute \src "ls180.v:1862.11-1862.53" wire width 3 $1\builder_sdphy_sdphydatar_next_state[2:0] - attribute \src "ls180.v:1856.11-1856.48" + attribute \src "ls180.v:1861.11-1861.48" wire width 3 $1\builder_sdphy_sdphydatar_state[2:0] - attribute \src "ls180.v:1833.5-1833.46" + attribute \src "ls180.v:1838.5-1838.46" wire $1\builder_sdphy_sdphyinit_next_state[0:0] - attribute \src "ls180.v:1832.5-1832.41" + attribute \src "ls180.v:1837.5-1837.41" wire $1\builder_sdphy_sdphyinit_state[0:0] - attribute \src "ls180.v:1929.5-1929.30" + attribute \src "ls180.v:1942.5-1942.30" wire $1\builder_shared_ack[0:0] - attribute \src "ls180.v:1925.12-1925.40" + attribute \src "ls180.v:1938.12-1938.40" wire width 32 $1\builder_shared_dat_r[31:0] - attribute \src "ls180.v:1936.11-1936.35" + attribute \src "ls180.v:1949.11-1949.35" wire width 8 $1\builder_slave_sel[7:0] - attribute \src "ls180.v:1937.11-1937.37" + attribute \src "ls180.v:1950.11-1950.37" wire width 8 $1\builder_slave_sel_r[7:0] - attribute \src "ls180.v:1825.11-1825.47" + attribute \src "ls180.v:1830.11-1830.47" wire width 2 $1\builder_spimaster0_next_state[1:0] - attribute \src "ls180.v:1824.11-1824.42" + attribute \src "ls180.v:1829.11-1829.42" wire width 2 $1\builder_spimaster0_state[1:0] - attribute \src "ls180.v:1829.11-1829.47" + attribute \src "ls180.v:1834.11-1834.47" wire width 2 $1\builder_spimaster1_next_state[1:0] - attribute \src "ls180.v:1828.11-1828.42" + attribute \src "ls180.v:1833.11-1833.42" wire width 2 $1\builder_spimaster1_state[1:0] - attribute \src "ls180.v:2633.11-2633.31" + attribute \src "ls180.v:2646.11-2646.31" wire width 2 $1\builder_state[1:0] - attribute \src "ls180.v:2686.5-2686.39" + attribute \src "ls180.v:2699.5-2699.39" wire $1\builder_sync_f_array_muxed0[0:0] - attribute \src "ls180.v:2687.5-2687.39" + attribute \src "ls180.v:2700.5-2700.39" wire $1\builder_sync_f_array_muxed1[0:0] - attribute \src "ls180.v:2679.11-2679.47" + attribute \src "ls180.v:2692.11-2692.47" wire width 2 $1\builder_sync_rhs_array_muxed0[1:0] - attribute \src "ls180.v:2680.12-2680.49" + attribute \src "ls180.v:2693.12-2693.49" wire width 13 $1\builder_sync_rhs_array_muxed1[12:0] - attribute \src "ls180.v:2681.5-2681.41" + attribute \src "ls180.v:2694.5-2694.41" wire $1\builder_sync_rhs_array_muxed2[0:0] - attribute \src "ls180.v:2682.5-2682.41" + attribute \src "ls180.v:2695.5-2695.41" wire $1\builder_sync_rhs_array_muxed3[0:0] - attribute \src "ls180.v:2683.5-2683.41" + attribute \src "ls180.v:2696.5-2696.41" wire $1\builder_sync_rhs_array_muxed4[0:0] - attribute \src "ls180.v:2684.5-2684.41" + attribute \src "ls180.v:2697.5-2697.41" wire $1\builder_sync_rhs_array_muxed5[0:0] - attribute \src "ls180.v:2685.5-2685.41" + attribute \src "ls180.v:2698.5-2698.41" wire $1\builder_sync_rhs_array_muxed6[0:0] - attribute \src "ls180.v:877.5-877.29" + attribute \src "ls180.v:876.5-876.29" wire $1\main_cmd_consumed[0:0] - attribute \src "ls180.v:874.5-874.34" + attribute \src "ls180.v:259.5-259.35" + wire $1\main_converter0_counter[0:0] + attribute \src "ls180.v:1782.5-1782.57" + wire $1\main_converter0_counter_converter0_next_value[0:0] + attribute \src "ls180.v:1783.5-1783.60" + wire $1\main_converter0_counter_converter0_next_value_ce[0:0] + attribute \src "ls180.v:261.12-261.41" + wire width 64 $1\main_converter0_dat_r[63:0] + attribute \src "ls180.v:258.5-258.32" + wire $1\main_converter0_skip[0:0] + attribute \src "ls180.v:274.5-274.35" + wire $1\main_converter1_counter[0:0] + attribute \src "ls180.v:1786.5-1786.57" + wire $1\main_converter1_counter_converter1_next_value[0:0] + attribute \src "ls180.v:1787.5-1787.60" + wire $1\main_converter1_counter_converter1_next_value_ce[0:0] + attribute \src "ls180.v:276.12-276.41" + wire width 64 $1\main_converter1_dat_r[63:0] + attribute \src "ls180.v:273.5-273.32" + wire $1\main_converter1_skip[0:0] + attribute \src "ls180.v:873.5-873.34" wire $1\main_converter_counter[0:0] - attribute \src "ls180.v:1822.5-1822.55" + attribute \src "ls180.v:1827.5-1827.55" wire $1\main_converter_counter_converter_next_value[0:0] - attribute \src "ls180.v:1823.5-1823.58" + attribute \src "ls180.v:1828.5-1828.58" wire $1\main_converter_counter_converter_next_value_ce[0:0] - attribute \src "ls180.v:876.12-876.40" + attribute \src "ls180.v:875.12-875.40" wire width 32 $1\main_converter_dat_r[31:0] - attribute \src "ls180.v:873.5-873.31" + attribute \src "ls180.v:872.5-872.31" wire $1\main_converter_skip[0:0] - attribute \src "ls180.v:308.12-308.38" + attribute \src "ls180.v:295.12-295.38" wire width 16 $1\main_dfi_p0_rddata[15:0] - attribute \src "ls180.v:309.5-309.36" + attribute \src "ls180.v:296.5-296.36" wire $1\main_dfi_p0_rddata_valid[0:0] - attribute \src "ls180.v:1108.12-1108.30" + attribute \src "ls180.v:1113.12-1113.30" wire width 24 $1\main_dummy[23:0] - attribute \src "ls180.v:1025.5-1025.27" - wire $1\main_gpio_oe_re[0:0] - attribute \src "ls180.v:1024.12-1024.40" - wire width 16 $1\main_gpio_oe_storage[15:0] - attribute \src "ls180.v:1029.5-1029.28" - wire $1\main_gpio_out_re[0:0] - attribute \src "ls180.v:1028.12-1028.41" - wire width 16 $1\main_gpio_out_storage[15:0] - attribute \src "ls180.v:1026.12-1026.36" - wire width 16 $1\main_gpio_status[15:0] - attribute \src "ls180.v:1133.5-1133.23" + attribute \src "ls180.v:1024.12-1024.49" + wire width 16 $1\main_gpiotristateasic0_status[15:0] + attribute \src "ls180.v:1030.5-1030.40" + wire $1\main_gpiotristateasic1_oe_re[0:0] + attribute \src "ls180.v:1029.12-1029.53" + wire width 16 $1\main_gpiotristateasic1_oe_storage[15:0] + attribute \src "ls180.v:1034.5-1034.41" + wire $1\main_gpiotristateasic1_out_re[0:0] + attribute \src "ls180.v:1033.12-1033.54" + wire width 16 $1\main_gpiotristateasic1_out_storage[15:0] + attribute \src "ls180.v:1031.12-1031.49" + wire width 16 $1\main_gpiotristateasic1_status[15:0] + attribute \src "ls180.v:1138.5-1138.23" wire $1\main_i2c_re[0:0] - attribute \src "ls180.v:1132.11-1132.34" + attribute \src "ls180.v:1137.11-1137.34" wire width 3 $1\main_i2c_storage[2:0] - attribute \src "ls180.v:293.5-293.24" + attribute \src "ls180.v:280.5-280.24" wire $1\main_int_rst[0:0] - attribute \src "ls180.v:251.5-251.39" + attribute \src "ls180.v:253.5-253.51" + wire $1\main_interface0_converted_interface_ack[0:0] + attribute \src "ls180.v:208.5-208.39" wire $1\main_interface0_ram_bus_ack[0:0] - attribute \src "ls180.v:1681.12-1681.43" + attribute \src "ls180.v:1686.12-1686.43" wire width 32 $1\main_interface1_bus_adr[31:0] - attribute \src "ls180.v:1685.5-1685.35" + attribute \src "ls180.v:1690.5-1690.35" wire $1\main_interface1_bus_cyc[0:0] - attribute \src "ls180.v:1684.11-1684.41" - wire width 4 $1\main_interface1_bus_sel[3:0] - attribute \src "ls180.v:1686.5-1686.35" + attribute \src "ls180.v:1689.11-1689.41" + wire width 8 $1\main_interface1_bus_sel[7:0] + attribute \src "ls180.v:1691.5-1691.35" wire $1\main_interface1_bus_stb[0:0] - attribute \src "ls180.v:1688.5-1688.34" + attribute \src "ls180.v:1693.5-1693.34" wire $1\main_interface1_bus_we[0:0] - attribute \src "ls180.v:266.5-266.39" + attribute \src "ls180.v:268.5-268.51" + wire $1\main_interface1_converted_interface_ack[0:0] + attribute \src "ls180.v:223.5-223.39" wire $1\main_interface1_ram_bus_ack[0:0] - attribute \src "ls180.v:281.5-281.39" + attribute \src "ls180.v:238.5-238.39" wire $1\main_interface2_ram_bus_ack[0:0] attribute \src "ls180.v:63.12-63.47" wire width 32 $1\main_libresocsim_bus_errors[31:0] - attribute \src "ls180.v:170.5-170.47" - wire $1\main_libresocsim_converter0_counter[0:0] - attribute \src "ls180.v:1777.5-1777.69" - wire $1\main_libresocsim_converter0_counter_converter0_next_value[0:0] - attribute \src "ls180.v:1778.5-1778.72" - wire $1\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] - attribute \src "ls180.v:172.12-172.53" - wire width 64 $1\main_libresocsim_converter0_dat_r[63:0] - attribute \src "ls180.v:169.5-169.44" - wire $1\main_libresocsim_converter0_skip[0:0] - attribute \src "ls180.v:185.5-185.47" - wire $1\main_libresocsim_converter1_counter[0:0] - attribute \src "ls180.v:1781.5-1781.69" - wire $1\main_libresocsim_converter1_counter_converter1_next_value[0:0] - attribute \src "ls180.v:1782.5-1782.72" - wire $1\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] - attribute \src "ls180.v:187.12-187.53" - wire width 64 $1\main_libresocsim_converter1_dat_r[63:0] - attribute \src "ls180.v:184.5-184.44" - wire $1\main_libresocsim_converter1_skip[0:0] - attribute \src "ls180.v:200.5-200.47" - wire $1\main_libresocsim_converter2_counter[0:0] - attribute \src "ls180.v:1785.5-1785.69" - wire $1\main_libresocsim_converter2_counter_converter2_next_value[0:0] - attribute \src "ls180.v:1786.5-1786.72" - wire $1\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] - attribute \src "ls180.v:202.12-202.53" - wire width 64 $1\main_libresocsim_converter2_dat_r[63:0] - attribute \src "ls180.v:199.5-199.44" - wire $1\main_libresocsim_converter2_skip[0:0] - attribute \src "ls180.v:223.5-223.34" + attribute \src "ls180.v:180.5-180.34" wire $1\main_libresocsim_en_re[0:0] - attribute \src "ls180.v:222.5-222.39" + attribute \src "ls180.v:179.5-179.39" wire $1\main_libresocsim_en_storage[0:0] - attribute \src "ls180.v:243.5-243.44" + attribute \src "ls180.v:200.5-200.44" wire $1\main_libresocsim_eventmanager_re[0:0] - attribute \src "ls180.v:242.5-242.49" + attribute \src "ls180.v:199.5-199.49" wire $1\main_libresocsim_eventmanager_storage[0:0] - attribute \src "ls180.v:158.12-158.71" - wire width 30 $1\main_libresocsim_interface0_converted_interface_adr[29:0] - attribute \src "ls180.v:162.5-162.63" - wire $1\main_libresocsim_interface0_converted_interface_cyc[0:0] - attribute \src "ls180.v:159.12-159.73" - wire width 32 $1\main_libresocsim_interface0_converted_interface_dat_w[31:0] - attribute \src "ls180.v:161.11-161.69" - wire width 4 $1\main_libresocsim_interface0_converted_interface_sel[3:0] - attribute \src "ls180.v:163.5-163.63" - wire $1\main_libresocsim_interface0_converted_interface_stb[0:0] - attribute \src "ls180.v:165.5-165.62" - wire $1\main_libresocsim_interface0_converted_interface_we[0:0] - attribute \src "ls180.v:173.12-173.71" - wire width 30 $1\main_libresocsim_interface1_converted_interface_adr[29:0] - attribute \src "ls180.v:177.5-177.63" - wire $1\main_libresocsim_interface1_converted_interface_cyc[0:0] - attribute \src "ls180.v:174.12-174.73" - wire width 32 $1\main_libresocsim_interface1_converted_interface_dat_w[31:0] - attribute \src "ls180.v:176.11-176.69" - wire width 4 $1\main_libresocsim_interface1_converted_interface_sel[3:0] - attribute \src "ls180.v:178.5-178.63" - wire $1\main_libresocsim_interface1_converted_interface_stb[0:0] - attribute \src "ls180.v:180.5-180.62" - wire $1\main_libresocsim_interface1_converted_interface_we[0:0] - attribute \src "ls180.v:188.12-188.71" - wire width 30 $1\main_libresocsim_interface2_converted_interface_adr[29:0] - attribute \src "ls180.v:192.5-192.63" - wire $1\main_libresocsim_interface2_converted_interface_cyc[0:0] - attribute \src "ls180.v:189.12-189.73" - wire width 32 $1\main_libresocsim_interface2_converted_interface_dat_w[31:0] - attribute \src "ls180.v:191.11-191.69" - wire width 4 $1\main_libresocsim_interface2_converted_interface_sel[3:0] - attribute \src "ls180.v:193.5-193.63" - wire $1\main_libresocsim_interface2_converted_interface_stb[0:0] - attribute \src "ls180.v:195.5-195.62" - wire $1\main_libresocsim_interface2_converted_interface_we[0:0] - attribute \src "ls180.v:72.5-72.46" - wire $1\main_libresocsim_libresoc_dbus_ack[0:0] - attribute \src "ls180.v:81.5-81.46" - wire $1\main_libresocsim_libresoc_ibus_ack[0:0] attribute \src "ls180.v:65.12-65.55" wire width 16 $1\main_libresocsim_libresoc_interrupt[15:0] - attribute \src "ls180.v:112.5-112.49" - wire $1\main_libresocsim_libresoc_jtag_wb_ack[0:0] - attribute \src "ls180.v:219.5-219.36" + attribute \src "ls180.v:88.12-88.58" + wire width 30 $1\main_libresocsim_libresoc_xics_icp_adr[29:0] + attribute \src "ls180.v:92.5-92.50" + wire $1\main_libresocsim_libresoc_xics_icp_cyc[0:0] + attribute \src "ls180.v:89.12-89.60" + wire width 32 $1\main_libresocsim_libresoc_xics_icp_dat_w[31:0] + attribute \src "ls180.v:91.11-91.56" + wire width 4 $1\main_libresocsim_libresoc_xics_icp_sel[3:0] + attribute \src "ls180.v:93.5-93.50" + wire $1\main_libresocsim_libresoc_xics_icp_stb[0:0] + attribute \src "ls180.v:95.5-95.49" + wire $1\main_libresocsim_libresoc_xics_icp_we[0:0] + attribute \src "ls180.v:97.12-97.58" + wire width 30 $1\main_libresocsim_libresoc_xics_ics_adr[29:0] + attribute \src "ls180.v:101.5-101.50" + wire $1\main_libresocsim_libresoc_xics_ics_cyc[0:0] + attribute \src "ls180.v:98.12-98.60" + wire width 32 $1\main_libresocsim_libresoc_xics_ics_dat_w[31:0] + attribute \src "ls180.v:100.11-100.56" + wire width 4 $1\main_libresocsim_libresoc_xics_ics_sel[3:0] + attribute \src "ls180.v:102.5-102.50" + wire $1\main_libresocsim_libresoc_xics_ics_stb[0:0] + attribute \src "ls180.v:104.5-104.49" + wire $1\main_libresocsim_libresoc_xics_ics_we[0:0] + attribute \src "ls180.v:176.5-176.36" wire $1\main_libresocsim_load_re[0:0] - attribute \src "ls180.v:218.12-218.49" + attribute \src "ls180.v:175.12-175.49" wire width 32 $1\main_libresocsim_load_storage[31:0] - attribute \src "ls180.v:209.5-209.40" + attribute \src "ls180.v:166.5-166.40" wire $1\main_libresocsim_ram_bus_ack[0:0] - attribute \src "ls180.v:221.5-221.38" + attribute \src "ls180.v:178.5-178.38" wire $1\main_libresocsim_reload_re[0:0] - attribute \src "ls180.v:220.12-220.51" + attribute \src "ls180.v:177.12-177.51" wire width 32 $1\main_libresocsim_reload_storage[31:0] attribute \src "ls180.v:56.5-56.37" wire $1\main_libresocsim_reset_re[0:0] @@ -223313,8358 +223411,8590 @@ module \ls180 wire $1\main_libresocsim_scratch_re[0:0] attribute \src "ls180.v:57.12-57.60" wire width 32 $1\main_libresocsim_scratch_storage[31:0] - attribute \src "ls180.v:225.5-225.44" + attribute \src "ls180.v:182.5-182.44" wire $1\main_libresocsim_update_value_re[0:0] - attribute \src "ls180.v:224.5-224.49" + attribute \src "ls180.v:181.5-181.49" wire $1\main_libresocsim_update_value_storage[0:0] - attribute \src "ls180.v:244.12-244.42" + attribute \src "ls180.v:201.12-201.42" wire width 32 $1\main_libresocsim_value[31:0] - attribute \src "ls180.v:226.12-226.49" + attribute \src "ls180.v:183.12-183.49" wire width 32 $1\main_libresocsim_value_status[31:0] - attribute \src "ls180.v:216.11-216.37" - wire width 4 $1\main_libresocsim_we[3:0] - attribute \src "ls180.v:232.5-232.39" + attribute \src "ls180.v:173.11-173.37" + wire width 8 $1\main_libresocsim_we[7:0] + attribute \src "ls180.v:189.5-189.39" wire $1\main_libresocsim_zero_clear[0:0] - attribute \src "ls180.v:233.5-233.45" + attribute \src "ls180.v:190.5-190.45" wire $1\main_libresocsim_zero_old_trigger[0:0] - attribute \src "ls180.v:230.5-230.41" + attribute \src "ls180.v:187.5-187.41" wire $1\main_libresocsim_zero_pending[0:0] - attribute \src "ls180.v:865.12-865.40" + attribute \src "ls180.v:864.12-864.40" wire width 30 $1\main_litedram_wb_adr[29:0] - attribute \src "ls180.v:869.5-869.32" + attribute \src "ls180.v:868.5-868.32" wire $1\main_litedram_wb_cyc[0:0] - attribute \src "ls180.v:866.12-866.42" + attribute \src "ls180.v:865.12-865.42" wire width 16 $1\main_litedram_wb_dat_w[15:0] - attribute \src "ls180.v:868.11-868.38" + attribute \src "ls180.v:867.11-867.38" wire width 2 $1\main_litedram_wb_sel[1:0] - attribute \src "ls180.v:870.5-870.32" + attribute \src "ls180.v:869.5-869.32" wire $1\main_litedram_wb_stb[0:0] - attribute \src "ls180.v:872.5-872.31" + attribute \src "ls180.v:871.5-871.31" wire $1\main_litedram_wb_we[0:0] - attribute \src "ls180.v:1112.12-1112.37" + attribute \src "ls180.v:1117.12-1117.37" wire width 32 $1\main_pwm0_counter[31:0] - attribute \src "ls180.v:1114.5-1114.31" + attribute \src "ls180.v:1119.5-1119.31" wire $1\main_pwm0_enable_re[0:0] - attribute \src "ls180.v:1113.5-1113.36" + attribute \src "ls180.v:1118.5-1118.36" wire $1\main_pwm0_enable_storage[0:0] - attribute \src "ls180.v:1118.5-1118.31" + attribute \src "ls180.v:1123.5-1123.31" wire $1\main_pwm0_period_re[0:0] - attribute \src "ls180.v:1117.12-1117.44" + attribute \src "ls180.v:1122.12-1122.44" wire width 32 $1\main_pwm0_period_storage[31:0] - attribute \src "ls180.v:1116.5-1116.30" + attribute \src "ls180.v:1121.5-1121.30" wire $1\main_pwm0_width_re[0:0] - attribute \src "ls180.v:1115.12-1115.43" + attribute \src "ls180.v:1120.12-1120.43" wire width 32 $1\main_pwm0_width_storage[31:0] - attribute \src "ls180.v:1122.12-1122.37" + attribute \src "ls180.v:1127.12-1127.37" wire width 32 $1\main_pwm1_counter[31:0] - attribute \src "ls180.v:1124.5-1124.31" + attribute \src "ls180.v:1129.5-1129.31" wire $1\main_pwm1_enable_re[0:0] - attribute \src "ls180.v:1123.5-1123.36" + attribute \src "ls180.v:1128.5-1128.36" wire $1\main_pwm1_enable_storage[0:0] - attribute \src "ls180.v:1128.5-1128.31" + attribute \src "ls180.v:1133.5-1133.31" wire $1\main_pwm1_period_re[0:0] - attribute \src "ls180.v:1127.12-1127.44" + attribute \src "ls180.v:1132.12-1132.44" wire width 32 $1\main_pwm1_period_storage[31:0] - attribute \src "ls180.v:1126.5-1126.30" + attribute \src "ls180.v:1131.5-1131.30" wire $1\main_pwm1_width_re[0:0] - attribute \src "ls180.v:1125.12-1125.43" + attribute \src "ls180.v:1130.12-1130.43" wire width 32 $1\main_pwm1_width_storage[31:0] - attribute \src "ls180.v:310.11-310.32" + attribute \src "ls180.v:297.11-297.32" wire width 3 $1\main_rddata_en[2:0] - attribute \src "ls180.v:1650.11-1650.50" - wire width 2 $1\main_sdblock2mem_converter_demux[1:0] - attribute \src "ls180.v:1646.5-1646.51" + attribute \src "ls180.v:1655.11-1655.50" + wire width 3 $1\main_sdblock2mem_converter_demux[2:0] + attribute \src "ls180.v:1651.5-1651.51" wire $1\main_sdblock2mem_converter_source_first[0:0] - attribute \src "ls180.v:1647.5-1647.50" + attribute \src "ls180.v:1652.5-1652.50" wire $1\main_sdblock2mem_converter_source_last[0:0] - attribute \src "ls180.v:1648.12-1648.66" - wire width 32 $1\main_sdblock2mem_converter_source_payload_data[31:0] - attribute \src "ls180.v:1649.11-1649.77" - wire width 3 $1\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] - attribute \src "ls180.v:1652.5-1652.49" + attribute \src "ls180.v:1653.12-1653.66" + wire width 64 $1\main_sdblock2mem_converter_source_payload_data[63:0] + attribute \src "ls180.v:1654.11-1654.77" + wire width 4 $1\main_sdblock2mem_converter_source_payload_valid_token_count[3:0] + attribute \src "ls180.v:1657.5-1657.49" wire $1\main_sdblock2mem_converter_strobe_all[0:0] - attribute \src "ls180.v:1625.11-1625.47" + attribute \src "ls180.v:1630.11-1630.47" wire width 5 $1\main_sdblock2mem_fifo_consume[4:0] - attribute \src "ls180.v:1622.11-1622.45" + attribute \src "ls180.v:1627.11-1627.45" wire width 6 $1\main_sdblock2mem_fifo_level[5:0] - attribute \src "ls180.v:1624.11-1624.47" + attribute \src "ls180.v:1629.11-1629.47" wire width 5 $1\main_sdblock2mem_fifo_produce[4:0] - attribute \src "ls180.v:1626.11-1626.50" + attribute \src "ls180.v:1631.11-1631.50" wire width 5 $1\main_sdblock2mem_fifo_wrport_adr[4:0] - attribute \src "ls180.v:1660.12-1660.62" + attribute \src "ls180.v:1665.12-1665.62" wire width 32 $1\main_sdblock2mem_sink_sink_payload_address[31:0] - attribute \src "ls180.v:1661.12-1661.60" - wire width 32 $1\main_sdblock2mem_sink_sink_payload_data1[31:0] - attribute \src "ls180.v:1658.5-1658.45" + attribute \src "ls180.v:1666.12-1666.60" + wire width 64 $1\main_sdblock2mem_sink_sink_payload_data1[63:0] + attribute \src "ls180.v:1663.5-1663.45" wire $1\main_sdblock2mem_sink_sink_valid1[0:0] - attribute \src "ls180.v:1668.5-1668.54" + attribute \src "ls180.v:1673.5-1673.54" wire $1\main_sdblock2mem_wishbonedmawriter_base_re[0:0] - attribute \src "ls180.v:1667.12-1667.67" + attribute \src "ls180.v:1672.12-1672.67" wire width 64 $1\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] - attribute \src "ls180.v:1672.5-1672.56" + attribute \src "ls180.v:1677.5-1677.56" wire $1\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] - attribute \src "ls180.v:1671.5-1671.61" + attribute \src "ls180.v:1676.5-1676.61" wire $1\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] - attribute \src "ls180.v:1670.5-1670.56" + attribute \src "ls180.v:1675.5-1675.56" wire $1\main_sdblock2mem_wishbonedmawriter_length_re[0:0] - attribute \src "ls180.v:1669.12-1669.69" + attribute \src "ls180.v:1674.12-1674.69" wire width 32 $1\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] - attribute \src "ls180.v:1676.5-1676.54" + attribute \src "ls180.v:1681.5-1681.54" wire $1\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] - attribute \src "ls180.v:1675.5-1675.59" + attribute \src "ls180.v:1680.5-1680.59" wire $1\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] - attribute \src "ls180.v:1678.12-1678.61" + attribute \src "ls180.v:1683.12-1683.61" wire width 32 $1\main_sdblock2mem_wishbonedmawriter_offset[31:0] - attribute \src "ls180.v:1898.12-1898.87" + attribute \src "ls180.v:1903.12-1903.87" wire width 32 $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] - attribute \src "ls180.v:1899.5-1899.82" + attribute \src "ls180.v:1904.5-1904.82" wire $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] - attribute \src "ls180.v:1663.5-1663.57" + attribute \src "ls180.v:1668.5-1668.57" wire $1\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] - attribute \src "ls180.v:1673.5-1673.53" + attribute \src "ls180.v:1678.5-1678.53" wire $1\main_sdblock2mem_wishbonedmawriter_status[0:0] - attribute \src "ls180.v:1442.5-1442.38" + attribute \src "ls180.v:1447.5-1447.38" wire $1\main_sdcore_block_count_re[0:0] - attribute \src "ls180.v:1441.12-1441.51" + attribute \src "ls180.v:1446.12-1446.51" wire width 32 $1\main_sdcore_block_count_storage[31:0] - attribute \src "ls180.v:1440.5-1440.39" + attribute \src "ls180.v:1445.5-1445.39" wire $1\main_sdcore_block_length_re[0:0] - attribute \src "ls180.v:1439.11-1439.51" + attribute \src "ls180.v:1444.11-1444.51" wire width 10 $1\main_sdcore_block_length_storage[9:0] - attribute \src "ls180.v:1426.5-1426.39" + attribute \src "ls180.v:1431.5-1431.39" wire $1\main_sdcore_cmd_argument_re[0:0] - attribute \src "ls180.v:1425.12-1425.52" + attribute \src "ls180.v:1430.12-1430.52" wire width 32 $1\main_sdcore_cmd_argument_storage[31:0] - attribute \src "ls180.v:1428.5-1428.38" + attribute \src "ls180.v:1433.5-1433.38" wire $1\main_sdcore_cmd_command_re[0:0] - attribute \src "ls180.v:1427.12-1427.51" + attribute \src "ls180.v:1432.12-1432.51" wire width 32 $1\main_sdcore_cmd_command_storage[31:0] - attribute \src "ls180.v:1581.11-1581.39" + attribute \src "ls180.v:1586.11-1586.39" wire width 3 $1\main_sdcore_cmd_count[2:0] - attribute \src "ls180.v:1882.11-1882.62" + attribute \src "ls180.v:1887.11-1887.62" wire width 3 $1\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] - attribute \src "ls180.v:1883.5-1883.59" + attribute \src "ls180.v:1888.5-1888.59" wire $1\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] - attribute \src "ls180.v:1582.5-1582.32" + attribute \src "ls180.v:1587.5-1587.32" wire $1\main_sdcore_cmd_done[0:0] - attribute \src "ls180.v:1878.5-1878.55" + attribute \src "ls180.v:1883.5-1883.55" wire $1\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] - attribute \src "ls180.v:1879.5-1879.58" + attribute \src "ls180.v:1884.5-1884.58" wire $1\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] - attribute \src "ls180.v:1583.5-1583.33" + attribute \src "ls180.v:1588.5-1588.33" wire $1\main_sdcore_cmd_error[0:0] - attribute \src "ls180.v:1886.5-1886.56" + attribute \src "ls180.v:1891.5-1891.56" wire $1\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] - attribute \src "ls180.v:1887.5-1887.59" + attribute \src "ls180.v:1892.5-1892.59" wire $1\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] - attribute \src "ls180.v:1433.13-1433.53" + attribute \src "ls180.v:1438.13-1438.53" wire width 128 $1\main_sdcore_cmd_response_status[127:0] - attribute \src "ls180.v:1894.13-1894.76" + attribute \src "ls180.v:1899.13-1899.76" wire width 128 $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] - attribute \src "ls180.v:1895.5-1895.69" + attribute \src "ls180.v:1900.5-1900.69" wire $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] - attribute \src "ls180.v:1584.5-1584.35" + attribute \src "ls180.v:1589.5-1589.35" wire $1\main_sdcore_cmd_timeout[0:0] - attribute \src "ls180.v:1888.5-1888.58" + attribute \src "ls180.v:1893.5-1893.58" wire $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] - attribute \src "ls180.v:1889.5-1889.61" + attribute \src "ls180.v:1894.5-1894.61" wire $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] - attribute \src "ls180.v:1542.11-1542.47" + attribute \src "ls180.v:1547.11-1547.47" wire width 4 $1\main_sdcore_crc16_checker_cnt[3:0] - attribute \src "ls180.v:1548.5-1548.46" + attribute \src "ls180.v:1553.5-1553.46" wire $1\main_sdcore_crc16_checker_crc0_clr[0:0] - attribute \src "ls180.v:1547.12-1547.54" + attribute \src "ls180.v:1552.12-1552.54" wire width 16 $1\main_sdcore_crc16_checker_crc0_crc[15:0] - attribute \src "ls180.v:1543.12-1543.58" + attribute \src "ls180.v:1548.12-1548.58" wire width 16 $1\main_sdcore_crc16_checker_crc0_crcreg0[15:0] - attribute \src "ls180.v:1555.5-1555.46" + attribute \src "ls180.v:1560.5-1560.46" wire $1\main_sdcore_crc16_checker_crc1_clr[0:0] - attribute \src "ls180.v:1554.12-1554.54" + attribute \src "ls180.v:1559.12-1559.54" wire width 16 $1\main_sdcore_crc16_checker_crc1_crc[15:0] - attribute \src "ls180.v:1550.12-1550.58" + attribute \src "ls180.v:1555.12-1555.58" wire width 16 $1\main_sdcore_crc16_checker_crc1_crcreg0[15:0] - attribute \src "ls180.v:1562.5-1562.46" + attribute \src "ls180.v:1567.5-1567.46" wire $1\main_sdcore_crc16_checker_crc2_clr[0:0] - attribute \src "ls180.v:1561.12-1561.54" + attribute \src "ls180.v:1566.12-1566.54" wire width 16 $1\main_sdcore_crc16_checker_crc2_crc[15:0] - attribute \src "ls180.v:1557.12-1557.58" + attribute \src "ls180.v:1562.12-1562.58" wire width 16 $1\main_sdcore_crc16_checker_crc2_crcreg0[15:0] - attribute \src "ls180.v:1569.5-1569.46" + attribute \src "ls180.v:1574.5-1574.46" wire $1\main_sdcore_crc16_checker_crc3_clr[0:0] - attribute \src "ls180.v:1568.12-1568.54" + attribute \src "ls180.v:1573.12-1573.54" wire width 16 $1\main_sdcore_crc16_checker_crc3_crc[15:0] - attribute \src "ls180.v:1564.12-1564.58" + attribute \src "ls180.v:1569.12-1569.58" wire width 16 $1\main_sdcore_crc16_checker_crc3_crcreg0[15:0] - attribute \src "ls180.v:1571.12-1571.53" + attribute \src "ls180.v:1576.12-1576.53" wire width 16 $1\main_sdcore_crc16_checker_crctmp0[15:0] - attribute \src "ls180.v:1572.12-1572.53" + attribute \src "ls180.v:1577.12-1577.53" wire width 16 $1\main_sdcore_crc16_checker_crctmp1[15:0] - attribute \src "ls180.v:1573.12-1573.53" + attribute \src "ls180.v:1578.12-1578.53" wire width 16 $1\main_sdcore_crc16_checker_crctmp2[15:0] - attribute \src "ls180.v:1574.12-1574.53" + attribute \src "ls180.v:1579.12-1579.53" wire width 16 $1\main_sdcore_crc16_checker_crctmp3[15:0] - attribute \src "ls180.v:1576.12-1576.51" + attribute \src "ls180.v:1581.12-1581.51" wire width 16 $1\main_sdcore_crc16_checker_fifo0[15:0] - attribute \src "ls180.v:1577.12-1577.51" + attribute \src "ls180.v:1582.12-1582.51" wire width 16 $1\main_sdcore_crc16_checker_fifo1[15:0] - attribute \src "ls180.v:1578.12-1578.51" + attribute \src "ls180.v:1583.12-1583.51" wire width 16 $1\main_sdcore_crc16_checker_fifo2[15:0] - attribute \src "ls180.v:1579.12-1579.51" + attribute \src "ls180.v:1584.12-1584.51" wire width 16 $1\main_sdcore_crc16_checker_fifo3[15:0] - attribute \src "ls180.v:1533.5-1533.48" + attribute \src "ls180.v:1538.5-1538.48" wire $1\main_sdcore_crc16_checker_sink_first[0:0] - attribute \src "ls180.v:1534.5-1534.47" + attribute \src "ls180.v:1539.5-1539.47" wire $1\main_sdcore_crc16_checker_sink_last[0:0] - attribute \src "ls180.v:1535.11-1535.61" + attribute \src "ls180.v:1540.11-1540.61" wire width 8 $1\main_sdcore_crc16_checker_sink_payload_data[7:0] - attribute \src "ls180.v:1532.5-1532.48" + attribute \src "ls180.v:1537.5-1537.48" wire $1\main_sdcore_crc16_checker_sink_ready[0:0] - attribute \src "ls180.v:1531.5-1531.48" + attribute \src "ls180.v:1536.5-1536.48" wire $1\main_sdcore_crc16_checker_sink_valid[0:0] - attribute \src "ls180.v:1536.5-1536.50" + attribute \src "ls180.v:1541.5-1541.50" wire $1\main_sdcore_crc16_checker_source_valid[0:0] - attribute \src "ls180.v:1541.11-1541.47" + attribute \src "ls180.v:1546.11-1546.47" wire width 8 $1\main_sdcore_crc16_checker_val[7:0] - attribute \src "ls180.v:1575.5-1575.43" + attribute \src "ls180.v:1580.5-1580.43" wire $1\main_sdcore_crc16_checker_valid[0:0] - attribute \src "ls180.v:1498.11-1498.48" + attribute \src "ls180.v:1503.11-1503.48" wire width 3 $1\main_sdcore_crc16_inserter_cnt[2:0] - attribute \src "ls180.v:1874.11-1874.87" + attribute \src "ls180.v:1879.11-1879.87" wire width 3 $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] - attribute \src "ls180.v:1875.5-1875.84" + attribute \src "ls180.v:1880.5-1880.84" wire $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] - attribute \src "ls180.v:1503.12-1503.55" + attribute \src "ls180.v:1508.12-1508.55" wire width 16 $1\main_sdcore_crc16_inserter_crc0_crc[15:0] - attribute \src "ls180.v:1499.12-1499.59" + attribute \src "ls180.v:1504.12-1504.59" wire width 16 $1\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] - attribute \src "ls180.v:1510.12-1510.55" + attribute \src "ls180.v:1515.12-1515.55" wire width 16 $1\main_sdcore_crc16_inserter_crc1_crc[15:0] - attribute \src "ls180.v:1506.12-1506.59" + attribute \src "ls180.v:1511.12-1511.59" wire width 16 $1\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] - attribute \src "ls180.v:1517.12-1517.55" + attribute \src "ls180.v:1522.12-1522.55" wire width 16 $1\main_sdcore_crc16_inserter_crc2_crc[15:0] - attribute \src "ls180.v:1513.12-1513.59" + attribute \src "ls180.v:1518.12-1518.59" wire width 16 $1\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] - attribute \src "ls180.v:1524.12-1524.55" + attribute \src "ls180.v:1529.12-1529.55" wire width 16 $1\main_sdcore_crc16_inserter_crc3_crc[15:0] - attribute \src "ls180.v:1520.12-1520.59" + attribute \src "ls180.v:1525.12-1525.59" wire width 16 $1\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] - attribute \src "ls180.v:1527.12-1527.54" + attribute \src "ls180.v:1532.12-1532.54" wire width 16 $1\main_sdcore_crc16_inserter_crctmp0[15:0] - attribute \src "ls180.v:1866.12-1866.93" + attribute \src "ls180.v:1871.12-1871.93" wire width 16 $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] - attribute \src "ls180.v:1867.5-1867.88" + attribute \src "ls180.v:1872.5-1872.88" wire $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] - attribute \src "ls180.v:1528.12-1528.54" + attribute \src "ls180.v:1533.12-1533.54" wire width 16 $1\main_sdcore_crc16_inserter_crctmp1[15:0] - attribute \src "ls180.v:1868.12-1868.93" + attribute \src "ls180.v:1873.12-1873.93" wire width 16 $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] - attribute \src "ls180.v:1869.5-1869.88" + attribute \src "ls180.v:1874.5-1874.88" wire $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] - attribute \src "ls180.v:1529.12-1529.54" + attribute \src "ls180.v:1534.12-1534.54" wire width 16 $1\main_sdcore_crc16_inserter_crctmp2[15:0] - attribute \src "ls180.v:1870.12-1870.93" + attribute \src "ls180.v:1875.12-1875.93" wire width 16 $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] - attribute \src "ls180.v:1871.5-1871.88" + attribute \src "ls180.v:1876.5-1876.88" wire $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] - attribute \src "ls180.v:1530.12-1530.54" + attribute \src "ls180.v:1535.12-1535.54" wire width 16 $1\main_sdcore_crc16_inserter_crctmp3[15:0] - attribute \src "ls180.v:1872.12-1872.93" + attribute \src "ls180.v:1877.12-1877.93" wire width 16 $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] - attribute \src "ls180.v:1873.5-1873.88" + attribute \src "ls180.v:1878.5-1878.88" wire $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] - attribute \src "ls180.v:1489.5-1489.49" + attribute \src "ls180.v:1494.5-1494.49" wire $1\main_sdcore_crc16_inserter_sink_ready[0:0] - attribute \src "ls180.v:1496.5-1496.50" + attribute \src "ls180.v:1501.5-1501.50" wire $1\main_sdcore_crc16_inserter_source_last[0:0] - attribute \src "ls180.v:1497.11-1497.64" + attribute \src "ls180.v:1502.11-1502.64" wire width 8 $1\main_sdcore_crc16_inserter_source_payload_data[7:0] - attribute \src "ls180.v:1494.5-1494.51" + attribute \src "ls180.v:1499.5-1499.51" wire $1\main_sdcore_crc16_inserter_source_ready[0:0] - attribute \src "ls180.v:1493.5-1493.51" + attribute \src "ls180.v:1498.5-1498.51" wire $1\main_sdcore_crc16_inserter_source_valid[0:0] - attribute \src "ls180.v:1485.11-1485.47" + attribute \src "ls180.v:1490.11-1490.47" wire width 7 $1\main_sdcore_crc7_inserter_crc[6:0] - attribute \src "ls180.v:1443.11-1443.51" + attribute \src "ls180.v:1448.11-1448.51" wire width 7 $1\main_sdcore_crc7_inserter_crcreg0[6:0] - attribute \src "ls180.v:1586.12-1586.42" + attribute \src "ls180.v:1591.12-1591.42" wire width 32 $1\main_sdcore_data_count[31:0] - attribute \src "ls180.v:1884.12-1884.65" + attribute \src "ls180.v:1889.12-1889.65" wire width 32 $1\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] - attribute \src "ls180.v:1885.5-1885.60" + attribute \src "ls180.v:1890.5-1890.60" wire $1\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] - attribute \src "ls180.v:1587.5-1587.33" + attribute \src "ls180.v:1592.5-1592.33" wire $1\main_sdcore_data_done[0:0] - attribute \src "ls180.v:1880.5-1880.56" + attribute \src "ls180.v:1885.5-1885.56" wire $1\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] - attribute \src "ls180.v:1881.5-1881.59" + attribute \src "ls180.v:1886.5-1886.59" wire $1\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] - attribute \src "ls180.v:1588.5-1588.34" + attribute \src "ls180.v:1593.5-1593.34" wire $1\main_sdcore_data_error[0:0] - attribute \src "ls180.v:1890.5-1890.57" + attribute \src "ls180.v:1895.5-1895.57" wire $1\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] - attribute \src "ls180.v:1891.5-1891.60" + attribute \src "ls180.v:1896.5-1896.60" wire $1\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] - attribute \src "ls180.v:1589.5-1589.36" + attribute \src "ls180.v:1594.5-1594.36" wire $1\main_sdcore_data_timeout[0:0] - attribute \src "ls180.v:1892.5-1892.59" + attribute \src "ls180.v:1897.5-1897.59" wire $1\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] - attribute \src "ls180.v:1893.5-1893.62" + attribute \src "ls180.v:1898.5-1898.62" wire $1\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] - attribute \src "ls180.v:1734.11-1734.48" - wire width 2 $1\main_sdmem2block_converter_mux[1:0] - attribute \src "ls180.v:1732.11-1732.64" + attribute \src "ls180.v:1739.11-1739.48" + wire width 3 $1\main_sdmem2block_converter_mux[2:0] + attribute \src "ls180.v:1737.11-1737.64" wire width 8 $1\main_sdmem2block_converter_source_payload_data[7:0] - attribute \src "ls180.v:1708.5-1708.40" + attribute \src "ls180.v:1713.5-1713.40" wire $1\main_sdmem2block_dma_base_re[0:0] - attribute \src "ls180.v:1707.12-1707.53" + attribute \src "ls180.v:1712.12-1712.53" wire width 64 $1\main_sdmem2block_dma_base_storage[63:0] - attribute \src "ls180.v:1706.12-1706.45" - wire width 32 $1\main_sdmem2block_dma_data[31:0] - attribute \src "ls180.v:1902.12-1902.75" - wire width 32 $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] - attribute \src "ls180.v:1903.5-1903.70" + attribute \src "ls180.v:1711.12-1711.45" + wire width 64 $1\main_sdmem2block_dma_data[63:0] + attribute \src "ls180.v:1907.12-1907.75" + wire width 64 $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[63:0] + attribute \src "ls180.v:1908.5-1908.70" wire $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] - attribute \src "ls180.v:1713.5-1713.44" + attribute \src "ls180.v:1718.5-1718.44" wire $1\main_sdmem2block_dma_done_status[0:0] - attribute \src "ls180.v:1712.5-1712.42" + attribute \src "ls180.v:1717.5-1717.42" wire $1\main_sdmem2block_dma_enable_re[0:0] - attribute \src "ls180.v:1711.5-1711.47" + attribute \src "ls180.v:1716.5-1716.47" wire $1\main_sdmem2block_dma_enable_storage[0:0] - attribute \src "ls180.v:1710.5-1710.42" + attribute \src "ls180.v:1715.5-1715.42" wire $1\main_sdmem2block_dma_length_re[0:0] - attribute \src "ls180.v:1709.12-1709.55" + attribute \src "ls180.v:1714.12-1714.55" wire width 32 $1\main_sdmem2block_dma_length_storage[31:0] - attribute \src "ls180.v:1716.5-1716.40" + attribute \src "ls180.v:1721.5-1721.40" wire $1\main_sdmem2block_dma_loop_re[0:0] - attribute \src "ls180.v:1715.5-1715.45" + attribute \src "ls180.v:1720.5-1720.45" wire $1\main_sdmem2block_dma_loop_storage[0:0] - attribute \src "ls180.v:1720.12-1720.47" + attribute \src "ls180.v:1725.12-1725.47" wire width 32 $1\main_sdmem2block_dma_offset[31:0] - attribute \src "ls180.v:1906.12-1906.87" + attribute \src "ls180.v:1911.12-1911.87" wire width 32 $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] - attribute \src "ls180.v:1907.5-1907.82" + attribute \src "ls180.v:1912.5-1912.82" wire $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] - attribute \src "ls180.v:1699.5-1699.42" + attribute \src "ls180.v:1704.5-1704.42" wire $1\main_sdmem2block_dma_sink_last[0:0] - attribute \src "ls180.v:1700.12-1700.61" + attribute \src "ls180.v:1705.12-1705.61" wire width 32 $1\main_sdmem2block_dma_sink_payload_address[31:0] - attribute \src "ls180.v:1698.5-1698.43" + attribute \src "ls180.v:1703.5-1703.43" wire $1\main_sdmem2block_dma_sink_ready[0:0] - attribute \src "ls180.v:1697.5-1697.43" + attribute \src "ls180.v:1702.5-1702.43" wire $1\main_sdmem2block_dma_sink_valid[0:0] - attribute \src "ls180.v:1704.5-1704.44" + attribute \src "ls180.v:1709.5-1709.44" wire $1\main_sdmem2block_dma_source_last[0:0] - attribute \src "ls180.v:1705.12-1705.60" - wire width 32 $1\main_sdmem2block_dma_source_payload_data[31:0] - attribute \src "ls180.v:1701.5-1701.45" + attribute \src "ls180.v:1710.12-1710.60" + wire width 64 $1\main_sdmem2block_dma_source_payload_data[63:0] + attribute \src "ls180.v:1706.5-1706.45" wire $1\main_sdmem2block_dma_source_valid[0:0] - attribute \src "ls180.v:1761.11-1761.47" + attribute \src "ls180.v:1766.11-1766.47" wire width 5 $1\main_sdmem2block_fifo_consume[4:0] - attribute \src "ls180.v:1758.11-1758.45" + attribute \src "ls180.v:1763.11-1763.45" wire width 6 $1\main_sdmem2block_fifo_level[5:0] - attribute \src "ls180.v:1760.11-1760.47" + attribute \src "ls180.v:1765.11-1765.47" wire width 5 $1\main_sdmem2block_fifo_produce[4:0] - attribute \src "ls180.v:1762.11-1762.50" + attribute \src "ls180.v:1767.11-1767.50" wire width 5 $1\main_sdmem2block_fifo_wrport_adr[4:0] - attribute \src "ls180.v:1142.5-1142.35" + attribute \src "ls180.v:1147.5-1147.35" wire $1\main_sdphy_clocker_clk0[0:0] - attribute \src "ls180.v:1145.5-1145.35" + attribute \src "ls180.v:1150.5-1150.35" wire $1\main_sdphy_clocker_clk1[0:0] - attribute \src "ls180.v:1146.5-1146.36" + attribute \src "ls180.v:1151.5-1151.36" wire $1\main_sdphy_clocker_clk_d[0:0] - attribute \src "ls180.v:1144.11-1144.41" + attribute \src "ls180.v:1149.11-1149.41" wire width 9 $1\main_sdphy_clocker_clks[8:0] - attribute \src "ls180.v:1140.5-1140.33" + attribute \src "ls180.v:1145.5-1145.33" wire $1\main_sdphy_clocker_re[0:0] - attribute \src "ls180.v:1139.11-1139.46" + attribute \src "ls180.v:1144.11-1144.46" wire width 9 $1\main_sdphy_clocker_storage[8:0] - attribute \src "ls180.v:1248.5-1248.49" + attribute \src "ls180.v:1253.5-1253.49" wire $1\main_sdphy_cmdr_cmdr_buf_source_first[0:0] - attribute \src "ls180.v:1249.5-1249.48" + attribute \src "ls180.v:1254.5-1254.48" wire $1\main_sdphy_cmdr_cmdr_buf_source_last[0:0] - attribute \src "ls180.v:1250.11-1250.62" + attribute \src "ls180.v:1255.11-1255.62" wire width 8 $1\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] - attribute \src "ls180.v:1246.5-1246.49" + attribute \src "ls180.v:1251.5-1251.49" wire $1\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] - attribute \src "ls180.v:1233.11-1233.54" + attribute \src "ls180.v:1238.11-1238.54" wire width 3 $1\main_sdphy_cmdr_cmdr_converter_demux[2:0] - attribute \src "ls180.v:1229.5-1229.55" + attribute \src "ls180.v:1234.5-1234.55" wire $1\main_sdphy_cmdr_cmdr_converter_source_first[0:0] - attribute \src "ls180.v:1230.5-1230.54" + attribute \src "ls180.v:1235.5-1235.54" wire $1\main_sdphy_cmdr_cmdr_converter_source_last[0:0] - attribute \src "ls180.v:1231.11-1231.68" + attribute \src "ls180.v:1236.11-1236.68" wire width 8 $1\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] - attribute \src "ls180.v:1232.11-1232.81" + attribute \src "ls180.v:1237.11-1237.81" wire width 4 $1\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] - attribute \src "ls180.v:1235.5-1235.53" + attribute \src "ls180.v:1240.5-1240.53" wire $1\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] - attribute \src "ls180.v:1251.5-1251.38" + attribute \src "ls180.v:1256.5-1256.38" wire $1\main_sdphy_cmdr_cmdr_reset[0:0] - attribute \src "ls180.v:1846.5-1846.66" + attribute \src "ls180.v:1851.5-1851.66" wire $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] - attribute \src "ls180.v:1847.5-1847.69" + attribute \src "ls180.v:1852.5-1852.69" wire $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] - attribute \src "ls180.v:1221.5-1221.36" + attribute \src "ls180.v:1226.5-1226.36" wire $1\main_sdphy_cmdr_cmdr_run[0:0] - attribute \src "ls180.v:1216.5-1216.53" + attribute \src "ls180.v:1221.5-1221.53" wire $1\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] - attribute \src "ls180.v:1203.11-1203.39" + attribute \src "ls180.v:1208.11-1208.39" wire width 8 $1\main_sdphy_cmdr_count[7:0] - attribute \src "ls180.v:1842.11-1842.67" + attribute \src "ls180.v:1847.11-1847.67" wire width 8 $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] - attribute \src "ls180.v:1843.5-1843.64" + attribute \src "ls180.v:1848.5-1848.64" wire $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] - attribute \src "ls180.v:1188.5-1188.48" + attribute \src "ls180.v:1193.5-1193.48" wire $1\main_sdphy_cmdr_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1189.5-1189.50" + attribute \src "ls180.v:1194.5-1194.50" wire $1\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:1190.5-1190.51" + attribute \src "ls180.v:1195.5-1195.51" wire $1\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:1195.5-1195.37" + attribute \src "ls180.v:1200.5-1200.37" wire $1\main_sdphy_cmdr_sink_last[0:0] - attribute \src "ls180.v:1196.11-1196.53" + attribute \src "ls180.v:1201.11-1201.53" wire width 8 $1\main_sdphy_cmdr_sink_payload_length[7:0] - attribute \src "ls180.v:1194.5-1194.38" + attribute \src "ls180.v:1199.5-1199.38" wire $1\main_sdphy_cmdr_sink_ready[0:0] - attribute \src "ls180.v:1193.5-1193.38" + attribute \src "ls180.v:1198.5-1198.38" wire $1\main_sdphy_cmdr_sink_valid[0:0] - attribute \src "ls180.v:1199.5-1199.39" + attribute \src "ls180.v:1204.5-1204.39" wire $1\main_sdphy_cmdr_source_last[0:0] - attribute \src "ls180.v:1200.11-1200.53" + attribute \src "ls180.v:1205.11-1205.53" wire width 8 $1\main_sdphy_cmdr_source_payload_data[7:0] - attribute \src "ls180.v:1201.11-1201.55" + attribute \src "ls180.v:1206.11-1206.55" wire width 3 $1\main_sdphy_cmdr_source_payload_status[2:0] - attribute \src "ls180.v:1198.5-1198.40" + attribute \src "ls180.v:1203.5-1203.40" wire $1\main_sdphy_cmdr_source_ready[0:0] - attribute \src "ls180.v:1197.5-1197.40" + attribute \src "ls180.v:1202.5-1202.40" wire $1\main_sdphy_cmdr_source_valid[0:0] - attribute \src "ls180.v:1202.12-1202.48" + attribute \src "ls180.v:1207.12-1207.48" wire width 32 $1\main_sdphy_cmdr_timeout[31:0] - attribute \src "ls180.v:1844.12-1844.71" + attribute \src "ls180.v:1849.12-1849.71" wire width 32 $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] - attribute \src "ls180.v:1845.5-1845.66" + attribute \src "ls180.v:1850.5-1850.66" wire $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] - attribute \src "ls180.v:1175.11-1175.39" + attribute \src "ls180.v:1180.11-1180.39" wire width 8 $1\main_sdphy_cmdw_count[7:0] - attribute \src "ls180.v:1838.11-1838.66" + attribute \src "ls180.v:1843.11-1843.66" wire width 8 $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] - attribute \src "ls180.v:1839.5-1839.63" + attribute \src "ls180.v:1844.5-1844.63" wire $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] - attribute \src "ls180.v:1174.5-1174.32" + attribute \src "ls180.v:1179.5-1179.32" wire $1\main_sdphy_cmdw_done[0:0] - attribute \src "ls180.v:1165.5-1165.48" + attribute \src "ls180.v:1170.5-1170.48" wire $1\main_sdphy_cmdw_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1166.5-1166.50" + attribute \src "ls180.v:1171.5-1171.50" wire $1\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:1167.5-1167.51" + attribute \src "ls180.v:1172.5-1172.51" wire $1\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:1172.5-1172.37" + attribute \src "ls180.v:1177.5-1177.37" wire $1\main_sdphy_cmdw_sink_last[0:0] - attribute \src "ls180.v:1173.11-1173.51" + attribute \src "ls180.v:1178.11-1178.51" wire width 8 $1\main_sdphy_cmdw_sink_payload_data[7:0] - attribute \src "ls180.v:1171.5-1171.38" + attribute \src "ls180.v:1176.5-1176.38" wire $1\main_sdphy_cmdw_sink_ready[0:0] - attribute \src "ls180.v:1170.5-1170.38" + attribute \src "ls180.v:1175.5-1175.38" wire $1\main_sdphy_cmdw_sink_valid[0:0] - attribute \src "ls180.v:1359.11-1359.41" + attribute \src "ls180.v:1364.11-1364.41" wire width 10 $1\main_sdphy_datar_count[9:0] - attribute \src "ls180.v:1858.11-1858.70" + attribute \src "ls180.v:1863.11-1863.70" wire width 10 $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] - attribute \src "ls180.v:1859.5-1859.66" + attribute \src "ls180.v:1864.5-1864.66" wire $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] - attribute \src "ls180.v:1404.5-1404.51" + attribute \src "ls180.v:1409.5-1409.51" wire $1\main_sdphy_datar_datar_buf_source_first[0:0] - attribute \src "ls180.v:1405.5-1405.50" + attribute \src "ls180.v:1410.5-1410.50" wire $1\main_sdphy_datar_datar_buf_source_last[0:0] - attribute \src "ls180.v:1406.11-1406.64" + attribute \src "ls180.v:1411.11-1411.64" wire width 8 $1\main_sdphy_datar_datar_buf_source_payload_data[7:0] - attribute \src "ls180.v:1402.5-1402.51" + attribute \src "ls180.v:1407.5-1407.51" wire $1\main_sdphy_datar_datar_buf_source_valid[0:0] - attribute \src "ls180.v:1389.5-1389.50" + attribute \src "ls180.v:1394.5-1394.50" wire $1\main_sdphy_datar_datar_converter_demux[0:0] - attribute \src "ls180.v:1385.5-1385.57" + attribute \src "ls180.v:1390.5-1390.57" wire $1\main_sdphy_datar_datar_converter_source_first[0:0] - attribute \src "ls180.v:1386.5-1386.56" + attribute \src "ls180.v:1391.5-1391.56" wire $1\main_sdphy_datar_datar_converter_source_last[0:0] - attribute \src "ls180.v:1387.11-1387.70" + attribute \src "ls180.v:1392.11-1392.70" wire width 8 $1\main_sdphy_datar_datar_converter_source_payload_data[7:0] - attribute \src "ls180.v:1388.11-1388.83" + attribute \src "ls180.v:1393.11-1393.83" wire width 2 $1\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] - attribute \src "ls180.v:1391.5-1391.55" + attribute \src "ls180.v:1396.5-1396.55" wire $1\main_sdphy_datar_datar_converter_strobe_all[0:0] - attribute \src "ls180.v:1407.5-1407.40" + attribute \src "ls180.v:1412.5-1412.40" wire $1\main_sdphy_datar_datar_reset[0:0] - attribute \src "ls180.v:1862.5-1862.69" + attribute \src "ls180.v:1867.5-1867.69" wire $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] - attribute \src "ls180.v:1863.5-1863.72" + attribute \src "ls180.v:1868.5-1868.72" wire $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] - attribute \src "ls180.v:1377.5-1377.38" + attribute \src "ls180.v:1382.5-1382.38" wire $1\main_sdphy_datar_datar_run[0:0] - attribute \src "ls180.v:1372.5-1372.55" + attribute \src "ls180.v:1377.5-1377.55" wire $1\main_sdphy_datar_datar_source_source_ready0[0:0] - attribute \src "ls180.v:1342.5-1342.49" + attribute \src "ls180.v:1347.5-1347.49" wire $1\main_sdphy_datar_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1349.5-1349.38" + attribute \src "ls180.v:1354.5-1354.38" wire $1\main_sdphy_datar_sink_last[0:0] - attribute \src "ls180.v:1350.11-1350.61" + attribute \src "ls180.v:1355.11-1355.61" wire width 10 $1\main_sdphy_datar_sink_payload_block_length[9:0] - attribute \src "ls180.v:1348.5-1348.39" + attribute \src "ls180.v:1353.5-1353.39" wire $1\main_sdphy_datar_sink_ready[0:0] - attribute \src "ls180.v:1347.5-1347.39" + attribute \src "ls180.v:1352.5-1352.39" wire $1\main_sdphy_datar_sink_valid[0:0] - attribute \src "ls180.v:1354.5-1354.40" + attribute \src "ls180.v:1359.5-1359.40" wire $1\main_sdphy_datar_source_last[0:0] - attribute \src "ls180.v:1355.11-1355.54" + attribute \src "ls180.v:1360.11-1360.54" wire width 8 $1\main_sdphy_datar_source_payload_data[7:0] - attribute \src "ls180.v:1356.11-1356.56" + attribute \src "ls180.v:1361.11-1361.56" wire width 3 $1\main_sdphy_datar_source_payload_status[2:0] - attribute \src "ls180.v:1352.5-1352.41" + attribute \src "ls180.v:1357.5-1357.41" wire $1\main_sdphy_datar_source_ready[0:0] - attribute \src "ls180.v:1351.5-1351.41" + attribute \src "ls180.v:1356.5-1356.41" wire $1\main_sdphy_datar_source_valid[0:0] - attribute \src "ls180.v:1357.5-1357.33" + attribute \src "ls180.v:1362.5-1362.33" wire $1\main_sdphy_datar_stop[0:0] - attribute \src "ls180.v:1358.12-1358.49" + attribute \src "ls180.v:1363.12-1363.49" wire width 32 $1\main_sdphy_datar_timeout[31:0] - attribute \src "ls180.v:1860.12-1860.73" + attribute \src "ls180.v:1865.12-1865.73" wire width 32 $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] - attribute \src "ls180.v:1861.5-1861.68" + attribute \src "ls180.v:1866.5-1866.68" wire $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] - attribute \src "ls180.v:1267.11-1267.40" + attribute \src "ls180.v:1272.11-1272.40" wire width 8 $1\main_sdphy_dataw_count[7:0] - attribute \src "ls180.v:1854.11-1854.61" + attribute \src "ls180.v:1859.11-1859.61" wire width 8 $1\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] - attribute \src "ls180.v:1855.5-1855.58" + attribute \src "ls180.v:1860.5-1860.58" wire $1\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] - attribute \src "ls180.v:1326.5-1326.50" + attribute \src "ls180.v:1331.5-1331.50" wire $1\main_sdphy_dataw_crcr_buf_source_first[0:0] - attribute \src "ls180.v:1327.5-1327.49" + attribute \src "ls180.v:1332.5-1332.49" wire $1\main_sdphy_dataw_crcr_buf_source_last[0:0] - attribute \src "ls180.v:1328.11-1328.63" + attribute \src "ls180.v:1333.11-1333.63" wire width 8 $1\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] - attribute \src "ls180.v:1324.5-1324.50" + attribute \src "ls180.v:1329.5-1329.50" wire $1\main_sdphy_dataw_crcr_buf_source_valid[0:0] - attribute \src "ls180.v:1311.11-1311.55" + attribute \src "ls180.v:1316.11-1316.55" wire width 3 $1\main_sdphy_dataw_crcr_converter_demux[2:0] - attribute \src "ls180.v:1307.5-1307.56" + attribute \src "ls180.v:1312.5-1312.56" wire $1\main_sdphy_dataw_crcr_converter_source_first[0:0] - attribute \src "ls180.v:1308.5-1308.55" + attribute \src "ls180.v:1313.5-1313.55" wire $1\main_sdphy_dataw_crcr_converter_source_last[0:0] - attribute \src "ls180.v:1309.11-1309.69" + attribute \src "ls180.v:1314.11-1314.69" wire width 8 $1\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] - attribute \src "ls180.v:1310.11-1310.82" + attribute \src "ls180.v:1315.11-1315.82" wire width 4 $1\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] - attribute \src "ls180.v:1313.5-1313.54" + attribute \src "ls180.v:1318.5-1318.54" wire $1\main_sdphy_dataw_crcr_converter_strobe_all[0:0] - attribute \src "ls180.v:1329.5-1329.39" + attribute \src "ls180.v:1334.5-1334.39" wire $1\main_sdphy_dataw_crcr_reset[0:0] - attribute \src "ls180.v:1850.5-1850.66" + attribute \src "ls180.v:1855.5-1855.66" wire $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] - attribute \src "ls180.v:1851.5-1851.69" + attribute \src "ls180.v:1856.5-1856.69" wire $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] - attribute \src "ls180.v:1299.5-1299.37" + attribute \src "ls180.v:1304.5-1304.37" wire $1\main_sdphy_dataw_crcr_run[0:0] - attribute \src "ls180.v:1294.5-1294.54" + attribute \src "ls180.v:1299.5-1299.54" wire $1\main_sdphy_dataw_crcr_source_source_ready0[0:0] - attribute \src "ls180.v:1281.5-1281.34" + attribute \src "ls180.v:1286.5-1286.34" wire $1\main_sdphy_dataw_error[0:0] - attribute \src "ls180.v:1256.5-1256.49" + attribute \src "ls180.v:1261.5-1261.49" wire $1\main_sdphy_dataw_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1259.11-1259.58" + attribute \src "ls180.v:1264.11-1264.58" wire width 4 $1\main_sdphy_dataw_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:1260.5-1260.53" + attribute \src "ls180.v:1265.5-1265.53" wire $1\main_sdphy_dataw_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:1263.5-1263.39" + attribute \src "ls180.v:1268.5-1268.39" wire $1\main_sdphy_dataw_sink_first[0:0] - attribute \src "ls180.v:1264.5-1264.38" + attribute \src "ls180.v:1269.5-1269.38" wire $1\main_sdphy_dataw_sink_last[0:0] - attribute \src "ls180.v:1265.11-1265.52" + attribute \src "ls180.v:1270.11-1270.52" wire width 8 $1\main_sdphy_dataw_sink_payload_data[7:0] - attribute \src "ls180.v:1262.5-1262.39" + attribute \src "ls180.v:1267.5-1267.39" wire $1\main_sdphy_dataw_sink_ready[0:0] - attribute \src "ls180.v:1261.5-1261.39" + attribute \src "ls180.v:1266.5-1266.39" wire $1\main_sdphy_dataw_sink_valid[0:0] - attribute \src "ls180.v:1279.5-1279.34" + attribute \src "ls180.v:1284.5-1284.34" wire $1\main_sdphy_dataw_start[0:0] - attribute \src "ls180.v:1266.5-1266.33" + attribute \src "ls180.v:1271.5-1271.33" wire $1\main_sdphy_dataw_stop[0:0] - attribute \src "ls180.v:1280.5-1280.34" + attribute \src "ls180.v:1285.5-1285.34" wire $1\main_sdphy_dataw_valid[0:0] - attribute \src "ls180.v:1160.11-1160.39" + attribute \src "ls180.v:1165.11-1165.39" wire width 8 $1\main_sdphy_init_count[7:0] - attribute \src "ls180.v:1834.11-1834.66" + attribute \src "ls180.v:1839.11-1839.66" wire width 8 $1\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] - attribute \src "ls180.v:1835.5-1835.63" + attribute \src "ls180.v:1840.5-1840.63" wire $1\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] - attribute \src "ls180.v:1155.5-1155.48" + attribute \src "ls180.v:1160.5-1160.48" wire $1\main_sdphy_init_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1156.5-1156.50" + attribute \src "ls180.v:1161.5-1161.50" wire $1\main_sdphy_init_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:1157.5-1157.51" + attribute \src "ls180.v:1162.5-1162.51" wire $1\main_sdphy_init_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:1158.11-1158.57" + attribute \src "ls180.v:1163.11-1163.57" wire width 4 $1\main_sdphy_init_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:1159.5-1159.52" + attribute \src "ls180.v:1164.5-1164.52" wire $1\main_sdphy_init_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:1409.5-1409.35" + attribute \src "ls180.v:1414.5-1414.35" wire $1\main_sdphy_sdpads_cmd_i[0:0] - attribute \src "ls180.v:1412.11-1412.42" + attribute \src "ls180.v:1417.11-1417.42" wire width 4 $1\main_sdphy_sdpads_data_i[3:0] - attribute \src "ls180.v:372.5-372.33" + attribute \src "ls180.v:359.5-359.33" wire $1\main_sdram_address_re[0:0] - attribute \src "ls180.v:371.12-371.46" + attribute \src "ls180.v:358.12-358.46" wire width 13 $1\main_sdram_address_storage[12:0] - attribute \src "ls180.v:374.5-374.34" + attribute \src "ls180.v:361.5-361.34" wire $1\main_sdram_baddress_re[0:0] - attribute \src "ls180.v:373.11-373.45" + attribute \src "ls180.v:360.11-360.45" wire width 2 $1\main_sdram_baddress_storage[1:0] - attribute \src "ls180.v:470.5-470.50" + attribute \src "ls180.v:457.5-457.50" wire $1\main_sdram_bankmachine0_auto_precharge[0:0] - attribute \src "ls180.v:492.11-492.70" + attribute \src "ls180.v:479.11-479.70" wire width 3 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:489.11-489.68" + attribute \src "ls180.v:476.11-476.68" wire width 4 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:491.11-491.70" + attribute \src "ls180.v:478.11-478.70" wire width 3 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:493.11-493.73" + attribute \src "ls180.v:480.11-480.73" wire width 3 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:516.5-516.59" + attribute \src "ls180.v:503.5-503.59" wire $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:517.5-517.58" + attribute \src "ls180.v:504.5-504.58" wire $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:519.12-519.74" + attribute \src "ls180.v:506.12-506.74" wire width 22 $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:518.5-518.64" + attribute \src "ls180.v:505.5-505.64" wire $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:514.5-514.59" + attribute \src "ls180.v:501.5-501.59" wire $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:462.12-462.57" + attribute \src "ls180.v:449.12-449.57" wire width 13 $1\main_sdram_bankmachine0_cmd_payload_a[12:0] - attribute \src "ls180.v:464.5-464.51" + attribute \src "ls180.v:451.5-451.51" wire $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] - attribute \src "ls180.v:467.5-467.54" + attribute \src "ls180.v:454.5-454.54" wire $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:468.5-468.55" + attribute \src "ls180.v:455.5-455.55" wire $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] - attribute \src "ls180.v:469.5-469.56" + attribute \src "ls180.v:456.5-456.56" wire $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] - attribute \src "ls180.v:465.5-465.51" + attribute \src "ls180.v:452.5-452.51" wire $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] - attribute \src "ls180.v:466.5-466.50" + attribute \src "ls180.v:453.5-453.50" wire $1\main_sdram_bankmachine0_cmd_payload_we[0:0] - attribute \src "ls180.v:461.5-461.45" + attribute \src "ls180.v:448.5-448.45" wire $1\main_sdram_bankmachine0_cmd_ready[0:0] - attribute \src "ls180.v:460.5-460.45" + attribute \src "ls180.v:447.5-447.45" wire $1\main_sdram_bankmachine0_cmd_valid[0:0] - attribute \src "ls180.v:459.5-459.47" + attribute \src "ls180.v:446.5-446.47" wire $1\main_sdram_bankmachine0_refresh_gnt[0:0] - attribute \src "ls180.v:457.5-457.51" + attribute \src "ls180.v:444.5-444.51" wire $1\main_sdram_bankmachine0_req_rdata_valid[0:0] - attribute \src "ls180.v:456.5-456.51" + attribute \src "ls180.v:443.5-443.51" wire $1\main_sdram_bankmachine0_req_wdata_ready[0:0] - attribute \src "ls180.v:520.12-520.47" + attribute \src "ls180.v:507.12-507.47" wire width 13 $1\main_sdram_bankmachine0_row[12:0] - attribute \src "ls180.v:524.5-524.45" + attribute \src "ls180.v:511.5-511.45" wire $1\main_sdram_bankmachine0_row_close[0:0] - attribute \src "ls180.v:525.5-525.54" + attribute \src "ls180.v:512.5-512.54" wire $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:523.5-523.44" + attribute \src "ls180.v:510.5-510.44" wire $1\main_sdram_bankmachine0_row_open[0:0] - attribute \src "ls180.v:521.5-521.46" + attribute \src "ls180.v:508.5-508.46" wire $1\main_sdram_bankmachine0_row_opened[0:0] - attribute \src "ls180.v:528.11-528.55" + attribute \src "ls180.v:515.11-515.55" wire width 3 $1\main_sdram_bankmachine0_twtpcon_count[2:0] - attribute \src "ls180.v:527.32-527.76" + attribute \src "ls180.v:514.32-514.76" wire $1\main_sdram_bankmachine0_twtpcon_ready[0:0] - attribute \src "ls180.v:552.5-552.50" + attribute \src "ls180.v:539.5-539.50" wire $1\main_sdram_bankmachine1_auto_precharge[0:0] - attribute \src "ls180.v:574.11-574.70" + attribute \src "ls180.v:561.11-561.70" wire width 3 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:571.11-571.68" + attribute \src "ls180.v:558.11-558.68" wire width 4 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:573.11-573.70" + attribute \src "ls180.v:560.11-560.70" wire width 3 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:575.11-575.73" + attribute \src "ls180.v:562.11-562.73" wire width 3 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:598.5-598.59" + attribute \src "ls180.v:585.5-585.59" wire $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:599.5-599.58" + attribute \src "ls180.v:586.5-586.58" wire $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:601.12-601.74" + attribute \src "ls180.v:588.12-588.74" wire width 22 $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:600.5-600.64" + attribute \src "ls180.v:587.5-587.64" wire $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:596.5-596.59" + attribute \src "ls180.v:583.5-583.59" wire $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:544.12-544.57" + attribute \src "ls180.v:531.12-531.57" wire width 13 $1\main_sdram_bankmachine1_cmd_payload_a[12:0] - attribute \src "ls180.v:546.5-546.51" + attribute \src "ls180.v:533.5-533.51" wire $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] - attribute \src "ls180.v:549.5-549.54" + attribute \src "ls180.v:536.5-536.54" wire $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:550.5-550.55" + attribute \src "ls180.v:537.5-537.55" wire $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] - attribute \src "ls180.v:551.5-551.56" + attribute \src "ls180.v:538.5-538.56" wire $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] - attribute \src "ls180.v:547.5-547.51" + attribute \src "ls180.v:534.5-534.51" wire $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] - attribute \src "ls180.v:548.5-548.50" + attribute \src "ls180.v:535.5-535.50" wire $1\main_sdram_bankmachine1_cmd_payload_we[0:0] - attribute \src "ls180.v:543.5-543.45" + attribute \src "ls180.v:530.5-530.45" wire $1\main_sdram_bankmachine1_cmd_ready[0:0] - attribute \src "ls180.v:542.5-542.45" + attribute \src "ls180.v:529.5-529.45" wire $1\main_sdram_bankmachine1_cmd_valid[0:0] - attribute \src "ls180.v:541.5-541.47" + attribute \src "ls180.v:528.5-528.47" wire $1\main_sdram_bankmachine1_refresh_gnt[0:0] - attribute \src "ls180.v:539.5-539.51" + attribute \src "ls180.v:526.5-526.51" wire $1\main_sdram_bankmachine1_req_rdata_valid[0:0] - attribute \src "ls180.v:538.5-538.51" + attribute \src "ls180.v:525.5-525.51" wire $1\main_sdram_bankmachine1_req_wdata_ready[0:0] - attribute \src "ls180.v:602.12-602.47" + attribute \src "ls180.v:589.12-589.47" wire width 13 $1\main_sdram_bankmachine1_row[12:0] - attribute \src "ls180.v:606.5-606.45" + attribute \src "ls180.v:593.5-593.45" wire $1\main_sdram_bankmachine1_row_close[0:0] - attribute \src "ls180.v:607.5-607.54" + attribute \src "ls180.v:594.5-594.54" wire $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:605.5-605.44" + attribute \src "ls180.v:592.5-592.44" wire $1\main_sdram_bankmachine1_row_open[0:0] - attribute \src "ls180.v:603.5-603.46" + attribute \src "ls180.v:590.5-590.46" wire $1\main_sdram_bankmachine1_row_opened[0:0] - attribute \src "ls180.v:610.11-610.55" + attribute \src "ls180.v:597.11-597.55" wire width 3 $1\main_sdram_bankmachine1_twtpcon_count[2:0] - attribute \src "ls180.v:609.32-609.76" + attribute \src "ls180.v:596.32-596.76" wire $1\main_sdram_bankmachine1_twtpcon_ready[0:0] - attribute \src "ls180.v:634.5-634.50" + attribute \src "ls180.v:621.5-621.50" wire $1\main_sdram_bankmachine2_auto_precharge[0:0] - attribute \src "ls180.v:656.11-656.70" + attribute \src "ls180.v:643.11-643.70" wire width 3 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:653.11-653.68" + attribute \src "ls180.v:640.11-640.68" wire width 4 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:655.11-655.70" + attribute \src "ls180.v:642.11-642.70" wire width 3 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:657.11-657.73" + attribute \src "ls180.v:644.11-644.73" wire width 3 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:680.5-680.59" + attribute \src "ls180.v:667.5-667.59" wire $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:681.5-681.58" + attribute \src "ls180.v:668.5-668.58" wire $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:683.12-683.74" + attribute \src "ls180.v:670.12-670.74" wire width 22 $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:682.5-682.64" + attribute \src "ls180.v:669.5-669.64" wire $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:678.5-678.59" + attribute \src "ls180.v:665.5-665.59" wire $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:626.12-626.57" + attribute \src "ls180.v:613.12-613.57" wire width 13 $1\main_sdram_bankmachine2_cmd_payload_a[12:0] - attribute \src "ls180.v:628.5-628.51" + attribute \src "ls180.v:615.5-615.51" wire $1\main_sdram_bankmachine2_cmd_payload_cas[0:0] - attribute \src "ls180.v:631.5-631.54" + attribute \src "ls180.v:618.5-618.54" wire $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:632.5-632.55" + attribute \src "ls180.v:619.5-619.55" wire $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] - attribute \src "ls180.v:633.5-633.56" + attribute \src "ls180.v:620.5-620.56" wire $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0] - attribute \src "ls180.v:629.5-629.51" + attribute \src "ls180.v:616.5-616.51" wire $1\main_sdram_bankmachine2_cmd_payload_ras[0:0] - attribute \src "ls180.v:630.5-630.50" + attribute \src "ls180.v:617.5-617.50" wire $1\main_sdram_bankmachine2_cmd_payload_we[0:0] - attribute \src "ls180.v:625.5-625.45" + attribute \src "ls180.v:612.5-612.45" wire $1\main_sdram_bankmachine2_cmd_ready[0:0] - attribute \src "ls180.v:624.5-624.45" + attribute \src "ls180.v:611.5-611.45" wire $1\main_sdram_bankmachine2_cmd_valid[0:0] - attribute \src "ls180.v:623.5-623.47" + attribute \src "ls180.v:610.5-610.47" wire $1\main_sdram_bankmachine2_refresh_gnt[0:0] - attribute \src "ls180.v:621.5-621.51" + attribute \src "ls180.v:608.5-608.51" wire $1\main_sdram_bankmachine2_req_rdata_valid[0:0] - attribute \src "ls180.v:620.5-620.51" + attribute \src "ls180.v:607.5-607.51" wire $1\main_sdram_bankmachine2_req_wdata_ready[0:0] - attribute \src "ls180.v:684.12-684.47" + attribute \src "ls180.v:671.12-671.47" wire width 13 $1\main_sdram_bankmachine2_row[12:0] - attribute \src "ls180.v:688.5-688.45" + attribute \src "ls180.v:675.5-675.45" wire $1\main_sdram_bankmachine2_row_close[0:0] - attribute \src "ls180.v:689.5-689.54" + attribute \src "ls180.v:676.5-676.54" wire $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:687.5-687.44" + attribute \src "ls180.v:674.5-674.44" wire $1\main_sdram_bankmachine2_row_open[0:0] - attribute \src "ls180.v:685.5-685.46" + attribute \src "ls180.v:672.5-672.46" wire $1\main_sdram_bankmachine2_row_opened[0:0] - attribute \src "ls180.v:692.11-692.55" + attribute \src "ls180.v:679.11-679.55" wire width 3 $1\main_sdram_bankmachine2_twtpcon_count[2:0] - attribute \src "ls180.v:691.32-691.76" + attribute \src "ls180.v:678.32-678.76" wire $1\main_sdram_bankmachine2_twtpcon_ready[0:0] - attribute \src "ls180.v:716.5-716.50" + attribute \src "ls180.v:703.5-703.50" wire $1\main_sdram_bankmachine3_auto_precharge[0:0] - attribute \src "ls180.v:738.11-738.70" + attribute \src "ls180.v:725.11-725.70" wire width 3 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:735.11-735.68" + attribute \src "ls180.v:722.11-722.68" wire width 4 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:737.11-737.70" + attribute \src "ls180.v:724.11-724.70" wire width 3 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:739.11-739.73" + attribute \src "ls180.v:726.11-726.73" wire width 3 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:762.5-762.59" + attribute \src "ls180.v:749.5-749.59" wire $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:763.5-763.58" + attribute \src "ls180.v:750.5-750.58" wire $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:765.12-765.74" + attribute \src "ls180.v:752.12-752.74" wire width 22 $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:764.5-764.64" + attribute \src "ls180.v:751.5-751.64" wire $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:760.5-760.59" + attribute \src "ls180.v:747.5-747.59" wire $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:708.12-708.57" + attribute \src "ls180.v:695.12-695.57" wire width 13 $1\main_sdram_bankmachine3_cmd_payload_a[12:0] - attribute \src "ls180.v:710.5-710.51" + attribute \src "ls180.v:697.5-697.51" wire $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] - attribute \src "ls180.v:713.5-713.54" + attribute \src "ls180.v:700.5-700.54" wire $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:714.5-714.55" + attribute \src "ls180.v:701.5-701.55" wire $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] - attribute \src "ls180.v:715.5-715.56" + attribute \src "ls180.v:702.5-702.56" wire $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] - attribute \src "ls180.v:711.5-711.51" + attribute \src "ls180.v:698.5-698.51" wire $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] - attribute \src "ls180.v:712.5-712.50" + attribute \src "ls180.v:699.5-699.50" wire $1\main_sdram_bankmachine3_cmd_payload_we[0:0] - attribute \src "ls180.v:707.5-707.45" + attribute \src "ls180.v:694.5-694.45" wire $1\main_sdram_bankmachine3_cmd_ready[0:0] - attribute \src "ls180.v:706.5-706.45" + attribute \src "ls180.v:693.5-693.45" wire $1\main_sdram_bankmachine3_cmd_valid[0:0] - attribute \src "ls180.v:705.5-705.47" + attribute \src "ls180.v:692.5-692.47" wire $1\main_sdram_bankmachine3_refresh_gnt[0:0] - attribute \src "ls180.v:703.5-703.51" + attribute \src "ls180.v:690.5-690.51" wire $1\main_sdram_bankmachine3_req_rdata_valid[0:0] - attribute \src "ls180.v:702.5-702.51" + attribute \src "ls180.v:689.5-689.51" wire $1\main_sdram_bankmachine3_req_wdata_ready[0:0] - attribute \src "ls180.v:766.12-766.47" + attribute \src "ls180.v:753.12-753.47" wire width 13 $1\main_sdram_bankmachine3_row[12:0] - attribute \src "ls180.v:770.5-770.45" + attribute \src "ls180.v:757.5-757.45" wire $1\main_sdram_bankmachine3_row_close[0:0] - attribute \src "ls180.v:771.5-771.54" + attribute \src "ls180.v:758.5-758.54" wire $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:769.5-769.44" + attribute \src "ls180.v:756.5-756.44" wire $1\main_sdram_bankmachine3_row_open[0:0] - attribute \src "ls180.v:767.5-767.46" + attribute \src "ls180.v:754.5-754.46" wire $1\main_sdram_bankmachine3_row_opened[0:0] - attribute \src "ls180.v:774.11-774.55" + attribute \src "ls180.v:761.11-761.55" wire width 3 $1\main_sdram_bankmachine3_twtpcon_count[2:0] - attribute \src "ls180.v:773.32-773.76" + attribute \src "ls180.v:760.32-760.76" wire $1\main_sdram_bankmachine3_twtpcon_ready[0:0] - attribute \src "ls180.v:789.5-789.49" + attribute \src "ls180.v:776.5-776.49" wire $1\main_sdram_choose_cmd_cmd_payload_cas[0:0] - attribute \src "ls180.v:790.5-790.49" + attribute \src "ls180.v:777.5-777.49" wire $1\main_sdram_choose_cmd_cmd_payload_ras[0:0] - attribute \src "ls180.v:791.5-791.48" + attribute \src "ls180.v:778.5-778.48" wire $1\main_sdram_choose_cmd_cmd_payload_we[0:0] - attribute \src "ls180.v:797.11-797.45" + attribute \src "ls180.v:784.11-784.45" wire width 2 $1\main_sdram_choose_cmd_grant[1:0] - attribute \src "ls180.v:795.11-795.46" + attribute \src "ls180.v:782.11-782.46" wire width 4 $1\main_sdram_choose_cmd_valids[3:0] - attribute \src "ls180.v:807.5-807.49" + attribute \src "ls180.v:794.5-794.49" wire $1\main_sdram_choose_req_cmd_payload_cas[0:0] - attribute \src "ls180.v:808.5-808.49" + attribute \src "ls180.v:795.5-795.49" wire $1\main_sdram_choose_req_cmd_payload_ras[0:0] - attribute \src "ls180.v:809.5-809.48" + attribute \src "ls180.v:796.5-796.48" wire $1\main_sdram_choose_req_cmd_payload_we[0:0] - attribute \src "ls180.v:804.5-804.43" + attribute \src "ls180.v:791.5-791.43" wire $1\main_sdram_choose_req_cmd_ready[0:0] - attribute \src "ls180.v:815.11-815.45" + attribute \src "ls180.v:802.11-802.45" wire width 2 $1\main_sdram_choose_req_grant[1:0] - attribute \src "ls180.v:813.11-813.46" + attribute \src "ls180.v:800.11-800.46" wire width 4 $1\main_sdram_choose_req_valids[3:0] - attribute \src "ls180.v:802.5-802.48" + attribute \src "ls180.v:789.5-789.48" wire $1\main_sdram_choose_req_want_activates[0:0] - attribute \src "ls180.v:799.5-799.44" + attribute \src "ls180.v:786.5-786.44" wire $1\main_sdram_choose_req_want_reads[0:0] - attribute \src "ls180.v:800.5-800.45" + attribute \src "ls180.v:787.5-787.45" wire $1\main_sdram_choose_req_want_writes[0:0] - attribute \src "ls180.v:428.5-428.31" + attribute \src "ls180.v:415.5-415.31" wire $1\main_sdram_cmd_last[0:0] - attribute \src "ls180.v:429.12-429.44" + attribute \src "ls180.v:416.12-416.44" wire width 13 $1\main_sdram_cmd_payload_a[12:0] - attribute \src "ls180.v:430.11-430.43" + attribute \src "ls180.v:417.11-417.43" wire width 2 $1\main_sdram_cmd_payload_ba[1:0] - attribute \src "ls180.v:431.5-431.38" + attribute \src "ls180.v:418.5-418.38" wire $1\main_sdram_cmd_payload_cas[0:0] - attribute \src "ls180.v:432.5-432.38" + attribute \src "ls180.v:419.5-419.38" wire $1\main_sdram_cmd_payload_ras[0:0] - attribute \src "ls180.v:433.5-433.37" + attribute \src "ls180.v:420.5-420.37" wire $1\main_sdram_cmd_payload_we[0:0] - attribute \src "ls180.v:427.5-427.32" + attribute \src "ls180.v:414.5-414.32" wire $1\main_sdram_cmd_ready[0:0] - attribute \src "ls180.v:426.5-426.32" + attribute \src "ls180.v:413.5-413.32" wire $1\main_sdram_cmd_valid[0:0] - attribute \src "ls180.v:366.5-366.33" + attribute \src "ls180.v:353.5-353.33" wire $1\main_sdram_command_re[0:0] - attribute \src "ls180.v:365.11-365.44" + attribute \src "ls180.v:352.11-352.44" wire width 6 $1\main_sdram_command_storage[5:0] - attribute \src "ls180.v:410.12-410.45" + attribute \src "ls180.v:397.12-397.45" wire width 13 $1\main_sdram_dfi_p0_address[12:0] - attribute \src "ls180.v:411.11-411.40" + attribute \src "ls180.v:398.11-398.40" wire width 2 $1\main_sdram_dfi_p0_bank[1:0] - attribute \src "ls180.v:412.5-412.35" + attribute \src "ls180.v:399.5-399.35" wire $1\main_sdram_dfi_p0_cas_n[0:0] - attribute \src "ls180.v:413.5-413.34" + attribute \src "ls180.v:400.5-400.34" wire $1\main_sdram_dfi_p0_cs_n[0:0] - attribute \src "ls180.v:414.5-414.35" + attribute \src "ls180.v:401.5-401.35" wire $1\main_sdram_dfi_p0_ras_n[0:0] - attribute \src "ls180.v:423.5-423.39" + attribute \src "ls180.v:410.5-410.39" wire $1\main_sdram_dfi_p0_rddata_en[0:0] - attribute \src "ls180.v:415.5-415.34" + attribute \src "ls180.v:402.5-402.34" wire $1\main_sdram_dfi_p0_we_n[0:0] - attribute \src "ls180.v:421.5-421.39" + attribute \src "ls180.v:408.5-408.39" wire $1\main_sdram_dfi_p0_wrdata_en[0:0] - attribute \src "ls180.v:834.5-834.26" + attribute \src "ls180.v:821.5-821.26" wire $1\main_sdram_en0[0:0] - attribute \src "ls180.v:837.5-837.26" + attribute \src "ls180.v:824.5-824.26" wire $1\main_sdram_en1[0:0] - attribute \src "ls180.v:407.12-407.46" + attribute \src "ls180.v:394.12-394.46" wire width 16 $1\main_sdram_interface_wdata[15:0] - attribute \src "ls180.v:408.11-408.47" + attribute \src "ls180.v:395.11-395.47" wire width 2 $1\main_sdram_interface_wdata_we[1:0] - attribute \src "ls180.v:313.5-313.36" + attribute \src "ls180.v:300.5-300.36" wire $1\main_sdram_inti_p0_cas_n[0:0] - attribute \src "ls180.v:314.5-314.35" + attribute \src "ls180.v:301.5-301.35" wire $1\main_sdram_inti_p0_cs_n[0:0] - attribute \src "ls180.v:315.5-315.36" + attribute \src "ls180.v:302.5-302.36" wire $1\main_sdram_inti_p0_ras_n[0:0] - attribute \src "ls180.v:325.12-325.45" + attribute \src "ls180.v:312.12-312.45" wire width 16 $1\main_sdram_inti_p0_rddata[15:0] - attribute \src "ls180.v:326.5-326.43" + attribute \src "ls180.v:313.5-313.43" wire $1\main_sdram_inti_p0_rddata_valid[0:0] - attribute \src "ls180.v:316.5-316.35" + attribute \src "ls180.v:303.5-303.35" wire $1\main_sdram_inti_p0_we_n[0:0] - attribute \src "ls180.v:352.5-352.38" + attribute \src "ls180.v:339.5-339.38" wire $1\main_sdram_master_p0_act_n[0:0] - attribute \src "ls180.v:343.12-343.48" + attribute \src "ls180.v:330.12-330.48" wire width 13 $1\main_sdram_master_p0_address[12:0] - attribute \src "ls180.v:344.11-344.43" + attribute \src "ls180.v:331.11-331.43" wire width 2 $1\main_sdram_master_p0_bank[1:0] - attribute \src "ls180.v:345.5-345.38" + attribute \src "ls180.v:332.5-332.38" wire $1\main_sdram_master_p0_cas_n[0:0] - attribute \src "ls180.v:349.5-349.36" + attribute \src "ls180.v:336.5-336.36" wire $1\main_sdram_master_p0_cke[0:0] - attribute \src "ls180.v:346.5-346.37" + attribute \src "ls180.v:333.5-333.37" wire $1\main_sdram_master_p0_cs_n[0:0] - attribute \src "ls180.v:350.5-350.36" + attribute \src "ls180.v:337.5-337.36" wire $1\main_sdram_master_p0_odt[0:0] - attribute \src "ls180.v:347.5-347.38" + attribute \src "ls180.v:334.5-334.38" wire $1\main_sdram_master_p0_ras_n[0:0] - attribute \src "ls180.v:356.5-356.42" + attribute \src "ls180.v:343.5-343.42" wire $1\main_sdram_master_p0_rddata_en[0:0] - attribute \src "ls180.v:351.5-351.40" + attribute \src "ls180.v:338.5-338.40" wire $1\main_sdram_master_p0_reset_n[0:0] - attribute \src "ls180.v:348.5-348.37" + attribute \src "ls180.v:335.5-335.37" wire $1\main_sdram_master_p0_we_n[0:0] - attribute \src "ls180.v:353.12-353.47" + attribute \src "ls180.v:340.12-340.47" wire width 16 $1\main_sdram_master_p0_wrdata[15:0] - attribute \src "ls180.v:354.5-354.42" + attribute \src "ls180.v:341.5-341.42" wire $1\main_sdram_master_p0_wrdata_en[0:0] - attribute \src "ls180.v:355.11-355.50" + attribute \src "ls180.v:342.11-342.50" wire width 2 $1\main_sdram_master_p0_wrdata_mask[1:0] - attribute \src "ls180.v:444.5-444.38" + attribute \src "ls180.v:431.5-431.38" wire $1\main_sdram_postponer_count[0:0] - attribute \src "ls180.v:443.5-443.38" + attribute \src "ls180.v:430.5-430.38" wire $1\main_sdram_postponer_req_o[0:0] - attribute \src "ls180.v:364.5-364.25" + attribute \src "ls180.v:351.5-351.25" wire $1\main_sdram_re[0:0] - attribute \src "ls180.v:450.5-450.38" + attribute \src "ls180.v:437.5-437.38" wire $1\main_sdram_sequencer_count[0:0] - attribute \src "ls180.v:449.11-449.46" + attribute \src "ls180.v:436.11-436.46" wire width 4 $1\main_sdram_sequencer_counter[3:0] - attribute \src "ls180.v:448.5-448.38" + attribute \src "ls180.v:435.5-435.38" wire $1\main_sdram_sequencer_done1[0:0] - attribute \src "ls180.v:445.5-445.39" + attribute \src "ls180.v:432.5-432.39" wire $1\main_sdram_sequencer_start0[0:0] - attribute \src "ls180.v:341.12-341.46" + attribute \src "ls180.v:328.12-328.46" wire width 16 $1\main_sdram_slave_p0_rddata[15:0] - attribute \src "ls180.v:342.5-342.44" + attribute \src "ls180.v:329.5-329.44" wire $1\main_sdram_slave_p0_rddata_valid[0:0] - attribute \src "ls180.v:377.12-377.37" + attribute \src "ls180.v:364.12-364.37" wire width 16 $1\main_sdram_status[15:0] - attribute \src "ls180.v:819.11-819.40" + attribute \src "ls180.v:806.11-806.40" wire width 2 $1\main_sdram_steerer_sel[1:0] - attribute \src "ls180.v:363.11-363.36" + attribute \src "ls180.v:350.11-350.36" wire width 4 $1\main_sdram_storage[3:0] - attribute \src "ls180.v:828.5-828.36" + attribute \src "ls180.v:815.5-815.36" wire $1\main_sdram_tccdcon_count[0:0] - attribute \src "ls180.v:827.32-827.63" + attribute \src "ls180.v:814.32-814.63" wire $1\main_sdram_tccdcon_ready[0:0] - attribute \src "ls180.v:836.11-836.34" + attribute \src "ls180.v:823.11-823.34" wire width 5 $1\main_sdram_time0[4:0] - attribute \src "ls180.v:839.11-839.34" + attribute \src "ls180.v:826.11-826.34" wire width 4 $1\main_sdram_time1[3:0] - attribute \src "ls180.v:441.11-441.44" + attribute \src "ls180.v:428.11-428.44" wire width 10 $1\main_sdram_timer_count1[9:0] - attribute \src "ls180.v:831.11-831.42" + attribute \src "ls180.v:818.11-818.42" wire width 3 $1\main_sdram_twtrcon_count[2:0] - attribute \src "ls180.v:830.32-830.63" + attribute \src "ls180.v:817.32-817.63" wire $1\main_sdram_twtrcon_ready[0:0] - attribute \src "ls180.v:376.5-376.32" + attribute \src "ls180.v:363.5-363.32" wire $1\main_sdram_wrdata_re[0:0] - attribute \src "ls180.v:375.12-375.45" + attribute \src "ls180.v:362.12-362.45" wire width 16 $1\main_sdram_wrdata_storage[15:0] - attribute \src "ls180.v:1044.12-1044.44" + attribute \src "ls180.v:855.5-855.54" + wire $1\main_socbushandler_converted_interface_ack[0:0] + attribute \src "ls180.v:861.5-861.38" + wire $1\main_socbushandler_counter[0:0] + attribute \src "ls180.v:1790.5-1790.60" + wire $1\main_socbushandler_counter_converter2_next_value[0:0] + attribute \src "ls180.v:1791.5-1791.63" + wire $1\main_socbushandler_counter_converter2_next_value_ce[0:0] + attribute \src "ls180.v:863.12-863.44" + wire width 64 $1\main_socbushandler_dat_r[63:0] + attribute \src "ls180.v:860.5-860.35" + wire $1\main_socbushandler_skip[0:0] + attribute \src "ls180.v:1049.12-1049.44" wire width 16 $1\main_spimaster11_storage[15:0] - attribute \src "ls180.v:1045.5-1045.31" + attribute \src "ls180.v:1050.5-1050.31" wire $1\main_spimaster12_re[0:0] - attribute \src "ls180.v:1049.11-1049.42" + attribute \src "ls180.v:1054.11-1054.42" wire width 8 $1\main_spimaster16_storage[7:0] - attribute \src "ls180.v:1050.5-1050.31" + attribute \src "ls180.v:1055.5-1055.31" wire $1\main_spimaster17_re[0:0] - attribute \src "ls180.v:1106.5-1106.30" + attribute \src "ls180.v:1111.5-1111.30" wire $1\main_spimaster1_re[0:0] - attribute \src "ls180.v:1105.12-1105.45" + attribute \src "ls180.v:1110.12-1110.45" wire width 16 $1\main_spimaster1_storage[15:0] - attribute \src "ls180.v:1054.5-1054.36" + attribute \src "ls180.v:1059.5-1059.36" wire $1\main_spimaster21_storage[0:0] - attribute \src "ls180.v:1055.5-1055.31" + attribute \src "ls180.v:1060.5-1060.31" wire $1\main_spimaster22_re[0:0] - attribute \src "ls180.v:1056.5-1056.36" + attribute \src "ls180.v:1061.5-1061.36" wire $1\main_spimaster23_storage[0:0] - attribute \src "ls180.v:1057.5-1057.31" + attribute \src "ls180.v:1062.5-1062.31" wire $1\main_spimaster24_re[0:0] - attribute \src "ls180.v:1058.5-1058.39" + attribute \src "ls180.v:1063.5-1063.39" wire $1\main_spimaster25_clk_enable[0:0] - attribute \src "ls180.v:1059.5-1059.38" + attribute \src "ls180.v:1064.5-1064.38" wire $1\main_spimaster26_cs_enable[0:0] - attribute \src "ls180.v:1060.11-1060.40" + attribute \src "ls180.v:1065.11-1065.40" wire width 3 $1\main_spimaster27_count[2:0] - attribute \src "ls180.v:1826.11-1826.62" + attribute \src "ls180.v:1831.11-1831.62" wire width 3 $1\main_spimaster27_count_spimaster0_next_value[2:0] - attribute \src "ls180.v:1827.5-1827.59" + attribute \src "ls180.v:1832.5-1832.59" wire $1\main_spimaster27_count_spimaster0_next_value_ce[0:0] - attribute \src "ls180.v:1061.5-1061.39" + attribute \src "ls180.v:1066.5-1066.39" wire $1\main_spimaster28_mosi_latch[0:0] - attribute \src "ls180.v:1062.5-1062.39" + attribute \src "ls180.v:1067.5-1067.39" wire $1\main_spimaster29_miso_latch[0:0] - attribute \src "ls180.v:1035.5-1035.32" + attribute \src "ls180.v:1040.5-1040.32" wire $1\main_spimaster2_done[0:0] - attribute \src "ls180.v:1063.12-1063.48" + attribute \src "ls180.v:1068.12-1068.48" wire width 16 $1\main_spimaster30_clk_divider[15:0] - attribute \src "ls180.v:1066.11-1066.44" + attribute \src "ls180.v:1071.11-1071.44" wire width 8 $1\main_spimaster33_mosi_data[7:0] - attribute \src "ls180.v:1067.11-1067.43" + attribute \src "ls180.v:1072.11-1072.43" wire width 3 $1\main_spimaster34_mosi_sel[2:0] - attribute \src "ls180.v:1068.11-1068.44" + attribute \src "ls180.v:1073.11-1073.44" wire width 8 $1\main_spimaster35_miso_data[7:0] - attribute \src "ls180.v:1036.5-1036.31" + attribute \src "ls180.v:1041.5-1041.31" wire $1\main_spimaster3_irq[0:0] - attribute \src "ls180.v:1038.11-1038.38" + attribute \src "ls180.v:1043.11-1043.38" wire width 8 $1\main_spimaster5_miso[7:0] - attribute \src "ls180.v:1042.5-1042.33" + attribute \src "ls180.v:1047.5-1047.33" wire $1\main_spimaster9_start[0:0] - attribute \src "ls180.v:1099.12-1099.47" + attribute \src "ls180.v:1104.12-1104.47" wire width 16 $1\main_spisdcard_clk_divider1[15:0] - attribute \src "ls180.v:1094.5-1094.37" + attribute \src "ls180.v:1099.5-1099.37" wire $1\main_spisdcard_clk_enable[0:0] - attribute \src "ls180.v:1081.5-1081.37" + attribute \src "ls180.v:1086.5-1086.37" wire $1\main_spisdcard_control_re[0:0] - attribute \src "ls180.v:1080.12-1080.50" + attribute \src "ls180.v:1085.12-1085.50" wire width 16 $1\main_spisdcard_control_storage[15:0] - attribute \src "ls180.v:1096.11-1096.38" + attribute \src "ls180.v:1101.11-1101.38" wire width 3 $1\main_spisdcard_count[2:0] - attribute \src "ls180.v:1830.11-1830.60" + attribute \src "ls180.v:1835.11-1835.60" wire width 3 $1\main_spisdcard_count_spimaster1_next_value[2:0] - attribute \src "ls180.v:1831.5-1831.57" + attribute \src "ls180.v:1836.5-1836.57" wire $1\main_spisdcard_count_spimaster1_next_value_ce[0:0] - attribute \src "ls180.v:1095.5-1095.36" + attribute \src "ls180.v:1100.5-1100.36" wire $1\main_spisdcard_cs_enable[0:0] - attribute \src "ls180.v:1091.5-1091.32" + attribute \src "ls180.v:1096.5-1096.32" wire $1\main_spisdcard_cs_re[0:0] - attribute \src "ls180.v:1090.5-1090.37" + attribute \src "ls180.v:1095.5-1095.37" wire $1\main_spisdcard_cs_storage[0:0] - attribute \src "ls180.v:1071.5-1071.32" + attribute \src "ls180.v:1076.5-1076.32" wire $1\main_spisdcard_done0[0:0] - attribute \src "ls180.v:1072.5-1072.30" + attribute \src "ls180.v:1077.5-1077.30" wire $1\main_spisdcard_irq[0:0] - attribute \src "ls180.v:1093.5-1093.38" + attribute \src "ls180.v:1098.5-1098.38" wire $1\main_spisdcard_loopback_re[0:0] - attribute \src "ls180.v:1092.5-1092.43" + attribute \src "ls180.v:1097.5-1097.43" wire $1\main_spisdcard_loopback_storage[0:0] - attribute \src "ls180.v:1074.11-1074.37" + attribute \src "ls180.v:1079.11-1079.37" wire width 8 $1\main_spisdcard_miso[7:0] - attribute \src "ls180.v:1104.11-1104.42" + attribute \src "ls180.v:1109.11-1109.42" wire width 8 $1\main_spisdcard_miso_data[7:0] - attribute \src "ls180.v:1098.5-1098.37" + attribute \src "ls180.v:1103.5-1103.37" wire $1\main_spisdcard_miso_latch[0:0] - attribute \src "ls180.v:1102.11-1102.42" + attribute \src "ls180.v:1107.11-1107.42" wire width 8 $1\main_spisdcard_mosi_data[7:0] - attribute \src "ls180.v:1097.5-1097.37" + attribute \src "ls180.v:1102.5-1102.37" wire $1\main_spisdcard_mosi_latch[0:0] - attribute \src "ls180.v:1086.5-1086.34" + attribute \src "ls180.v:1091.5-1091.34" wire $1\main_spisdcard_mosi_re[0:0] - attribute \src "ls180.v:1103.11-1103.41" + attribute \src "ls180.v:1108.11-1108.41" wire width 3 $1\main_spisdcard_mosi_sel[2:0] - attribute \src "ls180.v:1085.11-1085.45" + attribute \src "ls180.v:1090.11-1090.45" wire width 8 $1\main_spisdcard_mosi_storage[7:0] - attribute \src "ls180.v:1078.5-1078.33" + attribute \src "ls180.v:1083.5-1083.33" wire $1\main_spisdcard_start1[0:0] - attribute \src "ls180.v:258.11-258.31" - wire width 4 $1\main_sram0_we[3:0] - attribute \src "ls180.v:273.11-273.31" - wire width 4 $1\main_sram1_we[3:0] - attribute \src "ls180.v:288.11-288.31" - wire width 4 $1\main_sram2_we[3:0] - attribute \src "ls180.v:932.11-932.50" + attribute \src "ls180.v:215.11-215.31" + wire width 8 $1\main_sram0_we[7:0] + attribute \src "ls180.v:230.11-230.31" + wire width 8 $1\main_sram1_we[7:0] + attribute \src "ls180.v:245.11-245.31" + wire width 8 $1\main_sram2_we[7:0] + attribute \src "ls180.v:931.11-931.50" wire width 2 $1\main_uart_eventmanager_pending_w[1:0] - attribute \src "ls180.v:934.5-934.37" + attribute \src "ls180.v:933.5-933.37" wire $1\main_uart_eventmanager_re[0:0] - attribute \src "ls180.v:928.11-928.49" + attribute \src "ls180.v:927.11-927.49" wire width 2 $1\main_uart_eventmanager_status_w[1:0] - attribute \src "ls180.v:933.11-933.48" + attribute \src "ls180.v:932.11-932.48" wire width 2 $1\main_uart_eventmanager_storage[1:0] - attribute \src "ls180.v:900.12-900.54" + attribute \src "ls180.v:899.12-899.54" wire width 32 $1\main_uart_phy_phase_accumulator_rx[31:0] - attribute \src "ls180.v:890.12-890.54" + attribute \src "ls180.v:889.12-889.54" wire width 32 $1\main_uart_phy_phase_accumulator_tx[31:0] - attribute \src "ls180.v:883.5-883.28" + attribute \src "ls180.v:882.5-882.28" wire $1\main_uart_phy_re[0:0] - attribute \src "ls180.v:904.11-904.43" + attribute \src "ls180.v:903.11-903.43" wire width 4 $1\main_uart_phy_rx_bitcount[3:0] - attribute \src "ls180.v:905.5-905.33" + attribute \src "ls180.v:904.5-904.33" wire $1\main_uart_phy_rx_busy[0:0] - attribute \src "ls180.v:902.5-902.30" + attribute \src "ls180.v:901.5-901.30" wire $1\main_uart_phy_rx_r[0:0] - attribute \src "ls180.v:903.11-903.38" + attribute \src "ls180.v:902.11-902.38" wire width 8 $1\main_uart_phy_rx_reg[7:0] - attribute \src "ls180.v:885.5-885.36" + attribute \src "ls180.v:884.5-884.36" wire $1\main_uart_phy_sink_ready[0:0] - attribute \src "ls180.v:898.11-898.51" + attribute \src "ls180.v:897.11-897.51" wire width 8 $1\main_uart_phy_source_payload_data[7:0] - attribute \src "ls180.v:894.5-894.38" + attribute \src "ls180.v:893.5-893.38" wire $1\main_uart_phy_source_valid[0:0] - attribute \src "ls180.v:882.12-882.47" + attribute \src "ls180.v:881.12-881.47" wire width 32 $1\main_uart_phy_storage[31:0] - attribute \src "ls180.v:892.11-892.43" + attribute \src "ls180.v:891.11-891.43" wire width 4 $1\main_uart_phy_tx_bitcount[3:0] - attribute \src "ls180.v:893.5-893.33" + attribute \src "ls180.v:892.5-892.33" wire $1\main_uart_phy_tx_busy[0:0] - attribute \src "ls180.v:891.11-891.38" + attribute \src "ls180.v:890.11-890.38" wire width 8 $1\main_uart_phy_tx_reg[7:0] - attribute \src "ls180.v:899.5-899.39" + attribute \src "ls180.v:898.5-898.39" wire $1\main_uart_phy_uart_clk_rxen[0:0] - attribute \src "ls180.v:889.5-889.39" + attribute \src "ls180.v:888.5-888.39" wire $1\main_uart_phy_uart_clk_txen[0:0] - attribute \src "ls180.v:923.5-923.30" + attribute \src "ls180.v:922.5-922.30" wire $1\main_uart_rx_clear[0:0] - attribute \src "ls180.v:1007.11-1007.43" + attribute \src "ls180.v:1006.11-1006.43" wire width 4 $1\main_uart_rx_fifo_consume[3:0] - attribute \src "ls180.v:1004.11-1004.42" + attribute \src "ls180.v:1003.11-1003.42" wire width 5 $1\main_uart_rx_fifo_level0[4:0] - attribute \src "ls180.v:1006.11-1006.43" + attribute \src "ls180.v:1005.11-1005.43" wire width 4 $1\main_uart_rx_fifo_produce[3:0] - attribute \src "ls180.v:997.5-997.38" + attribute \src "ls180.v:996.5-996.38" wire $1\main_uart_rx_fifo_readable[0:0] - attribute \src "ls180.v:1008.11-1008.46" + attribute \src "ls180.v:1007.11-1007.46" wire width 4 $1\main_uart_rx_fifo_wrport_adr[3:0] - attribute \src "ls180.v:924.5-924.36" + attribute \src "ls180.v:923.5-923.36" wire $1\main_uart_rx_old_trigger[0:0] - attribute \src "ls180.v:921.5-921.32" + attribute \src "ls180.v:920.5-920.32" wire $1\main_uart_rx_pending[0:0] - attribute \src "ls180.v:918.5-918.30" + attribute \src "ls180.v:917.5-917.30" wire $1\main_uart_tx_clear[0:0] - attribute \src "ls180.v:970.11-970.43" + attribute \src "ls180.v:969.11-969.43" wire width 4 $1\main_uart_tx_fifo_consume[3:0] - attribute \src "ls180.v:967.11-967.42" + attribute \src "ls180.v:966.11-966.42" wire width 5 $1\main_uart_tx_fifo_level0[4:0] - attribute \src "ls180.v:969.11-969.43" + attribute \src "ls180.v:968.11-968.43" wire width 4 $1\main_uart_tx_fifo_produce[3:0] - attribute \src "ls180.v:960.5-960.38" + attribute \src "ls180.v:959.5-959.38" wire $1\main_uart_tx_fifo_readable[0:0] - attribute \src "ls180.v:971.11-971.46" + attribute \src "ls180.v:970.11-970.46" wire width 4 $1\main_uart_tx_fifo_wrport_adr[3:0] - attribute \src "ls180.v:919.5-919.36" + attribute \src "ls180.v:918.5-918.36" wire $1\main_uart_tx_old_trigger[0:0] - attribute \src "ls180.v:916.5-916.32" + attribute \src "ls180.v:915.5-915.32" wire $1\main_uart_tx_pending[0:0] - attribute \src "ls180.v:860.5-860.29" + attribute \src "ls180.v:847.5-847.29" wire $1\main_wb_sdram_ack[0:0] - attribute \src "ls180.v:878.5-878.31" + attribute \src "ls180.v:841.12-841.37" + wire width 30 $1\main_wb_sdram_adr[29:0] + attribute \src "ls180.v:845.5-845.29" + wire $1\main_wb_sdram_cyc[0:0] + attribute \src "ls180.v:842.12-842.39" + wire width 32 $1\main_wb_sdram_dat_w[31:0] + attribute \src "ls180.v:844.11-844.35" + wire width 4 $1\main_wb_sdram_sel[3:0] + attribute \src "ls180.v:846.5-846.29" + wire $1\main_wb_sdram_stb[0:0] + attribute \src "ls180.v:848.5-848.28" + wire $1\main_wb_sdram_we[0:0] + attribute \src "ls180.v:877.5-877.31" wire $1\main_wdata_consumed[0:0] - attribute \src "ls180.v:2860.68-2860.110" - wire $add$ls180.v:2860$34_Y - attribute \src "ls180.v:2920.68-2920.110" - wire $add$ls180.v:2920$45_Y - attribute \src "ls180.v:2980.68-2980.110" - wire $add$ls180.v:2980$56_Y - attribute \src "ls180.v:4143.54-4143.83" - wire $add$ls180.v:4143$588_Y - attribute \src "ls180.v:4243.36-4243.89" - wire width 5 $add$ls180.v:4243$634_Y - attribute \src "ls180.v:4273.36-4273.89" - wire width 5 $add$ls180.v:4273$645_Y - attribute \src "ls180.v:4328.54-4328.83" - wire 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$add$ls180.v:5345$1016_Y - attribute \src "ls180.v:5397.55-5397.84" - wire width 32 $add$ls180.v:5397$1026_Y - attribute \src "ls180.v:5423.57-5423.86" - wire width 32 $add$ls180.v:5423$1034_Y - attribute \src "ls180.v:5544.51-5544.134" - wire width 32 $add$ls180.v:5544$1050_Y - attribute \src "ls180.v:5547.77-5547.125" - wire width 32 $add$ls180.v:5547$1052_Y - attribute \src "ls180.v:5640.50-5640.105" - wire width 32 $add$ls180.v:5640$1061_Y - attribute \src "ls180.v:5642.77-5642.111" - wire width 32 $add$ls180.v:5642$1062_Y - attribute \src "ls180.v:7589.36-7589.70" - wire width 32 $add$ls180.v:7589$2472_Y - attribute \src "ls180.v:7686.37-7686.72" - wire width 4 $add$ls180.v:7686$2502_Y - attribute \src "ls180.v:7703.60-7703.119" - wire width 3 $add$ls180.v:7703$2506_Y - attribute \src "ls180.v:7706.60-7706.119" - wire width 3 $add$ls180.v:7706$2507_Y - attribute \src "ls180.v:7710.59-7710.116" - wire width 4 $add$ls180.v:7710$2512_Y - attribute \src "ls180.v:7749.60-7749.119" - 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"ls180.v:4088.220-4088.253" + wire $eq$ls180.v:4088$519_Y + attribute \src "ls180.v:4088.295-4088.328" + wire $eq$ls180.v:4088$522_Y + attribute \src "ls180.v:4093.42-4093.82" + wire $eq$ls180.v:4093$531_Y + attribute \src "ls180.v:4093.145-4093.178" + wire $eq$ls180.v:4093$532_Y + attribute \src "ls180.v:4093.220-4093.253" + wire $eq$ls180.v:4093$535_Y + attribute \src "ls180.v:4093.295-4093.328" + wire $eq$ls180.v:4093$538_Y + attribute \src "ls180.v:4098.42-4098.82" + wire $eq$ls180.v:4098$547_Y + attribute \src "ls180.v:4098.145-4098.178" + wire $eq$ls180.v:4098$548_Y + attribute \src "ls180.v:4098.220-4098.253" + wire $eq$ls180.v:4098$551_Y + attribute \src "ls180.v:4098.295-4098.328" + wire $eq$ls180.v:4098$554_Y + attribute \src "ls180.v:4103.42-4103.82" + wire $eq$ls180.v:4103$563_Y + attribute \src "ls180.v:4103.145-4103.178" + wire $eq$ls180.v:4103$564_Y + attribute \src "ls180.v:4103.220-4103.253" + wire $eq$ls180.v:4103$567_Y + attribute \src "ls180.v:4103.295-4103.328" + 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"ls180.v:4401.35-4401.102" + wire $eq$ls180.v:4401$730_Y + attribute \src "ls180.v:4429.10-4429.65" + wire $eq$ls180.v:4429$734_Y + attribute \src "ls180.v:4533.10-4533.40" + wire $eq$ls180.v:4533$761_Y + attribute \src "ls180.v:4590.10-4590.39" + wire $eq$ls180.v:4590$764_Y + attribute \src "ls180.v:4607.10-4607.39" + wire $eq$ls180.v:4607$766_Y + attribute \src "ls180.v:4635.38-4635.88" + wire $eq$ls180.v:4635$768_Y + attribute \src "ls180.v:4685.9-4685.40" + wire $eq$ls180.v:4685$778_Y + attribute \src "ls180.v:4694.36-4694.105" + wire $eq$ls180.v:4694$780_Y + attribute \src "ls180.v:4713.9-4713.40" + wire $eq$ls180.v:4713$784_Y + attribute \src "ls180.v:4725.10-4725.39" + wire $eq$ls180.v:4725$786_Y + attribute \src "ls180.v:4762.39-4762.94" + wire $eq$ls180.v:4762$790_Y + attribute \src "ls180.v:4799.32-4799.89" + wire $eq$ls180.v:4799$799_Y + attribute \src "ls180.v:4847.10-4847.40" + wire $eq$ls180.v:4847$803_Y + attribute \src "ls180.v:4896.40-4896.98" + wire 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"ls180.v:5257.7-5257.44" + wire $eq$ls180.v:5257$1029_Y + attribute \src "ls180.v:5381.36-5381.64" + wire $eq$ls180.v:5381$1080_Y + attribute \src "ls180.v:5387.10-5387.39" + wire $eq$ls180.v:5387$1083_Y + attribute \src "ls180.v:5388.11-5388.39" + wire $eq$ls180.v:5388$1084_Y + attribute \src "ls180.v:5400.34-5400.63" + wire $eq$ls180.v:5400$1085_Y + attribute \src "ls180.v:5401.9-5401.37" + wire $eq$ls180.v:5401$1086_Y + attribute \src "ls180.v:5408.10-5408.55" + wire $eq$ls180.v:5408$1087_Y + attribute \src "ls180.v:5414.12-5414.41" + wire $eq$ls180.v:5414$1088_Y + attribute \src "ls180.v:5417.13-5417.42" + wire $eq$ls180.v:5417$1089_Y + attribute \src "ls180.v:5439.10-5439.76" + wire $eq$ls180.v:5439$1094_Y + attribute \src "ls180.v:5454.35-5454.101" + wire $eq$ls180.v:5454$1097_Y + attribute \src "ls180.v:5456.10-5456.56" + wire $eq$ls180.v:5456$1098_Y + attribute \src "ls180.v:5465.12-5465.78" + wire $eq$ls180.v:5465$1102_Y + attribute \src "ls180.v:5472.11-5472.57" + wire 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attribute \src "ls180.v:8758.9-8758.49" + wire $eq$ls180.v:8758$2796_Y + attribute \src "ls180.v:8334.8-8334.54" + wire $ge$ls180.v:8334$2731_Y + attribute \src "ls180.v:8348.8-8348.54" + wire $ge$ls180.v:8348$2735_Y + attribute \src "ls180.v:5266.47-5266.83" + wire $gt$ls180.v:5266$1031_Y + attribute \src "ls180.v:5272.7-5272.43" + wire $lt$ls180.v:5272$1034_Y + attribute \src "ls180.v:8329.8-8329.43" + wire $lt$ls180.v:8329$2729_Y + attribute \src "ls180.v:8343.8-8343.43" + wire $lt$ls180.v:8343$2733_Y + attribute \src "ls180.v:10247.33-10247.36" + wire width 64 $memrd$\mem$ls180.v:10247$2850_DATA + attribute \src "ls180.v:10275.27-10275.32" + wire width 64 $memrd$\mem_1$ls180.v:10275$2876_DATA + attribute \src "ls180.v:10303.27-10303.32" + wire width 64 $memrd$\mem_2$ls180.v:10303$2902_DATA + attribute \src "ls180.v:10331.27-10331.32" + wire width 64 $memrd$\mem_3$ls180.v:10331$2928_DATA + attribute \src "ls180.v:10342.12-10342.19" + wire width 25 $memrd$\storage$ls180.v:10342$2933_DATA + attribute \src "ls180.v:10349.68-10349.75" + wire width 25 $memrd$\storage$ls180.v:10349$2935_DATA + attribute \src "ls180.v:10356.14-10356.23" + wire width 25 $memrd$\storage_1$ls180.v:10356$2940_DATA + attribute \src "ls180.v:10363.68-10363.77" + wire width 25 $memrd$\storage_1$ls180.v:10363$2942_DATA + attribute \src "ls180.v:10370.14-10370.23" + wire width 25 $memrd$\storage_2$ls180.v:10370$2947_DATA + attribute \src "ls180.v:10377.68-10377.77" + wire width 25 $memrd$\storage_2$ls180.v:10377$2949_DATA + attribute \src "ls180.v:10384.14-10384.23" + wire width 25 $memrd$\storage_3$ls180.v:10384$2954_DATA + attribute \src "ls180.v:10391.68-10391.77" + wire width 25 $memrd$\storage_3$ls180.v:10391$2956_DATA + attribute \src "ls180.v:10399.14-10399.23" + wire width 10 $memrd$\storage_4$ls180.v:10399$2961_DATA + attribute \src "ls180.v:10404.15-10404.24" + wire width 10 $memrd$\storage_4$ls180.v:10404$2963_DATA + attribute \src "ls180.v:10416.14-10416.23" + wire width 10 $memrd$\storage_5$ls180.v:10416$2968_DATA + attribute \src "ls180.v:10421.15-10421.24" + wire width 10 $memrd$\storage_5$ls180.v:10421$2970_DATA + attribute \src "ls180.v:10432.14-10432.23" + wire width 10 $memrd$\storage_6$ls180.v:10432$2975_DATA + attribute \src "ls180.v:10439.45-10439.54" + wire width 10 $memrd$\storage_6$ls180.v:10439$2977_DATA + attribute \src "ls180.v:10446.14-10446.23" + wire width 10 $memrd$\storage_7$ls180.v:10446$2982_DATA + attribute \src "ls180.v:10453.45-10453.54" + wire width 10 $memrd$\storage_7$ls180.v:10453$2984_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem$ls180.v:10229$1_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem$ls180.v:10229$1_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem$ls180.v:10229$1_EN + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem$ls180.v:10231$2_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem$ls180.v:10231$2_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem$ls180.v:10231$2_EN + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem$ls180.v:10233$3_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem$ls180.v:10233$3_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem$ls180.v:10233$3_EN + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem$ls180.v:10235$4_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem$ls180.v:10235$4_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem$ls180.v:10235$4_EN attribute \src "ls180.v:0.0-0.0" - wire width 7 $memwr$\mem$ls180.v:10162$1_ADDR + wire width 6 $memwr$\mem$ls180.v:10237$5_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 32 $memwr$\mem$ls180.v:10162$1_DATA + wire width 64 $memwr$\mem$ls180.v:10237$5_DATA attribute \src "ls180.v:0.0-0.0" - wire width 32 $memwr$\mem$ls180.v:10162$1_EN + wire width 64 $memwr$\mem$ls180.v:10237$5_EN attribute \src "ls180.v:0.0-0.0" - wire width 7 $memwr$\mem$ls180.v:10164$2_ADDR + wire width 6 $memwr$\mem$ls180.v:10239$6_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 32 $memwr$\mem$ls180.v:10164$2_DATA + wire width 64 $memwr$\mem$ls180.v:10239$6_DATA attribute \src "ls180.v:0.0-0.0" - wire width 32 $memwr$\mem$ls180.v:10164$2_EN + wire width 64 $memwr$\mem$ls180.v:10239$6_EN attribute \src "ls180.v:0.0-0.0" - wire width 7 $memwr$\mem$ls180.v:10166$3_ADDR + wire width 6 $memwr$\mem$ls180.v:10241$7_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 32 $memwr$\mem$ls180.v:10166$3_DATA + wire width 64 $memwr$\mem$ls180.v:10241$7_DATA attribute \src "ls180.v:0.0-0.0" - wire width 32 $memwr$\mem$ls180.v:10166$3_EN + wire width 64 $memwr$\mem$ls180.v:10241$7_EN attribute \src "ls180.v:0.0-0.0" - wire width 7 $memwr$\mem$ls180.v:10168$4_ADDR + wire width 6 $memwr$\mem$ls180.v:10243$8_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 32 $memwr$\mem$ls180.v:10168$4_DATA + wire width 64 $memwr$\mem$ls180.v:10243$8_DATA attribute \src "ls180.v:0.0-0.0" - wire width 32 $memwr$\mem$ls180.v:10168$4_EN + wire width 64 $memwr$\mem$ls180.v:10243$8_EN attribute \src "ls180.v:0.0-0.0" - wire width 7 $memwr$\mem_1$ls180.v:10182$5_ADDR + wire width 6 $memwr$\mem_1$ls180.v:10257$9_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 32 $memwr$\mem_1$ls180.v:10182$5_DATA + wire width 64 $memwr$\mem_1$ls180.v:10257$9_DATA attribute \src "ls180.v:0.0-0.0" - wire width 32 $memwr$\mem_1$ls180.v:10182$5_EN + wire width 64 $memwr$\mem_1$ls180.v:10257$9_EN attribute \src "ls180.v:0.0-0.0" - wire width 7 $memwr$\mem_1$ls180.v:10184$6_ADDR + wire width 6 $memwr$\mem_1$ls180.v:10259$10_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 32 $memwr$\mem_1$ls180.v:10184$6_DATA + wire width 64 $memwr$\mem_1$ls180.v:10259$10_DATA attribute \src "ls180.v:0.0-0.0" - wire width 32 $memwr$\mem_1$ls180.v:10184$6_EN + wire width 64 $memwr$\mem_1$ls180.v:10259$10_EN attribute \src "ls180.v:0.0-0.0" - wire width 7 $memwr$\mem_1$ls180.v:10186$7_ADDR + wire width 6 $memwr$\mem_1$ls180.v:10261$11_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 32 $memwr$\mem_1$ls180.v:10186$7_DATA + wire width 64 $memwr$\mem_1$ls180.v:10261$11_DATA attribute \src "ls180.v:0.0-0.0" - wire width 32 $memwr$\mem_1$ls180.v:10186$7_EN + wire width 64 $memwr$\mem_1$ls180.v:10261$11_EN attribute \src "ls180.v:0.0-0.0" - wire width 7 $memwr$\mem_1$ls180.v:10188$8_ADDR + wire width 6 $memwr$\mem_1$ls180.v:10263$12_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 32 $memwr$\mem_1$ls180.v:10188$8_DATA + wire width 64 $memwr$\mem_1$ls180.v:10263$12_DATA attribute \src "ls180.v:0.0-0.0" - wire width 32 $memwr$\mem_1$ls180.v:10188$8_EN + wire width 64 $memwr$\mem_1$ls180.v:10263$12_EN attribute \src "ls180.v:0.0-0.0" - wire width 7 $memwr$\mem_2$ls180.v:10202$9_ADDR + wire width 6 $memwr$\mem_1$ls180.v:10265$13_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 32 $memwr$\mem_2$ls180.v:10202$9_DATA + wire width 64 $memwr$\mem_1$ls180.v:10265$13_DATA attribute \src "ls180.v:0.0-0.0" - wire width 32 $memwr$\mem_2$ls180.v:10202$9_EN + wire width 64 $memwr$\mem_1$ls180.v:10265$13_EN attribute \src "ls180.v:0.0-0.0" - wire width 7 $memwr$\mem_2$ls180.v:10204$10_ADDR + wire width 6 $memwr$\mem_1$ls180.v:10267$14_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 32 $memwr$\mem_2$ls180.v:10204$10_DATA + wire width 64 $memwr$\mem_1$ls180.v:10267$14_DATA attribute \src "ls180.v:0.0-0.0" - wire width 32 $memwr$\mem_2$ls180.v:10204$10_EN + wire width 64 $memwr$\mem_1$ls180.v:10267$14_EN attribute \src "ls180.v:0.0-0.0" - wire width 7 $memwr$\mem_2$ls180.v:10206$11_ADDR + wire width 6 $memwr$\mem_1$ls180.v:10269$15_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 32 $memwr$\mem_2$ls180.v:10206$11_DATA + wire width 64 $memwr$\mem_1$ls180.v:10269$15_DATA attribute \src "ls180.v:0.0-0.0" - wire width 32 $memwr$\mem_2$ls180.v:10206$11_EN + wire width 64 $memwr$\mem_1$ls180.v:10269$15_EN attribute \src "ls180.v:0.0-0.0" - wire width 7 $memwr$\mem_2$ls180.v:10208$12_ADDR + wire width 6 $memwr$\mem_1$ls180.v:10271$16_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 32 $memwr$\mem_2$ls180.v:10208$12_DATA + wire width 64 $memwr$\mem_1$ls180.v:10271$16_DATA attribute \src "ls180.v:0.0-0.0" - wire width 32 $memwr$\mem_2$ls180.v:10208$12_EN + wire width 64 $memwr$\mem_1$ls180.v:10271$16_EN attribute \src "ls180.v:0.0-0.0" - wire width 7 $memwr$\mem_3$ls180.v:10222$13_ADDR + wire width 6 $memwr$\mem_2$ls180.v:10285$17_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 32 $memwr$\mem_3$ls180.v:10222$13_DATA + wire width 64 $memwr$\mem_2$ls180.v:10285$17_DATA attribute \src "ls180.v:0.0-0.0" - wire width 32 $memwr$\mem_3$ls180.v:10222$13_EN + wire width 64 $memwr$\mem_2$ls180.v:10285$17_EN attribute \src "ls180.v:0.0-0.0" - wire width 7 $memwr$\mem_3$ls180.v:10224$14_ADDR + wire width 6 $memwr$\mem_2$ls180.v:10287$18_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 32 $memwr$\mem_3$ls180.v:10224$14_DATA + wire width 64 $memwr$\mem_2$ls180.v:10287$18_DATA attribute \src "ls180.v:0.0-0.0" - wire width 32 $memwr$\mem_3$ls180.v:10224$14_EN + wire width 64 $memwr$\mem_2$ls180.v:10287$18_EN attribute \src "ls180.v:0.0-0.0" - wire width 7 $memwr$\mem_3$ls180.v:10226$15_ADDR + wire width 6 $memwr$\mem_2$ls180.v:10289$19_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 32 $memwr$\mem_3$ls180.v:10226$15_DATA + wire width 64 $memwr$\mem_2$ls180.v:10289$19_DATA attribute \src "ls180.v:0.0-0.0" - wire width 32 $memwr$\mem_3$ls180.v:10226$15_EN + wire width 64 $memwr$\mem_2$ls180.v:10289$19_EN attribute \src "ls180.v:0.0-0.0" - wire width 7 $memwr$\mem_3$ls180.v:10228$16_ADDR + wire width 6 $memwr$\mem_2$ls180.v:10291$20_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 32 $memwr$\mem_3$ls180.v:10228$16_DATA + wire width 64 $memwr$\mem_2$ls180.v:10291$20_DATA attribute \src "ls180.v:0.0-0.0" - wire width 32 $memwr$\mem_3$ls180.v:10228$16_EN + wire width 64 $memwr$\mem_2$ls180.v:10291$20_EN attribute \src "ls180.v:0.0-0.0" - wire width 3 $memwr$\storage$ls180.v:10242$17_ADDR + wire width 6 $memwr$\mem_2$ls180.v:10293$21_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 25 $memwr$\storage$ls180.v:10242$17_DATA + wire width 64 $memwr$\mem_2$ls180.v:10293$21_DATA attribute \src "ls180.v:0.0-0.0" - wire width 25 $memwr$\storage$ls180.v:10242$17_EN + wire width 64 $memwr$\mem_2$ls180.v:10293$21_EN attribute \src "ls180.v:0.0-0.0" - wire width 3 $memwr$\storage_1$ls180.v:10256$18_ADDR + wire width 6 $memwr$\mem_2$ls180.v:10295$22_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 25 $memwr$\storage_1$ls180.v:10256$18_DATA + wire width 64 $memwr$\mem_2$ls180.v:10295$22_DATA attribute \src "ls180.v:0.0-0.0" - wire width 25 $memwr$\storage_1$ls180.v:10256$18_EN + wire width 64 $memwr$\mem_2$ls180.v:10295$22_EN attribute \src "ls180.v:0.0-0.0" - wire width 3 $memwr$\storage_2$ls180.v:10270$19_ADDR + wire width 6 $memwr$\mem_2$ls180.v:10297$23_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 25 $memwr$\storage_2$ls180.v:10270$19_DATA + wire width 64 $memwr$\mem_2$ls180.v:10297$23_DATA attribute \src "ls180.v:0.0-0.0" - wire width 25 $memwr$\storage_2$ls180.v:10270$19_EN + wire width 64 $memwr$\mem_2$ls180.v:10297$23_EN attribute \src "ls180.v:0.0-0.0" - wire width 3 $memwr$\storage_3$ls180.v:10284$20_ADDR + wire width 6 $memwr$\mem_2$ls180.v:10299$24_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 25 $memwr$\storage_3$ls180.v:10284$20_DATA + wire width 64 $memwr$\mem_2$ls180.v:10299$24_DATA attribute \src "ls180.v:0.0-0.0" - wire width 25 $memwr$\storage_3$ls180.v:10284$20_EN + wire width 64 $memwr$\mem_2$ls180.v:10299$24_EN attribute \src "ls180.v:0.0-0.0" - wire width 4 $memwr$\storage_4$ls180.v:10299$21_ADDR + wire width 6 $memwr$\mem_3$ls180.v:10313$25_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 10 $memwr$\storage_4$ls180.v:10299$21_DATA + wire width 64 $memwr$\mem_3$ls180.v:10313$25_DATA attribute \src "ls180.v:0.0-0.0" - wire width 10 $memwr$\storage_4$ls180.v:10299$21_EN + wire width 64 $memwr$\mem_3$ls180.v:10313$25_EN attribute \src "ls180.v:0.0-0.0" - wire width 4 $memwr$\storage_5$ls180.v:10316$22_ADDR + wire width 6 $memwr$\mem_3$ls180.v:10315$26_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 10 $memwr$\storage_5$ls180.v:10316$22_DATA + wire width 64 $memwr$\mem_3$ls180.v:10315$26_DATA attribute \src "ls180.v:0.0-0.0" - wire width 10 $memwr$\storage_5$ls180.v:10316$22_EN + wire width 64 $memwr$\mem_3$ls180.v:10315$26_EN attribute \src "ls180.v:0.0-0.0" - wire width 5 $memwr$\storage_6$ls180.v:10332$23_ADDR + wire width 6 $memwr$\mem_3$ls180.v:10317$27_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 10 $memwr$\storage_6$ls180.v:10332$23_DATA + wire width 64 $memwr$\mem_3$ls180.v:10317$27_DATA attribute \src "ls180.v:0.0-0.0" - wire width 10 $memwr$\storage_6$ls180.v:10332$23_EN + wire width 64 $memwr$\mem_3$ls180.v:10317$27_EN attribute \src "ls180.v:0.0-0.0" - wire width 5 $memwr$\storage_7$ls180.v:10346$24_ADDR + wire width 6 $memwr$\mem_3$ls180.v:10319$28_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 10 $memwr$\storage_7$ls180.v:10346$24_DATA + wire width 64 $memwr$\mem_3$ls180.v:10319$28_DATA attribute \src "ls180.v:0.0-0.0" - wire width 10 $memwr$\storage_7$ls180.v:10346$24_EN - attribute \src "ls180.v:3010.41-3010.71" - wire $ne$ls180.v:3010$72_Y - attribute \src "ls180.v:3201.70-3201.104" - wire $ne$ls180.v:3201$125_Y - attribute \src "ls180.v:3262.8-3262.142" - wire $ne$ls180.v:3262$144_Y - attribute \src "ls180.v:3294.75-3294.133" - wire $ne$ls180.v:3294$151_Y - attribute \src "ls180.v:3295.75-3295.133" - wire $ne$ls180.v:3295$152_Y - attribute \src "ls180.v:3419.8-3419.142" - wire $ne$ls180.v:3419$174_Y - attribute \src "ls180.v:3451.75-3451.133" - wire $ne$ls180.v:3451$181_Y - attribute \src "ls180.v:3452.75-3452.133" - wire $ne$ls180.v:3452$182_Y - attribute \src "ls180.v:3576.8-3576.142" - wire $ne$ls180.v:3576$204_Y - attribute \src "ls180.v:3608.75-3608.133" - wire $ne$ls180.v:3608$211_Y - attribute \src "ls180.v:3609.75-3609.133" - wire $ne$ls180.v:3609$212_Y - attribute \src "ls180.v:3733.8-3733.142" - wire $ne$ls180.v:3733$234_Y - attribute \src "ls180.v:3765.75-3765.133" - wire $ne$ls180.v:3765$241_Y - attribute \src "ls180.v:3766.75-3766.133" - wire $ne$ls180.v:3766$242_Y - attribute \src "ls180.v:4258.47-4258.80" - wire $ne$ls180.v:4258$640_Y - attribute \src "ls180.v:4259.47-4259.79" - wire $ne$ls180.v:4259$641_Y - attribute \src "ls180.v:4288.47-4288.80" - wire $ne$ls180.v:4288$651_Y - attribute \src "ls180.v:4289.47-4289.79" - wire $ne$ls180.v:4289$652_Y - attribute \src "ls180.v:4758.32-4758.89" - wire $ne$ls180.v:4758$732_Y - attribute \src "ls180.v:5405.10-5405.56" - wire $ne$ls180.v:5405$1029_Y - attribute \src "ls180.v:5510.51-5510.87" - wire $ne$ls180.v:5510$1043_Y - attribute \src "ls180.v:5511.51-5511.86" - wire $ne$ls180.v:5511$1044_Y - attribute \src "ls180.v:5718.51-5718.87" - wire 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$xor$ls180.v:5018$825_Y - attribute \src "ls180.v:5018.164-5018.279" - wire $xor$ls180.v:5018$826_Y - attribute \src "ls180.v:5019.361-5019.434" - wire $xor$ls180.v:5019$827_Y - attribute \src "ls180.v:5019.205-5019.278" - wire $xor$ls180.v:5019$828_Y - attribute \src "ls180.v:5019.164-5019.279" - wire $xor$ls180.v:5019$829_Y - attribute \src "ls180.v:5020.361-5020.434" - wire $xor$ls180.v:5020$830_Y - attribute \src "ls180.v:5020.205-5020.278" - wire $xor$ls180.v:5020$831_Y - attribute \src "ls180.v:5020.164-5020.279" - wire $xor$ls180.v:5020$832_Y - attribute \src "ls180.v:5021.361-5021.434" - wire $xor$ls180.v:5021$833_Y - attribute \src "ls180.v:5021.205-5021.278" - wire $xor$ls180.v:5021$834_Y - attribute \src "ls180.v:5021.164-5021.279" - wire $xor$ls180.v:5021$835_Y - attribute \src "ls180.v:5022.361-5022.434" - wire $xor$ls180.v:5022$836_Y - attribute \src "ls180.v:5022.205-5022.278" - wire $xor$ls180.v:5022$837_Y - attribute \src "ls180.v:5022.164-5022.279" - wire $xor$ls180.v:5022$838_Y - attribute \src "ls180.v:5023.361-5023.434" - wire $xor$ls180.v:5023$839_Y - attribute \src "ls180.v:5023.205-5023.278" - wire $xor$ls180.v:5023$840_Y - attribute \src "ls180.v:5023.164-5023.279" - wire $xor$ls180.v:5023$841_Y - attribute \src "ls180.v:5024.361-5024.434" - wire $xor$ls180.v:5024$842_Y - attribute \src "ls180.v:5024.205-5024.278" - wire $xor$ls180.v:5024$843_Y - attribute \src "ls180.v:5024.164-5024.279" - wire $xor$ls180.v:5024$844_Y - attribute \src "ls180.v:5025.361-5025.434" - wire $xor$ls180.v:5025$845_Y - attribute \src "ls180.v:5025.205-5025.278" - wire $xor$ls180.v:5025$846_Y - attribute \src "ls180.v:5025.164-5025.279" - wire $xor$ls180.v:5025$847_Y - attribute \src "ls180.v:5026.361-5026.434" - wire $xor$ls180.v:5026$848_Y - attribute \src "ls180.v:5026.205-5026.278" - wire $xor$ls180.v:5026$849_Y - attribute \src "ls180.v:5026.164-5026.279" - wire $xor$ls180.v:5026$850_Y - attribute \src "ls180.v:5027.360-5027.432" - wire $xor$ls180.v:5027$851_Y - attribute \src "ls180.v:5027.205-5027.277" - wire $xor$ls180.v:5027$852_Y - attribute \src "ls180.v:5027.164-5027.278" - wire $xor$ls180.v:5027$853_Y - attribute \src "ls180.v:5028.360-5028.432" - wire $xor$ls180.v:5028$854_Y - attribute \src "ls180.v:5028.205-5028.277" - wire $xor$ls180.v:5028$855_Y - attribute \src "ls180.v:5028.164-5028.278" - wire $xor$ls180.v:5028$856_Y - attribute \src "ls180.v:5029.360-5029.432" - wire $xor$ls180.v:5029$857_Y - attribute \src "ls180.v:5029.205-5029.277" - wire $xor$ls180.v:5029$858_Y - attribute \src "ls180.v:5029.164-5029.278" - wire $xor$ls180.v:5029$859_Y - attribute \src "ls180.v:5030.360-5030.432" - wire $xor$ls180.v:5030$860_Y - attribute \src "ls180.v:5030.205-5030.277" - wire $xor$ls180.v:5030$861_Y - attribute \src "ls180.v:5030.164-5030.278" - wire $xor$ls180.v:5030$862_Y - attribute \src "ls180.v:5031.360-5031.432" - wire $xor$ls180.v:5031$863_Y - attribute \src "ls180.v:5031.205-5031.277" - wire $xor$ls180.v:5031$864_Y - attribute \src "ls180.v:5031.164-5031.278" - wire $xor$ls180.v:5031$865_Y - attribute \src "ls180.v:5032.360-5032.432" - wire $xor$ls180.v:5032$866_Y - attribute \src "ls180.v:5032.205-5032.277" - wire $xor$ls180.v:5032$867_Y - attribute \src "ls180.v:5032.164-5032.278" - wire $xor$ls180.v:5032$868_Y - attribute \src "ls180.v:5033.360-5033.432" - wire $xor$ls180.v:5033$869_Y - attribute \src "ls180.v:5033.205-5033.277" - wire $xor$ls180.v:5033$870_Y - attribute \src "ls180.v:5033.164-5033.278" - wire $xor$ls180.v:5033$871_Y - attribute \src "ls180.v:5034.360-5034.432" - wire $xor$ls180.v:5034$872_Y - attribute \src "ls180.v:5034.205-5034.277" - wire $xor$ls180.v:5034$873_Y - attribute \src "ls180.v:5034.164-5034.278" - wire $xor$ls180.v:5034$874_Y - attribute \src "ls180.v:5035.360-5035.432" - wire $xor$ls180.v:5035$875_Y - attribute \src "ls180.v:5035.205-5035.277" - wire $xor$ls180.v:5035$876_Y - attribute \src "ls180.v:5035.164-5035.278" - wire $xor$ls180.v:5035$877_Y - attribute \src "ls180.v:5036.360-5036.432" - wire $xor$ls180.v:5036$878_Y - attribute \src "ls180.v:5036.205-5036.277" - wire $xor$ls180.v:5036$879_Y - attribute \src "ls180.v:5036.164-5036.278" - wire $xor$ls180.v:5036$880_Y - attribute \src "ls180.v:5057.899-5057.983" - wire $xor$ls180.v:5057$894_Y - attribute \src "ls180.v:5057.634-5057.718" - wire $xor$ls180.v:5057$895_Y - attribute \src "ls180.v:5057.588-5057.719" - wire $xor$ls180.v:5057$896_Y - attribute \src "ls180.v:5057.234-5057.318" - wire $xor$ls180.v:5057$897_Y - attribute \src "ls180.v:5057.187-5057.319" - wire $xor$ls180.v:5057$898_Y - attribute \src "ls180.v:5058.899-5058.983" - wire $xor$ls180.v:5058$899_Y - attribute \src "ls180.v:5058.634-5058.718" - wire $xor$ls180.v:5058$900_Y - attribute \src "ls180.v:5058.588-5058.719" - wire $xor$ls180.v:5058$901_Y - attribute \src "ls180.v:5058.234-5058.318" - wire $xor$ls180.v:5058$902_Y - attribute \src "ls180.v:5058.187-5058.319" - wire $xor$ls180.v:5058$903_Y - attribute \src "ls180.v:5067.899-5067.983" - wire $xor$ls180.v:5067$905_Y - attribute \src "ls180.v:5067.634-5067.718" - wire $xor$ls180.v:5067$906_Y - attribute \src "ls180.v:5067.588-5067.719" - wire $xor$ls180.v:5067$907_Y - attribute \src "ls180.v:5067.234-5067.318" - wire $xor$ls180.v:5067$908_Y - attribute \src "ls180.v:5067.187-5067.319" - wire $xor$ls180.v:5067$909_Y - attribute \src "ls180.v:5068.899-5068.983" - wire $xor$ls180.v:5068$910_Y - attribute \src "ls180.v:5068.634-5068.718" - wire $xor$ls180.v:5068$911_Y - attribute \src "ls180.v:5068.588-5068.719" - wire $xor$ls180.v:5068$912_Y - attribute \src "ls180.v:5068.234-5068.318" - wire $xor$ls180.v:5068$913_Y - attribute \src "ls180.v:5068.187-5068.319" - wire $xor$ls180.v:5068$914_Y - attribute \src "ls180.v:5077.899-5077.983" - wire $xor$ls180.v:5077$916_Y - attribute \src "ls180.v:5077.634-5077.718" - wire $xor$ls180.v:5077$917_Y - attribute \src "ls180.v:5077.588-5077.719" - wire $xor$ls180.v:5077$918_Y - attribute \src "ls180.v:5077.234-5077.318" - wire $xor$ls180.v:5077$919_Y - attribute \src "ls180.v:5077.187-5077.319" - wire $xor$ls180.v:5077$920_Y - attribute \src "ls180.v:5078.899-5078.983" - wire $xor$ls180.v:5078$921_Y - attribute \src "ls180.v:5078.634-5078.718" - wire $xor$ls180.v:5078$922_Y - attribute \src "ls180.v:5078.588-5078.719" - wire $xor$ls180.v:5078$923_Y - attribute \src "ls180.v:5078.234-5078.318" - wire $xor$ls180.v:5078$924_Y - attribute \src "ls180.v:5078.187-5078.319" - wire $xor$ls180.v:5078$925_Y - attribute \src "ls180.v:5087.899-5087.983" - wire $xor$ls180.v:5087$927_Y - attribute \src "ls180.v:5087.634-5087.718" - wire $xor$ls180.v:5087$928_Y - attribute \src "ls180.v:5087.588-5087.719" - wire $xor$ls180.v:5087$929_Y - attribute \src "ls180.v:5087.234-5087.318" - wire $xor$ls180.v:5087$930_Y - attribute \src "ls180.v:5087.187-5087.319" - wire $xor$ls180.v:5087$931_Y - attribute \src "ls180.v:5088.899-5088.983" - wire $xor$ls180.v:5088$932_Y - attribute \src "ls180.v:5088.634-5088.718" - wire $xor$ls180.v:5088$933_Y - attribute \src "ls180.v:5088.588-5088.719" - wire $xor$ls180.v:5088$934_Y - attribute \src "ls180.v:5088.234-5088.318" - wire $xor$ls180.v:5088$935_Y - attribute \src "ls180.v:5088.187-5088.319" - wire $xor$ls180.v:5088$936_Y - attribute \src "ls180.v:5239.879-5239.961" - wire $xor$ls180.v:5239$969_Y - attribute \src "ls180.v:5239.620-5239.702" - wire $xor$ls180.v:5239$970_Y - attribute \src "ls180.v:5239.575-5239.703" - wire $xor$ls180.v:5239$971_Y - attribute \src "ls180.v:5239.229-5239.311" - wire $xor$ls180.v:5239$972_Y - attribute \src "ls180.v:5239.183-5239.312" - wire $xor$ls180.v:5239$973_Y - attribute \src "ls180.v:5240.879-5240.961" - wire $xor$ls180.v:5240$974_Y - attribute \src "ls180.v:5240.620-5240.702" - wire $xor$ls180.v:5240$975_Y - attribute \src "ls180.v:5240.575-5240.703" - wire $xor$ls180.v:5240$976_Y - attribute \src "ls180.v:5240.229-5240.311" - wire $xor$ls180.v:5240$977_Y - attribute \src "ls180.v:5240.183-5240.312" - wire $xor$ls180.v:5240$978_Y - attribute \src "ls180.v:5249.879-5249.961" - wire $xor$ls180.v:5249$980_Y - attribute \src "ls180.v:5249.620-5249.702" - wire $xor$ls180.v:5249$981_Y - attribute \src "ls180.v:5249.575-5249.703" - wire $xor$ls180.v:5249$982_Y - attribute \src "ls180.v:5249.229-5249.311" - wire $xor$ls180.v:5249$983_Y - attribute \src "ls180.v:5249.183-5249.312" - wire $xor$ls180.v:5249$984_Y - attribute \src "ls180.v:5250.879-5250.961" - wire $xor$ls180.v:5250$985_Y - attribute \src "ls180.v:5250.620-5250.702" - wire $xor$ls180.v:5250$986_Y - attribute \src "ls180.v:5250.575-5250.703" - wire $xor$ls180.v:5250$987_Y - attribute \src "ls180.v:5250.229-5250.311" - wire $xor$ls180.v:5250$988_Y - attribute \src "ls180.v:5250.183-5250.312" - wire $xor$ls180.v:5250$989_Y - attribute \src "ls180.v:5259.879-5259.961" - wire $xor$ls180.v:5259$991_Y - attribute \src "ls180.v:5259.620-5259.702" - wire $xor$ls180.v:5259$992_Y - attribute \src "ls180.v:5259.575-5259.703" - wire $xor$ls180.v:5259$993_Y - attribute \src "ls180.v:5259.229-5259.311" - wire $xor$ls180.v:5259$994_Y - attribute \src "ls180.v:5259.183-5259.312" - wire $xor$ls180.v:5259$995_Y - attribute \src "ls180.v:5260.183-5260.312" - wire $xor$ls180.v:5260$1000_Y - attribute \src "ls180.v:5260.879-5260.961" - wire $xor$ls180.v:5260$996_Y - attribute \src "ls180.v:5260.620-5260.702" - wire $xor$ls180.v:5260$997_Y - attribute \src "ls180.v:5260.575-5260.703" - wire $xor$ls180.v:5260$998_Y - attribute \src "ls180.v:5260.229-5260.311" - wire $xor$ls180.v:5260$999_Y - attribute \src "ls180.v:5269.879-5269.961" - wire $xor$ls180.v:5269$1002_Y - attribute \src "ls180.v:5269.620-5269.702" - wire $xor$ls180.v:5269$1003_Y - attribute \src "ls180.v:5269.575-5269.703" - wire $xor$ls180.v:5269$1004_Y - attribute \src "ls180.v:5269.229-5269.311" - wire $xor$ls180.v:5269$1005_Y - attribute \src "ls180.v:5269.183-5269.312" - wire $xor$ls180.v:5269$1006_Y - attribute \src "ls180.v:5270.879-5270.961" - wire $xor$ls180.v:5270$1007_Y - attribute \src "ls180.v:5270.620-5270.702" - wire $xor$ls180.v:5270$1008_Y - attribute \src "ls180.v:5270.575-5270.703" - wire $xor$ls180.v:5270$1009_Y - attribute \src "ls180.v:5270.229-5270.311" - wire $xor$ls180.v:5270$1010_Y - attribute \src "ls180.v:5270.183-5270.312" - wire $xor$ls180.v:5270$1011_Y - attribute \src "ls180.v:1790.11-1790.42" + wire $not$ls180.v:6302$1872_Y + attribute \src "ls180.v:6305.68-6305.99" + wire $not$ls180.v:6305$1879_Y + attribute \src "ls180.v:6308.68-6308.99" + wire $not$ls180.v:6308$1886_Y + attribute \src "ls180.v:6311.68-6311.99" + wire $not$ls180.v:6311$1893_Y + attribute \src "ls180.v:6314.65-6314.96" + wire $not$ls180.v:6314$1900_Y + attribute \src "ls180.v:6317.66-6317.97" + wire $not$ls180.v:6317$1907_Y + attribute \src "ls180.v:6320.68-6320.99" + wire $not$ls180.v:6320$1914_Y + attribute \src "ls180.v:6323.68-6323.99" + wire $not$ls180.v:6323$1921_Y + attribute \src "ls180.v:6326.68-6326.99" + wire $not$ls180.v:6326$1928_Y + attribute \src "ls180.v:6329.68-6329.99" + wire $not$ls180.v:6329$1935_Y + attribute \src "ls180.v:6354.68-6354.99" + wire $not$ls180.v:6354$1943_Y + attribute \src "ls180.v:6357.73-6357.104" + wire $not$ls180.v:6357$1950_Y + attribute \src "ls180.v:6360.73-6360.104" + wire $not$ls180.v:6360$1957_Y + attribute \src "ls180.v:6363.66-6363.97" + wire $not$ls180.v:6363$1964_Y + attribute \src "ls180.v:6371.70-6371.101" + wire $not$ls180.v:6371$1972_Y + attribute \src "ls180.v:6374.74-6374.105" + wire $not$ls180.v:6374$1979_Y + attribute \src "ls180.v:6377.64-6377.95" + wire $not$ls180.v:6377$1986_Y + attribute \src "ls180.v:6380.74-6380.105" + wire $not$ls180.v:6380$1993_Y + attribute \src "ls180.v:6383.74-6383.105" + wire $not$ls180.v:6383$2000_Y + attribute \src "ls180.v:6386.75-6386.106" + wire $not$ls180.v:6386$2007_Y + attribute \src "ls180.v:6389.73-6389.104" + wire $not$ls180.v:6389$2014_Y + attribute \src "ls180.v:6392.73-6392.104" + wire $not$ls180.v:6392$2021_Y + attribute \src "ls180.v:6395.73-6395.104" + wire $not$ls180.v:6395$2028_Y + attribute \src "ls180.v:6398.73-6398.104" + wire $not$ls180.v:6398$2035_Y + attribute \src "ls180.v:6416.67-6416.99" + wire $not$ls180.v:6416$2043_Y + attribute \src "ls180.v:6419.67-6419.99" + wire $not$ls180.v:6419$2050_Y + attribute \src "ls180.v:6422.65-6422.97" + wire $not$ls180.v:6422$2057_Y + attribute \src "ls180.v:6425.64-6425.96" + wire $not$ls180.v:6425$2064_Y + attribute \src "ls180.v:6428.63-6428.95" + wire $not$ls180.v:6428$2071_Y + attribute \src "ls180.v:6431.62-6431.94" + wire $not$ls180.v:6431$2078_Y + attribute \src "ls180.v:6434.68-6434.100" + wire $not$ls180.v:6434$2085_Y + attribute \src "ls180.v:6456.67-6456.99" + wire $not$ls180.v:6456$2094_Y + attribute \src "ls180.v:6459.67-6459.99" + wire $not$ls180.v:6459$2101_Y + attribute \src "ls180.v:6462.65-6462.97" + wire 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$sub$ls180.v:8310$2727_Y + attribute \src "ls180.v:8334.30-8334.53" + wire width 32 $sub$ls180.v:8334$2730_Y + attribute \src "ls180.v:8348.30-8348.53" + wire width 32 $sub$ls180.v:8348$2734_Y + attribute \src "ls180.v:8751.36-8751.70" + wire width 6 $sub$ls180.v:8751$2795_Y + attribute \src "ls180.v:8849.36-8849.70" + wire width 6 $sub$ls180.v:8849$2817_Y + attribute \src "ls180.v:8962.22-8962.42" + wire width 20 $sub$ls180.v:8962$2824_Y + attribute \src "ls180.v:5037.353-5037.425" + wire $xor$ls180.v:5037$827_Y + attribute \src "ls180.v:5037.200-5037.272" + wire $xor$ls180.v:5037$828_Y + attribute \src "ls180.v:5037.160-5037.273" + wire $xor$ls180.v:5037$829_Y + attribute \src "ls180.v:5038.353-5038.425" + wire $xor$ls180.v:5038$830_Y + attribute \src "ls180.v:5038.200-5038.272" + wire $xor$ls180.v:5038$831_Y + attribute \src "ls180.v:5038.160-5038.273" + wire $xor$ls180.v:5038$832_Y + attribute \src "ls180.v:5039.353-5039.425" + wire $xor$ls180.v:5039$833_Y + attribute \src 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"ls180.v:5061.361-5061.434" + wire $xor$ls180.v:5061$899_Y + attribute \src "ls180.v:5061.205-5061.278" + wire $xor$ls180.v:5061$900_Y + attribute \src "ls180.v:5061.164-5061.279" + wire $xor$ls180.v:5061$901_Y + attribute \src "ls180.v:5062.361-5062.434" + wire $xor$ls180.v:5062$902_Y + attribute \src "ls180.v:5062.205-5062.278" + wire $xor$ls180.v:5062$903_Y + attribute \src "ls180.v:5062.164-5062.279" + wire $xor$ls180.v:5062$904_Y + attribute \src "ls180.v:5063.361-5063.434" + wire $xor$ls180.v:5063$905_Y + attribute \src "ls180.v:5063.205-5063.278" + wire $xor$ls180.v:5063$906_Y + attribute \src "ls180.v:5063.164-5063.279" + wire $xor$ls180.v:5063$907_Y + attribute \src "ls180.v:5064.361-5064.434" + wire $xor$ls180.v:5064$908_Y + attribute \src "ls180.v:5064.205-5064.278" + wire $xor$ls180.v:5064$909_Y + attribute \src "ls180.v:5064.164-5064.279" + wire $xor$ls180.v:5064$910_Y + attribute \src "ls180.v:5065.361-5065.434" + wire $xor$ls180.v:5065$911_Y + attribute \src "ls180.v:5065.205-5065.278" + wire $xor$ls180.v:5065$912_Y + attribute \src "ls180.v:5065.164-5065.279" + wire $xor$ls180.v:5065$913_Y + attribute \src "ls180.v:5066.361-5066.434" + wire $xor$ls180.v:5066$914_Y + attribute \src "ls180.v:5066.205-5066.278" + wire $xor$ls180.v:5066$915_Y + attribute \src "ls180.v:5066.164-5066.279" + wire $xor$ls180.v:5066$916_Y + attribute \src "ls180.v:5067.360-5067.432" + wire $xor$ls180.v:5067$917_Y + attribute \src "ls180.v:5067.205-5067.277" + wire $xor$ls180.v:5067$918_Y + attribute \src "ls180.v:5067.164-5067.278" + wire $xor$ls180.v:5067$919_Y + attribute \src "ls180.v:5068.360-5068.432" + wire $xor$ls180.v:5068$920_Y + attribute \src "ls180.v:5068.205-5068.277" + wire $xor$ls180.v:5068$921_Y + attribute \src "ls180.v:5068.164-5068.278" + wire $xor$ls180.v:5068$922_Y + attribute \src "ls180.v:5069.360-5069.432" + wire $xor$ls180.v:5069$923_Y + attribute \src "ls180.v:5069.205-5069.277" + wire $xor$ls180.v:5069$924_Y + attribute \src "ls180.v:5069.164-5069.278" + wire $xor$ls180.v:5069$925_Y + attribute \src "ls180.v:5070.360-5070.432" + wire $xor$ls180.v:5070$926_Y + attribute \src "ls180.v:5070.205-5070.277" + wire $xor$ls180.v:5070$927_Y + attribute \src "ls180.v:5070.164-5070.278" + wire $xor$ls180.v:5070$928_Y + attribute \src "ls180.v:5071.360-5071.432" + wire $xor$ls180.v:5071$929_Y + attribute \src "ls180.v:5071.205-5071.277" + wire $xor$ls180.v:5071$930_Y + attribute \src "ls180.v:5071.164-5071.278" + wire $xor$ls180.v:5071$931_Y + attribute \src "ls180.v:5072.360-5072.432" + wire $xor$ls180.v:5072$932_Y + attribute \src "ls180.v:5072.205-5072.277" + wire $xor$ls180.v:5072$933_Y + attribute \src "ls180.v:5072.164-5072.278" + wire $xor$ls180.v:5072$934_Y + attribute \src "ls180.v:5073.360-5073.432" + wire $xor$ls180.v:5073$935_Y + attribute \src "ls180.v:5073.205-5073.277" + wire $xor$ls180.v:5073$936_Y + attribute \src "ls180.v:5073.164-5073.278" + wire $xor$ls180.v:5073$937_Y + attribute \src "ls180.v:5074.360-5074.432" + wire $xor$ls180.v:5074$938_Y + attribute \src "ls180.v:5074.205-5074.277" + wire $xor$ls180.v:5074$939_Y + attribute \src "ls180.v:5074.164-5074.278" + wire $xor$ls180.v:5074$940_Y + attribute \src "ls180.v:5075.360-5075.432" + wire $xor$ls180.v:5075$941_Y + attribute \src "ls180.v:5075.205-5075.277" + wire $xor$ls180.v:5075$942_Y + attribute \src "ls180.v:5075.164-5075.278" + wire $xor$ls180.v:5075$943_Y + attribute \src "ls180.v:5076.360-5076.432" + wire $xor$ls180.v:5076$944_Y + attribute \src "ls180.v:5076.205-5076.277" + wire $xor$ls180.v:5076$945_Y + attribute \src "ls180.v:5076.164-5076.278" + wire $xor$ls180.v:5076$946_Y + attribute \src "ls180.v:5097.899-5097.983" + wire $xor$ls180.v:5097$960_Y + attribute \src "ls180.v:5097.634-5097.718" + wire $xor$ls180.v:5097$961_Y + attribute \src "ls180.v:5097.588-5097.719" + wire $xor$ls180.v:5097$962_Y + attribute \src "ls180.v:5097.234-5097.318" + wire $xor$ls180.v:5097$963_Y + attribute \src "ls180.v:5097.187-5097.319" + wire $xor$ls180.v:5097$964_Y + attribute \src "ls180.v:5098.899-5098.983" + wire $xor$ls180.v:5098$965_Y + attribute \src "ls180.v:5098.634-5098.718" + wire $xor$ls180.v:5098$966_Y + attribute \src "ls180.v:5098.588-5098.719" + wire $xor$ls180.v:5098$967_Y + attribute \src "ls180.v:5098.234-5098.318" + wire $xor$ls180.v:5098$968_Y + attribute \src "ls180.v:5098.187-5098.319" + wire $xor$ls180.v:5098$969_Y + attribute \src "ls180.v:5107.899-5107.983" + wire $xor$ls180.v:5107$971_Y + attribute \src "ls180.v:5107.634-5107.718" + wire $xor$ls180.v:5107$972_Y + attribute \src "ls180.v:5107.588-5107.719" + wire $xor$ls180.v:5107$973_Y + attribute \src "ls180.v:5107.234-5107.318" + wire $xor$ls180.v:5107$974_Y + attribute \src "ls180.v:5107.187-5107.319" + wire $xor$ls180.v:5107$975_Y + attribute \src "ls180.v:5108.899-5108.983" + wire $xor$ls180.v:5108$976_Y + attribute \src "ls180.v:5108.634-5108.718" + wire $xor$ls180.v:5108$977_Y + attribute \src "ls180.v:5108.588-5108.719" + wire $xor$ls180.v:5108$978_Y + attribute \src "ls180.v:5108.234-5108.318" + wire $xor$ls180.v:5108$979_Y + attribute \src "ls180.v:5108.187-5108.319" + wire $xor$ls180.v:5108$980_Y + attribute \src "ls180.v:5117.899-5117.983" + wire $xor$ls180.v:5117$982_Y + attribute \src "ls180.v:5117.634-5117.718" + wire $xor$ls180.v:5117$983_Y + attribute \src "ls180.v:5117.588-5117.719" + wire $xor$ls180.v:5117$984_Y + attribute \src "ls180.v:5117.234-5117.318" + wire $xor$ls180.v:5117$985_Y + attribute \src "ls180.v:5117.187-5117.319" + wire $xor$ls180.v:5117$986_Y + attribute \src "ls180.v:5118.899-5118.983" + wire $xor$ls180.v:5118$987_Y + attribute \src "ls180.v:5118.634-5118.718" + wire $xor$ls180.v:5118$988_Y + attribute \src "ls180.v:5118.588-5118.719" + wire $xor$ls180.v:5118$989_Y + attribute \src "ls180.v:5118.234-5118.318" + wire $xor$ls180.v:5118$990_Y + attribute \src "ls180.v:5118.187-5118.319" + wire $xor$ls180.v:5118$991_Y + attribute \src "ls180.v:5127.899-5127.983" + wire $xor$ls180.v:5127$993_Y + attribute \src "ls180.v:5127.634-5127.718" + wire $xor$ls180.v:5127$994_Y + attribute \src "ls180.v:5127.588-5127.719" + wire $xor$ls180.v:5127$995_Y + attribute \src "ls180.v:5127.234-5127.318" + wire $xor$ls180.v:5127$996_Y + attribute \src "ls180.v:5127.187-5127.319" + wire $xor$ls180.v:5127$997_Y + attribute \src "ls180.v:5128.588-5128.719" + wire $xor$ls180.v:5128$1000_Y + attribute \src "ls180.v:5128.234-5128.318" + wire $xor$ls180.v:5128$1001_Y + attribute \src "ls180.v:5128.187-5128.319" + wire $xor$ls180.v:5128$1002_Y + attribute \src "ls180.v:5128.899-5128.983" + wire $xor$ls180.v:5128$998_Y + attribute \src "ls180.v:5128.634-5128.718" + wire $xor$ls180.v:5128$999_Y + attribute \src "ls180.v:5279.879-5279.961" + wire $xor$ls180.v:5279$1035_Y + attribute \src "ls180.v:5279.620-5279.702" + wire $xor$ls180.v:5279$1036_Y + attribute \src "ls180.v:5279.575-5279.703" + wire $xor$ls180.v:5279$1037_Y + attribute \src "ls180.v:5279.229-5279.311" + wire $xor$ls180.v:5279$1038_Y + attribute \src "ls180.v:5279.183-5279.312" + wire $xor$ls180.v:5279$1039_Y + attribute \src "ls180.v:5280.879-5280.961" + wire $xor$ls180.v:5280$1040_Y + attribute \src "ls180.v:5280.620-5280.702" + wire $xor$ls180.v:5280$1041_Y + attribute \src "ls180.v:5280.575-5280.703" + wire $xor$ls180.v:5280$1042_Y + attribute \src "ls180.v:5280.229-5280.311" + wire $xor$ls180.v:5280$1043_Y + attribute \src "ls180.v:5280.183-5280.312" + wire $xor$ls180.v:5280$1044_Y + attribute \src "ls180.v:5289.879-5289.961" + wire $xor$ls180.v:5289$1046_Y + attribute \src "ls180.v:5289.620-5289.702" + wire $xor$ls180.v:5289$1047_Y + attribute \src "ls180.v:5289.575-5289.703" + wire $xor$ls180.v:5289$1048_Y + attribute \src "ls180.v:5289.229-5289.311" + wire $xor$ls180.v:5289$1049_Y + attribute \src "ls180.v:5289.183-5289.312" + wire $xor$ls180.v:5289$1050_Y + attribute \src "ls180.v:5290.879-5290.961" + wire $xor$ls180.v:5290$1051_Y + attribute \src "ls180.v:5290.620-5290.702" + wire $xor$ls180.v:5290$1052_Y + attribute \src "ls180.v:5290.575-5290.703" + wire $xor$ls180.v:5290$1053_Y + attribute \src "ls180.v:5290.229-5290.311" + wire $xor$ls180.v:5290$1054_Y + attribute \src "ls180.v:5290.183-5290.312" + wire $xor$ls180.v:5290$1055_Y + attribute \src "ls180.v:5299.879-5299.961" + wire $xor$ls180.v:5299$1057_Y + attribute \src "ls180.v:5299.620-5299.702" + wire $xor$ls180.v:5299$1058_Y + attribute \src "ls180.v:5299.575-5299.703" + wire $xor$ls180.v:5299$1059_Y + attribute \src "ls180.v:5299.229-5299.311" + wire $xor$ls180.v:5299$1060_Y + attribute \src "ls180.v:5299.183-5299.312" + wire $xor$ls180.v:5299$1061_Y + attribute \src "ls180.v:5300.879-5300.961" + wire $xor$ls180.v:5300$1062_Y + attribute \src "ls180.v:5300.620-5300.702" + wire $xor$ls180.v:5300$1063_Y + attribute \src "ls180.v:5300.575-5300.703" + wire $xor$ls180.v:5300$1064_Y + attribute \src "ls180.v:5300.229-5300.311" + wire $xor$ls180.v:5300$1065_Y + attribute \src "ls180.v:5300.183-5300.312" + wire $xor$ls180.v:5300$1066_Y + attribute \src "ls180.v:5309.879-5309.961" + wire $xor$ls180.v:5309$1068_Y + attribute \src "ls180.v:5309.620-5309.702" + wire $xor$ls180.v:5309$1069_Y + attribute \src "ls180.v:5309.575-5309.703" + wire $xor$ls180.v:5309$1070_Y + attribute \src "ls180.v:5309.229-5309.311" + wire $xor$ls180.v:5309$1071_Y + attribute \src "ls180.v:5309.183-5309.312" + wire $xor$ls180.v:5309$1072_Y + attribute \src "ls180.v:5310.879-5310.961" + wire $xor$ls180.v:5310$1073_Y + attribute \src "ls180.v:5310.620-5310.702" + wire $xor$ls180.v:5310$1074_Y + attribute \src "ls180.v:5310.575-5310.703" + wire $xor$ls180.v:5310$1075_Y + attribute \src "ls180.v:5310.229-5310.311" + wire $xor$ls180.v:5310$1076_Y + attribute \src "ls180.v:5310.183-5310.312" + wire $xor$ls180.v:5310$1077_Y + attribute \src "ls180.v:1795.11-1795.42" wire width 3 \builder_bankmachine0_next_state - attribute \src "ls180.v:1789.11-1789.37" + attribute \src "ls180.v:1794.11-1794.37" wire width 3 \builder_bankmachine0_state - attribute \src "ls180.v:1792.11-1792.42" + attribute \src "ls180.v:1797.11-1797.42" wire width 3 \builder_bankmachine1_next_state - attribute \src "ls180.v:1791.11-1791.37" + attribute \src "ls180.v:1796.11-1796.37" wire width 3 \builder_bankmachine1_state - attribute \src "ls180.v:1794.11-1794.42" + attribute \src "ls180.v:1799.11-1799.42" wire width 3 \builder_bankmachine2_next_state - attribute \src "ls180.v:1793.11-1793.37" + attribute \src "ls180.v:1798.11-1798.37" wire width 3 \builder_bankmachine2_state - attribute \src "ls180.v:1796.11-1796.42" + attribute \src "ls180.v:1801.11-1801.42" wire width 3 \builder_bankmachine3_next_state - attribute \src "ls180.v:1795.11-1795.37" + attribute \src "ls180.v:1800.11-1800.37" wire width 3 \builder_bankmachine3_state - attribute \src "ls180.v:2641.5-2641.34" + attribute \src "ls180.v:2654.5-2654.34" wire \builder_comb_rhs_array_muxed0 - attribute \src "ls180.v:2642.12-2642.41" + attribute \src "ls180.v:2655.12-2655.41" wire width 13 \builder_comb_rhs_array_muxed1 - attribute \src "ls180.v:2654.5-2654.35" + attribute \src "ls180.v:2667.5-2667.35" wire \builder_comb_rhs_array_muxed10 - attribute \src "ls180.v:2655.5-2655.35" + attribute \src "ls180.v:2668.5-2668.35" wire \builder_comb_rhs_array_muxed11 - attribute \src "ls180.v:2659.12-2659.42" + attribute \src "ls180.v:2672.12-2672.42" wire width 22 \builder_comb_rhs_array_muxed12 - attribute \src "ls180.v:2660.5-2660.35" + attribute \src "ls180.v:2673.5-2673.35" wire \builder_comb_rhs_array_muxed13 - attribute \src "ls180.v:2661.5-2661.35" + attribute \src "ls180.v:2674.5-2674.35" wire \builder_comb_rhs_array_muxed14 - attribute \src "ls180.v:2662.12-2662.42" + attribute \src "ls180.v:2675.12-2675.42" wire width 22 \builder_comb_rhs_array_muxed15 - attribute \src "ls180.v:2663.5-2663.35" + attribute \src "ls180.v:2676.5-2676.35" wire \builder_comb_rhs_array_muxed16 - attribute \src "ls180.v:2664.5-2664.35" + attribute \src "ls180.v:2677.5-2677.35" wire \builder_comb_rhs_array_muxed17 - attribute \src "ls180.v:2665.12-2665.42" + attribute \src "ls180.v:2678.12-2678.42" wire width 22 \builder_comb_rhs_array_muxed18 - attribute \src "ls180.v:2666.5-2666.35" + attribute \src "ls180.v:2679.5-2679.35" wire \builder_comb_rhs_array_muxed19 - attribute \src "ls180.v:2643.11-2643.40" + attribute \src "ls180.v:2656.11-2656.40" wire width 2 \builder_comb_rhs_array_muxed2 - attribute \src "ls180.v:2667.5-2667.35" + attribute \src "ls180.v:2680.5-2680.35" wire \builder_comb_rhs_array_muxed20 - attribute \src "ls180.v:2668.12-2668.42" + attribute \src "ls180.v:2681.12-2681.42" wire width 22 \builder_comb_rhs_array_muxed21 - attribute \src "ls180.v:2669.5-2669.35" + attribute \src "ls180.v:2682.5-2682.35" wire \builder_comb_rhs_array_muxed22 - attribute \src "ls180.v:2670.5-2670.35" + attribute \src "ls180.v:2683.5-2683.35" wire \builder_comb_rhs_array_muxed23 - attribute \src "ls180.v:2671.12-2671.42" + attribute \src "ls180.v:2684.12-2684.42" wire width 32 \builder_comb_rhs_array_muxed24 - attribute \src "ls180.v:2672.12-2672.42" - wire width 32 \builder_comb_rhs_array_muxed25 - attribute \src "ls180.v:2673.11-2673.41" - wire width 4 \builder_comb_rhs_array_muxed26 - attribute \src "ls180.v:2674.5-2674.35" + attribute \src "ls180.v:2685.12-2685.42" + wire width 64 \builder_comb_rhs_array_muxed25 + attribute \src "ls180.v:2686.11-2686.41" + wire width 8 \builder_comb_rhs_array_muxed26 + attribute \src "ls180.v:2687.5-2687.35" wire \builder_comb_rhs_array_muxed27 - attribute \src "ls180.v:2675.5-2675.35" + attribute \src "ls180.v:2688.5-2688.35" wire \builder_comb_rhs_array_muxed28 - attribute \src "ls180.v:2676.5-2676.35" + attribute \src "ls180.v:2689.5-2689.35" wire \builder_comb_rhs_array_muxed29 - attribute \src "ls180.v:2644.5-2644.34" + attribute \src "ls180.v:2657.5-2657.34" wire \builder_comb_rhs_array_muxed3 - attribute \src "ls180.v:2677.11-2677.41" + attribute \src "ls180.v:2690.11-2690.41" wire width 3 \builder_comb_rhs_array_muxed30 - attribute \src "ls180.v:2678.11-2678.41" + attribute \src "ls180.v:2691.11-2691.41" wire width 2 \builder_comb_rhs_array_muxed31 - attribute \src "ls180.v:2645.5-2645.34" + attribute \src "ls180.v:2658.5-2658.34" wire \builder_comb_rhs_array_muxed4 - attribute \src "ls180.v:2646.5-2646.34" + attribute \src "ls180.v:2659.5-2659.34" wire \builder_comb_rhs_array_muxed5 - attribute \src "ls180.v:2650.5-2650.34" + attribute \src "ls180.v:2663.5-2663.34" wire \builder_comb_rhs_array_muxed6 - attribute \src "ls180.v:2651.12-2651.41" + attribute \src "ls180.v:2664.12-2664.41" wire width 13 \builder_comb_rhs_array_muxed7 - attribute \src "ls180.v:2652.11-2652.40" + attribute \src "ls180.v:2665.11-2665.40" wire width 2 \builder_comb_rhs_array_muxed8 - attribute \src "ls180.v:2653.5-2653.34" + attribute \src "ls180.v:2666.5-2666.34" wire \builder_comb_rhs_array_muxed9 - attribute \src "ls180.v:2647.5-2647.32" + attribute \src "ls180.v:2660.5-2660.32" wire \builder_comb_t_array_muxed0 - attribute \src "ls180.v:2648.5-2648.32" + attribute \src "ls180.v:2661.5-2661.32" wire \builder_comb_t_array_muxed1 - attribute \src "ls180.v:2649.5-2649.32" + attribute \src "ls180.v:2662.5-2662.32" wire \builder_comb_t_array_muxed2 - attribute \src "ls180.v:2656.5-2656.32" + attribute \src "ls180.v:2669.5-2669.32" wire \builder_comb_t_array_muxed3 - attribute \src "ls180.v:2657.5-2657.32" + attribute \src "ls180.v:2670.5-2670.32" wire \builder_comb_t_array_muxed4 - attribute \src "ls180.v:2658.5-2658.32" + attribute \src "ls180.v:2671.5-2671.32" wire \builder_comb_t_array_muxed5 - attribute \src "ls180.v:1776.5-1776.34" + attribute \src "ls180.v:1781.5-1781.34" wire \builder_converter0_next_state - attribute \src "ls180.v:1775.5-1775.29" + attribute \src "ls180.v:1780.5-1780.29" wire \builder_converter0_state - attribute \src "ls180.v:1780.5-1780.34" + attribute \src "ls180.v:1785.5-1785.34" wire \builder_converter1_next_state - attribute \src "ls180.v:1779.5-1779.29" + attribute \src "ls180.v:1784.5-1784.29" wire \builder_converter1_state - attribute \src "ls180.v:1784.5-1784.34" + attribute \src "ls180.v:1789.5-1789.34" wire \builder_converter2_next_state - attribute \src "ls180.v:1783.5-1783.29" + attribute \src "ls180.v:1788.5-1788.29" wire \builder_converter2_state - attribute \src "ls180.v:1821.5-1821.33" + attribute \src "ls180.v:1826.5-1826.33" wire \builder_converter_next_state - attribute \src "ls180.v:1820.5-1820.28" + attribute \src "ls180.v:1825.5-1825.28" wire \builder_converter_state - attribute \src "ls180.v:1941.12-1941.25" + attribute \src "ls180.v:1954.12-1954.25" wire width 20 \builder_count - attribute \src "ls180.v:2629.13-2629.41" + attribute \src "ls180.v:2642.13-2642.41" wire width 14 \builder_csr_interconnect_adr - attribute \src "ls180.v:2632.12-2632.42" + attribute \src "ls180.v:2645.12-2645.42" wire width 8 \builder_csr_interconnect_dat_r - attribute \src "ls180.v:2631.12-2631.42" + attribute \src "ls180.v:2644.12-2644.42" wire width 8 \builder_csr_interconnect_dat_w - attribute \src "ls180.v:2630.6-2630.33" + attribute \src "ls180.v:2643.6-2643.33" wire \builder_csr_interconnect_we - attribute \src "ls180.v:1979.12-1979.42" + attribute \src "ls180.v:1992.12-1992.42" wire width 8 \builder_csrbank0_bus_errors0_r - attribute \src "ls180.v:1978.6-1978.37" + attribute \src "ls180.v:1991.6-1991.37" wire \builder_csrbank0_bus_errors0_re - attribute \src "ls180.v:1981.12-1981.42" + attribute \src "ls180.v:1994.12-1994.42" wire width 8 \builder_csrbank0_bus_errors0_w - attribute \src "ls180.v:1980.6-1980.37" + attribute \src "ls180.v:1993.6-1993.37" wire \builder_csrbank0_bus_errors0_we - attribute \src "ls180.v:1975.12-1975.42" + attribute \src "ls180.v:1988.12-1988.42" wire width 8 \builder_csrbank0_bus_errors1_r - attribute \src "ls180.v:1974.6-1974.37" + attribute \src "ls180.v:1987.6-1987.37" wire \builder_csrbank0_bus_errors1_re - attribute \src "ls180.v:1977.12-1977.42" + attribute \src "ls180.v:1990.12-1990.42" wire width 8 \builder_csrbank0_bus_errors1_w - attribute \src "ls180.v:1976.6-1976.37" + attribute \src "ls180.v:1989.6-1989.37" wire \builder_csrbank0_bus_errors1_we - attribute \src "ls180.v:1971.12-1971.42" + attribute \src "ls180.v:1984.12-1984.42" wire width 8 \builder_csrbank0_bus_errors2_r - attribute \src "ls180.v:1970.6-1970.37" + attribute \src "ls180.v:1983.6-1983.37" wire \builder_csrbank0_bus_errors2_re - attribute \src "ls180.v:1973.12-1973.42" + attribute \src "ls180.v:1986.12-1986.42" wire width 8 \builder_csrbank0_bus_errors2_w - attribute \src "ls180.v:1972.6-1972.37" + attribute \src "ls180.v:1985.6-1985.37" wire \builder_csrbank0_bus_errors2_we - attribute \src "ls180.v:1967.12-1967.42" + attribute \src "ls180.v:1980.12-1980.42" wire width 8 \builder_csrbank0_bus_errors3_r - attribute \src "ls180.v:1966.6-1966.37" + attribute \src "ls180.v:1979.6-1979.37" wire \builder_csrbank0_bus_errors3_re - attribute \src "ls180.v:1969.12-1969.42" + attribute \src "ls180.v:1982.12-1982.42" wire width 8 \builder_csrbank0_bus_errors3_w - attribute \src "ls180.v:1968.6-1968.37" + attribute \src "ls180.v:1981.6-1981.37" wire \builder_csrbank0_bus_errors3_we - attribute \src "ls180.v:1947.6-1947.31" + attribute \src "ls180.v:1960.6-1960.31" wire \builder_csrbank0_reset0_r - attribute \src "ls180.v:1946.6-1946.32" + attribute \src "ls180.v:1959.6-1959.32" wire \builder_csrbank0_reset0_re - attribute \src "ls180.v:1949.6-1949.31" + attribute \src "ls180.v:1962.6-1962.31" wire \builder_csrbank0_reset0_w - attribute \src "ls180.v:1948.6-1948.32" + attribute \src "ls180.v:1961.6-1961.32" wire \builder_csrbank0_reset0_we - attribute \src "ls180.v:1963.12-1963.39" + attribute \src "ls180.v:1976.12-1976.39" wire width 8 \builder_csrbank0_scratch0_r - attribute \src "ls180.v:1962.6-1962.34" + attribute \src "ls180.v:1975.6-1975.34" wire \builder_csrbank0_scratch0_re - attribute \src "ls180.v:1965.12-1965.39" + attribute \src "ls180.v:1978.12-1978.39" wire width 8 \builder_csrbank0_scratch0_w - attribute \src "ls180.v:1964.6-1964.34" + attribute \src "ls180.v:1977.6-1977.34" wire \builder_csrbank0_scratch0_we - attribute \src "ls180.v:1959.12-1959.39" + attribute \src "ls180.v:1972.12-1972.39" wire width 8 \builder_csrbank0_scratch1_r - attribute \src "ls180.v:1958.6-1958.34" + attribute \src "ls180.v:1971.6-1971.34" wire \builder_csrbank0_scratch1_re - attribute \src "ls180.v:1961.12-1961.39" + attribute \src "ls180.v:1974.12-1974.39" wire width 8 \builder_csrbank0_scratch1_w - attribute \src "ls180.v:1960.6-1960.34" + attribute \src "ls180.v:1973.6-1973.34" wire \builder_csrbank0_scratch1_we - attribute \src "ls180.v:1955.12-1955.39" + attribute \src "ls180.v:1968.12-1968.39" wire width 8 \builder_csrbank0_scratch2_r - attribute \src "ls180.v:1954.6-1954.34" + attribute \src "ls180.v:1967.6-1967.34" wire \builder_csrbank0_scratch2_re - attribute \src "ls180.v:1957.12-1957.39" + attribute \src "ls180.v:1970.12-1970.39" wire width 8 \builder_csrbank0_scratch2_w - attribute \src "ls180.v:1956.6-1956.34" + attribute \src "ls180.v:1969.6-1969.34" wire \builder_csrbank0_scratch2_we - attribute \src "ls180.v:1951.12-1951.39" + attribute \src "ls180.v:1964.12-1964.39" wire width 8 \builder_csrbank0_scratch3_r - attribute \src "ls180.v:1950.6-1950.34" + attribute \src "ls180.v:1963.6-1963.34" wire \builder_csrbank0_scratch3_re - attribute \src "ls180.v:1953.12-1953.39" + attribute \src "ls180.v:1966.12-1966.39" wire width 8 \builder_csrbank0_scratch3_w - attribute \src "ls180.v:1952.6-1952.34" + attribute \src "ls180.v:1965.6-1965.34" wire \builder_csrbank0_scratch3_we - attribute \src "ls180.v:1982.6-1982.26" + attribute \src "ls180.v:1995.6-1995.26" wire \builder_csrbank0_sel - attribute \src "ls180.v:2453.12-2453.40" + attribute \src "ls180.v:2466.12-2466.40" wire width 8 \builder_csrbank10_control0_r - attribute \src "ls180.v:2452.6-2452.35" + attribute \src "ls180.v:2465.6-2465.35" wire \builder_csrbank10_control0_re - attribute \src "ls180.v:2455.12-2455.40" + attribute \src "ls180.v:2468.12-2468.40" wire width 8 \builder_csrbank10_control0_w - attribute \src "ls180.v:2454.6-2454.35" + attribute \src "ls180.v:2467.6-2467.35" wire \builder_csrbank10_control0_we - attribute \src "ls180.v:2449.12-2449.40" + attribute \src "ls180.v:2462.12-2462.40" wire width 8 \builder_csrbank10_control1_r - attribute \src "ls180.v:2448.6-2448.35" + attribute \src "ls180.v:2461.6-2461.35" wire \builder_csrbank10_control1_re - attribute \src "ls180.v:2451.12-2451.40" + attribute \src "ls180.v:2464.12-2464.40" wire width 8 \builder_csrbank10_control1_w - attribute \src "ls180.v:2450.6-2450.35" + attribute \src "ls180.v:2463.6-2463.35" wire \builder_csrbank10_control1_we - attribute \src "ls180.v:2469.6-2469.29" + attribute \src "ls180.v:2482.6-2482.29" wire \builder_csrbank10_cs0_r - attribute \src "ls180.v:2468.6-2468.30" + attribute \src "ls180.v:2481.6-2481.30" wire \builder_csrbank10_cs0_re - attribute \src "ls180.v:2471.6-2471.29" + attribute \src "ls180.v:2484.6-2484.29" wire \builder_csrbank10_cs0_w - attribute \src "ls180.v:2470.6-2470.30" + attribute \src "ls180.v:2483.6-2483.30" wire \builder_csrbank10_cs0_we - attribute \src "ls180.v:2473.6-2473.35" + attribute \src "ls180.v:2486.6-2486.35" wire \builder_csrbank10_loopback0_r - attribute \src "ls180.v:2472.6-2472.36" + attribute \src "ls180.v:2485.6-2485.36" wire \builder_csrbank10_loopback0_re - attribute \src "ls180.v:2475.6-2475.35" + attribute \src "ls180.v:2488.6-2488.35" wire \builder_csrbank10_loopback0_w - attribute \src "ls180.v:2474.6-2474.36" + attribute \src "ls180.v:2487.6-2487.36" wire \builder_csrbank10_loopback0_we - attribute \src "ls180.v:2465.12-2465.36" + attribute \src "ls180.v:2478.12-2478.36" wire width 8 \builder_csrbank10_miso_r - attribute \src "ls180.v:2464.6-2464.31" + attribute \src "ls180.v:2477.6-2477.31" wire \builder_csrbank10_miso_re - attribute \src "ls180.v:2467.12-2467.36" + attribute \src "ls180.v:2480.12-2480.36" wire width 8 \builder_csrbank10_miso_w - attribute \src "ls180.v:2466.6-2466.31" + attribute \src "ls180.v:2479.6-2479.31" wire \builder_csrbank10_miso_we - attribute \src "ls180.v:2461.12-2461.37" + attribute \src "ls180.v:2474.12-2474.37" wire width 8 \builder_csrbank10_mosi0_r - attribute \src "ls180.v:2460.6-2460.32" + attribute \src "ls180.v:2473.6-2473.32" wire \builder_csrbank10_mosi0_re - attribute \src "ls180.v:2463.12-2463.37" + attribute \src "ls180.v:2476.12-2476.37" wire width 8 \builder_csrbank10_mosi0_w - attribute \src "ls180.v:2462.6-2462.32" + attribute \src "ls180.v:2475.6-2475.32" wire \builder_csrbank10_mosi0_we - attribute \src "ls180.v:2476.6-2476.27" + attribute \src "ls180.v:2489.6-2489.27" wire \builder_csrbank10_sel - attribute \src "ls180.v:2457.6-2457.32" + attribute \src "ls180.v:2470.6-2470.32" wire \builder_csrbank10_status_r - attribute \src "ls180.v:2456.6-2456.33" + attribute \src "ls180.v:2469.6-2469.33" wire \builder_csrbank10_status_re - attribute \src "ls180.v:2459.6-2459.32" + attribute \src "ls180.v:2472.6-2472.32" wire \builder_csrbank10_status_w - attribute \src "ls180.v:2458.6-2458.33" + attribute \src "ls180.v:2471.6-2471.33" wire \builder_csrbank10_status_we - attribute \src "ls180.v:2514.12-2514.44" + attribute \src "ls180.v:2527.12-2527.44" wire width 8 \builder_csrbank11_clk_divider0_r - attribute \src "ls180.v:2513.6-2513.39" + attribute \src "ls180.v:2526.6-2526.39" wire \builder_csrbank11_clk_divider0_re - attribute \src "ls180.v:2516.12-2516.44" + attribute \src "ls180.v:2529.12-2529.44" wire width 8 \builder_csrbank11_clk_divider0_w - attribute \src "ls180.v:2515.6-2515.39" + attribute \src "ls180.v:2528.6-2528.39" wire \builder_csrbank11_clk_divider0_we - attribute \src "ls180.v:2510.12-2510.44" + attribute \src "ls180.v:2523.12-2523.44" wire width 8 \builder_csrbank11_clk_divider1_r - attribute \src "ls180.v:2509.6-2509.39" + attribute \src "ls180.v:2522.6-2522.39" wire \builder_csrbank11_clk_divider1_re - attribute \src "ls180.v:2512.12-2512.44" + attribute \src "ls180.v:2525.12-2525.44" wire width 8 \builder_csrbank11_clk_divider1_w - attribute \src "ls180.v:2511.6-2511.39" + attribute \src "ls180.v:2524.6-2524.39" wire \builder_csrbank11_clk_divider1_we - attribute \src "ls180.v:2486.12-2486.40" + attribute \src "ls180.v:2499.12-2499.40" wire width 8 \builder_csrbank11_control0_r - attribute \src "ls180.v:2485.6-2485.35" + attribute \src "ls180.v:2498.6-2498.35" wire \builder_csrbank11_control0_re - attribute \src "ls180.v:2488.12-2488.40" + attribute \src "ls180.v:2501.12-2501.40" wire width 8 \builder_csrbank11_control0_w - attribute \src "ls180.v:2487.6-2487.35" + attribute \src "ls180.v:2500.6-2500.35" wire \builder_csrbank11_control0_we - attribute \src "ls180.v:2482.12-2482.40" + attribute \src "ls180.v:2495.12-2495.40" wire width 8 \builder_csrbank11_control1_r - attribute \src "ls180.v:2481.6-2481.35" + attribute \src "ls180.v:2494.6-2494.35" wire \builder_csrbank11_control1_re - attribute \src "ls180.v:2484.12-2484.40" + attribute \src "ls180.v:2497.12-2497.40" wire width 8 \builder_csrbank11_control1_w - attribute \src "ls180.v:2483.6-2483.35" + attribute \src "ls180.v:2496.6-2496.35" wire \builder_csrbank11_control1_we - attribute \src "ls180.v:2502.6-2502.29" + attribute \src "ls180.v:2515.6-2515.29" wire \builder_csrbank11_cs0_r - attribute \src "ls180.v:2501.6-2501.30" + attribute \src "ls180.v:2514.6-2514.30" wire \builder_csrbank11_cs0_re - attribute \src "ls180.v:2504.6-2504.29" + attribute \src "ls180.v:2517.6-2517.29" wire \builder_csrbank11_cs0_w - attribute \src "ls180.v:2503.6-2503.30" + attribute \src "ls180.v:2516.6-2516.30" wire \builder_csrbank11_cs0_we - attribute \src "ls180.v:2506.6-2506.35" + attribute \src "ls180.v:2519.6-2519.35" wire \builder_csrbank11_loopback0_r - attribute \src "ls180.v:2505.6-2505.36" + attribute \src "ls180.v:2518.6-2518.36" wire \builder_csrbank11_loopback0_re - attribute \src "ls180.v:2508.6-2508.35" + attribute \src "ls180.v:2521.6-2521.35" wire \builder_csrbank11_loopback0_w - attribute \src "ls180.v:2507.6-2507.36" + attribute \src "ls180.v:2520.6-2520.36" wire \builder_csrbank11_loopback0_we - attribute \src "ls180.v:2498.12-2498.36" + attribute \src "ls180.v:2511.12-2511.36" wire width 8 \builder_csrbank11_miso_r - attribute \src "ls180.v:2497.6-2497.31" + attribute \src "ls180.v:2510.6-2510.31" wire \builder_csrbank11_miso_re - attribute \src "ls180.v:2500.12-2500.36" + attribute \src "ls180.v:2513.12-2513.36" wire width 8 \builder_csrbank11_miso_w - attribute \src "ls180.v:2499.6-2499.31" + attribute \src "ls180.v:2512.6-2512.31" wire \builder_csrbank11_miso_we - attribute \src "ls180.v:2494.12-2494.37" + attribute \src "ls180.v:2507.12-2507.37" wire width 8 \builder_csrbank11_mosi0_r - attribute \src "ls180.v:2493.6-2493.32" + attribute \src "ls180.v:2506.6-2506.32" wire \builder_csrbank11_mosi0_re - attribute \src "ls180.v:2496.12-2496.37" + attribute \src "ls180.v:2509.12-2509.37" wire width 8 \builder_csrbank11_mosi0_w - attribute \src "ls180.v:2495.6-2495.32" + attribute \src "ls180.v:2508.6-2508.32" wire \builder_csrbank11_mosi0_we - attribute \src "ls180.v:2517.6-2517.27" + attribute \src "ls180.v:2530.6-2530.27" wire \builder_csrbank11_sel - attribute \src "ls180.v:2490.6-2490.32" + attribute \src "ls180.v:2503.6-2503.32" wire \builder_csrbank11_status_r - attribute \src "ls180.v:2489.6-2489.33" + attribute \src "ls180.v:2502.6-2502.33" wire \builder_csrbank11_status_re - attribute \src "ls180.v:2492.6-2492.32" + attribute \src "ls180.v:2505.6-2505.32" wire \builder_csrbank11_status_w - attribute \src "ls180.v:2491.6-2491.33" + attribute \src "ls180.v:2504.6-2504.33" wire \builder_csrbank11_status_we - attribute \src "ls180.v:2555.6-2555.29" + attribute \src "ls180.v:2568.6-2568.29" wire \builder_csrbank12_en0_r - attribute \src "ls180.v:2554.6-2554.30" + attribute \src "ls180.v:2567.6-2567.30" wire \builder_csrbank12_en0_re - attribute \src "ls180.v:2557.6-2557.29" + attribute \src "ls180.v:2570.6-2570.29" wire \builder_csrbank12_en0_w - attribute \src "ls180.v:2556.6-2556.30" + attribute \src "ls180.v:2569.6-2569.30" wire \builder_csrbank12_en0_we - attribute \src "ls180.v:2579.6-2579.36" + attribute \src "ls180.v:2592.6-2592.36" wire \builder_csrbank12_ev_enable0_r - attribute \src "ls180.v:2578.6-2578.37" + attribute \src "ls180.v:2591.6-2591.37" wire \builder_csrbank12_ev_enable0_re - attribute \src "ls180.v:2581.6-2581.36" + attribute \src "ls180.v:2594.6-2594.36" wire \builder_csrbank12_ev_enable0_w - attribute \src "ls180.v:2580.6-2580.37" + attribute \src "ls180.v:2593.6-2593.37" wire \builder_csrbank12_ev_enable0_we - attribute \src "ls180.v:2535.12-2535.37" + attribute \src "ls180.v:2548.12-2548.37" wire width 8 \builder_csrbank12_load0_r - attribute \src "ls180.v:2534.6-2534.32" + attribute \src "ls180.v:2547.6-2547.32" wire \builder_csrbank12_load0_re - attribute \src "ls180.v:2537.12-2537.37" + attribute \src "ls180.v:2550.12-2550.37" wire width 8 \builder_csrbank12_load0_w - attribute \src "ls180.v:2536.6-2536.32" + attribute \src "ls180.v:2549.6-2549.32" wire \builder_csrbank12_load0_we - attribute \src "ls180.v:2531.12-2531.37" + attribute \src "ls180.v:2544.12-2544.37" wire width 8 \builder_csrbank12_load1_r - attribute \src "ls180.v:2530.6-2530.32" + attribute \src "ls180.v:2543.6-2543.32" wire \builder_csrbank12_load1_re - attribute \src "ls180.v:2533.12-2533.37" + attribute \src "ls180.v:2546.12-2546.37" wire width 8 \builder_csrbank12_load1_w - attribute \src "ls180.v:2532.6-2532.32" + attribute \src "ls180.v:2545.6-2545.32" wire \builder_csrbank12_load1_we - attribute \src "ls180.v:2527.12-2527.37" + attribute \src "ls180.v:2540.12-2540.37" wire width 8 \builder_csrbank12_load2_r - attribute \src "ls180.v:2526.6-2526.32" + attribute \src "ls180.v:2539.6-2539.32" wire \builder_csrbank12_load2_re - attribute \src "ls180.v:2529.12-2529.37" + attribute \src "ls180.v:2542.12-2542.37" wire width 8 \builder_csrbank12_load2_w - attribute \src "ls180.v:2528.6-2528.32" + attribute \src "ls180.v:2541.6-2541.32" wire \builder_csrbank12_load2_we - attribute \src "ls180.v:2523.12-2523.37" + attribute \src "ls180.v:2536.12-2536.37" wire width 8 \builder_csrbank12_load3_r - attribute \src "ls180.v:2522.6-2522.32" + attribute \src "ls180.v:2535.6-2535.32" wire \builder_csrbank12_load3_re - attribute \src "ls180.v:2525.12-2525.37" + attribute \src "ls180.v:2538.12-2538.37" wire width 8 \builder_csrbank12_load3_w - attribute \src "ls180.v:2524.6-2524.32" + attribute \src "ls180.v:2537.6-2537.32" wire \builder_csrbank12_load3_we - attribute \src "ls180.v:2551.12-2551.39" + attribute \src "ls180.v:2564.12-2564.39" wire width 8 \builder_csrbank12_reload0_r - attribute \src "ls180.v:2550.6-2550.34" + attribute \src "ls180.v:2563.6-2563.34" wire \builder_csrbank12_reload0_re - attribute \src "ls180.v:2553.12-2553.39" + attribute \src "ls180.v:2566.12-2566.39" wire width 8 \builder_csrbank12_reload0_w - attribute \src "ls180.v:2552.6-2552.34" + attribute \src "ls180.v:2565.6-2565.34" wire \builder_csrbank12_reload0_we - attribute \src "ls180.v:2547.12-2547.39" + attribute \src "ls180.v:2560.12-2560.39" wire width 8 \builder_csrbank12_reload1_r - attribute \src "ls180.v:2546.6-2546.34" + attribute \src "ls180.v:2559.6-2559.34" wire \builder_csrbank12_reload1_re - attribute \src "ls180.v:2549.12-2549.39" + attribute \src "ls180.v:2562.12-2562.39" wire width 8 \builder_csrbank12_reload1_w - attribute \src "ls180.v:2548.6-2548.34" + attribute \src "ls180.v:2561.6-2561.34" wire \builder_csrbank12_reload1_we - attribute \src "ls180.v:2543.12-2543.39" + attribute \src "ls180.v:2556.12-2556.39" wire width 8 \builder_csrbank12_reload2_r - attribute \src "ls180.v:2542.6-2542.34" + attribute \src "ls180.v:2555.6-2555.34" wire \builder_csrbank12_reload2_re - attribute \src "ls180.v:2545.12-2545.39" + attribute \src "ls180.v:2558.12-2558.39" wire width 8 \builder_csrbank12_reload2_w - attribute \src "ls180.v:2544.6-2544.34" + attribute \src "ls180.v:2557.6-2557.34" wire \builder_csrbank12_reload2_we - attribute \src "ls180.v:2539.12-2539.39" + attribute \src "ls180.v:2552.12-2552.39" wire width 8 \builder_csrbank12_reload3_r - attribute \src "ls180.v:2538.6-2538.34" + attribute \src "ls180.v:2551.6-2551.34" wire \builder_csrbank12_reload3_re - attribute \src "ls180.v:2541.12-2541.39" + attribute \src "ls180.v:2554.12-2554.39" wire width 8 \builder_csrbank12_reload3_w - attribute \src "ls180.v:2540.6-2540.34" + attribute \src "ls180.v:2553.6-2553.34" wire \builder_csrbank12_reload3_we - attribute \src "ls180.v:2582.6-2582.27" + attribute \src "ls180.v:2595.6-2595.27" wire \builder_csrbank12_sel - attribute \src "ls180.v:2559.6-2559.39" + attribute \src "ls180.v:2572.6-2572.39" wire \builder_csrbank12_update_value0_r - attribute \src "ls180.v:2558.6-2558.40" + attribute \src "ls180.v:2571.6-2571.40" wire \builder_csrbank12_update_value0_re - attribute \src "ls180.v:2561.6-2561.39" + attribute \src "ls180.v:2574.6-2574.39" wire \builder_csrbank12_update_value0_w - attribute \src "ls180.v:2560.6-2560.40" + attribute \src "ls180.v:2573.6-2573.40" wire \builder_csrbank12_update_value0_we - attribute \src "ls180.v:2575.12-2575.38" + attribute \src "ls180.v:2588.12-2588.38" wire width 8 \builder_csrbank12_value0_r - attribute \src "ls180.v:2574.6-2574.33" + attribute \src "ls180.v:2587.6-2587.33" wire \builder_csrbank12_value0_re - attribute \src "ls180.v:2577.12-2577.38" + attribute \src "ls180.v:2590.12-2590.38" wire width 8 \builder_csrbank12_value0_w - attribute \src "ls180.v:2576.6-2576.33" + attribute \src "ls180.v:2589.6-2589.33" wire \builder_csrbank12_value0_we - attribute \src "ls180.v:2571.12-2571.38" + attribute \src "ls180.v:2584.12-2584.38" wire width 8 \builder_csrbank12_value1_r - attribute \src "ls180.v:2570.6-2570.33" + attribute \src "ls180.v:2583.6-2583.33" wire \builder_csrbank12_value1_re - attribute \src "ls180.v:2573.12-2573.38" + attribute \src "ls180.v:2586.12-2586.38" wire width 8 \builder_csrbank12_value1_w - attribute \src "ls180.v:2572.6-2572.33" + attribute \src "ls180.v:2585.6-2585.33" wire \builder_csrbank12_value1_we - attribute \src "ls180.v:2567.12-2567.38" + attribute \src "ls180.v:2580.12-2580.38" wire width 8 \builder_csrbank12_value2_r - attribute \src "ls180.v:2566.6-2566.33" + attribute \src "ls180.v:2579.6-2579.33" wire \builder_csrbank12_value2_re - attribute \src "ls180.v:2569.12-2569.38" + attribute \src "ls180.v:2582.12-2582.38" wire width 8 \builder_csrbank12_value2_w - attribute \src "ls180.v:2568.6-2568.33" + attribute \src "ls180.v:2581.6-2581.33" wire \builder_csrbank12_value2_we - attribute \src "ls180.v:2563.12-2563.38" + attribute \src "ls180.v:2576.12-2576.38" wire width 8 \builder_csrbank12_value3_r - attribute \src "ls180.v:2562.6-2562.33" + attribute \src "ls180.v:2575.6-2575.33" wire \builder_csrbank12_value3_re - attribute \src "ls180.v:2565.12-2565.38" + attribute \src "ls180.v:2578.12-2578.38" wire width 8 \builder_csrbank12_value3_w - attribute \src "ls180.v:2564.6-2564.33" + attribute \src "ls180.v:2577.6-2577.33" wire \builder_csrbank12_value3_we - attribute \src "ls180.v:2596.12-2596.42" + attribute \src "ls180.v:2609.12-2609.42" wire width 2 \builder_csrbank13_ev_enable0_r - attribute \src "ls180.v:2595.6-2595.37" + attribute \src "ls180.v:2608.6-2608.37" wire \builder_csrbank13_ev_enable0_re - attribute \src "ls180.v:2598.12-2598.42" + attribute \src "ls180.v:2611.12-2611.42" wire width 2 \builder_csrbank13_ev_enable0_w - attribute \src "ls180.v:2597.6-2597.37" + attribute \src "ls180.v:2610.6-2610.37" wire \builder_csrbank13_ev_enable0_we - attribute \src "ls180.v:2592.6-2592.33" + attribute \src "ls180.v:2605.6-2605.33" wire \builder_csrbank13_rxempty_r - attribute \src "ls180.v:2591.6-2591.34" + attribute \src "ls180.v:2604.6-2604.34" wire \builder_csrbank13_rxempty_re - attribute \src "ls180.v:2594.6-2594.33" + attribute \src "ls180.v:2607.6-2607.33" wire \builder_csrbank13_rxempty_w - attribute \src "ls180.v:2593.6-2593.34" + attribute \src "ls180.v:2606.6-2606.34" wire \builder_csrbank13_rxempty_we - attribute \src "ls180.v:2604.6-2604.32" + attribute \src "ls180.v:2617.6-2617.32" wire \builder_csrbank13_rxfull_r - attribute \src "ls180.v:2603.6-2603.33" + attribute \src "ls180.v:2616.6-2616.33" wire \builder_csrbank13_rxfull_re - attribute \src "ls180.v:2606.6-2606.32" + attribute \src "ls180.v:2619.6-2619.32" wire \builder_csrbank13_rxfull_w - attribute \src "ls180.v:2605.6-2605.33" + attribute \src "ls180.v:2618.6-2618.33" wire \builder_csrbank13_rxfull_we - attribute \src "ls180.v:2607.6-2607.27" + attribute \src "ls180.v:2620.6-2620.27" wire \builder_csrbank13_sel - attribute \src "ls180.v:2600.6-2600.33" + attribute \src "ls180.v:2613.6-2613.33" wire \builder_csrbank13_txempty_r - attribute \src "ls180.v:2599.6-2599.34" + attribute \src "ls180.v:2612.6-2612.34" wire \builder_csrbank13_txempty_re - attribute \src "ls180.v:2602.6-2602.33" + attribute \src "ls180.v:2615.6-2615.33" wire \builder_csrbank13_txempty_w - attribute \src "ls180.v:2601.6-2601.34" + attribute \src "ls180.v:2614.6-2614.34" wire \builder_csrbank13_txempty_we - attribute \src "ls180.v:2588.6-2588.32" + attribute \src "ls180.v:2601.6-2601.32" wire \builder_csrbank13_txfull_r - attribute \src "ls180.v:2587.6-2587.33" + attribute \src "ls180.v:2600.6-2600.33" wire \builder_csrbank13_txfull_re - attribute \src "ls180.v:2590.6-2590.32" + attribute \src "ls180.v:2603.6-2603.32" wire \builder_csrbank13_txfull_w - attribute \src "ls180.v:2589.6-2589.33" + attribute \src "ls180.v:2602.6-2602.33" wire \builder_csrbank13_txfull_we - attribute \src "ls180.v:2628.6-2628.27" + attribute \src "ls180.v:2641.6-2641.27" wire \builder_csrbank14_sel - attribute \src "ls180.v:2625.12-2625.44" + attribute \src "ls180.v:2638.12-2638.44" wire width 8 \builder_csrbank14_tuning_word0_r - attribute \src "ls180.v:2624.6-2624.39" + attribute \src "ls180.v:2637.6-2637.39" wire \builder_csrbank14_tuning_word0_re - attribute \src "ls180.v:2627.12-2627.44" + attribute \src "ls180.v:2640.12-2640.44" wire width 8 \builder_csrbank14_tuning_word0_w - attribute \src "ls180.v:2626.6-2626.39" + attribute \src "ls180.v:2639.6-2639.39" wire \builder_csrbank14_tuning_word0_we - attribute \src "ls180.v:2621.12-2621.44" + attribute \src "ls180.v:2634.12-2634.44" wire width 8 \builder_csrbank14_tuning_word1_r - attribute \src "ls180.v:2620.6-2620.39" + attribute \src "ls180.v:2633.6-2633.39" wire \builder_csrbank14_tuning_word1_re - attribute \src "ls180.v:2623.12-2623.44" + attribute \src "ls180.v:2636.12-2636.44" wire width 8 \builder_csrbank14_tuning_word1_w - attribute \src "ls180.v:2622.6-2622.39" + attribute \src "ls180.v:2635.6-2635.39" wire \builder_csrbank14_tuning_word1_we - attribute \src "ls180.v:2617.12-2617.44" + attribute \src "ls180.v:2630.12-2630.44" wire width 8 \builder_csrbank14_tuning_word2_r - attribute \src "ls180.v:2616.6-2616.39" + attribute \src "ls180.v:2629.6-2629.39" wire \builder_csrbank14_tuning_word2_re - attribute \src "ls180.v:2619.12-2619.44" + attribute \src "ls180.v:2632.12-2632.44" wire width 8 \builder_csrbank14_tuning_word2_w - attribute \src "ls180.v:2618.6-2618.39" + attribute \src "ls180.v:2631.6-2631.39" wire \builder_csrbank14_tuning_word2_we - attribute \src "ls180.v:2613.12-2613.44" + attribute \src "ls180.v:2626.12-2626.44" wire width 8 \builder_csrbank14_tuning_word3_r - attribute \src "ls180.v:2612.6-2612.39" + attribute \src "ls180.v:2625.6-2625.39" wire \builder_csrbank14_tuning_word3_re - attribute \src "ls180.v:2615.12-2615.44" + attribute \src "ls180.v:2628.12-2628.44" wire width 8 \builder_csrbank14_tuning_word3_w - attribute \src "ls180.v:2614.6-2614.39" + attribute \src "ls180.v:2627.6-2627.39" wire \builder_csrbank14_tuning_word3_we - attribute \src "ls180.v:2000.12-2000.34" + attribute \src "ls180.v:2013.12-2013.34" wire width 8 \builder_csrbank1_in0_r - attribute \src "ls180.v:1999.6-1999.29" + attribute \src "ls180.v:2012.6-2012.29" wire \builder_csrbank1_in0_re - attribute \src "ls180.v:2002.12-2002.34" + attribute \src "ls180.v:2015.12-2015.34" wire width 8 \builder_csrbank1_in0_w - attribute \src "ls180.v:2001.6-2001.29" + attribute \src "ls180.v:2014.6-2014.29" wire \builder_csrbank1_in0_we - attribute \src "ls180.v:1996.12-1996.34" + attribute \src "ls180.v:2009.12-2009.34" wire width 8 \builder_csrbank1_in1_r - attribute \src "ls180.v:1995.6-1995.29" + attribute \src "ls180.v:2008.6-2008.29" wire \builder_csrbank1_in1_re - attribute \src "ls180.v:1998.12-1998.34" + attribute \src "ls180.v:2011.12-2011.34" wire width 8 \builder_csrbank1_in1_w - attribute \src "ls180.v:1997.6-1997.29" + attribute \src "ls180.v:2010.6-2010.29" wire \builder_csrbank1_in1_we - attribute \src "ls180.v:1992.12-1992.34" + attribute \src "ls180.v:2005.12-2005.34" wire width 8 \builder_csrbank1_oe0_r - attribute \src "ls180.v:1991.6-1991.29" + attribute \src "ls180.v:2004.6-2004.29" wire \builder_csrbank1_oe0_re - attribute \src "ls180.v:1994.12-1994.34" + attribute \src "ls180.v:2007.12-2007.34" wire width 8 \builder_csrbank1_oe0_w - attribute \src "ls180.v:1993.6-1993.29" + attribute \src "ls180.v:2006.6-2006.29" wire \builder_csrbank1_oe0_we - attribute \src "ls180.v:1988.12-1988.34" + attribute \src "ls180.v:2001.12-2001.34" wire width 8 \builder_csrbank1_oe1_r - attribute \src "ls180.v:1987.6-1987.29" + attribute \src "ls180.v:2000.6-2000.29" wire \builder_csrbank1_oe1_re - attribute \src "ls180.v:1990.12-1990.34" + attribute \src "ls180.v:2003.12-2003.34" wire width 8 \builder_csrbank1_oe1_w - attribute \src "ls180.v:1989.6-1989.29" + attribute \src "ls180.v:2002.6-2002.29" wire \builder_csrbank1_oe1_we - attribute \src "ls180.v:2008.12-2008.35" + attribute \src "ls180.v:2021.12-2021.35" wire width 8 \builder_csrbank1_out0_r - attribute \src "ls180.v:2007.6-2007.30" + attribute \src "ls180.v:2020.6-2020.30" wire \builder_csrbank1_out0_re - attribute \src "ls180.v:2010.12-2010.35" + attribute \src "ls180.v:2023.12-2023.35" wire width 8 \builder_csrbank1_out0_w - attribute \src "ls180.v:2009.6-2009.30" + attribute \src "ls180.v:2022.6-2022.30" wire \builder_csrbank1_out0_we - attribute \src "ls180.v:2004.12-2004.35" + attribute \src "ls180.v:2017.12-2017.35" wire width 8 \builder_csrbank1_out1_r - attribute \src "ls180.v:2003.6-2003.30" + attribute \src "ls180.v:2016.6-2016.30" wire \builder_csrbank1_out1_re - attribute \src "ls180.v:2006.12-2006.35" + attribute \src "ls180.v:2019.12-2019.35" wire width 8 \builder_csrbank1_out1_w - attribute \src "ls180.v:2005.6-2005.30" + attribute \src "ls180.v:2018.6-2018.30" wire \builder_csrbank1_out1_we - attribute \src "ls180.v:2011.6-2011.26" + attribute \src "ls180.v:2024.6-2024.26" wire \builder_csrbank1_sel - attribute \src "ls180.v:2021.6-2021.26" + attribute \src "ls180.v:2034.6-2034.26" wire \builder_csrbank2_r_r - attribute \src "ls180.v:2020.6-2020.27" + attribute \src "ls180.v:2033.6-2033.27" wire \builder_csrbank2_r_re - attribute \src "ls180.v:2023.6-2023.26" + attribute \src "ls180.v:2036.6-2036.26" wire \builder_csrbank2_r_w - attribute \src "ls180.v:2022.6-2022.27" + attribute \src "ls180.v:2035.6-2035.27" wire \builder_csrbank2_r_we - attribute \src "ls180.v:2024.6-2024.26" + attribute \src "ls180.v:2037.6-2037.26" wire \builder_csrbank2_sel - attribute \src "ls180.v:2017.12-2017.33" + attribute \src "ls180.v:2030.12-2030.33" wire width 3 \builder_csrbank2_w0_r - attribute \src "ls180.v:2016.6-2016.28" + attribute \src "ls180.v:2029.6-2029.28" wire \builder_csrbank2_w0_re - attribute \src "ls180.v:2019.12-2019.33" + attribute \src "ls180.v:2032.12-2032.33" wire width 3 \builder_csrbank2_w0_w - attribute \src "ls180.v:2018.6-2018.28" + attribute \src "ls180.v:2031.6-2031.28" wire \builder_csrbank2_w0_we - attribute \src "ls180.v:2030.6-2030.32" + attribute \src "ls180.v:2043.6-2043.32" wire \builder_csrbank3_enable0_r - attribute \src "ls180.v:2029.6-2029.33" + attribute \src "ls180.v:2042.6-2042.33" wire \builder_csrbank3_enable0_re - attribute \src "ls180.v:2032.6-2032.32" + attribute \src "ls180.v:2045.6-2045.32" wire \builder_csrbank3_enable0_w - attribute \src "ls180.v:2031.6-2031.33" + attribute \src "ls180.v:2044.6-2044.33" wire \builder_csrbank3_enable0_we - attribute \src "ls180.v:2062.12-2062.38" + attribute \src "ls180.v:2075.12-2075.38" wire width 8 \builder_csrbank3_period0_r - attribute \src "ls180.v:2061.6-2061.33" + attribute \src "ls180.v:2074.6-2074.33" wire \builder_csrbank3_period0_re - attribute \src "ls180.v:2064.12-2064.38" + attribute \src "ls180.v:2077.12-2077.38" wire width 8 \builder_csrbank3_period0_w - attribute \src "ls180.v:2063.6-2063.33" + attribute \src "ls180.v:2076.6-2076.33" wire \builder_csrbank3_period0_we - attribute \src "ls180.v:2058.12-2058.38" + attribute \src "ls180.v:2071.12-2071.38" wire width 8 \builder_csrbank3_period1_r - attribute \src "ls180.v:2057.6-2057.33" + attribute \src "ls180.v:2070.6-2070.33" wire \builder_csrbank3_period1_re - attribute \src "ls180.v:2060.12-2060.38" + attribute \src "ls180.v:2073.12-2073.38" wire width 8 \builder_csrbank3_period1_w - attribute \src "ls180.v:2059.6-2059.33" + attribute \src "ls180.v:2072.6-2072.33" wire \builder_csrbank3_period1_we - attribute \src "ls180.v:2054.12-2054.38" + attribute \src "ls180.v:2067.12-2067.38" wire width 8 \builder_csrbank3_period2_r - attribute \src "ls180.v:2053.6-2053.33" + attribute \src "ls180.v:2066.6-2066.33" wire \builder_csrbank3_period2_re - attribute \src "ls180.v:2056.12-2056.38" + attribute \src "ls180.v:2069.12-2069.38" wire width 8 \builder_csrbank3_period2_w - attribute \src "ls180.v:2055.6-2055.33" + attribute \src "ls180.v:2068.6-2068.33" wire \builder_csrbank3_period2_we - attribute \src "ls180.v:2050.12-2050.38" + attribute \src "ls180.v:2063.12-2063.38" wire width 8 \builder_csrbank3_period3_r - attribute \src "ls180.v:2049.6-2049.33" + attribute \src "ls180.v:2062.6-2062.33" wire \builder_csrbank3_period3_re - attribute \src "ls180.v:2052.12-2052.38" + attribute \src "ls180.v:2065.12-2065.38" wire width 8 \builder_csrbank3_period3_w - attribute \src "ls180.v:2051.6-2051.33" + attribute \src "ls180.v:2064.6-2064.33" wire \builder_csrbank3_period3_we - attribute \src "ls180.v:2065.6-2065.26" + attribute \src "ls180.v:2078.6-2078.26" wire \builder_csrbank3_sel - attribute \src "ls180.v:2046.12-2046.37" + attribute \src "ls180.v:2059.12-2059.37" wire width 8 \builder_csrbank3_width0_r - attribute \src "ls180.v:2045.6-2045.32" + attribute \src "ls180.v:2058.6-2058.32" wire \builder_csrbank3_width0_re - attribute \src "ls180.v:2048.12-2048.37" + attribute \src "ls180.v:2061.12-2061.37" wire width 8 \builder_csrbank3_width0_w - attribute \src "ls180.v:2047.6-2047.32" + attribute \src "ls180.v:2060.6-2060.32" wire \builder_csrbank3_width0_we - attribute \src "ls180.v:2042.12-2042.37" + attribute \src "ls180.v:2055.12-2055.37" wire width 8 \builder_csrbank3_width1_r - attribute \src "ls180.v:2041.6-2041.32" + attribute \src "ls180.v:2054.6-2054.32" wire \builder_csrbank3_width1_re - attribute \src "ls180.v:2044.12-2044.37" + attribute \src "ls180.v:2057.12-2057.37" wire width 8 \builder_csrbank3_width1_w - attribute \src "ls180.v:2043.6-2043.32" + attribute \src "ls180.v:2056.6-2056.32" wire \builder_csrbank3_width1_we - attribute \src "ls180.v:2038.12-2038.37" + attribute \src "ls180.v:2051.12-2051.37" wire width 8 \builder_csrbank3_width2_r - attribute \src "ls180.v:2037.6-2037.32" + attribute \src "ls180.v:2050.6-2050.32" wire \builder_csrbank3_width2_re - attribute \src "ls180.v:2040.12-2040.37" + attribute \src "ls180.v:2053.12-2053.37" wire width 8 \builder_csrbank3_width2_w - attribute \src "ls180.v:2039.6-2039.32" + attribute \src "ls180.v:2052.6-2052.32" wire \builder_csrbank3_width2_we - attribute \src "ls180.v:2034.12-2034.37" + attribute \src "ls180.v:2047.12-2047.37" wire width 8 \builder_csrbank3_width3_r - attribute \src "ls180.v:2033.6-2033.32" + attribute \src "ls180.v:2046.6-2046.32" wire \builder_csrbank3_width3_re - attribute \src "ls180.v:2036.12-2036.37" + attribute \src "ls180.v:2049.12-2049.37" wire width 8 \builder_csrbank3_width3_w - attribute \src "ls180.v:2035.6-2035.32" + attribute \src "ls180.v:2048.6-2048.32" wire \builder_csrbank3_width3_we - attribute \src "ls180.v:2071.6-2071.32" + attribute \src "ls180.v:2084.6-2084.32" wire \builder_csrbank4_enable0_r - attribute \src "ls180.v:2070.6-2070.33" + attribute \src "ls180.v:2083.6-2083.33" wire \builder_csrbank4_enable0_re - attribute \src "ls180.v:2073.6-2073.32" + attribute \src "ls180.v:2086.6-2086.32" wire \builder_csrbank4_enable0_w - attribute \src "ls180.v:2072.6-2072.33" + attribute \src "ls180.v:2085.6-2085.33" wire \builder_csrbank4_enable0_we - attribute \src "ls180.v:2103.12-2103.38" + attribute \src "ls180.v:2116.12-2116.38" wire width 8 \builder_csrbank4_period0_r - attribute \src "ls180.v:2102.6-2102.33" + attribute \src "ls180.v:2115.6-2115.33" wire \builder_csrbank4_period0_re - attribute \src "ls180.v:2105.12-2105.38" + attribute \src "ls180.v:2118.12-2118.38" wire width 8 \builder_csrbank4_period0_w - attribute \src "ls180.v:2104.6-2104.33" + attribute \src "ls180.v:2117.6-2117.33" wire \builder_csrbank4_period0_we - attribute \src "ls180.v:2099.12-2099.38" + attribute \src "ls180.v:2112.12-2112.38" wire width 8 \builder_csrbank4_period1_r - attribute \src "ls180.v:2098.6-2098.33" + attribute \src "ls180.v:2111.6-2111.33" wire \builder_csrbank4_period1_re - attribute \src "ls180.v:2101.12-2101.38" + attribute \src "ls180.v:2114.12-2114.38" wire width 8 \builder_csrbank4_period1_w - attribute \src "ls180.v:2100.6-2100.33" + attribute \src "ls180.v:2113.6-2113.33" wire \builder_csrbank4_period1_we - attribute \src "ls180.v:2095.12-2095.38" + attribute \src "ls180.v:2108.12-2108.38" wire width 8 \builder_csrbank4_period2_r - attribute \src "ls180.v:2094.6-2094.33" + attribute \src "ls180.v:2107.6-2107.33" wire \builder_csrbank4_period2_re - attribute \src "ls180.v:2097.12-2097.38" + attribute \src "ls180.v:2110.12-2110.38" wire width 8 \builder_csrbank4_period2_w - attribute \src "ls180.v:2096.6-2096.33" + attribute \src "ls180.v:2109.6-2109.33" wire \builder_csrbank4_period2_we - attribute \src "ls180.v:2091.12-2091.38" + attribute \src "ls180.v:2104.12-2104.38" wire width 8 \builder_csrbank4_period3_r - attribute \src "ls180.v:2090.6-2090.33" + attribute \src "ls180.v:2103.6-2103.33" wire \builder_csrbank4_period3_re - attribute \src "ls180.v:2093.12-2093.38" + attribute \src "ls180.v:2106.12-2106.38" wire width 8 \builder_csrbank4_period3_w - attribute \src "ls180.v:2092.6-2092.33" + attribute \src "ls180.v:2105.6-2105.33" wire \builder_csrbank4_period3_we - attribute \src "ls180.v:2106.6-2106.26" + attribute \src "ls180.v:2119.6-2119.26" wire \builder_csrbank4_sel - attribute \src "ls180.v:2087.12-2087.37" + attribute \src "ls180.v:2100.12-2100.37" wire width 8 \builder_csrbank4_width0_r - attribute \src "ls180.v:2086.6-2086.32" + attribute \src "ls180.v:2099.6-2099.32" wire \builder_csrbank4_width0_re - attribute \src "ls180.v:2089.12-2089.37" + attribute \src "ls180.v:2102.12-2102.37" wire width 8 \builder_csrbank4_width0_w - attribute \src "ls180.v:2088.6-2088.32" + attribute \src "ls180.v:2101.6-2101.32" wire \builder_csrbank4_width0_we - attribute \src "ls180.v:2083.12-2083.37" + attribute \src "ls180.v:2096.12-2096.37" wire width 8 \builder_csrbank4_width1_r - attribute \src "ls180.v:2082.6-2082.32" + attribute \src "ls180.v:2095.6-2095.32" wire \builder_csrbank4_width1_re - attribute \src "ls180.v:2085.12-2085.37" + attribute \src "ls180.v:2098.12-2098.37" wire width 8 \builder_csrbank4_width1_w - attribute \src "ls180.v:2084.6-2084.32" + attribute \src "ls180.v:2097.6-2097.32" wire \builder_csrbank4_width1_we - attribute \src "ls180.v:2079.12-2079.37" + attribute \src "ls180.v:2092.12-2092.37" wire width 8 \builder_csrbank4_width2_r - attribute \src "ls180.v:2078.6-2078.32" + attribute \src "ls180.v:2091.6-2091.32" wire \builder_csrbank4_width2_re - attribute \src "ls180.v:2081.12-2081.37" + attribute \src "ls180.v:2094.12-2094.37" wire width 8 \builder_csrbank4_width2_w - attribute \src "ls180.v:2080.6-2080.32" + attribute \src "ls180.v:2093.6-2093.32" wire \builder_csrbank4_width2_we - attribute \src "ls180.v:2075.12-2075.37" + attribute \src "ls180.v:2088.12-2088.37" wire width 8 \builder_csrbank4_width3_r - attribute \src "ls180.v:2074.6-2074.32" + attribute \src "ls180.v:2087.6-2087.32" wire \builder_csrbank4_width3_re - attribute \src "ls180.v:2077.12-2077.37" + attribute \src "ls180.v:2090.12-2090.37" wire width 8 \builder_csrbank4_width3_w - attribute \src "ls180.v:2076.6-2076.32" + attribute \src "ls180.v:2089.6-2089.32" wire \builder_csrbank4_width3_we - attribute \src "ls180.v:2140.12-2140.40" + attribute \src "ls180.v:2153.12-2153.40" wire width 8 \builder_csrbank5_dma_base0_r - attribute \src "ls180.v:2139.6-2139.35" + attribute \src "ls180.v:2152.6-2152.35" wire \builder_csrbank5_dma_base0_re - attribute \src "ls180.v:2142.12-2142.40" + attribute \src "ls180.v:2155.12-2155.40" wire width 8 \builder_csrbank5_dma_base0_w - attribute \src "ls180.v:2141.6-2141.35" + attribute \src "ls180.v:2154.6-2154.35" wire \builder_csrbank5_dma_base0_we - attribute \src "ls180.v:2136.12-2136.40" + attribute \src "ls180.v:2149.12-2149.40" wire width 8 \builder_csrbank5_dma_base1_r - attribute \src "ls180.v:2135.6-2135.35" + attribute \src "ls180.v:2148.6-2148.35" wire \builder_csrbank5_dma_base1_re - attribute \src "ls180.v:2138.12-2138.40" + attribute \src "ls180.v:2151.12-2151.40" wire width 8 \builder_csrbank5_dma_base1_w - attribute \src "ls180.v:2137.6-2137.35" + attribute \src "ls180.v:2150.6-2150.35" wire \builder_csrbank5_dma_base1_we - attribute \src "ls180.v:2132.12-2132.40" + attribute \src "ls180.v:2145.12-2145.40" wire width 8 \builder_csrbank5_dma_base2_r - attribute \src "ls180.v:2131.6-2131.35" + attribute \src "ls180.v:2144.6-2144.35" wire \builder_csrbank5_dma_base2_re - attribute \src "ls180.v:2134.12-2134.40" + attribute \src "ls180.v:2147.12-2147.40" wire width 8 \builder_csrbank5_dma_base2_w - attribute \src "ls180.v:2133.6-2133.35" + attribute \src "ls180.v:2146.6-2146.35" wire \builder_csrbank5_dma_base2_we - attribute \src "ls180.v:2128.12-2128.40" + attribute \src "ls180.v:2141.12-2141.40" wire width 8 \builder_csrbank5_dma_base3_r - attribute \src "ls180.v:2127.6-2127.35" + attribute \src "ls180.v:2140.6-2140.35" wire \builder_csrbank5_dma_base3_re - attribute \src "ls180.v:2130.12-2130.40" + attribute \src "ls180.v:2143.12-2143.40" wire width 8 \builder_csrbank5_dma_base3_w - attribute \src "ls180.v:2129.6-2129.35" + attribute \src "ls180.v:2142.6-2142.35" wire \builder_csrbank5_dma_base3_we - attribute \src "ls180.v:2124.12-2124.40" + attribute \src "ls180.v:2137.12-2137.40" wire width 8 \builder_csrbank5_dma_base4_r - attribute \src "ls180.v:2123.6-2123.35" + attribute \src "ls180.v:2136.6-2136.35" wire \builder_csrbank5_dma_base4_re - attribute \src "ls180.v:2126.12-2126.40" + attribute \src "ls180.v:2139.12-2139.40" wire width 8 \builder_csrbank5_dma_base4_w - attribute \src "ls180.v:2125.6-2125.35" + attribute \src "ls180.v:2138.6-2138.35" wire \builder_csrbank5_dma_base4_we - attribute \src "ls180.v:2120.12-2120.40" + attribute \src "ls180.v:2133.12-2133.40" wire width 8 \builder_csrbank5_dma_base5_r - attribute \src "ls180.v:2119.6-2119.35" + attribute \src "ls180.v:2132.6-2132.35" wire \builder_csrbank5_dma_base5_re - attribute \src "ls180.v:2122.12-2122.40" + attribute \src "ls180.v:2135.12-2135.40" wire width 8 \builder_csrbank5_dma_base5_w - attribute \src "ls180.v:2121.6-2121.35" + attribute \src "ls180.v:2134.6-2134.35" wire \builder_csrbank5_dma_base5_we - attribute \src "ls180.v:2116.12-2116.40" + attribute \src "ls180.v:2129.12-2129.40" wire width 8 \builder_csrbank5_dma_base6_r - attribute \src "ls180.v:2115.6-2115.35" + attribute \src "ls180.v:2128.6-2128.35" wire \builder_csrbank5_dma_base6_re - attribute \src "ls180.v:2118.12-2118.40" + attribute \src "ls180.v:2131.12-2131.40" wire width 8 \builder_csrbank5_dma_base6_w - attribute \src "ls180.v:2117.6-2117.35" + attribute \src "ls180.v:2130.6-2130.35" wire \builder_csrbank5_dma_base6_we - attribute \src "ls180.v:2112.12-2112.40" + attribute \src "ls180.v:2125.12-2125.40" wire width 8 \builder_csrbank5_dma_base7_r - attribute \src "ls180.v:2111.6-2111.35" + attribute \src "ls180.v:2124.6-2124.35" wire \builder_csrbank5_dma_base7_re - attribute \src "ls180.v:2114.12-2114.40" + attribute \src "ls180.v:2127.12-2127.40" wire width 8 \builder_csrbank5_dma_base7_w - attribute \src "ls180.v:2113.6-2113.35" + attribute \src "ls180.v:2126.6-2126.35" wire \builder_csrbank5_dma_base7_we - attribute \src "ls180.v:2164.6-2164.33" + attribute \src "ls180.v:2177.6-2177.33" wire \builder_csrbank5_dma_done_r - attribute \src "ls180.v:2163.6-2163.34" + attribute \src "ls180.v:2176.6-2176.34" wire \builder_csrbank5_dma_done_re - attribute \src "ls180.v:2166.6-2166.33" + attribute \src "ls180.v:2179.6-2179.33" wire \builder_csrbank5_dma_done_w - attribute \src "ls180.v:2165.6-2165.34" + attribute \src "ls180.v:2178.6-2178.34" wire \builder_csrbank5_dma_done_we - attribute \src "ls180.v:2160.6-2160.36" + attribute \src "ls180.v:2173.6-2173.36" wire \builder_csrbank5_dma_enable0_r - attribute \src "ls180.v:2159.6-2159.37" + attribute \src "ls180.v:2172.6-2172.37" wire \builder_csrbank5_dma_enable0_re - attribute \src "ls180.v:2162.6-2162.36" + attribute \src "ls180.v:2175.6-2175.36" wire \builder_csrbank5_dma_enable0_w - attribute \src "ls180.v:2161.6-2161.37" + attribute \src "ls180.v:2174.6-2174.37" wire \builder_csrbank5_dma_enable0_we - attribute \src "ls180.v:2156.12-2156.42" + attribute \src "ls180.v:2169.12-2169.42" wire width 8 \builder_csrbank5_dma_length0_r - attribute \src "ls180.v:2155.6-2155.37" + attribute \src "ls180.v:2168.6-2168.37" wire \builder_csrbank5_dma_length0_re - attribute \src "ls180.v:2158.12-2158.42" + attribute \src "ls180.v:2171.12-2171.42" wire width 8 \builder_csrbank5_dma_length0_w - attribute \src "ls180.v:2157.6-2157.37" + attribute \src "ls180.v:2170.6-2170.37" wire \builder_csrbank5_dma_length0_we - attribute \src "ls180.v:2152.12-2152.42" + attribute \src "ls180.v:2165.12-2165.42" wire width 8 \builder_csrbank5_dma_length1_r - attribute \src "ls180.v:2151.6-2151.37" + attribute \src "ls180.v:2164.6-2164.37" wire \builder_csrbank5_dma_length1_re - attribute \src "ls180.v:2154.12-2154.42" + attribute \src "ls180.v:2167.12-2167.42" wire width 8 \builder_csrbank5_dma_length1_w - attribute \src "ls180.v:2153.6-2153.37" + attribute \src "ls180.v:2166.6-2166.37" wire \builder_csrbank5_dma_length1_we - attribute \src "ls180.v:2148.12-2148.42" + attribute \src "ls180.v:2161.12-2161.42" wire width 8 \builder_csrbank5_dma_length2_r - attribute \src "ls180.v:2147.6-2147.37" + attribute \src "ls180.v:2160.6-2160.37" wire \builder_csrbank5_dma_length2_re - attribute \src "ls180.v:2150.12-2150.42" + attribute \src "ls180.v:2163.12-2163.42" wire width 8 \builder_csrbank5_dma_length2_w - attribute \src "ls180.v:2149.6-2149.37" + attribute \src "ls180.v:2162.6-2162.37" wire \builder_csrbank5_dma_length2_we - attribute \src "ls180.v:2144.12-2144.42" + attribute \src "ls180.v:2157.12-2157.42" wire width 8 \builder_csrbank5_dma_length3_r - attribute \src "ls180.v:2143.6-2143.37" + attribute \src "ls180.v:2156.6-2156.37" wire \builder_csrbank5_dma_length3_re - attribute \src "ls180.v:2146.12-2146.42" + attribute \src "ls180.v:2159.12-2159.42" wire width 8 \builder_csrbank5_dma_length3_w - attribute \src "ls180.v:2145.6-2145.37" + attribute \src "ls180.v:2158.6-2158.37" wire \builder_csrbank5_dma_length3_we - attribute \src "ls180.v:2168.6-2168.34" + attribute \src "ls180.v:2181.6-2181.34" wire \builder_csrbank5_dma_loop0_r - attribute \src "ls180.v:2167.6-2167.35" + attribute \src "ls180.v:2180.6-2180.35" wire \builder_csrbank5_dma_loop0_re - attribute \src "ls180.v:2170.6-2170.34" + attribute \src "ls180.v:2183.6-2183.34" wire \builder_csrbank5_dma_loop0_w - attribute \src "ls180.v:2169.6-2169.35" + attribute \src "ls180.v:2182.6-2182.35" wire \builder_csrbank5_dma_loop0_we - attribute \src "ls180.v:2171.6-2171.26" + attribute \src "ls180.v:2184.6-2184.26" wire \builder_csrbank5_sel - attribute \src "ls180.v:2301.12-2301.43" + attribute \src "ls180.v:2314.12-2314.43" wire width 8 \builder_csrbank6_block_count0_r - attribute \src "ls180.v:2300.6-2300.38" + attribute \src "ls180.v:2313.6-2313.38" wire \builder_csrbank6_block_count0_re - attribute \src "ls180.v:2303.12-2303.43" + attribute \src "ls180.v:2316.12-2316.43" wire width 8 \builder_csrbank6_block_count0_w - attribute \src "ls180.v:2302.6-2302.38" + attribute \src "ls180.v:2315.6-2315.38" wire \builder_csrbank6_block_count0_we - attribute \src "ls180.v:2297.12-2297.43" + attribute \src "ls180.v:2310.12-2310.43" wire width 8 \builder_csrbank6_block_count1_r - attribute \src "ls180.v:2296.6-2296.38" + attribute \src "ls180.v:2309.6-2309.38" wire \builder_csrbank6_block_count1_re - attribute \src "ls180.v:2299.12-2299.43" + attribute \src "ls180.v:2312.12-2312.43" wire width 8 \builder_csrbank6_block_count1_w - attribute \src "ls180.v:2298.6-2298.38" + attribute \src "ls180.v:2311.6-2311.38" wire \builder_csrbank6_block_count1_we - attribute \src "ls180.v:2293.12-2293.43" + attribute \src "ls180.v:2306.12-2306.43" wire width 8 \builder_csrbank6_block_count2_r - attribute \src "ls180.v:2292.6-2292.38" + attribute \src "ls180.v:2305.6-2305.38" wire \builder_csrbank6_block_count2_re - attribute \src "ls180.v:2295.12-2295.43" + attribute \src "ls180.v:2308.12-2308.43" wire width 8 \builder_csrbank6_block_count2_w - attribute \src "ls180.v:2294.6-2294.38" + attribute \src "ls180.v:2307.6-2307.38" wire \builder_csrbank6_block_count2_we - attribute \src "ls180.v:2289.12-2289.43" + attribute \src "ls180.v:2302.12-2302.43" wire width 8 \builder_csrbank6_block_count3_r - attribute \src "ls180.v:2288.6-2288.38" + attribute \src "ls180.v:2301.6-2301.38" wire \builder_csrbank6_block_count3_re - attribute \src "ls180.v:2291.12-2291.43" + attribute \src "ls180.v:2304.12-2304.43" wire width 8 \builder_csrbank6_block_count3_w - attribute \src "ls180.v:2290.6-2290.38" + attribute \src "ls180.v:2303.6-2303.38" wire \builder_csrbank6_block_count3_we - attribute \src "ls180.v:2285.12-2285.44" + attribute \src "ls180.v:2298.12-2298.44" wire width 8 \builder_csrbank6_block_length0_r - attribute \src "ls180.v:2284.6-2284.39" + attribute \src "ls180.v:2297.6-2297.39" wire \builder_csrbank6_block_length0_re - attribute \src "ls180.v:2287.12-2287.44" + attribute \src "ls180.v:2300.12-2300.44" wire width 8 \builder_csrbank6_block_length0_w - attribute \src "ls180.v:2286.6-2286.39" + attribute \src "ls180.v:2299.6-2299.39" wire \builder_csrbank6_block_length0_we - attribute \src "ls180.v:2281.12-2281.44" + attribute \src "ls180.v:2294.12-2294.44" wire width 2 \builder_csrbank6_block_length1_r - attribute \src "ls180.v:2280.6-2280.39" + attribute \src "ls180.v:2293.6-2293.39" wire \builder_csrbank6_block_length1_re - attribute \src "ls180.v:2283.12-2283.44" + attribute \src "ls180.v:2296.12-2296.44" wire width 2 \builder_csrbank6_block_length1_w - attribute \src "ls180.v:2282.6-2282.39" + attribute \src "ls180.v:2295.6-2295.39" wire \builder_csrbank6_block_length1_we - attribute \src "ls180.v:2189.12-2189.44" + attribute \src "ls180.v:2202.12-2202.44" wire width 8 \builder_csrbank6_cmd_argument0_r - attribute \src "ls180.v:2188.6-2188.39" + attribute \src "ls180.v:2201.6-2201.39" wire \builder_csrbank6_cmd_argument0_re - attribute \src "ls180.v:2191.12-2191.44" + attribute \src "ls180.v:2204.12-2204.44" wire width 8 \builder_csrbank6_cmd_argument0_w - attribute \src "ls180.v:2190.6-2190.39" + attribute \src "ls180.v:2203.6-2203.39" wire \builder_csrbank6_cmd_argument0_we - attribute \src "ls180.v:2185.12-2185.44" + attribute \src "ls180.v:2198.12-2198.44" wire width 8 \builder_csrbank6_cmd_argument1_r - attribute \src "ls180.v:2184.6-2184.39" + attribute \src "ls180.v:2197.6-2197.39" wire \builder_csrbank6_cmd_argument1_re - attribute \src "ls180.v:2187.12-2187.44" + attribute \src "ls180.v:2200.12-2200.44" wire width 8 \builder_csrbank6_cmd_argument1_w - attribute \src "ls180.v:2186.6-2186.39" + attribute \src "ls180.v:2199.6-2199.39" wire \builder_csrbank6_cmd_argument1_we - attribute \src "ls180.v:2181.12-2181.44" + attribute \src "ls180.v:2194.12-2194.44" wire width 8 \builder_csrbank6_cmd_argument2_r - attribute \src "ls180.v:2180.6-2180.39" + attribute \src "ls180.v:2193.6-2193.39" wire \builder_csrbank6_cmd_argument2_re - attribute \src "ls180.v:2183.12-2183.44" + attribute \src "ls180.v:2196.12-2196.44" wire width 8 \builder_csrbank6_cmd_argument2_w - attribute \src "ls180.v:2182.6-2182.39" + attribute \src "ls180.v:2195.6-2195.39" wire \builder_csrbank6_cmd_argument2_we - attribute \src "ls180.v:2177.12-2177.44" + attribute \src "ls180.v:2190.12-2190.44" wire width 8 \builder_csrbank6_cmd_argument3_r - attribute \src "ls180.v:2176.6-2176.39" + attribute \src "ls180.v:2189.6-2189.39" wire \builder_csrbank6_cmd_argument3_re - attribute \src "ls180.v:2179.12-2179.44" + attribute \src "ls180.v:2192.12-2192.44" wire width 8 \builder_csrbank6_cmd_argument3_w - attribute \src "ls180.v:2178.6-2178.39" + attribute \src "ls180.v:2191.6-2191.39" wire \builder_csrbank6_cmd_argument3_we - attribute \src "ls180.v:2205.12-2205.43" + attribute \src "ls180.v:2218.12-2218.43" wire width 8 \builder_csrbank6_cmd_command0_r - attribute \src "ls180.v:2204.6-2204.38" + attribute \src "ls180.v:2217.6-2217.38" wire \builder_csrbank6_cmd_command0_re - attribute \src "ls180.v:2207.12-2207.43" + attribute \src "ls180.v:2220.12-2220.43" wire width 8 \builder_csrbank6_cmd_command0_w - attribute \src "ls180.v:2206.6-2206.38" + attribute \src "ls180.v:2219.6-2219.38" wire \builder_csrbank6_cmd_command0_we - attribute \src "ls180.v:2201.12-2201.43" + attribute \src "ls180.v:2214.12-2214.43" wire width 8 \builder_csrbank6_cmd_command1_r - attribute \src "ls180.v:2200.6-2200.38" + attribute \src "ls180.v:2213.6-2213.38" wire \builder_csrbank6_cmd_command1_re - attribute \src "ls180.v:2203.12-2203.43" + attribute \src "ls180.v:2216.12-2216.43" wire width 8 \builder_csrbank6_cmd_command1_w - attribute \src "ls180.v:2202.6-2202.38" + attribute \src "ls180.v:2215.6-2215.38" wire \builder_csrbank6_cmd_command1_we - attribute \src "ls180.v:2197.12-2197.43" + attribute \src "ls180.v:2210.12-2210.43" wire width 8 \builder_csrbank6_cmd_command2_r - attribute \src "ls180.v:2196.6-2196.38" + attribute \src "ls180.v:2209.6-2209.38" wire \builder_csrbank6_cmd_command2_re - attribute \src "ls180.v:2199.12-2199.43" + attribute \src "ls180.v:2212.12-2212.43" wire width 8 \builder_csrbank6_cmd_command2_w - attribute \src "ls180.v:2198.6-2198.38" + attribute \src "ls180.v:2211.6-2211.38" wire \builder_csrbank6_cmd_command2_we - attribute \src "ls180.v:2193.12-2193.43" + attribute \src "ls180.v:2206.12-2206.43" wire width 8 \builder_csrbank6_cmd_command3_r - attribute \src "ls180.v:2192.6-2192.38" + attribute \src "ls180.v:2205.6-2205.38" wire \builder_csrbank6_cmd_command3_re - attribute \src "ls180.v:2195.12-2195.43" + attribute \src "ls180.v:2208.12-2208.43" wire width 8 \builder_csrbank6_cmd_command3_w - attribute \src "ls180.v:2194.6-2194.38" + attribute \src "ls180.v:2207.6-2207.38" wire \builder_csrbank6_cmd_command3_we - attribute \src "ls180.v:2273.12-2273.40" + attribute \src "ls180.v:2286.12-2286.40" wire width 4 \builder_csrbank6_cmd_event_r - attribute \src "ls180.v:2272.6-2272.35" + attribute \src "ls180.v:2285.6-2285.35" wire \builder_csrbank6_cmd_event_re - attribute \src "ls180.v:2275.12-2275.40" + attribute \src "ls180.v:2288.12-2288.40" wire width 4 \builder_csrbank6_cmd_event_w - attribute \src "ls180.v:2274.6-2274.35" + attribute \src "ls180.v:2287.6-2287.35" wire \builder_csrbank6_cmd_event_we - attribute \src "ls180.v:2269.12-2269.44" + attribute \src "ls180.v:2282.12-2282.44" wire width 8 \builder_csrbank6_cmd_response0_r - attribute \src "ls180.v:2268.6-2268.39" + attribute \src "ls180.v:2281.6-2281.39" wire \builder_csrbank6_cmd_response0_re - attribute \src "ls180.v:2271.12-2271.44" + attribute \src "ls180.v:2284.12-2284.44" wire width 8 \builder_csrbank6_cmd_response0_w - attribute \src "ls180.v:2270.6-2270.39" + attribute \src "ls180.v:2283.6-2283.39" wire \builder_csrbank6_cmd_response0_we - attribute \src "ls180.v:2229.12-2229.45" + attribute \src "ls180.v:2242.12-2242.45" wire width 8 \builder_csrbank6_cmd_response10_r - attribute \src "ls180.v:2228.6-2228.40" + attribute \src "ls180.v:2241.6-2241.40" wire \builder_csrbank6_cmd_response10_re - attribute \src "ls180.v:2231.12-2231.45" + attribute \src "ls180.v:2244.12-2244.45" wire width 8 \builder_csrbank6_cmd_response10_w - attribute \src "ls180.v:2230.6-2230.40" + attribute \src "ls180.v:2243.6-2243.40" wire \builder_csrbank6_cmd_response10_we - attribute \src "ls180.v:2225.12-2225.45" + attribute \src "ls180.v:2238.12-2238.45" wire width 8 \builder_csrbank6_cmd_response11_r - attribute \src "ls180.v:2224.6-2224.40" + attribute \src "ls180.v:2237.6-2237.40" wire \builder_csrbank6_cmd_response11_re - attribute \src "ls180.v:2227.12-2227.45" + attribute \src "ls180.v:2240.12-2240.45" wire width 8 \builder_csrbank6_cmd_response11_w - attribute \src "ls180.v:2226.6-2226.40" + attribute \src "ls180.v:2239.6-2239.40" wire \builder_csrbank6_cmd_response11_we - attribute \src "ls180.v:2221.12-2221.45" + attribute \src "ls180.v:2234.12-2234.45" wire width 8 \builder_csrbank6_cmd_response12_r - attribute \src "ls180.v:2220.6-2220.40" + attribute \src "ls180.v:2233.6-2233.40" wire \builder_csrbank6_cmd_response12_re - attribute \src "ls180.v:2223.12-2223.45" + attribute \src "ls180.v:2236.12-2236.45" wire width 8 \builder_csrbank6_cmd_response12_w - attribute \src "ls180.v:2222.6-2222.40" + attribute \src "ls180.v:2235.6-2235.40" wire \builder_csrbank6_cmd_response12_we - attribute \src "ls180.v:2217.12-2217.45" + attribute \src "ls180.v:2230.12-2230.45" wire width 8 \builder_csrbank6_cmd_response13_r - attribute \src "ls180.v:2216.6-2216.40" + attribute \src "ls180.v:2229.6-2229.40" wire \builder_csrbank6_cmd_response13_re - attribute \src "ls180.v:2219.12-2219.45" + attribute \src "ls180.v:2232.12-2232.45" wire width 8 \builder_csrbank6_cmd_response13_w - attribute \src "ls180.v:2218.6-2218.40" + attribute \src "ls180.v:2231.6-2231.40" wire \builder_csrbank6_cmd_response13_we - attribute \src "ls180.v:2213.12-2213.45" + attribute \src "ls180.v:2226.12-2226.45" wire width 8 \builder_csrbank6_cmd_response14_r - attribute \src "ls180.v:2212.6-2212.40" + attribute \src "ls180.v:2225.6-2225.40" wire \builder_csrbank6_cmd_response14_re - attribute \src "ls180.v:2215.12-2215.45" + attribute \src "ls180.v:2228.12-2228.45" wire width 8 \builder_csrbank6_cmd_response14_w - attribute \src "ls180.v:2214.6-2214.40" + attribute \src "ls180.v:2227.6-2227.40" wire \builder_csrbank6_cmd_response14_we - attribute \src "ls180.v:2209.12-2209.45" + attribute \src "ls180.v:2222.12-2222.45" wire width 8 \builder_csrbank6_cmd_response15_r - attribute \src "ls180.v:2208.6-2208.40" + attribute \src "ls180.v:2221.6-2221.40" wire \builder_csrbank6_cmd_response15_re - attribute \src "ls180.v:2211.12-2211.45" + attribute \src "ls180.v:2224.12-2224.45" wire width 8 \builder_csrbank6_cmd_response15_w - attribute \src "ls180.v:2210.6-2210.40" + attribute \src "ls180.v:2223.6-2223.40" wire \builder_csrbank6_cmd_response15_we - attribute \src "ls180.v:2265.12-2265.44" + attribute \src "ls180.v:2278.12-2278.44" wire width 8 \builder_csrbank6_cmd_response1_r - attribute \src "ls180.v:2264.6-2264.39" + attribute \src "ls180.v:2277.6-2277.39" wire \builder_csrbank6_cmd_response1_re - attribute \src "ls180.v:2267.12-2267.44" + attribute \src "ls180.v:2280.12-2280.44" wire width 8 \builder_csrbank6_cmd_response1_w - attribute \src "ls180.v:2266.6-2266.39" + attribute \src "ls180.v:2279.6-2279.39" wire \builder_csrbank6_cmd_response1_we - attribute \src "ls180.v:2261.12-2261.44" + attribute \src "ls180.v:2274.12-2274.44" wire width 8 \builder_csrbank6_cmd_response2_r - attribute \src "ls180.v:2260.6-2260.39" + attribute \src "ls180.v:2273.6-2273.39" wire \builder_csrbank6_cmd_response2_re - attribute \src "ls180.v:2263.12-2263.44" + attribute \src "ls180.v:2276.12-2276.44" wire width 8 \builder_csrbank6_cmd_response2_w - attribute \src "ls180.v:2262.6-2262.39" + attribute \src "ls180.v:2275.6-2275.39" wire \builder_csrbank6_cmd_response2_we - attribute \src "ls180.v:2257.12-2257.44" + attribute \src "ls180.v:2270.12-2270.44" wire width 8 \builder_csrbank6_cmd_response3_r - attribute \src "ls180.v:2256.6-2256.39" + attribute \src "ls180.v:2269.6-2269.39" wire \builder_csrbank6_cmd_response3_re - attribute \src "ls180.v:2259.12-2259.44" + attribute \src "ls180.v:2272.12-2272.44" wire width 8 \builder_csrbank6_cmd_response3_w - attribute \src "ls180.v:2258.6-2258.39" + attribute \src "ls180.v:2271.6-2271.39" wire \builder_csrbank6_cmd_response3_we - attribute \src "ls180.v:2253.12-2253.44" + attribute \src "ls180.v:2266.12-2266.44" wire width 8 \builder_csrbank6_cmd_response4_r - attribute \src "ls180.v:2252.6-2252.39" + attribute \src "ls180.v:2265.6-2265.39" wire \builder_csrbank6_cmd_response4_re - attribute \src "ls180.v:2255.12-2255.44" + attribute \src "ls180.v:2268.12-2268.44" wire width 8 \builder_csrbank6_cmd_response4_w - attribute \src "ls180.v:2254.6-2254.39" + attribute \src "ls180.v:2267.6-2267.39" wire \builder_csrbank6_cmd_response4_we - attribute \src "ls180.v:2249.12-2249.44" + attribute \src "ls180.v:2262.12-2262.44" wire width 8 \builder_csrbank6_cmd_response5_r - attribute \src "ls180.v:2248.6-2248.39" + attribute \src "ls180.v:2261.6-2261.39" wire \builder_csrbank6_cmd_response5_re - attribute \src "ls180.v:2251.12-2251.44" + attribute \src "ls180.v:2264.12-2264.44" wire width 8 \builder_csrbank6_cmd_response5_w - attribute \src "ls180.v:2250.6-2250.39" + attribute \src "ls180.v:2263.6-2263.39" wire \builder_csrbank6_cmd_response5_we - attribute \src "ls180.v:2245.12-2245.44" + attribute \src "ls180.v:2258.12-2258.44" wire width 8 \builder_csrbank6_cmd_response6_r - attribute \src "ls180.v:2244.6-2244.39" + attribute \src "ls180.v:2257.6-2257.39" wire \builder_csrbank6_cmd_response6_re - attribute \src "ls180.v:2247.12-2247.44" + attribute \src "ls180.v:2260.12-2260.44" wire width 8 \builder_csrbank6_cmd_response6_w - attribute \src "ls180.v:2246.6-2246.39" + attribute \src "ls180.v:2259.6-2259.39" wire \builder_csrbank6_cmd_response6_we - attribute \src "ls180.v:2241.12-2241.44" + attribute \src "ls180.v:2254.12-2254.44" wire width 8 \builder_csrbank6_cmd_response7_r - attribute \src "ls180.v:2240.6-2240.39" + attribute \src "ls180.v:2253.6-2253.39" wire \builder_csrbank6_cmd_response7_re - attribute \src "ls180.v:2243.12-2243.44" + attribute \src "ls180.v:2256.12-2256.44" wire width 8 \builder_csrbank6_cmd_response7_w - attribute \src "ls180.v:2242.6-2242.39" + attribute \src "ls180.v:2255.6-2255.39" wire \builder_csrbank6_cmd_response7_we - attribute \src "ls180.v:2237.12-2237.44" + attribute \src "ls180.v:2250.12-2250.44" wire width 8 \builder_csrbank6_cmd_response8_r - attribute \src "ls180.v:2236.6-2236.39" + attribute \src "ls180.v:2249.6-2249.39" wire \builder_csrbank6_cmd_response8_re - attribute \src "ls180.v:2239.12-2239.44" + attribute \src "ls180.v:2252.12-2252.44" wire width 8 \builder_csrbank6_cmd_response8_w - attribute \src "ls180.v:2238.6-2238.39" + attribute \src "ls180.v:2251.6-2251.39" wire \builder_csrbank6_cmd_response8_we - attribute \src "ls180.v:2233.12-2233.44" + attribute \src "ls180.v:2246.12-2246.44" wire width 8 \builder_csrbank6_cmd_response9_r - attribute \src "ls180.v:2232.6-2232.39" + attribute \src "ls180.v:2245.6-2245.39" wire \builder_csrbank6_cmd_response9_re - attribute \src "ls180.v:2235.12-2235.44" + attribute \src "ls180.v:2248.12-2248.44" wire width 8 \builder_csrbank6_cmd_response9_w - attribute \src "ls180.v:2234.6-2234.39" + attribute \src "ls180.v:2247.6-2247.39" wire \builder_csrbank6_cmd_response9_we - attribute \src "ls180.v:2277.12-2277.41" + attribute \src "ls180.v:2290.12-2290.41" wire width 4 \builder_csrbank6_data_event_r - attribute \src "ls180.v:2276.6-2276.36" + attribute \src "ls180.v:2289.6-2289.36" wire \builder_csrbank6_data_event_re - attribute \src "ls180.v:2279.12-2279.41" + attribute \src "ls180.v:2292.12-2292.41" wire width 4 \builder_csrbank6_data_event_w - attribute \src "ls180.v:2278.6-2278.36" + attribute \src "ls180.v:2291.6-2291.36" wire \builder_csrbank6_data_event_we - attribute \src "ls180.v:2304.6-2304.26" + attribute \src "ls180.v:2317.6-2317.26" wire \builder_csrbank6_sel - attribute \src "ls180.v:2338.12-2338.40" + attribute \src "ls180.v:2351.12-2351.40" wire width 8 \builder_csrbank7_dma_base0_r - attribute \src "ls180.v:2337.6-2337.35" + attribute \src "ls180.v:2350.6-2350.35" wire \builder_csrbank7_dma_base0_re - attribute \src "ls180.v:2340.12-2340.40" + attribute \src "ls180.v:2353.12-2353.40" wire width 8 \builder_csrbank7_dma_base0_w - attribute \src "ls180.v:2339.6-2339.35" + attribute \src "ls180.v:2352.6-2352.35" wire \builder_csrbank7_dma_base0_we - attribute \src "ls180.v:2334.12-2334.40" + attribute \src "ls180.v:2347.12-2347.40" wire width 8 \builder_csrbank7_dma_base1_r - attribute \src "ls180.v:2333.6-2333.35" + attribute \src "ls180.v:2346.6-2346.35" wire \builder_csrbank7_dma_base1_re - attribute \src "ls180.v:2336.12-2336.40" + attribute \src "ls180.v:2349.12-2349.40" wire width 8 \builder_csrbank7_dma_base1_w - attribute \src "ls180.v:2335.6-2335.35" + attribute \src "ls180.v:2348.6-2348.35" wire \builder_csrbank7_dma_base1_we - attribute \src "ls180.v:2330.12-2330.40" + attribute \src "ls180.v:2343.12-2343.40" wire width 8 \builder_csrbank7_dma_base2_r - attribute \src "ls180.v:2329.6-2329.35" + attribute \src "ls180.v:2342.6-2342.35" wire \builder_csrbank7_dma_base2_re - attribute \src "ls180.v:2332.12-2332.40" + attribute \src "ls180.v:2345.12-2345.40" wire width 8 \builder_csrbank7_dma_base2_w - attribute \src "ls180.v:2331.6-2331.35" + attribute \src "ls180.v:2344.6-2344.35" wire \builder_csrbank7_dma_base2_we - attribute \src "ls180.v:2326.12-2326.40" + attribute \src "ls180.v:2339.12-2339.40" wire width 8 \builder_csrbank7_dma_base3_r - attribute \src "ls180.v:2325.6-2325.35" + attribute \src "ls180.v:2338.6-2338.35" wire \builder_csrbank7_dma_base3_re - attribute \src "ls180.v:2328.12-2328.40" + attribute \src "ls180.v:2341.12-2341.40" wire width 8 \builder_csrbank7_dma_base3_w - attribute \src "ls180.v:2327.6-2327.35" + attribute \src "ls180.v:2340.6-2340.35" wire \builder_csrbank7_dma_base3_we - attribute \src "ls180.v:2322.12-2322.40" + attribute \src "ls180.v:2335.12-2335.40" wire width 8 \builder_csrbank7_dma_base4_r - attribute \src "ls180.v:2321.6-2321.35" + attribute \src "ls180.v:2334.6-2334.35" wire \builder_csrbank7_dma_base4_re - attribute \src "ls180.v:2324.12-2324.40" + attribute \src "ls180.v:2337.12-2337.40" wire width 8 \builder_csrbank7_dma_base4_w - attribute \src "ls180.v:2323.6-2323.35" + attribute \src "ls180.v:2336.6-2336.35" wire \builder_csrbank7_dma_base4_we - attribute \src "ls180.v:2318.12-2318.40" + attribute \src "ls180.v:2331.12-2331.40" wire width 8 \builder_csrbank7_dma_base5_r - attribute \src "ls180.v:2317.6-2317.35" + attribute \src "ls180.v:2330.6-2330.35" wire \builder_csrbank7_dma_base5_re - attribute \src "ls180.v:2320.12-2320.40" + attribute \src "ls180.v:2333.12-2333.40" wire width 8 \builder_csrbank7_dma_base5_w - attribute \src "ls180.v:2319.6-2319.35" + attribute \src "ls180.v:2332.6-2332.35" wire \builder_csrbank7_dma_base5_we - attribute \src "ls180.v:2314.12-2314.40" + attribute \src "ls180.v:2327.12-2327.40" wire width 8 \builder_csrbank7_dma_base6_r - attribute \src "ls180.v:2313.6-2313.35" + attribute \src "ls180.v:2326.6-2326.35" wire \builder_csrbank7_dma_base6_re - attribute \src "ls180.v:2316.12-2316.40" + attribute \src "ls180.v:2329.12-2329.40" wire width 8 \builder_csrbank7_dma_base6_w - attribute \src "ls180.v:2315.6-2315.35" + attribute \src "ls180.v:2328.6-2328.35" wire \builder_csrbank7_dma_base6_we - attribute \src "ls180.v:2310.12-2310.40" + attribute \src "ls180.v:2323.12-2323.40" wire width 8 \builder_csrbank7_dma_base7_r - attribute \src "ls180.v:2309.6-2309.35" + attribute \src "ls180.v:2322.6-2322.35" wire \builder_csrbank7_dma_base7_re - attribute \src "ls180.v:2312.12-2312.40" + attribute \src "ls180.v:2325.12-2325.40" wire width 8 \builder_csrbank7_dma_base7_w - attribute \src "ls180.v:2311.6-2311.35" + attribute \src "ls180.v:2324.6-2324.35" wire \builder_csrbank7_dma_base7_we - attribute \src "ls180.v:2362.6-2362.33" + attribute \src "ls180.v:2375.6-2375.33" wire \builder_csrbank7_dma_done_r - attribute \src "ls180.v:2361.6-2361.34" + attribute \src "ls180.v:2374.6-2374.34" wire \builder_csrbank7_dma_done_re - attribute \src "ls180.v:2364.6-2364.33" + attribute \src "ls180.v:2377.6-2377.33" wire \builder_csrbank7_dma_done_w - attribute \src "ls180.v:2363.6-2363.34" + attribute \src "ls180.v:2376.6-2376.34" wire \builder_csrbank7_dma_done_we - attribute \src "ls180.v:2358.6-2358.36" + attribute \src "ls180.v:2371.6-2371.36" wire \builder_csrbank7_dma_enable0_r - attribute \src "ls180.v:2357.6-2357.37" + attribute \src "ls180.v:2370.6-2370.37" wire \builder_csrbank7_dma_enable0_re - attribute \src "ls180.v:2360.6-2360.36" + attribute \src "ls180.v:2373.6-2373.36" wire \builder_csrbank7_dma_enable0_w - attribute \src "ls180.v:2359.6-2359.37" + attribute \src "ls180.v:2372.6-2372.37" wire \builder_csrbank7_dma_enable0_we - attribute \src "ls180.v:2354.12-2354.42" + attribute \src "ls180.v:2367.12-2367.42" wire width 8 \builder_csrbank7_dma_length0_r - attribute \src "ls180.v:2353.6-2353.37" + attribute \src "ls180.v:2366.6-2366.37" wire \builder_csrbank7_dma_length0_re - attribute \src "ls180.v:2356.12-2356.42" + attribute \src "ls180.v:2369.12-2369.42" wire width 8 \builder_csrbank7_dma_length0_w - attribute \src "ls180.v:2355.6-2355.37" + attribute \src "ls180.v:2368.6-2368.37" wire \builder_csrbank7_dma_length0_we - attribute \src "ls180.v:2350.12-2350.42" + attribute \src "ls180.v:2363.12-2363.42" wire width 8 \builder_csrbank7_dma_length1_r - attribute \src "ls180.v:2349.6-2349.37" + attribute \src "ls180.v:2362.6-2362.37" wire \builder_csrbank7_dma_length1_re - attribute \src "ls180.v:2352.12-2352.42" + attribute \src "ls180.v:2365.12-2365.42" wire width 8 \builder_csrbank7_dma_length1_w - attribute \src "ls180.v:2351.6-2351.37" + attribute \src "ls180.v:2364.6-2364.37" wire \builder_csrbank7_dma_length1_we - attribute \src "ls180.v:2346.12-2346.42" + attribute \src "ls180.v:2359.12-2359.42" wire width 8 \builder_csrbank7_dma_length2_r - attribute \src "ls180.v:2345.6-2345.37" + attribute \src "ls180.v:2358.6-2358.37" wire \builder_csrbank7_dma_length2_re - attribute \src "ls180.v:2348.12-2348.42" + attribute \src "ls180.v:2361.12-2361.42" wire width 8 \builder_csrbank7_dma_length2_w - attribute \src "ls180.v:2347.6-2347.37" + attribute \src "ls180.v:2360.6-2360.37" wire \builder_csrbank7_dma_length2_we - attribute \src "ls180.v:2342.12-2342.42" + attribute \src "ls180.v:2355.12-2355.42" wire width 8 \builder_csrbank7_dma_length3_r - attribute \src "ls180.v:2341.6-2341.37" + attribute \src "ls180.v:2354.6-2354.37" wire \builder_csrbank7_dma_length3_re - attribute \src "ls180.v:2344.12-2344.42" + attribute \src "ls180.v:2357.12-2357.42" wire width 8 \builder_csrbank7_dma_length3_w - attribute \src "ls180.v:2343.6-2343.37" + attribute \src "ls180.v:2356.6-2356.37" wire \builder_csrbank7_dma_length3_we - attribute \src "ls180.v:2366.6-2366.34" + attribute \src "ls180.v:2379.6-2379.34" wire \builder_csrbank7_dma_loop0_r - attribute \src "ls180.v:2365.6-2365.35" + attribute \src "ls180.v:2378.6-2378.35" wire \builder_csrbank7_dma_loop0_re - attribute \src "ls180.v:2368.6-2368.34" + attribute \src "ls180.v:2381.6-2381.34" wire \builder_csrbank7_dma_loop0_w - attribute \src "ls180.v:2367.6-2367.35" + attribute \src "ls180.v:2380.6-2380.35" wire \builder_csrbank7_dma_loop0_we - attribute \src "ls180.v:2382.12-2382.42" + attribute \src "ls180.v:2395.12-2395.42" wire width 8 \builder_csrbank7_dma_offset0_r - attribute \src "ls180.v:2381.6-2381.37" + attribute \src "ls180.v:2394.6-2394.37" wire \builder_csrbank7_dma_offset0_re - attribute \src "ls180.v:2384.12-2384.42" + attribute \src "ls180.v:2397.12-2397.42" wire width 8 \builder_csrbank7_dma_offset0_w - attribute \src "ls180.v:2383.6-2383.37" + attribute \src "ls180.v:2396.6-2396.37" wire \builder_csrbank7_dma_offset0_we - attribute \src "ls180.v:2378.12-2378.42" + attribute \src "ls180.v:2391.12-2391.42" wire width 8 \builder_csrbank7_dma_offset1_r - attribute \src "ls180.v:2377.6-2377.37" + attribute \src "ls180.v:2390.6-2390.37" wire \builder_csrbank7_dma_offset1_re - attribute \src "ls180.v:2380.12-2380.42" + attribute \src "ls180.v:2393.12-2393.42" wire width 8 \builder_csrbank7_dma_offset1_w - attribute \src "ls180.v:2379.6-2379.37" + attribute \src "ls180.v:2392.6-2392.37" wire \builder_csrbank7_dma_offset1_we - attribute \src "ls180.v:2374.12-2374.42" + attribute \src "ls180.v:2387.12-2387.42" wire width 8 \builder_csrbank7_dma_offset2_r - attribute \src "ls180.v:2373.6-2373.37" + attribute \src "ls180.v:2386.6-2386.37" wire \builder_csrbank7_dma_offset2_re - attribute \src "ls180.v:2376.12-2376.42" + attribute \src "ls180.v:2389.12-2389.42" wire width 8 \builder_csrbank7_dma_offset2_w - attribute \src "ls180.v:2375.6-2375.37" + attribute \src "ls180.v:2388.6-2388.37" wire \builder_csrbank7_dma_offset2_we - attribute \src "ls180.v:2370.12-2370.42" + attribute \src "ls180.v:2383.12-2383.42" wire width 8 \builder_csrbank7_dma_offset3_r - attribute \src "ls180.v:2369.6-2369.37" + attribute \src "ls180.v:2382.6-2382.37" wire \builder_csrbank7_dma_offset3_re - attribute \src "ls180.v:2372.12-2372.42" + attribute \src "ls180.v:2385.12-2385.42" wire width 8 \builder_csrbank7_dma_offset3_w - attribute \src "ls180.v:2371.6-2371.37" + attribute \src "ls180.v:2384.6-2384.37" wire \builder_csrbank7_dma_offset3_we - attribute \src "ls180.v:2385.6-2385.26" + attribute \src "ls180.v:2398.6-2398.26" wire \builder_csrbank7_sel - attribute \src "ls180.v:2391.6-2391.36" + attribute \src "ls180.v:2404.6-2404.36" wire \builder_csrbank8_card_detect_r - attribute \src "ls180.v:2390.6-2390.37" + attribute \src "ls180.v:2403.6-2403.37" wire \builder_csrbank8_card_detect_re - attribute \src "ls180.v:2393.6-2393.36" + attribute \src "ls180.v:2406.6-2406.36" wire \builder_csrbank8_card_detect_w - attribute \src "ls180.v:2392.6-2392.37" + attribute \src "ls180.v:2405.6-2405.37" wire \builder_csrbank8_card_detect_we - attribute \src "ls180.v:2399.12-2399.47" + attribute \src "ls180.v:2412.12-2412.47" wire width 8 \builder_csrbank8_clocker_divider0_r - attribute \src "ls180.v:2398.6-2398.42" + attribute \src "ls180.v:2411.6-2411.42" wire \builder_csrbank8_clocker_divider0_re - attribute \src "ls180.v:2401.12-2401.47" + attribute \src "ls180.v:2414.12-2414.47" wire width 8 \builder_csrbank8_clocker_divider0_w - attribute \src "ls180.v:2400.6-2400.42" + attribute \src "ls180.v:2413.6-2413.42" wire \builder_csrbank8_clocker_divider0_we - attribute \src "ls180.v:2395.6-2395.41" + attribute \src "ls180.v:2408.6-2408.41" wire \builder_csrbank8_clocker_divider1_r - attribute \src "ls180.v:2394.6-2394.42" + attribute \src "ls180.v:2407.6-2407.42" wire \builder_csrbank8_clocker_divider1_re - attribute \src "ls180.v:2397.6-2397.41" + attribute \src "ls180.v:2410.6-2410.41" wire \builder_csrbank8_clocker_divider1_w - attribute \src "ls180.v:2396.6-2396.42" + attribute \src "ls180.v:2409.6-2409.42" wire \builder_csrbank8_clocker_divider1_we - attribute \src "ls180.v:2402.6-2402.26" + attribute \src "ls180.v:2415.6-2415.26" wire \builder_csrbank8_sel - attribute \src "ls180.v:2408.12-2408.44" + attribute \src "ls180.v:2421.12-2421.44" wire width 4 \builder_csrbank9_dfii_control0_r - attribute \src "ls180.v:2407.6-2407.39" + attribute \src "ls180.v:2420.6-2420.39" wire \builder_csrbank9_dfii_control0_re - attribute \src "ls180.v:2410.12-2410.44" + attribute \src "ls180.v:2423.12-2423.44" wire width 4 \builder_csrbank9_dfii_control0_w - attribute \src "ls180.v:2409.6-2409.39" + attribute \src "ls180.v:2422.6-2422.39" wire \builder_csrbank9_dfii_control0_we - attribute \src "ls180.v:2420.12-2420.48" + attribute \src "ls180.v:2433.12-2433.48" wire width 8 \builder_csrbank9_dfii_pi0_address0_r - attribute \src "ls180.v:2419.6-2419.43" + attribute \src "ls180.v:2432.6-2432.43" wire \builder_csrbank9_dfii_pi0_address0_re - attribute \src "ls180.v:2422.12-2422.48" + attribute \src "ls180.v:2435.12-2435.48" wire width 8 \builder_csrbank9_dfii_pi0_address0_w - attribute \src "ls180.v:2421.6-2421.43" + attribute \src "ls180.v:2434.6-2434.43" wire \builder_csrbank9_dfii_pi0_address0_we - attribute \src "ls180.v:2416.12-2416.48" + attribute \src "ls180.v:2429.12-2429.48" wire width 5 \builder_csrbank9_dfii_pi0_address1_r - attribute \src "ls180.v:2415.6-2415.43" + attribute \src "ls180.v:2428.6-2428.43" wire \builder_csrbank9_dfii_pi0_address1_re - attribute \src "ls180.v:2418.12-2418.48" + attribute \src "ls180.v:2431.12-2431.48" wire width 5 \builder_csrbank9_dfii_pi0_address1_w - attribute \src "ls180.v:2417.6-2417.43" + attribute \src "ls180.v:2430.6-2430.43" wire \builder_csrbank9_dfii_pi0_address1_we - attribute \src "ls180.v:2424.12-2424.49" + attribute \src "ls180.v:2437.12-2437.49" wire width 2 \builder_csrbank9_dfii_pi0_baddress0_r - attribute \src "ls180.v:2423.6-2423.44" + attribute \src "ls180.v:2436.6-2436.44" wire \builder_csrbank9_dfii_pi0_baddress0_re - attribute \src "ls180.v:2426.12-2426.49" + attribute \src "ls180.v:2439.12-2439.49" wire width 2 \builder_csrbank9_dfii_pi0_baddress0_w - attribute \src "ls180.v:2425.6-2425.44" + attribute \src "ls180.v:2438.6-2438.44" wire \builder_csrbank9_dfii_pi0_baddress0_we - attribute \src "ls180.v:2412.12-2412.48" + attribute \src "ls180.v:2425.12-2425.48" wire width 6 \builder_csrbank9_dfii_pi0_command0_r - attribute \src "ls180.v:2411.6-2411.43" + attribute \src "ls180.v:2424.6-2424.43" wire \builder_csrbank9_dfii_pi0_command0_re - attribute \src "ls180.v:2414.12-2414.48" + attribute \src "ls180.v:2427.12-2427.48" wire width 6 \builder_csrbank9_dfii_pi0_command0_w - attribute \src "ls180.v:2413.6-2413.43" + attribute \src "ls180.v:2426.6-2426.43" wire \builder_csrbank9_dfii_pi0_command0_we - attribute \src "ls180.v:2440.12-2440.47" + attribute \src "ls180.v:2453.12-2453.47" wire width 8 \builder_csrbank9_dfii_pi0_rddata0_r - attribute \src "ls180.v:2439.6-2439.42" + attribute \src "ls180.v:2452.6-2452.42" wire \builder_csrbank9_dfii_pi0_rddata0_re - attribute \src "ls180.v:2442.12-2442.47" + attribute \src "ls180.v:2455.12-2455.47" wire width 8 \builder_csrbank9_dfii_pi0_rddata0_w - attribute \src "ls180.v:2441.6-2441.42" + attribute \src "ls180.v:2454.6-2454.42" wire \builder_csrbank9_dfii_pi0_rddata0_we - attribute \src "ls180.v:2436.12-2436.47" + attribute \src "ls180.v:2449.12-2449.47" wire width 8 \builder_csrbank9_dfii_pi0_rddata1_r - attribute \src "ls180.v:2435.6-2435.42" + attribute \src "ls180.v:2448.6-2448.42" wire \builder_csrbank9_dfii_pi0_rddata1_re - attribute \src "ls180.v:2438.12-2438.47" + attribute \src "ls180.v:2451.12-2451.47" wire width 8 \builder_csrbank9_dfii_pi0_rddata1_w - attribute \src "ls180.v:2437.6-2437.42" + attribute \src "ls180.v:2450.6-2450.42" wire \builder_csrbank9_dfii_pi0_rddata1_we - attribute \src "ls180.v:2432.12-2432.47" + attribute \src "ls180.v:2445.12-2445.47" wire width 8 \builder_csrbank9_dfii_pi0_wrdata0_r - attribute \src "ls180.v:2431.6-2431.42" + attribute \src "ls180.v:2444.6-2444.42" wire \builder_csrbank9_dfii_pi0_wrdata0_re - attribute \src "ls180.v:2434.12-2434.47" + attribute \src "ls180.v:2447.12-2447.47" wire width 8 \builder_csrbank9_dfii_pi0_wrdata0_w - attribute \src "ls180.v:2433.6-2433.42" + attribute \src "ls180.v:2446.6-2446.42" wire \builder_csrbank9_dfii_pi0_wrdata0_we - attribute \src "ls180.v:2428.12-2428.47" + attribute \src "ls180.v:2441.12-2441.47" wire width 8 \builder_csrbank9_dfii_pi0_wrdata1_r - attribute \src "ls180.v:2427.6-2427.42" + attribute \src "ls180.v:2440.6-2440.42" wire \builder_csrbank9_dfii_pi0_wrdata1_re - attribute \src "ls180.v:2430.12-2430.47" + attribute \src "ls180.v:2443.12-2443.47" wire width 8 \builder_csrbank9_dfii_pi0_wrdata1_w - attribute \src "ls180.v:2429.6-2429.42" + attribute \src "ls180.v:2442.6-2442.42" wire \builder_csrbank9_dfii_pi0_wrdata1_we - attribute \src "ls180.v:2443.6-2443.26" + attribute \src "ls180.v:2456.6-2456.26" wire \builder_csrbank9_sel - attribute \src "ls180.v:1940.6-1940.18" + attribute \src "ls180.v:1953.6-1953.18" wire \builder_done - attribute \src "ls180.v:1938.5-1938.18" + attribute \src "ls180.v:1951.5-1951.18" wire \builder_error - attribute \src "ls180.v:1935.11-1935.24" + attribute \src "ls180.v:1948.11-1948.24" wire width 3 \builder_grant - attribute \src "ls180.v:1942.13-1942.44" + attribute \src "ls180.v:1955.13-1955.44" wire width 14 \builder_interface0_bank_bus_adr - attribute \src "ls180.v:1945.11-1945.44" + attribute \src "ls180.v:1958.11-1958.44" wire width 8 \builder_interface0_bank_bus_dat_r - attribute \src "ls180.v:1944.12-1944.45" + attribute \src "ls180.v:1957.12-1957.45" wire width 8 \builder_interface0_bank_bus_dat_w - attribute \src "ls180.v:1943.6-1943.36" + attribute \src "ls180.v:1956.6-1956.36" wire \builder_interface0_bank_bus_we - attribute \src "ls180.v:2444.13-2444.45" + attribute \src "ls180.v:2457.13-2457.45" wire width 14 \builder_interface10_bank_bus_adr - attribute \src "ls180.v:2447.11-2447.45" + attribute \src "ls180.v:2460.11-2460.45" wire width 8 \builder_interface10_bank_bus_dat_r - attribute \src "ls180.v:2446.12-2446.46" + attribute \src "ls180.v:2459.12-2459.46" wire width 8 \builder_interface10_bank_bus_dat_w - attribute \src "ls180.v:2445.6-2445.37" + attribute \src "ls180.v:2458.6-2458.37" wire \builder_interface10_bank_bus_we - attribute \src "ls180.v:2477.13-2477.45" + attribute \src "ls180.v:2490.13-2490.45" wire width 14 \builder_interface11_bank_bus_adr - attribute \src "ls180.v:2480.11-2480.45" + attribute \src "ls180.v:2493.11-2493.45" wire width 8 \builder_interface11_bank_bus_dat_r - attribute \src "ls180.v:2479.12-2479.46" + attribute \src "ls180.v:2492.12-2492.46" wire width 8 \builder_interface11_bank_bus_dat_w - attribute \src "ls180.v:2478.6-2478.37" + attribute \src "ls180.v:2491.6-2491.37" wire \builder_interface11_bank_bus_we - attribute \src "ls180.v:2518.13-2518.45" + attribute \src "ls180.v:2531.13-2531.45" wire width 14 \builder_interface12_bank_bus_adr - attribute \src "ls180.v:2521.11-2521.45" + attribute \src "ls180.v:2534.11-2534.45" wire width 8 \builder_interface12_bank_bus_dat_r - attribute \src "ls180.v:2520.12-2520.46" + attribute \src "ls180.v:2533.12-2533.46" wire width 8 \builder_interface12_bank_bus_dat_w - attribute \src "ls180.v:2519.6-2519.37" + attribute \src "ls180.v:2532.6-2532.37" wire \builder_interface12_bank_bus_we - attribute \src "ls180.v:2583.13-2583.45" + attribute \src "ls180.v:2596.13-2596.45" wire width 14 \builder_interface13_bank_bus_adr - attribute \src "ls180.v:2586.11-2586.45" + attribute \src "ls180.v:2599.11-2599.45" wire width 8 \builder_interface13_bank_bus_dat_r - attribute \src "ls180.v:2585.12-2585.46" + attribute \src "ls180.v:2598.12-2598.46" wire width 8 \builder_interface13_bank_bus_dat_w - attribute \src "ls180.v:2584.6-2584.37" + attribute \src "ls180.v:2597.6-2597.37" wire \builder_interface13_bank_bus_we - attribute \src "ls180.v:2608.13-2608.45" + attribute \src "ls180.v:2621.13-2621.45" wire width 14 \builder_interface14_bank_bus_adr - attribute \src "ls180.v:2611.11-2611.45" + attribute \src "ls180.v:2624.11-2624.45" wire width 8 \builder_interface14_bank_bus_dat_r - attribute \src "ls180.v:2610.12-2610.46" + attribute \src "ls180.v:2623.12-2623.46" wire width 8 \builder_interface14_bank_bus_dat_w - attribute \src "ls180.v:2609.6-2609.37" + attribute \src "ls180.v:2622.6-2622.37" wire \builder_interface14_bank_bus_we - attribute \src "ls180.v:1983.13-1983.44" + attribute \src "ls180.v:1996.13-1996.44" wire width 14 \builder_interface1_bank_bus_adr - attribute \src "ls180.v:1986.11-1986.44" + attribute \src "ls180.v:1999.11-1999.44" wire width 8 \builder_interface1_bank_bus_dat_r - attribute \src "ls180.v:1985.12-1985.45" + attribute \src "ls180.v:1998.12-1998.45" wire width 8 \builder_interface1_bank_bus_dat_w - attribute \src "ls180.v:1984.6-1984.36" + attribute \src "ls180.v:1997.6-1997.36" wire \builder_interface1_bank_bus_we - attribute \src "ls180.v:2012.13-2012.44" + attribute \src "ls180.v:2025.13-2025.44" wire width 14 \builder_interface2_bank_bus_adr - attribute \src "ls180.v:2015.11-2015.44" + attribute \src "ls180.v:2028.11-2028.44" wire width 8 \builder_interface2_bank_bus_dat_r - attribute \src "ls180.v:2014.12-2014.45" + attribute \src "ls180.v:2027.12-2027.45" wire width 8 \builder_interface2_bank_bus_dat_w - attribute \src "ls180.v:2013.6-2013.36" + attribute \src "ls180.v:2026.6-2026.36" wire \builder_interface2_bank_bus_we - attribute \src "ls180.v:2025.13-2025.44" + attribute \src "ls180.v:2038.13-2038.44" wire width 14 \builder_interface3_bank_bus_adr - attribute \src "ls180.v:2028.11-2028.44" + attribute \src "ls180.v:2041.11-2041.44" wire width 8 \builder_interface3_bank_bus_dat_r - attribute \src "ls180.v:2027.12-2027.45" + attribute \src "ls180.v:2040.12-2040.45" wire width 8 \builder_interface3_bank_bus_dat_w - attribute \src "ls180.v:2026.6-2026.36" + attribute \src "ls180.v:2039.6-2039.36" wire \builder_interface3_bank_bus_we - attribute \src "ls180.v:2066.13-2066.44" + attribute \src "ls180.v:2079.13-2079.44" wire width 14 \builder_interface4_bank_bus_adr - attribute \src "ls180.v:2069.11-2069.44" + attribute \src "ls180.v:2082.11-2082.44" wire width 8 \builder_interface4_bank_bus_dat_r - attribute \src "ls180.v:2068.12-2068.45" + attribute \src "ls180.v:2081.12-2081.45" wire width 8 \builder_interface4_bank_bus_dat_w - attribute \src "ls180.v:2067.6-2067.36" + attribute \src "ls180.v:2080.6-2080.36" wire \builder_interface4_bank_bus_we - attribute \src "ls180.v:2107.13-2107.44" + attribute \src "ls180.v:2120.13-2120.44" wire width 14 \builder_interface5_bank_bus_adr - attribute \src "ls180.v:2110.11-2110.44" + attribute \src "ls180.v:2123.11-2123.44" wire width 8 \builder_interface5_bank_bus_dat_r - attribute \src "ls180.v:2109.12-2109.45" + attribute \src "ls180.v:2122.12-2122.45" wire width 8 \builder_interface5_bank_bus_dat_w - attribute \src "ls180.v:2108.6-2108.36" + attribute \src "ls180.v:2121.6-2121.36" wire \builder_interface5_bank_bus_we - attribute \src "ls180.v:2172.13-2172.44" + attribute \src "ls180.v:2185.13-2185.44" wire width 14 \builder_interface6_bank_bus_adr - attribute \src "ls180.v:2175.11-2175.44" + attribute \src "ls180.v:2188.11-2188.44" wire width 8 \builder_interface6_bank_bus_dat_r - attribute \src "ls180.v:2174.12-2174.45" + attribute \src "ls180.v:2187.12-2187.45" wire width 8 \builder_interface6_bank_bus_dat_w - attribute \src "ls180.v:2173.6-2173.36" + attribute \src "ls180.v:2186.6-2186.36" wire \builder_interface6_bank_bus_we - attribute \src "ls180.v:2305.13-2305.44" + attribute \src "ls180.v:2318.13-2318.44" wire width 14 \builder_interface7_bank_bus_adr - attribute \src "ls180.v:2308.11-2308.44" + attribute \src "ls180.v:2321.11-2321.44" wire width 8 \builder_interface7_bank_bus_dat_r - attribute \src "ls180.v:2307.12-2307.45" + attribute \src "ls180.v:2320.12-2320.45" wire width 8 \builder_interface7_bank_bus_dat_w - attribute \src "ls180.v:2306.6-2306.36" + attribute \src "ls180.v:2319.6-2319.36" wire \builder_interface7_bank_bus_we - attribute \src "ls180.v:2386.13-2386.44" + attribute \src "ls180.v:2399.13-2399.44" wire width 14 \builder_interface8_bank_bus_adr - attribute \src "ls180.v:2389.11-2389.44" + attribute \src "ls180.v:2402.11-2402.44" wire width 8 \builder_interface8_bank_bus_dat_r - attribute \src "ls180.v:2388.12-2388.45" + attribute \src "ls180.v:2401.12-2401.45" wire width 8 \builder_interface8_bank_bus_dat_w - attribute \src "ls180.v:2387.6-2387.36" + attribute \src "ls180.v:2400.6-2400.36" wire \builder_interface8_bank_bus_we - attribute \src "ls180.v:2403.13-2403.44" + attribute \src "ls180.v:2416.13-2416.44" wire width 14 \builder_interface9_bank_bus_adr - attribute \src "ls180.v:2406.11-2406.44" + attribute \src "ls180.v:2419.11-2419.44" wire width 8 \builder_interface9_bank_bus_dat_r - attribute \src "ls180.v:2405.12-2405.45" + attribute \src "ls180.v:2418.12-2418.45" wire width 8 \builder_interface9_bank_bus_dat_w - attribute \src "ls180.v:2404.6-2404.36" + attribute \src "ls180.v:2417.6-2417.36" wire \builder_interface9_bank_bus_we - attribute \src "ls180.v:1908.12-1908.35" + attribute \src "ls180.v:1913.12-1913.35" wire width 14 \builder_libresocsim_adr - attribute \src "ls180.v:2637.12-2637.47" + attribute \src "ls180.v:2650.12-2650.47" wire width 14 \builder_libresocsim_adr_next_value1 - attribute \src "ls180.v:2638.5-2638.43" + attribute \src "ls180.v:2651.5-2651.43" wire \builder_libresocsim_adr_next_value_ce1 - attribute \src "ls180.v:1911.12-1911.37" + attribute \src "ls180.v:1931.5-1931.48" + wire \builder_libresocsim_converted_interface_ack + attribute \src "ls180.v:1925.13-1925.56" + wire width 30 \builder_libresocsim_converted_interface_adr + attribute \src "ls180.v:1934.12-1934.55" + wire width 2 \builder_libresocsim_converted_interface_bte + attribute \src "ls180.v:1933.12-1933.55" + wire width 3 \builder_libresocsim_converted_interface_cti + attribute \src "ls180.v:1929.6-1929.49" + wire \builder_libresocsim_converted_interface_cyc + attribute \src "ls180.v:1927.12-1927.57" + wire width 64 \builder_libresocsim_converted_interface_dat_r + attribute \src "ls180.v:1926.13-1926.58" + wire width 64 \builder_libresocsim_converted_interface_dat_w + attribute \src "ls180.v:1935.5-1935.48" + wire \builder_libresocsim_converted_interface_err + attribute \src "ls180.v:1928.12-1928.55" + wire width 8 \builder_libresocsim_converted_interface_sel + attribute \src "ls180.v:1930.6-1930.49" + wire \builder_libresocsim_converted_interface_stb + attribute \src "ls180.v:1932.6-1932.48" + wire \builder_libresocsim_converted_interface_we + attribute \src "ls180.v:1916.12-1916.37" wire width 8 \builder_libresocsim_dat_r - attribute \src "ls180.v:1910.11-1910.36" + attribute \src "ls180.v:1915.11-1915.36" wire width 8 \builder_libresocsim_dat_w - attribute \src "ls180.v:2635.11-2635.48" + attribute \src "ls180.v:2648.11-2648.48" wire width 8 \builder_libresocsim_dat_w_next_value0 - attribute \src "ls180.v:2636.5-2636.45" + attribute \src "ls180.v:2649.5-2649.45" wire \builder_libresocsim_dat_w_next_value_ce0 - attribute \src "ls180.v:1909.5-1909.27" + attribute \src "ls180.v:1914.5-1914.27" wire \builder_libresocsim_we - attribute \src "ls180.v:2639.5-2639.39" + attribute \src "ls180.v:2652.5-2652.39" wire \builder_libresocsim_we_next_value2 - attribute \src "ls180.v:2640.5-2640.42" + attribute \src "ls180.v:2653.5-2653.42" wire \builder_libresocsim_we_next_value_ce2 - attribute \src "ls180.v:1918.5-1918.37" + attribute \src "ls180.v:1923.5-1923.37" wire \builder_libresocsim_wishbone_ack - attribute \src "ls180.v:1912.13-1912.45" + attribute \src "ls180.v:1917.12-1917.44" wire width 30 \builder_libresocsim_wishbone_adr - attribute \src "ls180.v:1921.12-1921.44" - wire width 2 \builder_libresocsim_wishbone_bte - attribute \src "ls180.v:1920.12-1920.44" - wire width 3 \builder_libresocsim_wishbone_cti - attribute \src "ls180.v:1916.6-1916.38" + attribute \src "ls180.v:1921.5-1921.37" wire \builder_libresocsim_wishbone_cyc - attribute \src "ls180.v:1914.12-1914.46" + attribute \src "ls180.v:1919.12-1919.46" wire width 32 \builder_libresocsim_wishbone_dat_r - attribute \src "ls180.v:1913.13-1913.47" + attribute \src "ls180.v:1918.12-1918.46" wire width 32 \builder_libresocsim_wishbone_dat_w - attribute \src "ls180.v:1922.5-1922.37" - wire \builder_libresocsim_wishbone_err - attribute \src "ls180.v:1915.12-1915.44" + attribute \src "ls180.v:1920.11-1920.43" wire width 4 \builder_libresocsim_wishbone_sel - attribute \src "ls180.v:1917.6-1917.38" + attribute \src "ls180.v:1922.5-1922.37" wire \builder_libresocsim_wishbone_stb - attribute \src "ls180.v:1919.6-1919.37" + attribute \src "ls180.v:1924.5-1924.36" wire \builder_libresocsim_wishbone_we - attribute \src "ls180.v:1811.5-1811.20" + attribute \src "ls180.v:1816.5-1816.20" wire \builder_locked0 - attribute \src "ls180.v:1812.5-1812.20" + attribute \src "ls180.v:1817.5-1817.20" wire \builder_locked1 - attribute \src "ls180.v:1813.5-1813.20" + attribute \src "ls180.v:1818.5-1818.20" wire \builder_locked2 - attribute \src "ls180.v:1814.5-1814.20" + attribute \src "ls180.v:1819.5-1819.20" wire \builder_locked3 - attribute \src "ls180.v:1798.11-1798.41" + attribute \src "ls180.v:1803.11-1803.41" wire width 3 \builder_multiplexer_next_state - attribute \src "ls180.v:1797.11-1797.36" + attribute \src "ls180.v:1802.11-1802.36" wire width 3 \builder_multiplexer_state attribute \no_retiming "true" - attribute \src "ls180.v:2744.32-2744.59" + attribute \src "ls180.v:2757.32-2757.59" wire \builder_multiregimpl0_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2745.32-2745.59" + attribute \src "ls180.v:2758.32-2758.59" wire \builder_multiregimpl0_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2764.32-2764.60" + attribute \src "ls180.v:2777.32-2777.60" wire \builder_multiregimpl10_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2765.32-2765.60" + attribute \src "ls180.v:2778.32-2778.60" wire \builder_multiregimpl10_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2766.32-2766.60" + attribute \src "ls180.v:2779.32-2779.60" wire \builder_multiregimpl11_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2767.32-2767.60" + attribute \src "ls180.v:2780.32-2780.60" wire \builder_multiregimpl11_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2768.32-2768.60" + attribute \src "ls180.v:2781.32-2781.60" wire \builder_multiregimpl12_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2769.32-2769.60" + attribute \src "ls180.v:2782.32-2782.60" wire \builder_multiregimpl12_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2770.32-2770.60" + attribute \src "ls180.v:2783.32-2783.60" wire \builder_multiregimpl13_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2771.32-2771.60" + attribute \src "ls180.v:2784.32-2784.60" wire \builder_multiregimpl13_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2772.32-2772.60" + attribute \src "ls180.v:2785.32-2785.60" wire \builder_multiregimpl14_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2773.32-2773.60" + attribute \src "ls180.v:2786.32-2786.60" wire \builder_multiregimpl14_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2774.32-2774.60" + attribute \src "ls180.v:2787.32-2787.60" wire \builder_multiregimpl15_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2775.32-2775.60" + attribute \src "ls180.v:2788.32-2788.60" wire \builder_multiregimpl15_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2776.32-2776.60" + attribute \src "ls180.v:2789.32-2789.60" wire \builder_multiregimpl16_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2777.32-2777.60" + attribute \src "ls180.v:2790.32-2790.60" wire \builder_multiregimpl16_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2746.32-2746.59" + attribute \src "ls180.v:2759.32-2759.59" wire \builder_multiregimpl1_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2747.32-2747.59" + attribute \src "ls180.v:2760.32-2760.59" wire \builder_multiregimpl1_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2748.32-2748.59" + attribute \src "ls180.v:2761.32-2761.59" wire \builder_multiregimpl2_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2749.32-2749.59" + attribute \src "ls180.v:2762.32-2762.59" wire \builder_multiregimpl2_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2750.32-2750.59" + attribute \src "ls180.v:2763.32-2763.59" wire \builder_multiregimpl3_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2751.32-2751.59" + attribute \src "ls180.v:2764.32-2764.59" wire \builder_multiregimpl3_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2752.32-2752.59" + attribute \src "ls180.v:2765.32-2765.59" wire \builder_multiregimpl4_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2753.32-2753.59" + attribute \src "ls180.v:2766.32-2766.59" wire \builder_multiregimpl4_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2754.32-2754.59" + attribute \src "ls180.v:2767.32-2767.59" wire \builder_multiregimpl5_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2755.32-2755.59" + attribute \src "ls180.v:2768.32-2768.59" wire \builder_multiregimpl5_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2756.32-2756.59" + attribute \src "ls180.v:2769.32-2769.59" wire \builder_multiregimpl6_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2757.32-2757.59" + attribute \src "ls180.v:2770.32-2770.59" wire \builder_multiregimpl6_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2758.32-2758.59" + attribute \src "ls180.v:2771.32-2771.59" wire \builder_multiregimpl7_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2759.32-2759.59" + attribute \src "ls180.v:2772.32-2772.59" wire \builder_multiregimpl7_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2760.32-2760.59" + attribute \src "ls180.v:2773.32-2773.59" wire \builder_multiregimpl8_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2761.32-2761.59" + attribute \src "ls180.v:2774.32-2774.59" wire \builder_multiregimpl8_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2762.32-2762.59" + attribute \src "ls180.v:2775.32-2775.59" wire \builder_multiregimpl9_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2763.32-2763.59" + attribute \src "ls180.v:2776.32-2776.59" wire \builder_multiregimpl9_regs1 - attribute \src "ls180.v:1816.5-1816.36" + attribute \src "ls180.v:1821.5-1821.36" wire \builder_new_master_rdata_valid0 - attribute \src "ls180.v:1817.5-1817.36" + attribute \src "ls180.v:1822.5-1822.36" wire \builder_new_master_rdata_valid1 - attribute \src "ls180.v:1818.5-1818.36" + attribute \src "ls180.v:1823.5-1823.36" wire \builder_new_master_rdata_valid2 - attribute \src "ls180.v:1819.5-1819.36" + attribute \src "ls180.v:1824.5-1824.36" wire \builder_new_master_rdata_valid3 - attribute \src "ls180.v:1815.5-1815.35" + attribute \src "ls180.v:1820.5-1820.35" wire \builder_new_master_wdata_ready - attribute \src "ls180.v:2634.11-2634.29" + attribute \src "ls180.v:2647.11-2647.29" wire width 2 \builder_next_state - attribute \src "ls180.v:1788.11-1788.39" + attribute \src "ls180.v:1793.11-1793.39" wire width 2 \builder_refresher_next_state - attribute \src "ls180.v:1787.11-1787.34" + attribute \src "ls180.v:1792.11-1792.34" wire width 2 \builder_refresher_state - attribute \src "ls180.v:1934.12-1934.27" + attribute \src "ls180.v:1947.12-1947.27" wire width 5 \builder_request - attribute \src "ls180.v:1801.6-1801.28" + attribute \src "ls180.v:1806.6-1806.28" wire \builder_roundrobin0_ce - attribute \src "ls180.v:1800.6-1800.31" + attribute \src "ls180.v:1805.6-1805.31" wire \builder_roundrobin0_grant - attribute \src "ls180.v:1799.6-1799.33" + attribute \src "ls180.v:1804.6-1804.33" wire \builder_roundrobin0_request - attribute \src "ls180.v:1804.6-1804.28" + attribute \src "ls180.v:1809.6-1809.28" wire \builder_roundrobin1_ce - attribute \src "ls180.v:1803.6-1803.31" + attribute \src "ls180.v:1808.6-1808.31" wire \builder_roundrobin1_grant - attribute \src "ls180.v:1802.6-1802.33" + attribute \src "ls180.v:1807.6-1807.33" wire \builder_roundrobin1_request - attribute \src "ls180.v:1807.6-1807.28" + attribute \src "ls180.v:1812.6-1812.28" wire \builder_roundrobin2_ce - attribute \src "ls180.v:1806.6-1806.31" + attribute \src "ls180.v:1811.6-1811.31" wire \builder_roundrobin2_grant - attribute \src "ls180.v:1805.6-1805.33" + attribute \src "ls180.v:1810.6-1810.33" wire \builder_roundrobin2_request - attribute \src "ls180.v:1810.6-1810.28" + attribute \src "ls180.v:1815.6-1815.28" wire \builder_roundrobin3_ce - attribute \src "ls180.v:1809.6-1809.31" + attribute \src "ls180.v:1814.6-1814.31" wire \builder_roundrobin3_grant - attribute \src "ls180.v:1808.6-1808.33" + attribute \src "ls180.v:1813.6-1813.33" wire \builder_roundrobin3_request - attribute \src "ls180.v:1897.11-1897.44" + attribute \src "ls180.v:1902.11-1902.44" wire width 2 \builder_sdblock2memdma_next_state - attribute \src "ls180.v:1896.11-1896.39" + attribute \src "ls180.v:1901.11-1901.39" wire width 2 \builder_sdblock2memdma_state - attribute \src "ls180.v:1865.5-1865.50" + attribute \src "ls180.v:1870.5-1870.50" wire \builder_sdcore_crcupstreaminserter_next_state - attribute \src "ls180.v:1864.5-1864.45" + attribute \src "ls180.v:1869.5-1869.45" wire \builder_sdcore_crcupstreaminserter_state - attribute \src "ls180.v:1877.11-1877.40" + attribute \src "ls180.v:1882.11-1882.40" wire width 3 \builder_sdcore_fsm_next_state - attribute \src "ls180.v:1876.11-1876.35" + attribute \src "ls180.v:1881.11-1881.35" wire width 3 \builder_sdcore_fsm_state - attribute \src "ls180.v:1901.5-1901.42" + attribute \src "ls180.v:1906.5-1906.42" wire \builder_sdmem2blockdma_fsm_next_state - attribute \src "ls180.v:1900.5-1900.37" + attribute \src "ls180.v:1905.5-1905.37" wire \builder_sdmem2blockdma_fsm_state - attribute \src "ls180.v:1905.11-1905.58" + attribute \src "ls180.v:1910.11-1910.58" wire width 2 \builder_sdmem2blockdma_resetinserter_next_state - attribute \src "ls180.v:1904.11-1904.53" + attribute \src "ls180.v:1909.11-1909.53" wire width 2 \builder_sdmem2blockdma_resetinserter_state - attribute \src "ls180.v:1853.11-1853.39" + attribute \src "ls180.v:1858.11-1858.39" wire width 3 \builder_sdphy_fsm_next_state - attribute \src "ls180.v:1852.11-1852.34" + attribute \src "ls180.v:1857.11-1857.34" wire width 3 \builder_sdphy_fsm_state - attribute \src "ls180.v:1841.11-1841.45" + attribute \src "ls180.v:1846.11-1846.45" wire width 3 \builder_sdphy_sdphycmdr_next_state - attribute \src "ls180.v:1840.11-1840.40" + attribute \src "ls180.v:1845.11-1845.40" wire width 3 \builder_sdphy_sdphycmdr_state - attribute \src "ls180.v:1837.11-1837.45" + attribute \src "ls180.v:1842.11-1842.45" wire width 2 \builder_sdphy_sdphycmdw_next_state - attribute \src "ls180.v:1836.11-1836.40" + attribute \src "ls180.v:1841.11-1841.40" wire width 2 \builder_sdphy_sdphycmdw_state - attribute \src "ls180.v:1849.5-1849.39" + attribute \src "ls180.v:1854.5-1854.39" wire \builder_sdphy_sdphycrcr_next_state - attribute \src "ls180.v:1848.5-1848.34" + attribute \src "ls180.v:1853.5-1853.34" wire \builder_sdphy_sdphycrcr_state - attribute \src "ls180.v:1857.11-1857.46" + attribute \src "ls180.v:1862.11-1862.46" wire width 3 \builder_sdphy_sdphydatar_next_state - attribute \src "ls180.v:1856.11-1856.41" + attribute \src "ls180.v:1861.11-1861.41" wire width 3 \builder_sdphy_sdphydatar_state - attribute \src "ls180.v:1833.5-1833.39" + attribute \src "ls180.v:1838.5-1838.39" wire \builder_sdphy_sdphyinit_next_state - attribute \src "ls180.v:1832.5-1832.34" + attribute \src "ls180.v:1837.5-1837.34" wire \builder_sdphy_sdphyinit_state - attribute \src "ls180.v:1929.5-1929.23" + attribute \src "ls180.v:1942.5-1942.23" wire \builder_shared_ack - attribute \src "ls180.v:1923.13-1923.31" + attribute \src "ls180.v:1936.13-1936.31" wire width 30 \builder_shared_adr - attribute \src "ls180.v:1932.12-1932.30" + attribute \src "ls180.v:1945.12-1945.30" wire width 2 \builder_shared_bte - attribute \src "ls180.v:1931.12-1931.30" + attribute \src "ls180.v:1944.12-1944.30" wire width 3 \builder_shared_cti - attribute \src "ls180.v:1927.6-1927.24" + attribute \src "ls180.v:1940.6-1940.24" wire \builder_shared_cyc - attribute \src "ls180.v:1925.12-1925.32" + attribute \src "ls180.v:1938.12-1938.32" wire width 32 \builder_shared_dat_r - attribute \src "ls180.v:1924.13-1924.33" + attribute \src "ls180.v:1937.13-1937.33" wire width 32 \builder_shared_dat_w - attribute \src "ls180.v:1933.6-1933.24" + attribute \src "ls180.v:1946.6-1946.24" wire \builder_shared_err - attribute \src "ls180.v:1926.12-1926.30" + attribute \src "ls180.v:1939.12-1939.30" wire width 4 \builder_shared_sel - attribute \src "ls180.v:1928.6-1928.24" + attribute \src "ls180.v:1941.6-1941.24" wire \builder_shared_stb - attribute \src "ls180.v:1930.6-1930.23" + attribute \src "ls180.v:1943.6-1943.23" wire \builder_shared_we - attribute \src "ls180.v:1936.11-1936.28" + attribute \src "ls180.v:1949.11-1949.28" wire width 8 \builder_slave_sel - attribute \src "ls180.v:1937.11-1937.30" + attribute \src "ls180.v:1950.11-1950.30" wire width 8 \builder_slave_sel_r - attribute \src "ls180.v:1825.11-1825.40" + attribute \src "ls180.v:1830.11-1830.40" wire width 2 \builder_spimaster0_next_state - attribute \src "ls180.v:1824.11-1824.35" + attribute \src "ls180.v:1829.11-1829.35" wire width 2 \builder_spimaster0_state - attribute \src "ls180.v:1829.11-1829.40" + attribute \src "ls180.v:1834.11-1834.40" wire width 2 \builder_spimaster1_next_state - attribute \src "ls180.v:1828.11-1828.35" + attribute \src "ls180.v:1833.11-1833.35" wire width 2 \builder_spimaster1_state - attribute \src "ls180.v:2633.11-2633.24" + attribute \src "ls180.v:2646.11-2646.24" wire width 2 \builder_state - attribute \src "ls180.v:2686.5-2686.32" + attribute \src "ls180.v:2699.5-2699.32" wire \builder_sync_f_array_muxed0 - attribute \src "ls180.v:2687.5-2687.32" + attribute \src "ls180.v:2700.5-2700.32" wire \builder_sync_f_array_muxed1 - attribute \src "ls180.v:2679.11-2679.40" + attribute \src "ls180.v:2692.11-2692.40" wire width 2 \builder_sync_rhs_array_muxed0 - attribute \src "ls180.v:2680.12-2680.41" + attribute \src "ls180.v:2693.12-2693.41" wire width 13 \builder_sync_rhs_array_muxed1 - attribute \src "ls180.v:2681.5-2681.34" + attribute \src "ls180.v:2694.5-2694.34" wire \builder_sync_rhs_array_muxed2 - attribute \src "ls180.v:2682.5-2682.34" + attribute \src "ls180.v:2695.5-2695.34" wire \builder_sync_rhs_array_muxed3 - attribute \src "ls180.v:2683.5-2683.34" + attribute \src "ls180.v:2696.5-2696.34" wire \builder_sync_rhs_array_muxed4 - attribute \src "ls180.v:2684.5-2684.34" + attribute \src "ls180.v:2697.5-2697.34" wire \builder_sync_rhs_array_muxed5 - attribute \src "ls180.v:2685.5-2685.34" + attribute \src "ls180.v:2698.5-2698.34" wire \builder_sync_rhs_array_muxed6 - attribute \src "ls180.v:1939.6-1939.18" + attribute \src "ls180.v:1952.6-1952.18" wire \builder_wait - attribute \src "ls180.v:19.19-19.23" - wire width 3 input 15 \eint - attribute \src "ls180.v:137.12-137.18" + attribute \src "ls180.v:34.19-34.23" + wire width 3 input 30 \eint + attribute \src "ls180.v:151.12-151.18" wire width 3 \eint_1 - attribute \src "ls180.v:28.20-28.26" - wire width 16 input 24 \gpio_i - attribute \src "ls180.v:29.21-29.27" - wire width 16 output 25 \gpio_o - attribute \src "ls180.v:30.21-30.28" - wire width 16 output 26 \gpio_oe - attribute \src "ls180.v:31.14-31.21" - wire output 27 \i2c_scl - attribute \src "ls180.v:32.13-32.22" - wire input 28 \i2c_sda_i - attribute \src "ls180.v:33.14-33.23" - wire output 29 \i2c_sda_o - attribute \src "ls180.v:34.14-34.24" - wire output 30 \i2c_sda_oe + attribute \src "ls180.v:24.20-24.26" + wire width 16 input 20 \gpio_i + attribute \src "ls180.v:25.20-25.26" + wire width 16 output 21 \gpio_o + attribute \src "ls180.v:26.20-26.27" + wire width 16 output 22 \gpio_oe + attribute \src "ls180.v:35.14-35.21" + wire output 31 \i2c_scl + attribute \src "ls180.v:36.13-36.22" + wire input 32 \i2c_sda_i + attribute \src "ls180.v:37.14-37.23" + wire output 33 \i2c_sda_o + attribute \src "ls180.v:38.14-38.24" + wire output 34 \i2c_sda_oe attribute \src "ls180.v:49.13-49.21" wire input 45 \jtag_tck attribute \src "ls180.v:50.13-50.21" @@ -231673,208 +232003,288 @@ module \ls180 wire output 47 \jtag_tdo attribute \src "ls180.v:48.13-48.21" wire input 44 \jtag_tms - attribute \src "ls180.v:879.6-879.18" + attribute \src "ls180.v:878.6-878.18" wire \main_ack_cmd - attribute \src "ls180.v:881.6-881.20" - wire \main_ack_rdata attribute \src "ls180.v:880.6-880.20" + wire \main_ack_rdata + attribute \src "ls180.v:879.6-879.20" wire \main_ack_wdata - attribute \src "ls180.v:877.5-877.22" + attribute \src "ls180.v:876.5-876.22" wire \main_cmd_consumed - attribute \src "ls180.v:874.5-874.27" + attribute \src "ls180.v:259.5-259.28" + wire \main_converter0_counter + attribute \src "ls180.v:1782.5-1782.50" + wire \main_converter0_counter_converter0_next_value + attribute \src "ls180.v:1783.5-1783.53" + wire \main_converter0_counter_converter0_next_value_ce + attribute \src "ls180.v:261.12-261.33" + wire width 64 \main_converter0_dat_r + attribute \src "ls180.v:260.6-260.27" + wire \main_converter0_reset + attribute \src "ls180.v:258.5-258.25" + wire \main_converter0_skip + attribute \src "ls180.v:274.5-274.28" + wire \main_converter1_counter + attribute \src "ls180.v:1786.5-1786.50" + wire \main_converter1_counter_converter1_next_value + attribute \src "ls180.v:1787.5-1787.53" + wire \main_converter1_counter_converter1_next_value_ce + attribute \src "ls180.v:276.12-276.33" + wire width 64 \main_converter1_dat_r + attribute \src "ls180.v:275.6-275.27" + wire \main_converter1_reset + attribute \src "ls180.v:273.5-273.25" + wire \main_converter1_skip + attribute \src "ls180.v:873.5-873.27" wire \main_converter_counter - attribute \src "ls180.v:1822.5-1822.48" + attribute \src "ls180.v:1827.5-1827.48" wire \main_converter_counter_converter_next_value - attribute \src "ls180.v:1823.5-1823.51" + attribute \src "ls180.v:1828.5-1828.51" wire \main_converter_counter_converter_next_value_ce - attribute \src "ls180.v:876.12-876.32" + attribute \src "ls180.v:875.12-875.32" wire width 32 \main_converter_dat_r - attribute \src "ls180.v:875.6-875.26" + attribute \src "ls180.v:874.6-874.26" wire \main_converter_reset - attribute \src "ls180.v:873.5-873.24" + attribute \src "ls180.v:872.5-872.24" wire \main_converter_skip - attribute \src "ls180.v:303.6-303.23" + attribute \src "ls180.v:290.6-290.23" wire \main_dfi_p0_act_n - attribute \src "ls180.v:294.13-294.32" + attribute \src "ls180.v:281.13-281.32" wire width 13 \main_dfi_p0_address - attribute \src "ls180.v:295.12-295.28" + attribute \src "ls180.v:282.12-282.28" wire width 2 \main_dfi_p0_bank - attribute \src "ls180.v:296.6-296.23" + attribute \src "ls180.v:283.6-283.23" wire \main_dfi_p0_cas_n - attribute \src "ls180.v:300.6-300.21" + attribute \src "ls180.v:287.6-287.21" wire \main_dfi_p0_cke - attribute \src "ls180.v:297.6-297.22" + attribute \src "ls180.v:284.6-284.22" wire \main_dfi_p0_cs_n - attribute \src "ls180.v:301.6-301.21" + attribute \src "ls180.v:288.6-288.21" wire \main_dfi_p0_odt - attribute \src "ls180.v:298.6-298.23" + attribute \src "ls180.v:285.6-285.23" wire \main_dfi_p0_ras_n - attribute \src "ls180.v:308.12-308.30" + attribute \src "ls180.v:295.12-295.30" wire width 16 \main_dfi_p0_rddata - attribute \src "ls180.v:307.6-307.27" + attribute \src "ls180.v:294.6-294.27" wire \main_dfi_p0_rddata_en - attribute \src "ls180.v:309.5-309.29" + attribute \src "ls180.v:296.5-296.29" wire \main_dfi_p0_rddata_valid - attribute \src "ls180.v:302.6-302.25" + attribute \src "ls180.v:289.6-289.25" wire \main_dfi_p0_reset_n - attribute \src "ls180.v:299.6-299.22" + attribute \src "ls180.v:286.6-286.22" wire \main_dfi_p0_we_n - attribute \src "ls180.v:304.13-304.31" + attribute \src "ls180.v:291.13-291.31" wire width 16 \main_dfi_p0_wrdata - attribute \src "ls180.v:305.6-305.27" + attribute \src "ls180.v:292.6-292.27" wire \main_dfi_p0_wrdata_en - attribute \src "ls180.v:306.12-306.35" + attribute \src "ls180.v:293.12-293.35" wire width 2 \main_dfi_p0_wrdata_mask - attribute \src "ls180.v:1108.12-1108.22" + attribute \src "ls180.v:1113.12-1113.22" wire width 24 \main_dummy - attribute \src "ls180.v:1025.5-1025.20" - wire \main_gpio_oe_re - attribute \src "ls180.v:1024.12-1024.32" - wire width 16 \main_gpio_oe_storage - attribute \src "ls180.v:1029.5-1029.21" - wire \main_gpio_out_re - attribute \src "ls180.v:1028.12-1028.33" - wire width 16 \main_gpio_out_storage - attribute \src "ls180.v:1030.13-1030.29" - wire width 16 \main_gpio_pads_i - attribute \src "ls180.v:1031.13-1031.29" - wire width 16 \main_gpio_pads_o - attribute \src "ls180.v:1032.13-1032.30" - wire width 16 \main_gpio_pads_oe - attribute \src "ls180.v:1026.12-1026.28" - wire width 16 \main_gpio_status - attribute \src "ls180.v:1027.6-1027.18" - wire \main_gpio_we - attribute \src "ls180.v:1130.6-1130.17" + attribute \src "ls180.v:1023.12-1023.45" + wire width 16 \main_gpiotristateasic0_oe_storage + attribute \src "ls180.v:1025.12-1025.46" + wire width 16 \main_gpiotristateasic0_out_storage + attribute \src "ls180.v:1026.13-1026.42" + wire width 16 \main_gpiotristateasic0_pads_i + attribute \src "ls180.v:1027.13-1027.42" + wire width 16 \main_gpiotristateasic0_pads_o + attribute \src "ls180.v:1028.13-1028.43" + wire width 16 \main_gpiotristateasic0_pads_oe + attribute \src "ls180.v:1024.12-1024.41" + wire width 16 \main_gpiotristateasic0_status + attribute \src "ls180.v:1030.5-1030.33" + wire \main_gpiotristateasic1_oe_re + attribute \src "ls180.v:1029.12-1029.45" + wire width 16 \main_gpiotristateasic1_oe_storage + attribute \src "ls180.v:1034.5-1034.34" + wire \main_gpiotristateasic1_out_re + attribute \src "ls180.v:1033.12-1033.46" + wire width 16 \main_gpiotristateasic1_out_storage + attribute \src "ls180.v:1035.13-1035.42" + wire width 16 \main_gpiotristateasic1_pads_i + attribute \src "ls180.v:1036.13-1036.42" + wire width 16 \main_gpiotristateasic1_pads_o + attribute \src "ls180.v:1037.13-1037.43" + wire width 16 \main_gpiotristateasic1_pads_oe + attribute \src "ls180.v:1031.12-1031.41" + wire width 16 \main_gpiotristateasic1_status + attribute \src "ls180.v:1032.6-1032.31" + wire \main_gpiotristateasic1_we + attribute \src "ls180.v:1135.6-1135.17" wire \main_i2c_oe - attribute \src "ls180.v:1133.5-1133.16" + attribute \src "ls180.v:1138.5-1138.16" wire \main_i2c_re - attribute \src "ls180.v:1129.6-1129.18" + attribute \src "ls180.v:1134.6-1134.18" wire \main_i2c_scl - attribute \src "ls180.v:1131.6-1131.19" + attribute \src "ls180.v:1136.6-1136.19" wire \main_i2c_sda0 - attribute \src "ls180.v:1134.6-1134.19" + attribute \src "ls180.v:1139.6-1139.19" wire \main_i2c_sda1 - attribute \src "ls180.v:1135.6-1135.21" + attribute \src "ls180.v:1140.6-1140.21" wire \main_i2c_status - attribute \src "ls180.v:1132.11-1132.27" + attribute \src "ls180.v:1137.11-1137.27" wire width 3 \main_i2c_storage - attribute \src "ls180.v:1136.6-1136.17" + attribute \src "ls180.v:1141.6-1141.17" wire \main_i2c_we - attribute \src "ls180.v:293.5-293.17" + attribute \src "ls180.v:280.5-280.17" wire \main_int_rst - attribute \src "ls180.v:1596.6-1596.29" + attribute \src "ls180.v:1601.6-1601.29" wire \main_interface0_bus_ack - attribute \src "ls180.v:1590.13-1590.36" + attribute \src "ls180.v:1595.13-1595.36" wire width 32 \main_interface0_bus_adr - attribute \src "ls180.v:1599.11-1599.34" + attribute \src "ls180.v:1604.11-1604.34" wire width 2 \main_interface0_bus_bte - attribute \src "ls180.v:1598.11-1598.34" + attribute \src "ls180.v:1603.11-1603.34" wire width 3 \main_interface0_bus_cti - attribute \src "ls180.v:1594.6-1594.29" + attribute \src "ls180.v:1599.6-1599.29" wire \main_interface0_bus_cyc - attribute \src "ls180.v:1592.13-1592.38" - wire width 32 \main_interface0_bus_dat_r - attribute \src "ls180.v:1591.13-1591.38" - wire width 32 \main_interface0_bus_dat_w - attribute \src "ls180.v:1600.6-1600.29" + attribute \src "ls180.v:1597.13-1597.38" + wire width 64 \main_interface0_bus_dat_r + attribute \src "ls180.v:1596.13-1596.38" + wire width 64 \main_interface0_bus_dat_w + attribute \src "ls180.v:1605.6-1605.29" wire \main_interface0_bus_err - attribute \src "ls180.v:1593.12-1593.35" - wire width 4 \main_interface0_bus_sel - attribute \src "ls180.v:1595.6-1595.29" + attribute \src "ls180.v:1598.12-1598.35" + wire width 8 \main_interface0_bus_sel + attribute \src "ls180.v:1600.6-1600.29" wire \main_interface0_bus_stb - attribute \src "ls180.v:1597.6-1597.28" + attribute \src "ls180.v:1602.6-1602.28" wire \main_interface0_bus_we - attribute \src "ls180.v:251.5-251.32" + attribute \src "ls180.v:253.5-253.44" + wire \main_interface0_converted_interface_ack + attribute \src "ls180.v:247.13-247.52" + wire width 30 \main_interface0_converted_interface_adr + attribute \src "ls180.v:256.12-256.51" + wire width 2 \main_interface0_converted_interface_bte + attribute \src "ls180.v:255.12-255.51" + wire width 3 \main_interface0_converted_interface_cti + attribute \src "ls180.v:251.6-251.45" + wire \main_interface0_converted_interface_cyc + attribute \src "ls180.v:249.13-249.54" + wire width 64 \main_interface0_converted_interface_dat_r + attribute \src "ls180.v:248.13-248.54" + wire width 64 \main_interface0_converted_interface_dat_w + attribute \src "ls180.v:257.5-257.44" + wire \main_interface0_converted_interface_err + attribute \src "ls180.v:250.12-250.51" + wire width 8 \main_interface0_converted_interface_sel + attribute \src "ls180.v:252.6-252.45" + wire \main_interface0_converted_interface_stb + attribute \src "ls180.v:254.6-254.44" + wire \main_interface0_converted_interface_we + attribute \src "ls180.v:208.5-208.32" wire \main_interface0_ram_bus_ack - attribute \src "ls180.v:245.13-245.40" + attribute \src "ls180.v:202.13-202.40" wire width 30 \main_interface0_ram_bus_adr - attribute \src "ls180.v:254.12-254.39" + attribute \src "ls180.v:211.12-211.39" wire width 2 \main_interface0_ram_bus_bte - attribute \src "ls180.v:253.12-253.39" + attribute \src "ls180.v:210.12-210.39" wire width 3 \main_interface0_ram_bus_cti - attribute \src "ls180.v:249.6-249.33" + attribute \src "ls180.v:206.6-206.33" wire \main_interface0_ram_bus_cyc - attribute \src "ls180.v:247.13-247.42" - wire width 32 \main_interface0_ram_bus_dat_r - attribute \src "ls180.v:246.13-246.42" - wire width 32 \main_interface0_ram_bus_dat_w - attribute \src "ls180.v:255.5-255.32" + attribute \src "ls180.v:204.13-204.42" + wire width 64 \main_interface0_ram_bus_dat_r + attribute \src "ls180.v:203.13-203.42" + wire width 64 \main_interface0_ram_bus_dat_w + attribute \src "ls180.v:212.5-212.32" wire \main_interface0_ram_bus_err - attribute \src "ls180.v:248.12-248.39" - wire width 4 \main_interface0_ram_bus_sel - attribute \src "ls180.v:250.6-250.33" + attribute \src "ls180.v:205.12-205.39" + wire width 8 \main_interface0_ram_bus_sel + attribute \src "ls180.v:207.6-207.33" wire \main_interface0_ram_bus_stb - attribute \src "ls180.v:252.6-252.32" + attribute \src "ls180.v:209.6-209.32" wire \main_interface0_ram_bus_we - attribute \src "ls180.v:1687.6-1687.29" + attribute \src "ls180.v:1692.6-1692.29" wire \main_interface1_bus_ack - attribute \src "ls180.v:1681.12-1681.35" + attribute \src "ls180.v:1686.12-1686.35" wire width 32 \main_interface1_bus_adr - attribute \src "ls180.v:1690.11-1690.34" + attribute \src "ls180.v:1695.11-1695.34" wire width 2 \main_interface1_bus_bte - attribute \src "ls180.v:1689.11-1689.34" + attribute \src "ls180.v:1694.11-1694.34" wire width 3 \main_interface1_bus_cti - attribute \src "ls180.v:1685.5-1685.28" + attribute \src "ls180.v:1690.5-1690.28" wire \main_interface1_bus_cyc - attribute \src "ls180.v:1683.13-1683.38" - wire width 32 \main_interface1_bus_dat_r - attribute \src "ls180.v:1682.12-1682.37" - wire width 32 \main_interface1_bus_dat_w - attribute \src "ls180.v:1691.6-1691.29" + attribute \src "ls180.v:1688.13-1688.38" + wire width 64 \main_interface1_bus_dat_r + attribute \src "ls180.v:1687.12-1687.37" + wire width 64 \main_interface1_bus_dat_w + attribute \src "ls180.v:1696.6-1696.29" wire \main_interface1_bus_err - attribute \src "ls180.v:1684.11-1684.34" - wire width 4 \main_interface1_bus_sel - attribute \src "ls180.v:1686.5-1686.28" + attribute \src "ls180.v:1689.11-1689.34" + wire width 8 \main_interface1_bus_sel + attribute \src "ls180.v:1691.5-1691.28" wire \main_interface1_bus_stb - attribute \src "ls180.v:1688.5-1688.27" + attribute \src "ls180.v:1693.5-1693.27" wire \main_interface1_bus_we - attribute \src "ls180.v:266.5-266.32" + attribute \src "ls180.v:268.5-268.44" + wire \main_interface1_converted_interface_ack + attribute \src "ls180.v:262.13-262.52" + wire width 30 \main_interface1_converted_interface_adr + attribute \src "ls180.v:271.12-271.51" + wire width 2 \main_interface1_converted_interface_bte + attribute \src "ls180.v:270.12-270.51" + wire width 3 \main_interface1_converted_interface_cti + attribute \src "ls180.v:266.6-266.45" + wire \main_interface1_converted_interface_cyc + attribute \src "ls180.v:264.13-264.54" + wire width 64 \main_interface1_converted_interface_dat_r + attribute \src "ls180.v:263.13-263.54" + wire width 64 \main_interface1_converted_interface_dat_w + attribute \src "ls180.v:272.5-272.44" + wire \main_interface1_converted_interface_err + attribute \src "ls180.v:265.12-265.51" + wire width 8 \main_interface1_converted_interface_sel + attribute \src "ls180.v:267.6-267.45" + wire \main_interface1_converted_interface_stb + attribute \src "ls180.v:269.6-269.44" + wire \main_interface1_converted_interface_we + attribute \src "ls180.v:223.5-223.32" wire \main_interface1_ram_bus_ack - attribute \src "ls180.v:260.13-260.40" + attribute \src "ls180.v:217.13-217.40" wire width 30 \main_interface1_ram_bus_adr - attribute \src "ls180.v:269.12-269.39" + attribute \src "ls180.v:226.12-226.39" wire width 2 \main_interface1_ram_bus_bte - attribute \src "ls180.v:268.12-268.39" + attribute \src "ls180.v:225.12-225.39" wire width 3 \main_interface1_ram_bus_cti - attribute \src "ls180.v:264.6-264.33" + attribute \src "ls180.v:221.6-221.33" wire \main_interface1_ram_bus_cyc - attribute \src "ls180.v:262.13-262.42" - wire width 32 \main_interface1_ram_bus_dat_r - attribute \src "ls180.v:261.13-261.42" - wire width 32 \main_interface1_ram_bus_dat_w - attribute \src "ls180.v:270.5-270.32" + attribute \src "ls180.v:219.13-219.42" + wire width 64 \main_interface1_ram_bus_dat_r + attribute \src "ls180.v:218.13-218.42" + wire width 64 \main_interface1_ram_bus_dat_w + attribute \src "ls180.v:227.5-227.32" wire \main_interface1_ram_bus_err - attribute \src "ls180.v:263.12-263.39" - wire width 4 \main_interface1_ram_bus_sel - attribute \src "ls180.v:265.6-265.33" + attribute \src "ls180.v:220.12-220.39" + wire width 8 \main_interface1_ram_bus_sel + attribute \src "ls180.v:222.6-222.33" wire \main_interface1_ram_bus_stb - attribute \src "ls180.v:267.6-267.32" + attribute \src "ls180.v:224.6-224.32" wire \main_interface1_ram_bus_we - attribute \src "ls180.v:281.5-281.32" + attribute \src "ls180.v:238.5-238.32" wire \main_interface2_ram_bus_ack - attribute \src "ls180.v:275.13-275.40" + attribute \src "ls180.v:232.13-232.40" wire width 30 \main_interface2_ram_bus_adr - attribute \src "ls180.v:284.12-284.39" + attribute \src "ls180.v:241.12-241.39" wire width 2 \main_interface2_ram_bus_bte - attribute \src "ls180.v:283.12-283.39" + attribute \src "ls180.v:240.12-240.39" wire width 3 \main_interface2_ram_bus_cti - attribute \src "ls180.v:279.6-279.33" + attribute \src "ls180.v:236.6-236.33" wire \main_interface2_ram_bus_cyc - attribute \src "ls180.v:277.13-277.42" - wire width 32 \main_interface2_ram_bus_dat_r - attribute \src "ls180.v:276.13-276.42" - wire width 32 \main_interface2_ram_bus_dat_w - attribute \src "ls180.v:285.5-285.32" + attribute \src "ls180.v:234.13-234.42" + wire width 64 \main_interface2_ram_bus_dat_r + attribute \src "ls180.v:233.13-233.42" + wire width 64 \main_interface2_ram_bus_dat_w + attribute \src "ls180.v:242.5-242.32" wire \main_interface2_ram_bus_err - attribute \src "ls180.v:278.12-278.39" - wire width 4 \main_interface2_ram_bus_sel - attribute \src "ls180.v:280.6-280.33" + attribute \src "ls180.v:235.12-235.39" + wire width 8 \main_interface2_ram_bus_sel + attribute \src "ls180.v:237.6-237.33" wire \main_interface2_ram_bus_stb - attribute \src "ls180.v:282.6-282.32" + attribute \src "ls180.v:239.6-239.32" wire \main_interface2_ram_bus_we - attribute \src "ls180.v:214.12-214.32" - wire width 7 \main_libresocsim_adr + attribute \src "ls180.v:171.12-171.32" + wire width 6 \main_libresocsim_adr attribute \src "ls180.v:62.6-62.32" wire \main_libresocsim_bus_error attribute \src "ls180.v:63.12-63.39" @@ -231883,217 +232293,119 @@ module \ls180 wire width 32 \main_libresocsim_bus_errors_status attribute \src "ls180.v:60.6-60.36" wire \main_libresocsim_bus_errors_we - attribute \src "ls180.v:170.5-170.40" - wire \main_libresocsim_converter0_counter - attribute \src "ls180.v:1777.5-1777.62" - wire \main_libresocsim_converter0_counter_converter0_next_value - attribute \src "ls180.v:1778.5-1778.65" - wire \main_libresocsim_converter0_counter_converter0_next_value_ce - attribute \src "ls180.v:172.12-172.45" - wire width 64 \main_libresocsim_converter0_dat_r - attribute \src "ls180.v:171.6-171.39" - wire \main_libresocsim_converter0_reset - attribute \src "ls180.v:169.5-169.37" - wire \main_libresocsim_converter0_skip - attribute \src "ls180.v:185.5-185.40" - wire \main_libresocsim_converter1_counter - attribute \src "ls180.v:1781.5-1781.62" - wire \main_libresocsim_converter1_counter_converter1_next_value - attribute \src "ls180.v:1782.5-1782.65" - wire \main_libresocsim_converter1_counter_converter1_next_value_ce - attribute \src "ls180.v:187.12-187.45" - wire width 64 \main_libresocsim_converter1_dat_r - attribute \src "ls180.v:186.6-186.39" - wire \main_libresocsim_converter1_reset - attribute \src "ls180.v:184.5-184.37" - wire \main_libresocsim_converter1_skip - attribute \src "ls180.v:200.5-200.40" - wire \main_libresocsim_converter2_counter - attribute \src "ls180.v:1785.5-1785.62" - wire \main_libresocsim_converter2_counter_converter2_next_value - attribute \src "ls180.v:1786.5-1786.65" - wire \main_libresocsim_converter2_counter_converter2_next_value_ce - attribute \src "ls180.v:202.12-202.45" - wire width 64 \main_libresocsim_converter2_dat_r - attribute \src "ls180.v:201.6-201.39" - wire \main_libresocsim_converter2_reset - attribute \src "ls180.v:199.5-199.37" - wire \main_libresocsim_converter2_skip - attribute \src "ls180.v:215.13-215.35" - wire width 32 \main_libresocsim_dat_r - attribute \src "ls180.v:217.13-217.35" - wire width 32 \main_libresocsim_dat_w - attribute \src "ls180.v:223.5-223.27" + attribute \src "ls180.v:172.13-172.35" + wire width 64 \main_libresocsim_dat_r + attribute \src "ls180.v:174.13-174.35" + wire width 64 \main_libresocsim_dat_w + attribute \src "ls180.v:180.5-180.27" wire \main_libresocsim_en_re - attribute \src "ls180.v:222.5-222.32" + attribute \src "ls180.v:179.5-179.32" wire \main_libresocsim_en_storage - attribute \src "ls180.v:239.6-239.45" + attribute \src "ls180.v:196.6-196.45" wire \main_libresocsim_eventmanager_pending_r - attribute \src "ls180.v:238.6-238.46" + attribute \src "ls180.v:195.6-195.46" wire \main_libresocsim_eventmanager_pending_re - attribute \src "ls180.v:241.6-241.45" + attribute \src "ls180.v:198.6-198.45" wire \main_libresocsim_eventmanager_pending_w - attribute \src "ls180.v:240.6-240.46" + attribute \src "ls180.v:197.6-197.46" wire \main_libresocsim_eventmanager_pending_we - attribute \src "ls180.v:243.5-243.37" + attribute \src "ls180.v:200.5-200.37" wire \main_libresocsim_eventmanager_re - attribute \src "ls180.v:235.6-235.44" + attribute \src "ls180.v:192.6-192.44" wire \main_libresocsim_eventmanager_status_r - attribute \src "ls180.v:234.6-234.45" + attribute \src "ls180.v:191.6-191.45" wire \main_libresocsim_eventmanager_status_re - attribute \src "ls180.v:237.6-237.44" + attribute \src "ls180.v:194.6-194.44" wire \main_libresocsim_eventmanager_status_w - attribute \src "ls180.v:236.6-236.45" + attribute \src "ls180.v:193.6-193.45" wire \main_libresocsim_eventmanager_status_we - attribute \src "ls180.v:242.5-242.42" + attribute \src "ls180.v:199.5-199.42" wire \main_libresocsim_eventmanager_storage - attribute \src "ls180.v:164.6-164.57" - wire \main_libresocsim_interface0_converted_interface_ack - attribute \src "ls180.v:158.12-158.63" - wire width 30 \main_libresocsim_interface0_converted_interface_adr - attribute \src "ls180.v:167.11-167.62" - wire width 2 \main_libresocsim_interface0_converted_interface_bte - attribute \src "ls180.v:166.11-166.62" - wire width 3 \main_libresocsim_interface0_converted_interface_cti - attribute \src "ls180.v:162.5-162.56" - wire \main_libresocsim_interface0_converted_interface_cyc - attribute \src "ls180.v:160.13-160.66" - wire width 32 \main_libresocsim_interface0_converted_interface_dat_r - attribute \src "ls180.v:159.12-159.65" - wire width 32 \main_libresocsim_interface0_converted_interface_dat_w - attribute \src "ls180.v:168.6-168.57" - wire \main_libresocsim_interface0_converted_interface_err - attribute \src "ls180.v:161.11-161.62" - wire width 4 \main_libresocsim_interface0_converted_interface_sel - attribute \src "ls180.v:163.5-163.56" - wire \main_libresocsim_interface0_converted_interface_stb - attribute \src "ls180.v:165.5-165.55" - wire \main_libresocsim_interface0_converted_interface_we - attribute \src "ls180.v:179.6-179.57" - wire \main_libresocsim_interface1_converted_interface_ack - attribute \src "ls180.v:173.12-173.63" - wire width 30 \main_libresocsim_interface1_converted_interface_adr - attribute \src "ls180.v:182.11-182.62" - wire width 2 \main_libresocsim_interface1_converted_interface_bte - attribute \src "ls180.v:181.11-181.62" - wire width 3 \main_libresocsim_interface1_converted_interface_cti - attribute \src "ls180.v:177.5-177.56" - wire \main_libresocsim_interface1_converted_interface_cyc - attribute \src "ls180.v:175.13-175.66" - wire width 32 \main_libresocsim_interface1_converted_interface_dat_r - attribute \src "ls180.v:174.12-174.65" - wire width 32 \main_libresocsim_interface1_converted_interface_dat_w - attribute \src "ls180.v:183.6-183.57" - wire \main_libresocsim_interface1_converted_interface_err - attribute \src "ls180.v:176.11-176.62" - wire width 4 \main_libresocsim_interface1_converted_interface_sel - attribute \src "ls180.v:178.5-178.56" - wire \main_libresocsim_interface1_converted_interface_stb - attribute \src "ls180.v:180.5-180.55" - wire \main_libresocsim_interface1_converted_interface_we - attribute \src "ls180.v:194.6-194.57" - wire \main_libresocsim_interface2_converted_interface_ack - attribute \src "ls180.v:188.12-188.63" - wire width 30 \main_libresocsim_interface2_converted_interface_adr - attribute \src "ls180.v:197.11-197.62" - wire width 2 \main_libresocsim_interface2_converted_interface_bte - attribute \src "ls180.v:196.11-196.62" - wire width 3 \main_libresocsim_interface2_converted_interface_cti - attribute \src "ls180.v:192.5-192.56" - wire \main_libresocsim_interface2_converted_interface_cyc - attribute \src "ls180.v:190.13-190.66" - wire width 32 \main_libresocsim_interface2_converted_interface_dat_r - attribute \src "ls180.v:189.12-189.65" - wire width 32 \main_libresocsim_interface2_converted_interface_dat_w - attribute \src "ls180.v:198.6-198.57" - wire \main_libresocsim_interface2_converted_interface_err - attribute \src "ls180.v:191.11-191.62" - wire width 4 \main_libresocsim_interface2_converted_interface_sel - attribute \src "ls180.v:193.5-193.56" - wire \main_libresocsim_interface2_converted_interface_stb - attribute \src "ls180.v:195.5-195.55" - wire \main_libresocsim_interface2_converted_interface_we - attribute \src "ls180.v:228.6-228.26" + attribute \src "ls180.v:185.6-185.26" wire \main_libresocsim_irq - attribute \src "ls180.v:119.6-119.32" + attribute \src "ls180.v:121.6-121.32" wire \main_libresocsim_libresoc0 - attribute \src "ls180.v:120.6-120.32" + attribute \src "ls180.v:122.6-122.32" wire \main_libresocsim_libresoc1 - attribute \src "ls180.v:121.13-121.39" + attribute \src "ls180.v:123.13-123.39" wire width 64 \main_libresocsim_libresoc2 - attribute \src "ls180.v:123.12-123.45" + attribute \src "ls180.v:125.12-125.45" wire width 2 \main_libresocsim_libresoc_clk_sel - attribute \src "ls180.v:146.13-146.67" + attribute \src "ls180.v:144.13-144.67" wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_i - attribute \src "ls180.v:147.13-147.67" + attribute \src "ls180.v:145.13-145.67" wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_o - attribute \src "ls180.v:148.13-148.68" + attribute \src "ls180.v:146.13-146.68" wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe - attribute \src "ls180.v:149.6-149.61" + attribute \src "ls180.v:152.6-152.61" wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_scl - attribute \src "ls180.v:150.6-150.63" + attribute \src "ls180.v:153.6-153.63" wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i - attribute \src "ls180.v:151.6-151.63" + attribute \src "ls180.v:154.6-154.63" wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_o - attribute \src "ls180.v:152.6-152.64" + attribute \src "ls180.v:155.6-155.64" wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_oe - attribute \src "ls180.v:153.6-153.64" + attribute \src "ls180.v:147.6-147.64" wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_clk - attribute \src "ls180.v:154.6-154.66" + attribute \src "ls180.v:148.6-148.66" wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i - attribute \src "ls180.v:155.6-155.66" + attribute \src "ls180.v:149.6-149.66" wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o - attribute \src "ls180.v:156.6-156.67" + attribute \src "ls180.v:150.6-150.67" wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe - attribute \src "ls180.v:125.13-125.68" + attribute \src "ls180.v:132.13-132.68" wire width 13 \main_libresocsim_libresoc_constraintmanager_obj_sdram_a - attribute \src "ls180.v:134.12-134.68" + attribute \src "ls180.v:141.12-141.68" wire width 2 \main_libresocsim_libresoc_constraintmanager_obj_sdram_ba - attribute \src "ls180.v:131.6-131.65" + attribute \src "ls180.v:138.6-138.65" wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cas_n - attribute \src "ls180.v:133.6-133.63" + attribute \src "ls180.v:140.6-140.63" wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cke - attribute \src "ls180.v:132.6-132.64" + attribute \src "ls180.v:139.6-139.64" wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cs_n - attribute \src "ls180.v:135.12-135.68" + attribute \src "ls180.v:142.12-142.68" wire width 2 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dm - attribute \src "ls180.v:126.13-126.71" + attribute \src "ls180.v:133.13-133.71" wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i - attribute \src "ls180.v:127.13-127.71" + attribute \src "ls180.v:134.13-134.71" wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o - attribute \src "ls180.v:128.6-128.65" + attribute \src "ls180.v:135.6-135.65" wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe - attribute \src "ls180.v:130.6-130.65" + attribute \src "ls180.v:137.6-137.65" wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_ras_n - attribute \src "ls180.v:129.6-129.64" + attribute \src "ls180.v:136.6-136.64" wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_we_n - attribute \src "ls180.v:142.6-142.67" + attribute \src "ls180.v:156.6-156.67" wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_clk - attribute \src "ls180.v:144.6-144.68" + attribute \src "ls180.v:158.6-158.68" wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_cs_n - attribute \src "ls180.v:145.6-145.68" + attribute \src "ls180.v:159.6-159.68" wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso - attribute \src "ls180.v:143.6-143.68" + attribute \src "ls180.v:157.6-157.68" wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_mosi - attribute \src "ls180.v:138.6-138.67" + attribute \src "ls180.v:127.6-127.67" wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_clk - attribute \src "ls180.v:140.6-140.68" + attribute \src "ls180.v:129.6-129.68" wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_cs_n - attribute \src "ls180.v:141.6-141.68" + attribute \src "ls180.v:130.6-130.68" wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso - attribute \src "ls180.v:139.6-139.68" + attribute \src "ls180.v:128.6-128.68" wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_mosi - attribute \src "ls180.v:72.5-72.39" + attribute \src "ls180.v:72.6-72.40" wire \main_libresocsim_libresoc_dbus_ack attribute \src "ls180.v:66.13-66.47" wire width 29 \main_libresocsim_libresoc_dbus_adr + attribute \src "ls180.v:75.11-75.45" + wire width 2 \main_libresocsim_libresoc_dbus_bte + attribute \src "ls180.v:74.11-74.45" + wire width 3 \main_libresocsim_libresoc_dbus_cti attribute \src "ls180.v:70.6-70.40" wire \main_libresocsim_libresoc_dbus_cyc attribute \src "ls180.v:68.13-68.49" wire width 64 \main_libresocsim_libresoc_dbus_dat_r attribute \src "ls180.v:67.13-67.49" wire width 64 \main_libresocsim_libresoc_dbus_dat_w - attribute \src "ls180.v:74.5-74.39" + attribute \src "ls180.v:76.6-76.40" wire \main_libresocsim_libresoc_dbus_err attribute \src "ls180.v:69.12-69.46" wire width 8 \main_libresocsim_libresoc_dbus_sel @@ -232101,45 +232413,53 @@ module \ls180 wire \main_libresocsim_libresoc_dbus_stb attribute \src "ls180.v:73.6-73.39" wire \main_libresocsim_libresoc_dbus_we - attribute \src "ls180.v:81.5-81.39" + attribute \src "ls180.v:83.6-83.40" wire \main_libresocsim_libresoc_ibus_ack - attribute \src "ls180.v:75.13-75.47" + attribute \src "ls180.v:77.13-77.47" wire width 29 \main_libresocsim_libresoc_ibus_adr - attribute \src "ls180.v:79.6-79.40" + attribute \src "ls180.v:86.11-86.45" + wire width 2 \main_libresocsim_libresoc_ibus_bte + attribute \src "ls180.v:85.11-85.45" + wire width 3 \main_libresocsim_libresoc_ibus_cti + attribute \src "ls180.v:81.6-81.40" wire \main_libresocsim_libresoc_ibus_cyc - attribute \src "ls180.v:77.13-77.49" + attribute \src "ls180.v:79.13-79.49" wire width 64 \main_libresocsim_libresoc_ibus_dat_r - attribute \src "ls180.v:76.13-76.49" + attribute \src "ls180.v:78.13-78.49" wire width 64 \main_libresocsim_libresoc_ibus_dat_w - attribute \src "ls180.v:83.5-83.39" + attribute \src "ls180.v:87.6-87.40" wire \main_libresocsim_libresoc_ibus_err - attribute \src "ls180.v:78.12-78.46" + attribute \src "ls180.v:80.12-80.46" wire width 8 \main_libresocsim_libresoc_ibus_sel - attribute \src "ls180.v:80.6-80.40" + attribute \src "ls180.v:82.6-82.40" wire \main_libresocsim_libresoc_ibus_stb - attribute \src "ls180.v:82.6-82.39" + attribute \src "ls180.v:84.6-84.39" wire \main_libresocsim_libresoc_ibus_we attribute \src "ls180.v:65.12-65.47" wire width 16 \main_libresocsim_libresoc_interrupt - attribute \src "ls180.v:115.6-115.40" - wire \main_libresocsim_libresoc_jtag_tck attribute \src "ls180.v:117.6-117.40" + wire \main_libresocsim_libresoc_jtag_tck + attribute \src "ls180.v:119.6-119.40" wire \main_libresocsim_libresoc_jtag_tdi - attribute \src "ls180.v:118.6-118.40" + attribute \src "ls180.v:120.6-120.40" wire \main_libresocsim_libresoc_jtag_tdo - attribute \src "ls180.v:116.6-116.40" + attribute \src "ls180.v:118.6-118.40" wire \main_libresocsim_libresoc_jtag_tms - attribute \src "ls180.v:112.5-112.42" + attribute \src "ls180.v:112.6-112.43" wire \main_libresocsim_libresoc_jtag_wb_ack attribute \src "ls180.v:106.13-106.50" wire width 29 \main_libresocsim_libresoc_jtag_wb_adr + attribute \src "ls180.v:115.11-115.48" + wire width 2 \main_libresocsim_libresoc_jtag_wb_bte + attribute \src "ls180.v:114.11-114.48" + wire width 3 \main_libresocsim_libresoc_jtag_wb_cti attribute \src "ls180.v:110.6-110.43" wire \main_libresocsim_libresoc_jtag_wb_cyc attribute \src "ls180.v:108.13-108.52" wire width 64 \main_libresocsim_libresoc_jtag_wb_dat_r attribute \src "ls180.v:107.13-107.52" wire width 64 \main_libresocsim_libresoc_jtag_wb_dat_w - attribute \src "ls180.v:114.5-114.42" + attribute \src "ls180.v:116.6-116.43" wire \main_libresocsim_libresoc_jtag_wb_err attribute \src "ls180.v:109.12-109.49" wire width 8 \main_libresocsim_libresoc_jtag_wb_sel @@ -232147,85 +232467,77 @@ module \ls180 wire \main_libresocsim_libresoc_jtag_wb_stb attribute \src "ls180.v:113.6-113.42" wire \main_libresocsim_libresoc_jtag_wb_we - attribute \src "ls180.v:122.6-122.40" + attribute \src "ls180.v:124.6-124.40" wire \main_libresocsim_libresoc_pll_18_o - attribute \src "ls180.v:124.6-124.41" + attribute \src "ls180.v:126.6-126.41" wire \main_libresocsim_libresoc_pll_lck_o attribute \src "ls180.v:64.6-64.37" wire \main_libresocsim_libresoc_reset - attribute \src "ls180.v:90.6-90.44" + attribute \src "ls180.v:94.6-94.44" wire \main_libresocsim_libresoc_xics_icp_ack - attribute \src "ls180.v:84.13-84.51" + attribute \src "ls180.v:88.12-88.50" wire width 30 \main_libresocsim_libresoc_xics_icp_adr - attribute \src "ls180.v:93.12-93.50" - wire width 2 \main_libresocsim_libresoc_xics_icp_bte - attribute \src "ls180.v:92.12-92.50" - wire width 3 \main_libresocsim_libresoc_xics_icp_cti - attribute \src "ls180.v:88.6-88.44" + attribute \src "ls180.v:92.5-92.43" wire \main_libresocsim_libresoc_xics_icp_cyc - attribute \src "ls180.v:86.13-86.53" + attribute \src "ls180.v:90.13-90.53" wire width 32 \main_libresocsim_libresoc_xics_icp_dat_r - attribute \src "ls180.v:85.13-85.53" + attribute \src "ls180.v:89.12-89.52" wire width 32 \main_libresocsim_libresoc_xics_icp_dat_w - attribute \src "ls180.v:94.6-94.44" + attribute \src "ls180.v:96.6-96.44" wire \main_libresocsim_libresoc_xics_icp_err - attribute \src "ls180.v:87.12-87.50" + attribute \src "ls180.v:91.11-91.49" wire width 4 \main_libresocsim_libresoc_xics_icp_sel - attribute \src "ls180.v:89.6-89.44" + attribute \src "ls180.v:93.5-93.43" wire \main_libresocsim_libresoc_xics_icp_stb - attribute \src "ls180.v:91.6-91.43" + attribute \src "ls180.v:95.5-95.42" wire \main_libresocsim_libresoc_xics_icp_we - attribute \src "ls180.v:101.6-101.44" + attribute \src "ls180.v:103.6-103.44" wire \main_libresocsim_libresoc_xics_ics_ack - attribute \src "ls180.v:95.13-95.51" + attribute \src "ls180.v:97.12-97.50" wire width 30 \main_libresocsim_libresoc_xics_ics_adr - attribute \src "ls180.v:104.12-104.50" - wire width 2 \main_libresocsim_libresoc_xics_ics_bte - attribute \src "ls180.v:103.12-103.50" - wire width 3 \main_libresocsim_libresoc_xics_ics_cti - attribute \src "ls180.v:99.6-99.44" + attribute \src "ls180.v:101.5-101.43" wire \main_libresocsim_libresoc_xics_ics_cyc - attribute \src "ls180.v:97.13-97.53" + attribute \src "ls180.v:99.13-99.53" wire width 32 \main_libresocsim_libresoc_xics_ics_dat_r - attribute \src "ls180.v:96.13-96.53" + attribute \src "ls180.v:98.12-98.52" wire width 32 \main_libresocsim_libresoc_xics_ics_dat_w attribute \src "ls180.v:105.6-105.44" wire \main_libresocsim_libresoc_xics_ics_err - attribute \src "ls180.v:98.12-98.50" + attribute \src "ls180.v:100.11-100.49" wire width 4 \main_libresocsim_libresoc_xics_ics_sel - attribute \src "ls180.v:100.6-100.44" + attribute \src "ls180.v:102.5-102.43" wire \main_libresocsim_libresoc_xics_ics_stb - attribute \src "ls180.v:102.6-102.43" + attribute \src "ls180.v:104.5-104.42" wire \main_libresocsim_libresoc_xics_ics_we - attribute \src "ls180.v:219.5-219.29" + attribute \src "ls180.v:176.5-176.29" wire \main_libresocsim_load_re - attribute \src "ls180.v:218.12-218.41" + attribute \src "ls180.v:175.12-175.41" wire width 32 \main_libresocsim_load_storage - attribute \src "ls180.v:209.5-209.33" + attribute \src "ls180.v:166.5-166.33" wire \main_libresocsim_ram_bus_ack - attribute \src "ls180.v:203.13-203.41" + attribute \src "ls180.v:160.13-160.41" wire width 30 \main_libresocsim_ram_bus_adr - attribute \src "ls180.v:212.12-212.40" + attribute \src "ls180.v:169.12-169.40" wire width 2 \main_libresocsim_ram_bus_bte - attribute \src "ls180.v:211.12-211.40" + attribute \src "ls180.v:168.12-168.40" wire width 3 \main_libresocsim_ram_bus_cti - attribute \src "ls180.v:207.6-207.34" + attribute \src "ls180.v:164.6-164.34" wire \main_libresocsim_ram_bus_cyc - attribute \src "ls180.v:205.13-205.43" - wire width 32 \main_libresocsim_ram_bus_dat_r - attribute \src "ls180.v:204.13-204.43" - wire width 32 \main_libresocsim_ram_bus_dat_w - attribute \src "ls180.v:213.5-213.33" + attribute \src "ls180.v:162.13-162.43" + wire width 64 \main_libresocsim_ram_bus_dat_r + attribute \src "ls180.v:161.13-161.43" + wire width 64 \main_libresocsim_ram_bus_dat_w + attribute \src "ls180.v:170.5-170.33" wire \main_libresocsim_ram_bus_err - attribute \src "ls180.v:206.12-206.40" - wire width 4 \main_libresocsim_ram_bus_sel - attribute \src "ls180.v:208.6-208.34" + attribute \src "ls180.v:163.12-163.40" + wire width 8 \main_libresocsim_ram_bus_sel + attribute \src "ls180.v:165.6-165.34" wire \main_libresocsim_ram_bus_stb - attribute \src "ls180.v:210.6-210.33" + attribute \src "ls180.v:167.6-167.33" wire \main_libresocsim_ram_bus_we - attribute \src "ls180.v:221.5-221.31" + attribute \src "ls180.v:178.5-178.31" wire \main_libresocsim_reload_re - attribute \src "ls180.v:220.12-220.43" + attribute \src "ls180.v:177.12-177.43" wire width 32 \main_libresocsim_reload_storage attribute \src "ls180.v:61.6-61.28" wire \main_libresocsim_reset @@ -232237,3251 +232549,3279 @@ module \ls180 wire \main_libresocsim_scratch_re attribute \src "ls180.v:57.12-57.44" wire width 32 \main_libresocsim_scratch_storage - attribute \src "ls180.v:225.5-225.37" + attribute \src "ls180.v:182.5-182.37" wire \main_libresocsim_update_value_re - attribute \src "ls180.v:224.5-224.42" + attribute \src "ls180.v:181.5-181.42" wire \main_libresocsim_update_value_storage - attribute \src "ls180.v:244.12-244.34" + attribute \src "ls180.v:201.12-201.34" wire width 32 \main_libresocsim_value - attribute \src "ls180.v:226.12-226.41" + attribute \src "ls180.v:183.12-183.41" wire width 32 \main_libresocsim_value_status - attribute \src "ls180.v:227.6-227.31" + attribute \src "ls180.v:184.6-184.31" wire \main_libresocsim_value_we - attribute \src "ls180.v:216.11-216.30" - wire width 4 \main_libresocsim_we - attribute \src "ls180.v:232.5-232.32" + attribute \src "ls180.v:173.11-173.30" + wire width 8 \main_libresocsim_we + attribute \src "ls180.v:189.5-189.32" wire \main_libresocsim_zero_clear - attribute \src "ls180.v:233.5-233.38" + attribute \src "ls180.v:190.5-190.38" wire \main_libresocsim_zero_old_trigger - attribute \src "ls180.v:230.5-230.34" + attribute \src "ls180.v:187.5-187.34" wire \main_libresocsim_zero_pending - attribute \src "ls180.v:229.6-229.34" + attribute \src "ls180.v:186.6-186.34" wire \main_libresocsim_zero_status - attribute \src "ls180.v:231.6-231.35" + attribute \src "ls180.v:188.6-188.35" wire \main_libresocsim_zero_trigger - attribute \src "ls180.v:871.6-871.26" + attribute \src "ls180.v:870.6-870.26" wire \main_litedram_wb_ack - attribute \src "ls180.v:865.12-865.32" + attribute \src "ls180.v:864.12-864.32" wire width 30 \main_litedram_wb_adr - attribute \src "ls180.v:869.5-869.25" + attribute \src "ls180.v:868.5-868.25" wire \main_litedram_wb_cyc - attribute \src "ls180.v:867.13-867.35" + attribute \src "ls180.v:866.13-866.35" wire width 16 \main_litedram_wb_dat_r - attribute \src "ls180.v:866.12-866.34" + attribute \src "ls180.v:865.12-865.34" wire width 16 \main_litedram_wb_dat_w - attribute \src "ls180.v:868.11-868.31" + attribute \src "ls180.v:867.11-867.31" wire width 2 \main_litedram_wb_sel - attribute \src "ls180.v:870.5-870.25" + attribute \src "ls180.v:869.5-869.25" wire \main_litedram_wb_stb - attribute \src "ls180.v:872.5-872.24" + attribute \src "ls180.v:871.5-871.24" wire \main_litedram_wb_we - attribute \src "ls180.v:1107.13-1107.20" + attribute \src "ls180.v:1112.13-1112.20" wire width 24 \main_nc - attribute \src "ls180.v:844.6-844.24" + attribute \src "ls180.v:831.6-831.24" wire \main_port_cmd_last - attribute \src "ls180.v:846.13-846.39" + attribute \src "ls180.v:833.13-833.39" wire width 24 \main_port_cmd_payload_addr - attribute \src "ls180.v:845.6-845.30" + attribute \src "ls180.v:832.6-832.30" wire \main_port_cmd_payload_we - attribute \src "ls180.v:843.6-843.25" + attribute \src "ls180.v:830.6-830.25" wire \main_port_cmd_ready - attribute \src "ls180.v:842.6-842.25" + attribute \src "ls180.v:829.6-829.25" wire \main_port_cmd_valid - attribute \src "ls180.v:841.6-841.21" + attribute \src "ls180.v:828.6-828.21" wire \main_port_flush - attribute \src "ls180.v:853.13-853.41" + attribute \src "ls180.v:840.13-840.41" wire width 16 \main_port_rdata_payload_data - attribute \src "ls180.v:852.6-852.27" + attribute \src "ls180.v:839.6-839.27" wire \main_port_rdata_ready - attribute \src "ls180.v:851.6-851.27" + attribute \src "ls180.v:838.6-838.27" wire \main_port_rdata_valid - attribute \src "ls180.v:849.13-849.41" + attribute \src "ls180.v:836.13-836.41" wire width 16 \main_port_wdata_payload_data - attribute \src "ls180.v:850.12-850.38" + attribute \src "ls180.v:837.12-837.38" wire width 2 \main_port_wdata_payload_we - attribute \src "ls180.v:848.6-848.27" + attribute \src "ls180.v:835.6-835.27" wire \main_port_wdata_ready - attribute \src "ls180.v:847.6-847.27" + attribute \src "ls180.v:834.6-834.27" wire \main_port_wdata_valid - attribute \src "ls180.v:1112.12-1112.29" + attribute \src "ls180.v:1117.12-1117.29" wire width 32 \main_pwm0_counter - attribute \src "ls180.v:1109.6-1109.22" + attribute \src "ls180.v:1114.6-1114.22" wire \main_pwm0_enable - attribute \src "ls180.v:1114.5-1114.24" + attribute \src "ls180.v:1119.5-1119.24" wire \main_pwm0_enable_re - attribute \src "ls180.v:1113.5-1113.29" + attribute \src "ls180.v:1118.5-1118.29" wire \main_pwm0_enable_storage - attribute \src "ls180.v:1111.13-1111.29" + attribute \src "ls180.v:1116.13-1116.29" wire width 32 \main_pwm0_period - attribute \src "ls180.v:1118.5-1118.24" + attribute \src "ls180.v:1123.5-1123.24" wire \main_pwm0_period_re - attribute \src "ls180.v:1117.12-1117.36" + attribute \src "ls180.v:1122.12-1122.36" wire width 32 \main_pwm0_period_storage - attribute \src "ls180.v:1110.13-1110.28" + attribute \src "ls180.v:1115.13-1115.28" wire width 32 \main_pwm0_width - attribute \src "ls180.v:1116.5-1116.23" + attribute \src "ls180.v:1121.5-1121.23" wire \main_pwm0_width_re - attribute \src "ls180.v:1115.12-1115.35" + attribute \src "ls180.v:1120.12-1120.35" wire width 32 \main_pwm0_width_storage - attribute \src "ls180.v:1122.12-1122.29" + attribute \src "ls180.v:1127.12-1127.29" wire width 32 \main_pwm1_counter - attribute \src "ls180.v:1119.6-1119.22" + attribute \src "ls180.v:1124.6-1124.22" wire \main_pwm1_enable - attribute \src "ls180.v:1124.5-1124.24" + attribute \src "ls180.v:1129.5-1129.24" wire \main_pwm1_enable_re - attribute \src "ls180.v:1123.5-1123.29" + attribute \src "ls180.v:1128.5-1128.29" wire \main_pwm1_enable_storage - attribute \src "ls180.v:1121.13-1121.29" + attribute \src "ls180.v:1126.13-1126.29" wire width 32 \main_pwm1_period - attribute \src "ls180.v:1128.5-1128.24" + attribute \src "ls180.v:1133.5-1133.24" wire \main_pwm1_period_re - attribute \src "ls180.v:1127.12-1127.36" + attribute \src "ls180.v:1132.12-1132.36" wire width 32 \main_pwm1_period_storage - attribute \src "ls180.v:1120.13-1120.28" + attribute \src "ls180.v:1125.13-1125.28" wire width 32 \main_pwm1_width - attribute \src "ls180.v:1126.5-1126.23" + attribute \src "ls180.v:1131.5-1131.23" wire \main_pwm1_width_re - attribute \src "ls180.v:1125.12-1125.35" + attribute \src "ls180.v:1130.12-1130.35" wire width 32 \main_pwm1_width_storage - attribute \src "ls180.v:310.11-310.25" + attribute \src "ls180.v:297.11-297.25" wire width 3 \main_rddata_en - attribute \src "ls180.v:1650.11-1650.43" - wire width 2 \main_sdblock2mem_converter_demux - attribute \src "ls180.v:1651.6-1651.42" + attribute \src "ls180.v:1655.11-1655.43" + wire width 3 \main_sdblock2mem_converter_demux + attribute \src "ls180.v:1656.6-1656.42" wire \main_sdblock2mem_converter_load_part - attribute \src "ls180.v:1641.6-1641.43" + attribute \src "ls180.v:1646.6-1646.43" wire \main_sdblock2mem_converter_sink_first - attribute \src "ls180.v:1642.6-1642.42" + attribute \src "ls180.v:1647.6-1647.42" wire \main_sdblock2mem_converter_sink_last - attribute \src "ls180.v:1643.12-1643.56" + attribute \src "ls180.v:1648.12-1648.56" wire width 8 \main_sdblock2mem_converter_sink_payload_data - attribute \src "ls180.v:1640.6-1640.43" + attribute \src "ls180.v:1645.6-1645.43" wire \main_sdblock2mem_converter_sink_ready - attribute \src "ls180.v:1639.6-1639.43" + attribute \src "ls180.v:1644.6-1644.43" wire \main_sdblock2mem_converter_sink_valid - attribute \src "ls180.v:1646.5-1646.44" + attribute \src "ls180.v:1651.5-1651.44" wire \main_sdblock2mem_converter_source_first - attribute \src "ls180.v:1647.5-1647.43" + attribute \src "ls180.v:1652.5-1652.43" wire \main_sdblock2mem_converter_source_last - attribute \src "ls180.v:1648.12-1648.58" - wire width 32 \main_sdblock2mem_converter_source_payload_data - attribute \src "ls180.v:1649.11-1649.70" - wire width 3 \main_sdblock2mem_converter_source_payload_valid_token_count - attribute \src "ls180.v:1645.6-1645.45" + attribute \src "ls180.v:1653.12-1653.58" + wire width 64 \main_sdblock2mem_converter_source_payload_data + attribute \src "ls180.v:1654.11-1654.70" + wire width 4 \main_sdblock2mem_converter_source_payload_valid_token_count + attribute \src "ls180.v:1650.6-1650.45" wire \main_sdblock2mem_converter_source_ready - attribute \src "ls180.v:1644.6-1644.45" + attribute \src "ls180.v:1649.6-1649.45" wire \main_sdblock2mem_converter_source_valid - attribute \src "ls180.v:1652.5-1652.42" + attribute \src "ls180.v:1657.5-1657.42" wire \main_sdblock2mem_converter_strobe_all - attribute \src "ls180.v:1625.11-1625.40" + attribute \src "ls180.v:1630.11-1630.40" wire width 5 \main_sdblock2mem_fifo_consume - attribute \src "ls180.v:1630.6-1630.35" + attribute \src "ls180.v:1635.6-1635.35" wire \main_sdblock2mem_fifo_do_read - attribute \src "ls180.v:1634.6-1634.41" + attribute \src "ls180.v:1639.6-1639.41" wire \main_sdblock2mem_fifo_fifo_in_first - attribute \src "ls180.v:1635.6-1635.40" + attribute \src "ls180.v:1640.6-1640.40" wire \main_sdblock2mem_fifo_fifo_in_last - attribute \src "ls180.v:1633.12-1633.54" + attribute \src "ls180.v:1638.12-1638.54" wire width 8 \main_sdblock2mem_fifo_fifo_in_payload_data - attribute \src "ls180.v:1637.6-1637.42" + attribute \src "ls180.v:1642.6-1642.42" wire \main_sdblock2mem_fifo_fifo_out_first - attribute \src "ls180.v:1638.6-1638.41" + attribute \src "ls180.v:1643.6-1643.41" wire \main_sdblock2mem_fifo_fifo_out_last - attribute \src "ls180.v:1636.12-1636.55" + attribute \src "ls180.v:1641.12-1641.55" wire width 8 \main_sdblock2mem_fifo_fifo_out_payload_data - attribute \src "ls180.v:1622.11-1622.38" + attribute \src "ls180.v:1627.11-1627.38" wire width 6 \main_sdblock2mem_fifo_level - attribute \src "ls180.v:1624.11-1624.40" + attribute \src "ls180.v:1629.11-1629.40" wire width 5 \main_sdblock2mem_fifo_produce - attribute \src "ls180.v:1631.12-1631.44" + attribute \src "ls180.v:1636.12-1636.44" wire width 5 \main_sdblock2mem_fifo_rdport_adr - attribute \src "ls180.v:1632.12-1632.46" + attribute \src "ls180.v:1637.12-1637.46" wire width 10 \main_sdblock2mem_fifo_rdport_dat_r - attribute \src "ls180.v:1623.5-1623.34" + attribute \src "ls180.v:1628.5-1628.34" wire \main_sdblock2mem_fifo_replace - attribute \src "ls180.v:1608.6-1608.38" + attribute \src "ls180.v:1613.6-1613.38" wire \main_sdblock2mem_fifo_sink_first - attribute \src "ls180.v:1609.6-1609.37" + attribute \src "ls180.v:1614.6-1614.37" wire \main_sdblock2mem_fifo_sink_last - attribute \src "ls180.v:1610.12-1610.51" + attribute \src "ls180.v:1615.12-1615.51" wire width 8 \main_sdblock2mem_fifo_sink_payload_data - attribute \src "ls180.v:1607.6-1607.38" + attribute \src "ls180.v:1612.6-1612.38" wire \main_sdblock2mem_fifo_sink_ready - attribute \src "ls180.v:1606.6-1606.38" + attribute \src "ls180.v:1611.6-1611.38" wire \main_sdblock2mem_fifo_sink_valid - attribute \src "ls180.v:1613.6-1613.40" + attribute \src "ls180.v:1618.6-1618.40" wire \main_sdblock2mem_fifo_source_first - attribute \src "ls180.v:1614.6-1614.39" + attribute \src "ls180.v:1619.6-1619.39" wire \main_sdblock2mem_fifo_source_last - attribute \src "ls180.v:1615.12-1615.53" + attribute \src "ls180.v:1620.12-1620.53" wire width 8 \main_sdblock2mem_fifo_source_payload_data - attribute \src "ls180.v:1612.6-1612.40" + attribute \src "ls180.v:1617.6-1617.40" wire \main_sdblock2mem_fifo_source_ready - attribute \src "ls180.v:1611.6-1611.40" + attribute \src "ls180.v:1616.6-1616.40" wire \main_sdblock2mem_fifo_source_valid - attribute \src "ls180.v:1620.12-1620.46" + attribute \src "ls180.v:1625.12-1625.46" wire width 10 \main_sdblock2mem_fifo_syncfifo_din - attribute \src "ls180.v:1621.12-1621.47" + attribute \src "ls180.v:1626.12-1626.47" wire width 10 \main_sdblock2mem_fifo_syncfifo_dout - attribute \src "ls180.v:1618.6-1618.39" + attribute \src "ls180.v:1623.6-1623.39" wire \main_sdblock2mem_fifo_syncfifo_re - attribute \src "ls180.v:1619.6-1619.45" + attribute \src "ls180.v:1624.6-1624.45" wire \main_sdblock2mem_fifo_syncfifo_readable - attribute \src "ls180.v:1616.6-1616.39" + attribute \src "ls180.v:1621.6-1621.39" wire \main_sdblock2mem_fifo_syncfifo_we - attribute \src "ls180.v:1617.6-1617.45" + attribute \src "ls180.v:1622.6-1622.45" wire \main_sdblock2mem_fifo_syncfifo_writable - attribute \src "ls180.v:1626.11-1626.43" + attribute \src "ls180.v:1631.11-1631.43" wire width 5 \main_sdblock2mem_fifo_wrport_adr - attribute \src "ls180.v:1627.12-1627.46" + attribute \src "ls180.v:1632.12-1632.46" wire width 10 \main_sdblock2mem_fifo_wrport_dat_r - attribute \src "ls180.v:1629.12-1629.46" + attribute \src "ls180.v:1634.12-1634.46" wire width 10 \main_sdblock2mem_fifo_wrport_dat_w - attribute \src "ls180.v:1628.6-1628.37" + attribute \src "ls180.v:1633.6-1633.37" wire \main_sdblock2mem_fifo_wrport_we - attribute \src "ls180.v:1603.6-1603.38" + attribute \src "ls180.v:1608.6-1608.38" wire \main_sdblock2mem_sink_sink_first - attribute \src "ls180.v:1604.6-1604.37" + attribute \src "ls180.v:1609.6-1609.37" wire \main_sdblock2mem_sink_sink_last - attribute \src "ls180.v:1660.12-1660.54" + attribute \src "ls180.v:1665.12-1665.54" wire width 32 \main_sdblock2mem_sink_sink_payload_address - attribute \src "ls180.v:1605.12-1605.52" + attribute \src "ls180.v:1610.12-1610.52" wire width 8 \main_sdblock2mem_sink_sink_payload_data0 - attribute \src "ls180.v:1661.12-1661.52" - wire width 32 \main_sdblock2mem_sink_sink_payload_data1 - attribute \src "ls180.v:1602.6-1602.39" + attribute \src "ls180.v:1666.12-1666.52" + wire width 64 \main_sdblock2mem_sink_sink_payload_data1 + attribute \src "ls180.v:1607.6-1607.39" wire \main_sdblock2mem_sink_sink_ready0 - attribute \src "ls180.v:1659.6-1659.39" + attribute \src "ls180.v:1664.6-1664.39" wire \main_sdblock2mem_sink_sink_ready1 - attribute \src "ls180.v:1601.6-1601.39" + attribute \src "ls180.v:1606.6-1606.39" wire \main_sdblock2mem_sink_sink_valid0 - attribute \src "ls180.v:1658.5-1658.38" + attribute \src "ls180.v:1663.5-1663.38" wire \main_sdblock2mem_sink_sink_valid1 - attribute \src "ls180.v:1655.6-1655.42" + attribute \src "ls180.v:1660.6-1660.42" wire \main_sdblock2mem_source_source_first - attribute \src "ls180.v:1656.6-1656.41" + attribute \src "ls180.v:1661.6-1661.41" wire \main_sdblock2mem_source_source_last - attribute \src "ls180.v:1657.13-1657.56" - wire width 32 \main_sdblock2mem_source_source_payload_data - attribute \src "ls180.v:1654.6-1654.42" + attribute \src "ls180.v:1662.13-1662.56" + wire width 64 \main_sdblock2mem_source_source_payload_data + attribute \src "ls180.v:1659.6-1659.42" wire \main_sdblock2mem_source_source_ready - attribute \src "ls180.v:1653.6-1653.42" + attribute \src "ls180.v:1658.6-1658.42" wire \main_sdblock2mem_source_source_valid - attribute \src "ls180.v:1677.13-1677.52" + attribute \src "ls180.v:1682.13-1682.52" wire width 32 \main_sdblock2mem_wishbonedmawriter_base - attribute \src "ls180.v:1668.5-1668.47" + attribute \src "ls180.v:1673.5-1673.47" wire \main_sdblock2mem_wishbonedmawriter_base_re - attribute \src "ls180.v:1667.12-1667.59" + attribute \src "ls180.v:1672.12-1672.59" wire width 64 \main_sdblock2mem_wishbonedmawriter_base_storage - attribute \src "ls180.v:1672.5-1672.49" + attribute \src "ls180.v:1677.5-1677.49" wire \main_sdblock2mem_wishbonedmawriter_enable_re - attribute \src "ls180.v:1671.5-1671.54" + attribute \src "ls180.v:1676.5-1676.54" wire \main_sdblock2mem_wishbonedmawriter_enable_storage - attribute \src "ls180.v:1679.13-1679.54" + attribute \src "ls180.v:1684.13-1684.54" wire width 32 \main_sdblock2mem_wishbonedmawriter_length - attribute \src "ls180.v:1670.5-1670.49" + attribute \src "ls180.v:1675.5-1675.49" wire \main_sdblock2mem_wishbonedmawriter_length_re - attribute \src "ls180.v:1669.12-1669.61" + attribute \src "ls180.v:1674.12-1674.61" wire width 32 \main_sdblock2mem_wishbonedmawriter_length_storage - attribute \src "ls180.v:1676.5-1676.47" + attribute \src "ls180.v:1681.5-1681.47" wire \main_sdblock2mem_wishbonedmawriter_loop_re - attribute \src "ls180.v:1675.5-1675.52" + attribute \src "ls180.v:1680.5-1680.52" wire \main_sdblock2mem_wishbonedmawriter_loop_storage - attribute \src "ls180.v:1678.12-1678.53" + attribute \src "ls180.v:1683.12-1683.53" wire width 32 \main_sdblock2mem_wishbonedmawriter_offset - attribute \src "ls180.v:1898.12-1898.79" + attribute \src "ls180.v:1903.12-1903.79" wire width 32 \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value - attribute \src "ls180.v:1899.5-1899.75" + attribute \src "ls180.v:1904.5-1904.75" wire \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce - attribute \src "ls180.v:1680.6-1680.46" + attribute \src "ls180.v:1685.6-1685.46" wire \main_sdblock2mem_wishbonedmawriter_reset - attribute \src "ls180.v:1664.6-1664.51" + attribute \src "ls180.v:1669.6-1669.51" wire \main_sdblock2mem_wishbonedmawriter_sink_first - attribute \src "ls180.v:1665.6-1665.50" + attribute \src "ls180.v:1670.6-1670.50" wire \main_sdblock2mem_wishbonedmawriter_sink_last - attribute \src "ls180.v:1666.13-1666.65" - wire width 32 \main_sdblock2mem_wishbonedmawriter_sink_payload_data - attribute \src "ls180.v:1663.5-1663.50" + attribute \src "ls180.v:1671.13-1671.65" + wire width 64 \main_sdblock2mem_wishbonedmawriter_sink_payload_data + attribute \src "ls180.v:1668.5-1668.50" wire \main_sdblock2mem_wishbonedmawriter_sink_ready - attribute \src "ls180.v:1662.6-1662.51" + attribute \src "ls180.v:1667.6-1667.51" wire \main_sdblock2mem_wishbonedmawriter_sink_valid - attribute \src "ls180.v:1673.5-1673.46" + attribute \src "ls180.v:1678.5-1678.46" wire \main_sdblock2mem_wishbonedmawriter_status - attribute \src "ls180.v:1674.6-1674.43" + attribute \src "ls180.v:1679.6-1679.43" wire \main_sdblock2mem_wishbonedmawriter_we - attribute \src "ls180.v:1442.5-1442.31" + attribute \src "ls180.v:1447.5-1447.31" wire \main_sdcore_block_count_re - attribute \src "ls180.v:1441.12-1441.43" + attribute \src "ls180.v:1446.12-1446.43" wire width 32 \main_sdcore_block_count_storage - attribute \src "ls180.v:1440.5-1440.32" + attribute \src "ls180.v:1445.5-1445.32" wire \main_sdcore_block_length_re - attribute \src "ls180.v:1439.11-1439.43" + attribute \src "ls180.v:1444.11-1444.43" wire width 10 \main_sdcore_block_length_storage - attribute \src "ls180.v:1426.5-1426.32" + attribute \src "ls180.v:1431.5-1431.32" wire \main_sdcore_cmd_argument_re - attribute \src "ls180.v:1425.12-1425.44" + attribute \src "ls180.v:1430.12-1430.44" wire width 32 \main_sdcore_cmd_argument_storage - attribute \src "ls180.v:1428.5-1428.31" + attribute \src "ls180.v:1433.5-1433.31" wire \main_sdcore_cmd_command_re - attribute \src "ls180.v:1427.12-1427.43" + attribute \src "ls180.v:1432.12-1432.43" wire width 32 \main_sdcore_cmd_command_storage - attribute \src "ls180.v:1581.11-1581.32" + attribute \src "ls180.v:1586.11-1586.32" wire width 3 \main_sdcore_cmd_count - attribute \src "ls180.v:1882.11-1882.55" + attribute \src "ls180.v:1887.11-1887.55" wire width 3 \main_sdcore_cmd_count_sdcore_fsm_next_value2 - attribute \src "ls180.v:1883.5-1883.52" + attribute \src "ls180.v:1888.5-1888.52" wire \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2 - attribute \src "ls180.v:1582.5-1582.25" + attribute \src "ls180.v:1587.5-1587.25" wire \main_sdcore_cmd_done - attribute \src "ls180.v:1878.5-1878.48" + attribute \src "ls180.v:1883.5-1883.48" wire \main_sdcore_cmd_done_sdcore_fsm_next_value0 - attribute \src "ls180.v:1879.5-1879.51" + attribute \src "ls180.v:1884.5-1884.51" wire \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0 - attribute \src "ls180.v:1583.5-1583.26" + attribute \src "ls180.v:1588.5-1588.26" wire \main_sdcore_cmd_error - attribute \src "ls180.v:1886.5-1886.49" + attribute \src "ls180.v:1891.5-1891.49" wire \main_sdcore_cmd_error_sdcore_fsm_next_value4 - attribute \src "ls180.v:1887.5-1887.52" + attribute \src "ls180.v:1892.5-1892.52" wire \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4 - attribute \src "ls180.v:1435.12-1435.40" + attribute \src "ls180.v:1440.12-1440.40" wire width 4 \main_sdcore_cmd_event_status - attribute \src "ls180.v:1436.6-1436.30" + attribute \src "ls180.v:1441.6-1441.30" wire \main_sdcore_cmd_event_we - attribute \src "ls180.v:1433.13-1433.44" + attribute \src "ls180.v:1438.13-1438.44" wire width 128 \main_sdcore_cmd_response_status - attribute \src "ls180.v:1894.13-1894.67" + attribute \src "ls180.v:1899.13-1899.67" wire width 128 \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 - attribute \src "ls180.v:1895.5-1895.62" + attribute \src "ls180.v:1900.5-1900.62" wire \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 - attribute \src "ls180.v:1434.6-1434.33" + attribute \src "ls180.v:1439.6-1439.33" wire \main_sdcore_cmd_response_we - attribute \src "ls180.v:1430.6-1430.28" + attribute \src "ls180.v:1435.6-1435.28" wire \main_sdcore_cmd_send_r - attribute \src "ls180.v:1429.6-1429.29" + attribute \src "ls180.v:1434.6-1434.29" wire \main_sdcore_cmd_send_re - attribute \src "ls180.v:1432.5-1432.27" + attribute \src "ls180.v:1437.5-1437.27" wire \main_sdcore_cmd_send_w - attribute \src "ls180.v:1431.6-1431.29" + attribute \src "ls180.v:1436.6-1436.29" wire \main_sdcore_cmd_send_we - attribute \src "ls180.v:1584.5-1584.28" + attribute \src "ls180.v:1589.5-1589.28" wire \main_sdcore_cmd_timeout - attribute \src "ls180.v:1888.5-1888.51" + attribute \src "ls180.v:1893.5-1893.51" wire \main_sdcore_cmd_timeout_sdcore_fsm_next_value5 - attribute \src "ls180.v:1889.5-1889.54" + attribute \src "ls180.v:1894.5-1894.54" wire \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 - attribute \src "ls180.v:1580.12-1580.32" + attribute \src "ls180.v:1585.12-1585.32" wire width 2 \main_sdcore_cmd_type - attribute \src "ls180.v:1542.11-1542.40" + attribute \src "ls180.v:1547.11-1547.40" wire width 4 \main_sdcore_crc16_checker_cnt - attribute \src "ls180.v:1548.5-1548.39" + attribute \src "ls180.v:1553.5-1553.39" wire \main_sdcore_crc16_checker_crc0_clr - attribute \src "ls180.v:1547.12-1547.46" + attribute \src "ls180.v:1552.12-1552.46" wire width 16 \main_sdcore_crc16_checker_crc0_crc - attribute \src "ls180.v:1543.12-1543.50" + attribute \src "ls180.v:1548.12-1548.50" wire width 16 \main_sdcore_crc16_checker_crc0_crcreg0 - attribute \src "ls180.v:1544.13-1544.51" + attribute \src "ls180.v:1549.13-1549.51" wire width 16 \main_sdcore_crc16_checker_crc0_crcreg1 - attribute \src "ls180.v:1545.13-1545.51" + attribute \src "ls180.v:1550.13-1550.51" wire width 16 \main_sdcore_crc16_checker_crc0_crcreg2 - attribute \src "ls180.v:1549.6-1549.43" + attribute \src "ls180.v:1554.6-1554.43" wire \main_sdcore_crc16_checker_crc0_enable - attribute \src "ls180.v:1546.12-1546.46" + attribute \src "ls180.v:1551.12-1551.46" wire width 2 \main_sdcore_crc16_checker_crc0_val - attribute \src "ls180.v:1555.5-1555.39" + attribute \src "ls180.v:1560.5-1560.39" wire \main_sdcore_crc16_checker_crc1_clr - attribute \src "ls180.v:1554.12-1554.46" + attribute \src "ls180.v:1559.12-1559.46" wire width 16 \main_sdcore_crc16_checker_crc1_crc - attribute \src "ls180.v:1550.12-1550.50" + attribute \src "ls180.v:1555.12-1555.50" wire width 16 \main_sdcore_crc16_checker_crc1_crcreg0 - attribute \src "ls180.v:1551.13-1551.51" + attribute \src "ls180.v:1556.13-1556.51" wire width 16 \main_sdcore_crc16_checker_crc1_crcreg1 - attribute \src "ls180.v:1552.13-1552.51" + attribute \src "ls180.v:1557.13-1557.51" wire width 16 \main_sdcore_crc16_checker_crc1_crcreg2 - attribute \src "ls180.v:1556.6-1556.43" + attribute \src "ls180.v:1561.6-1561.43" wire \main_sdcore_crc16_checker_crc1_enable - attribute \src "ls180.v:1553.12-1553.46" + attribute \src "ls180.v:1558.12-1558.46" wire width 2 \main_sdcore_crc16_checker_crc1_val - attribute \src "ls180.v:1562.5-1562.39" + attribute \src "ls180.v:1567.5-1567.39" wire \main_sdcore_crc16_checker_crc2_clr - attribute \src "ls180.v:1561.12-1561.46" + attribute \src "ls180.v:1566.12-1566.46" wire width 16 \main_sdcore_crc16_checker_crc2_crc - attribute \src "ls180.v:1557.12-1557.50" + attribute \src "ls180.v:1562.12-1562.50" wire width 16 \main_sdcore_crc16_checker_crc2_crcreg0 - attribute \src "ls180.v:1558.13-1558.51" + attribute \src "ls180.v:1563.13-1563.51" wire width 16 \main_sdcore_crc16_checker_crc2_crcreg1 - attribute \src "ls180.v:1559.13-1559.51" + attribute \src "ls180.v:1564.13-1564.51" wire width 16 \main_sdcore_crc16_checker_crc2_crcreg2 - attribute \src "ls180.v:1563.6-1563.43" + attribute \src "ls180.v:1568.6-1568.43" wire \main_sdcore_crc16_checker_crc2_enable - attribute \src "ls180.v:1560.12-1560.46" + attribute \src "ls180.v:1565.12-1565.46" wire width 2 \main_sdcore_crc16_checker_crc2_val - attribute \src "ls180.v:1569.5-1569.39" + attribute \src "ls180.v:1574.5-1574.39" wire \main_sdcore_crc16_checker_crc3_clr - attribute \src "ls180.v:1568.12-1568.46" + attribute \src "ls180.v:1573.12-1573.46" wire width 16 \main_sdcore_crc16_checker_crc3_crc - attribute \src "ls180.v:1564.12-1564.50" + attribute \src "ls180.v:1569.12-1569.50" wire width 16 \main_sdcore_crc16_checker_crc3_crcreg0 - attribute \src "ls180.v:1565.13-1565.51" + attribute \src "ls180.v:1570.13-1570.51" wire width 16 \main_sdcore_crc16_checker_crc3_crcreg1 - attribute \src "ls180.v:1566.13-1566.51" + attribute \src "ls180.v:1571.13-1571.51" wire width 16 \main_sdcore_crc16_checker_crc3_crcreg2 - attribute \src "ls180.v:1570.6-1570.43" + attribute \src "ls180.v:1575.6-1575.43" wire \main_sdcore_crc16_checker_crc3_enable - attribute \src "ls180.v:1567.12-1567.46" + attribute \src "ls180.v:1572.12-1572.46" wire width 2 \main_sdcore_crc16_checker_crc3_val - attribute \src "ls180.v:1571.12-1571.45" + attribute \src "ls180.v:1576.12-1576.45" wire width 16 \main_sdcore_crc16_checker_crctmp0 - attribute \src "ls180.v:1572.12-1572.45" + attribute \src "ls180.v:1577.12-1577.45" wire width 16 \main_sdcore_crc16_checker_crctmp1 - attribute \src "ls180.v:1573.12-1573.45" + attribute \src "ls180.v:1578.12-1578.45" wire width 16 \main_sdcore_crc16_checker_crctmp2 - attribute \src "ls180.v:1574.12-1574.45" + attribute \src "ls180.v:1579.12-1579.45" wire width 16 \main_sdcore_crc16_checker_crctmp3 - attribute \src "ls180.v:1576.12-1576.43" + attribute \src "ls180.v:1581.12-1581.43" wire width 16 \main_sdcore_crc16_checker_fifo0 - attribute \src "ls180.v:1577.12-1577.43" + attribute \src "ls180.v:1582.12-1582.43" wire width 16 \main_sdcore_crc16_checker_fifo1 - attribute \src "ls180.v:1578.12-1578.43" + attribute \src "ls180.v:1583.12-1583.43" wire width 16 \main_sdcore_crc16_checker_fifo2 - attribute \src "ls180.v:1579.12-1579.43" + attribute \src "ls180.v:1584.12-1584.43" wire width 16 \main_sdcore_crc16_checker_fifo3 - attribute \src "ls180.v:1533.5-1533.41" + attribute \src "ls180.v:1538.5-1538.41" wire \main_sdcore_crc16_checker_sink_first - attribute \src "ls180.v:1534.5-1534.40" + attribute \src "ls180.v:1539.5-1539.40" wire \main_sdcore_crc16_checker_sink_last - attribute \src "ls180.v:1535.11-1535.54" + attribute \src "ls180.v:1540.11-1540.54" wire width 8 \main_sdcore_crc16_checker_sink_payload_data - attribute \src "ls180.v:1532.5-1532.41" + attribute \src "ls180.v:1537.5-1537.41" wire \main_sdcore_crc16_checker_sink_ready - attribute \src "ls180.v:1531.5-1531.41" + attribute \src "ls180.v:1536.5-1536.41" wire \main_sdcore_crc16_checker_sink_valid - attribute \src "ls180.v:1538.5-1538.43" + attribute \src "ls180.v:1543.5-1543.43" wire \main_sdcore_crc16_checker_source_first - attribute \src "ls180.v:1539.6-1539.43" + attribute \src "ls180.v:1544.6-1544.43" wire \main_sdcore_crc16_checker_source_last - attribute \src "ls180.v:1540.12-1540.57" + attribute \src "ls180.v:1545.12-1545.57" wire width 8 \main_sdcore_crc16_checker_source_payload_data - attribute \src "ls180.v:1537.6-1537.44" + attribute \src "ls180.v:1542.6-1542.44" wire \main_sdcore_crc16_checker_source_ready - attribute \src "ls180.v:1536.5-1536.43" + attribute \src "ls180.v:1541.5-1541.43" wire \main_sdcore_crc16_checker_source_valid - attribute \src "ls180.v:1541.11-1541.40" + attribute \src "ls180.v:1546.11-1546.40" wire width 8 \main_sdcore_crc16_checker_val - attribute \src "ls180.v:1575.5-1575.36" + attribute \src "ls180.v:1580.5-1580.36" wire \main_sdcore_crc16_checker_valid - attribute \src "ls180.v:1498.11-1498.41" + attribute \src "ls180.v:1503.11-1503.41" wire width 3 \main_sdcore_crc16_inserter_cnt - attribute \src "ls180.v:1874.11-1874.80" + attribute \src "ls180.v:1879.11-1879.80" wire width 3 \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 - attribute \src "ls180.v:1875.5-1875.77" + attribute \src "ls180.v:1880.5-1880.77" wire \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 - attribute \src "ls180.v:1504.6-1504.41" + attribute \src "ls180.v:1509.6-1509.41" wire \main_sdcore_crc16_inserter_crc0_clr - attribute \src "ls180.v:1503.12-1503.47" + attribute \src "ls180.v:1508.12-1508.47" wire width 16 \main_sdcore_crc16_inserter_crc0_crc - attribute \src "ls180.v:1499.12-1499.51" + attribute \src "ls180.v:1504.12-1504.51" wire width 16 \main_sdcore_crc16_inserter_crc0_crcreg0 - attribute \src "ls180.v:1500.13-1500.52" + attribute \src "ls180.v:1505.13-1505.52" wire width 16 \main_sdcore_crc16_inserter_crc0_crcreg1 - attribute \src "ls180.v:1501.13-1501.52" + attribute \src "ls180.v:1506.13-1506.52" wire width 16 \main_sdcore_crc16_inserter_crc0_crcreg2 - attribute \src "ls180.v:1505.6-1505.44" + attribute \src "ls180.v:1510.6-1510.44" wire \main_sdcore_crc16_inserter_crc0_enable - attribute \src "ls180.v:1502.12-1502.47" + attribute \src "ls180.v:1507.12-1507.47" wire width 2 \main_sdcore_crc16_inserter_crc0_val - attribute \src "ls180.v:1511.6-1511.41" + attribute \src "ls180.v:1516.6-1516.41" wire \main_sdcore_crc16_inserter_crc1_clr - attribute \src "ls180.v:1510.12-1510.47" + attribute \src "ls180.v:1515.12-1515.47" wire width 16 \main_sdcore_crc16_inserter_crc1_crc - attribute \src "ls180.v:1506.12-1506.51" + attribute \src "ls180.v:1511.12-1511.51" wire width 16 \main_sdcore_crc16_inserter_crc1_crcreg0 - attribute \src "ls180.v:1507.13-1507.52" + attribute \src "ls180.v:1512.13-1512.52" wire width 16 \main_sdcore_crc16_inserter_crc1_crcreg1 - attribute \src "ls180.v:1508.13-1508.52" + attribute \src "ls180.v:1513.13-1513.52" wire width 16 \main_sdcore_crc16_inserter_crc1_crcreg2 - attribute \src "ls180.v:1512.6-1512.44" + attribute \src "ls180.v:1517.6-1517.44" wire \main_sdcore_crc16_inserter_crc1_enable - attribute \src "ls180.v:1509.12-1509.47" + attribute \src "ls180.v:1514.12-1514.47" wire width 2 \main_sdcore_crc16_inserter_crc1_val - attribute \src "ls180.v:1518.6-1518.41" + attribute \src "ls180.v:1523.6-1523.41" wire \main_sdcore_crc16_inserter_crc2_clr - attribute \src "ls180.v:1517.12-1517.47" + attribute \src "ls180.v:1522.12-1522.47" wire width 16 \main_sdcore_crc16_inserter_crc2_crc - attribute \src "ls180.v:1513.12-1513.51" + attribute \src "ls180.v:1518.12-1518.51" wire width 16 \main_sdcore_crc16_inserter_crc2_crcreg0 - attribute \src "ls180.v:1514.13-1514.52" + attribute \src "ls180.v:1519.13-1519.52" wire width 16 \main_sdcore_crc16_inserter_crc2_crcreg1 - attribute \src "ls180.v:1515.13-1515.52" + attribute \src "ls180.v:1520.13-1520.52" wire width 16 \main_sdcore_crc16_inserter_crc2_crcreg2 - attribute \src "ls180.v:1519.6-1519.44" + attribute \src "ls180.v:1524.6-1524.44" wire \main_sdcore_crc16_inserter_crc2_enable - attribute \src "ls180.v:1516.12-1516.47" + attribute \src "ls180.v:1521.12-1521.47" wire width 2 \main_sdcore_crc16_inserter_crc2_val - attribute \src "ls180.v:1525.6-1525.41" + attribute \src "ls180.v:1530.6-1530.41" wire \main_sdcore_crc16_inserter_crc3_clr - attribute \src "ls180.v:1524.12-1524.47" + attribute \src "ls180.v:1529.12-1529.47" wire width 16 \main_sdcore_crc16_inserter_crc3_crc - attribute \src "ls180.v:1520.12-1520.51" + attribute \src "ls180.v:1525.12-1525.51" wire width 16 \main_sdcore_crc16_inserter_crc3_crcreg0 - attribute \src "ls180.v:1521.13-1521.52" + attribute \src "ls180.v:1526.13-1526.52" wire width 16 \main_sdcore_crc16_inserter_crc3_crcreg1 - attribute \src "ls180.v:1522.13-1522.52" + attribute \src "ls180.v:1527.13-1527.52" wire width 16 \main_sdcore_crc16_inserter_crc3_crcreg2 - attribute \src "ls180.v:1526.6-1526.44" + attribute \src "ls180.v:1531.6-1531.44" wire \main_sdcore_crc16_inserter_crc3_enable - attribute \src "ls180.v:1523.12-1523.47" + attribute \src "ls180.v:1528.12-1528.47" wire width 2 \main_sdcore_crc16_inserter_crc3_val - attribute \src "ls180.v:1527.12-1527.46" + attribute \src "ls180.v:1532.12-1532.46" wire width 16 \main_sdcore_crc16_inserter_crctmp0 - attribute \src "ls180.v:1866.12-1866.85" + attribute \src "ls180.v:1871.12-1871.85" wire width 16 \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 - attribute \src "ls180.v:1867.5-1867.81" + attribute \src "ls180.v:1872.5-1872.81" wire \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 - attribute \src "ls180.v:1528.12-1528.46" + attribute \src "ls180.v:1533.12-1533.46" wire width 16 \main_sdcore_crc16_inserter_crctmp1 - attribute \src "ls180.v:1868.12-1868.85" + attribute \src "ls180.v:1873.12-1873.85" wire width 16 \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 - attribute \src "ls180.v:1869.5-1869.81" + attribute \src "ls180.v:1874.5-1874.81" wire \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 - attribute \src "ls180.v:1529.12-1529.46" + attribute \src "ls180.v:1534.12-1534.46" wire width 16 \main_sdcore_crc16_inserter_crctmp2 - attribute \src "ls180.v:1870.12-1870.85" + attribute \src "ls180.v:1875.12-1875.85" wire width 16 \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 - attribute \src "ls180.v:1871.5-1871.81" + attribute \src "ls180.v:1876.5-1876.81" wire \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 - attribute \src "ls180.v:1530.12-1530.46" + attribute \src "ls180.v:1535.12-1535.46" wire width 16 \main_sdcore_crc16_inserter_crctmp3 - attribute \src "ls180.v:1872.12-1872.85" + attribute \src "ls180.v:1877.12-1877.85" wire width 16 \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 - attribute \src "ls180.v:1873.5-1873.81" + attribute \src "ls180.v:1878.5-1878.81" wire \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 - attribute \src "ls180.v:1490.6-1490.43" + attribute \src "ls180.v:1495.6-1495.43" wire \main_sdcore_crc16_inserter_sink_first - attribute \src "ls180.v:1491.6-1491.42" + attribute \src "ls180.v:1496.6-1496.42" wire \main_sdcore_crc16_inserter_sink_last - attribute \src "ls180.v:1492.12-1492.56" + attribute \src "ls180.v:1497.12-1497.56" wire width 8 \main_sdcore_crc16_inserter_sink_payload_data - attribute \src "ls180.v:1489.5-1489.42" + attribute \src "ls180.v:1494.5-1494.42" wire \main_sdcore_crc16_inserter_sink_ready - attribute \src "ls180.v:1488.6-1488.43" + attribute \src "ls180.v:1493.6-1493.43" wire \main_sdcore_crc16_inserter_sink_valid - attribute \src "ls180.v:1495.5-1495.44" + attribute \src "ls180.v:1500.5-1500.44" wire \main_sdcore_crc16_inserter_source_first - attribute \src "ls180.v:1496.5-1496.43" + attribute \src "ls180.v:1501.5-1501.43" wire \main_sdcore_crc16_inserter_source_last - attribute \src "ls180.v:1497.11-1497.57" + attribute \src "ls180.v:1502.11-1502.57" wire width 8 \main_sdcore_crc16_inserter_source_payload_data - attribute \src "ls180.v:1494.5-1494.44" + attribute \src "ls180.v:1499.5-1499.44" wire \main_sdcore_crc16_inserter_source_ready - attribute \src "ls180.v:1493.5-1493.44" + attribute \src "ls180.v:1498.5-1498.44" wire \main_sdcore_crc16_inserter_source_valid - attribute \src "ls180.v:1486.6-1486.35" + attribute \src "ls180.v:1491.6-1491.35" wire \main_sdcore_crc7_inserter_clr - attribute \src "ls180.v:1485.11-1485.40" + attribute \src "ls180.v:1490.11-1490.40" wire width 7 \main_sdcore_crc7_inserter_crc - attribute \src "ls180.v:1443.11-1443.44" + attribute \src "ls180.v:1448.11-1448.44" wire width 7 \main_sdcore_crc7_inserter_crcreg0 - attribute \src "ls180.v:1444.12-1444.45" + attribute \src "ls180.v:1449.12-1449.45" wire width 7 \main_sdcore_crc7_inserter_crcreg1 - attribute \src "ls180.v:1453.12-1453.46" + attribute \src "ls180.v:1458.12-1458.46" wire width 7 \main_sdcore_crc7_inserter_crcreg10 - attribute \src "ls180.v:1454.12-1454.46" + attribute \src "ls180.v:1459.12-1459.46" wire width 7 \main_sdcore_crc7_inserter_crcreg11 - attribute \src "ls180.v:1455.12-1455.46" + attribute \src "ls180.v:1460.12-1460.46" wire width 7 \main_sdcore_crc7_inserter_crcreg12 - attribute \src "ls180.v:1456.12-1456.46" + attribute \src "ls180.v:1461.12-1461.46" wire width 7 \main_sdcore_crc7_inserter_crcreg13 - attribute \src "ls180.v:1457.12-1457.46" + attribute \src "ls180.v:1462.12-1462.46" wire width 7 \main_sdcore_crc7_inserter_crcreg14 - attribute \src "ls180.v:1458.12-1458.46" + attribute \src "ls180.v:1463.12-1463.46" wire width 7 \main_sdcore_crc7_inserter_crcreg15 - attribute \src "ls180.v:1459.12-1459.46" + attribute \src "ls180.v:1464.12-1464.46" wire width 7 \main_sdcore_crc7_inserter_crcreg16 - attribute \src "ls180.v:1460.12-1460.46" + attribute \src "ls180.v:1465.12-1465.46" wire width 7 \main_sdcore_crc7_inserter_crcreg17 - attribute \src "ls180.v:1461.12-1461.46" + attribute \src "ls180.v:1466.12-1466.46" wire width 7 \main_sdcore_crc7_inserter_crcreg18 - attribute \src "ls180.v:1462.12-1462.46" + attribute \src "ls180.v:1467.12-1467.46" wire width 7 \main_sdcore_crc7_inserter_crcreg19 - attribute \src "ls180.v:1445.12-1445.45" + attribute \src "ls180.v:1450.12-1450.45" wire width 7 \main_sdcore_crc7_inserter_crcreg2 - attribute \src "ls180.v:1463.12-1463.46" + attribute \src "ls180.v:1468.12-1468.46" wire width 7 \main_sdcore_crc7_inserter_crcreg20 - attribute \src "ls180.v:1464.12-1464.46" + attribute \src "ls180.v:1469.12-1469.46" wire width 7 \main_sdcore_crc7_inserter_crcreg21 - attribute \src "ls180.v:1465.12-1465.46" + attribute \src "ls180.v:1470.12-1470.46" wire width 7 \main_sdcore_crc7_inserter_crcreg22 - attribute \src "ls180.v:1466.12-1466.46" + attribute \src "ls180.v:1471.12-1471.46" wire width 7 \main_sdcore_crc7_inserter_crcreg23 - attribute \src "ls180.v:1467.12-1467.46" + attribute \src "ls180.v:1472.12-1472.46" wire width 7 \main_sdcore_crc7_inserter_crcreg24 - attribute \src "ls180.v:1468.12-1468.46" + attribute \src "ls180.v:1473.12-1473.46" wire width 7 \main_sdcore_crc7_inserter_crcreg25 - attribute \src "ls180.v:1469.12-1469.46" + attribute \src "ls180.v:1474.12-1474.46" wire width 7 \main_sdcore_crc7_inserter_crcreg26 - attribute \src "ls180.v:1470.12-1470.46" + attribute \src "ls180.v:1475.12-1475.46" wire width 7 \main_sdcore_crc7_inserter_crcreg27 - attribute \src "ls180.v:1471.12-1471.46" + attribute \src "ls180.v:1476.12-1476.46" wire width 7 \main_sdcore_crc7_inserter_crcreg28 - attribute \src "ls180.v:1472.12-1472.46" + attribute \src "ls180.v:1477.12-1477.46" wire width 7 \main_sdcore_crc7_inserter_crcreg29 - attribute \src "ls180.v:1446.12-1446.45" + attribute \src "ls180.v:1451.12-1451.45" wire width 7 \main_sdcore_crc7_inserter_crcreg3 - attribute \src "ls180.v:1473.12-1473.46" + attribute \src "ls180.v:1478.12-1478.46" wire width 7 \main_sdcore_crc7_inserter_crcreg30 - attribute \src "ls180.v:1474.12-1474.46" + attribute \src "ls180.v:1479.12-1479.46" wire width 7 \main_sdcore_crc7_inserter_crcreg31 - attribute \src "ls180.v:1475.12-1475.46" + attribute \src "ls180.v:1480.12-1480.46" wire width 7 \main_sdcore_crc7_inserter_crcreg32 - attribute \src "ls180.v:1476.12-1476.46" + attribute \src "ls180.v:1481.12-1481.46" wire width 7 \main_sdcore_crc7_inserter_crcreg33 - attribute \src "ls180.v:1477.12-1477.46" + attribute \src "ls180.v:1482.12-1482.46" wire width 7 \main_sdcore_crc7_inserter_crcreg34 - attribute \src "ls180.v:1478.12-1478.46" + attribute \src "ls180.v:1483.12-1483.46" wire width 7 \main_sdcore_crc7_inserter_crcreg35 - attribute \src "ls180.v:1479.12-1479.46" + attribute \src "ls180.v:1484.12-1484.46" wire width 7 \main_sdcore_crc7_inserter_crcreg36 - attribute \src "ls180.v:1480.12-1480.46" + attribute \src "ls180.v:1485.12-1485.46" wire width 7 \main_sdcore_crc7_inserter_crcreg37 - attribute \src "ls180.v:1481.12-1481.46" + attribute \src "ls180.v:1486.12-1486.46" wire width 7 \main_sdcore_crc7_inserter_crcreg38 - attribute \src "ls180.v:1482.12-1482.46" + attribute \src "ls180.v:1487.12-1487.46" wire width 7 \main_sdcore_crc7_inserter_crcreg39 - attribute \src "ls180.v:1447.12-1447.45" + attribute \src "ls180.v:1452.12-1452.45" wire width 7 \main_sdcore_crc7_inserter_crcreg4 - attribute \src "ls180.v:1483.12-1483.46" + attribute \src "ls180.v:1488.12-1488.46" wire width 7 \main_sdcore_crc7_inserter_crcreg40 - attribute \src "ls180.v:1448.12-1448.45" + attribute \src "ls180.v:1453.12-1453.45" wire width 7 \main_sdcore_crc7_inserter_crcreg5 - attribute \src "ls180.v:1449.12-1449.45" + attribute \src "ls180.v:1454.12-1454.45" wire width 7 \main_sdcore_crc7_inserter_crcreg6 - attribute \src "ls180.v:1450.12-1450.45" + attribute \src "ls180.v:1455.12-1455.45" wire width 7 \main_sdcore_crc7_inserter_crcreg7 - attribute \src "ls180.v:1451.12-1451.45" + attribute \src "ls180.v:1456.12-1456.45" wire width 7 \main_sdcore_crc7_inserter_crcreg8 - attribute \src "ls180.v:1452.12-1452.45" + attribute \src "ls180.v:1457.12-1457.45" wire width 7 \main_sdcore_crc7_inserter_crcreg9 - attribute \src "ls180.v:1487.6-1487.38" + attribute \src "ls180.v:1492.6-1492.38" wire \main_sdcore_crc7_inserter_enable - attribute \src "ls180.v:1484.13-1484.42" + attribute \src "ls180.v:1489.13-1489.42" wire width 40 \main_sdcore_crc7_inserter_val - attribute \src "ls180.v:1586.12-1586.34" + attribute \src "ls180.v:1591.12-1591.34" wire width 32 \main_sdcore_data_count - attribute \src "ls180.v:1884.12-1884.57" + attribute \src "ls180.v:1889.12-1889.57" wire width 32 \main_sdcore_data_count_sdcore_fsm_next_value3 - attribute \src "ls180.v:1885.5-1885.53" + attribute \src "ls180.v:1890.5-1890.53" wire \main_sdcore_data_count_sdcore_fsm_next_value_ce3 - attribute \src "ls180.v:1587.5-1587.26" + attribute \src "ls180.v:1592.5-1592.26" wire \main_sdcore_data_done - attribute \src "ls180.v:1880.5-1880.49" + attribute \src "ls180.v:1885.5-1885.49" wire \main_sdcore_data_done_sdcore_fsm_next_value1 - attribute \src "ls180.v:1881.5-1881.52" + attribute \src "ls180.v:1886.5-1886.52" wire \main_sdcore_data_done_sdcore_fsm_next_value_ce1 - attribute \src "ls180.v:1588.5-1588.27" + attribute \src "ls180.v:1593.5-1593.27" wire \main_sdcore_data_error - attribute \src "ls180.v:1890.5-1890.50" + attribute \src "ls180.v:1895.5-1895.50" wire \main_sdcore_data_error_sdcore_fsm_next_value6 - attribute \src "ls180.v:1891.5-1891.53" + attribute \src "ls180.v:1896.5-1896.53" wire \main_sdcore_data_error_sdcore_fsm_next_value_ce6 - attribute \src "ls180.v:1437.12-1437.41" + attribute \src "ls180.v:1442.12-1442.41" wire width 4 \main_sdcore_data_event_status - attribute \src "ls180.v:1438.6-1438.31" + attribute \src "ls180.v:1443.6-1443.31" wire \main_sdcore_data_event_we - attribute \src "ls180.v:1589.5-1589.29" + attribute \src "ls180.v:1594.5-1594.29" wire \main_sdcore_data_timeout - attribute \src "ls180.v:1892.5-1892.52" + attribute \src "ls180.v:1897.5-1897.52" wire \main_sdcore_data_timeout_sdcore_fsm_next_value7 - attribute \src "ls180.v:1893.5-1893.55" + attribute \src "ls180.v:1898.5-1898.55" wire \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7 - attribute \src "ls180.v:1585.12-1585.33" + attribute \src "ls180.v:1590.12-1590.33" wire width 2 \main_sdcore_data_type - attribute \src "ls180.v:1417.6-1417.33" + attribute \src "ls180.v:1422.6-1422.33" wire \main_sdcore_sink_sink_first - attribute \src "ls180.v:1418.6-1418.32" + attribute \src "ls180.v:1423.6-1423.32" wire \main_sdcore_sink_sink_last - attribute \src "ls180.v:1419.12-1419.46" + attribute \src "ls180.v:1424.12-1424.46" wire width 8 \main_sdcore_sink_sink_payload_data - attribute \src "ls180.v:1416.6-1416.33" + attribute \src "ls180.v:1421.6-1421.33" wire \main_sdcore_sink_sink_ready - attribute \src "ls180.v:1415.6-1415.33" + attribute \src "ls180.v:1420.6-1420.33" wire \main_sdcore_sink_sink_valid - attribute \src "ls180.v:1422.6-1422.37" + attribute \src "ls180.v:1427.6-1427.37" wire \main_sdcore_source_source_first - attribute \src "ls180.v:1423.6-1423.36" + attribute \src "ls180.v:1428.6-1428.36" wire \main_sdcore_source_source_last - attribute \src "ls180.v:1424.12-1424.50" + attribute \src "ls180.v:1429.12-1429.50" wire width 8 \main_sdcore_source_source_payload_data - attribute \src "ls180.v:1421.6-1421.37" + attribute \src "ls180.v:1426.6-1426.37" wire \main_sdcore_source_source_ready - attribute \src "ls180.v:1420.6-1420.37" + attribute \src "ls180.v:1425.6-1425.37" wire \main_sdcore_source_source_valid - attribute \src "ls180.v:1735.6-1735.38" + attribute \src "ls180.v:1740.6-1740.38" wire \main_sdmem2block_converter_first - attribute \src "ls180.v:1736.6-1736.37" + attribute \src "ls180.v:1741.6-1741.37" wire \main_sdmem2block_converter_last - attribute \src "ls180.v:1734.11-1734.41" - wire width 2 \main_sdmem2block_converter_mux - attribute \src "ls180.v:1725.6-1725.43" + attribute \src "ls180.v:1739.11-1739.41" + wire width 3 \main_sdmem2block_converter_mux + attribute \src "ls180.v:1730.6-1730.43" wire \main_sdmem2block_converter_sink_first - attribute \src "ls180.v:1726.6-1726.42" + attribute \src "ls180.v:1731.6-1731.42" wire \main_sdmem2block_converter_sink_last - attribute \src "ls180.v:1727.13-1727.57" - wire width 32 \main_sdmem2block_converter_sink_payload_data - attribute \src "ls180.v:1724.6-1724.43" + attribute \src "ls180.v:1732.13-1732.57" + wire width 64 \main_sdmem2block_converter_sink_payload_data + attribute \src "ls180.v:1729.6-1729.43" wire \main_sdmem2block_converter_sink_ready - attribute \src "ls180.v:1723.6-1723.43" + attribute \src "ls180.v:1728.6-1728.43" wire \main_sdmem2block_converter_sink_valid - attribute \src "ls180.v:1730.6-1730.45" + attribute \src "ls180.v:1735.6-1735.45" wire \main_sdmem2block_converter_source_first - attribute \src "ls180.v:1731.6-1731.44" + attribute \src "ls180.v:1736.6-1736.44" wire \main_sdmem2block_converter_source_last - attribute \src "ls180.v:1732.11-1732.57" + attribute \src "ls180.v:1737.11-1737.57" wire width 8 \main_sdmem2block_converter_source_payload_data - attribute \src "ls180.v:1733.6-1733.65" + attribute \src "ls180.v:1738.6-1738.65" wire \main_sdmem2block_converter_source_payload_valid_token_count - attribute \src "ls180.v:1729.6-1729.45" + attribute \src "ls180.v:1734.6-1734.45" wire \main_sdmem2block_converter_source_ready - attribute \src "ls180.v:1728.6-1728.45" + attribute \src "ls180.v:1733.6-1733.45" wire \main_sdmem2block_converter_source_valid - attribute \src "ls180.v:1719.13-1719.38" + attribute \src "ls180.v:1724.13-1724.38" wire width 32 \main_sdmem2block_dma_base - attribute \src "ls180.v:1708.5-1708.33" + attribute \src "ls180.v:1713.5-1713.33" wire \main_sdmem2block_dma_base_re - attribute \src "ls180.v:1707.12-1707.45" + attribute \src "ls180.v:1712.12-1712.45" wire width 64 \main_sdmem2block_dma_base_storage - attribute \src "ls180.v:1706.12-1706.37" - wire width 32 \main_sdmem2block_dma_data - attribute \src "ls180.v:1902.12-1902.67" - wire width 32 \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value - attribute \src "ls180.v:1903.5-1903.63" + attribute \src "ls180.v:1711.12-1711.37" + wire width 64 \main_sdmem2block_dma_data + attribute \src "ls180.v:1907.12-1907.67" + wire width 64 \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value + attribute \src "ls180.v:1908.5-1908.63" wire \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce - attribute \src "ls180.v:1713.5-1713.37" + attribute \src "ls180.v:1718.5-1718.37" wire \main_sdmem2block_dma_done_status - attribute \src "ls180.v:1714.6-1714.34" + attribute \src "ls180.v:1719.6-1719.34" wire \main_sdmem2block_dma_done_we - attribute \src "ls180.v:1712.5-1712.35" + attribute \src "ls180.v:1717.5-1717.35" wire \main_sdmem2block_dma_enable_re - attribute \src "ls180.v:1711.5-1711.40" + attribute \src "ls180.v:1716.5-1716.40" wire \main_sdmem2block_dma_enable_storage - attribute \src "ls180.v:1721.13-1721.40" + attribute \src "ls180.v:1726.13-1726.40" wire width 32 \main_sdmem2block_dma_length - attribute \src "ls180.v:1710.5-1710.35" + attribute \src "ls180.v:1715.5-1715.35" wire \main_sdmem2block_dma_length_re - attribute \src "ls180.v:1709.12-1709.47" + attribute \src "ls180.v:1714.12-1714.47" wire width 32 \main_sdmem2block_dma_length_storage - attribute \src "ls180.v:1716.5-1716.33" + attribute \src "ls180.v:1721.5-1721.33" wire \main_sdmem2block_dma_loop_re - attribute \src "ls180.v:1715.5-1715.38" + attribute \src "ls180.v:1720.5-1720.38" wire \main_sdmem2block_dma_loop_storage - attribute \src "ls180.v:1720.12-1720.39" + attribute \src "ls180.v:1725.12-1725.39" wire width 32 \main_sdmem2block_dma_offset - attribute \src "ls180.v:1906.12-1906.79" + attribute \src "ls180.v:1911.12-1911.79" wire width 32 \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value - attribute \src "ls180.v:1907.5-1907.75" + attribute \src "ls180.v:1912.5-1912.75" wire \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce - attribute \src "ls180.v:1717.13-1717.47" + attribute \src "ls180.v:1722.13-1722.47" wire width 32 \main_sdmem2block_dma_offset_status - attribute \src "ls180.v:1718.6-1718.36" + attribute \src "ls180.v:1723.6-1723.36" wire \main_sdmem2block_dma_offset_we - attribute \src "ls180.v:1722.6-1722.32" + attribute \src "ls180.v:1727.6-1727.32" wire \main_sdmem2block_dma_reset - attribute \src "ls180.v:1699.5-1699.35" + attribute \src "ls180.v:1704.5-1704.35" wire \main_sdmem2block_dma_sink_last - attribute \src "ls180.v:1700.12-1700.53" + attribute \src "ls180.v:1705.12-1705.53" wire width 32 \main_sdmem2block_dma_sink_payload_address - attribute \src "ls180.v:1698.5-1698.36" + attribute \src "ls180.v:1703.5-1703.36" wire \main_sdmem2block_dma_sink_ready - attribute \src "ls180.v:1697.5-1697.36" + attribute \src "ls180.v:1702.5-1702.36" wire \main_sdmem2block_dma_sink_valid - attribute \src "ls180.v:1703.5-1703.38" + attribute \src "ls180.v:1708.5-1708.38" wire \main_sdmem2block_dma_source_first - attribute \src "ls180.v:1704.5-1704.37" + attribute \src "ls180.v:1709.5-1709.37" wire \main_sdmem2block_dma_source_last - attribute \src "ls180.v:1705.12-1705.52" - wire width 32 \main_sdmem2block_dma_source_payload_data - attribute \src "ls180.v:1702.6-1702.39" + attribute \src "ls180.v:1710.12-1710.52" + wire width 64 \main_sdmem2block_dma_source_payload_data + attribute \src "ls180.v:1707.6-1707.39" wire \main_sdmem2block_dma_source_ready - attribute \src "ls180.v:1701.5-1701.38" + attribute \src "ls180.v:1706.5-1706.38" wire \main_sdmem2block_dma_source_valid - attribute \src "ls180.v:1761.11-1761.40" + attribute \src "ls180.v:1766.11-1766.40" wire width 5 \main_sdmem2block_fifo_consume - attribute \src "ls180.v:1766.6-1766.35" + attribute \src "ls180.v:1771.6-1771.35" wire \main_sdmem2block_fifo_do_read - attribute \src "ls180.v:1770.6-1770.41" + attribute \src "ls180.v:1775.6-1775.41" wire \main_sdmem2block_fifo_fifo_in_first - attribute \src "ls180.v:1771.6-1771.40" + attribute \src "ls180.v:1776.6-1776.40" wire \main_sdmem2block_fifo_fifo_in_last - attribute \src "ls180.v:1769.12-1769.54" + attribute \src "ls180.v:1774.12-1774.54" wire width 8 \main_sdmem2block_fifo_fifo_in_payload_data - attribute \src "ls180.v:1773.6-1773.42" + attribute \src "ls180.v:1778.6-1778.42" wire \main_sdmem2block_fifo_fifo_out_first - attribute \src "ls180.v:1774.6-1774.41" + attribute \src "ls180.v:1779.6-1779.41" wire \main_sdmem2block_fifo_fifo_out_last - attribute \src "ls180.v:1772.12-1772.55" + attribute \src "ls180.v:1777.12-1777.55" wire width 8 \main_sdmem2block_fifo_fifo_out_payload_data - attribute \src "ls180.v:1758.11-1758.38" + attribute \src "ls180.v:1763.11-1763.38" wire width 6 \main_sdmem2block_fifo_level - attribute \src "ls180.v:1760.11-1760.40" + attribute \src "ls180.v:1765.11-1765.40" wire width 5 \main_sdmem2block_fifo_produce - attribute \src "ls180.v:1767.12-1767.44" + attribute \src "ls180.v:1772.12-1772.44" wire width 5 \main_sdmem2block_fifo_rdport_adr - attribute \src "ls180.v:1768.12-1768.46" + attribute \src "ls180.v:1773.12-1773.46" wire width 10 \main_sdmem2block_fifo_rdport_dat_r - attribute \src "ls180.v:1759.5-1759.34" + attribute \src "ls180.v:1764.5-1764.34" wire \main_sdmem2block_fifo_replace - attribute \src "ls180.v:1744.6-1744.38" + attribute \src "ls180.v:1749.6-1749.38" wire \main_sdmem2block_fifo_sink_first - attribute \src "ls180.v:1745.6-1745.37" + attribute \src "ls180.v:1750.6-1750.37" wire \main_sdmem2block_fifo_sink_last - attribute \src "ls180.v:1746.12-1746.51" + attribute \src "ls180.v:1751.12-1751.51" wire width 8 \main_sdmem2block_fifo_sink_payload_data - attribute \src "ls180.v:1743.6-1743.38" + attribute \src "ls180.v:1748.6-1748.38" wire \main_sdmem2block_fifo_sink_ready - attribute \src "ls180.v:1742.6-1742.38" + attribute \src "ls180.v:1747.6-1747.38" wire \main_sdmem2block_fifo_sink_valid - attribute \src "ls180.v:1749.6-1749.40" + attribute \src "ls180.v:1754.6-1754.40" wire \main_sdmem2block_fifo_source_first - attribute \src "ls180.v:1750.6-1750.39" + attribute \src "ls180.v:1755.6-1755.39" wire \main_sdmem2block_fifo_source_last - attribute \src "ls180.v:1751.12-1751.53" + attribute \src "ls180.v:1756.12-1756.53" wire width 8 \main_sdmem2block_fifo_source_payload_data - attribute \src "ls180.v:1748.6-1748.40" + attribute \src "ls180.v:1753.6-1753.40" wire \main_sdmem2block_fifo_source_ready - attribute \src "ls180.v:1747.6-1747.40" + attribute \src "ls180.v:1752.6-1752.40" wire \main_sdmem2block_fifo_source_valid - attribute \src "ls180.v:1756.12-1756.46" + attribute \src "ls180.v:1761.12-1761.46" wire width 10 \main_sdmem2block_fifo_syncfifo_din - attribute \src "ls180.v:1757.12-1757.47" + attribute \src "ls180.v:1762.12-1762.47" wire width 10 \main_sdmem2block_fifo_syncfifo_dout - attribute \src "ls180.v:1754.6-1754.39" + attribute \src "ls180.v:1759.6-1759.39" wire \main_sdmem2block_fifo_syncfifo_re - attribute \src "ls180.v:1755.6-1755.45" + attribute \src "ls180.v:1760.6-1760.45" wire \main_sdmem2block_fifo_syncfifo_readable - attribute \src "ls180.v:1752.6-1752.39" + attribute \src "ls180.v:1757.6-1757.39" wire \main_sdmem2block_fifo_syncfifo_we - attribute \src "ls180.v:1753.6-1753.45" + attribute \src "ls180.v:1758.6-1758.45" wire \main_sdmem2block_fifo_syncfifo_writable - attribute \src "ls180.v:1762.11-1762.43" + attribute \src "ls180.v:1767.11-1767.43" wire width 5 \main_sdmem2block_fifo_wrport_adr - attribute \src "ls180.v:1763.12-1763.46" + attribute \src "ls180.v:1768.12-1768.46" wire width 10 \main_sdmem2block_fifo_wrport_dat_r - attribute \src "ls180.v:1765.12-1765.46" + attribute \src "ls180.v:1770.12-1770.46" wire width 10 \main_sdmem2block_fifo_wrport_dat_w - attribute \src "ls180.v:1764.6-1764.37" + attribute \src "ls180.v:1769.6-1769.37" wire \main_sdmem2block_fifo_wrport_we - attribute \src "ls180.v:1694.6-1694.43" + attribute \src "ls180.v:1699.6-1699.43" wire \main_sdmem2block_source_source_first0 - attribute \src "ls180.v:1739.6-1739.43" + attribute \src "ls180.v:1744.6-1744.43" wire \main_sdmem2block_source_source_first1 - attribute \src "ls180.v:1695.6-1695.42" + attribute \src "ls180.v:1700.6-1700.42" wire \main_sdmem2block_source_source_last0 - attribute \src "ls180.v:1740.6-1740.42" + attribute \src "ls180.v:1745.6-1745.42" wire \main_sdmem2block_source_source_last1 - attribute \src "ls180.v:1696.12-1696.56" + attribute \src "ls180.v:1701.12-1701.56" wire width 8 \main_sdmem2block_source_source_payload_data0 - attribute \src "ls180.v:1741.12-1741.56" + attribute \src "ls180.v:1746.12-1746.56" wire width 8 \main_sdmem2block_source_source_payload_data1 - attribute \src "ls180.v:1693.6-1693.43" + attribute \src "ls180.v:1698.6-1698.43" wire \main_sdmem2block_source_source_ready0 - attribute \src "ls180.v:1738.6-1738.43" + attribute \src "ls180.v:1743.6-1743.43" wire \main_sdmem2block_source_source_ready1 - attribute \src "ls180.v:1692.6-1692.43" + attribute \src "ls180.v:1697.6-1697.43" wire \main_sdmem2block_source_source_valid0 - attribute \src "ls180.v:1737.6-1737.43" + attribute \src "ls180.v:1742.6-1742.43" wire \main_sdmem2block_source_source_valid1 - attribute \src "ls180.v:1143.6-1143.27" + attribute \src "ls180.v:1148.6-1148.27" wire \main_sdphy_clocker_ce - attribute \src "ls180.v:1142.5-1142.28" + attribute \src "ls180.v:1147.5-1147.28" wire \main_sdphy_clocker_clk0 - attribute \src "ls180.v:1145.5-1145.28" + attribute \src "ls180.v:1150.5-1150.28" wire \main_sdphy_clocker_clk1 - attribute \src "ls180.v:1146.5-1146.29" + attribute \src "ls180.v:1151.5-1151.29" wire \main_sdphy_clocker_clk_d - attribute \src "ls180.v:1144.11-1144.34" + attribute \src "ls180.v:1149.11-1149.34" wire width 9 \main_sdphy_clocker_clks - attribute \src "ls180.v:1140.5-1140.26" + attribute \src "ls180.v:1145.5-1145.26" wire \main_sdphy_clocker_re - attribute \src "ls180.v:1141.6-1141.29" + attribute \src "ls180.v:1146.6-1146.29" wire \main_sdphy_clocker_stop - attribute \src "ls180.v:1139.11-1139.37" + attribute \src "ls180.v:1144.11-1144.37" wire width 9 \main_sdphy_clocker_storage - attribute \src "ls180.v:1243.6-1243.41" + attribute \src "ls180.v:1248.6-1248.41" wire \main_sdphy_cmdr_cmdr_buf_sink_first - attribute \src "ls180.v:1244.6-1244.40" + attribute \src "ls180.v:1249.6-1249.40" wire \main_sdphy_cmdr_cmdr_buf_sink_last - attribute \src "ls180.v:1245.12-1245.54" + attribute \src "ls180.v:1250.12-1250.54" wire width 8 \main_sdphy_cmdr_cmdr_buf_sink_payload_data - attribute \src "ls180.v:1242.6-1242.41" + attribute \src "ls180.v:1247.6-1247.41" wire \main_sdphy_cmdr_cmdr_buf_sink_ready - attribute \src "ls180.v:1241.6-1241.41" + attribute \src "ls180.v:1246.6-1246.41" wire \main_sdphy_cmdr_cmdr_buf_sink_valid - attribute \src "ls180.v:1248.5-1248.42" + attribute \src "ls180.v:1253.5-1253.42" wire \main_sdphy_cmdr_cmdr_buf_source_first - attribute \src "ls180.v:1249.5-1249.41" + attribute \src "ls180.v:1254.5-1254.41" wire \main_sdphy_cmdr_cmdr_buf_source_last - attribute \src "ls180.v:1250.11-1250.55" + attribute \src "ls180.v:1255.11-1255.55" wire width 8 \main_sdphy_cmdr_cmdr_buf_source_payload_data - attribute \src "ls180.v:1247.6-1247.43" + attribute \src "ls180.v:1252.6-1252.43" wire \main_sdphy_cmdr_cmdr_buf_source_ready - attribute \src "ls180.v:1246.5-1246.42" + attribute \src "ls180.v:1251.5-1251.42" wire \main_sdphy_cmdr_cmdr_buf_source_valid - attribute \src "ls180.v:1233.11-1233.47" + attribute \src "ls180.v:1238.11-1238.47" wire width 3 \main_sdphy_cmdr_cmdr_converter_demux - attribute \src "ls180.v:1234.6-1234.46" + attribute \src "ls180.v:1239.6-1239.46" wire \main_sdphy_cmdr_cmdr_converter_load_part - attribute \src "ls180.v:1224.5-1224.46" + attribute \src "ls180.v:1229.5-1229.46" wire \main_sdphy_cmdr_cmdr_converter_sink_first - attribute \src "ls180.v:1225.5-1225.45" + attribute \src "ls180.v:1230.5-1230.45" wire \main_sdphy_cmdr_cmdr_converter_sink_last - attribute \src "ls180.v:1226.6-1226.54" + attribute \src "ls180.v:1231.6-1231.54" wire \main_sdphy_cmdr_cmdr_converter_sink_payload_data - attribute \src "ls180.v:1223.6-1223.47" + attribute \src "ls180.v:1228.6-1228.47" wire \main_sdphy_cmdr_cmdr_converter_sink_ready - attribute \src "ls180.v:1222.6-1222.47" + attribute \src "ls180.v:1227.6-1227.47" wire \main_sdphy_cmdr_cmdr_converter_sink_valid - attribute \src "ls180.v:1229.5-1229.48" + attribute \src "ls180.v:1234.5-1234.48" wire \main_sdphy_cmdr_cmdr_converter_source_first - attribute \src "ls180.v:1230.5-1230.47" + attribute \src "ls180.v:1235.5-1235.47" wire \main_sdphy_cmdr_cmdr_converter_source_last - attribute \src "ls180.v:1231.11-1231.61" + attribute \src "ls180.v:1236.11-1236.61" wire width 8 \main_sdphy_cmdr_cmdr_converter_source_payload_data - attribute \src "ls180.v:1232.11-1232.74" + attribute \src "ls180.v:1237.11-1237.74" wire width 4 \main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count - attribute \src "ls180.v:1228.6-1228.49" + attribute \src "ls180.v:1233.6-1233.49" wire \main_sdphy_cmdr_cmdr_converter_source_ready - attribute \src "ls180.v:1227.6-1227.49" + attribute \src "ls180.v:1232.6-1232.49" wire \main_sdphy_cmdr_cmdr_converter_source_valid - attribute \src "ls180.v:1235.5-1235.46" + attribute \src "ls180.v:1240.5-1240.46" wire \main_sdphy_cmdr_cmdr_converter_strobe_all - attribute \src "ls180.v:1206.6-1206.40" + attribute \src "ls180.v:1211.6-1211.40" wire \main_sdphy_cmdr_cmdr_pads_in_first - attribute \src "ls180.v:1207.6-1207.39" + attribute \src "ls180.v:1212.6-1212.39" wire \main_sdphy_cmdr_cmdr_pads_in_last - attribute \src "ls180.v:1208.6-1208.46" + attribute \src "ls180.v:1213.6-1213.46" wire \main_sdphy_cmdr_cmdr_pads_in_payload_clk - attribute \src "ls180.v:1209.6-1209.48" + attribute \src "ls180.v:1214.6-1214.48" wire \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_i - attribute \src "ls180.v:1210.6-1210.48" + attribute \src "ls180.v:1215.6-1215.48" wire \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_o - attribute \src "ls180.v:1211.6-1211.49" + attribute \src "ls180.v:1216.6-1216.49" wire \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_oe - attribute \src "ls180.v:1212.12-1212.55" + attribute \src "ls180.v:1217.12-1217.55" wire width 4 \main_sdphy_cmdr_cmdr_pads_in_payload_data_i - attribute \src "ls180.v:1213.12-1213.55" + attribute \src "ls180.v:1218.12-1218.55" wire width 4 \main_sdphy_cmdr_cmdr_pads_in_payload_data_o - attribute \src "ls180.v:1214.6-1214.50" + attribute \src "ls180.v:1219.6-1219.50" wire \main_sdphy_cmdr_cmdr_pads_in_payload_data_oe - attribute \src "ls180.v:1205.5-1205.39" + attribute \src "ls180.v:1210.5-1210.39" wire \main_sdphy_cmdr_cmdr_pads_in_ready - attribute \src "ls180.v:1204.6-1204.40" + attribute \src "ls180.v:1209.6-1209.40" wire \main_sdphy_cmdr_cmdr_pads_in_valid - attribute \src "ls180.v:1251.5-1251.31" + attribute \src "ls180.v:1256.5-1256.31" wire \main_sdphy_cmdr_cmdr_reset - attribute \src "ls180.v:1846.5-1846.59" + attribute \src "ls180.v:1851.5-1851.59" wire \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 - attribute \src "ls180.v:1847.5-1847.62" + attribute \src "ls180.v:1852.5-1852.62" wire \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 - attribute \src "ls180.v:1221.5-1221.29" + attribute \src "ls180.v:1226.5-1226.29" wire \main_sdphy_cmdr_cmdr_run - attribute \src "ls180.v:1217.6-1217.47" + attribute \src "ls180.v:1222.6-1222.47" wire \main_sdphy_cmdr_cmdr_source_source_first0 - attribute \src "ls180.v:1238.6-1238.47" + attribute \src "ls180.v:1243.6-1243.47" wire \main_sdphy_cmdr_cmdr_source_source_first1 - attribute \src "ls180.v:1218.6-1218.46" + attribute \src "ls180.v:1223.6-1223.46" wire \main_sdphy_cmdr_cmdr_source_source_last0 - attribute \src "ls180.v:1239.6-1239.46" + attribute \src "ls180.v:1244.6-1244.46" wire \main_sdphy_cmdr_cmdr_source_source_last1 - attribute \src "ls180.v:1219.12-1219.60" + attribute \src "ls180.v:1224.12-1224.60" wire width 8 \main_sdphy_cmdr_cmdr_source_source_payload_data0 - attribute \src "ls180.v:1240.12-1240.60" + attribute \src "ls180.v:1245.12-1245.60" wire width 8 \main_sdphy_cmdr_cmdr_source_source_payload_data1 - attribute \src "ls180.v:1216.5-1216.46" + attribute \src "ls180.v:1221.5-1221.46" wire \main_sdphy_cmdr_cmdr_source_source_ready0 - attribute \src "ls180.v:1237.6-1237.47" + attribute \src "ls180.v:1242.6-1242.47" wire \main_sdphy_cmdr_cmdr_source_source_ready1 - attribute \src "ls180.v:1215.6-1215.47" + attribute \src "ls180.v:1220.6-1220.47" wire \main_sdphy_cmdr_cmdr_source_source_valid0 - attribute \src "ls180.v:1236.6-1236.47" + attribute \src "ls180.v:1241.6-1241.47" wire \main_sdphy_cmdr_cmdr_source_source_valid1 - attribute \src "ls180.v:1220.6-1220.32" + attribute \src "ls180.v:1225.6-1225.32" wire \main_sdphy_cmdr_cmdr_start - attribute \src "ls180.v:1203.11-1203.32" + attribute \src "ls180.v:1208.11-1208.32" wire width 8 \main_sdphy_cmdr_count - attribute \src "ls180.v:1842.11-1842.60" + attribute \src "ls180.v:1847.11-1847.60" wire width 8 \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0 - attribute \src "ls180.v:1843.5-1843.57" + attribute \src "ls180.v:1848.5-1848.57" wire \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0 - attribute \src "ls180.v:1178.5-1178.42" + attribute \src "ls180.v:1183.5-1183.42" wire \main_sdphy_cmdr_pads_in_pads_in_first - attribute \src "ls180.v:1179.5-1179.41" + attribute \src "ls180.v:1184.5-1184.41" wire \main_sdphy_cmdr_pads_in_pads_in_last - attribute \src "ls180.v:1180.5-1180.48" + attribute \src "ls180.v:1185.5-1185.48" wire \main_sdphy_cmdr_pads_in_pads_in_payload_clk - attribute \src "ls180.v:1181.6-1181.51" + attribute \src "ls180.v:1186.6-1186.51" wire \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_i - attribute \src "ls180.v:1182.5-1182.50" + attribute \src "ls180.v:1187.5-1187.50" wire \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o - attribute \src "ls180.v:1183.5-1183.51" + attribute \src "ls180.v:1188.5-1188.51" wire \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe - attribute \src "ls180.v:1184.12-1184.58" + attribute \src "ls180.v:1189.12-1189.58" wire width 4 \main_sdphy_cmdr_pads_in_pads_in_payload_data_i - attribute \src "ls180.v:1185.11-1185.57" + attribute \src "ls180.v:1190.11-1190.57" wire width 4 \main_sdphy_cmdr_pads_in_pads_in_payload_data_o - attribute \src "ls180.v:1186.5-1186.52" + attribute \src "ls180.v:1191.5-1191.52" wire \main_sdphy_cmdr_pads_in_pads_in_payload_data_oe - attribute \src "ls180.v:1177.6-1177.43" + attribute \src "ls180.v:1182.6-1182.43" wire \main_sdphy_cmdr_pads_in_pads_in_ready - attribute \src "ls180.v:1176.6-1176.43" + attribute \src "ls180.v:1181.6-1181.43" wire \main_sdphy_cmdr_pads_in_pads_in_valid - attribute \src "ls180.v:1188.5-1188.41" + attribute \src "ls180.v:1193.5-1193.41" wire \main_sdphy_cmdr_pads_out_payload_clk - attribute \src "ls180.v:1189.5-1189.43" + attribute \src "ls180.v:1194.5-1194.43" wire \main_sdphy_cmdr_pads_out_payload_cmd_o - attribute \src "ls180.v:1190.5-1190.44" + attribute \src "ls180.v:1195.5-1195.44" wire \main_sdphy_cmdr_pads_out_payload_cmd_oe - attribute \src "ls180.v:1191.11-1191.50" + attribute \src "ls180.v:1196.11-1196.50" wire width 4 \main_sdphy_cmdr_pads_out_payload_data_o - attribute \src "ls180.v:1192.5-1192.45" + attribute \src "ls180.v:1197.5-1197.45" wire \main_sdphy_cmdr_pads_out_payload_data_oe - attribute \src "ls180.v:1187.6-1187.36" + attribute \src "ls180.v:1192.6-1192.36" wire \main_sdphy_cmdr_pads_out_ready - attribute \src "ls180.v:1195.5-1195.30" + attribute \src "ls180.v:1200.5-1200.30" wire \main_sdphy_cmdr_sink_last - attribute \src "ls180.v:1196.11-1196.46" + attribute \src "ls180.v:1201.11-1201.46" wire width 8 \main_sdphy_cmdr_sink_payload_length - attribute \src "ls180.v:1194.5-1194.31" + attribute \src "ls180.v:1199.5-1199.31" wire \main_sdphy_cmdr_sink_ready - attribute \src "ls180.v:1193.5-1193.31" + attribute \src "ls180.v:1198.5-1198.31" wire \main_sdphy_cmdr_sink_valid - attribute \src "ls180.v:1199.5-1199.32" + attribute \src "ls180.v:1204.5-1204.32" wire \main_sdphy_cmdr_source_last - attribute \src "ls180.v:1200.11-1200.46" + attribute \src "ls180.v:1205.11-1205.46" wire width 8 \main_sdphy_cmdr_source_payload_data - attribute \src "ls180.v:1201.11-1201.48" + attribute \src "ls180.v:1206.11-1206.48" wire width 3 \main_sdphy_cmdr_source_payload_status - attribute \src "ls180.v:1198.5-1198.33" + attribute \src "ls180.v:1203.5-1203.33" wire \main_sdphy_cmdr_source_ready - attribute \src "ls180.v:1197.5-1197.33" + attribute \src "ls180.v:1202.5-1202.33" wire \main_sdphy_cmdr_source_valid - attribute \src "ls180.v:1202.12-1202.35" + attribute \src "ls180.v:1207.12-1207.35" wire width 32 \main_sdphy_cmdr_timeout - attribute \src "ls180.v:1844.12-1844.63" + attribute \src "ls180.v:1849.12-1849.63" wire width 32 \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1 - attribute \src "ls180.v:1845.5-1845.59" + attribute \src "ls180.v:1850.5-1850.59" wire \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 - attribute \src "ls180.v:1175.11-1175.32" + attribute \src "ls180.v:1180.11-1180.32" wire width 8 \main_sdphy_cmdw_count - attribute \src "ls180.v:1838.11-1838.59" + attribute \src "ls180.v:1843.11-1843.59" wire width 8 \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value - attribute \src "ls180.v:1839.5-1839.56" + attribute \src "ls180.v:1844.5-1844.56" wire \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce - attribute \src "ls180.v:1174.5-1174.25" + attribute \src "ls180.v:1179.5-1179.25" wire \main_sdphy_cmdw_done - attribute \src "ls180.v:1162.6-1162.43" + attribute \src "ls180.v:1167.6-1167.43" wire \main_sdphy_cmdw_pads_in_payload_cmd_i - attribute \src "ls180.v:1163.12-1163.50" + attribute \src "ls180.v:1168.12-1168.50" wire width 4 \main_sdphy_cmdw_pads_in_payload_data_i - attribute \src "ls180.v:1161.6-1161.35" + attribute \src "ls180.v:1166.6-1166.35" wire \main_sdphy_cmdw_pads_in_valid - attribute \src "ls180.v:1165.5-1165.41" + attribute \src "ls180.v:1170.5-1170.41" wire \main_sdphy_cmdw_pads_out_payload_clk - attribute \src "ls180.v:1166.5-1166.43" + attribute \src "ls180.v:1171.5-1171.43" wire \main_sdphy_cmdw_pads_out_payload_cmd_o - attribute \src "ls180.v:1167.5-1167.44" + attribute \src "ls180.v:1172.5-1172.44" wire \main_sdphy_cmdw_pads_out_payload_cmd_oe - attribute \src "ls180.v:1168.11-1168.50" + attribute \src "ls180.v:1173.11-1173.50" wire width 4 \main_sdphy_cmdw_pads_out_payload_data_o - attribute \src "ls180.v:1169.5-1169.45" + attribute \src "ls180.v:1174.5-1174.45" wire \main_sdphy_cmdw_pads_out_payload_data_oe - attribute \src "ls180.v:1164.6-1164.36" + attribute \src "ls180.v:1169.6-1169.36" wire \main_sdphy_cmdw_pads_out_ready - attribute \src "ls180.v:1172.5-1172.30" + attribute \src "ls180.v:1177.5-1177.30" wire \main_sdphy_cmdw_sink_last - attribute \src "ls180.v:1173.11-1173.44" + attribute \src "ls180.v:1178.11-1178.44" wire width 8 \main_sdphy_cmdw_sink_payload_data - attribute \src "ls180.v:1171.5-1171.31" + attribute \src "ls180.v:1176.5-1176.31" wire \main_sdphy_cmdw_sink_ready - attribute \src "ls180.v:1170.5-1170.31" + attribute \src "ls180.v:1175.5-1175.31" wire \main_sdphy_cmdw_sink_valid - attribute \src "ls180.v:1359.11-1359.33" + attribute \src "ls180.v:1364.11-1364.33" wire width 10 \main_sdphy_datar_count - attribute \src "ls180.v:1858.11-1858.62" + attribute \src "ls180.v:1863.11-1863.62" wire width 10 \main_sdphy_datar_count_sdphy_sdphydatar_next_value0 - attribute \src "ls180.v:1859.5-1859.59" + attribute \src "ls180.v:1864.5-1864.59" wire \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0 - attribute \src "ls180.v:1399.6-1399.43" + attribute \src "ls180.v:1404.6-1404.43" wire \main_sdphy_datar_datar_buf_sink_first - attribute \src "ls180.v:1400.6-1400.42" + attribute \src "ls180.v:1405.6-1405.42" wire \main_sdphy_datar_datar_buf_sink_last - attribute \src "ls180.v:1401.12-1401.56" + attribute \src "ls180.v:1406.12-1406.56" wire width 8 \main_sdphy_datar_datar_buf_sink_payload_data - attribute \src "ls180.v:1398.6-1398.43" + attribute \src "ls180.v:1403.6-1403.43" wire \main_sdphy_datar_datar_buf_sink_ready - attribute \src "ls180.v:1397.6-1397.43" + attribute \src "ls180.v:1402.6-1402.43" wire \main_sdphy_datar_datar_buf_sink_valid - attribute \src "ls180.v:1404.5-1404.44" + attribute \src "ls180.v:1409.5-1409.44" wire \main_sdphy_datar_datar_buf_source_first - attribute \src "ls180.v:1405.5-1405.43" + attribute \src "ls180.v:1410.5-1410.43" wire \main_sdphy_datar_datar_buf_source_last - attribute \src "ls180.v:1406.11-1406.57" + attribute \src "ls180.v:1411.11-1411.57" wire width 8 \main_sdphy_datar_datar_buf_source_payload_data - attribute \src "ls180.v:1403.6-1403.45" + attribute \src "ls180.v:1408.6-1408.45" wire \main_sdphy_datar_datar_buf_source_ready - attribute \src "ls180.v:1402.5-1402.44" + attribute \src "ls180.v:1407.5-1407.44" wire \main_sdphy_datar_datar_buf_source_valid - attribute \src "ls180.v:1389.5-1389.43" + attribute \src "ls180.v:1394.5-1394.43" wire \main_sdphy_datar_datar_converter_demux - attribute \src "ls180.v:1390.6-1390.48" + attribute \src "ls180.v:1395.6-1395.48" wire \main_sdphy_datar_datar_converter_load_part - attribute \src "ls180.v:1380.5-1380.48" + attribute \src "ls180.v:1385.5-1385.48" wire \main_sdphy_datar_datar_converter_sink_first - attribute \src "ls180.v:1381.5-1381.47" + attribute \src "ls180.v:1386.5-1386.47" wire \main_sdphy_datar_datar_converter_sink_last - attribute \src "ls180.v:1382.12-1382.62" + attribute \src "ls180.v:1387.12-1387.62" wire width 4 \main_sdphy_datar_datar_converter_sink_payload_data - attribute \src "ls180.v:1379.6-1379.49" + attribute \src "ls180.v:1384.6-1384.49" wire \main_sdphy_datar_datar_converter_sink_ready - attribute \src "ls180.v:1378.6-1378.49" + attribute \src "ls180.v:1383.6-1383.49" wire \main_sdphy_datar_datar_converter_sink_valid - attribute \src "ls180.v:1385.5-1385.50" + attribute \src "ls180.v:1390.5-1390.50" wire \main_sdphy_datar_datar_converter_source_first - attribute \src "ls180.v:1386.5-1386.49" + attribute \src "ls180.v:1391.5-1391.49" wire \main_sdphy_datar_datar_converter_source_last - attribute \src "ls180.v:1387.11-1387.63" + attribute \src "ls180.v:1392.11-1392.63" wire width 8 \main_sdphy_datar_datar_converter_source_payload_data - attribute \src "ls180.v:1388.11-1388.76" + attribute \src "ls180.v:1393.11-1393.76" wire width 2 \main_sdphy_datar_datar_converter_source_payload_valid_token_count - attribute \src "ls180.v:1384.6-1384.51" + attribute \src "ls180.v:1389.6-1389.51" wire \main_sdphy_datar_datar_converter_source_ready - attribute \src "ls180.v:1383.6-1383.51" + attribute \src "ls180.v:1388.6-1388.51" wire \main_sdphy_datar_datar_converter_source_valid - attribute \src "ls180.v:1391.5-1391.48" + attribute \src "ls180.v:1396.5-1396.48" wire \main_sdphy_datar_datar_converter_strobe_all - attribute \src "ls180.v:1362.6-1362.42" + attribute \src "ls180.v:1367.6-1367.42" wire \main_sdphy_datar_datar_pads_in_first - attribute \src "ls180.v:1363.6-1363.41" + attribute \src "ls180.v:1368.6-1368.41" wire \main_sdphy_datar_datar_pads_in_last - attribute \src "ls180.v:1364.6-1364.48" + attribute \src "ls180.v:1369.6-1369.48" wire \main_sdphy_datar_datar_pads_in_payload_clk - attribute \src "ls180.v:1365.6-1365.50" + attribute \src "ls180.v:1370.6-1370.50" wire \main_sdphy_datar_datar_pads_in_payload_cmd_i - attribute \src "ls180.v:1366.6-1366.50" + attribute \src "ls180.v:1371.6-1371.50" wire \main_sdphy_datar_datar_pads_in_payload_cmd_o - attribute \src "ls180.v:1367.6-1367.51" + attribute \src "ls180.v:1372.6-1372.51" wire \main_sdphy_datar_datar_pads_in_payload_cmd_oe - attribute \src "ls180.v:1368.12-1368.57" + attribute \src "ls180.v:1373.12-1373.57" wire width 4 \main_sdphy_datar_datar_pads_in_payload_data_i - attribute \src "ls180.v:1369.12-1369.57" + attribute \src "ls180.v:1374.12-1374.57" wire width 4 \main_sdphy_datar_datar_pads_in_payload_data_o - attribute \src "ls180.v:1370.6-1370.52" + attribute \src "ls180.v:1375.6-1375.52" wire \main_sdphy_datar_datar_pads_in_payload_data_oe - attribute \src "ls180.v:1361.5-1361.41" + attribute \src "ls180.v:1366.5-1366.41" wire \main_sdphy_datar_datar_pads_in_ready - attribute \src "ls180.v:1360.6-1360.42" + attribute \src "ls180.v:1365.6-1365.42" wire \main_sdphy_datar_datar_pads_in_valid - attribute \src "ls180.v:1407.5-1407.33" + attribute \src "ls180.v:1412.5-1412.33" wire \main_sdphy_datar_datar_reset - attribute \src "ls180.v:1862.5-1862.62" + attribute \src "ls180.v:1867.5-1867.62" wire \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 - attribute \src "ls180.v:1863.5-1863.65" + attribute \src "ls180.v:1868.5-1868.65" wire \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 - attribute \src "ls180.v:1377.5-1377.31" + attribute \src "ls180.v:1382.5-1382.31" wire \main_sdphy_datar_datar_run - attribute \src "ls180.v:1373.6-1373.49" + attribute \src "ls180.v:1378.6-1378.49" wire \main_sdphy_datar_datar_source_source_first0 - attribute \src "ls180.v:1394.6-1394.49" + attribute \src "ls180.v:1399.6-1399.49" wire \main_sdphy_datar_datar_source_source_first1 - attribute \src "ls180.v:1374.6-1374.48" + attribute \src "ls180.v:1379.6-1379.48" wire \main_sdphy_datar_datar_source_source_last0 - attribute \src "ls180.v:1395.6-1395.48" + attribute \src "ls180.v:1400.6-1400.48" wire \main_sdphy_datar_datar_source_source_last1 - attribute \src "ls180.v:1375.12-1375.62" + attribute \src "ls180.v:1380.12-1380.62" wire width 8 \main_sdphy_datar_datar_source_source_payload_data0 - attribute \src "ls180.v:1396.12-1396.62" + attribute \src "ls180.v:1401.12-1401.62" wire width 8 \main_sdphy_datar_datar_source_source_payload_data1 - attribute \src "ls180.v:1372.5-1372.48" + attribute \src "ls180.v:1377.5-1377.48" wire \main_sdphy_datar_datar_source_source_ready0 - attribute \src "ls180.v:1393.6-1393.49" + attribute \src "ls180.v:1398.6-1398.49" wire \main_sdphy_datar_datar_source_source_ready1 - attribute \src "ls180.v:1371.6-1371.49" + attribute \src "ls180.v:1376.6-1376.49" wire \main_sdphy_datar_datar_source_source_valid0 - attribute \src "ls180.v:1392.6-1392.49" + attribute \src "ls180.v:1397.6-1397.49" wire \main_sdphy_datar_datar_source_source_valid1 - attribute \src "ls180.v:1376.6-1376.34" + attribute \src "ls180.v:1381.6-1381.34" wire \main_sdphy_datar_datar_start - attribute \src "ls180.v:1332.5-1332.43" + attribute \src "ls180.v:1337.5-1337.43" wire \main_sdphy_datar_pads_in_pads_in_first - attribute \src "ls180.v:1333.5-1333.42" + attribute \src "ls180.v:1338.5-1338.42" wire \main_sdphy_datar_pads_in_pads_in_last - attribute \src "ls180.v:1334.5-1334.49" + attribute \src "ls180.v:1339.5-1339.49" wire \main_sdphy_datar_pads_in_pads_in_payload_clk - attribute \src "ls180.v:1335.6-1335.52" + attribute \src "ls180.v:1340.6-1340.52" wire \main_sdphy_datar_pads_in_pads_in_payload_cmd_i - attribute \src "ls180.v:1336.5-1336.51" + attribute \src "ls180.v:1341.5-1341.51" wire \main_sdphy_datar_pads_in_pads_in_payload_cmd_o - attribute \src "ls180.v:1337.5-1337.52" + attribute \src "ls180.v:1342.5-1342.52" wire \main_sdphy_datar_pads_in_pads_in_payload_cmd_oe - attribute \src "ls180.v:1338.12-1338.59" + attribute \src "ls180.v:1343.12-1343.59" wire width 4 \main_sdphy_datar_pads_in_pads_in_payload_data_i - attribute \src "ls180.v:1339.11-1339.58" + attribute \src "ls180.v:1344.11-1344.58" wire width 4 \main_sdphy_datar_pads_in_pads_in_payload_data_o - attribute \src "ls180.v:1340.5-1340.53" + attribute \src "ls180.v:1345.5-1345.53" wire \main_sdphy_datar_pads_in_pads_in_payload_data_oe - attribute \src "ls180.v:1331.6-1331.44" + attribute \src "ls180.v:1336.6-1336.44" wire \main_sdphy_datar_pads_in_pads_in_ready - attribute \src "ls180.v:1330.6-1330.44" + attribute \src "ls180.v:1335.6-1335.44" wire \main_sdphy_datar_pads_in_pads_in_valid - attribute \src "ls180.v:1342.5-1342.42" + attribute \src "ls180.v:1347.5-1347.42" wire \main_sdphy_datar_pads_out_payload_clk - attribute \src "ls180.v:1343.5-1343.44" + attribute \src "ls180.v:1348.5-1348.44" wire \main_sdphy_datar_pads_out_payload_cmd_o - attribute \src "ls180.v:1344.5-1344.45" + attribute \src "ls180.v:1349.5-1349.45" wire \main_sdphy_datar_pads_out_payload_cmd_oe - attribute \src "ls180.v:1345.11-1345.51" + attribute \src "ls180.v:1350.11-1350.51" wire width 4 \main_sdphy_datar_pads_out_payload_data_o - attribute \src "ls180.v:1346.5-1346.46" + attribute \src "ls180.v:1351.5-1351.46" wire \main_sdphy_datar_pads_out_payload_data_oe - attribute \src "ls180.v:1341.6-1341.37" + attribute \src "ls180.v:1346.6-1346.37" wire \main_sdphy_datar_pads_out_ready - attribute \src "ls180.v:1349.5-1349.31" + attribute \src "ls180.v:1354.5-1354.31" wire \main_sdphy_datar_sink_last - attribute \src "ls180.v:1350.11-1350.53" + attribute \src "ls180.v:1355.11-1355.53" wire width 10 \main_sdphy_datar_sink_payload_block_length - attribute \src "ls180.v:1348.5-1348.32" + attribute \src "ls180.v:1353.5-1353.32" wire \main_sdphy_datar_sink_ready - attribute \src "ls180.v:1347.5-1347.32" + attribute \src "ls180.v:1352.5-1352.32" wire \main_sdphy_datar_sink_valid - attribute \src "ls180.v:1353.5-1353.34" + attribute \src "ls180.v:1358.5-1358.34" wire \main_sdphy_datar_source_first - attribute \src "ls180.v:1354.5-1354.33" + attribute \src "ls180.v:1359.5-1359.33" wire \main_sdphy_datar_source_last - attribute \src "ls180.v:1355.11-1355.47" + attribute \src "ls180.v:1360.11-1360.47" wire width 8 \main_sdphy_datar_source_payload_data - attribute \src "ls180.v:1356.11-1356.49" + attribute \src "ls180.v:1361.11-1361.49" wire width 3 \main_sdphy_datar_source_payload_status - attribute \src "ls180.v:1352.5-1352.34" + attribute \src "ls180.v:1357.5-1357.34" wire \main_sdphy_datar_source_ready - attribute \src "ls180.v:1351.5-1351.34" + attribute \src "ls180.v:1356.5-1356.34" wire \main_sdphy_datar_source_valid - attribute \src "ls180.v:1357.5-1357.26" + attribute \src "ls180.v:1362.5-1362.26" wire \main_sdphy_datar_stop - attribute \src "ls180.v:1358.12-1358.36" + attribute \src "ls180.v:1363.12-1363.36" wire width 32 \main_sdphy_datar_timeout - attribute \src "ls180.v:1860.12-1860.65" + attribute \src "ls180.v:1865.12-1865.65" wire width 32 \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1 - attribute \src "ls180.v:1861.5-1861.61" + attribute \src "ls180.v:1866.5-1866.61" wire \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1 - attribute \src "ls180.v:1267.11-1267.33" + attribute \src "ls180.v:1272.11-1272.33" wire width 8 \main_sdphy_dataw_count - attribute \src "ls180.v:1854.11-1854.54" + attribute \src "ls180.v:1859.11-1859.54" wire width 8 \main_sdphy_dataw_count_sdphy_fsm_next_value - attribute \src "ls180.v:1855.5-1855.51" + attribute \src "ls180.v:1860.5-1860.51" wire \main_sdphy_dataw_count_sdphy_fsm_next_value_ce - attribute \src "ls180.v:1321.6-1321.42" + attribute \src "ls180.v:1326.6-1326.42" wire \main_sdphy_dataw_crcr_buf_sink_first - attribute \src "ls180.v:1322.6-1322.41" + attribute \src "ls180.v:1327.6-1327.41" wire \main_sdphy_dataw_crcr_buf_sink_last - attribute \src "ls180.v:1323.12-1323.55" + attribute \src "ls180.v:1328.12-1328.55" wire width 8 \main_sdphy_dataw_crcr_buf_sink_payload_data - attribute \src "ls180.v:1320.6-1320.42" + attribute \src "ls180.v:1325.6-1325.42" wire \main_sdphy_dataw_crcr_buf_sink_ready - attribute \src "ls180.v:1319.6-1319.42" + attribute \src "ls180.v:1324.6-1324.42" wire \main_sdphy_dataw_crcr_buf_sink_valid - attribute \src "ls180.v:1326.5-1326.43" + attribute \src "ls180.v:1331.5-1331.43" wire \main_sdphy_dataw_crcr_buf_source_first - attribute \src "ls180.v:1327.5-1327.42" + attribute \src "ls180.v:1332.5-1332.42" wire \main_sdphy_dataw_crcr_buf_source_last - attribute \src "ls180.v:1328.11-1328.56" + attribute \src "ls180.v:1333.11-1333.56" wire width 8 \main_sdphy_dataw_crcr_buf_source_payload_data - attribute \src "ls180.v:1325.6-1325.44" + attribute \src "ls180.v:1330.6-1330.44" wire \main_sdphy_dataw_crcr_buf_source_ready - attribute \src "ls180.v:1324.5-1324.43" + attribute \src "ls180.v:1329.5-1329.43" wire \main_sdphy_dataw_crcr_buf_source_valid - attribute \src "ls180.v:1311.11-1311.48" + attribute \src "ls180.v:1316.11-1316.48" wire width 3 \main_sdphy_dataw_crcr_converter_demux - attribute \src "ls180.v:1312.6-1312.47" + attribute \src "ls180.v:1317.6-1317.47" wire \main_sdphy_dataw_crcr_converter_load_part - attribute \src "ls180.v:1302.5-1302.47" + attribute \src "ls180.v:1307.5-1307.47" wire \main_sdphy_dataw_crcr_converter_sink_first - attribute \src "ls180.v:1303.5-1303.46" + attribute \src "ls180.v:1308.5-1308.46" wire \main_sdphy_dataw_crcr_converter_sink_last - attribute \src "ls180.v:1304.6-1304.55" + attribute \src "ls180.v:1309.6-1309.55" wire \main_sdphy_dataw_crcr_converter_sink_payload_data - attribute \src "ls180.v:1301.6-1301.48" + attribute \src "ls180.v:1306.6-1306.48" wire \main_sdphy_dataw_crcr_converter_sink_ready - attribute \src "ls180.v:1300.6-1300.48" + attribute \src "ls180.v:1305.6-1305.48" wire \main_sdphy_dataw_crcr_converter_sink_valid - attribute \src "ls180.v:1307.5-1307.49" + attribute \src "ls180.v:1312.5-1312.49" wire \main_sdphy_dataw_crcr_converter_source_first - attribute \src "ls180.v:1308.5-1308.48" + attribute \src "ls180.v:1313.5-1313.48" wire \main_sdphy_dataw_crcr_converter_source_last - attribute \src "ls180.v:1309.11-1309.62" + attribute \src "ls180.v:1314.11-1314.62" wire width 8 \main_sdphy_dataw_crcr_converter_source_payload_data - attribute \src "ls180.v:1310.11-1310.75" + attribute \src "ls180.v:1315.11-1315.75" wire width 4 \main_sdphy_dataw_crcr_converter_source_payload_valid_token_count - attribute \src "ls180.v:1306.6-1306.50" + attribute \src "ls180.v:1311.6-1311.50" wire \main_sdphy_dataw_crcr_converter_source_ready - attribute \src "ls180.v:1305.6-1305.50" + attribute \src "ls180.v:1310.6-1310.50" wire \main_sdphy_dataw_crcr_converter_source_valid - attribute \src "ls180.v:1313.5-1313.47" + attribute \src "ls180.v:1318.5-1318.47" wire \main_sdphy_dataw_crcr_converter_strobe_all - attribute \src "ls180.v:1284.6-1284.41" + attribute \src "ls180.v:1289.6-1289.41" wire \main_sdphy_dataw_crcr_pads_in_first - attribute \src "ls180.v:1285.6-1285.40" + attribute \src "ls180.v:1290.6-1290.40" wire \main_sdphy_dataw_crcr_pads_in_last - attribute \src "ls180.v:1286.6-1286.47" + attribute \src "ls180.v:1291.6-1291.47" wire \main_sdphy_dataw_crcr_pads_in_payload_clk - attribute \src "ls180.v:1287.6-1287.49" + attribute \src "ls180.v:1292.6-1292.49" wire \main_sdphy_dataw_crcr_pads_in_payload_cmd_i - attribute \src "ls180.v:1288.6-1288.49" + attribute \src "ls180.v:1293.6-1293.49" wire \main_sdphy_dataw_crcr_pads_in_payload_cmd_o - attribute \src "ls180.v:1289.6-1289.50" + attribute \src "ls180.v:1294.6-1294.50" wire \main_sdphy_dataw_crcr_pads_in_payload_cmd_oe - attribute \src "ls180.v:1290.12-1290.56" + attribute \src "ls180.v:1295.12-1295.56" wire width 4 \main_sdphy_dataw_crcr_pads_in_payload_data_i - attribute \src "ls180.v:1291.12-1291.56" + attribute \src "ls180.v:1296.12-1296.56" wire width 4 \main_sdphy_dataw_crcr_pads_in_payload_data_o - attribute \src "ls180.v:1292.6-1292.51" + attribute \src "ls180.v:1297.6-1297.51" wire \main_sdphy_dataw_crcr_pads_in_payload_data_oe - attribute \src "ls180.v:1283.5-1283.40" + attribute \src "ls180.v:1288.5-1288.40" wire \main_sdphy_dataw_crcr_pads_in_ready - attribute \src "ls180.v:1282.6-1282.41" + attribute \src "ls180.v:1287.6-1287.41" wire \main_sdphy_dataw_crcr_pads_in_valid - attribute \src "ls180.v:1329.5-1329.32" + attribute \src "ls180.v:1334.5-1334.32" wire \main_sdphy_dataw_crcr_reset - attribute \src "ls180.v:1850.5-1850.59" + attribute \src "ls180.v:1855.5-1855.59" wire \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value - attribute \src "ls180.v:1851.5-1851.62" + attribute \src "ls180.v:1856.5-1856.62" wire \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce - attribute \src "ls180.v:1299.5-1299.30" + attribute \src "ls180.v:1304.5-1304.30" wire \main_sdphy_dataw_crcr_run - attribute \src "ls180.v:1295.6-1295.48" + attribute \src "ls180.v:1300.6-1300.48" wire \main_sdphy_dataw_crcr_source_source_first0 - attribute \src "ls180.v:1316.6-1316.48" + attribute \src "ls180.v:1321.6-1321.48" wire \main_sdphy_dataw_crcr_source_source_first1 - attribute \src "ls180.v:1296.6-1296.47" + attribute \src "ls180.v:1301.6-1301.47" wire \main_sdphy_dataw_crcr_source_source_last0 - attribute \src "ls180.v:1317.6-1317.47" + attribute \src "ls180.v:1322.6-1322.47" wire \main_sdphy_dataw_crcr_source_source_last1 - attribute \src "ls180.v:1297.12-1297.61" + attribute \src "ls180.v:1302.12-1302.61" wire width 8 \main_sdphy_dataw_crcr_source_source_payload_data0 - attribute \src "ls180.v:1318.12-1318.61" + attribute \src "ls180.v:1323.12-1323.61" wire width 8 \main_sdphy_dataw_crcr_source_source_payload_data1 - attribute \src "ls180.v:1294.5-1294.47" + attribute \src "ls180.v:1299.5-1299.47" wire \main_sdphy_dataw_crcr_source_source_ready0 - attribute \src "ls180.v:1315.6-1315.48" + attribute \src "ls180.v:1320.6-1320.48" wire \main_sdphy_dataw_crcr_source_source_ready1 - attribute \src "ls180.v:1293.6-1293.48" + attribute \src "ls180.v:1298.6-1298.48" wire \main_sdphy_dataw_crcr_source_source_valid0 - attribute \src "ls180.v:1314.6-1314.48" + attribute \src "ls180.v:1319.6-1319.48" wire \main_sdphy_dataw_crcr_source_source_valid1 - attribute \src "ls180.v:1298.6-1298.33" + attribute \src "ls180.v:1303.6-1303.33" wire \main_sdphy_dataw_crcr_start - attribute \src "ls180.v:1281.5-1281.27" + attribute \src "ls180.v:1286.5-1286.27" wire \main_sdphy_dataw_error - attribute \src "ls180.v:1270.5-1270.43" + attribute \src "ls180.v:1275.5-1275.43" wire \main_sdphy_dataw_pads_in_pads_in_first - attribute \src "ls180.v:1271.5-1271.42" + attribute \src "ls180.v:1276.5-1276.42" wire \main_sdphy_dataw_pads_in_pads_in_last - attribute \src "ls180.v:1272.5-1272.49" + attribute \src "ls180.v:1277.5-1277.49" wire \main_sdphy_dataw_pads_in_pads_in_payload_clk - attribute \src "ls180.v:1273.5-1273.51" + attribute \src "ls180.v:1278.5-1278.51" wire \main_sdphy_dataw_pads_in_pads_in_payload_cmd_i - attribute \src "ls180.v:1274.5-1274.51" + attribute \src "ls180.v:1279.5-1279.51" wire \main_sdphy_dataw_pads_in_pads_in_payload_cmd_o - attribute \src "ls180.v:1275.5-1275.52" + attribute \src "ls180.v:1280.5-1280.52" wire \main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe - attribute \src "ls180.v:1276.11-1276.58" + attribute \src "ls180.v:1281.11-1281.58" wire width 4 \main_sdphy_dataw_pads_in_pads_in_payload_data_i - attribute \src "ls180.v:1277.11-1277.58" + attribute \src "ls180.v:1282.11-1282.58" wire width 4 \main_sdphy_dataw_pads_in_pads_in_payload_data_o - attribute \src "ls180.v:1278.5-1278.53" + attribute \src "ls180.v:1283.5-1283.53" wire \main_sdphy_dataw_pads_in_pads_in_payload_data_oe - attribute \src "ls180.v:1269.6-1269.44" + attribute \src "ls180.v:1274.6-1274.44" wire \main_sdphy_dataw_pads_in_pads_in_ready - attribute \src "ls180.v:1268.5-1268.43" + attribute \src "ls180.v:1273.5-1273.43" wire \main_sdphy_dataw_pads_in_pads_in_valid - attribute \src "ls180.v:1253.6-1253.44" + attribute \src "ls180.v:1258.6-1258.44" wire \main_sdphy_dataw_pads_in_payload_cmd_i - attribute \src "ls180.v:1254.12-1254.51" + attribute \src "ls180.v:1259.12-1259.51" wire width 4 \main_sdphy_dataw_pads_in_payload_data_i - attribute \src "ls180.v:1252.6-1252.36" + attribute \src "ls180.v:1257.6-1257.36" wire \main_sdphy_dataw_pads_in_valid - attribute \src "ls180.v:1256.5-1256.42" + attribute \src "ls180.v:1261.5-1261.42" wire \main_sdphy_dataw_pads_out_payload_clk - attribute \src "ls180.v:1257.5-1257.44" + attribute \src "ls180.v:1262.5-1262.44" wire \main_sdphy_dataw_pads_out_payload_cmd_o - attribute \src "ls180.v:1258.5-1258.45" + attribute \src "ls180.v:1263.5-1263.45" wire \main_sdphy_dataw_pads_out_payload_cmd_oe - attribute \src "ls180.v:1259.11-1259.51" + attribute \src "ls180.v:1264.11-1264.51" wire width 4 \main_sdphy_dataw_pads_out_payload_data_o - attribute \src "ls180.v:1260.5-1260.46" + attribute \src "ls180.v:1265.5-1265.46" wire \main_sdphy_dataw_pads_out_payload_data_oe - attribute \src "ls180.v:1255.6-1255.37" + attribute \src "ls180.v:1260.6-1260.37" wire \main_sdphy_dataw_pads_out_ready - attribute \src "ls180.v:1263.5-1263.32" + attribute \src "ls180.v:1268.5-1268.32" wire \main_sdphy_dataw_sink_first - attribute \src "ls180.v:1264.5-1264.31" + attribute \src "ls180.v:1269.5-1269.31" wire \main_sdphy_dataw_sink_last - attribute \src "ls180.v:1265.11-1265.45" + attribute \src "ls180.v:1270.11-1270.45" wire width 8 \main_sdphy_dataw_sink_payload_data - attribute \src "ls180.v:1262.5-1262.32" + attribute \src "ls180.v:1267.5-1267.32" wire \main_sdphy_dataw_sink_ready - attribute \src "ls180.v:1261.5-1261.32" + attribute \src "ls180.v:1266.5-1266.32" wire \main_sdphy_dataw_sink_valid - attribute \src "ls180.v:1279.5-1279.27" + attribute \src "ls180.v:1284.5-1284.27" wire \main_sdphy_dataw_start - attribute \src "ls180.v:1266.5-1266.26" + attribute \src "ls180.v:1271.5-1271.26" wire \main_sdphy_dataw_stop - attribute \src "ls180.v:1280.5-1280.27" + attribute \src "ls180.v:1285.5-1285.27" wire \main_sdphy_dataw_valid - attribute \src "ls180.v:1160.11-1160.32" + attribute \src "ls180.v:1165.11-1165.32" wire width 8 \main_sdphy_init_count - attribute \src "ls180.v:1834.11-1834.59" + attribute \src "ls180.v:1839.11-1839.59" wire width 8 \main_sdphy_init_count_sdphy_sdphyinit_next_value - attribute \src "ls180.v:1835.5-1835.56" + attribute \src "ls180.v:1840.5-1840.56" wire \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce - attribute \src "ls180.v:1148.6-1148.34" + attribute \src "ls180.v:1153.6-1153.34" wire \main_sdphy_init_initialize_r - attribute \src "ls180.v:1147.6-1147.35" + attribute \src "ls180.v:1152.6-1152.35" wire \main_sdphy_init_initialize_re - attribute \src "ls180.v:1150.5-1150.33" + attribute \src "ls180.v:1155.5-1155.33" wire \main_sdphy_init_initialize_w - attribute \src "ls180.v:1149.6-1149.35" + attribute \src "ls180.v:1154.6-1154.35" wire \main_sdphy_init_initialize_we - attribute \src "ls180.v:1152.6-1152.43" + attribute \src "ls180.v:1157.6-1157.43" wire \main_sdphy_init_pads_in_payload_cmd_i - attribute \src "ls180.v:1153.12-1153.50" + attribute \src "ls180.v:1158.12-1158.50" wire width 4 \main_sdphy_init_pads_in_payload_data_i - attribute \src "ls180.v:1151.6-1151.35" + attribute \src "ls180.v:1156.6-1156.35" wire \main_sdphy_init_pads_in_valid - attribute \src "ls180.v:1155.5-1155.41" + attribute \src "ls180.v:1160.5-1160.41" wire \main_sdphy_init_pads_out_payload_clk - attribute \src "ls180.v:1156.5-1156.43" + attribute \src "ls180.v:1161.5-1161.43" wire \main_sdphy_init_pads_out_payload_cmd_o - attribute \src "ls180.v:1157.5-1157.44" + attribute \src "ls180.v:1162.5-1162.44" wire \main_sdphy_init_pads_out_payload_cmd_oe - attribute \src "ls180.v:1158.11-1158.50" + attribute \src "ls180.v:1163.11-1163.50" wire width 4 \main_sdphy_init_pads_out_payload_data_o - attribute \src "ls180.v:1159.5-1159.45" + attribute \src "ls180.v:1164.5-1164.45" wire \main_sdphy_init_pads_out_payload_data_oe - attribute \src "ls180.v:1154.6-1154.36" + attribute \src "ls180.v:1159.6-1159.36" wire \main_sdphy_init_pads_out_ready - attribute \src "ls180.v:1408.6-1408.27" + attribute \src "ls180.v:1413.6-1413.27" wire \main_sdphy_sdpads_clk - attribute \src "ls180.v:1409.5-1409.28" + attribute \src "ls180.v:1414.5-1414.28" wire \main_sdphy_sdpads_cmd_i - attribute \src "ls180.v:1410.6-1410.29" + attribute \src "ls180.v:1415.6-1415.29" wire \main_sdphy_sdpads_cmd_o - attribute \src "ls180.v:1411.6-1411.30" + attribute \src "ls180.v:1416.6-1416.30" wire \main_sdphy_sdpads_cmd_oe - attribute \src "ls180.v:1412.11-1412.35" + attribute \src "ls180.v:1417.11-1417.35" wire width 4 \main_sdphy_sdpads_data_i - attribute \src "ls180.v:1413.12-1413.36" + attribute \src "ls180.v:1418.12-1418.36" wire width 4 \main_sdphy_sdpads_data_o - attribute \src "ls180.v:1414.6-1414.31" + attribute \src "ls180.v:1419.6-1419.31" wire \main_sdphy_sdpads_data_oe - attribute \src "ls180.v:1137.6-1137.23" + attribute \src "ls180.v:1142.6-1142.23" wire \main_sdphy_status - attribute \src "ls180.v:1138.6-1138.19" + attribute \src "ls180.v:1143.6-1143.19" wire \main_sdphy_we - attribute \src "ls180.v:372.5-372.26" + attribute \src "ls180.v:359.5-359.26" wire \main_sdram_address_re - attribute \src "ls180.v:371.12-371.38" + attribute \src "ls180.v:358.12-358.38" wire width 13 \main_sdram_address_storage - attribute \src "ls180.v:374.5-374.27" + attribute \src "ls180.v:361.5-361.27" wire \main_sdram_baddress_re - attribute \src "ls180.v:373.11-373.38" + attribute \src "ls180.v:360.11-360.38" wire width 2 \main_sdram_baddress_storage - attribute \src "ls180.v:470.5-470.43" + attribute \src "ls180.v:457.5-457.43" wire \main_sdram_bankmachine0_auto_precharge - attribute \src "ls180.v:492.11-492.63" + attribute \src "ls180.v:479.11-479.63" wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_consume - attribute \src "ls180.v:497.6-497.58" + attribute \src "ls180.v:484.6-484.58" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:502.6-502.64" + attribute \src "ls180.v:489.6-489.64" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first - attribute \src "ls180.v:503.6-503.63" + attribute \src "ls180.v:490.6-490.63" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last - attribute \src "ls180.v:501.13-501.78" + attribute \src "ls180.v:488.13-488.78" wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr - attribute \src "ls180.v:500.6-500.69" + attribute \src "ls180.v:487.6-487.69" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we - attribute \src "ls180.v:506.6-506.65" + attribute \src "ls180.v:493.6-493.65" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first - attribute \src "ls180.v:507.6-507.64" + attribute \src "ls180.v:494.6-494.64" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last - attribute \src "ls180.v:505.13-505.79" + attribute \src "ls180.v:492.13-492.79" wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr - attribute \src "ls180.v:504.6-504.70" + attribute \src "ls180.v:491.6-491.70" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we - attribute \src "ls180.v:489.11-489.61" + attribute \src "ls180.v:476.11-476.61" wire width 4 \main_sdram_bankmachine0_cmd_buffer_lookahead_level - attribute \src "ls180.v:491.11-491.63" + attribute \src "ls180.v:478.11-478.63" wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_produce - attribute \src "ls180.v:498.12-498.67" + attribute \src "ls180.v:485.12-485.67" wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr - attribute \src "ls180.v:499.13-499.70" + attribute \src "ls180.v:486.13-486.70" wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r - attribute \src "ls180.v:490.5-490.57" + attribute \src "ls180.v:477.5-477.57" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_replace - attribute \src "ls180.v:473.5-473.60" + attribute \src "ls180.v:460.5-460.60" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first - attribute \src "ls180.v:474.5-474.59" + attribute \src "ls180.v:461.5-461.59" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last - attribute \src "ls180.v:476.13-476.75" + attribute \src "ls180.v:463.13-463.75" wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr - attribute \src "ls180.v:475.6-475.66" + attribute \src "ls180.v:462.6-462.66" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we - attribute \src "ls180.v:472.6-472.61" + attribute \src "ls180.v:459.6-459.61" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready - attribute \src "ls180.v:471.6-471.61" + attribute \src "ls180.v:458.6-458.61" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid - attribute \src "ls180.v:479.6-479.63" + attribute \src "ls180.v:466.6-466.63" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_first - attribute \src "ls180.v:480.6-480.62" + attribute \src "ls180.v:467.6-467.62" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_last - attribute \src "ls180.v:482.13-482.77" + attribute \src "ls180.v:469.13-469.77" wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr - attribute \src "ls180.v:481.6-481.68" + attribute \src "ls180.v:468.6-468.68" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we - attribute \src "ls180.v:478.6-478.63" + attribute \src "ls180.v:465.6-465.63" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_ready - attribute \src "ls180.v:477.6-477.63" + attribute \src "ls180.v:464.6-464.63" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid - attribute \src "ls180.v:487.13-487.71" + attribute \src "ls180.v:474.13-474.71" wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din - attribute \src "ls180.v:488.13-488.72" + attribute \src "ls180.v:475.13-475.72" wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout - attribute \src "ls180.v:485.6-485.63" + attribute \src "ls180.v:472.6-472.63" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re - attribute \src "ls180.v:486.6-486.69" + attribute \src "ls180.v:473.6-473.69" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable - attribute \src "ls180.v:483.6-483.63" + attribute \src "ls180.v:470.6-470.63" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we - attribute \src "ls180.v:484.6-484.69" + attribute \src "ls180.v:471.6-471.69" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable - attribute \src "ls180.v:493.11-493.66" + attribute \src "ls180.v:480.11-480.66" wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr - attribute \src "ls180.v:494.13-494.70" + attribute \src "ls180.v:481.13-481.70" wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r - attribute \src "ls180.v:496.13-496.70" + attribute \src "ls180.v:483.13-483.70" wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w - attribute \src "ls180.v:495.6-495.60" + attribute \src "ls180.v:482.6-482.60" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:510.6-510.51" + attribute \src "ls180.v:497.6-497.51" wire \main_sdram_bankmachine0_cmd_buffer_sink_first - attribute \src "ls180.v:511.6-511.50" + attribute \src "ls180.v:498.6-498.50" wire \main_sdram_bankmachine0_cmd_buffer_sink_last - attribute \src "ls180.v:513.13-513.65" + attribute \src "ls180.v:500.13-500.65" wire width 22 \main_sdram_bankmachine0_cmd_buffer_sink_payload_addr - attribute \src "ls180.v:512.6-512.56" + attribute \src "ls180.v:499.6-499.56" wire \main_sdram_bankmachine0_cmd_buffer_sink_payload_we - attribute \src "ls180.v:509.6-509.51" + attribute \src "ls180.v:496.6-496.51" wire \main_sdram_bankmachine0_cmd_buffer_sink_ready - attribute \src "ls180.v:508.6-508.51" + attribute \src "ls180.v:495.6-495.51" wire \main_sdram_bankmachine0_cmd_buffer_sink_valid - attribute \src "ls180.v:516.5-516.52" + attribute \src "ls180.v:503.5-503.52" wire \main_sdram_bankmachine0_cmd_buffer_source_first - attribute \src "ls180.v:517.5-517.51" + attribute \src "ls180.v:504.5-504.51" wire \main_sdram_bankmachine0_cmd_buffer_source_last - attribute \src "ls180.v:519.12-519.66" + attribute \src "ls180.v:506.12-506.66" wire width 22 \main_sdram_bankmachine0_cmd_buffer_source_payload_addr - attribute \src "ls180.v:518.5-518.57" + attribute \src "ls180.v:505.5-505.57" wire \main_sdram_bankmachine0_cmd_buffer_source_payload_we - attribute \src "ls180.v:515.6-515.53" + attribute \src "ls180.v:502.6-502.53" wire \main_sdram_bankmachine0_cmd_buffer_source_ready - attribute \src "ls180.v:514.5-514.52" + attribute \src "ls180.v:501.5-501.52" wire \main_sdram_bankmachine0_cmd_buffer_source_valid - attribute \src "ls180.v:462.12-462.49" + attribute \src "ls180.v:449.12-449.49" wire width 13 \main_sdram_bankmachine0_cmd_payload_a - attribute \src "ls180.v:463.12-463.50" + attribute \src "ls180.v:450.12-450.50" wire width 2 \main_sdram_bankmachine0_cmd_payload_ba - attribute \src "ls180.v:464.5-464.44" + attribute \src "ls180.v:451.5-451.44" wire \main_sdram_bankmachine0_cmd_payload_cas - attribute \src "ls180.v:467.5-467.47" + attribute \src "ls180.v:454.5-454.47" wire \main_sdram_bankmachine0_cmd_payload_is_cmd - attribute \src "ls180.v:468.5-468.48" + attribute \src "ls180.v:455.5-455.48" wire \main_sdram_bankmachine0_cmd_payload_is_read - attribute \src "ls180.v:469.5-469.49" + attribute \src "ls180.v:456.5-456.49" wire \main_sdram_bankmachine0_cmd_payload_is_write - attribute \src "ls180.v:465.5-465.44" + attribute \src "ls180.v:452.5-452.44" wire \main_sdram_bankmachine0_cmd_payload_ras - attribute \src "ls180.v:466.5-466.43" + attribute \src "ls180.v:453.5-453.43" wire \main_sdram_bankmachine0_cmd_payload_we - attribute \src "ls180.v:461.5-461.38" + attribute \src "ls180.v:448.5-448.38" wire \main_sdram_bankmachine0_cmd_ready - attribute \src "ls180.v:460.5-460.38" + attribute \src "ls180.v:447.5-447.38" wire \main_sdram_bankmachine0_cmd_valid - attribute \src "ls180.v:459.5-459.40" + attribute \src "ls180.v:446.5-446.40" wire \main_sdram_bankmachine0_refresh_gnt - attribute \src "ls180.v:458.6-458.41" + attribute \src "ls180.v:445.6-445.41" wire \main_sdram_bankmachine0_refresh_req - attribute \src "ls180.v:454.13-454.45" + attribute \src "ls180.v:441.13-441.45" wire width 22 \main_sdram_bankmachine0_req_addr - attribute \src "ls180.v:455.6-455.38" + attribute \src "ls180.v:442.6-442.38" wire \main_sdram_bankmachine0_req_lock - attribute \src "ls180.v:457.5-457.44" + attribute \src "ls180.v:444.5-444.44" wire \main_sdram_bankmachine0_req_rdata_valid - attribute \src "ls180.v:452.6-452.39" + attribute \src "ls180.v:439.6-439.39" wire \main_sdram_bankmachine0_req_ready - attribute \src "ls180.v:451.6-451.39" + attribute \src "ls180.v:438.6-438.39" wire \main_sdram_bankmachine0_req_valid - attribute \src "ls180.v:456.5-456.44" + attribute \src "ls180.v:443.5-443.44" wire \main_sdram_bankmachine0_req_wdata_ready - attribute \src "ls180.v:453.6-453.36" + attribute \src "ls180.v:440.6-440.36" wire \main_sdram_bankmachine0_req_we - attribute \src "ls180.v:520.12-520.39" + attribute \src "ls180.v:507.12-507.39" wire width 13 \main_sdram_bankmachine0_row - attribute \src "ls180.v:524.5-524.38" + attribute \src "ls180.v:511.5-511.38" wire \main_sdram_bankmachine0_row_close - attribute \src "ls180.v:525.5-525.47" + attribute \src "ls180.v:512.5-512.47" wire \main_sdram_bankmachine0_row_col_n_addr_sel - attribute \src "ls180.v:522.6-522.37" + attribute \src "ls180.v:509.6-509.37" wire \main_sdram_bankmachine0_row_hit - attribute \src "ls180.v:523.5-523.37" + attribute \src "ls180.v:510.5-510.37" wire \main_sdram_bankmachine0_row_open - attribute \src "ls180.v:521.5-521.39" + attribute \src "ls180.v:508.5-508.39" wire \main_sdram_bankmachine0_row_opened attribute \no_retiming "true" - attribute \src "ls180.v:532.32-532.69" + attribute \src "ls180.v:519.32-519.69" wire \main_sdram_bankmachine0_trascon_ready - attribute \src "ls180.v:531.6-531.43" + attribute \src "ls180.v:518.6-518.43" wire \main_sdram_bankmachine0_trascon_valid attribute \no_retiming "true" - attribute \src "ls180.v:530.32-530.68" + attribute \src "ls180.v:517.32-517.68" wire \main_sdram_bankmachine0_trccon_ready - attribute \src "ls180.v:529.6-529.42" + attribute \src "ls180.v:516.6-516.42" wire \main_sdram_bankmachine0_trccon_valid - attribute \src "ls180.v:528.11-528.48" + attribute \src "ls180.v:515.11-515.48" wire width 3 \main_sdram_bankmachine0_twtpcon_count attribute \no_retiming "true" - attribute \src "ls180.v:527.32-527.69" + attribute \src "ls180.v:514.32-514.69" wire \main_sdram_bankmachine0_twtpcon_ready - attribute \src "ls180.v:526.6-526.43" + attribute \src "ls180.v:513.6-513.43" wire \main_sdram_bankmachine0_twtpcon_valid - attribute \src "ls180.v:552.5-552.43" + attribute \src "ls180.v:539.5-539.43" wire \main_sdram_bankmachine1_auto_precharge - attribute \src "ls180.v:574.11-574.63" + attribute \src "ls180.v:561.11-561.63" wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_consume - attribute \src "ls180.v:579.6-579.58" + attribute \src "ls180.v:566.6-566.58" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:584.6-584.64" + attribute \src "ls180.v:571.6-571.64" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first - attribute \src "ls180.v:585.6-585.63" + attribute \src "ls180.v:572.6-572.63" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last - attribute \src "ls180.v:583.13-583.78" + attribute \src "ls180.v:570.13-570.78" wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr - attribute \src "ls180.v:582.6-582.69" + attribute \src "ls180.v:569.6-569.69" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we - attribute \src "ls180.v:588.6-588.65" + attribute \src "ls180.v:575.6-575.65" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first - attribute \src "ls180.v:589.6-589.64" + attribute \src "ls180.v:576.6-576.64" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last - attribute \src "ls180.v:587.13-587.79" + attribute \src "ls180.v:574.13-574.79" wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr - attribute \src "ls180.v:586.6-586.70" + attribute \src "ls180.v:573.6-573.70" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we - attribute \src "ls180.v:571.11-571.61" + attribute \src "ls180.v:558.11-558.61" wire width 4 \main_sdram_bankmachine1_cmd_buffer_lookahead_level - attribute \src "ls180.v:573.11-573.63" + attribute \src "ls180.v:560.11-560.63" wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_produce - attribute \src "ls180.v:580.12-580.67" + attribute \src "ls180.v:567.12-567.67" wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr - attribute \src "ls180.v:581.13-581.70" + attribute \src "ls180.v:568.13-568.70" wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r - attribute \src "ls180.v:572.5-572.57" + attribute \src "ls180.v:559.5-559.57" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_replace - attribute \src "ls180.v:555.5-555.60" + attribute \src "ls180.v:542.5-542.60" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first - attribute \src "ls180.v:556.5-556.59" + attribute \src "ls180.v:543.5-543.59" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last - attribute \src "ls180.v:558.13-558.75" + attribute \src "ls180.v:545.13-545.75" wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr - attribute \src "ls180.v:557.6-557.66" + attribute \src "ls180.v:544.6-544.66" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we - attribute \src "ls180.v:554.6-554.61" + attribute \src "ls180.v:541.6-541.61" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready - attribute \src "ls180.v:553.6-553.61" + attribute \src "ls180.v:540.6-540.61" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid - attribute \src "ls180.v:561.6-561.63" + attribute \src "ls180.v:548.6-548.63" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_first - attribute \src "ls180.v:562.6-562.62" + attribute \src "ls180.v:549.6-549.62" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_last - attribute \src "ls180.v:564.13-564.77" + attribute \src "ls180.v:551.13-551.77" wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr - attribute \src "ls180.v:563.6-563.68" + attribute \src "ls180.v:550.6-550.68" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we - attribute \src "ls180.v:560.6-560.63" + attribute \src "ls180.v:547.6-547.63" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_ready - attribute \src "ls180.v:559.6-559.63" + attribute \src "ls180.v:546.6-546.63" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid - attribute \src "ls180.v:569.13-569.71" + attribute \src "ls180.v:556.13-556.71" wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din - attribute \src "ls180.v:570.13-570.72" + attribute \src "ls180.v:557.13-557.72" wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout - attribute \src "ls180.v:567.6-567.63" + attribute \src "ls180.v:554.6-554.63" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re - attribute \src "ls180.v:568.6-568.69" + attribute \src "ls180.v:555.6-555.69" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable - attribute \src "ls180.v:565.6-565.63" + attribute \src "ls180.v:552.6-552.63" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we - attribute \src "ls180.v:566.6-566.69" + attribute \src "ls180.v:553.6-553.69" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable - attribute \src "ls180.v:575.11-575.66" + attribute \src "ls180.v:562.11-562.66" wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr - attribute \src "ls180.v:576.13-576.70" + attribute \src "ls180.v:563.13-563.70" wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r - attribute \src "ls180.v:578.13-578.70" + attribute \src "ls180.v:565.13-565.70" wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w - attribute \src "ls180.v:577.6-577.60" + attribute \src "ls180.v:564.6-564.60" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:592.6-592.51" + attribute \src "ls180.v:579.6-579.51" wire \main_sdram_bankmachine1_cmd_buffer_sink_first - attribute \src "ls180.v:593.6-593.50" + attribute \src "ls180.v:580.6-580.50" wire \main_sdram_bankmachine1_cmd_buffer_sink_last - attribute \src "ls180.v:595.13-595.65" + attribute \src "ls180.v:582.13-582.65" wire width 22 \main_sdram_bankmachine1_cmd_buffer_sink_payload_addr - attribute \src "ls180.v:594.6-594.56" + attribute \src "ls180.v:581.6-581.56" wire \main_sdram_bankmachine1_cmd_buffer_sink_payload_we - attribute \src "ls180.v:591.6-591.51" + attribute \src "ls180.v:578.6-578.51" wire \main_sdram_bankmachine1_cmd_buffer_sink_ready - attribute \src "ls180.v:590.6-590.51" + attribute \src "ls180.v:577.6-577.51" wire \main_sdram_bankmachine1_cmd_buffer_sink_valid - attribute \src "ls180.v:598.5-598.52" + attribute \src "ls180.v:585.5-585.52" wire \main_sdram_bankmachine1_cmd_buffer_source_first - attribute \src "ls180.v:599.5-599.51" + attribute \src "ls180.v:586.5-586.51" wire \main_sdram_bankmachine1_cmd_buffer_source_last - attribute \src "ls180.v:601.12-601.66" + attribute \src "ls180.v:588.12-588.66" wire width 22 \main_sdram_bankmachine1_cmd_buffer_source_payload_addr - attribute \src "ls180.v:600.5-600.57" + attribute \src "ls180.v:587.5-587.57" wire \main_sdram_bankmachine1_cmd_buffer_source_payload_we - attribute \src "ls180.v:597.6-597.53" + attribute \src "ls180.v:584.6-584.53" wire \main_sdram_bankmachine1_cmd_buffer_source_ready - attribute \src "ls180.v:596.5-596.52" + attribute \src "ls180.v:583.5-583.52" wire \main_sdram_bankmachine1_cmd_buffer_source_valid - attribute \src "ls180.v:544.12-544.49" + attribute \src "ls180.v:531.12-531.49" wire width 13 \main_sdram_bankmachine1_cmd_payload_a - attribute \src "ls180.v:545.12-545.50" + attribute \src "ls180.v:532.12-532.50" wire width 2 \main_sdram_bankmachine1_cmd_payload_ba - attribute \src "ls180.v:546.5-546.44" + attribute \src "ls180.v:533.5-533.44" wire \main_sdram_bankmachine1_cmd_payload_cas - attribute \src "ls180.v:549.5-549.47" + attribute \src "ls180.v:536.5-536.47" wire \main_sdram_bankmachine1_cmd_payload_is_cmd - attribute \src "ls180.v:550.5-550.48" + attribute \src "ls180.v:537.5-537.48" wire \main_sdram_bankmachine1_cmd_payload_is_read - attribute \src "ls180.v:551.5-551.49" + attribute \src "ls180.v:538.5-538.49" wire \main_sdram_bankmachine1_cmd_payload_is_write - attribute \src "ls180.v:547.5-547.44" + attribute \src "ls180.v:534.5-534.44" wire \main_sdram_bankmachine1_cmd_payload_ras - attribute \src "ls180.v:548.5-548.43" + attribute \src "ls180.v:535.5-535.43" wire \main_sdram_bankmachine1_cmd_payload_we - attribute \src "ls180.v:543.5-543.38" + attribute \src "ls180.v:530.5-530.38" wire \main_sdram_bankmachine1_cmd_ready - attribute \src "ls180.v:542.5-542.38" + attribute \src "ls180.v:529.5-529.38" wire \main_sdram_bankmachine1_cmd_valid - attribute \src "ls180.v:541.5-541.40" + attribute \src "ls180.v:528.5-528.40" wire \main_sdram_bankmachine1_refresh_gnt - attribute \src "ls180.v:540.6-540.41" + attribute \src "ls180.v:527.6-527.41" wire \main_sdram_bankmachine1_refresh_req - attribute \src "ls180.v:536.13-536.45" + attribute \src "ls180.v:523.13-523.45" wire width 22 \main_sdram_bankmachine1_req_addr - attribute \src "ls180.v:537.6-537.38" + attribute \src "ls180.v:524.6-524.38" wire \main_sdram_bankmachine1_req_lock - attribute \src "ls180.v:539.5-539.44" + attribute \src "ls180.v:526.5-526.44" wire \main_sdram_bankmachine1_req_rdata_valid - attribute \src "ls180.v:534.6-534.39" + attribute \src "ls180.v:521.6-521.39" wire \main_sdram_bankmachine1_req_ready - attribute \src "ls180.v:533.6-533.39" + attribute \src "ls180.v:520.6-520.39" wire \main_sdram_bankmachine1_req_valid - attribute \src "ls180.v:538.5-538.44" + attribute \src "ls180.v:525.5-525.44" wire \main_sdram_bankmachine1_req_wdata_ready - attribute \src "ls180.v:535.6-535.36" + attribute \src "ls180.v:522.6-522.36" wire \main_sdram_bankmachine1_req_we - attribute \src "ls180.v:602.12-602.39" + attribute \src "ls180.v:589.12-589.39" wire width 13 \main_sdram_bankmachine1_row - attribute \src "ls180.v:606.5-606.38" + attribute \src "ls180.v:593.5-593.38" wire \main_sdram_bankmachine1_row_close - attribute \src "ls180.v:607.5-607.47" + attribute \src "ls180.v:594.5-594.47" wire \main_sdram_bankmachine1_row_col_n_addr_sel - attribute \src "ls180.v:604.6-604.37" + attribute \src "ls180.v:591.6-591.37" wire \main_sdram_bankmachine1_row_hit - attribute \src "ls180.v:605.5-605.37" + attribute \src "ls180.v:592.5-592.37" wire \main_sdram_bankmachine1_row_open - attribute \src "ls180.v:603.5-603.39" + attribute \src "ls180.v:590.5-590.39" wire \main_sdram_bankmachine1_row_opened attribute \no_retiming "true" - attribute \src "ls180.v:614.32-614.69" + attribute \src "ls180.v:601.32-601.69" wire \main_sdram_bankmachine1_trascon_ready - attribute \src "ls180.v:613.6-613.43" + attribute \src "ls180.v:600.6-600.43" wire \main_sdram_bankmachine1_trascon_valid attribute \no_retiming "true" - attribute \src "ls180.v:612.32-612.68" + attribute \src "ls180.v:599.32-599.68" wire \main_sdram_bankmachine1_trccon_ready - attribute \src "ls180.v:611.6-611.42" + attribute \src "ls180.v:598.6-598.42" wire \main_sdram_bankmachine1_trccon_valid - attribute \src "ls180.v:610.11-610.48" + attribute \src "ls180.v:597.11-597.48" wire width 3 \main_sdram_bankmachine1_twtpcon_count attribute \no_retiming "true" - attribute \src "ls180.v:609.32-609.69" + attribute \src "ls180.v:596.32-596.69" wire \main_sdram_bankmachine1_twtpcon_ready - attribute \src "ls180.v:608.6-608.43" + attribute \src "ls180.v:595.6-595.43" wire \main_sdram_bankmachine1_twtpcon_valid - attribute \src "ls180.v:634.5-634.43" + attribute \src "ls180.v:621.5-621.43" wire \main_sdram_bankmachine2_auto_precharge - attribute \src "ls180.v:656.11-656.63" + attribute \src "ls180.v:643.11-643.63" wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_consume - attribute \src "ls180.v:661.6-661.58" + attribute \src "ls180.v:648.6-648.58" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:666.6-666.64" + attribute \src "ls180.v:653.6-653.64" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first - attribute \src "ls180.v:667.6-667.63" + attribute \src "ls180.v:654.6-654.63" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last - attribute \src "ls180.v:665.13-665.78" + attribute \src "ls180.v:652.13-652.78" wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr - attribute \src "ls180.v:664.6-664.69" + attribute \src "ls180.v:651.6-651.69" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we - attribute \src "ls180.v:670.6-670.65" + attribute \src "ls180.v:657.6-657.65" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first - attribute \src "ls180.v:671.6-671.64" + attribute \src "ls180.v:658.6-658.64" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last - attribute \src "ls180.v:669.13-669.79" + attribute \src "ls180.v:656.13-656.79" wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr - attribute \src "ls180.v:668.6-668.70" + attribute \src "ls180.v:655.6-655.70" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we - attribute \src "ls180.v:653.11-653.61" + attribute \src "ls180.v:640.11-640.61" wire width 4 \main_sdram_bankmachine2_cmd_buffer_lookahead_level - attribute \src "ls180.v:655.11-655.63" + attribute \src "ls180.v:642.11-642.63" wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_produce - attribute \src "ls180.v:662.12-662.67" + attribute \src "ls180.v:649.12-649.67" wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr - attribute \src "ls180.v:663.13-663.70" + attribute \src "ls180.v:650.13-650.70" wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r - attribute \src "ls180.v:654.5-654.57" + attribute \src "ls180.v:641.5-641.57" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_replace - attribute \src "ls180.v:637.5-637.60" + attribute \src "ls180.v:624.5-624.60" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first - attribute \src "ls180.v:638.5-638.59" + attribute \src "ls180.v:625.5-625.59" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last - attribute \src "ls180.v:640.13-640.75" + attribute \src "ls180.v:627.13-627.75" wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr - attribute \src "ls180.v:639.6-639.66" + attribute \src "ls180.v:626.6-626.66" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we - attribute \src "ls180.v:636.6-636.61" + attribute \src "ls180.v:623.6-623.61" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready - attribute \src "ls180.v:635.6-635.61" + attribute \src "ls180.v:622.6-622.61" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid - attribute \src "ls180.v:643.6-643.63" + attribute \src "ls180.v:630.6-630.63" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_first - attribute \src "ls180.v:644.6-644.62" + attribute \src "ls180.v:631.6-631.62" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_last - attribute \src "ls180.v:646.13-646.77" + attribute \src "ls180.v:633.13-633.77" wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr - attribute \src "ls180.v:645.6-645.68" + attribute \src "ls180.v:632.6-632.68" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we - attribute \src "ls180.v:642.6-642.63" + attribute \src "ls180.v:629.6-629.63" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_ready - attribute \src "ls180.v:641.6-641.63" + attribute \src "ls180.v:628.6-628.63" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid - attribute \src "ls180.v:651.13-651.71" + attribute \src "ls180.v:638.13-638.71" wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din - attribute \src "ls180.v:652.13-652.72" + attribute \src "ls180.v:639.13-639.72" wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout - attribute \src "ls180.v:649.6-649.63" + attribute \src "ls180.v:636.6-636.63" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re - attribute \src "ls180.v:650.6-650.69" + attribute \src "ls180.v:637.6-637.69" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable - attribute \src "ls180.v:647.6-647.63" + attribute \src "ls180.v:634.6-634.63" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we - attribute \src "ls180.v:648.6-648.69" + attribute \src "ls180.v:635.6-635.69" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable - attribute \src "ls180.v:657.11-657.66" + attribute \src "ls180.v:644.11-644.66" wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr - attribute \src "ls180.v:658.13-658.70" + attribute \src "ls180.v:645.13-645.70" wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r - attribute \src "ls180.v:660.13-660.70" + attribute \src "ls180.v:647.13-647.70" wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w - attribute \src "ls180.v:659.6-659.60" + attribute \src "ls180.v:646.6-646.60" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:674.6-674.51" + attribute \src "ls180.v:661.6-661.51" wire \main_sdram_bankmachine2_cmd_buffer_sink_first - attribute \src "ls180.v:675.6-675.50" + attribute \src "ls180.v:662.6-662.50" wire \main_sdram_bankmachine2_cmd_buffer_sink_last - attribute \src "ls180.v:677.13-677.65" + attribute \src "ls180.v:664.13-664.65" wire width 22 \main_sdram_bankmachine2_cmd_buffer_sink_payload_addr - attribute \src "ls180.v:676.6-676.56" + attribute \src "ls180.v:663.6-663.56" wire \main_sdram_bankmachine2_cmd_buffer_sink_payload_we - attribute \src "ls180.v:673.6-673.51" + attribute \src "ls180.v:660.6-660.51" wire \main_sdram_bankmachine2_cmd_buffer_sink_ready - attribute \src "ls180.v:672.6-672.51" + attribute \src "ls180.v:659.6-659.51" wire \main_sdram_bankmachine2_cmd_buffer_sink_valid - attribute \src "ls180.v:680.5-680.52" + attribute \src "ls180.v:667.5-667.52" wire \main_sdram_bankmachine2_cmd_buffer_source_first - attribute \src "ls180.v:681.5-681.51" + attribute \src "ls180.v:668.5-668.51" wire \main_sdram_bankmachine2_cmd_buffer_source_last - attribute \src "ls180.v:683.12-683.66" + attribute \src "ls180.v:670.12-670.66" wire width 22 \main_sdram_bankmachine2_cmd_buffer_source_payload_addr - attribute \src "ls180.v:682.5-682.57" + attribute \src "ls180.v:669.5-669.57" wire \main_sdram_bankmachine2_cmd_buffer_source_payload_we - attribute \src "ls180.v:679.6-679.53" + attribute \src "ls180.v:666.6-666.53" wire \main_sdram_bankmachine2_cmd_buffer_source_ready - attribute \src "ls180.v:678.5-678.52" + attribute \src "ls180.v:665.5-665.52" wire \main_sdram_bankmachine2_cmd_buffer_source_valid - attribute \src "ls180.v:626.12-626.49" + attribute \src "ls180.v:613.12-613.49" wire width 13 \main_sdram_bankmachine2_cmd_payload_a - attribute \src "ls180.v:627.12-627.50" + attribute \src "ls180.v:614.12-614.50" wire width 2 \main_sdram_bankmachine2_cmd_payload_ba - attribute \src "ls180.v:628.5-628.44" + attribute \src "ls180.v:615.5-615.44" wire \main_sdram_bankmachine2_cmd_payload_cas - attribute \src "ls180.v:631.5-631.47" + attribute \src "ls180.v:618.5-618.47" wire \main_sdram_bankmachine2_cmd_payload_is_cmd - attribute \src "ls180.v:632.5-632.48" + attribute \src "ls180.v:619.5-619.48" wire \main_sdram_bankmachine2_cmd_payload_is_read - attribute \src "ls180.v:633.5-633.49" + attribute \src "ls180.v:620.5-620.49" wire \main_sdram_bankmachine2_cmd_payload_is_write - attribute \src "ls180.v:629.5-629.44" + attribute \src "ls180.v:616.5-616.44" wire \main_sdram_bankmachine2_cmd_payload_ras - attribute \src "ls180.v:630.5-630.43" + attribute \src "ls180.v:617.5-617.43" wire \main_sdram_bankmachine2_cmd_payload_we - attribute \src "ls180.v:625.5-625.38" + attribute \src "ls180.v:612.5-612.38" wire \main_sdram_bankmachine2_cmd_ready - attribute \src "ls180.v:624.5-624.38" + attribute \src "ls180.v:611.5-611.38" wire \main_sdram_bankmachine2_cmd_valid - attribute \src "ls180.v:623.5-623.40" + attribute \src "ls180.v:610.5-610.40" wire \main_sdram_bankmachine2_refresh_gnt - attribute \src "ls180.v:622.6-622.41" + attribute \src "ls180.v:609.6-609.41" wire \main_sdram_bankmachine2_refresh_req - attribute \src "ls180.v:618.13-618.45" + attribute \src "ls180.v:605.13-605.45" wire width 22 \main_sdram_bankmachine2_req_addr - attribute \src "ls180.v:619.6-619.38" + attribute \src "ls180.v:606.6-606.38" wire \main_sdram_bankmachine2_req_lock - attribute \src "ls180.v:621.5-621.44" + attribute \src "ls180.v:608.5-608.44" wire \main_sdram_bankmachine2_req_rdata_valid - attribute \src "ls180.v:616.6-616.39" + attribute \src "ls180.v:603.6-603.39" wire \main_sdram_bankmachine2_req_ready - attribute \src "ls180.v:615.6-615.39" + attribute \src "ls180.v:602.6-602.39" wire \main_sdram_bankmachine2_req_valid - attribute \src "ls180.v:620.5-620.44" + attribute \src "ls180.v:607.5-607.44" wire \main_sdram_bankmachine2_req_wdata_ready - attribute \src "ls180.v:617.6-617.36" + attribute \src "ls180.v:604.6-604.36" wire \main_sdram_bankmachine2_req_we - attribute \src "ls180.v:684.12-684.39" + attribute \src "ls180.v:671.12-671.39" wire width 13 \main_sdram_bankmachine2_row - attribute \src "ls180.v:688.5-688.38" + attribute \src "ls180.v:675.5-675.38" wire \main_sdram_bankmachine2_row_close - attribute \src "ls180.v:689.5-689.47" + attribute \src "ls180.v:676.5-676.47" wire \main_sdram_bankmachine2_row_col_n_addr_sel - attribute \src "ls180.v:686.6-686.37" + attribute \src "ls180.v:673.6-673.37" wire \main_sdram_bankmachine2_row_hit - attribute \src "ls180.v:687.5-687.37" + attribute \src "ls180.v:674.5-674.37" wire \main_sdram_bankmachine2_row_open - attribute \src "ls180.v:685.5-685.39" + attribute \src "ls180.v:672.5-672.39" wire \main_sdram_bankmachine2_row_opened attribute \no_retiming "true" - attribute \src "ls180.v:696.32-696.69" + attribute \src "ls180.v:683.32-683.69" wire \main_sdram_bankmachine2_trascon_ready - attribute \src "ls180.v:695.6-695.43" + attribute \src "ls180.v:682.6-682.43" wire \main_sdram_bankmachine2_trascon_valid attribute \no_retiming "true" - attribute \src "ls180.v:694.32-694.68" + attribute \src "ls180.v:681.32-681.68" wire \main_sdram_bankmachine2_trccon_ready - attribute \src "ls180.v:693.6-693.42" + attribute \src "ls180.v:680.6-680.42" wire \main_sdram_bankmachine2_trccon_valid - attribute \src "ls180.v:692.11-692.48" + attribute \src "ls180.v:679.11-679.48" wire width 3 \main_sdram_bankmachine2_twtpcon_count attribute \no_retiming "true" - attribute \src "ls180.v:691.32-691.69" + attribute \src "ls180.v:678.32-678.69" wire \main_sdram_bankmachine2_twtpcon_ready - attribute \src "ls180.v:690.6-690.43" + attribute \src "ls180.v:677.6-677.43" wire \main_sdram_bankmachine2_twtpcon_valid - attribute \src "ls180.v:716.5-716.43" + attribute \src "ls180.v:703.5-703.43" wire \main_sdram_bankmachine3_auto_precharge - attribute \src "ls180.v:738.11-738.63" + attribute \src "ls180.v:725.11-725.63" wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_consume - attribute \src "ls180.v:743.6-743.58" + attribute \src "ls180.v:730.6-730.58" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:748.6-748.64" + attribute \src "ls180.v:735.6-735.64" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first - attribute \src "ls180.v:749.6-749.63" + attribute \src "ls180.v:736.6-736.63" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last - attribute \src "ls180.v:747.13-747.78" + attribute \src "ls180.v:734.13-734.78" wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr - attribute \src "ls180.v:746.6-746.69" + attribute \src "ls180.v:733.6-733.69" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we - attribute \src "ls180.v:752.6-752.65" + attribute \src "ls180.v:739.6-739.65" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first - attribute \src "ls180.v:753.6-753.64" + attribute \src "ls180.v:740.6-740.64" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last - attribute \src "ls180.v:751.13-751.79" + attribute \src "ls180.v:738.13-738.79" wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr - attribute \src "ls180.v:750.6-750.70" + attribute \src "ls180.v:737.6-737.70" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we - attribute \src "ls180.v:735.11-735.61" + attribute \src "ls180.v:722.11-722.61" wire width 4 \main_sdram_bankmachine3_cmd_buffer_lookahead_level - attribute \src "ls180.v:737.11-737.63" + attribute \src "ls180.v:724.11-724.63" wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_produce - attribute \src "ls180.v:744.12-744.67" + attribute \src "ls180.v:731.12-731.67" wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr - attribute \src "ls180.v:745.13-745.70" + attribute \src "ls180.v:732.13-732.70" wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r - attribute \src "ls180.v:736.5-736.57" + attribute \src "ls180.v:723.5-723.57" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_replace - attribute \src "ls180.v:719.5-719.60" + attribute \src "ls180.v:706.5-706.60" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first - attribute \src "ls180.v:720.5-720.59" + attribute \src "ls180.v:707.5-707.59" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last - attribute \src "ls180.v:722.13-722.75" + attribute \src "ls180.v:709.13-709.75" wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr - attribute \src "ls180.v:721.6-721.66" + attribute \src "ls180.v:708.6-708.66" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we - attribute \src "ls180.v:718.6-718.61" + attribute \src "ls180.v:705.6-705.61" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready - attribute \src "ls180.v:717.6-717.61" + attribute \src "ls180.v:704.6-704.61" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid - attribute \src "ls180.v:725.6-725.63" + attribute \src "ls180.v:712.6-712.63" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_first - attribute \src "ls180.v:726.6-726.62" + attribute \src "ls180.v:713.6-713.62" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_last - attribute \src "ls180.v:728.13-728.77" + attribute \src "ls180.v:715.13-715.77" wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr - attribute \src "ls180.v:727.6-727.68" + attribute \src "ls180.v:714.6-714.68" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we - attribute \src "ls180.v:724.6-724.63" + attribute \src "ls180.v:711.6-711.63" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_ready - attribute \src "ls180.v:723.6-723.63" + attribute \src "ls180.v:710.6-710.63" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid - attribute \src "ls180.v:733.13-733.71" + attribute \src "ls180.v:720.13-720.71" wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din - attribute \src "ls180.v:734.13-734.72" + attribute \src "ls180.v:721.13-721.72" wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout - attribute \src "ls180.v:731.6-731.63" + attribute \src "ls180.v:718.6-718.63" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re - attribute \src "ls180.v:732.6-732.69" + attribute \src "ls180.v:719.6-719.69" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable - attribute \src "ls180.v:729.6-729.63" + attribute \src "ls180.v:716.6-716.63" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we - attribute \src "ls180.v:730.6-730.69" + attribute \src "ls180.v:717.6-717.69" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable - attribute \src "ls180.v:739.11-739.66" + attribute \src "ls180.v:726.11-726.66" wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr - attribute \src "ls180.v:740.13-740.70" + attribute \src "ls180.v:727.13-727.70" wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r - attribute \src "ls180.v:742.13-742.70" + attribute \src "ls180.v:729.13-729.70" wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w - attribute \src "ls180.v:741.6-741.60" + attribute \src "ls180.v:728.6-728.60" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:756.6-756.51" + attribute \src "ls180.v:743.6-743.51" wire \main_sdram_bankmachine3_cmd_buffer_sink_first - attribute \src "ls180.v:757.6-757.50" + attribute \src "ls180.v:744.6-744.50" wire \main_sdram_bankmachine3_cmd_buffer_sink_last - attribute \src "ls180.v:759.13-759.65" + attribute \src "ls180.v:746.13-746.65" wire width 22 \main_sdram_bankmachine3_cmd_buffer_sink_payload_addr - attribute \src "ls180.v:758.6-758.56" + attribute \src "ls180.v:745.6-745.56" wire \main_sdram_bankmachine3_cmd_buffer_sink_payload_we - attribute \src "ls180.v:755.6-755.51" + attribute \src "ls180.v:742.6-742.51" wire \main_sdram_bankmachine3_cmd_buffer_sink_ready - attribute \src "ls180.v:754.6-754.51" + attribute \src "ls180.v:741.6-741.51" wire \main_sdram_bankmachine3_cmd_buffer_sink_valid - attribute \src "ls180.v:762.5-762.52" + attribute \src "ls180.v:749.5-749.52" wire \main_sdram_bankmachine3_cmd_buffer_source_first - attribute \src "ls180.v:763.5-763.51" + attribute \src "ls180.v:750.5-750.51" wire \main_sdram_bankmachine3_cmd_buffer_source_last - attribute \src "ls180.v:765.12-765.66" + attribute \src "ls180.v:752.12-752.66" wire width 22 \main_sdram_bankmachine3_cmd_buffer_source_payload_addr - attribute \src "ls180.v:764.5-764.57" + attribute \src "ls180.v:751.5-751.57" wire \main_sdram_bankmachine3_cmd_buffer_source_payload_we - attribute \src "ls180.v:761.6-761.53" + attribute \src "ls180.v:748.6-748.53" wire \main_sdram_bankmachine3_cmd_buffer_source_ready - attribute \src "ls180.v:760.5-760.52" + attribute \src "ls180.v:747.5-747.52" wire \main_sdram_bankmachine3_cmd_buffer_source_valid - attribute \src "ls180.v:708.12-708.49" + attribute \src "ls180.v:695.12-695.49" wire width 13 \main_sdram_bankmachine3_cmd_payload_a - attribute \src "ls180.v:709.12-709.50" + attribute \src "ls180.v:696.12-696.50" wire width 2 \main_sdram_bankmachine3_cmd_payload_ba - attribute \src "ls180.v:710.5-710.44" + attribute \src "ls180.v:697.5-697.44" wire \main_sdram_bankmachine3_cmd_payload_cas - attribute \src "ls180.v:713.5-713.47" + attribute \src "ls180.v:700.5-700.47" wire \main_sdram_bankmachine3_cmd_payload_is_cmd - attribute \src "ls180.v:714.5-714.48" + attribute \src "ls180.v:701.5-701.48" wire \main_sdram_bankmachine3_cmd_payload_is_read - attribute \src "ls180.v:715.5-715.49" + attribute \src "ls180.v:702.5-702.49" wire \main_sdram_bankmachine3_cmd_payload_is_write - attribute \src "ls180.v:711.5-711.44" + attribute \src "ls180.v:698.5-698.44" wire \main_sdram_bankmachine3_cmd_payload_ras - attribute \src "ls180.v:712.5-712.43" + attribute \src "ls180.v:699.5-699.43" wire \main_sdram_bankmachine3_cmd_payload_we - attribute \src "ls180.v:707.5-707.38" + attribute \src "ls180.v:694.5-694.38" wire \main_sdram_bankmachine3_cmd_ready - attribute \src "ls180.v:706.5-706.38" + attribute \src "ls180.v:693.5-693.38" wire \main_sdram_bankmachine3_cmd_valid - attribute \src "ls180.v:705.5-705.40" + attribute \src "ls180.v:692.5-692.40" wire \main_sdram_bankmachine3_refresh_gnt - attribute \src "ls180.v:704.6-704.41" + attribute \src "ls180.v:691.6-691.41" wire \main_sdram_bankmachine3_refresh_req - attribute \src "ls180.v:700.13-700.45" + attribute \src "ls180.v:687.13-687.45" wire width 22 \main_sdram_bankmachine3_req_addr - attribute \src "ls180.v:701.6-701.38" + attribute \src "ls180.v:688.6-688.38" wire \main_sdram_bankmachine3_req_lock - attribute \src "ls180.v:703.5-703.44" + attribute \src "ls180.v:690.5-690.44" wire \main_sdram_bankmachine3_req_rdata_valid - attribute \src "ls180.v:698.6-698.39" + attribute \src "ls180.v:685.6-685.39" wire \main_sdram_bankmachine3_req_ready - attribute \src "ls180.v:697.6-697.39" + attribute \src "ls180.v:684.6-684.39" wire \main_sdram_bankmachine3_req_valid - attribute \src "ls180.v:702.5-702.44" + attribute \src "ls180.v:689.5-689.44" wire \main_sdram_bankmachine3_req_wdata_ready - attribute \src "ls180.v:699.6-699.36" + attribute \src "ls180.v:686.6-686.36" wire \main_sdram_bankmachine3_req_we - attribute \src "ls180.v:766.12-766.39" + attribute \src "ls180.v:753.12-753.39" wire width 13 \main_sdram_bankmachine3_row - attribute \src "ls180.v:770.5-770.38" + attribute \src "ls180.v:757.5-757.38" wire \main_sdram_bankmachine3_row_close - attribute \src "ls180.v:771.5-771.47" + attribute \src "ls180.v:758.5-758.47" wire \main_sdram_bankmachine3_row_col_n_addr_sel - attribute \src "ls180.v:768.6-768.37" + attribute \src "ls180.v:755.6-755.37" wire \main_sdram_bankmachine3_row_hit - attribute \src "ls180.v:769.5-769.37" + attribute \src "ls180.v:756.5-756.37" wire \main_sdram_bankmachine3_row_open - attribute \src "ls180.v:767.5-767.39" + attribute \src "ls180.v:754.5-754.39" wire \main_sdram_bankmachine3_row_opened attribute \no_retiming "true" - attribute \src "ls180.v:778.32-778.69" + attribute \src "ls180.v:765.32-765.69" wire \main_sdram_bankmachine3_trascon_ready - attribute \src "ls180.v:777.6-777.43" + attribute \src "ls180.v:764.6-764.43" wire \main_sdram_bankmachine3_trascon_valid attribute \no_retiming "true" - attribute \src "ls180.v:776.32-776.68" + attribute \src "ls180.v:763.32-763.68" wire \main_sdram_bankmachine3_trccon_ready - attribute \src "ls180.v:775.6-775.42" + attribute \src "ls180.v:762.6-762.42" wire \main_sdram_bankmachine3_trccon_valid - attribute \src "ls180.v:774.11-774.48" + attribute \src "ls180.v:761.11-761.48" wire width 3 \main_sdram_bankmachine3_twtpcon_count attribute \no_retiming "true" - attribute \src "ls180.v:773.32-773.69" + attribute \src "ls180.v:760.32-760.69" wire \main_sdram_bankmachine3_twtpcon_ready - attribute \src "ls180.v:772.6-772.43" + attribute \src "ls180.v:759.6-759.43" wire \main_sdram_bankmachine3_twtpcon_valid - attribute \src "ls180.v:780.6-780.28" + attribute \src "ls180.v:767.6-767.28" wire \main_sdram_cas_allowed - attribute \src "ls180.v:798.6-798.30" + attribute \src "ls180.v:785.6-785.30" wire \main_sdram_choose_cmd_ce - attribute \src "ls180.v:787.13-787.48" + attribute \src "ls180.v:774.13-774.48" wire width 13 \main_sdram_choose_cmd_cmd_payload_a - attribute \src "ls180.v:788.12-788.48" + attribute \src "ls180.v:775.12-775.48" wire width 2 \main_sdram_choose_cmd_cmd_payload_ba - attribute \src "ls180.v:789.5-789.42" + attribute \src "ls180.v:776.5-776.42" wire \main_sdram_choose_cmd_cmd_payload_cas - attribute \src "ls180.v:792.6-792.46" + attribute \src "ls180.v:779.6-779.46" wire \main_sdram_choose_cmd_cmd_payload_is_cmd - attribute \src "ls180.v:793.6-793.47" + attribute \src "ls180.v:780.6-780.47" wire \main_sdram_choose_cmd_cmd_payload_is_read - attribute \src "ls180.v:794.6-794.48" + attribute \src "ls180.v:781.6-781.48" wire \main_sdram_choose_cmd_cmd_payload_is_write - attribute \src "ls180.v:790.5-790.42" + attribute \src "ls180.v:777.5-777.42" wire \main_sdram_choose_cmd_cmd_payload_ras - attribute \src "ls180.v:791.5-791.41" + attribute \src "ls180.v:778.5-778.41" wire \main_sdram_choose_cmd_cmd_payload_we - attribute \src "ls180.v:786.5-786.36" + attribute \src "ls180.v:773.5-773.36" wire \main_sdram_choose_cmd_cmd_ready - attribute \src "ls180.v:785.6-785.37" + attribute \src "ls180.v:772.6-772.37" wire \main_sdram_choose_cmd_cmd_valid - attribute \src "ls180.v:797.11-797.38" + attribute \src "ls180.v:784.11-784.38" wire width 2 \main_sdram_choose_cmd_grant - attribute \src "ls180.v:796.12-796.41" + attribute \src "ls180.v:783.12-783.41" wire width 4 \main_sdram_choose_cmd_request - attribute \src "ls180.v:795.11-795.39" + attribute \src "ls180.v:782.11-782.39" wire width 4 \main_sdram_choose_cmd_valids - attribute \src "ls180.v:784.5-784.41" + attribute \src "ls180.v:771.5-771.41" wire \main_sdram_choose_cmd_want_activates - attribute \src "ls180.v:783.5-783.36" + attribute \src "ls180.v:770.5-770.36" wire \main_sdram_choose_cmd_want_cmds - attribute \src "ls180.v:781.5-781.37" + attribute \src "ls180.v:768.5-768.37" wire \main_sdram_choose_cmd_want_reads - attribute \src "ls180.v:782.5-782.38" + attribute \src "ls180.v:769.5-769.38" wire \main_sdram_choose_cmd_want_writes - attribute \src "ls180.v:816.6-816.30" + attribute \src "ls180.v:803.6-803.30" wire \main_sdram_choose_req_ce - attribute \src "ls180.v:805.13-805.48" + attribute \src "ls180.v:792.13-792.48" wire width 13 \main_sdram_choose_req_cmd_payload_a - attribute \src "ls180.v:806.12-806.48" + attribute \src "ls180.v:793.12-793.48" wire width 2 \main_sdram_choose_req_cmd_payload_ba - attribute \src "ls180.v:807.5-807.42" + attribute \src "ls180.v:794.5-794.42" wire \main_sdram_choose_req_cmd_payload_cas - attribute \src "ls180.v:810.6-810.46" + attribute \src "ls180.v:797.6-797.46" wire \main_sdram_choose_req_cmd_payload_is_cmd - attribute \src "ls180.v:811.6-811.47" + attribute \src "ls180.v:798.6-798.47" wire \main_sdram_choose_req_cmd_payload_is_read - attribute \src "ls180.v:812.6-812.48" + attribute \src "ls180.v:799.6-799.48" wire \main_sdram_choose_req_cmd_payload_is_write - attribute \src "ls180.v:808.5-808.42" + attribute \src "ls180.v:795.5-795.42" wire \main_sdram_choose_req_cmd_payload_ras - attribute \src "ls180.v:809.5-809.41" + attribute \src "ls180.v:796.5-796.41" wire \main_sdram_choose_req_cmd_payload_we - attribute \src "ls180.v:804.5-804.36" + attribute \src "ls180.v:791.5-791.36" wire \main_sdram_choose_req_cmd_ready - attribute \src "ls180.v:803.6-803.37" + attribute \src "ls180.v:790.6-790.37" wire \main_sdram_choose_req_cmd_valid - attribute \src "ls180.v:815.11-815.38" + attribute \src "ls180.v:802.11-802.38" wire width 2 \main_sdram_choose_req_grant - attribute \src "ls180.v:814.12-814.41" + attribute \src "ls180.v:801.12-801.41" wire width 4 \main_sdram_choose_req_request - attribute \src "ls180.v:813.11-813.39" + attribute \src "ls180.v:800.11-800.39" wire width 4 \main_sdram_choose_req_valids - attribute \src "ls180.v:802.5-802.41" + attribute \src "ls180.v:789.5-789.41" wire \main_sdram_choose_req_want_activates - attribute \src "ls180.v:801.6-801.37" + attribute \src "ls180.v:788.6-788.37" wire \main_sdram_choose_req_want_cmds - attribute \src "ls180.v:799.5-799.37" + attribute \src "ls180.v:786.5-786.37" wire \main_sdram_choose_req_want_reads - attribute \src "ls180.v:800.5-800.38" + attribute \src "ls180.v:787.5-787.38" wire \main_sdram_choose_req_want_writes - attribute \src "ls180.v:360.6-360.20" + attribute \src "ls180.v:347.6-347.20" wire \main_sdram_cke - attribute \src "ls180.v:428.5-428.24" + attribute \src "ls180.v:415.5-415.24" wire \main_sdram_cmd_last - attribute \src "ls180.v:429.12-429.36" + attribute \src "ls180.v:416.12-416.36" wire width 13 \main_sdram_cmd_payload_a - attribute \src "ls180.v:430.11-430.36" + attribute \src "ls180.v:417.11-417.36" wire width 2 \main_sdram_cmd_payload_ba - attribute \src "ls180.v:431.5-431.31" + attribute \src "ls180.v:418.5-418.31" wire \main_sdram_cmd_payload_cas - attribute \src "ls180.v:434.5-434.35" + attribute \src "ls180.v:421.5-421.35" wire \main_sdram_cmd_payload_is_read - attribute \src "ls180.v:435.5-435.36" + attribute \src "ls180.v:422.5-422.36" wire \main_sdram_cmd_payload_is_write - attribute \src "ls180.v:432.5-432.31" + attribute \src "ls180.v:419.5-419.31" wire \main_sdram_cmd_payload_ras - attribute \src "ls180.v:433.5-433.30" + attribute \src "ls180.v:420.5-420.30" wire \main_sdram_cmd_payload_we - attribute \src "ls180.v:427.5-427.25" + attribute \src "ls180.v:414.5-414.25" wire \main_sdram_cmd_ready - attribute \src "ls180.v:426.5-426.25" + attribute \src "ls180.v:413.5-413.25" wire \main_sdram_cmd_valid - attribute \src "ls180.v:368.6-368.32" + attribute \src "ls180.v:355.6-355.32" wire \main_sdram_command_issue_r - attribute \src "ls180.v:367.6-367.33" + attribute \src "ls180.v:354.6-354.33" wire \main_sdram_command_issue_re - attribute \src "ls180.v:370.5-370.31" + attribute \src "ls180.v:357.5-357.31" wire \main_sdram_command_issue_w - attribute \src "ls180.v:369.6-369.33" + attribute \src "ls180.v:356.6-356.33" wire \main_sdram_command_issue_we - attribute \src "ls180.v:366.5-366.26" + attribute \src "ls180.v:353.5-353.26" wire \main_sdram_command_re - attribute \src "ls180.v:365.11-365.37" + attribute \src "ls180.v:352.11-352.37" wire width 6 \main_sdram_command_storage - attribute \src "ls180.v:419.5-419.28" + attribute \src "ls180.v:406.5-406.28" wire \main_sdram_dfi_p0_act_n - attribute \src "ls180.v:410.12-410.37" + attribute \src "ls180.v:397.12-397.37" wire width 13 \main_sdram_dfi_p0_address - attribute \src "ls180.v:411.11-411.33" + attribute \src "ls180.v:398.11-398.33" wire width 2 \main_sdram_dfi_p0_bank - attribute \src "ls180.v:412.5-412.28" + attribute \src "ls180.v:399.5-399.28" wire \main_sdram_dfi_p0_cas_n - attribute \src "ls180.v:416.6-416.27" + attribute \src "ls180.v:403.6-403.27" wire \main_sdram_dfi_p0_cke - attribute \src "ls180.v:413.5-413.27" + attribute \src "ls180.v:400.5-400.27" wire \main_sdram_dfi_p0_cs_n - attribute \src "ls180.v:417.6-417.27" + attribute \src "ls180.v:404.6-404.27" wire \main_sdram_dfi_p0_odt - attribute \src "ls180.v:414.5-414.28" + attribute \src "ls180.v:401.5-401.28" wire \main_sdram_dfi_p0_ras_n - attribute \src "ls180.v:424.13-424.37" + attribute \src "ls180.v:411.13-411.37" wire width 16 \main_sdram_dfi_p0_rddata - attribute \src "ls180.v:423.5-423.32" + attribute \src "ls180.v:410.5-410.32" wire \main_sdram_dfi_p0_rddata_en - attribute \src "ls180.v:425.6-425.36" + attribute \src "ls180.v:412.6-412.36" wire \main_sdram_dfi_p0_rddata_valid - attribute \src "ls180.v:418.6-418.31" + attribute \src "ls180.v:405.6-405.31" wire \main_sdram_dfi_p0_reset_n - attribute \src "ls180.v:415.5-415.27" + attribute \src "ls180.v:402.5-402.27" wire \main_sdram_dfi_p0_we_n - attribute \src "ls180.v:420.13-420.37" + attribute \src "ls180.v:407.13-407.37" wire width 16 \main_sdram_dfi_p0_wrdata - attribute \src "ls180.v:421.5-421.32" + attribute \src "ls180.v:408.5-408.32" wire \main_sdram_dfi_p0_wrdata_en - attribute \src "ls180.v:422.12-422.41" + attribute \src "ls180.v:409.12-409.41" wire width 2 \main_sdram_dfi_p0_wrdata_mask - attribute \src "ls180.v:834.5-834.19" + attribute \src "ls180.v:821.5-821.19" wire \main_sdram_en0 - attribute \src "ls180.v:837.5-837.19" + attribute \src "ls180.v:824.5-824.19" wire \main_sdram_en1 - attribute \src "ls180.v:840.6-840.30" + attribute \src "ls180.v:827.6-827.30" wire \main_sdram_go_to_refresh - attribute \src "ls180.v:382.13-382.44" + attribute \src "ls180.v:369.13-369.44" wire width 22 \main_sdram_interface_bank0_addr - attribute \src "ls180.v:383.6-383.37" + attribute \src "ls180.v:370.6-370.37" wire \main_sdram_interface_bank0_lock - attribute \src "ls180.v:385.6-385.44" + attribute \src "ls180.v:372.6-372.44" wire \main_sdram_interface_bank0_rdata_valid - attribute \src "ls180.v:380.6-380.38" + attribute \src "ls180.v:367.6-367.38" wire \main_sdram_interface_bank0_ready - attribute \src "ls180.v:379.6-379.38" + attribute \src "ls180.v:366.6-366.38" wire \main_sdram_interface_bank0_valid - attribute \src "ls180.v:384.6-384.44" + attribute \src "ls180.v:371.6-371.44" wire \main_sdram_interface_bank0_wdata_ready - attribute \src "ls180.v:381.6-381.35" + attribute \src "ls180.v:368.6-368.35" wire \main_sdram_interface_bank0_we - attribute \src "ls180.v:389.13-389.44" + attribute \src "ls180.v:376.13-376.44" wire width 22 \main_sdram_interface_bank1_addr - attribute \src "ls180.v:390.6-390.37" + attribute \src "ls180.v:377.6-377.37" wire \main_sdram_interface_bank1_lock - attribute \src "ls180.v:392.6-392.44" + attribute \src "ls180.v:379.6-379.44" wire \main_sdram_interface_bank1_rdata_valid - attribute \src "ls180.v:387.6-387.38" + attribute \src "ls180.v:374.6-374.38" wire \main_sdram_interface_bank1_ready - attribute \src "ls180.v:386.6-386.38" + attribute \src "ls180.v:373.6-373.38" wire \main_sdram_interface_bank1_valid - attribute \src "ls180.v:391.6-391.44" + attribute \src "ls180.v:378.6-378.44" wire \main_sdram_interface_bank1_wdata_ready - attribute \src "ls180.v:388.6-388.35" + attribute \src "ls180.v:375.6-375.35" wire \main_sdram_interface_bank1_we - attribute \src "ls180.v:396.13-396.44" + attribute \src "ls180.v:383.13-383.44" wire width 22 \main_sdram_interface_bank2_addr - attribute \src "ls180.v:397.6-397.37" + attribute \src "ls180.v:384.6-384.37" wire \main_sdram_interface_bank2_lock - attribute \src "ls180.v:399.6-399.44" + attribute \src "ls180.v:386.6-386.44" wire \main_sdram_interface_bank2_rdata_valid - attribute \src "ls180.v:394.6-394.38" + attribute \src "ls180.v:381.6-381.38" wire \main_sdram_interface_bank2_ready - attribute \src "ls180.v:393.6-393.38" + attribute \src "ls180.v:380.6-380.38" wire \main_sdram_interface_bank2_valid - attribute \src "ls180.v:398.6-398.44" + attribute \src "ls180.v:385.6-385.44" wire \main_sdram_interface_bank2_wdata_ready - attribute \src "ls180.v:395.6-395.35" + attribute \src "ls180.v:382.6-382.35" wire \main_sdram_interface_bank2_we - attribute \src "ls180.v:403.13-403.44" + attribute \src "ls180.v:390.13-390.44" wire width 22 \main_sdram_interface_bank3_addr - attribute \src "ls180.v:404.6-404.37" + attribute \src "ls180.v:391.6-391.37" wire \main_sdram_interface_bank3_lock - attribute \src "ls180.v:406.6-406.44" + attribute \src "ls180.v:393.6-393.44" wire \main_sdram_interface_bank3_rdata_valid - attribute \src "ls180.v:401.6-401.38" + attribute \src "ls180.v:388.6-388.38" wire \main_sdram_interface_bank3_ready - attribute \src "ls180.v:400.6-400.38" + attribute \src "ls180.v:387.6-387.38" wire \main_sdram_interface_bank3_valid - attribute \src "ls180.v:405.6-405.44" + attribute \src "ls180.v:392.6-392.44" wire \main_sdram_interface_bank3_wdata_ready - attribute \src "ls180.v:402.6-402.35" + attribute \src "ls180.v:389.6-389.35" wire \main_sdram_interface_bank3_we - attribute \src "ls180.v:409.13-409.39" + attribute \src "ls180.v:396.13-396.39" wire width 16 \main_sdram_interface_rdata - attribute \src "ls180.v:407.12-407.38" + attribute \src "ls180.v:394.12-394.38" wire width 16 \main_sdram_interface_wdata - attribute \src "ls180.v:408.11-408.40" + attribute \src "ls180.v:395.11-395.40" wire width 2 \main_sdram_interface_wdata_we - attribute \src "ls180.v:320.5-320.29" + attribute \src "ls180.v:307.5-307.29" wire \main_sdram_inti_p0_act_n - attribute \src "ls180.v:311.13-311.39" + attribute \src "ls180.v:298.13-298.39" wire width 13 \main_sdram_inti_p0_address - attribute \src "ls180.v:312.12-312.35" + attribute \src "ls180.v:299.12-299.35" wire width 2 \main_sdram_inti_p0_bank - attribute \src "ls180.v:313.5-313.29" + attribute \src "ls180.v:300.5-300.29" wire \main_sdram_inti_p0_cas_n - attribute \src "ls180.v:317.6-317.28" + attribute \src "ls180.v:304.6-304.28" wire \main_sdram_inti_p0_cke - attribute \src "ls180.v:314.5-314.28" + attribute \src "ls180.v:301.5-301.28" wire \main_sdram_inti_p0_cs_n - attribute \src "ls180.v:318.6-318.28" + attribute \src "ls180.v:305.6-305.28" wire \main_sdram_inti_p0_odt - attribute \src "ls180.v:315.5-315.29" + attribute \src "ls180.v:302.5-302.29" wire \main_sdram_inti_p0_ras_n - attribute \src "ls180.v:325.12-325.37" + attribute \src "ls180.v:312.12-312.37" wire width 16 \main_sdram_inti_p0_rddata - attribute \src "ls180.v:324.6-324.34" + attribute \src "ls180.v:311.6-311.34" wire \main_sdram_inti_p0_rddata_en - attribute \src "ls180.v:326.5-326.36" + attribute \src "ls180.v:313.5-313.36" wire \main_sdram_inti_p0_rddata_valid - attribute \src "ls180.v:319.6-319.32" + attribute \src "ls180.v:306.6-306.32" wire \main_sdram_inti_p0_reset_n - attribute \src "ls180.v:316.5-316.28" + attribute \src "ls180.v:303.5-303.28" wire \main_sdram_inti_p0_we_n - attribute \src "ls180.v:321.13-321.38" + attribute \src "ls180.v:308.13-308.38" wire width 16 \main_sdram_inti_p0_wrdata - attribute \src "ls180.v:322.6-322.34" + attribute \src "ls180.v:309.6-309.34" wire \main_sdram_inti_p0_wrdata_en - attribute \src "ls180.v:323.12-323.42" + attribute \src "ls180.v:310.12-310.42" wire width 2 \main_sdram_inti_p0_wrdata_mask - attribute \src "ls180.v:352.5-352.31" + attribute \src "ls180.v:339.5-339.31" wire \main_sdram_master_p0_act_n - attribute \src "ls180.v:343.12-343.40" + attribute \src "ls180.v:330.12-330.40" wire width 13 \main_sdram_master_p0_address - attribute \src "ls180.v:344.11-344.36" + attribute \src "ls180.v:331.11-331.36" wire width 2 \main_sdram_master_p0_bank - attribute \src "ls180.v:345.5-345.31" + attribute \src "ls180.v:332.5-332.31" wire \main_sdram_master_p0_cas_n - attribute \src "ls180.v:349.5-349.29" + attribute \src "ls180.v:336.5-336.29" wire \main_sdram_master_p0_cke - attribute \src "ls180.v:346.5-346.30" + attribute \src "ls180.v:333.5-333.30" wire \main_sdram_master_p0_cs_n - attribute \src "ls180.v:350.5-350.29" + attribute \src "ls180.v:337.5-337.29" wire \main_sdram_master_p0_odt - attribute \src "ls180.v:347.5-347.31" + attribute \src "ls180.v:334.5-334.31" wire \main_sdram_master_p0_ras_n - attribute \src "ls180.v:357.13-357.40" + attribute \src "ls180.v:344.13-344.40" wire width 16 \main_sdram_master_p0_rddata - attribute \src "ls180.v:356.5-356.35" + attribute \src "ls180.v:343.5-343.35" wire \main_sdram_master_p0_rddata_en - attribute \src "ls180.v:358.6-358.39" + attribute \src "ls180.v:345.6-345.39" wire \main_sdram_master_p0_rddata_valid - attribute \src "ls180.v:351.5-351.33" + attribute \src "ls180.v:338.5-338.33" wire \main_sdram_master_p0_reset_n - attribute \src "ls180.v:348.5-348.30" + attribute \src "ls180.v:335.5-335.30" wire \main_sdram_master_p0_we_n - attribute \src "ls180.v:353.12-353.39" + attribute \src "ls180.v:340.12-340.39" wire width 16 \main_sdram_master_p0_wrdata - attribute \src "ls180.v:354.5-354.35" + attribute \src "ls180.v:341.5-341.35" wire \main_sdram_master_p0_wrdata_en - attribute \src "ls180.v:355.11-355.43" + attribute \src "ls180.v:342.11-342.43" wire width 2 \main_sdram_master_p0_wrdata_mask - attribute \src "ls180.v:835.6-835.26" + attribute \src "ls180.v:822.6-822.26" wire \main_sdram_max_time0 - attribute \src "ls180.v:838.6-838.26" + attribute \src "ls180.v:825.6-825.26" wire \main_sdram_max_time1 - attribute \src "ls180.v:817.12-817.28" + attribute \src "ls180.v:804.12-804.28" wire width 13 \main_sdram_nop_a - attribute \src "ls180.v:818.11-818.28" + attribute \src "ls180.v:805.11-805.28" wire width 2 \main_sdram_nop_ba - attribute \src "ls180.v:361.6-361.20" + attribute \src "ls180.v:348.6-348.20" wire \main_sdram_odt - attribute \src "ls180.v:444.5-444.31" + attribute \src "ls180.v:431.5-431.31" wire \main_sdram_postponer_count - attribute \src "ls180.v:442.6-442.32" + attribute \src "ls180.v:429.6-429.32" wire \main_sdram_postponer_req_i - attribute \src "ls180.v:443.5-443.31" + attribute \src "ls180.v:430.5-430.31" wire \main_sdram_postponer_req_o - attribute \src "ls180.v:779.6-779.28" + attribute \src "ls180.v:766.6-766.28" wire \main_sdram_ras_allowed - attribute \src "ls180.v:364.5-364.18" + attribute \src "ls180.v:351.5-351.18" wire \main_sdram_re - attribute \src "ls180.v:832.6-832.31" + attribute \src "ls180.v:819.6-819.31" wire \main_sdram_read_available - attribute \src "ls180.v:362.6-362.24" + attribute \src "ls180.v:349.6-349.24" wire \main_sdram_reset_n - attribute \src "ls180.v:359.6-359.20" + attribute \src "ls180.v:346.6-346.20" wire \main_sdram_sel - attribute \src "ls180.v:450.5-450.31" + attribute \src "ls180.v:437.5-437.31" wire \main_sdram_sequencer_count - attribute \src "ls180.v:449.11-449.39" + attribute \src "ls180.v:436.11-436.39" wire width 4 \main_sdram_sequencer_counter - attribute \src "ls180.v:446.6-446.32" + attribute \src "ls180.v:433.6-433.32" wire \main_sdram_sequencer_done0 - attribute \src "ls180.v:448.5-448.31" + attribute \src "ls180.v:435.5-435.31" wire \main_sdram_sequencer_done1 - attribute \src "ls180.v:445.5-445.32" + attribute \src "ls180.v:432.5-432.32" wire \main_sdram_sequencer_start0 - attribute \src "ls180.v:447.6-447.33" + attribute \src "ls180.v:434.6-434.33" wire \main_sdram_sequencer_start1 - attribute \src "ls180.v:336.6-336.31" + attribute \src "ls180.v:323.6-323.31" wire \main_sdram_slave_p0_act_n - attribute \src "ls180.v:327.13-327.40" + attribute \src "ls180.v:314.13-314.40" wire width 13 \main_sdram_slave_p0_address - attribute \src "ls180.v:328.12-328.36" + attribute \src "ls180.v:315.12-315.36" wire width 2 \main_sdram_slave_p0_bank - attribute \src "ls180.v:329.6-329.31" + attribute \src "ls180.v:316.6-316.31" wire \main_sdram_slave_p0_cas_n - attribute \src "ls180.v:333.6-333.29" + attribute \src "ls180.v:320.6-320.29" wire \main_sdram_slave_p0_cke - attribute \src "ls180.v:330.6-330.30" + attribute \src "ls180.v:317.6-317.30" wire \main_sdram_slave_p0_cs_n - attribute \src "ls180.v:334.6-334.29" + attribute \src "ls180.v:321.6-321.29" wire \main_sdram_slave_p0_odt - attribute \src "ls180.v:331.6-331.31" + attribute \src "ls180.v:318.6-318.31" wire \main_sdram_slave_p0_ras_n - attribute \src "ls180.v:341.12-341.38" + attribute \src "ls180.v:328.12-328.38" wire width 16 \main_sdram_slave_p0_rddata - attribute \src "ls180.v:340.6-340.35" + attribute \src "ls180.v:327.6-327.35" wire \main_sdram_slave_p0_rddata_en - attribute \src "ls180.v:342.5-342.37" + attribute \src "ls180.v:329.5-329.37" wire \main_sdram_slave_p0_rddata_valid - attribute \src "ls180.v:335.6-335.33" + attribute \src "ls180.v:322.6-322.33" wire \main_sdram_slave_p0_reset_n - attribute \src "ls180.v:332.6-332.30" + attribute \src "ls180.v:319.6-319.30" wire \main_sdram_slave_p0_we_n - attribute \src "ls180.v:337.13-337.39" + attribute \src "ls180.v:324.13-324.39" wire width 16 \main_sdram_slave_p0_wrdata - attribute \src "ls180.v:338.6-338.35" + attribute \src "ls180.v:325.6-325.35" wire \main_sdram_slave_p0_wrdata_en - attribute \src "ls180.v:339.12-339.43" + attribute \src "ls180.v:326.12-326.43" wire width 2 \main_sdram_slave_p0_wrdata_mask - attribute \src "ls180.v:377.12-377.29" + attribute \src "ls180.v:364.12-364.29" wire width 16 \main_sdram_status - attribute \src "ls180.v:820.5-820.24" + attribute \src "ls180.v:807.5-807.24" wire \main_sdram_steerer0 - attribute \src "ls180.v:821.5-821.24" + attribute \src "ls180.v:808.5-808.24" wire \main_sdram_steerer1 - attribute \src "ls180.v:819.11-819.33" + attribute \src "ls180.v:806.11-806.33" wire width 2 \main_sdram_steerer_sel - attribute \src "ls180.v:363.11-363.29" + attribute \src "ls180.v:350.11-350.29" wire width 4 \main_sdram_storage - attribute \src "ls180.v:828.5-828.29" + attribute \src "ls180.v:815.5-815.29" wire \main_sdram_tccdcon_count attribute \no_retiming "true" - attribute \src "ls180.v:827.32-827.56" + attribute \src "ls180.v:814.32-814.56" wire \main_sdram_tccdcon_ready - attribute \src "ls180.v:826.6-826.30" + attribute \src "ls180.v:813.6-813.30" wire \main_sdram_tccdcon_valid attribute \no_retiming "true" - attribute \src "ls180.v:825.32-825.56" + attribute \src "ls180.v:812.32-812.56" wire \main_sdram_tfawcon_ready - attribute \src "ls180.v:824.6-824.30" + attribute \src "ls180.v:811.6-811.30" wire \main_sdram_tfawcon_valid - attribute \src "ls180.v:836.11-836.27" + attribute \src "ls180.v:823.11-823.27" wire width 5 \main_sdram_time0 - attribute \src "ls180.v:839.11-839.27" + attribute \src "ls180.v:826.11-826.27" wire width 4 \main_sdram_time1 - attribute \src "ls180.v:439.12-439.35" + attribute \src "ls180.v:426.12-426.35" wire width 10 \main_sdram_timer_count0 - attribute \src "ls180.v:441.11-441.34" + attribute \src "ls180.v:428.11-428.34" wire width 10 \main_sdram_timer_count1 - attribute \src "ls180.v:438.6-438.28" + attribute \src "ls180.v:425.6-425.28" wire \main_sdram_timer_done0 - attribute \src "ls180.v:440.6-440.28" + attribute \src "ls180.v:427.6-427.28" wire \main_sdram_timer_done1 - attribute \src "ls180.v:437.6-437.27" + attribute \src "ls180.v:424.6-424.27" wire \main_sdram_timer_wait attribute \no_retiming "true" - attribute \src "ls180.v:823.32-823.56" + attribute \src "ls180.v:810.32-810.56" wire \main_sdram_trrdcon_ready - attribute \src "ls180.v:822.6-822.30" + attribute \src "ls180.v:809.6-809.30" wire \main_sdram_trrdcon_valid - attribute \src "ls180.v:831.11-831.35" + attribute \src "ls180.v:818.11-818.35" wire width 3 \main_sdram_twtrcon_count attribute \no_retiming "true" - attribute \src "ls180.v:830.32-830.56" + attribute \src "ls180.v:817.32-817.56" wire \main_sdram_twtrcon_ready - attribute \src "ls180.v:829.6-829.30" + attribute \src "ls180.v:816.6-816.30" wire \main_sdram_twtrcon_valid - attribute \src "ls180.v:436.6-436.30" + attribute \src "ls180.v:423.6-423.30" wire \main_sdram_wants_refresh - attribute \src "ls180.v:378.6-378.19" + attribute \src "ls180.v:365.6-365.19" wire \main_sdram_we - attribute \src "ls180.v:376.5-376.25" + attribute \src "ls180.v:363.5-363.25" wire \main_sdram_wrdata_re - attribute \src "ls180.v:375.12-375.37" + attribute \src "ls180.v:362.12-362.37" wire width 16 \main_sdram_wrdata_storage - attribute \src "ls180.v:833.6-833.32" + attribute \src "ls180.v:820.6-820.32" wire \main_sdram_write_available - attribute \src "ls180.v:1033.6-1033.27" + attribute \src "ls180.v:855.5-855.47" + wire \main_socbushandler_converted_interface_ack + attribute \src "ls180.v:849.13-849.55" + wire width 30 \main_socbushandler_converted_interface_adr + attribute \src "ls180.v:858.12-858.54" + wire width 2 \main_socbushandler_converted_interface_bte + attribute \src "ls180.v:857.12-857.54" + wire width 3 \main_socbushandler_converted_interface_cti + attribute \src "ls180.v:853.6-853.48" + wire \main_socbushandler_converted_interface_cyc + attribute \src "ls180.v:851.13-851.57" + wire width 64 \main_socbushandler_converted_interface_dat_r + attribute \src "ls180.v:850.13-850.57" + wire width 64 \main_socbushandler_converted_interface_dat_w + attribute \src "ls180.v:859.5-859.47" + wire \main_socbushandler_converted_interface_err + attribute \src "ls180.v:852.12-852.54" + wire width 8 \main_socbushandler_converted_interface_sel + attribute \src "ls180.v:854.6-854.48" + wire \main_socbushandler_converted_interface_stb + attribute \src "ls180.v:856.6-856.47" + wire \main_socbushandler_converted_interface_we + attribute \src "ls180.v:861.5-861.31" + wire \main_socbushandler_counter + attribute \src "ls180.v:1790.5-1790.53" + wire \main_socbushandler_counter_converter2_next_value + attribute \src "ls180.v:1791.5-1791.56" + wire \main_socbushandler_counter_converter2_next_value_ce + attribute \src "ls180.v:863.12-863.36" + wire width 64 \main_socbushandler_dat_r + attribute \src "ls180.v:862.6-862.30" + wire \main_socbushandler_reset + attribute \src "ls180.v:860.5-860.28" + wire \main_socbushandler_skip + attribute \src "ls180.v:1038.6-1038.27" wire \main_spimaster0_start - attribute \src "ls180.v:1043.12-1043.35" + attribute \src "ls180.v:1048.12-1048.35" wire width 8 \main_spimaster10_length - attribute \src "ls180.v:1044.12-1044.36" + attribute \src "ls180.v:1049.12-1049.36" wire width 16 \main_spimaster11_storage - attribute \src "ls180.v:1045.5-1045.24" + attribute \src "ls180.v:1050.5-1050.24" wire \main_spimaster12_re - attribute \src "ls180.v:1046.6-1046.27" + attribute \src "ls180.v:1051.6-1051.27" wire \main_spimaster13_done - attribute \src "ls180.v:1047.6-1047.29" + attribute \src "ls180.v:1052.6-1052.29" wire \main_spimaster14_status - attribute \src "ls180.v:1048.6-1048.25" + attribute \src "ls180.v:1053.6-1053.25" wire \main_spimaster15_we - attribute \src "ls180.v:1049.11-1049.35" + attribute \src "ls180.v:1054.11-1054.35" wire width 8 \main_spimaster16_storage - attribute \src "ls180.v:1050.5-1050.24" + attribute \src "ls180.v:1055.5-1055.24" wire \main_spimaster17_re - attribute \src "ls180.v:1051.12-1051.35" + attribute \src "ls180.v:1056.12-1056.35" wire width 8 \main_spimaster18_status - attribute \src "ls180.v:1052.6-1052.25" + attribute \src "ls180.v:1057.6-1057.25" wire \main_spimaster19_we - attribute \src "ls180.v:1034.12-1034.34" + attribute \src "ls180.v:1039.12-1039.34" wire width 8 \main_spimaster1_length - attribute \src "ls180.v:1106.5-1106.23" + attribute \src "ls180.v:1111.5-1111.23" wire \main_spimaster1_re - attribute \src "ls180.v:1105.12-1105.35" + attribute \src "ls180.v:1110.12-1110.35" wire width 16 \main_spimaster1_storage - attribute \src "ls180.v:1053.6-1053.26" + attribute \src "ls180.v:1058.6-1058.26" wire \main_spimaster20_sel - attribute \src "ls180.v:1054.5-1054.29" + attribute \src "ls180.v:1059.5-1059.29" wire \main_spimaster21_storage - attribute \src "ls180.v:1055.5-1055.24" + attribute \src "ls180.v:1060.5-1060.24" wire \main_spimaster22_re - attribute \src "ls180.v:1056.5-1056.29" + attribute \src "ls180.v:1061.5-1061.29" wire \main_spimaster23_storage - attribute \src "ls180.v:1057.5-1057.24" + attribute \src "ls180.v:1062.5-1062.24" wire \main_spimaster24_re - attribute \src "ls180.v:1058.5-1058.32" + attribute \src "ls180.v:1063.5-1063.32" wire \main_spimaster25_clk_enable - attribute \src "ls180.v:1059.5-1059.31" + attribute \src "ls180.v:1064.5-1064.31" wire \main_spimaster26_cs_enable - attribute \src "ls180.v:1060.11-1060.33" + attribute \src "ls180.v:1065.11-1065.33" wire width 3 \main_spimaster27_count - attribute \src "ls180.v:1826.11-1826.55" + attribute \src "ls180.v:1831.11-1831.55" wire width 3 \main_spimaster27_count_spimaster0_next_value - attribute \src "ls180.v:1827.5-1827.52" + attribute \src "ls180.v:1832.5-1832.52" wire \main_spimaster27_count_spimaster0_next_value_ce - attribute \src "ls180.v:1061.5-1061.32" + attribute \src "ls180.v:1066.5-1066.32" wire \main_spimaster28_mosi_latch - attribute \src "ls180.v:1062.5-1062.32" + attribute \src "ls180.v:1067.5-1067.32" wire \main_spimaster29_miso_latch - attribute \src "ls180.v:1035.5-1035.25" + attribute \src "ls180.v:1040.5-1040.25" wire \main_spimaster2_done - attribute \src "ls180.v:1063.12-1063.40" + attribute \src "ls180.v:1068.12-1068.40" wire width 16 \main_spimaster30_clk_divider - attribute \src "ls180.v:1064.6-1064.31" + attribute \src "ls180.v:1069.6-1069.31" wire \main_spimaster31_clk_rise - attribute \src "ls180.v:1065.6-1065.31" + attribute \src "ls180.v:1070.6-1070.31" wire \main_spimaster32_clk_fall - attribute \src "ls180.v:1066.11-1066.37" + attribute \src "ls180.v:1071.11-1071.37" wire width 8 \main_spimaster33_mosi_data - attribute \src "ls180.v:1067.11-1067.36" + attribute \src "ls180.v:1072.11-1072.36" wire width 3 \main_spimaster34_mosi_sel - attribute \src "ls180.v:1068.11-1068.37" + attribute \src "ls180.v:1073.11-1073.37" wire width 8 \main_spimaster35_miso_data - attribute \src "ls180.v:1036.5-1036.24" + attribute \src "ls180.v:1041.5-1041.24" wire \main_spimaster3_irq - attribute \src "ls180.v:1037.12-1037.32" + attribute \src "ls180.v:1042.12-1042.32" wire width 8 \main_spimaster4_mosi - attribute \src "ls180.v:1038.11-1038.31" + attribute \src "ls180.v:1043.11-1043.31" wire width 8 \main_spimaster5_miso - attribute \src "ls180.v:1039.6-1039.24" + attribute \src "ls180.v:1044.6-1044.24" wire \main_spimaster6_cs - attribute \src "ls180.v:1040.6-1040.30" + attribute \src "ls180.v:1045.6-1045.30" wire \main_spimaster7_loopback - attribute \src "ls180.v:1041.12-1041.39" + attribute \src "ls180.v:1046.12-1046.39" wire width 16 \main_spimaster8_clk_divider - attribute \src "ls180.v:1042.5-1042.26" + attribute \src "ls180.v:1047.5-1047.26" wire \main_spimaster9_start - attribute \src "ls180.v:1077.13-1077.40" + attribute \src "ls180.v:1082.13-1082.40" wire width 16 \main_spisdcard_clk_divider0 - attribute \src "ls180.v:1099.12-1099.39" + attribute \src "ls180.v:1104.12-1104.39" wire width 16 \main_spisdcard_clk_divider1 - attribute \src "ls180.v:1094.5-1094.30" + attribute \src "ls180.v:1099.5-1099.30" wire \main_spisdcard_clk_enable - attribute \src "ls180.v:1101.6-1101.29" + attribute \src "ls180.v:1106.6-1106.29" wire \main_spisdcard_clk_fall - attribute \src "ls180.v:1100.6-1100.29" + attribute \src "ls180.v:1105.6-1105.29" wire \main_spisdcard_clk_rise - attribute \src "ls180.v:1081.5-1081.30" + attribute \src "ls180.v:1086.5-1086.30" wire \main_spisdcard_control_re - attribute \src "ls180.v:1080.12-1080.42" + attribute \src "ls180.v:1085.12-1085.42" wire width 16 \main_spisdcard_control_storage - attribute \src "ls180.v:1096.11-1096.31" + attribute \src "ls180.v:1101.11-1101.31" wire width 3 \main_spisdcard_count - attribute \src "ls180.v:1830.11-1830.53" + attribute \src "ls180.v:1835.11-1835.53" wire width 3 \main_spisdcard_count_spimaster1_next_value - attribute \src "ls180.v:1831.5-1831.50" + attribute \src "ls180.v:1836.5-1836.50" wire \main_spisdcard_count_spimaster1_next_value_ce - attribute \src "ls180.v:1075.6-1075.23" + attribute \src "ls180.v:1080.6-1080.23" wire \main_spisdcard_cs - attribute \src "ls180.v:1095.5-1095.29" + attribute \src "ls180.v:1100.5-1100.29" wire \main_spisdcard_cs_enable - attribute \src "ls180.v:1091.5-1091.25" + attribute \src "ls180.v:1096.5-1096.25" wire \main_spisdcard_cs_re - attribute \src "ls180.v:1090.5-1090.30" + attribute \src "ls180.v:1095.5-1095.30" wire \main_spisdcard_cs_storage - attribute \src "ls180.v:1071.5-1071.25" + attribute \src "ls180.v:1076.5-1076.25" wire \main_spisdcard_done0 - attribute \src "ls180.v:1082.6-1082.26" + attribute \src "ls180.v:1087.6-1087.26" wire \main_spisdcard_done1 - attribute \src "ls180.v:1072.5-1072.23" + attribute \src "ls180.v:1077.5-1077.23" wire \main_spisdcard_irq - attribute \src "ls180.v:1070.12-1070.34" + attribute \src "ls180.v:1075.12-1075.34" wire width 8 \main_spisdcard_length0 - attribute \src "ls180.v:1079.12-1079.34" + attribute \src "ls180.v:1084.12-1084.34" wire width 8 \main_spisdcard_length1 - attribute \src "ls180.v:1076.6-1076.29" + attribute \src "ls180.v:1081.6-1081.29" wire \main_spisdcard_loopback - attribute \src "ls180.v:1093.5-1093.31" + attribute \src "ls180.v:1098.5-1098.31" wire \main_spisdcard_loopback_re - attribute \src "ls180.v:1092.5-1092.36" + attribute \src "ls180.v:1097.5-1097.36" wire \main_spisdcard_loopback_storage - attribute \src "ls180.v:1074.11-1074.30" + attribute \src "ls180.v:1079.11-1079.30" wire width 8 \main_spisdcard_miso - attribute \src "ls180.v:1104.11-1104.35" + attribute \src "ls180.v:1109.11-1109.35" wire width 8 \main_spisdcard_miso_data - attribute \src "ls180.v:1098.5-1098.30" + attribute \src "ls180.v:1103.5-1103.30" wire \main_spisdcard_miso_latch - attribute \src "ls180.v:1087.12-1087.38" + attribute \src "ls180.v:1092.12-1092.38" wire width 8 \main_spisdcard_miso_status - attribute \src "ls180.v:1088.6-1088.28" + attribute \src "ls180.v:1093.6-1093.28" wire \main_spisdcard_miso_we - attribute \src "ls180.v:1073.12-1073.31" + attribute \src "ls180.v:1078.12-1078.31" wire width 8 \main_spisdcard_mosi - attribute \src "ls180.v:1102.11-1102.35" + attribute \src "ls180.v:1107.11-1107.35" wire width 8 \main_spisdcard_mosi_data - attribute \src "ls180.v:1097.5-1097.30" + attribute \src "ls180.v:1102.5-1102.30" wire \main_spisdcard_mosi_latch - attribute \src "ls180.v:1086.5-1086.27" + attribute \src "ls180.v:1091.5-1091.27" wire \main_spisdcard_mosi_re - attribute \src "ls180.v:1103.11-1103.34" + attribute \src "ls180.v:1108.11-1108.34" wire width 3 \main_spisdcard_mosi_sel - attribute \src "ls180.v:1085.11-1085.38" + attribute \src "ls180.v:1090.11-1090.38" wire width 8 \main_spisdcard_mosi_storage - attribute \src "ls180.v:1089.6-1089.24" + attribute \src "ls180.v:1094.6-1094.24" wire \main_spisdcard_sel - attribute \src "ls180.v:1069.6-1069.27" + attribute \src "ls180.v:1074.6-1074.27" wire \main_spisdcard_start0 - attribute \src "ls180.v:1078.5-1078.26" + attribute \src "ls180.v:1083.5-1083.26" wire \main_spisdcard_start1 - attribute \src "ls180.v:1083.6-1083.34" + attribute \src "ls180.v:1088.6-1088.34" wire \main_spisdcard_status_status - attribute \src "ls180.v:1084.6-1084.30" + attribute \src "ls180.v:1089.6-1089.30" wire \main_spisdcard_status_we - attribute \src "ls180.v:256.12-256.26" - wire width 7 \main_sram0_adr - attribute \src "ls180.v:257.13-257.29" - wire width 32 \main_sram0_dat_r - attribute \src "ls180.v:259.13-259.29" - wire width 32 \main_sram0_dat_w - attribute \src "ls180.v:258.11-258.24" - wire width 4 \main_sram0_we - attribute \src "ls180.v:271.12-271.26" - wire width 7 \main_sram1_adr - attribute \src "ls180.v:272.13-272.29" - wire width 32 \main_sram1_dat_r - attribute \src "ls180.v:274.13-274.29" - wire width 32 \main_sram1_dat_w - attribute \src "ls180.v:273.11-273.24" - wire width 4 \main_sram1_we - attribute \src "ls180.v:286.12-286.26" - wire width 7 \main_sram2_adr - attribute \src "ls180.v:287.13-287.29" - wire width 32 \main_sram2_dat_r - attribute \src "ls180.v:289.13-289.29" - wire width 32 \main_sram2_dat_w - attribute \src "ls180.v:288.11-288.24" - wire width 4 \main_sram2_we - attribute \src "ls180.v:930.12-930.44" + attribute \src "ls180.v:213.12-213.26" + wire width 6 \main_sram0_adr + attribute \src "ls180.v:214.13-214.29" + wire width 64 \main_sram0_dat_r + attribute \src "ls180.v:216.13-216.29" + wire width 64 \main_sram0_dat_w + attribute \src "ls180.v:215.11-215.24" + wire width 8 \main_sram0_we + attribute \src "ls180.v:228.12-228.26" + wire width 6 \main_sram1_adr + attribute \src "ls180.v:229.13-229.29" + wire width 64 \main_sram1_dat_r + attribute \src "ls180.v:231.13-231.29" + wire width 64 \main_sram1_dat_w + attribute \src "ls180.v:230.11-230.24" + wire width 8 \main_sram1_we + attribute \src "ls180.v:243.12-243.26" + wire width 6 \main_sram2_adr + attribute \src "ls180.v:244.13-244.29" + wire width 64 \main_sram2_dat_r + attribute \src "ls180.v:246.13-246.29" + wire width 64 \main_sram2_dat_w + attribute \src "ls180.v:245.11-245.24" + wire width 8 \main_sram2_we + attribute \src "ls180.v:929.12-929.44" wire width 2 \main_uart_eventmanager_pending_r - attribute \src "ls180.v:929.6-929.39" + attribute \src "ls180.v:928.6-928.39" wire \main_uart_eventmanager_pending_re - attribute \src "ls180.v:932.11-932.43" + attribute \src "ls180.v:931.11-931.43" wire width 2 \main_uart_eventmanager_pending_w - attribute \src "ls180.v:931.6-931.39" + attribute \src "ls180.v:930.6-930.39" wire \main_uart_eventmanager_pending_we - attribute \src "ls180.v:934.5-934.30" + attribute \src "ls180.v:933.5-933.30" wire \main_uart_eventmanager_re - attribute \src "ls180.v:926.12-926.43" + attribute \src "ls180.v:925.12-925.43" wire width 2 \main_uart_eventmanager_status_r - attribute \src "ls180.v:925.6-925.38" + attribute \src "ls180.v:924.6-924.38" wire \main_uart_eventmanager_status_re - attribute \src "ls180.v:928.11-928.42" + attribute \src "ls180.v:927.11-927.42" wire width 2 \main_uart_eventmanager_status_w - attribute \src "ls180.v:927.6-927.38" + attribute \src "ls180.v:926.6-926.38" wire \main_uart_eventmanager_status_we - attribute \src "ls180.v:933.11-933.41" + attribute \src "ls180.v:932.11-932.41" wire width 2 \main_uart_eventmanager_storage - attribute \src "ls180.v:914.6-914.19" + attribute \src "ls180.v:913.6-913.19" wire \main_uart_irq - attribute \src "ls180.v:900.12-900.46" + attribute \src "ls180.v:899.12-899.46" wire width 32 \main_uart_phy_phase_accumulator_rx - attribute \src "ls180.v:890.12-890.46" + attribute \src "ls180.v:889.12-889.46" wire width 32 \main_uart_phy_phase_accumulator_tx - attribute \src "ls180.v:883.5-883.21" + attribute \src "ls180.v:882.5-882.21" wire \main_uart_phy_re - attribute \src "ls180.v:901.6-901.22" + attribute \src "ls180.v:900.6-900.22" wire \main_uart_phy_rx - attribute \src "ls180.v:904.11-904.36" + attribute \src "ls180.v:903.11-903.36" wire width 4 \main_uart_phy_rx_bitcount - attribute \src "ls180.v:905.5-905.26" + attribute \src "ls180.v:904.5-904.26" wire \main_uart_phy_rx_busy - attribute \src "ls180.v:902.5-902.23" + attribute \src "ls180.v:901.5-901.23" wire \main_uart_phy_rx_r - attribute \src "ls180.v:903.11-903.31" + attribute \src "ls180.v:902.11-902.31" wire width 8 \main_uart_phy_rx_reg - attribute \src "ls180.v:886.6-886.30" + attribute \src "ls180.v:885.6-885.30" wire \main_uart_phy_sink_first - attribute \src "ls180.v:887.6-887.29" + attribute \src "ls180.v:886.6-886.29" wire \main_uart_phy_sink_last - attribute \src "ls180.v:888.12-888.43" + attribute \src "ls180.v:887.12-887.43" wire width 8 \main_uart_phy_sink_payload_data - attribute \src "ls180.v:885.5-885.29" + attribute \src "ls180.v:884.5-884.29" wire \main_uart_phy_sink_ready - attribute \src "ls180.v:884.6-884.30" + attribute \src "ls180.v:883.6-883.30" wire \main_uart_phy_sink_valid - attribute \src "ls180.v:896.5-896.31" + attribute \src "ls180.v:895.5-895.31" wire \main_uart_phy_source_first - attribute \src "ls180.v:897.5-897.30" + attribute \src "ls180.v:896.5-896.30" wire \main_uart_phy_source_last - attribute \src "ls180.v:898.11-898.44" + attribute \src "ls180.v:897.11-897.44" wire width 8 \main_uart_phy_source_payload_data - attribute \src "ls180.v:895.6-895.32" + attribute \src "ls180.v:894.6-894.32" wire \main_uart_phy_source_ready - attribute \src "ls180.v:894.5-894.31" + attribute \src "ls180.v:893.5-893.31" wire \main_uart_phy_source_valid - attribute \src "ls180.v:882.12-882.33" + attribute \src "ls180.v:881.12-881.33" wire width 32 \main_uart_phy_storage - attribute \src "ls180.v:892.11-892.36" + attribute \src "ls180.v:891.11-891.36" wire width 4 \main_uart_phy_tx_bitcount - attribute \src "ls180.v:893.5-893.26" + attribute \src "ls180.v:892.5-892.26" wire \main_uart_phy_tx_busy - attribute \src "ls180.v:891.11-891.31" + attribute \src "ls180.v:890.11-890.31" wire width 8 \main_uart_phy_tx_reg - attribute \src "ls180.v:899.5-899.32" + attribute \src "ls180.v:898.5-898.32" wire \main_uart_phy_uart_clk_rxen - attribute \src "ls180.v:889.5-889.32" + attribute \src "ls180.v:888.5-888.32" wire \main_uart_phy_uart_clk_txen - attribute \src "ls180.v:1023.5-1023.20" + attribute \src "ls180.v:1022.5-1022.20" wire \main_uart_reset - attribute \src "ls180.v:923.5-923.23" + attribute \src "ls180.v:922.5-922.23" wire \main_uart_rx_clear - attribute \src "ls180.v:1007.11-1007.36" + attribute \src "ls180.v:1006.11-1006.36" wire width 4 \main_uart_rx_fifo_consume - attribute \src "ls180.v:1012.6-1012.31" + attribute \src "ls180.v:1011.6-1011.31" wire \main_uart_rx_fifo_do_read - attribute \src "ls180.v:1018.6-1018.37" + attribute \src "ls180.v:1017.6-1017.37" wire \main_uart_rx_fifo_fifo_in_first - attribute \src "ls180.v:1019.6-1019.36" + attribute \src "ls180.v:1018.6-1018.36" wire \main_uart_rx_fifo_fifo_in_last - attribute \src "ls180.v:1017.12-1017.50" + attribute \src "ls180.v:1016.12-1016.50" wire width 8 \main_uart_rx_fifo_fifo_in_payload_data - attribute \src "ls180.v:1021.6-1021.38" + attribute \src "ls180.v:1020.6-1020.38" wire \main_uart_rx_fifo_fifo_out_first - attribute \src "ls180.v:1022.6-1022.37" + attribute \src "ls180.v:1021.6-1021.37" wire \main_uart_rx_fifo_fifo_out_last - attribute \src "ls180.v:1020.12-1020.51" + attribute \src "ls180.v:1019.12-1019.51" wire width 8 \main_uart_rx_fifo_fifo_out_payload_data - attribute \src "ls180.v:1004.11-1004.35" + attribute \src "ls180.v:1003.11-1003.35" wire width 5 \main_uart_rx_fifo_level0 - attribute \src "ls180.v:1016.12-1016.36" + attribute \src "ls180.v:1015.12-1015.36" wire width 5 \main_uart_rx_fifo_level1 - attribute \src "ls180.v:1006.11-1006.36" + attribute \src "ls180.v:1005.11-1005.36" wire width 4 \main_uart_rx_fifo_produce - attribute \src "ls180.v:1013.12-1013.40" + attribute \src "ls180.v:1012.12-1012.40" wire width 4 \main_uart_rx_fifo_rdport_adr - attribute \src "ls180.v:1014.12-1014.42" + attribute \src "ls180.v:1013.12-1013.42" wire width 10 \main_uart_rx_fifo_rdport_dat_r - attribute \src "ls180.v:1015.6-1015.33" + attribute \src "ls180.v:1014.6-1014.33" wire \main_uart_rx_fifo_rdport_re - attribute \src "ls180.v:996.6-996.26" + attribute \src "ls180.v:995.6-995.26" wire \main_uart_rx_fifo_re - attribute \src "ls180.v:997.5-997.31" + attribute \src "ls180.v:996.5-996.31" wire \main_uart_rx_fifo_readable - attribute \src "ls180.v:1005.5-1005.30" + attribute \src "ls180.v:1004.5-1004.30" wire \main_uart_rx_fifo_replace - attribute \src "ls180.v:988.6-988.34" + attribute \src "ls180.v:987.6-987.34" wire \main_uart_rx_fifo_sink_first - attribute \src "ls180.v:989.6-989.33" + attribute \src "ls180.v:988.6-988.33" wire \main_uart_rx_fifo_sink_last - attribute \src "ls180.v:990.12-990.47" + attribute \src "ls180.v:989.12-989.47" wire width 8 \main_uart_rx_fifo_sink_payload_data - attribute \src "ls180.v:987.6-987.34" - wire \main_uart_rx_fifo_sink_ready attribute \src "ls180.v:986.6-986.34" + wire \main_uart_rx_fifo_sink_ready + attribute \src "ls180.v:985.6-985.34" wire \main_uart_rx_fifo_sink_valid - attribute \src "ls180.v:993.6-993.36" + attribute \src "ls180.v:992.6-992.36" wire \main_uart_rx_fifo_source_first - attribute \src "ls180.v:994.6-994.35" + attribute \src "ls180.v:993.6-993.35" wire \main_uart_rx_fifo_source_last - attribute \src "ls180.v:995.12-995.49" + attribute \src "ls180.v:994.12-994.49" wire width 8 \main_uart_rx_fifo_source_payload_data - attribute \src "ls180.v:992.6-992.36" - wire \main_uart_rx_fifo_source_ready attribute \src "ls180.v:991.6-991.36" + wire \main_uart_rx_fifo_source_ready + attribute \src "ls180.v:990.6-990.36" wire \main_uart_rx_fifo_source_valid - attribute \src "ls180.v:1002.12-1002.42" + attribute \src "ls180.v:1001.12-1001.42" wire width 10 \main_uart_rx_fifo_syncfifo_din - attribute \src "ls180.v:1003.12-1003.43" + attribute \src "ls180.v:1002.12-1002.43" wire width 10 \main_uart_rx_fifo_syncfifo_dout - attribute \src "ls180.v:1000.6-1000.35" + attribute \src "ls180.v:999.6-999.35" wire \main_uart_rx_fifo_syncfifo_re - attribute \src "ls180.v:1001.6-1001.41" + attribute \src "ls180.v:1000.6-1000.41" wire \main_uart_rx_fifo_syncfifo_readable - attribute \src "ls180.v:998.6-998.35" + attribute \src "ls180.v:997.6-997.35" wire \main_uart_rx_fifo_syncfifo_we - attribute \src "ls180.v:999.6-999.41" + attribute \src "ls180.v:998.6-998.41" wire \main_uart_rx_fifo_syncfifo_writable - attribute \src "ls180.v:1008.11-1008.39" + attribute \src "ls180.v:1007.11-1007.39" wire width 4 \main_uart_rx_fifo_wrport_adr - attribute \src "ls180.v:1009.12-1009.42" + attribute \src "ls180.v:1008.12-1008.42" wire width 10 \main_uart_rx_fifo_wrport_dat_r - attribute \src "ls180.v:1011.12-1011.42" + attribute \src "ls180.v:1010.12-1010.42" wire width 10 \main_uart_rx_fifo_wrport_dat_w - attribute \src "ls180.v:1010.6-1010.33" + attribute \src "ls180.v:1009.6-1009.33" wire \main_uart_rx_fifo_wrport_we - attribute \src "ls180.v:924.5-924.29" + attribute \src "ls180.v:923.5-923.29" wire \main_uart_rx_old_trigger - attribute \src "ls180.v:921.5-921.25" + attribute \src "ls180.v:920.5-920.25" wire \main_uart_rx_pending - attribute \src "ls180.v:920.6-920.25" + attribute \src "ls180.v:919.6-919.25" wire \main_uart_rx_status - attribute \src "ls180.v:922.6-922.26" + attribute \src "ls180.v:921.6-921.26" wire \main_uart_rx_trigger - attribute \src "ls180.v:912.6-912.30" + attribute \src "ls180.v:911.6-911.30" wire \main_uart_rxempty_status - attribute \src "ls180.v:913.6-913.26" + attribute \src "ls180.v:912.6-912.26" wire \main_uart_rxempty_we - attribute \src "ls180.v:937.6-937.29" + attribute \src "ls180.v:936.6-936.29" wire \main_uart_rxfull_status - attribute \src "ls180.v:938.6-938.25" + attribute \src "ls180.v:937.6-937.25" wire \main_uart_rxfull_we - attribute \src "ls180.v:907.12-907.28" + attribute \src "ls180.v:906.12-906.28" wire width 8 \main_uart_rxtx_r - attribute \src "ls180.v:906.6-906.23" + attribute \src "ls180.v:905.6-905.23" wire \main_uart_rxtx_re - attribute \src "ls180.v:909.12-909.28" + attribute \src "ls180.v:908.12-908.28" wire width 8 \main_uart_rxtx_w - attribute \src "ls180.v:908.6-908.23" + attribute \src "ls180.v:907.6-907.23" wire \main_uart_rxtx_we - attribute \src "ls180.v:918.5-918.23" + attribute \src "ls180.v:917.5-917.23" wire \main_uart_tx_clear - attribute \src "ls180.v:970.11-970.36" + attribute \src "ls180.v:969.11-969.36" wire width 4 \main_uart_tx_fifo_consume - attribute \src "ls180.v:975.6-975.31" + attribute \src "ls180.v:974.6-974.31" wire \main_uart_tx_fifo_do_read - attribute \src "ls180.v:981.6-981.37" + attribute \src "ls180.v:980.6-980.37" wire \main_uart_tx_fifo_fifo_in_first - attribute \src "ls180.v:982.6-982.36" + attribute \src "ls180.v:981.6-981.36" wire \main_uart_tx_fifo_fifo_in_last - attribute \src "ls180.v:980.12-980.50" + attribute \src "ls180.v:979.12-979.50" wire width 8 \main_uart_tx_fifo_fifo_in_payload_data - attribute \src "ls180.v:984.6-984.38" + attribute \src "ls180.v:983.6-983.38" wire \main_uart_tx_fifo_fifo_out_first - attribute \src "ls180.v:985.6-985.37" + attribute \src "ls180.v:984.6-984.37" wire \main_uart_tx_fifo_fifo_out_last - attribute \src "ls180.v:983.12-983.51" + attribute \src "ls180.v:982.12-982.51" wire width 8 \main_uart_tx_fifo_fifo_out_payload_data - attribute \src "ls180.v:967.11-967.35" + attribute \src "ls180.v:966.11-966.35" wire width 5 \main_uart_tx_fifo_level0 - attribute \src "ls180.v:979.12-979.36" + attribute \src "ls180.v:978.12-978.36" wire width 5 \main_uart_tx_fifo_level1 - attribute \src "ls180.v:969.11-969.36" + attribute \src "ls180.v:968.11-968.36" wire width 4 \main_uart_tx_fifo_produce - attribute \src "ls180.v:976.12-976.40" + attribute \src "ls180.v:975.12-975.40" wire width 4 \main_uart_tx_fifo_rdport_adr - attribute \src "ls180.v:977.12-977.42" + attribute \src "ls180.v:976.12-976.42" wire width 10 \main_uart_tx_fifo_rdport_dat_r - attribute \src "ls180.v:978.6-978.33" + attribute \src "ls180.v:977.6-977.33" wire \main_uart_tx_fifo_rdport_re - attribute \src "ls180.v:959.6-959.26" + attribute \src "ls180.v:958.6-958.26" wire \main_uart_tx_fifo_re - attribute \src "ls180.v:960.5-960.31" + attribute \src "ls180.v:959.5-959.31" wire \main_uart_tx_fifo_readable - attribute \src "ls180.v:968.5-968.30" + attribute \src "ls180.v:967.5-967.30" wire \main_uart_tx_fifo_replace - attribute \src "ls180.v:951.5-951.33" + attribute \src "ls180.v:950.5-950.33" wire \main_uart_tx_fifo_sink_first - attribute \src "ls180.v:952.5-952.32" + attribute \src "ls180.v:951.5-951.32" wire \main_uart_tx_fifo_sink_last - attribute \src "ls180.v:953.12-953.47" + attribute \src "ls180.v:952.12-952.47" wire width 8 \main_uart_tx_fifo_sink_payload_data - attribute \src "ls180.v:950.6-950.34" - wire \main_uart_tx_fifo_sink_ready attribute \src "ls180.v:949.6-949.34" + wire \main_uart_tx_fifo_sink_ready + attribute \src "ls180.v:948.6-948.34" wire \main_uart_tx_fifo_sink_valid - attribute \src "ls180.v:956.6-956.36" + attribute \src "ls180.v:955.6-955.36" wire \main_uart_tx_fifo_source_first - attribute \src "ls180.v:957.6-957.35" + attribute \src "ls180.v:956.6-956.35" wire \main_uart_tx_fifo_source_last - attribute \src "ls180.v:958.12-958.49" + attribute \src "ls180.v:957.12-957.49" wire width 8 \main_uart_tx_fifo_source_payload_data - attribute \src "ls180.v:955.6-955.36" - wire \main_uart_tx_fifo_source_ready attribute \src "ls180.v:954.6-954.36" + wire \main_uart_tx_fifo_source_ready + attribute \src "ls180.v:953.6-953.36" wire \main_uart_tx_fifo_source_valid - attribute \src "ls180.v:965.12-965.42" + attribute \src "ls180.v:964.12-964.42" wire width 10 \main_uart_tx_fifo_syncfifo_din - attribute \src "ls180.v:966.12-966.43" + attribute \src "ls180.v:965.12-965.43" wire width 10 \main_uart_tx_fifo_syncfifo_dout - attribute \src "ls180.v:963.6-963.35" + attribute \src "ls180.v:962.6-962.35" wire \main_uart_tx_fifo_syncfifo_re - attribute \src "ls180.v:964.6-964.41" + attribute \src "ls180.v:963.6-963.41" wire \main_uart_tx_fifo_syncfifo_readable - attribute \src "ls180.v:961.6-961.35" + attribute \src "ls180.v:960.6-960.35" wire \main_uart_tx_fifo_syncfifo_we - attribute \src "ls180.v:962.6-962.41" + attribute \src "ls180.v:961.6-961.41" wire \main_uart_tx_fifo_syncfifo_writable - attribute \src "ls180.v:971.11-971.39" + attribute \src "ls180.v:970.11-970.39" wire width 4 \main_uart_tx_fifo_wrport_adr - attribute \src "ls180.v:972.12-972.42" + attribute \src "ls180.v:971.12-971.42" wire width 10 \main_uart_tx_fifo_wrport_dat_r - attribute \src "ls180.v:974.12-974.42" + attribute \src "ls180.v:973.12-973.42" wire width 10 \main_uart_tx_fifo_wrport_dat_w - attribute \src "ls180.v:973.6-973.33" + attribute \src "ls180.v:972.6-972.33" wire \main_uart_tx_fifo_wrport_we - attribute \src "ls180.v:919.5-919.29" + attribute \src "ls180.v:918.5-918.29" wire \main_uart_tx_old_trigger - attribute \src "ls180.v:916.5-916.25" + attribute \src "ls180.v:915.5-915.25" wire \main_uart_tx_pending - attribute \src "ls180.v:915.6-915.25" + attribute \src "ls180.v:914.6-914.25" wire \main_uart_tx_status - attribute \src "ls180.v:917.6-917.26" + attribute \src "ls180.v:916.6-916.26" wire \main_uart_tx_trigger - attribute \src "ls180.v:935.6-935.30" + attribute \src "ls180.v:934.6-934.30" wire \main_uart_txempty_status - attribute \src "ls180.v:936.6-936.26" + attribute \src "ls180.v:935.6-935.26" wire \main_uart_txempty_we - attribute \src "ls180.v:910.6-910.29" + attribute \src "ls180.v:909.6-909.29" wire \main_uart_txfull_status - attribute \src "ls180.v:911.6-911.25" + attribute \src "ls180.v:910.6-910.25" wire \main_uart_txfull_we - attribute \src "ls180.v:941.6-941.31" + attribute \src "ls180.v:940.6-940.31" wire \main_uart_uart_sink_first - attribute \src "ls180.v:942.6-942.30" + attribute \src "ls180.v:941.6-941.30" wire \main_uart_uart_sink_last - attribute \src "ls180.v:943.12-943.44" + attribute \src "ls180.v:942.12-942.44" wire width 8 \main_uart_uart_sink_payload_data - attribute \src "ls180.v:940.6-940.31" - wire \main_uart_uart_sink_ready attribute \src "ls180.v:939.6-939.31" + wire \main_uart_uart_sink_ready + attribute \src "ls180.v:938.6-938.31" wire \main_uart_uart_sink_valid - attribute \src "ls180.v:946.6-946.33" + attribute \src "ls180.v:945.6-945.33" wire \main_uart_uart_source_first - attribute \src "ls180.v:947.6-947.32" + attribute \src "ls180.v:946.6-946.32" wire \main_uart_uart_source_last - attribute \src "ls180.v:948.12-948.46" + attribute \src "ls180.v:947.12-947.46" wire width 8 \main_uart_uart_source_payload_data - attribute \src "ls180.v:945.6-945.33" - wire \main_uart_uart_source_ready attribute \src "ls180.v:944.6-944.33" + wire \main_uart_uart_source_ready + attribute \src "ls180.v:943.6-943.33" wire \main_uart_uart_source_valid - attribute \src "ls180.v:860.5-860.22" + attribute \src "ls180.v:847.5-847.22" wire \main_wb_sdram_ack - attribute \src "ls180.v:854.13-854.30" + attribute \src "ls180.v:841.12-841.29" wire width 30 \main_wb_sdram_adr - attribute \src "ls180.v:863.12-863.29" - wire width 2 \main_wb_sdram_bte - attribute \src "ls180.v:862.12-862.29" - wire width 3 \main_wb_sdram_cti - attribute \src "ls180.v:858.6-858.23" + attribute \src "ls180.v:845.5-845.22" wire \main_wb_sdram_cyc - attribute \src "ls180.v:856.13-856.32" + attribute \src "ls180.v:843.13-843.32" wire width 32 \main_wb_sdram_dat_r - attribute \src "ls180.v:855.13-855.32" + attribute \src "ls180.v:842.12-842.31" wire width 32 \main_wb_sdram_dat_w - attribute \src "ls180.v:864.5-864.22" - wire \main_wb_sdram_err - attribute \src "ls180.v:857.12-857.29" + attribute \src "ls180.v:844.11-844.28" wire width 4 \main_wb_sdram_sel - attribute \src "ls180.v:859.6-859.23" + attribute \src "ls180.v:846.5-846.22" wire \main_wb_sdram_stb - attribute \src "ls180.v:861.6-861.22" + attribute \src "ls180.v:848.5-848.21" wire \main_wb_sdram_we - attribute \src "ls180.v:878.5-878.24" + attribute \src "ls180.v:877.5-877.24" wire \main_wdata_consumed - attribute \src "ls180.v:10159.11-10159.17" - wire width 7 \memadr - attribute \src "ls180.v:10179.11-10179.19" - wire width 7 \memadr_1 - attribute \src "ls180.v:10199.11-10199.19" - wire width 7 \memadr_2 - attribute \src "ls180.v:10219.11-10219.19" - wire width 7 \memadr_3 - attribute \src "ls180.v:10239.12-10239.18" + attribute \src "ls180.v:10226.11-10226.17" + wire width 6 \memadr + attribute \src "ls180.v:10254.11-10254.19" + wire width 6 \memadr_1 + attribute \src "ls180.v:10282.11-10282.19" + wire width 6 \memadr_2 + attribute \src "ls180.v:10310.11-10310.19" + wire width 6 \memadr_3 + attribute \src "ls180.v:10338.12-10338.18" wire width 25 \memdat - attribute \src "ls180.v:10253.12-10253.20" + attribute \src "ls180.v:10352.12-10352.20" wire width 25 \memdat_1 - attribute \src "ls180.v:10267.12-10267.20" + attribute \src "ls180.v:10366.12-10366.20" wire width 25 \memdat_2 - attribute \src "ls180.v:10281.12-10281.20" + attribute \src "ls180.v:10380.12-10380.20" wire width 25 \memdat_3 - attribute \src "ls180.v:10295.11-10295.19" + attribute \src "ls180.v:10394.11-10394.19" wire width 10 \memdat_4 - attribute \src "ls180.v:10296.11-10296.19" + attribute \src "ls180.v:10395.11-10395.19" wire width 10 \memdat_5 - attribute \src "ls180.v:10312.11-10312.19" + attribute \src "ls180.v:10411.11-10411.19" wire width 10 \memdat_6 - attribute \src "ls180.v:10313.11-10313.19" + attribute \src "ls180.v:10412.11-10412.19" wire width 10 \memdat_7 - attribute \src "ls180.v:10329.11-10329.19" + attribute \src "ls180.v:10428.11-10428.19" wire width 10 \memdat_8 - attribute \src "ls180.v:10343.11-10343.19" + attribute \src "ls180.v:10442.11-10442.19" wire width 10 \memdat_9 attribute \src "ls180.v:52.20-52.22" wire width 24 input 48 \nc - attribute \src "ls180.v:292.6-292.13" + attribute \src "ls180.v:279.6-279.13" wire \por_clk - attribute \src "ls180.v:42.19-42.22" - wire width 2 output 38 \pwm - attribute \src "ls180.v:157.12-157.17" + attribute \src "ls180.v:11.19-11.22" + wire width 2 output 7 \pwm + attribute \src "ls180.v:131.12-131.17" wire width 2 \pwm_1 - attribute \src "ls180.v:35.13-35.23" - wire output 31 \sdcard_clk - attribute \src "ls180.v:36.13-36.25" - wire input 32 \sdcard_cmd_i - attribute \src "ls180.v:37.13-37.25" - wire output 33 \sdcard_cmd_o - attribute \src "ls180.v:38.13-38.26" - wire output 34 \sdcard_cmd_oe - attribute \src "ls180.v:39.19-39.32" - wire width 4 input 35 \sdcard_data_i - attribute \src "ls180.v:40.19-40.32" - wire width 4 output 36 \sdcard_data_o - attribute \src "ls180.v:41.13-41.27" - wire output 37 \sdcard_data_oe - attribute \src "ls180.v:5.20-5.27" - wire width 13 output 1 \sdram_a - attribute \src "ls180.v:14.19-14.27" - wire width 2 output 10 \sdram_ba - attribute \src "ls180.v:11.13-11.24" - wire output 7 \sdram_cas_n - attribute \src "ls180.v:13.13-13.22" - wire output 9 \sdram_cke - attribute \src "ls180.v:16.13-16.24" - wire output 12 \sdram_clock - attribute \src "ls180.v:136.6-136.19" + attribute \src "ls180.v:27.13-27.23" + wire output 23 \sdcard_clk + attribute \src "ls180.v:28.13-28.25" + wire input 24 \sdcard_cmd_i + attribute \src "ls180.v:29.13-29.25" + wire output 25 \sdcard_cmd_o + attribute \src "ls180.v:30.13-30.26" + wire output 26 \sdcard_cmd_oe + attribute \src "ls180.v:31.19-31.32" + wire width 4 input 27 \sdcard_data_i + attribute \src "ls180.v:32.19-32.32" + wire width 4 output 28 \sdcard_data_o + attribute \src "ls180.v:33.13-33.27" + wire output 29 \sdcard_data_oe + attribute \src "ls180.v:12.20-12.27" + wire width 13 output 8 \sdram_a + attribute \src "ls180.v:21.19-21.27" + wire width 2 output 17 \sdram_ba + attribute \src "ls180.v:18.13-18.24" + wire output 14 \sdram_cas_n + attribute \src "ls180.v:20.13-20.22" + wire output 16 \sdram_cke + attribute \src "ls180.v:23.13-23.24" + wire output 19 \sdram_clock + attribute \src "ls180.v:143.6-143.19" wire \sdram_clock_1 - attribute \src "ls180.v:12.13-12.23" - wire output 8 \sdram_cs_n - attribute \src "ls180.v:15.19-15.27" - wire width 2 output 11 \sdram_dm - attribute \src "ls180.v:6.20-6.30" - wire width 16 input 2 \sdram_dq_i - attribute \src "ls180.v:7.20-7.30" - wire width 16 output 3 \sdram_dq_o - attribute \src "ls180.v:8.13-8.24" - wire output 4 \sdram_dq_oe - attribute \src "ls180.v:10.13-10.24" - wire output 6 \sdram_ras_n - attribute \src "ls180.v:9.13-9.23" - wire output 5 \sdram_we_n - attribute \src "ls180.v:2688.6-2688.15" + attribute \src "ls180.v:19.13-19.23" + wire output 15 \sdram_cs_n + attribute \src "ls180.v:22.19-22.27" + wire width 2 output 18 \sdram_dm + attribute \src "ls180.v:13.20-13.30" + wire width 16 input 9 \sdram_dq_i + attribute \src "ls180.v:14.20-14.30" + wire width 16 output 10 \sdram_dq_o + attribute \src "ls180.v:15.13-15.24" + wire output 11 \sdram_dq_oe + attribute \src "ls180.v:17.13-17.24" + wire output 13 \sdram_ras_n + attribute \src "ls180.v:16.13-16.23" + wire output 12 \sdram_we_n + attribute \src "ls180.v:2701.6-2701.15" wire \sdrio_clk - attribute \src "ls180.v:2689.6-2689.17" + attribute \src "ls180.v:2702.6-2702.17" wire \sdrio_clk_1 - attribute \src "ls180.v:2698.6-2698.18" + attribute \src "ls180.v:2711.6-2711.18" wire \sdrio_clk_10 - attribute \src "ls180.v:2699.6-2699.18" + attribute \src "ls180.v:2712.6-2712.18" wire \sdrio_clk_11 - attribute \src "ls180.v:2700.6-2700.18" + attribute \src "ls180.v:2713.6-2713.18" wire \sdrio_clk_12 - attribute \src "ls180.v:2701.6-2701.18" + attribute \src "ls180.v:2714.6-2714.18" wire \sdrio_clk_13 - attribute \src "ls180.v:2702.6-2702.18" + attribute \src "ls180.v:2715.6-2715.18" wire \sdrio_clk_14 - attribute \src "ls180.v:2703.6-2703.18" + attribute \src "ls180.v:2716.6-2716.18" wire \sdrio_clk_15 - attribute \src "ls180.v:2704.6-2704.18" + attribute \src "ls180.v:2717.6-2717.18" wire \sdrio_clk_16 - attribute \src "ls180.v:2705.6-2705.18" + attribute \src "ls180.v:2718.6-2718.18" wire \sdrio_clk_17 - attribute \src "ls180.v:2706.6-2706.18" + attribute \src "ls180.v:2719.6-2719.18" wire \sdrio_clk_18 - attribute \src "ls180.v:2707.6-2707.18" + attribute \src "ls180.v:2720.6-2720.18" wire \sdrio_clk_19 - attribute \src "ls180.v:2690.6-2690.17" + attribute \src "ls180.v:2703.6-2703.17" wire \sdrio_clk_2 - attribute \src "ls180.v:2708.6-2708.18" + attribute \src "ls180.v:2721.6-2721.18" wire \sdrio_clk_20 - attribute \src "ls180.v:2709.6-2709.18" + attribute \src "ls180.v:2722.6-2722.18" wire \sdrio_clk_21 - attribute \src "ls180.v:2710.6-2710.18" + attribute \src "ls180.v:2723.6-2723.18" wire \sdrio_clk_22 - attribute \src "ls180.v:2711.6-2711.18" + attribute \src "ls180.v:2724.6-2724.18" wire \sdrio_clk_23 - attribute \src "ls180.v:2712.6-2712.18" + attribute \src "ls180.v:2725.6-2725.18" wire \sdrio_clk_24 - attribute \src "ls180.v:2713.6-2713.18" + attribute \src "ls180.v:2726.6-2726.18" wire \sdrio_clk_25 - attribute \src "ls180.v:2714.6-2714.18" + attribute \src "ls180.v:2727.6-2727.18" wire \sdrio_clk_26 - attribute \src "ls180.v:2715.6-2715.18" + attribute \src "ls180.v:2728.6-2728.18" wire \sdrio_clk_27 - attribute \src "ls180.v:2716.6-2716.18" + attribute \src "ls180.v:2729.6-2729.18" wire \sdrio_clk_28 - attribute \src "ls180.v:2717.6-2717.18" + attribute \src "ls180.v:2730.6-2730.18" wire \sdrio_clk_29 - attribute \src "ls180.v:2691.6-2691.17" + attribute \src "ls180.v:2704.6-2704.17" wire \sdrio_clk_3 - attribute \src "ls180.v:2718.6-2718.18" + attribute \src "ls180.v:2731.6-2731.18" wire \sdrio_clk_30 - attribute \src "ls180.v:2719.6-2719.18" + attribute \src "ls180.v:2732.6-2732.18" wire \sdrio_clk_31 - attribute \src "ls180.v:2720.6-2720.18" + attribute \src "ls180.v:2733.6-2733.18" wire \sdrio_clk_32 - attribute \src "ls180.v:2721.6-2721.18" + attribute \src "ls180.v:2734.6-2734.18" wire \sdrio_clk_33 - attribute \src "ls180.v:2722.6-2722.18" + attribute \src "ls180.v:2735.6-2735.18" wire \sdrio_clk_34 - attribute \src "ls180.v:2723.6-2723.18" + attribute \src "ls180.v:2736.6-2736.18" wire \sdrio_clk_35 - attribute \src "ls180.v:2724.6-2724.18" + attribute \src "ls180.v:2737.6-2737.18" wire \sdrio_clk_36 - attribute \src "ls180.v:2725.6-2725.18" + attribute \src "ls180.v:2738.6-2738.18" wire \sdrio_clk_37 - attribute \src "ls180.v:2726.6-2726.18" + attribute \src "ls180.v:2739.6-2739.18" wire \sdrio_clk_38 - attribute \src "ls180.v:2727.6-2727.18" + attribute \src "ls180.v:2740.6-2740.18" wire \sdrio_clk_39 - attribute \src "ls180.v:2692.6-2692.17" + attribute \src "ls180.v:2705.6-2705.17" wire \sdrio_clk_4 - attribute \src "ls180.v:2728.6-2728.18" + attribute \src "ls180.v:2741.6-2741.18" wire \sdrio_clk_40 - attribute \src "ls180.v:2729.6-2729.18" + attribute \src "ls180.v:2742.6-2742.18" wire \sdrio_clk_41 - attribute \src "ls180.v:2730.6-2730.18" + attribute \src "ls180.v:2743.6-2743.18" wire \sdrio_clk_42 - attribute \src "ls180.v:2731.6-2731.18" + attribute \src "ls180.v:2744.6-2744.18" wire \sdrio_clk_43 - attribute \src "ls180.v:2732.6-2732.18" + attribute \src "ls180.v:2745.6-2745.18" wire \sdrio_clk_44 - attribute \src "ls180.v:2733.6-2733.18" + attribute \src "ls180.v:2746.6-2746.18" wire \sdrio_clk_45 - attribute \src "ls180.v:2734.6-2734.18" + attribute \src "ls180.v:2747.6-2747.18" wire \sdrio_clk_46 - attribute \src "ls180.v:2735.6-2735.18" + attribute \src "ls180.v:2748.6-2748.18" wire \sdrio_clk_47 - attribute \src "ls180.v:2736.6-2736.18" + attribute \src "ls180.v:2749.6-2749.18" wire \sdrio_clk_48 - attribute \src "ls180.v:2737.6-2737.18" + attribute \src "ls180.v:2750.6-2750.18" wire \sdrio_clk_49 - attribute \src "ls180.v:2693.6-2693.17" + attribute \src "ls180.v:2706.6-2706.17" wire \sdrio_clk_5 - attribute \src "ls180.v:2738.6-2738.18" + attribute \src "ls180.v:2751.6-2751.18" wire \sdrio_clk_50 - attribute \src "ls180.v:2739.6-2739.18" + attribute \src "ls180.v:2752.6-2752.18" wire \sdrio_clk_51 - attribute \src "ls180.v:2740.6-2740.18" + attribute \src "ls180.v:2753.6-2753.18" wire \sdrio_clk_52 - attribute \src "ls180.v:2741.6-2741.18" + attribute \src "ls180.v:2754.6-2754.18" wire \sdrio_clk_53 - attribute \src "ls180.v:2742.6-2742.18" + attribute \src "ls180.v:2755.6-2755.18" wire \sdrio_clk_54 - attribute \src "ls180.v:2743.6-2743.18" + attribute \src "ls180.v:2756.6-2756.18" wire \sdrio_clk_55 - attribute \src "ls180.v:2778.6-2778.18" + attribute \src "ls180.v:2791.6-2791.18" wire \sdrio_clk_56 - attribute \src "ls180.v:2779.6-2779.18" + attribute \src "ls180.v:2792.6-2792.18" wire \sdrio_clk_57 - attribute \src "ls180.v:2780.6-2780.18" + attribute \src "ls180.v:2793.6-2793.18" wire \sdrio_clk_58 - attribute \src "ls180.v:2781.6-2781.18" + attribute \src "ls180.v:2794.6-2794.18" wire \sdrio_clk_59 - attribute \src "ls180.v:2694.6-2694.17" + attribute \src "ls180.v:2707.6-2707.17" wire \sdrio_clk_6 - attribute \src "ls180.v:2782.6-2782.18" + attribute \src "ls180.v:2795.6-2795.18" wire \sdrio_clk_60 - attribute \src "ls180.v:2783.6-2783.18" + attribute \src "ls180.v:2796.6-2796.18" wire \sdrio_clk_61 - attribute \src "ls180.v:2784.6-2784.18" + attribute \src "ls180.v:2797.6-2797.18" wire \sdrio_clk_62 - attribute \src "ls180.v:2785.6-2785.18" + attribute \src "ls180.v:2798.6-2798.18" wire \sdrio_clk_63 - attribute \src "ls180.v:2786.6-2786.18" + attribute \src "ls180.v:2799.6-2799.18" wire \sdrio_clk_64 - attribute \src "ls180.v:2787.6-2787.18" + attribute \src "ls180.v:2800.6-2800.18" wire \sdrio_clk_65 - attribute \src "ls180.v:2788.6-2788.18" + attribute \src "ls180.v:2801.6-2801.18" wire \sdrio_clk_66 - attribute \src "ls180.v:2789.6-2789.18" + attribute \src "ls180.v:2802.6-2802.18" wire \sdrio_clk_67 - attribute \src "ls180.v:2790.6-2790.18" + attribute \src "ls180.v:2803.6-2803.18" wire \sdrio_clk_68 - attribute \src "ls180.v:2695.6-2695.17" + attribute \src "ls180.v:2708.6-2708.17" wire \sdrio_clk_7 - attribute \src "ls180.v:2696.6-2696.17" + attribute \src "ls180.v:2709.6-2709.17" wire \sdrio_clk_8 - attribute \src "ls180.v:2697.6-2697.17" + attribute \src "ls180.v:2710.6-2710.17" wire \sdrio_clk_9 - attribute \src "ls180.v:24.13-24.26" - wire output 20 \spimaster_clk - attribute \src "ls180.v:26.13-26.27" - wire output 22 \spimaster_cs_n - attribute \src "ls180.v:27.13-27.27" - wire input 23 \spimaster_miso - attribute \src "ls180.v:25.13-25.27" - wire output 21 \spimaster_mosi - attribute \src "ls180.v:20.13-20.26" - wire output 16 \spisdcard_clk - attribute \src "ls180.v:22.13-22.27" - wire output 18 \spisdcard_cs_n - attribute \src "ls180.v:23.13-23.27" - wire input 19 \spisdcard_miso - attribute \src "ls180.v:21.13-21.27" - wire output 17 \spisdcard_mosi + attribute \src "ls180.v:39.13-39.26" + wire output 35 \spimaster_clk + attribute \src "ls180.v:41.13-41.27" + wire output 37 \spimaster_cs_n + attribute \src "ls180.v:42.13-42.27" + wire input 38 \spimaster_miso + attribute \src "ls180.v:40.13-40.27" + wire output 36 \spimaster_mosi + attribute \src "ls180.v:7.13-7.26" + wire output 3 \spisdcard_clk + attribute \src "ls180.v:9.13-9.27" + wire output 5 \spisdcard_cs_n + attribute \src "ls180.v:10.13-10.27" + wire input 6 \spisdcard_miso + attribute \src "ls180.v:8.13-8.27" + wire output 4 \spisdcard_mosi attribute \src "ls180.v:43.13-43.20" wire input 39 \sys_clk - attribute \src "ls180.v:290.6-290.15" + attribute \src "ls180.v:277.6-277.15" wire \sys_clk_1 attribute \src "ls180.v:45.19-45.31" wire width 2 input 41 \sys_clksel_i @@ -235491,71 +235831,71 @@ module \ls180 wire output 43 \sys_pll_lck_o attribute \src "ls180.v:44.13-44.20" wire input 40 \sys_rst - attribute \src "ls180.v:291.6-291.15" + attribute \src "ls180.v:278.6-278.15" wire \sys_rst_1 - attribute \src "ls180.v:18.13-18.20" - wire input 14 \uart_rx - attribute \src "ls180.v:17.13-17.20" - wire output 13 \uart_tx - attribute \src "ls180.v:10158.12-10158.15" - memory width 32 size 128 \mem - attribute \src "ls180.v:10178.12-10178.17" - memory width 32 size 128 \mem_1 - attribute \src "ls180.v:10198.12-10198.17" - memory width 32 size 128 \mem_2 - attribute \src "ls180.v:10218.12-10218.17" - memory width 32 size 128 \mem_3 - attribute \src "ls180.v:10238.12-10238.19" + attribute \src "ls180.v:6.13-6.20" + wire input 2 \uart_rx + attribute \src "ls180.v:5.13-5.20" + wire output 1 \uart_tx + attribute \src "ls180.v:10225.12-10225.15" + memory width 64 size 64 \mem + attribute \src "ls180.v:10253.12-10253.17" + memory width 64 size 64 \mem_1 + attribute \src "ls180.v:10281.12-10281.17" + memory width 64 size 64 \mem_2 + attribute \src "ls180.v:10309.12-10309.17" + memory width 64 size 64 \mem_3 + attribute \src "ls180.v:10337.12-10337.19" memory width 25 size 8 \storage - attribute \src "ls180.v:10252.12-10252.21" + attribute \src "ls180.v:10351.12-10351.21" memory width 25 size 8 \storage_1 - attribute \src "ls180.v:10266.12-10266.21" + attribute \src "ls180.v:10365.12-10365.21" memory width 25 size 8 \storage_2 - attribute \src "ls180.v:10280.12-10280.21" + attribute \src "ls180.v:10379.12-10379.21" memory width 25 size 8 \storage_3 - attribute \src "ls180.v:10294.11-10294.20" + attribute \src "ls180.v:10393.11-10393.20" memory width 10 size 16 \storage_4 - attribute \src "ls180.v:10311.11-10311.20" + attribute \src "ls180.v:10410.11-10410.20" memory width 10 size 16 \storage_5 - attribute \src "ls180.v:10328.11-10328.20" + attribute \src "ls180.v:10427.11-10427.20" memory width 10 size 32 \storage_6 - attribute \src "ls180.v:10342.11-10342.20" + attribute \src "ls180.v:10441.11-10441.20" memory width 10 size 32 \storage_7 - attribute \src "ls180.v:2860.68-2860.110" - cell $add $add$ls180.v:2860$34 + attribute \src "ls180.v:2873.56-2873.86" + cell $add $add$ls180.v:2873$50 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_converter0_counter + connect \A \main_converter0_counter connect \B 1'1 - connect \Y $add$ls180.v:2860$34_Y + connect \Y $add$ls180.v:2873$50_Y end - attribute \src "ls180.v:2920.68-2920.110" - cell $add $add$ls180.v:2920$45 + attribute \src "ls180.v:2933.56-2933.86" + cell $add $add$ls180.v:2933$61 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_converter1_counter + connect \A \main_converter1_counter connect \B 1'1 - connect \Y $add$ls180.v:2920$45_Y + connect \Y $add$ls180.v:2933$61_Y end - attribute \src "ls180.v:2980.68-2980.110" - cell $add $add$ls180.v:2980$56 + attribute \src "ls180.v:2993.59-2993.92" + cell $add $add$ls180.v:2993$72 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_converter2_counter + connect \A \main_socbushandler_counter connect \B 1'1 - connect \Y $add$ls180.v:2980$56_Y + connect \Y $add$ls180.v:2993$72_Y end - attribute \src "ls180.v:4143.54-4143.83" - cell $add $add$ls180.v:4143$588 + attribute \src "ls180.v:4172.54-4172.83" + cell $add $add$ls180.v:4172$652 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -235563,10 +235903,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_converter_counter connect \B 1'1 - connect \Y $add$ls180.v:4143$588_Y + connect \Y $add$ls180.v:4172$652_Y end - attribute \src "ls180.v:4243.36-4243.89" - cell $add $add$ls180.v:4243$634 + attribute \src "ls180.v:4272.36-4272.89" + cell $add $add$ls180.v:4272$698 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -235574,10 +235914,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_uart_tx_fifo_level0 connect \B \main_uart_tx_fifo_readable - connect \Y $add$ls180.v:4243$634_Y + connect \Y $add$ls180.v:4272$698_Y end - attribute \src "ls180.v:4273.36-4273.89" - cell $add $add$ls180.v:4273$645 + attribute \src "ls180.v:4302.36-4302.89" + cell $add $add$ls180.v:4302$709 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -235585,10 +235925,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_uart_rx_fifo_level0 connect \B \main_uart_rx_fifo_readable - connect \Y $add$ls180.v:4273$645_Y + connect \Y $add$ls180.v:4302$709_Y end - attribute \src "ls180.v:4328.54-4328.83" - cell $add $add$ls180.v:4328$658 + attribute \src "ls180.v:4368.54-4368.83" + cell $add $add$ls180.v:4368$724 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -235596,10 +235936,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_spimaster27_count connect \B 1'1 - connect \Y $add$ls180.v:4328$658_Y + connect \Y $add$ls180.v:4368$724_Y end - attribute \src "ls180.v:4387.52-4387.79" - cell $add $add$ls180.v:4387$666 + attribute \src "ls180.v:4427.52-4427.79" + cell $add $add$ls180.v:4427$732 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -235607,10 +235947,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_spisdcard_count connect \B 1'1 - connect \Y $add$ls180.v:4387$666_Y + connect \Y $add$ls180.v:4427$732_Y end - attribute \src "ls180.v:4491.58-4491.86" - cell $add $add$ls180.v:4491$694 + attribute \src "ls180.v:4531.58-4531.86" + cell $add $add$ls180.v:4531$760 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -235618,10 +235958,10 @@ module \ls180 parameter \Y_WIDTH 8 connect \A \main_sdphy_init_count connect \B 1'1 - connect \Y $add$ls180.v:4491$694_Y + connect \Y $add$ls180.v:4531$760_Y end - attribute \src "ls180.v:4548.58-4548.86" - cell $add $add$ls180.v:4548$697 + attribute \src "ls180.v:4588.58-4588.86" + cell $add $add$ls180.v:4588$763 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -235629,10 +235969,10 @@ module \ls180 parameter \Y_WIDTH 8 connect \A \main_sdphy_cmdw_count connect \B 1'1 - connect \Y $add$ls180.v:4548$697_Y + connect \Y $add$ls180.v:4588$763_Y end - attribute \src "ls180.v:4565.58-4565.86" - cell $add $add$ls180.v:4565$699 + attribute \src "ls180.v:4605.58-4605.86" + cell $add $add$ls180.v:4605$765 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -235640,10 +235980,10 @@ module \ls180 parameter \Y_WIDTH 8 connect \A \main_sdphy_cmdw_count connect \B 1'1 - connect \Y $add$ls180.v:4565$699_Y + connect \Y $add$ls180.v:4605$765_Y end - attribute \src "ls180.v:4658.59-4658.87" - cell $add $add$ls180.v:4658$716 + attribute \src "ls180.v:4698.59-4698.87" + cell $add $add$ls180.v:4698$782 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -235651,10 +235991,10 @@ module \ls180 parameter \Y_WIDTH 8 connect \A \main_sdphy_cmdr_count connect \B 1'1 - connect \Y $add$ls180.v:4658$716_Y + connect \Y $add$ls180.v:4698$782_Y end - attribute \src "ls180.v:4683.59-4683.87" - cell $add $add$ls180.v:4683$719 + attribute \src "ls180.v:4723.59-4723.87" + cell $add $add$ls180.v:4723$785 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -235662,10 +236002,10 @@ module \ls180 parameter \Y_WIDTH 8 connect \A \main_sdphy_cmdr_count connect \B 1'1 - connect \Y $add$ls180.v:4683$719_Y + connect \Y $add$ls180.v:4723$785_Y end - attribute \src "ls180.v:4805.53-4805.82" - cell $add $add$ls180.v:4805$736 + attribute \src "ls180.v:4845.53-4845.82" + cell $add $add$ls180.v:4845$802 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -235673,10 +236013,10 @@ module \ls180 parameter \Y_WIDTH 8 connect \A \main_sdphy_dataw_count connect \B 1'1 - connect \Y $add$ls180.v:4805$736_Y + connect \Y $add$ls180.v:4845$802_Y end - attribute \src "ls180.v:4916.65-4916.114" - cell $add $add$ls180.v:4916$750 + attribute \src "ls180.v:4956.65-4956.114" + cell $add $add$ls180.v:4956$816 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -235684,10 +236024,10 @@ module \ls180 parameter \Y_WIDTH 10 connect \A \main_sdphy_datar_sink_payload_block_length connect \B 4'1000 - connect \Y $add$ls180.v:4916$750_Y + connect \Y $add$ls180.v:4956$816_Y end - attribute \src "ls180.v:4921.62-4921.91" - cell $add $add$ls180.v:4921$753 + attribute \src "ls180.v:4961.62-4961.91" + cell $add $add$ls180.v:4961$819 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -235695,10 +236035,10 @@ module \ls180 parameter \Y_WIDTH 10 connect \A \main_sdphy_datar_count connect \B 1'1 - connect \Y $add$ls180.v:4921$753_Y + connect \Y $add$ls180.v:4961$819_Y end - attribute \src "ls180.v:4947.61-4947.90" - cell $add $add$ls180.v:4947$756 + attribute \src "ls180.v:4987.61-4987.90" + cell $add $add$ls180.v:4987$822 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -235706,10 +236046,10 @@ module \ls180 parameter \Y_WIDTH 10 connect \A \main_sdphy_datar_count connect \B 1'1 - connect \Y $add$ls180.v:4947$756_Y + connect \Y $add$ls180.v:4987$822_Y end - attribute \src "ls180.v:5151.80-5151.117" - cell $add $add$ls180.v:5151$941 + attribute \src "ls180.v:5191.80-5191.117" + cell $add $add$ls180.v:5191$1007 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -235717,10 +236057,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdcore_crc16_inserter_cnt connect \B 1'1 - connect \Y $add$ls180.v:5151$941_Y + connect \Y $add$ls180.v:5191$1007_Y end - attribute \src "ls180.v:5345.54-5345.82" - cell $add $add$ls180.v:5345$1016 + attribute \src "ls180.v:5385.54-5385.82" + cell $add $add$ls180.v:5385$1082 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -235728,10 +236068,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdcore_cmd_count connect \B 1'1 - connect \Y $add$ls180.v:5345$1016_Y + connect \Y $add$ls180.v:5385$1082_Y end - attribute \src "ls180.v:5397.55-5397.84" - cell $add $add$ls180.v:5397$1026 + attribute \src "ls180.v:5437.55-5437.84" + cell $add $add$ls180.v:5437$1092 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -235739,10 +236079,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdcore_data_count connect \B 1'1 - connect \Y $add$ls180.v:5397$1026_Y + connect \Y $add$ls180.v:5437$1092_Y end - attribute \src "ls180.v:5423.57-5423.86" - cell $add $add$ls180.v:5423$1034 + attribute \src "ls180.v:5463.57-5463.86" + cell $add $add$ls180.v:5463$1100 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -235750,10 +236090,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdcore_data_count connect \B 1'1 - connect \Y $add$ls180.v:5423$1034_Y + connect \Y $add$ls180.v:5463$1100_Y end - attribute \src "ls180.v:5544.51-5544.134" - cell $add $add$ls180.v:5544$1050 + attribute \src "ls180.v:5584.51-5584.134" + cell $add $add$ls180.v:5584$1116 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -235761,10 +236101,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdblock2mem_wishbonedmawriter_base connect \B \main_sdblock2mem_wishbonedmawriter_offset - connect \Y $add$ls180.v:5544$1050_Y + connect \Y $add$ls180.v:5584$1116_Y end - attribute \src "ls180.v:5547.77-5547.125" - cell $add $add$ls180.v:5547$1052 + attribute \src "ls180.v:5587.77-5587.125" + cell $add $add$ls180.v:5587$1118 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -235772,10 +236112,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdblock2mem_wishbonedmawriter_offset connect \B 1'1 - connect \Y $add$ls180.v:5547$1052_Y + connect \Y $add$ls180.v:5587$1118_Y end - attribute \src "ls180.v:5640.50-5640.105" - cell $add $add$ls180.v:5640$1061 + attribute \src "ls180.v:5680.50-5680.105" + cell $add $add$ls180.v:5680$1127 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -235783,10 +236123,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdmem2block_dma_base connect \B \main_sdmem2block_dma_offset - connect \Y $add$ls180.v:5640$1061_Y + connect \Y $add$ls180.v:5680$1127_Y end - attribute \src "ls180.v:5642.77-5642.111" - cell $add $add$ls180.v:5642$1062 + attribute \src "ls180.v:5682.77-5682.111" + cell $add $add$ls180.v:5682$1128 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -235794,10 +236134,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdmem2block_dma_offset connect \B 1'1 - connect \Y $add$ls180.v:5642$1062_Y + connect \Y $add$ls180.v:5682$1128_Y end - attribute \src "ls180.v:7589.36-7589.70" - cell $add $add$ls180.v:7589$2472 + attribute \src "ls180.v:7644.36-7644.70" + cell $add $add$ls180.v:7644$2539 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -235805,10 +236145,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_libresocsim_bus_errors connect \B 1'1 - connect \Y $add$ls180.v:7589$2472_Y + connect \Y $add$ls180.v:7644$2539_Y end - attribute \src "ls180.v:7686.37-7686.72" - cell $add $add$ls180.v:7686$2502 + attribute \src "ls180.v:7741.37-7741.72" + cell $add $add$ls180.v:7741$2569 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -235816,10 +236156,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_sequencer_counter connect \B 1'1 - connect \Y $add$ls180.v:7686$2502_Y + connect \Y $add$ls180.v:7741$2569_Y end - attribute \src "ls180.v:7703.60-7703.119" - cell $add $add$ls180.v:7703$2506 + attribute \src "ls180.v:7758.60-7758.119" + cell $add $add$ls180.v:7758$2573 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -235827,10 +236167,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_produce connect \B 1'1 - connect \Y $add$ls180.v:7703$2506_Y + connect \Y $add$ls180.v:7758$2573_Y end - attribute \src "ls180.v:7706.60-7706.119" - cell $add $add$ls180.v:7706$2507 + attribute \src "ls180.v:7761.60-7761.119" + cell $add $add$ls180.v:7761$2574 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -235838,10 +236178,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_consume connect \B 1'1 - connect \Y $add$ls180.v:7706$2507_Y + connect \Y $add$ls180.v:7761$2574_Y end - attribute \src "ls180.v:7710.59-7710.116" - cell $add $add$ls180.v:7710$2512 + attribute \src "ls180.v:7765.59-7765.116" + cell $add $add$ls180.v:7765$2579 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -235849,10 +236189,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $add$ls180.v:7710$2512_Y + connect \Y $add$ls180.v:7765$2579_Y end - attribute \src "ls180.v:7749.60-7749.119" - cell $add $add$ls180.v:7749$2522 + attribute \src "ls180.v:7804.60-7804.119" + cell $add $add$ls180.v:7804$2589 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -235860,10 +236200,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_produce connect \B 1'1 - connect \Y $add$ls180.v:7749$2522_Y + connect \Y $add$ls180.v:7804$2589_Y end - attribute \src "ls180.v:7752.60-7752.119" - cell $add $add$ls180.v:7752$2523 + attribute \src "ls180.v:7807.60-7807.119" + cell $add $add$ls180.v:7807$2590 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -235871,10 +236211,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_consume connect \B 1'1 - connect \Y $add$ls180.v:7752$2523_Y + connect \Y $add$ls180.v:7807$2590_Y end - attribute \src "ls180.v:7756.59-7756.116" - cell $add $add$ls180.v:7756$2528 + attribute \src "ls180.v:7811.59-7811.116" + cell $add $add$ls180.v:7811$2595 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -235882,10 +236222,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $add$ls180.v:7756$2528_Y + connect \Y $add$ls180.v:7811$2595_Y end - attribute \src "ls180.v:7795.60-7795.119" - cell $add $add$ls180.v:7795$2538 + attribute \src "ls180.v:7850.60-7850.119" + cell $add $add$ls180.v:7850$2605 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -235893,10 +236233,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_produce connect \B 1'1 - connect \Y $add$ls180.v:7795$2538_Y + connect \Y $add$ls180.v:7850$2605_Y end - attribute \src "ls180.v:7798.60-7798.119" - cell $add $add$ls180.v:7798$2539 + attribute \src "ls180.v:7853.60-7853.119" + cell $add $add$ls180.v:7853$2606 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -235904,10 +236244,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_consume connect \B 1'1 - connect \Y $add$ls180.v:7798$2539_Y + connect \Y $add$ls180.v:7853$2606_Y end - attribute \src "ls180.v:7802.59-7802.116" - cell $add $add$ls180.v:7802$2544 + attribute \src "ls180.v:7857.59-7857.116" + cell $add $add$ls180.v:7857$2611 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -235915,10 +236255,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $add$ls180.v:7802$2544_Y + connect \Y $add$ls180.v:7857$2611_Y end - attribute \src "ls180.v:7841.60-7841.119" - cell $add $add$ls180.v:7841$2554 + attribute \src "ls180.v:7896.60-7896.119" + cell $add $add$ls180.v:7896$2621 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -235926,10 +236266,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_produce connect \B 1'1 - connect \Y $add$ls180.v:7841$2554_Y + connect \Y $add$ls180.v:7896$2621_Y end - attribute \src "ls180.v:7844.60-7844.119" - cell $add $add$ls180.v:7844$2555 + attribute \src "ls180.v:7899.60-7899.119" + cell $add $add$ls180.v:7899$2622 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -235937,10 +236277,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_consume connect \B 1'1 - connect \Y $add$ls180.v:7844$2555_Y + connect \Y $add$ls180.v:7899$2622_Y end - attribute \src "ls180.v:7848.59-7848.116" - cell $add $add$ls180.v:7848$2560 + attribute \src "ls180.v:7903.59-7903.116" + cell $add $add$ls180.v:7903$2627 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -235948,10 +236288,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $add$ls180.v:7848$2560_Y + connect \Y $add$ls180.v:7903$2627_Y end - attribute \src "ls180.v:8078.34-8078.66" - cell $add $add$ls180.v:8078$2614 + attribute \src "ls180.v:8133.34-8133.66" + cell $add $add$ls180.v:8133$2681 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -235959,10 +236299,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_uart_phy_tx_bitcount connect \B 1'1 - connect \Y $add$ls180.v:8078$2614_Y + connect \Y $add$ls180.v:8133$2681_Y end - attribute \src "ls180.v:8094.73-8094.131" - cell $add $add$ls180.v:8094$2617 + attribute \src "ls180.v:8149.73-8149.131" + cell $add $add$ls180.v:8149$2684 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -235970,10 +236310,10 @@ module \ls180 parameter \Y_WIDTH 33 connect \A \main_uart_phy_phase_accumulator_tx connect \B \main_uart_phy_storage - connect \Y $add$ls180.v:8094$2617_Y + connect \Y $add$ls180.v:8149$2684_Y end - attribute \src "ls180.v:8107.34-8107.66" - cell $add $add$ls180.v:8107$2621 + attribute \src "ls180.v:8162.34-8162.66" + cell $add $add$ls180.v:8162$2688 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -235981,10 +236321,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_uart_phy_rx_bitcount connect \B 1'1 - connect \Y $add$ls180.v:8107$2621_Y + connect \Y $add$ls180.v:8162$2688_Y end - attribute \src "ls180.v:8126.73-8126.131" - cell $add $add$ls180.v:8126$2624 + attribute \src "ls180.v:8181.73-8181.131" + cell $add $add$ls180.v:8181$2691 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -235992,10 +236332,10 @@ module \ls180 parameter \Y_WIDTH 33 connect \A \main_uart_phy_phase_accumulator_rx connect \B \main_uart_phy_storage - connect \Y $add$ls180.v:8126$2624_Y + connect \Y $add$ls180.v:8181$2691_Y end - attribute \src "ls180.v:8152.33-8152.65" - cell $add $add$ls180.v:8152$2632 + attribute \src "ls180.v:8207.33-8207.65" + cell $add $add$ls180.v:8207$2699 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -236003,10 +236343,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_uart_tx_fifo_produce connect \B 1'1 - connect \Y $add$ls180.v:8152$2632_Y + connect \Y $add$ls180.v:8207$2699_Y end - attribute \src "ls180.v:8155.33-8155.65" - cell $add $add$ls180.v:8155$2633 + attribute \src "ls180.v:8210.33-8210.65" + cell $add $add$ls180.v:8210$2700 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -236014,10 +236354,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_uart_tx_fifo_consume connect \B 1'1 - connect \Y $add$ls180.v:8155$2633_Y + connect \Y $add$ls180.v:8210$2700_Y end - attribute \src "ls180.v:8159.33-8159.64" - cell $add $add$ls180.v:8159$2638 + attribute \src "ls180.v:8214.33-8214.64" + cell $add $add$ls180.v:8214$2705 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -236025,10 +236365,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_uart_tx_fifo_level0 connect \B 1'1 - connect \Y $add$ls180.v:8159$2638_Y + connect \Y $add$ls180.v:8214$2705_Y end - attribute \src "ls180.v:8174.33-8174.65" - cell $add $add$ls180.v:8174$2643 + attribute \src "ls180.v:8229.33-8229.65" + cell $add $add$ls180.v:8229$2710 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -236036,10 +236376,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_uart_rx_fifo_produce connect \B 1'1 - connect \Y $add$ls180.v:8174$2643_Y + connect \Y $add$ls180.v:8229$2710_Y end - attribute \src "ls180.v:8177.33-8177.65" - cell $add $add$ls180.v:8177$2644 + attribute \src "ls180.v:8232.33-8232.65" + cell $add $add$ls180.v:8232$2711 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -236047,10 +236387,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_uart_rx_fifo_consume connect \B 1'1 - connect \Y $add$ls180.v:8177$2644_Y + connect \Y $add$ls180.v:8232$2711_Y end - attribute \src "ls180.v:8181.33-8181.64" - cell $add $add$ls180.v:8181$2649 + attribute \src "ls180.v:8236.33-8236.64" + cell $add $add$ls180.v:8236$2716 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -236058,10 +236398,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_uart_rx_fifo_level0 connect \B 1'1 - connect \Y $add$ls180.v:8181$2649_Y + connect \Y $add$ls180.v:8236$2716_Y end - attribute \src "ls180.v:8202.35-8202.70" - cell $add $add$ls180.v:8202$2651 + attribute \src "ls180.v:8257.35-8257.70" + cell $add $add$ls180.v:8257$2718 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -236069,10 +236409,10 @@ module \ls180 parameter \Y_WIDTH 16 connect \A \main_spimaster30_clk_divider connect \B 1'1 - connect \Y $add$ls180.v:8202$2651_Y + connect \Y $add$ls180.v:8257$2718_Y end - attribute \src "ls180.v:8237.34-8237.68" - cell $add $add$ls180.v:8237$2656 + attribute \src "ls180.v:8292.34-8292.68" + cell $add $add$ls180.v:8292$2723 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -236080,10 +236420,10 @@ module \ls180 parameter \Y_WIDTH 16 connect \A \main_spisdcard_clk_divider1 connect \B 1'1 - connect \Y $add$ls180.v:8237$2656_Y + connect \Y $add$ls180.v:8292$2723_Y end - attribute \src "ls180.v:8273.25-8273.49" - cell $add $add$ls180.v:8273$2661 + attribute \src "ls180.v:8328.25-8328.49" + cell $add $add$ls180.v:8328$2728 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -236091,10 +236431,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_pwm0_counter connect \B 1'1 - connect \Y $add$ls180.v:8273$2661_Y + connect \Y $add$ls180.v:8328$2728_Y end - attribute \src "ls180.v:8287.25-8287.49" - cell $add $add$ls180.v:8287$2665 + attribute \src "ls180.v:8342.25-8342.49" + cell $add $add$ls180.v:8342$2732 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -236102,10 +236442,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_pwm1_counter connect \B 1'1 - connect \Y $add$ls180.v:8287$2665_Y + connect \Y $add$ls180.v:8342$2732_Y end - attribute \src "ls180.v:8301.31-8301.61" - cell $add $add$ls180.v:8301$2670 + attribute \src "ls180.v:8356.31-8356.61" + cell $add $add$ls180.v:8356$2737 parameter \A_SIGNED 0 parameter \A_WIDTH 9 parameter \B_SIGNED 0 @@ -236113,10 +236453,10 @@ module \ls180 parameter \Y_WIDTH 9 connect \A \main_sdphy_clocker_clks connect \B 1'1 - connect \Y $add$ls180.v:8301$2670_Y + connect \Y $add$ls180.v:8356$2737_Y end - attribute \src "ls180.v:8324.45-8324.88" - cell $add $add$ls180.v:8324$2674 + attribute \src "ls180.v:8379.45-8379.88" + cell $add $add$ls180.v:8379$2741 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -236124,10 +236464,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdphy_cmdr_cmdr_converter_demux connect \B 1'1 - connect \Y $add$ls180.v:8324$2674_Y + connect \Y $add$ls180.v:8379$2741_Y end - attribute \src "ls180.v:8370.71-8370.114" - cell $add $add$ls180.v:8370$2680 + attribute \src "ls180.v:8425.71-8425.114" + cell $add $add$ls180.v:8425$2747 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -236135,10 +236475,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdphy_cmdr_cmdr_converter_demux connect \B 1'1 - connect \Y $add$ls180.v:8370$2680_Y + connect \Y $add$ls180.v:8425$2747_Y end - attribute \src "ls180.v:8405.46-8405.90" - cell $add $add$ls180.v:8405$2686 + attribute \src "ls180.v:8460.46-8460.90" + cell $add $add$ls180.v:8460$2753 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -236146,10 +236486,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdphy_dataw_crcr_converter_demux connect \B 1'1 - connect \Y $add$ls180.v:8405$2686_Y + connect \Y $add$ls180.v:8460$2753_Y end - attribute \src "ls180.v:8451.72-8451.116" - cell $add $add$ls180.v:8451$2692 + attribute \src "ls180.v:8506.72-8506.116" + cell $add $add$ls180.v:8506$2759 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -236157,10 +236497,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdphy_dataw_crcr_converter_demux connect \B 1'1 - connect \Y $add$ls180.v:8451$2692_Y + connect \Y $add$ls180.v:8506$2759_Y end - attribute \src "ls180.v:8484.47-8484.92" - cell $add $add$ls180.v:8484$2698 + attribute \src "ls180.v:8539.47-8539.92" + cell $add $add$ls180.v:8539$2765 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -236168,10 +236508,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_converter_demux connect \B 1'1 - connect \Y $add$ls180.v:8484$2698_Y + connect \Y $add$ls180.v:8539$2765_Y end - attribute \src "ls180.v:8512.73-8512.118" - cell $add $add$ls180.v:8512$2704 + attribute \src "ls180.v:8567.73-8567.118" + cell $add $add$ls180.v:8567$2771 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -236179,10 +236519,10 @@ module \ls180 parameter \Y_WIDTH 2 connect \A \main_sdphy_datar_datar_converter_demux connect \B 1'1 - connect \Y $add$ls180.v:8512$2704_Y + connect \Y $add$ls180.v:8567$2771_Y end - attribute \src "ls180.v:8624.39-8624.75" - cell $add $add$ls180.v:8624$2717 + attribute \src "ls180.v:8679.39-8679.75" + cell $add $add$ls180.v:8679$2784 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -236190,10 +236530,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdcore_crc16_checker_cnt connect \B 1'1 - connect \Y $add$ls180.v:8624$2717_Y + connect \Y $add$ls180.v:8679$2784_Y end - attribute \src "ls180.v:8685.37-8685.73" - cell $add $add$ls180.v:8685$2721 + attribute \src "ls180.v:8740.37-8740.73" + cell $add $add$ls180.v:8740$2788 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -236201,10 +236541,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_sdblock2mem_fifo_produce connect \B 1'1 - connect \Y $add$ls180.v:8685$2721_Y + connect \Y $add$ls180.v:8740$2788_Y end - attribute \src "ls180.v:8688.37-8688.73" - cell $add $add$ls180.v:8688$2722 + attribute \src "ls180.v:8743.37-8743.73" + cell $add $add$ls180.v:8743$2789 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -236212,10 +236552,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_sdblock2mem_fifo_consume connect \B 1'1 - connect \Y $add$ls180.v:8688$2722_Y + connect \Y $add$ls180.v:8743$2789_Y end - attribute \src "ls180.v:8692.36-8692.70" - cell $add $add$ls180.v:8692$2727 + attribute \src "ls180.v:8747.36-8747.70" + cell $add $add$ls180.v:8747$2794 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -236223,43 +236563,43 @@ module \ls180 parameter \Y_WIDTH 6 connect \A \main_sdblock2mem_fifo_level connect \B 1'1 - connect \Y $add$ls180.v:8692$2727_Y + connect \Y $add$ls180.v:8747$2794_Y end - attribute \src "ls180.v:8707.41-8707.80" - cell $add $add$ls180.v:8707$2731 + attribute \src "ls180.v:8762.41-8762.80" + cell $add $add$ls180.v:8762$2798 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 2 + parameter \Y_WIDTH 3 connect \A \main_sdblock2mem_converter_demux connect \B 1'1 - connect \Y $add$ls180.v:8707$2731_Y + connect \Y $add$ls180.v:8762$2798_Y end - attribute \src "ls180.v:8741.67-8741.106" - cell $add $add$ls180.v:8741$2737 + attribute \src "ls180.v:8808.67-8808.106" + cell $add $add$ls180.v:8808$2804 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 + parameter \Y_WIDTH 4 connect \A \main_sdblock2mem_converter_demux connect \B 1'1 - connect \Y $add$ls180.v:8741$2737_Y + connect \Y $add$ls180.v:8808$2804_Y end - attribute \src "ls180.v:8767.39-8767.76" - cell $add $add$ls180.v:8767$2739 + attribute \src "ls180.v:8834.39-8834.76" + cell $add $add$ls180.v:8834$2806 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 2 + parameter \Y_WIDTH 3 connect \A \main_sdmem2block_converter_mux connect \B 1'1 - connect \Y $add$ls180.v:8767$2739_Y + connect \Y $add$ls180.v:8834$2806_Y end - attribute \src "ls180.v:8771.37-8771.73" - cell $add $add$ls180.v:8771$2743 + attribute \src "ls180.v:8838.37-8838.73" + cell $add $add$ls180.v:8838$2810 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -236267,10 +236607,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_sdmem2block_fifo_produce connect \B 1'1 - connect \Y $add$ls180.v:8771$2743_Y + connect \Y $add$ls180.v:8838$2810_Y end - attribute \src "ls180.v:8774.37-8774.73" - cell $add $add$ls180.v:8774$2744 + attribute \src "ls180.v:8841.37-8841.73" + cell $add $add$ls180.v:8841$2811 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -236278,10 +236618,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_sdmem2block_fifo_consume connect \B 1'1 - connect \Y $add$ls180.v:8774$2744_Y + connect \Y $add$ls180.v:8841$2811_Y end - attribute \src "ls180.v:8778.36-8778.70" - cell $add $add$ls180.v:8778$2749 + attribute \src "ls180.v:8845.36-8845.70" + cell $add $add$ls180.v:8845$2816 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -236289,76 +236629,76 @@ module \ls180 parameter \Y_WIDTH 6 connect \A \main_sdmem2block_fifo_level connect \B 1'1 - connect \Y $add$ls180.v:8778$2749_Y + connect \Y $add$ls180.v:8845$2816_Y end - attribute \src "ls180.v:2854.9-2854.80" - cell $and $and$ls180.v:2854$29 + attribute \src "ls180.v:2867.9-2867.90" + cell $and $and$ls180.v:2867$45 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_libresoc_ibus_stb - connect \B \main_libresocsim_libresoc_ibus_cyc - connect \Y $and$ls180.v:2854$29_Y + connect \A \main_interface0_converted_interface_stb + connect \B \main_interface0_converted_interface_cyc + connect \Y $and$ls180.v:2867$45_Y end - attribute \src "ls180.v:2872.9-2872.80" - cell $and $and$ls180.v:2872$36 + attribute \src "ls180.v:2885.9-2885.90" + cell $and $and$ls180.v:2885$52 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_libresoc_ibus_stb - connect \B \main_libresocsim_libresoc_ibus_cyc - connect \Y $and$ls180.v:2872$36_Y + connect \A \main_interface0_converted_interface_stb + connect \B \main_interface0_converted_interface_cyc + connect \Y $and$ls180.v:2885$52_Y end - attribute \src "ls180.v:2914.9-2914.80" - cell $and $and$ls180.v:2914$40 + attribute \src "ls180.v:2927.9-2927.90" + cell $and $and$ls180.v:2927$56 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_libresoc_dbus_stb - connect \B \main_libresocsim_libresoc_dbus_cyc - connect \Y $and$ls180.v:2914$40_Y + connect \A \main_interface1_converted_interface_stb + connect \B \main_interface1_converted_interface_cyc + connect \Y $and$ls180.v:2927$56_Y end - attribute \src "ls180.v:2932.9-2932.80" - cell $and $and$ls180.v:2932$47 + attribute \src "ls180.v:2945.9-2945.90" + cell $and $and$ls180.v:2945$63 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_libresoc_dbus_stb - connect \B \main_libresocsim_libresoc_dbus_cyc - connect \Y $and$ls180.v:2932$47_Y + connect \A \main_interface1_converted_interface_stb + connect \B \main_interface1_converted_interface_cyc + connect \Y $and$ls180.v:2945$63_Y end - attribute \src "ls180.v:2974.9-2974.86" - cell $and $and$ls180.v:2974$51 + attribute \src "ls180.v:2987.9-2987.96" + cell $and $and$ls180.v:2987$67 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_libresoc_jtag_wb_stb - connect \B \main_libresocsim_libresoc_jtag_wb_cyc - connect \Y $and$ls180.v:2974$51_Y + connect \A \main_socbushandler_converted_interface_stb + connect \B \main_socbushandler_converted_interface_cyc + connect \Y $and$ls180.v:2987$67_Y end - attribute \src "ls180.v:2992.9-2992.86" - cell $and $and$ls180.v:2992$58 + attribute \src "ls180.v:3005.9-3005.96" + cell $and $and$ls180.v:3005$74 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_libresoc_jtag_wb_stb - connect \B \main_libresocsim_libresoc_jtag_wb_cyc - connect \Y $and$ls180.v:2992$58_Y + connect \A \main_socbushandler_converted_interface_stb + connect \B \main_socbushandler_converted_interface_cyc + connect \Y $and$ls180.v:3005$74_Y end - attribute \src "ls180.v:3002.31-3002.90" - cell $and $and$ls180.v:3002$60 + attribute \src "ls180.v:3015.31-3015.90" + cell $and $and$ls180.v:3015$76 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -236366,32 +236706,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_ram_bus_cyc connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:3002$60_Y + connect \Y $and$ls180.v:3015$76_Y end - attribute \src "ls180.v:3002.30-3002.121" - cell $and $and$ls180.v:3002$61 + attribute \src "ls180.v:3015.30-3015.121" + cell $and $and$ls180.v:3015$77 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3002$60_Y + connect \A $and$ls180.v:3015$76_Y connect \B \main_libresocsim_ram_bus_we - connect \Y $and$ls180.v:3002$61_Y + connect \Y $and$ls180.v:3015$77_Y end - attribute \src "ls180.v:3002.29-3002.156" - cell $and $and$ls180.v:3002$62 + attribute \src "ls180.v:3015.29-3015.156" + cell $and $and$ls180.v:3015$78 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3002$61_Y + connect \A $and$ls180.v:3015$77_Y connect \B \main_libresocsim_ram_bus_sel [0] - connect \Y $and$ls180.v:3002$62_Y + connect \Y $and$ls180.v:3015$78_Y end - attribute \src "ls180.v:3003.31-3003.90" - cell $and $and$ls180.v:3003$63 + attribute \src "ls180.v:3016.31-3016.90" + cell $and $and$ls180.v:3016$79 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -236399,32 +236739,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_ram_bus_cyc connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:3003$63_Y + connect \Y $and$ls180.v:3016$79_Y end - attribute \src "ls180.v:3003.30-3003.121" - cell $and $and$ls180.v:3003$64 + attribute \src "ls180.v:3016.30-3016.121" + cell $and $and$ls180.v:3016$80 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3003$63_Y + connect \A $and$ls180.v:3016$79_Y connect \B \main_libresocsim_ram_bus_we - connect \Y $and$ls180.v:3003$64_Y + connect \Y $and$ls180.v:3016$80_Y end - attribute \src "ls180.v:3003.29-3003.156" - cell $and $and$ls180.v:3003$65 + attribute \src "ls180.v:3016.29-3016.156" + cell $and $and$ls180.v:3016$81 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3003$64_Y + connect \A $and$ls180.v:3016$80_Y connect \B \main_libresocsim_ram_bus_sel [1] - connect \Y $and$ls180.v:3003$65_Y + connect \Y $and$ls180.v:3016$81_Y end - attribute \src "ls180.v:3004.31-3004.90" - cell $and $and$ls180.v:3004$66 + attribute \src "ls180.v:3017.31-3017.90" + cell $and $and$ls180.v:3017$82 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -236432,32 +236772,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_ram_bus_cyc connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:3004$66_Y + connect \Y $and$ls180.v:3017$82_Y end - attribute \src "ls180.v:3004.30-3004.121" - cell $and $and$ls180.v:3004$67 + attribute \src "ls180.v:3017.30-3017.121" + cell $and $and$ls180.v:3017$83 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3004$66_Y + connect \A $and$ls180.v:3017$82_Y connect \B \main_libresocsim_ram_bus_we - connect \Y $and$ls180.v:3004$67_Y + connect \Y $and$ls180.v:3017$83_Y end - attribute \src "ls180.v:3004.29-3004.156" - cell $and $and$ls180.v:3004$68 + attribute \src "ls180.v:3017.29-3017.156" + cell $and $and$ls180.v:3017$84 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3004$67_Y + connect \A $and$ls180.v:3017$83_Y connect \B \main_libresocsim_ram_bus_sel [2] - connect \Y $and$ls180.v:3004$68_Y + connect \Y $and$ls180.v:3017$84_Y end - attribute \src "ls180.v:3005.31-3005.90" - cell $and $and$ls180.v:3005$69 + attribute \src "ls180.v:3018.31-3018.90" + cell $and $and$ls180.v:3018$85 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -236465,32 +236805,164 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_ram_bus_cyc connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:3005$69_Y + connect \Y $and$ls180.v:3018$85_Y end - attribute \src "ls180.v:3005.30-3005.121" - cell $and $and$ls180.v:3005$70 + attribute \src "ls180.v:3018.30-3018.121" + cell $and $and$ls180.v:3018$86 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3005$69_Y + connect \A $and$ls180.v:3018$85_Y connect \B \main_libresocsim_ram_bus_we - connect \Y $and$ls180.v:3005$70_Y + connect \Y $and$ls180.v:3018$86_Y end - attribute \src "ls180.v:3005.29-3005.156" - cell $and $and$ls180.v:3005$71 + attribute \src "ls180.v:3018.29-3018.156" + cell $and $and$ls180.v:3018$87 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3005$70_Y + connect \A $and$ls180.v:3018$86_Y connect \B \main_libresocsim_ram_bus_sel [3] - connect \Y $and$ls180.v:3005$71_Y + connect \Y $and$ls180.v:3018$87_Y + end + attribute \src "ls180.v:3019.31-3019.90" + cell $and $and$ls180.v:3019$88 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_cyc + connect \B \main_libresocsim_ram_bus_stb + connect \Y $and$ls180.v:3019$88_Y + end + attribute \src "ls180.v:3019.30-3019.121" + cell $and $and$ls180.v:3019$89 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3019$88_Y + connect \B \main_libresocsim_ram_bus_we + connect \Y $and$ls180.v:3019$89_Y + end + attribute \src "ls180.v:3019.29-3019.156" + cell $and $and$ls180.v:3019$90 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3019$89_Y + connect \B \main_libresocsim_ram_bus_sel [4] + connect \Y $and$ls180.v:3019$90_Y + end + attribute \src "ls180.v:3020.31-3020.90" + cell $and $and$ls180.v:3020$91 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_cyc + connect \B \main_libresocsim_ram_bus_stb + connect \Y $and$ls180.v:3020$91_Y + end + attribute \src "ls180.v:3020.30-3020.121" + cell $and $and$ls180.v:3020$92 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3020$91_Y + connect \B \main_libresocsim_ram_bus_we + connect \Y $and$ls180.v:3020$92_Y + end + attribute \src "ls180.v:3020.29-3020.156" + cell $and $and$ls180.v:3020$93 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3020$92_Y + connect \B \main_libresocsim_ram_bus_sel [5] + connect \Y $and$ls180.v:3020$93_Y + end + attribute \src "ls180.v:3021.31-3021.90" + cell $and $and$ls180.v:3021$94 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_cyc + connect \B \main_libresocsim_ram_bus_stb + connect \Y $and$ls180.v:3021$94_Y + end + attribute \src "ls180.v:3021.30-3021.121" + cell $and $and$ls180.v:3021$95 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3021$94_Y + connect \B \main_libresocsim_ram_bus_we + connect \Y $and$ls180.v:3021$95_Y + end + attribute \src "ls180.v:3021.29-3021.156" + cell $and $and$ls180.v:3021$96 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3021$95_Y + connect \B \main_libresocsim_ram_bus_sel [6] + connect \Y $and$ls180.v:3021$96_Y + end + attribute \src "ls180.v:3022.31-3022.90" + cell $and $and$ls180.v:3022$97 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_cyc + connect \B \main_libresocsim_ram_bus_stb + connect \Y $and$ls180.v:3022$97_Y end - attribute \src "ls180.v:3014.7-3014.89" - cell $and $and$ls180.v:3014$74 + attribute \src "ls180.v:3022.30-3022.121" + cell $and $and$ls180.v:3022$98 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3022$97_Y + connect \B \main_libresocsim_ram_bus_we + connect \Y $and$ls180.v:3022$98_Y + end + attribute \src "ls180.v:3022.29-3022.156" + cell $and $and$ls180.v:3022$99 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3022$98_Y + connect \B \main_libresocsim_ram_bus_sel [7] + connect \Y $and$ls180.v:3022$99_Y + end + attribute \src "ls180.v:3031.7-3031.89" + cell $and $and$ls180.v:3031$102 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -236498,10 +236970,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_eventmanager_pending_re connect \B \main_libresocsim_eventmanager_pending_r - connect \Y $and$ls180.v:3014$74_Y + connect \Y $and$ls180.v:3031$102_Y end - attribute \src "ls180.v:3019.32-3019.111" - cell $and $and$ls180.v:3019$75 + attribute \src "ls180.v:3036.32-3036.111" + cell $and $and$ls180.v:3036$103 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -236509,10 +236981,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_eventmanager_pending_w connect \B \main_libresocsim_eventmanager_storage - connect \Y $and$ls180.v:3019$75_Y + connect \Y $and$ls180.v:3036$103_Y end - attribute \src "ls180.v:3023.25-3023.82" - cell $and $and$ls180.v:3023$77 + attribute \src "ls180.v:3040.25-3040.82" + cell $and $and$ls180.v:3040$105 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -236520,32 +236992,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_interface0_ram_bus_cyc connect \B \main_interface0_ram_bus_stb - connect \Y $and$ls180.v:3023$77_Y + connect \Y $and$ls180.v:3040$105_Y end - attribute \src "ls180.v:3023.24-3023.112" - cell $and $and$ls180.v:3023$78 + attribute \src "ls180.v:3040.24-3040.112" + cell $and $and$ls180.v:3040$106 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3023$77_Y + connect \A $and$ls180.v:3040$105_Y connect \B \main_interface0_ram_bus_we - connect \Y $and$ls180.v:3023$78_Y + connect \Y $and$ls180.v:3040$106_Y end - attribute \src "ls180.v:3023.23-3023.146" - cell $and $and$ls180.v:3023$79 + attribute \src "ls180.v:3040.23-3040.146" + cell $and $and$ls180.v:3040$107 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3023$78_Y + connect \A $and$ls180.v:3040$106_Y connect \B \main_interface0_ram_bus_sel [0] - connect \Y $and$ls180.v:3023$79_Y + connect \Y $and$ls180.v:3040$107_Y end - attribute \src "ls180.v:3024.25-3024.82" - cell $and $and$ls180.v:3024$80 + attribute \src "ls180.v:3041.25-3041.82" + cell $and $and$ls180.v:3041$108 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -236553,32 +237025,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_interface0_ram_bus_cyc connect \B \main_interface0_ram_bus_stb - connect \Y $and$ls180.v:3024$80_Y + connect \Y $and$ls180.v:3041$108_Y end - attribute \src "ls180.v:3024.24-3024.112" - cell $and $and$ls180.v:3024$81 + attribute \src "ls180.v:3041.24-3041.112" + cell $and $and$ls180.v:3041$109 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3024$80_Y + connect \A $and$ls180.v:3041$108_Y connect \B \main_interface0_ram_bus_we - connect \Y $and$ls180.v:3024$81_Y + connect \Y $and$ls180.v:3041$109_Y end - attribute \src "ls180.v:3024.23-3024.146" - cell $and $and$ls180.v:3024$82 + attribute \src "ls180.v:3041.23-3041.146" + cell $and $and$ls180.v:3041$110 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3024$81_Y + connect \A $and$ls180.v:3041$109_Y connect \B \main_interface0_ram_bus_sel [1] - connect \Y $and$ls180.v:3024$82_Y + connect \Y $and$ls180.v:3041$110_Y end - attribute \src "ls180.v:3025.25-3025.82" - cell $and $and$ls180.v:3025$83 + attribute \src "ls180.v:3042.25-3042.82" + cell $and $and$ls180.v:3042$111 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -236586,32 +237058,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_interface0_ram_bus_cyc connect \B \main_interface0_ram_bus_stb - connect \Y $and$ls180.v:3025$83_Y + connect \Y $and$ls180.v:3042$111_Y end - attribute \src "ls180.v:3025.24-3025.112" - cell $and $and$ls180.v:3025$84 + attribute \src "ls180.v:3042.24-3042.112" + cell $and $and$ls180.v:3042$112 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3025$83_Y + connect \A $and$ls180.v:3042$111_Y connect \B \main_interface0_ram_bus_we - connect \Y $and$ls180.v:3025$84_Y + connect \Y $and$ls180.v:3042$112_Y end - attribute \src "ls180.v:3025.23-3025.146" - cell $and $and$ls180.v:3025$85 + attribute \src "ls180.v:3042.23-3042.146" + cell $and $and$ls180.v:3042$113 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3025$84_Y + connect \A $and$ls180.v:3042$112_Y connect \B \main_interface0_ram_bus_sel [2] - connect \Y $and$ls180.v:3025$85_Y + connect \Y $and$ls180.v:3042$113_Y end - attribute \src "ls180.v:3026.25-3026.82" - cell $and $and$ls180.v:3026$86 + attribute \src "ls180.v:3043.25-3043.82" + cell $and $and$ls180.v:3043$114 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -236619,65 +237091,164 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_interface0_ram_bus_cyc connect \B \main_interface0_ram_bus_stb - connect \Y $and$ls180.v:3026$86_Y + connect \Y $and$ls180.v:3043$114_Y end - attribute \src "ls180.v:3026.24-3026.112" - cell $and $and$ls180.v:3026$87 + attribute \src "ls180.v:3043.24-3043.112" + cell $and $and$ls180.v:3043$115 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3026$86_Y + connect \A $and$ls180.v:3043$114_Y connect \B \main_interface0_ram_bus_we - connect \Y $and$ls180.v:3026$87_Y + connect \Y $and$ls180.v:3043$115_Y end - attribute \src "ls180.v:3026.23-3026.146" - cell $and $and$ls180.v:3026$88 + attribute \src "ls180.v:3043.23-3043.146" + cell $and $and$ls180.v:3043$116 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3026$87_Y + connect \A $and$ls180.v:3043$115_Y connect \B \main_interface0_ram_bus_sel [3] - connect \Y $and$ls180.v:3026$88_Y + connect \Y $and$ls180.v:3043$116_Y end - attribute \src "ls180.v:3033.25-3033.82" - cell $and $and$ls180.v:3033$90 + attribute \src "ls180.v:3044.25-3044.82" + cell $and $and$ls180.v:3044$117 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_interface1_ram_bus_cyc - connect \B \main_interface1_ram_bus_stb - connect \Y $and$ls180.v:3033$90_Y + connect \A \main_interface0_ram_bus_cyc + connect \B \main_interface0_ram_bus_stb + connect \Y $and$ls180.v:3044$117_Y end - attribute \src "ls180.v:3033.24-3033.112" - cell $and $and$ls180.v:3033$91 + attribute \src "ls180.v:3044.24-3044.112" + cell $and $and$ls180.v:3044$118 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3033$90_Y - connect \B \main_interface1_ram_bus_we - connect \Y $and$ls180.v:3033$91_Y + connect \A $and$ls180.v:3044$117_Y + connect \B \main_interface0_ram_bus_we + connect \Y $and$ls180.v:3044$118_Y end - attribute \src "ls180.v:3033.23-3033.146" - cell $and $and$ls180.v:3033$92 + attribute \src "ls180.v:3044.23-3044.146" + cell $and $and$ls180.v:3044$119 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3033$91_Y - connect \B \main_interface1_ram_bus_sel [0] - connect \Y $and$ls180.v:3033$92_Y + connect \A $and$ls180.v:3044$118_Y + connect \B \main_interface0_ram_bus_sel [4] + connect \Y $and$ls180.v:3044$119_Y + end + attribute \src "ls180.v:3045.25-3045.82" + cell $and $and$ls180.v:3045$120 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface0_ram_bus_cyc + connect \B \main_interface0_ram_bus_stb + connect \Y $and$ls180.v:3045$120_Y + end + attribute \src "ls180.v:3045.24-3045.112" + cell $and $and$ls180.v:3045$121 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3045$120_Y + connect \B \main_interface0_ram_bus_we + connect \Y $and$ls180.v:3045$121_Y + end + attribute \src "ls180.v:3045.23-3045.146" + cell $and $and$ls180.v:3045$122 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3045$121_Y + connect \B \main_interface0_ram_bus_sel [5] + connect \Y $and$ls180.v:3045$122_Y + end + attribute \src "ls180.v:3046.25-3046.82" + cell $and $and$ls180.v:3046$123 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface0_ram_bus_cyc + connect \B \main_interface0_ram_bus_stb + connect \Y $and$ls180.v:3046$123_Y + end + attribute \src "ls180.v:3046.24-3046.112" + cell $and $and$ls180.v:3046$124 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3046$123_Y + connect \B \main_interface0_ram_bus_we + connect \Y $and$ls180.v:3046$124_Y + end + attribute \src "ls180.v:3046.23-3046.146" + cell $and $and$ls180.v:3046$125 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3046$124_Y + connect \B \main_interface0_ram_bus_sel [6] + connect \Y $and$ls180.v:3046$125_Y end - attribute \src "ls180.v:3034.25-3034.82" - cell $and $and$ls180.v:3034$93 + attribute \src "ls180.v:3047.25-3047.82" + cell $and $and$ls180.v:3047$126 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface0_ram_bus_cyc + connect \B \main_interface0_ram_bus_stb + connect \Y $and$ls180.v:3047$126_Y + end + attribute \src "ls180.v:3047.24-3047.112" + cell $and $and$ls180.v:3047$127 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3047$126_Y + connect \B \main_interface0_ram_bus_we + connect \Y $and$ls180.v:3047$127_Y + end + attribute \src "ls180.v:3047.23-3047.146" + cell $and $and$ls180.v:3047$128 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3047$127_Y + connect \B \main_interface0_ram_bus_sel [7] + connect \Y $and$ls180.v:3047$128_Y + end + attribute \src "ls180.v:3054.25-3054.82" + cell $and $and$ls180.v:3054$130 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -236685,32 +237256,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_interface1_ram_bus_cyc connect \B \main_interface1_ram_bus_stb - connect \Y $and$ls180.v:3034$93_Y + connect \Y $and$ls180.v:3054$130_Y end - attribute \src "ls180.v:3034.24-3034.112" - cell $and $and$ls180.v:3034$94 + attribute \src "ls180.v:3054.24-3054.112" + cell $and $and$ls180.v:3054$131 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3034$93_Y + connect \A $and$ls180.v:3054$130_Y connect \B \main_interface1_ram_bus_we - connect \Y $and$ls180.v:3034$94_Y + connect \Y $and$ls180.v:3054$131_Y end - attribute \src "ls180.v:3034.23-3034.146" - cell $and $and$ls180.v:3034$95 + attribute \src "ls180.v:3054.23-3054.146" + cell $and $and$ls180.v:3054$132 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3034$94_Y - connect \B \main_interface1_ram_bus_sel [1] - connect \Y $and$ls180.v:3034$95_Y + connect \A $and$ls180.v:3054$131_Y + connect \B \main_interface1_ram_bus_sel [0] + connect \Y $and$ls180.v:3054$132_Y end - attribute \src "ls180.v:3035.25-3035.82" - cell $and $and$ls180.v:3035$96 + attribute \src "ls180.v:3055.25-3055.82" + cell $and $and$ls180.v:3055$133 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -236718,54 +237289,98 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_interface1_ram_bus_cyc connect \B \main_interface1_ram_bus_stb - connect \Y $and$ls180.v:3035$96_Y + connect \Y $and$ls180.v:3055$133_Y end - attribute \src "ls180.v:3035.24-3035.112" - cell $and $and$ls180.v:3035$97 + attribute \src "ls180.v:3055.24-3055.112" + cell $and $and$ls180.v:3055$134 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3035$96_Y + connect \A $and$ls180.v:3055$133_Y connect \B \main_interface1_ram_bus_we - connect \Y $and$ls180.v:3035$97_Y + connect \Y $and$ls180.v:3055$134_Y end - attribute \src "ls180.v:3035.23-3035.146" - cell $and $and$ls180.v:3035$98 + attribute \src "ls180.v:3055.23-3055.146" + cell $and $and$ls180.v:3055$135 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3035$97_Y + connect \A $and$ls180.v:3055$134_Y + connect \B \main_interface1_ram_bus_sel [1] + connect \Y $and$ls180.v:3055$135_Y + end + attribute \src "ls180.v:3056.25-3056.82" + cell $and $and$ls180.v:3056$136 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface1_ram_bus_cyc + connect \B \main_interface1_ram_bus_stb + connect \Y $and$ls180.v:3056$136_Y + end + attribute \src "ls180.v:3056.24-3056.112" + cell $and $and$ls180.v:3056$137 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3056$136_Y + connect \B \main_interface1_ram_bus_we + connect \Y $and$ls180.v:3056$137_Y + end + attribute \src "ls180.v:3056.23-3056.146" + cell $and $and$ls180.v:3056$138 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3056$137_Y connect \B \main_interface1_ram_bus_sel [2] - connect \Y $and$ls180.v:3035$98_Y + connect \Y $and$ls180.v:3056$138_Y + end + attribute \src "ls180.v:3057.25-3057.82" + cell $and $and$ls180.v:3057$139 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface1_ram_bus_cyc + connect \B \main_interface1_ram_bus_stb + connect \Y $and$ls180.v:3057$139_Y end - attribute \src "ls180.v:3036.24-3036.112" - cell $and $and$ls180.v:3036$100 + attribute \src "ls180.v:3057.24-3057.112" + cell $and $and$ls180.v:3057$140 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3036$99_Y + connect \A $and$ls180.v:3057$139_Y connect \B \main_interface1_ram_bus_we - connect \Y $and$ls180.v:3036$100_Y + connect \Y $and$ls180.v:3057$140_Y end - attribute \src "ls180.v:3036.23-3036.146" - cell $and $and$ls180.v:3036$101 + attribute \src "ls180.v:3057.23-3057.146" + cell $and $and$ls180.v:3057$141 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3036$100_Y + connect \A $and$ls180.v:3057$140_Y connect \B \main_interface1_ram_bus_sel [3] - connect \Y $and$ls180.v:3036$101_Y + connect \Y $and$ls180.v:3057$141_Y end - attribute \src "ls180.v:3036.25-3036.82" - cell $and $and$ls180.v:3036$99 + attribute \src "ls180.v:3058.25-3058.82" + cell $and $and$ls180.v:3058$142 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -236773,10 +237388,131 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_interface1_ram_bus_cyc connect \B \main_interface1_ram_bus_stb - connect \Y $and$ls180.v:3036$99_Y + connect \Y $and$ls180.v:3058$142_Y end - attribute \src "ls180.v:3043.25-3043.82" - cell $and $and$ls180.v:3043$103 + attribute \src "ls180.v:3058.24-3058.112" + cell $and $and$ls180.v:3058$143 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3058$142_Y + connect \B \main_interface1_ram_bus_we + connect \Y $and$ls180.v:3058$143_Y + end + attribute \src "ls180.v:3058.23-3058.146" + cell $and $and$ls180.v:3058$144 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3058$143_Y + connect \B \main_interface1_ram_bus_sel [4] + connect \Y $and$ls180.v:3058$144_Y + end + attribute \src "ls180.v:3059.25-3059.82" + cell $and $and$ls180.v:3059$145 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface1_ram_bus_cyc + connect \B \main_interface1_ram_bus_stb + connect \Y $and$ls180.v:3059$145_Y + end + attribute \src "ls180.v:3059.24-3059.112" + cell $and $and$ls180.v:3059$146 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3059$145_Y + connect \B \main_interface1_ram_bus_we + connect \Y $and$ls180.v:3059$146_Y + end + attribute \src "ls180.v:3059.23-3059.146" + cell $and $and$ls180.v:3059$147 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3059$146_Y + connect \B \main_interface1_ram_bus_sel [5] + connect \Y $and$ls180.v:3059$147_Y + end + attribute \src "ls180.v:3060.25-3060.82" + cell $and $and$ls180.v:3060$148 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface1_ram_bus_cyc + connect \B \main_interface1_ram_bus_stb + connect \Y $and$ls180.v:3060$148_Y + end + attribute \src "ls180.v:3060.24-3060.112" + cell $and $and$ls180.v:3060$149 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3060$148_Y + connect \B \main_interface1_ram_bus_we + connect \Y $and$ls180.v:3060$149_Y + end + attribute \src "ls180.v:3060.23-3060.146" + cell $and $and$ls180.v:3060$150 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3060$149_Y + connect \B \main_interface1_ram_bus_sel [6] + connect \Y $and$ls180.v:3060$150_Y + end + attribute \src "ls180.v:3061.25-3061.82" + cell $and $and$ls180.v:3061$151 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface1_ram_bus_cyc + connect \B \main_interface1_ram_bus_stb + connect \Y $and$ls180.v:3061$151_Y + end + attribute \src "ls180.v:3061.24-3061.112" + cell $and $and$ls180.v:3061$152 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3061$151_Y + connect \B \main_interface1_ram_bus_we + connect \Y $and$ls180.v:3061$152_Y + end + attribute \src "ls180.v:3061.23-3061.146" + cell $and $and$ls180.v:3061$153 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3061$152_Y + connect \B \main_interface1_ram_bus_sel [7] + connect \Y $and$ls180.v:3061$153_Y + end + attribute \src "ls180.v:3068.25-3068.82" + cell $and $and$ls180.v:3068$155 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -236784,32 +237520,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_interface2_ram_bus_cyc connect \B \main_interface2_ram_bus_stb - connect \Y $and$ls180.v:3043$103_Y + connect \Y $and$ls180.v:3068$155_Y end - attribute \src "ls180.v:3043.24-3043.112" - cell $and $and$ls180.v:3043$104 + attribute \src "ls180.v:3068.24-3068.112" + cell $and $and$ls180.v:3068$156 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3043$103_Y + connect \A $and$ls180.v:3068$155_Y connect \B \main_interface2_ram_bus_we - connect \Y $and$ls180.v:3043$104_Y + connect \Y $and$ls180.v:3068$156_Y end - attribute \src "ls180.v:3043.23-3043.146" - cell $and $and$ls180.v:3043$105 + attribute \src "ls180.v:3068.23-3068.146" + cell $and $and$ls180.v:3068$157 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3043$104_Y + connect \A $and$ls180.v:3068$156_Y connect \B \main_interface2_ram_bus_sel [0] - connect \Y $and$ls180.v:3043$105_Y + connect \Y $and$ls180.v:3068$157_Y end - attribute \src "ls180.v:3044.25-3044.82" - cell $and $and$ls180.v:3044$106 + attribute \src "ls180.v:3069.25-3069.82" + cell $and $and$ls180.v:3069$158 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -236817,32 +237553,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_interface2_ram_bus_cyc connect \B \main_interface2_ram_bus_stb - connect \Y $and$ls180.v:3044$106_Y + connect \Y $and$ls180.v:3069$158_Y end - attribute \src "ls180.v:3044.24-3044.112" - cell $and $and$ls180.v:3044$107 + attribute \src "ls180.v:3069.24-3069.112" + cell $and $and$ls180.v:3069$159 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3044$106_Y + connect \A $and$ls180.v:3069$158_Y connect \B \main_interface2_ram_bus_we - connect \Y $and$ls180.v:3044$107_Y + connect \Y $and$ls180.v:3069$159_Y end - attribute \src "ls180.v:3044.23-3044.146" - cell $and $and$ls180.v:3044$108 + attribute \src "ls180.v:3069.23-3069.146" + cell $and $and$ls180.v:3069$160 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3044$107_Y + connect \A $and$ls180.v:3069$159_Y connect \B \main_interface2_ram_bus_sel [1] - connect \Y $and$ls180.v:3044$108_Y + connect \Y $and$ls180.v:3069$160_Y end - attribute \src "ls180.v:3045.25-3045.82" - cell $and $and$ls180.v:3045$109 + attribute \src "ls180.v:3070.25-3070.82" + cell $and $and$ls180.v:3070$161 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -236850,32 +237586,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_interface2_ram_bus_cyc connect \B \main_interface2_ram_bus_stb - connect \Y $and$ls180.v:3045$109_Y + connect \Y $and$ls180.v:3070$161_Y end - attribute \src "ls180.v:3045.24-3045.112" - cell $and $and$ls180.v:3045$110 + attribute \src "ls180.v:3070.24-3070.112" + cell $and $and$ls180.v:3070$162 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3045$109_Y + connect \A $and$ls180.v:3070$161_Y connect \B \main_interface2_ram_bus_we - connect \Y $and$ls180.v:3045$110_Y + connect \Y $and$ls180.v:3070$162_Y end - attribute \src "ls180.v:3045.23-3045.146" - cell $and $and$ls180.v:3045$111 + attribute \src "ls180.v:3070.23-3070.146" + cell $and $and$ls180.v:3070$163 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3045$110_Y + connect \A $and$ls180.v:3070$162_Y connect \B \main_interface2_ram_bus_sel [2] - connect \Y $and$ls180.v:3045$111_Y + connect \Y $and$ls180.v:3070$163_Y end - attribute \src "ls180.v:3046.25-3046.82" - cell $and $and$ls180.v:3046$112 + attribute \src "ls180.v:3071.25-3071.82" + cell $and $and$ls180.v:3071$164 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -236883,32 +237619,164 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_interface2_ram_bus_cyc connect \B \main_interface2_ram_bus_stb - connect \Y $and$ls180.v:3046$112_Y + connect \Y $and$ls180.v:3071$164_Y end - attribute \src "ls180.v:3046.24-3046.112" - cell $and $and$ls180.v:3046$113 + attribute \src "ls180.v:3071.24-3071.112" + cell $and $and$ls180.v:3071$165 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3046$112_Y + connect \A $and$ls180.v:3071$164_Y connect \B \main_interface2_ram_bus_we - connect \Y $and$ls180.v:3046$113_Y + connect \Y $and$ls180.v:3071$165_Y end - attribute \src "ls180.v:3046.23-3046.146" - cell $and $and$ls180.v:3046$114 + attribute \src "ls180.v:3071.23-3071.146" + cell $and $and$ls180.v:3071$166 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3046$113_Y + connect \A $and$ls180.v:3071$165_Y connect \B \main_interface2_ram_bus_sel [3] - connect \Y $and$ls180.v:3046$114_Y + connect \Y $and$ls180.v:3071$166_Y + end + attribute \src "ls180.v:3072.25-3072.82" + cell $and $and$ls180.v:3072$167 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface2_ram_bus_cyc + connect \B \main_interface2_ram_bus_stb + connect \Y $and$ls180.v:3072$167_Y + end + attribute \src "ls180.v:3072.24-3072.112" + cell $and $and$ls180.v:3072$168 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3072$167_Y + connect \B \main_interface2_ram_bus_we + connect \Y $and$ls180.v:3072$168_Y end - attribute \src "ls180.v:3163.40-3163.99" - cell $and $and$ls180.v:3163$121 + attribute \src "ls180.v:3072.23-3072.146" + cell $and $and$ls180.v:3072$169 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3072$168_Y + connect \B \main_interface2_ram_bus_sel [4] + connect \Y $and$ls180.v:3072$169_Y + end + attribute \src "ls180.v:3073.25-3073.82" + cell $and $and$ls180.v:3073$170 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface2_ram_bus_cyc + connect \B \main_interface2_ram_bus_stb + connect \Y $and$ls180.v:3073$170_Y + end + attribute \src "ls180.v:3073.24-3073.112" + cell $and $and$ls180.v:3073$171 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3073$170_Y + connect \B \main_interface2_ram_bus_we + connect \Y $and$ls180.v:3073$171_Y + end + attribute \src "ls180.v:3073.23-3073.146" + cell $and $and$ls180.v:3073$172 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3073$171_Y + connect \B \main_interface2_ram_bus_sel [5] + connect \Y $and$ls180.v:3073$172_Y + end + attribute \src "ls180.v:3074.25-3074.82" + cell $and $and$ls180.v:3074$173 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface2_ram_bus_cyc + connect \B \main_interface2_ram_bus_stb + connect \Y $and$ls180.v:3074$173_Y + end + attribute \src "ls180.v:3074.24-3074.112" + cell $and $and$ls180.v:3074$174 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3074$173_Y + connect \B \main_interface2_ram_bus_we + connect \Y $and$ls180.v:3074$174_Y + end + attribute \src "ls180.v:3074.23-3074.146" + cell $and $and$ls180.v:3074$175 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3074$174_Y + connect \B \main_interface2_ram_bus_sel [6] + connect \Y $and$ls180.v:3074$175_Y + end + attribute \src "ls180.v:3075.25-3075.82" + cell $and $and$ls180.v:3075$176 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface2_ram_bus_cyc + connect \B \main_interface2_ram_bus_stb + connect \Y $and$ls180.v:3075$176_Y + end + attribute \src "ls180.v:3075.24-3075.112" + cell $and $and$ls180.v:3075$177 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3075$176_Y + connect \B \main_interface2_ram_bus_we + connect \Y $and$ls180.v:3075$177_Y + end + attribute \src "ls180.v:3075.23-3075.146" + cell $and $and$ls180.v:3075$178 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3075$177_Y + connect \B \main_interface2_ram_bus_sel [7] + connect \Y $and$ls180.v:3075$178_Y + end + attribute \src "ls180.v:3192.40-3192.99" + cell $and $and$ls180.v:3192$185 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -236916,10 +237784,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_command_issue_re connect \B \main_sdram_command_storage [4] - connect \Y $and$ls180.v:3163$121_Y + connect \Y $and$ls180.v:3192$185_Y end - attribute \src "ls180.v:3164.40-3164.99" - cell $and $and$ls180.v:3164$122 + attribute \src "ls180.v:3193.40-3193.99" + cell $and $and$ls180.v:3193$186 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -236927,21 +237795,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_command_issue_re connect \B \main_sdram_command_storage [5] - connect \Y $and$ls180.v:3164$122_Y + connect \Y $and$ls180.v:3193$186_Y end - attribute \src "ls180.v:3202.38-3202.103" - cell $and $and$ls180.v:3202$128 + attribute \src "ls180.v:3231.38-3231.103" + cell $and $and$ls180.v:3231$192 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_done1 - connect \B $eq$ls180.v:3202$127_Y - connect \Y $and$ls180.v:3202$128_Y + connect \B $eq$ls180.v:3231$191_Y + connect \Y $and$ls180.v:3231$192_Y end - attribute \src "ls180.v:3256.50-3256.119" - cell $and $and$ls180.v:3256$136 + attribute \src "ls180.v:3285.50-3285.119" + cell $and $and$ls180.v:3285$200 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -236949,21 +237817,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_valid connect \B \main_sdram_bankmachine0_cmd_ready - connect \Y $and$ls180.v:3256$136_Y + connect \Y $and$ls180.v:3285$200_Y end - attribute \src "ls180.v:3256.49-3256.167" - cell $and $and$ls180.v:3256$137 + attribute \src "ls180.v:3285.49-3285.167" + cell $and $and$ls180.v:3285$201 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3256$136_Y + connect \A $and$ls180.v:3285$200_Y connect \B \main_sdram_bankmachine0_cmd_payload_is_write - connect \Y $and$ls180.v:3256$137_Y + connect \Y $and$ls180.v:3285$201_Y end - attribute \src "ls180.v:3257.49-3257.118" - cell $and $and$ls180.v:3257$138 + attribute \src "ls180.v:3286.49-3286.118" + cell $and $and$ls180.v:3286$202 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -236971,21 +237839,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_valid connect \B \main_sdram_bankmachine0_cmd_ready - connect \Y $and$ls180.v:3257$138_Y + connect \Y $and$ls180.v:3286$202_Y end - attribute \src "ls180.v:3257.48-3257.154" - cell $and $and$ls180.v:3257$139 + attribute \src "ls180.v:3286.48-3286.154" + cell $and $and$ls180.v:3286$203 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3257$138_Y + connect \A $and$ls180.v:3286$202_Y connect \B \main_sdram_bankmachine0_row_open - connect \Y $and$ls180.v:3257$139_Y + connect \Y $and$ls180.v:3286$203_Y end - attribute \src "ls180.v:3258.50-3258.119" - cell $and $and$ls180.v:3258$140 + attribute \src "ls180.v:3287.50-3287.119" + cell $and $and$ls180.v:3287$204 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -236993,21 +237861,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_valid connect \B \main_sdram_bankmachine0_cmd_ready - connect \Y $and$ls180.v:3258$140_Y + connect \Y $and$ls180.v:3287$204_Y end - attribute \src "ls180.v:3258.49-3258.155" - cell $and $and$ls180.v:3258$141 + attribute \src "ls180.v:3287.49-3287.155" + cell $and $and$ls180.v:3287$205 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3258$140_Y + connect \A $and$ls180.v:3287$204_Y connect \B \main_sdram_bankmachine0_row_open - connect \Y $and$ls180.v:3258$141_Y + connect \Y $and$ls180.v:3287$205_Y end - attribute \src "ls180.v:3261.7-3261.114" - cell $and $and$ls180.v:3261$143 + attribute \src "ls180.v:3290.7-3290.114" + cell $and $and$ls180.v:3290$207 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237015,21 +237883,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid connect \B \main_sdram_bankmachine0_cmd_buffer_source_valid - connect \Y $and$ls180.v:3261$143_Y + connect \Y $and$ls180.v:3290$207_Y end - attribute \src "ls180.v:3290.66-3290.246" - cell $and $and$ls180.v:3290$149 + attribute \src "ls180.v:3319.66-3319.246" + cell $and $and$ls180.v:3319$213 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we - connect \B $or$ls180.v:3290$148_Y - connect \Y $and$ls180.v:3290$149_Y + connect \B $or$ls180.v:3319$212_Y + connect \Y $and$ls180.v:3319$213_Y end - attribute \src "ls180.v:3291.64-3291.187" - cell $and $and$ls180.v:3291$150 + attribute \src "ls180.v:3320.64-3320.187" + cell $and $and$ls180.v:3320$214 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237037,10 +237905,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re - connect \Y $and$ls180.v:3291$150_Y + connect \Y $and$ls180.v:3320$214_Y end - attribute \src "ls180.v:3315.9-3315.86" - cell $and $and$ls180.v:3315$156 + attribute \src "ls180.v:3344.9-3344.86" + cell $and $and$ls180.v:3344$220 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237048,10 +237916,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_twtpcon_ready connect \B \main_sdram_bankmachine0_trascon_ready - connect \Y $and$ls180.v:3315$156_Y + connect \Y $and$ls180.v:3344$220_Y end - attribute \src "ls180.v:3327.9-3327.86" - cell $and $and$ls180.v:3327$157 + attribute \src "ls180.v:3356.9-3356.86" + cell $and $and$ls180.v:3356$221 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237059,10 +237927,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_twtpcon_ready connect \B \main_sdram_bankmachine0_trascon_ready - connect \Y $and$ls180.v:3327$157_Y + connect \Y $and$ls180.v:3356$221_Y end - attribute \src "ls180.v:3377.13-3377.87" - cell $and $and$ls180.v:3377$159 + attribute \src "ls180.v:3406.13-3406.87" + cell $and $and$ls180.v:3406$223 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237070,10 +237938,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_ready connect \B \main_sdram_bankmachine0_auto_precharge - connect \Y $and$ls180.v:3377$159_Y + connect \Y $and$ls180.v:3406$223_Y end - attribute \src "ls180.v:3413.50-3413.119" - cell $and $and$ls180.v:3413$166 + attribute \src "ls180.v:3442.50-3442.119" + cell $and $and$ls180.v:3442$230 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237081,21 +237949,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_valid connect \B \main_sdram_bankmachine1_cmd_ready - connect \Y $and$ls180.v:3413$166_Y + connect \Y $and$ls180.v:3442$230_Y end - attribute \src "ls180.v:3413.49-3413.167" - cell $and $and$ls180.v:3413$167 + attribute \src "ls180.v:3442.49-3442.167" + cell $and $and$ls180.v:3442$231 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3413$166_Y + connect \A $and$ls180.v:3442$230_Y connect \B \main_sdram_bankmachine1_cmd_payload_is_write - connect \Y $and$ls180.v:3413$167_Y + connect \Y $and$ls180.v:3442$231_Y end - attribute \src "ls180.v:3414.49-3414.118" - cell $and $and$ls180.v:3414$168 + attribute \src "ls180.v:3443.49-3443.118" + cell $and $and$ls180.v:3443$232 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237103,21 +237971,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_valid connect \B \main_sdram_bankmachine1_cmd_ready - connect \Y $and$ls180.v:3414$168_Y + connect \Y $and$ls180.v:3443$232_Y end - attribute \src "ls180.v:3414.48-3414.154" - cell $and $and$ls180.v:3414$169 + attribute \src "ls180.v:3443.48-3443.154" + cell $and $and$ls180.v:3443$233 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3414$168_Y + connect \A $and$ls180.v:3443$232_Y connect \B \main_sdram_bankmachine1_row_open - connect \Y $and$ls180.v:3414$169_Y + connect \Y $and$ls180.v:3443$233_Y end - attribute \src "ls180.v:3415.50-3415.119" - cell $and $and$ls180.v:3415$170 + attribute \src "ls180.v:3444.50-3444.119" + cell $and $and$ls180.v:3444$234 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237125,21 +237993,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_valid connect \B \main_sdram_bankmachine1_cmd_ready - connect \Y $and$ls180.v:3415$170_Y + connect \Y $and$ls180.v:3444$234_Y end - attribute \src "ls180.v:3415.49-3415.155" - cell $and $and$ls180.v:3415$171 + attribute \src "ls180.v:3444.49-3444.155" + cell $and $and$ls180.v:3444$235 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3415$170_Y + connect \A $and$ls180.v:3444$234_Y connect \B \main_sdram_bankmachine1_row_open - connect \Y $and$ls180.v:3415$171_Y + connect \Y $and$ls180.v:3444$235_Y end - attribute \src "ls180.v:3418.7-3418.114" - cell $and $and$ls180.v:3418$173 + attribute \src "ls180.v:3447.7-3447.114" + cell $and $and$ls180.v:3447$237 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237147,21 +238015,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid connect \B \main_sdram_bankmachine1_cmd_buffer_source_valid - connect \Y $and$ls180.v:3418$173_Y + connect \Y $and$ls180.v:3447$237_Y end - attribute \src "ls180.v:3447.66-3447.246" - cell $and $and$ls180.v:3447$179 + attribute \src "ls180.v:3476.66-3476.246" + cell $and $and$ls180.v:3476$243 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we - connect \B $or$ls180.v:3447$178_Y - connect \Y $and$ls180.v:3447$179_Y + connect \B $or$ls180.v:3476$242_Y + connect \Y $and$ls180.v:3476$243_Y end - attribute \src "ls180.v:3448.64-3448.187" - cell $and $and$ls180.v:3448$180 + attribute \src "ls180.v:3477.64-3477.187" + cell $and $and$ls180.v:3477$244 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237169,10 +238037,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re - connect \Y $and$ls180.v:3448$180_Y + connect \Y $and$ls180.v:3477$244_Y end - attribute \src "ls180.v:3472.9-3472.86" - cell $and $and$ls180.v:3472$186 + attribute \src "ls180.v:3501.9-3501.86" + cell $and $and$ls180.v:3501$250 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237180,10 +238048,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_twtpcon_ready connect \B \main_sdram_bankmachine1_trascon_ready - connect \Y $and$ls180.v:3472$186_Y + connect \Y $and$ls180.v:3501$250_Y end - attribute \src "ls180.v:3484.9-3484.86" - cell $and $and$ls180.v:3484$187 + attribute \src "ls180.v:3513.9-3513.86" + cell $and $and$ls180.v:3513$251 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237191,10 +238059,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_twtpcon_ready connect \B \main_sdram_bankmachine1_trascon_ready - connect \Y $and$ls180.v:3484$187_Y + connect \Y $and$ls180.v:3513$251_Y end - attribute \src "ls180.v:3534.13-3534.87" - cell $and $and$ls180.v:3534$189 + attribute \src "ls180.v:3563.13-3563.87" + cell $and $and$ls180.v:3563$253 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237202,10 +238070,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_ready connect \B \main_sdram_bankmachine1_auto_precharge - connect \Y $and$ls180.v:3534$189_Y + connect \Y $and$ls180.v:3563$253_Y end - attribute \src "ls180.v:3570.50-3570.119" - cell $and $and$ls180.v:3570$196 + attribute \src "ls180.v:3599.50-3599.119" + cell $and $and$ls180.v:3599$260 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237213,21 +238081,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_valid connect \B \main_sdram_bankmachine2_cmd_ready - connect \Y $and$ls180.v:3570$196_Y + connect \Y $and$ls180.v:3599$260_Y end - attribute \src "ls180.v:3570.49-3570.167" - cell $and $and$ls180.v:3570$197 + attribute \src "ls180.v:3599.49-3599.167" + cell $and $and$ls180.v:3599$261 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3570$196_Y + connect \A $and$ls180.v:3599$260_Y connect \B \main_sdram_bankmachine2_cmd_payload_is_write - connect \Y $and$ls180.v:3570$197_Y + connect \Y $and$ls180.v:3599$261_Y end - attribute \src "ls180.v:3571.49-3571.118" - cell $and $and$ls180.v:3571$198 + attribute \src "ls180.v:3600.49-3600.118" + cell $and $and$ls180.v:3600$262 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237235,21 +238103,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_valid connect \B \main_sdram_bankmachine2_cmd_ready - connect \Y $and$ls180.v:3571$198_Y + connect \Y $and$ls180.v:3600$262_Y end - attribute \src "ls180.v:3571.48-3571.154" - cell $and $and$ls180.v:3571$199 + attribute \src "ls180.v:3600.48-3600.154" + cell $and $and$ls180.v:3600$263 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3571$198_Y + connect \A $and$ls180.v:3600$262_Y connect \B \main_sdram_bankmachine2_row_open - connect \Y $and$ls180.v:3571$199_Y + connect \Y $and$ls180.v:3600$263_Y end - attribute \src "ls180.v:3572.50-3572.119" - cell $and $and$ls180.v:3572$200 + attribute \src "ls180.v:3601.50-3601.119" + cell $and $and$ls180.v:3601$264 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237257,21 +238125,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_valid connect \B \main_sdram_bankmachine2_cmd_ready - connect \Y $and$ls180.v:3572$200_Y + connect \Y $and$ls180.v:3601$264_Y end - attribute \src "ls180.v:3572.49-3572.155" - cell $and $and$ls180.v:3572$201 + attribute \src "ls180.v:3601.49-3601.155" + cell $and $and$ls180.v:3601$265 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3572$200_Y + connect \A $and$ls180.v:3601$264_Y connect \B \main_sdram_bankmachine2_row_open - connect \Y $and$ls180.v:3572$201_Y + connect \Y $and$ls180.v:3601$265_Y end - attribute \src "ls180.v:3575.7-3575.114" - cell $and $and$ls180.v:3575$203 + attribute \src "ls180.v:3604.7-3604.114" + cell $and $and$ls180.v:3604$267 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237279,21 +238147,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid connect \B \main_sdram_bankmachine2_cmd_buffer_source_valid - connect \Y $and$ls180.v:3575$203_Y + connect \Y $and$ls180.v:3604$267_Y end - attribute \src "ls180.v:3604.66-3604.246" - cell $and $and$ls180.v:3604$209 + attribute \src "ls180.v:3633.66-3633.246" + cell $and $and$ls180.v:3633$273 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we - connect \B $or$ls180.v:3604$208_Y - connect \Y $and$ls180.v:3604$209_Y + connect \B $or$ls180.v:3633$272_Y + connect \Y $and$ls180.v:3633$273_Y end - attribute \src "ls180.v:3605.64-3605.187" - cell $and $and$ls180.v:3605$210 + attribute \src "ls180.v:3634.64-3634.187" + cell $and $and$ls180.v:3634$274 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237301,10 +238169,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re - connect \Y $and$ls180.v:3605$210_Y + connect \Y $and$ls180.v:3634$274_Y end - attribute \src "ls180.v:3629.9-3629.86" - cell $and $and$ls180.v:3629$216 + attribute \src "ls180.v:3658.9-3658.86" + cell $and $and$ls180.v:3658$280 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237312,10 +238180,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_twtpcon_ready connect \B \main_sdram_bankmachine2_trascon_ready - connect \Y $and$ls180.v:3629$216_Y + connect \Y $and$ls180.v:3658$280_Y end - attribute \src "ls180.v:3641.9-3641.86" - cell $and $and$ls180.v:3641$217 + attribute \src "ls180.v:3670.9-3670.86" + cell $and $and$ls180.v:3670$281 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237323,10 +238191,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_twtpcon_ready connect \B \main_sdram_bankmachine2_trascon_ready - connect \Y $and$ls180.v:3641$217_Y + connect \Y $and$ls180.v:3670$281_Y end - attribute \src "ls180.v:3691.13-3691.87" - cell $and $and$ls180.v:3691$219 + attribute \src "ls180.v:3720.13-3720.87" + cell $and $and$ls180.v:3720$283 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237334,10 +238202,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_ready connect \B \main_sdram_bankmachine2_auto_precharge - connect \Y $and$ls180.v:3691$219_Y + connect \Y $and$ls180.v:3720$283_Y end - attribute \src "ls180.v:3727.50-3727.119" - cell $and $and$ls180.v:3727$226 + attribute \src "ls180.v:3756.50-3756.119" + cell $and $and$ls180.v:3756$290 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237345,21 +238213,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_valid connect \B \main_sdram_bankmachine3_cmd_ready - connect \Y $and$ls180.v:3727$226_Y + connect \Y $and$ls180.v:3756$290_Y end - attribute \src "ls180.v:3727.49-3727.167" - cell $and $and$ls180.v:3727$227 + attribute \src "ls180.v:3756.49-3756.167" + cell $and $and$ls180.v:3756$291 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3727$226_Y + connect \A $and$ls180.v:3756$290_Y connect \B \main_sdram_bankmachine3_cmd_payload_is_write - connect \Y $and$ls180.v:3727$227_Y + connect \Y $and$ls180.v:3756$291_Y end - attribute \src "ls180.v:3728.49-3728.118" - cell $and $and$ls180.v:3728$228 + attribute \src "ls180.v:3757.49-3757.118" + cell $and $and$ls180.v:3757$292 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237367,21 +238235,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_valid connect \B \main_sdram_bankmachine3_cmd_ready - connect \Y $and$ls180.v:3728$228_Y + connect \Y $and$ls180.v:3757$292_Y end - attribute \src "ls180.v:3728.48-3728.154" - cell $and $and$ls180.v:3728$229 + attribute \src "ls180.v:3757.48-3757.154" + cell $and $and$ls180.v:3757$293 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3728$228_Y + connect \A $and$ls180.v:3757$292_Y connect \B \main_sdram_bankmachine3_row_open - connect \Y $and$ls180.v:3728$229_Y + connect \Y $and$ls180.v:3757$293_Y end - attribute \src "ls180.v:3729.50-3729.119" - cell $and $and$ls180.v:3729$230 + attribute \src "ls180.v:3758.50-3758.119" + cell $and $and$ls180.v:3758$294 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237389,21 +238257,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_valid connect \B \main_sdram_bankmachine3_cmd_ready - connect \Y $and$ls180.v:3729$230_Y + connect \Y $and$ls180.v:3758$294_Y end - attribute \src "ls180.v:3729.49-3729.155" - cell $and $and$ls180.v:3729$231 + attribute \src "ls180.v:3758.49-3758.155" + cell $and $and$ls180.v:3758$295 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3729$230_Y + connect \A $and$ls180.v:3758$294_Y connect \B \main_sdram_bankmachine3_row_open - connect \Y $and$ls180.v:3729$231_Y + connect \Y $and$ls180.v:3758$295_Y end - attribute \src "ls180.v:3732.7-3732.114" - cell $and $and$ls180.v:3732$233 + attribute \src "ls180.v:3761.7-3761.114" + cell $and $and$ls180.v:3761$297 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237411,21 +238279,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid connect \B \main_sdram_bankmachine3_cmd_buffer_source_valid - connect \Y $and$ls180.v:3732$233_Y + connect \Y $and$ls180.v:3761$297_Y end - attribute \src "ls180.v:3761.66-3761.246" - cell $and $and$ls180.v:3761$239 + attribute \src "ls180.v:3790.66-3790.246" + cell $and $and$ls180.v:3790$303 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we - connect \B $or$ls180.v:3761$238_Y - connect \Y $and$ls180.v:3761$239_Y + connect \B $or$ls180.v:3790$302_Y + connect \Y $and$ls180.v:3790$303_Y end - attribute \src "ls180.v:3762.64-3762.187" - cell $and $and$ls180.v:3762$240 + attribute \src "ls180.v:3791.64-3791.187" + cell $and $and$ls180.v:3791$304 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237433,10 +238301,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re - connect \Y $and$ls180.v:3762$240_Y + connect \Y $and$ls180.v:3791$304_Y end - attribute \src "ls180.v:3786.9-3786.86" - cell $and $and$ls180.v:3786$246 + attribute \src "ls180.v:3815.9-3815.86" + cell $and $and$ls180.v:3815$310 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237444,10 +238312,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_twtpcon_ready connect \B \main_sdram_bankmachine3_trascon_ready - connect \Y $and$ls180.v:3786$246_Y + connect \Y $and$ls180.v:3815$310_Y end - attribute \src "ls180.v:3798.9-3798.86" - cell $and $and$ls180.v:3798$247 + attribute \src "ls180.v:3827.9-3827.86" + cell $and $and$ls180.v:3827$311 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237455,10 +238323,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_twtpcon_ready connect \B \main_sdram_bankmachine3_trascon_ready - connect \Y $and$ls180.v:3798$247_Y + connect \Y $and$ls180.v:3827$311_Y end - attribute \src "ls180.v:3848.13-3848.87" - cell $and $and$ls180.v:3848$249 + attribute \src "ls180.v:3877.13-3877.87" + cell $and $and$ls180.v:3877$313 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237466,10 +238334,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_ready connect \B \main_sdram_bankmachine3_auto_precharge - connect \Y $and$ls180.v:3848$249_Y + connect \Y $and$ls180.v:3877$313_Y end - attribute \src "ls180.v:3863.37-3863.102" - cell $and $and$ls180.v:3863$250 + attribute \src "ls180.v:3892.37-3892.102" + cell $and $and$ls180.v:3892$314 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237477,43 +238345,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3863$250_Y + connect \Y $and$ls180.v:3892$314_Y end - attribute \src "ls180.v:3863.108-3863.188" - cell $and $and$ls180.v:3863$252 + attribute \src "ls180.v:3892.108-3892.188" + cell $and $and$ls180.v:3892$316 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_ras - connect \B $not$ls180.v:3863$251_Y - connect \Y $and$ls180.v:3863$252_Y + connect \B $not$ls180.v:3892$315_Y + connect \Y $and$ls180.v:3892$316_Y end - attribute \src "ls180.v:3863.107-3863.231" - cell $and $and$ls180.v:3863$254 + attribute \src "ls180.v:3892.107-3892.231" + cell $and $and$ls180.v:3892$318 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3863$252_Y - connect \B $not$ls180.v:3863$253_Y - connect \Y $and$ls180.v:3863$254_Y + connect \A $and$ls180.v:3892$316_Y + connect \B $not$ls180.v:3892$317_Y + connect \Y $and$ls180.v:3892$318_Y end - attribute \src "ls180.v:3863.36-3863.232" - cell $and $and$ls180.v:3863$255 + attribute \src "ls180.v:3892.36-3892.232" + cell $and $and$ls180.v:3892$319 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3863$250_Y - connect \B $and$ls180.v:3863$254_Y - connect \Y $and$ls180.v:3863$255_Y + connect \A $and$ls180.v:3892$314_Y + connect \B $and$ls180.v:3892$318_Y + connect \Y $and$ls180.v:3892$319_Y end - attribute \src "ls180.v:3864.37-3864.102" - cell $and $and$ls180.v:3864$256 + attribute \src "ls180.v:3893.37-3893.102" + cell $and $and$ls180.v:3893$320 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237521,43 +238389,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3864$256_Y + connect \Y $and$ls180.v:3893$320_Y end - attribute \src "ls180.v:3864.108-3864.188" - cell $and $and$ls180.v:3864$258 + attribute \src "ls180.v:3893.108-3893.188" + cell $and $and$ls180.v:3893$322 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_ras - connect \B $not$ls180.v:3864$257_Y - connect \Y $and$ls180.v:3864$258_Y + connect \B $not$ls180.v:3893$321_Y + connect \Y $and$ls180.v:3893$322_Y end - attribute \src "ls180.v:3864.107-3864.231" - cell $and $and$ls180.v:3864$260 + attribute \src "ls180.v:3893.107-3893.231" + cell $and $and$ls180.v:3893$324 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3864$258_Y - connect \B $not$ls180.v:3864$259_Y - connect \Y $and$ls180.v:3864$260_Y + connect \A $and$ls180.v:3893$322_Y + connect \B $not$ls180.v:3893$323_Y + connect \Y $and$ls180.v:3893$324_Y end - attribute \src "ls180.v:3864.36-3864.232" - cell $and $and$ls180.v:3864$261 + attribute \src "ls180.v:3893.36-3893.232" + cell $and $and$ls180.v:3893$325 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3864$256_Y - connect \B $and$ls180.v:3864$260_Y - connect \Y $and$ls180.v:3864$261_Y + connect \A $and$ls180.v:3893$320_Y + connect \B $and$ls180.v:3893$324_Y + connect \Y $and$ls180.v:3893$325_Y end - attribute \src "ls180.v:3865.34-3865.85" - cell $and $and$ls180.v:3865$262 + attribute \src "ls180.v:3894.34-3894.85" + cell $and $and$ls180.v:3894$326 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237565,10 +238433,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_trrdcon_ready connect \B \main_sdram_tfawcon_ready - connect \Y $and$ls180.v:3865$262_Y + connect \Y $and$ls180.v:3894$326_Y end - attribute \src "ls180.v:3866.37-3866.102" - cell $and $and$ls180.v:3866$263 + attribute \src "ls180.v:3895.37-3895.102" + cell $and $and$ls180.v:3895$327 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237576,21 +238444,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3866$263_Y + connect \Y $and$ls180.v:3895$327_Y end - attribute \src "ls180.v:3866.36-3866.194" - cell $and $and$ls180.v:3866$265 + attribute \src "ls180.v:3895.36-3895.194" + cell $and $and$ls180.v:3895$329 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3866$263_Y - connect \B $or$ls180.v:3866$264_Y - connect \Y $and$ls180.v:3866$265_Y + connect \A $and$ls180.v:3895$327_Y + connect \B $or$ls180.v:3895$328_Y + connect \Y $and$ls180.v:3895$329_Y end - attribute \src "ls180.v:3868.37-3868.102" - cell $and $and$ls180.v:3868$266 + attribute \src "ls180.v:3897.37-3897.102" + cell $and $and$ls180.v:3897$330 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237598,21 +238466,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3868$266_Y + connect \Y $and$ls180.v:3897$330_Y end - attribute \src "ls180.v:3868.36-3868.148" - cell $and $and$ls180.v:3868$267 + attribute \src "ls180.v:3897.36-3897.148" + cell $and $and$ls180.v:3897$331 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3868$266_Y + connect \A $and$ls180.v:3897$330_Y connect \B \main_sdram_choose_req_cmd_payload_is_write - connect \Y $and$ls180.v:3868$267_Y + connect \Y $and$ls180.v:3897$331_Y end - attribute \src "ls180.v:3869.40-3869.119" - cell $and $and$ls180.v:3869$268 + attribute \src "ls180.v:3898.40-3898.119" + cell $and $and$ls180.v:3898$332 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237620,10 +238488,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_valid connect \B \main_sdram_bankmachine0_cmd_payload_is_read - connect \Y $and$ls180.v:3869$268_Y + connect \Y $and$ls180.v:3898$332_Y end - attribute \src "ls180.v:3869.124-3869.203" - cell $and $and$ls180.v:3869$269 + attribute \src "ls180.v:3898.124-3898.203" + cell $and $and$ls180.v:3898$333 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237631,10 +238499,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_valid connect \B \main_sdram_bankmachine1_cmd_payload_is_read - connect \Y $and$ls180.v:3869$269_Y + connect \Y $and$ls180.v:3898$333_Y end - attribute \src "ls180.v:3869.209-3869.288" - cell $and $and$ls180.v:3869$271 + attribute \src "ls180.v:3898.209-3898.288" + cell $and $and$ls180.v:3898$335 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237642,10 +238510,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_valid connect \B \main_sdram_bankmachine2_cmd_payload_is_read - connect \Y $and$ls180.v:3869$271_Y + connect \Y $and$ls180.v:3898$335_Y end - attribute \src "ls180.v:3869.294-3869.373" - cell $and $and$ls180.v:3869$273 + attribute \src "ls180.v:3898.294-3898.373" + cell $and $and$ls180.v:3898$337 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237653,10 +238521,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_valid connect \B \main_sdram_bankmachine3_cmd_payload_is_read - connect \Y $and$ls180.v:3869$273_Y + connect \Y $and$ls180.v:3898$337_Y end - attribute \src "ls180.v:3870.41-3870.121" - cell $and $and$ls180.v:3870$275 + attribute \src "ls180.v:3899.41-3899.121" + cell $and $and$ls180.v:3899$339 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237664,10 +238532,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_valid connect \B \main_sdram_bankmachine0_cmd_payload_is_write - connect \Y $and$ls180.v:3870$275_Y + connect \Y $and$ls180.v:3899$339_Y end - attribute \src "ls180.v:3870.126-3870.206" - cell $and $and$ls180.v:3870$276 + attribute \src "ls180.v:3899.126-3899.206" + cell $and $and$ls180.v:3899$340 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237675,10 +238543,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_valid connect \B \main_sdram_bankmachine1_cmd_payload_is_write - connect \Y $and$ls180.v:3870$276_Y + connect \Y $and$ls180.v:3899$340_Y end - attribute \src "ls180.v:3870.212-3870.292" - cell $and $and$ls180.v:3870$278 + attribute \src "ls180.v:3899.212-3899.292" + cell $and $and$ls180.v:3899$342 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237686,10 +238554,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_valid connect \B \main_sdram_bankmachine2_cmd_payload_is_write - connect \Y $and$ls180.v:3870$278_Y + connect \Y $and$ls180.v:3899$342_Y end - attribute \src "ls180.v:3870.298-3870.378" - cell $and $and$ls180.v:3870$280 + attribute \src "ls180.v:3899.298-3899.378" + cell $and $and$ls180.v:3899$344 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237697,10 +238565,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_valid connect \B \main_sdram_bankmachine3_cmd_payload_is_write - connect \Y $and$ls180.v:3870$280_Y + connect \Y $and$ls180.v:3899$344_Y end - attribute \src "ls180.v:3877.38-3877.111" - cell $and $and$ls180.v:3877$284 + attribute \src "ls180.v:3906.38-3906.111" + cell $and $and$ls180.v:3906$348 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237708,32 +238576,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_refresh_gnt connect \B \main_sdram_bankmachine1_refresh_gnt - connect \Y $and$ls180.v:3877$284_Y + connect \Y $and$ls180.v:3906$348_Y end - attribute \src "ls180.v:3877.37-3877.150" - cell $and $and$ls180.v:3877$285 + attribute \src "ls180.v:3906.37-3906.150" + cell $and $and$ls180.v:3906$349 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3877$284_Y + connect \A $and$ls180.v:3906$348_Y connect \B \main_sdram_bankmachine2_refresh_gnt - connect \Y $and$ls180.v:3877$285_Y + connect \Y $and$ls180.v:3906$349_Y end - attribute \src "ls180.v:3877.36-3877.189" - cell $and $and$ls180.v:3877$286 + attribute \src "ls180.v:3906.36-3906.189" + cell $and $and$ls180.v:3906$350 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3877$285_Y + connect \A $and$ls180.v:3906$349_Y connect \B \main_sdram_bankmachine3_refresh_gnt - connect \Y $and$ls180.v:3877$286_Y + connect \Y $and$ls180.v:3906$350_Y end - attribute \src "ls180.v:3883.77-3883.153" - cell $and $and$ls180.v:3883$289 + attribute \src "ls180.v:3912.77-3912.153" + cell $and $and$ls180.v:3912$353 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237741,65 +238609,65 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_payload_is_cmd connect \B \main_sdram_choose_cmd_want_cmds - connect \Y $and$ls180.v:3883$289_Y + connect \Y $and$ls180.v:3912$353_Y end - attribute \src "ls180.v:3883.162-3883.246" - cell $and $and$ls180.v:3883$291 + attribute \src "ls180.v:3912.162-3912.246" + cell $and $and$ls180.v:3912$355 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_payload_ras - connect \B $not$ls180.v:3883$290_Y - connect \Y $and$ls180.v:3883$291_Y + connect \B $not$ls180.v:3912$354_Y + connect \Y $and$ls180.v:3912$355_Y end - attribute \src "ls180.v:3883.161-3883.291" - cell $and $and$ls180.v:3883$293 + attribute \src "ls180.v:3912.161-3912.291" + cell $and $and$ls180.v:3912$357 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3883$291_Y - connect \B $not$ls180.v:3883$292_Y - connect \Y $and$ls180.v:3883$293_Y + connect \A $and$ls180.v:3912$355_Y + connect \B $not$ls180.v:3912$356_Y + connect \Y $and$ls180.v:3912$357_Y end - attribute \src "ls180.v:3883.76-3883.333" - cell $and $and$ls180.v:3883$296 + attribute \src "ls180.v:3912.76-3912.333" + cell $and $and$ls180.v:3912$360 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3883$289_Y - connect \B $or$ls180.v:3883$295_Y - connect \Y $and$ls180.v:3883$296_Y + connect \A $and$ls180.v:3912$353_Y + connect \B $or$ls180.v:3912$359_Y + connect \Y $and$ls180.v:3912$360_Y end - attribute \src "ls180.v:3883.338-3883.505" - cell $and $and$ls180.v:3883$299 + attribute \src "ls180.v:3912.338-3912.505" + cell $and $and$ls180.v:3912$363 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3883$297_Y - connect \B $eq$ls180.v:3883$298_Y - connect \Y $and$ls180.v:3883$299_Y + connect \A $eq$ls180.v:3912$361_Y + connect \B $eq$ls180.v:3912$362_Y + connect \Y $and$ls180.v:3912$363_Y end - attribute \src "ls180.v:3883.38-3883.507" - cell $and $and$ls180.v:3883$301 + attribute \src "ls180.v:3912.38-3912.507" + cell $and $and$ls180.v:3912$365 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_valid - connect \B $or$ls180.v:3883$300_Y - connect \Y $and$ls180.v:3883$301_Y + connect \B $or$ls180.v:3912$364_Y + connect \Y $and$ls180.v:3912$365_Y end - attribute \src "ls180.v:3884.77-3884.153" - cell $and $and$ls180.v:3884$302 + attribute \src "ls180.v:3913.77-3913.153" + cell $and $and$ls180.v:3913$366 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237807,65 +238675,65 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_payload_is_cmd connect \B \main_sdram_choose_cmd_want_cmds - connect \Y $and$ls180.v:3884$302_Y + connect \Y $and$ls180.v:3913$366_Y end - attribute \src "ls180.v:3884.162-3884.246" - cell $and $and$ls180.v:3884$304 + attribute \src "ls180.v:3913.162-3913.246" + cell $and $and$ls180.v:3913$368 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_payload_ras - connect \B $not$ls180.v:3884$303_Y - connect \Y $and$ls180.v:3884$304_Y + connect \B $not$ls180.v:3913$367_Y + connect \Y $and$ls180.v:3913$368_Y end - attribute \src "ls180.v:3884.161-3884.291" - cell $and $and$ls180.v:3884$306 + attribute \src "ls180.v:3913.161-3913.291" + cell $and $and$ls180.v:3913$370 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3884$304_Y - connect \B $not$ls180.v:3884$305_Y - connect \Y $and$ls180.v:3884$306_Y + connect \A $and$ls180.v:3913$368_Y + connect \B $not$ls180.v:3913$369_Y + connect \Y $and$ls180.v:3913$370_Y end - attribute \src "ls180.v:3884.76-3884.333" - cell $and $and$ls180.v:3884$309 + attribute \src "ls180.v:3913.76-3913.333" + cell $and $and$ls180.v:3913$373 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3884$302_Y - connect \B $or$ls180.v:3884$308_Y - connect \Y $and$ls180.v:3884$309_Y + connect \A $and$ls180.v:3913$366_Y + connect \B $or$ls180.v:3913$372_Y + connect \Y $and$ls180.v:3913$373_Y end - attribute \src "ls180.v:3884.338-3884.505" - cell $and $and$ls180.v:3884$312 + attribute \src "ls180.v:3913.338-3913.505" + cell $and $and$ls180.v:3913$376 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3884$310_Y - connect \B $eq$ls180.v:3884$311_Y - connect \Y $and$ls180.v:3884$312_Y + connect \A $eq$ls180.v:3913$374_Y + connect \B $eq$ls180.v:3913$375_Y + connect \Y $and$ls180.v:3913$376_Y end - attribute \src "ls180.v:3884.38-3884.507" - cell $and $and$ls180.v:3884$314 + attribute \src "ls180.v:3913.38-3913.507" + cell $and $and$ls180.v:3913$378 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_valid - connect \B $or$ls180.v:3884$313_Y - connect \Y $and$ls180.v:3884$314_Y + connect \B $or$ls180.v:3913$377_Y + connect \Y $and$ls180.v:3913$378_Y end - attribute \src "ls180.v:3885.77-3885.153" - cell $and $and$ls180.v:3885$315 + attribute \src "ls180.v:3914.77-3914.153" + cell $and $and$ls180.v:3914$379 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237873,65 +238741,65 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_payload_is_cmd connect \B \main_sdram_choose_cmd_want_cmds - connect \Y $and$ls180.v:3885$315_Y + connect \Y $and$ls180.v:3914$379_Y end - attribute \src "ls180.v:3885.162-3885.246" - cell $and $and$ls180.v:3885$317 + attribute \src "ls180.v:3914.162-3914.246" + cell $and $and$ls180.v:3914$381 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_payload_ras - connect \B $not$ls180.v:3885$316_Y - connect \Y $and$ls180.v:3885$317_Y + connect \B $not$ls180.v:3914$380_Y + connect \Y $and$ls180.v:3914$381_Y end - attribute \src "ls180.v:3885.161-3885.291" - cell $and $and$ls180.v:3885$319 + attribute \src "ls180.v:3914.161-3914.291" + cell $and $and$ls180.v:3914$383 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3885$317_Y - connect \B $not$ls180.v:3885$318_Y - connect \Y $and$ls180.v:3885$319_Y + connect \A $and$ls180.v:3914$381_Y + connect \B $not$ls180.v:3914$382_Y + connect \Y $and$ls180.v:3914$383_Y end - attribute \src "ls180.v:3885.76-3885.333" - cell $and $and$ls180.v:3885$322 + attribute \src "ls180.v:3914.76-3914.333" + cell $and $and$ls180.v:3914$386 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3885$315_Y - connect \B $or$ls180.v:3885$321_Y - connect \Y $and$ls180.v:3885$322_Y + connect \A $and$ls180.v:3914$379_Y + connect \B $or$ls180.v:3914$385_Y + connect \Y $and$ls180.v:3914$386_Y end - attribute \src "ls180.v:3885.338-3885.505" - cell $and $and$ls180.v:3885$325 + attribute \src "ls180.v:3914.338-3914.505" + cell $and $and$ls180.v:3914$389 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3885$323_Y - connect \B $eq$ls180.v:3885$324_Y - connect \Y $and$ls180.v:3885$325_Y + connect \A $eq$ls180.v:3914$387_Y + connect \B $eq$ls180.v:3914$388_Y + connect \Y $and$ls180.v:3914$389_Y end - attribute \src "ls180.v:3885.38-3885.507" - cell $and $and$ls180.v:3885$327 + attribute \src "ls180.v:3914.38-3914.507" + cell $and $and$ls180.v:3914$391 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_valid - connect \B $or$ls180.v:3885$326_Y - connect \Y $and$ls180.v:3885$327_Y + connect \B $or$ls180.v:3914$390_Y + connect \Y $and$ls180.v:3914$391_Y end - attribute \src "ls180.v:3886.77-3886.153" - cell $and $and$ls180.v:3886$328 + attribute \src "ls180.v:3915.77-3915.153" + cell $and $and$ls180.v:3915$392 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237939,65 +238807,65 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_payload_is_cmd connect \B \main_sdram_choose_cmd_want_cmds - connect \Y $and$ls180.v:3886$328_Y + connect \Y $and$ls180.v:3915$392_Y end - attribute \src "ls180.v:3886.162-3886.246" - cell $and $and$ls180.v:3886$330 + attribute \src "ls180.v:3915.162-3915.246" + cell $and $and$ls180.v:3915$394 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_payload_ras - connect \B $not$ls180.v:3886$329_Y - connect \Y $and$ls180.v:3886$330_Y + connect \B $not$ls180.v:3915$393_Y + connect \Y $and$ls180.v:3915$394_Y end - attribute \src "ls180.v:3886.161-3886.291" - cell $and $and$ls180.v:3886$332 + attribute \src "ls180.v:3915.161-3915.291" + cell $and $and$ls180.v:3915$396 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3886$330_Y - connect \B $not$ls180.v:3886$331_Y - connect \Y $and$ls180.v:3886$332_Y + connect \A $and$ls180.v:3915$394_Y + connect \B $not$ls180.v:3915$395_Y + connect \Y $and$ls180.v:3915$396_Y end - attribute \src "ls180.v:3886.76-3886.333" - cell $and $and$ls180.v:3886$335 + attribute \src "ls180.v:3915.76-3915.333" + cell $and $and$ls180.v:3915$399 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3886$328_Y - connect \B $or$ls180.v:3886$334_Y - connect \Y $and$ls180.v:3886$335_Y + connect \A $and$ls180.v:3915$392_Y + connect \B $or$ls180.v:3915$398_Y + connect \Y $and$ls180.v:3915$399_Y end - attribute \src "ls180.v:3886.338-3886.505" - cell $and $and$ls180.v:3886$338 + attribute \src "ls180.v:3915.338-3915.505" + cell $and $and$ls180.v:3915$402 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3886$336_Y - connect \B $eq$ls180.v:3886$337_Y - connect \Y $and$ls180.v:3886$338_Y + connect \A $eq$ls180.v:3915$400_Y + connect \B $eq$ls180.v:3915$401_Y + connect \Y $and$ls180.v:3915$402_Y end - attribute \src "ls180.v:3886.38-3886.507" - cell $and $and$ls180.v:3886$340 + attribute \src "ls180.v:3915.38-3915.507" + cell $and $and$ls180.v:3915$404 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_valid - connect \B $or$ls180.v:3886$339_Y - connect \Y $and$ls180.v:3886$340_Y + connect \B $or$ls180.v:3915$403_Y + connect \Y $and$ls180.v:3915$404_Y end - attribute \src "ls180.v:3916.77-3916.153" - cell $and $and$ls180.v:3916$347 + attribute \src "ls180.v:3945.77-3945.153" + cell $and $and$ls180.v:3945$411 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -238005,65 +238873,65 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_payload_is_cmd connect \B \main_sdram_choose_req_want_cmds - connect \Y $and$ls180.v:3916$347_Y + connect \Y $and$ls180.v:3945$411_Y end - attribute \src "ls180.v:3916.162-3916.246" - cell $and $and$ls180.v:3916$349 + attribute \src "ls180.v:3945.162-3945.246" + cell $and $and$ls180.v:3945$413 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_payload_ras - connect \B $not$ls180.v:3916$348_Y - connect \Y $and$ls180.v:3916$349_Y + connect \B $not$ls180.v:3945$412_Y + connect \Y $and$ls180.v:3945$413_Y end - attribute \src "ls180.v:3916.161-3916.291" - cell $and $and$ls180.v:3916$351 + attribute \src "ls180.v:3945.161-3945.291" + cell $and $and$ls180.v:3945$415 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3916$349_Y - connect \B $not$ls180.v:3916$350_Y - connect \Y $and$ls180.v:3916$351_Y + connect \A $and$ls180.v:3945$413_Y + connect \B $not$ls180.v:3945$414_Y + connect \Y $and$ls180.v:3945$415_Y end - attribute \src "ls180.v:3916.76-3916.333" - cell $and $and$ls180.v:3916$354 + attribute \src "ls180.v:3945.76-3945.333" + cell $and $and$ls180.v:3945$418 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3916$347_Y - connect \B $or$ls180.v:3916$353_Y - connect \Y $and$ls180.v:3916$354_Y + connect \A $and$ls180.v:3945$411_Y + connect \B $or$ls180.v:3945$417_Y + connect \Y $and$ls180.v:3945$418_Y end - attribute \src "ls180.v:3916.338-3916.505" - cell $and $and$ls180.v:3916$357 + attribute \src "ls180.v:3945.338-3945.505" + cell $and $and$ls180.v:3945$421 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3916$355_Y - connect \B $eq$ls180.v:3916$356_Y - connect \Y $and$ls180.v:3916$357_Y + connect \A $eq$ls180.v:3945$419_Y + connect \B $eq$ls180.v:3945$420_Y + connect \Y $and$ls180.v:3945$421_Y end - attribute \src "ls180.v:3916.38-3916.507" - cell $and $and$ls180.v:3916$359 + attribute \src "ls180.v:3945.38-3945.507" + cell $and $and$ls180.v:3945$423 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_valid - connect \B $or$ls180.v:3916$358_Y - connect \Y $and$ls180.v:3916$359_Y + connect \B $or$ls180.v:3945$422_Y + connect \Y $and$ls180.v:3945$423_Y end - attribute \src "ls180.v:3917.77-3917.153" - cell $and $and$ls180.v:3917$360 + attribute \src "ls180.v:3946.77-3946.153" + cell $and $and$ls180.v:3946$424 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -238071,65 +238939,65 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_payload_is_cmd connect \B \main_sdram_choose_req_want_cmds - connect \Y $and$ls180.v:3917$360_Y + connect \Y $and$ls180.v:3946$424_Y end - attribute \src "ls180.v:3917.162-3917.246" - cell $and $and$ls180.v:3917$362 + attribute \src "ls180.v:3946.162-3946.246" + cell $and $and$ls180.v:3946$426 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_payload_ras - connect \B $not$ls180.v:3917$361_Y - connect \Y $and$ls180.v:3917$362_Y + connect \B $not$ls180.v:3946$425_Y + connect \Y $and$ls180.v:3946$426_Y end - attribute \src "ls180.v:3917.161-3917.291" - cell $and $and$ls180.v:3917$364 + attribute \src "ls180.v:3946.161-3946.291" + cell $and $and$ls180.v:3946$428 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3917$362_Y - connect \B $not$ls180.v:3917$363_Y - connect \Y $and$ls180.v:3917$364_Y + connect \A $and$ls180.v:3946$426_Y + connect \B $not$ls180.v:3946$427_Y + connect \Y $and$ls180.v:3946$428_Y end - attribute \src "ls180.v:3917.76-3917.333" - cell $and $and$ls180.v:3917$367 + attribute \src "ls180.v:3946.76-3946.333" + cell $and $and$ls180.v:3946$431 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3917$360_Y - connect \B $or$ls180.v:3917$366_Y - connect \Y $and$ls180.v:3917$367_Y + connect \A $and$ls180.v:3946$424_Y + connect \B $or$ls180.v:3946$430_Y + connect \Y $and$ls180.v:3946$431_Y end - attribute \src "ls180.v:3917.338-3917.505" - cell $and $and$ls180.v:3917$370 + attribute \src "ls180.v:3946.338-3946.505" + cell $and $and$ls180.v:3946$434 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3917$368_Y - connect \B $eq$ls180.v:3917$369_Y - connect \Y $and$ls180.v:3917$370_Y + connect \A $eq$ls180.v:3946$432_Y + connect \B $eq$ls180.v:3946$433_Y + connect \Y $and$ls180.v:3946$434_Y end - attribute \src "ls180.v:3917.38-3917.507" - cell $and $and$ls180.v:3917$372 + attribute \src "ls180.v:3946.38-3946.507" + cell $and $and$ls180.v:3946$436 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_valid - connect \B $or$ls180.v:3917$371_Y - connect \Y $and$ls180.v:3917$372_Y + connect \B $or$ls180.v:3946$435_Y + connect \Y $and$ls180.v:3946$436_Y end - attribute \src "ls180.v:3918.77-3918.153" - cell $and $and$ls180.v:3918$373 + attribute \src "ls180.v:3947.77-3947.153" + cell $and $and$ls180.v:3947$437 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -238137,65 +239005,65 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_payload_is_cmd connect \B \main_sdram_choose_req_want_cmds - connect \Y $and$ls180.v:3918$373_Y + connect \Y $and$ls180.v:3947$437_Y end - attribute \src "ls180.v:3918.162-3918.246" - cell $and $and$ls180.v:3918$375 + attribute \src "ls180.v:3947.162-3947.246" + cell $and $and$ls180.v:3947$439 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_payload_ras - connect \B $not$ls180.v:3918$374_Y - connect \Y $and$ls180.v:3918$375_Y + connect \B $not$ls180.v:3947$438_Y + connect \Y $and$ls180.v:3947$439_Y end - attribute \src "ls180.v:3918.161-3918.291" - cell $and $and$ls180.v:3918$377 + attribute \src "ls180.v:3947.161-3947.291" + cell $and $and$ls180.v:3947$441 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3918$375_Y - connect \B $not$ls180.v:3918$376_Y - connect \Y $and$ls180.v:3918$377_Y + connect \A $and$ls180.v:3947$439_Y + connect \B $not$ls180.v:3947$440_Y + connect \Y $and$ls180.v:3947$441_Y end - attribute \src "ls180.v:3918.76-3918.333" - cell $and $and$ls180.v:3918$380 + attribute \src "ls180.v:3947.76-3947.333" + cell $and $and$ls180.v:3947$444 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3918$373_Y - connect \B $or$ls180.v:3918$379_Y - connect \Y $and$ls180.v:3918$380_Y + connect \A $and$ls180.v:3947$437_Y + connect \B $or$ls180.v:3947$443_Y + connect \Y $and$ls180.v:3947$444_Y end - attribute \src "ls180.v:3918.338-3918.505" - cell $and $and$ls180.v:3918$383 + attribute \src "ls180.v:3947.338-3947.505" + cell $and $and$ls180.v:3947$447 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3918$381_Y - connect \B $eq$ls180.v:3918$382_Y - connect \Y $and$ls180.v:3918$383_Y + connect \A $eq$ls180.v:3947$445_Y + connect \B $eq$ls180.v:3947$446_Y + connect \Y $and$ls180.v:3947$447_Y end - attribute \src "ls180.v:3918.38-3918.507" - cell $and $and$ls180.v:3918$385 + attribute \src "ls180.v:3947.38-3947.507" + cell $and $and$ls180.v:3947$449 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_valid - connect \B $or$ls180.v:3918$384_Y - connect \Y $and$ls180.v:3918$385_Y + connect \B $or$ls180.v:3947$448_Y + connect \Y $and$ls180.v:3947$449_Y end - attribute \src "ls180.v:3919.77-3919.153" - cell $and $and$ls180.v:3919$386 + attribute \src "ls180.v:3948.77-3948.153" + cell $and $and$ls180.v:3948$450 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -238203,65 +239071,65 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_payload_is_cmd connect \B \main_sdram_choose_req_want_cmds - connect \Y $and$ls180.v:3919$386_Y + connect \Y $and$ls180.v:3948$450_Y end - attribute \src "ls180.v:3919.162-3919.246" - cell $and $and$ls180.v:3919$388 + attribute \src "ls180.v:3948.162-3948.246" + cell $and $and$ls180.v:3948$452 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_payload_ras - connect \B $not$ls180.v:3919$387_Y - connect \Y $and$ls180.v:3919$388_Y + connect \B $not$ls180.v:3948$451_Y + connect \Y $and$ls180.v:3948$452_Y end - attribute \src "ls180.v:3919.161-3919.291" - cell $and $and$ls180.v:3919$390 + attribute \src "ls180.v:3948.161-3948.291" + cell $and $and$ls180.v:3948$454 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3919$388_Y - connect \B $not$ls180.v:3919$389_Y - connect \Y $and$ls180.v:3919$390_Y + connect \A $and$ls180.v:3948$452_Y + connect \B $not$ls180.v:3948$453_Y + connect \Y $and$ls180.v:3948$454_Y end - attribute \src "ls180.v:3919.76-3919.333" - cell $and $and$ls180.v:3919$393 + attribute \src "ls180.v:3948.76-3948.333" + cell $and $and$ls180.v:3948$457 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3919$386_Y - connect \B $or$ls180.v:3919$392_Y - connect \Y $and$ls180.v:3919$393_Y + connect \A $and$ls180.v:3948$450_Y + connect \B $or$ls180.v:3948$456_Y + connect \Y $and$ls180.v:3948$457_Y end - attribute \src "ls180.v:3919.338-3919.505" - cell $and $and$ls180.v:3919$396 + attribute \src "ls180.v:3948.338-3948.505" + cell $and $and$ls180.v:3948$460 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3919$394_Y - connect \B $eq$ls180.v:3919$395_Y - connect \Y $and$ls180.v:3919$396_Y + connect \A $eq$ls180.v:3948$458_Y + connect \B $eq$ls180.v:3948$459_Y + connect \Y $and$ls180.v:3948$460_Y end - attribute \src "ls180.v:3919.38-3919.507" - cell $and $and$ls180.v:3919$398 + attribute \src "ls180.v:3948.38-3948.507" + cell $and $and$ls180.v:3948$462 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_valid - connect \B $or$ls180.v:3919$397_Y - connect \Y $and$ls180.v:3919$398_Y + connect \B $or$ls180.v:3948$461_Y + connect \Y $and$ls180.v:3948$462_Y end - attribute \src "ls180.v:3948.8-3948.73" - cell $and $and$ls180.v:3948$403 + attribute \src "ls180.v:3977.8-3977.73" + cell $and $and$ls180.v:3977$467 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -238269,21 +239137,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_cmd_cmd_valid connect \B \main_sdram_choose_cmd_cmd_ready - connect \Y $and$ls180.v:3948$403_Y + connect \Y $and$ls180.v:3977$467_Y end - attribute \src "ls180.v:3948.7-3948.114" - cell $and $and$ls180.v:3948$405 + attribute \src "ls180.v:3977.7-3977.114" + cell $and $and$ls180.v:3977$469 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3948$403_Y - connect \B $eq$ls180.v:3948$404_Y - connect \Y $and$ls180.v:3948$405_Y + connect \A $and$ls180.v:3977$467_Y + connect \B $eq$ls180.v:3977$468_Y + connect \Y $and$ls180.v:3977$469_Y end - attribute \src "ls180.v:3951.8-3951.73" - cell $and $and$ls180.v:3951$406 + attribute \src "ls180.v:3980.8-3980.73" + cell $and $and$ls180.v:3980$470 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -238291,21 +239159,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3951$406_Y + connect \Y $and$ls180.v:3980$470_Y end - attribute \src "ls180.v:3951.7-3951.114" - cell $and $and$ls180.v:3951$408 + attribute \src "ls180.v:3980.7-3980.114" + cell $and $and$ls180.v:3980$472 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3951$406_Y - connect \B $eq$ls180.v:3951$407_Y - connect \Y $and$ls180.v:3951$408_Y + connect \A $and$ls180.v:3980$470_Y + connect \B $eq$ls180.v:3980$471_Y + connect \Y $and$ls180.v:3980$472_Y end - attribute \src "ls180.v:3957.8-3957.73" - cell $and $and$ls180.v:3957$410 + attribute \src "ls180.v:3986.8-3986.73" + cell $and $and$ls180.v:3986$474 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -238313,21 +239181,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_cmd_cmd_valid connect \B \main_sdram_choose_cmd_cmd_ready - connect \Y $and$ls180.v:3957$410_Y + connect \Y $and$ls180.v:3986$474_Y end - attribute \src "ls180.v:3957.7-3957.114" - cell $and $and$ls180.v:3957$412 + attribute \src "ls180.v:3986.7-3986.114" + cell $and $and$ls180.v:3986$476 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3957$410_Y - connect \B $eq$ls180.v:3957$411_Y - connect \Y $and$ls180.v:3957$412_Y + connect \A $and$ls180.v:3986$474_Y + connect \B $eq$ls180.v:3986$475_Y + connect \Y $and$ls180.v:3986$476_Y end - attribute \src "ls180.v:3960.8-3960.73" - cell $and $and$ls180.v:3960$413 + attribute \src "ls180.v:3989.8-3989.73" + cell $and $and$ls180.v:3989$477 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -238335,21 +239203,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3960$413_Y + connect \Y $and$ls180.v:3989$477_Y end - attribute \src "ls180.v:3960.7-3960.114" - cell $and $and$ls180.v:3960$415 + attribute \src "ls180.v:3989.7-3989.114" + cell $and $and$ls180.v:3989$479 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3960$413_Y - connect \B $eq$ls180.v:3960$414_Y - connect \Y $and$ls180.v:3960$415_Y + connect \A $and$ls180.v:3989$477_Y + connect \B $eq$ls180.v:3989$478_Y + connect \Y $and$ls180.v:3989$479_Y end - attribute \src "ls180.v:3966.8-3966.73" - cell $and $and$ls180.v:3966$417 + attribute \src "ls180.v:3995.8-3995.73" + cell $and $and$ls180.v:3995$481 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -238357,21 +239225,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_cmd_cmd_valid connect \B \main_sdram_choose_cmd_cmd_ready - connect \Y $and$ls180.v:3966$417_Y + connect \Y $and$ls180.v:3995$481_Y end - attribute \src "ls180.v:3966.7-3966.114" - cell $and $and$ls180.v:3966$419 + attribute \src "ls180.v:3995.7-3995.114" + cell $and $and$ls180.v:3995$483 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3966$417_Y - connect \B $eq$ls180.v:3966$418_Y - connect \Y $and$ls180.v:3966$419_Y + connect \A $and$ls180.v:3995$481_Y + connect \B $eq$ls180.v:3995$482_Y + connect \Y $and$ls180.v:3995$483_Y end - attribute \src "ls180.v:3969.8-3969.73" - cell $and $and$ls180.v:3969$420 + attribute \src "ls180.v:3998.8-3998.73" + cell $and $and$ls180.v:3998$484 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -238379,21 +239247,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3969$420_Y + connect \Y $and$ls180.v:3998$484_Y end - attribute \src "ls180.v:3969.7-3969.114" - cell $and $and$ls180.v:3969$422 + attribute \src "ls180.v:3998.7-3998.114" + cell $and $and$ls180.v:3998$486 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3969$420_Y - connect \B $eq$ls180.v:3969$421_Y - connect \Y $and$ls180.v:3969$422_Y + connect \A $and$ls180.v:3998$484_Y + connect \B $eq$ls180.v:3998$485_Y + connect \Y $and$ls180.v:3998$486_Y end - attribute \src "ls180.v:3975.8-3975.73" - cell $and $and$ls180.v:3975$424 + attribute \src "ls180.v:4004.8-4004.73" + cell $and $and$ls180.v:4004$488 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -238401,21 +239269,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_cmd_cmd_valid connect \B \main_sdram_choose_cmd_cmd_ready - connect \Y $and$ls180.v:3975$424_Y + connect \Y $and$ls180.v:4004$488_Y end - attribute \src "ls180.v:3975.7-3975.114" - cell $and $and$ls180.v:3975$426 + attribute \src "ls180.v:4004.7-4004.114" + cell $and $and$ls180.v:4004$490 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3975$424_Y - connect \B $eq$ls180.v:3975$425_Y - connect \Y $and$ls180.v:3975$426_Y + connect \A $and$ls180.v:4004$488_Y + connect \B $eq$ls180.v:4004$489_Y + connect \Y $and$ls180.v:4004$490_Y end - attribute \src "ls180.v:3978.8-3978.73" - cell $and $and$ls180.v:3978$427 + attribute \src "ls180.v:4007.8-4007.73" + cell $and $and$ls180.v:4007$491 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -238423,615 +239291,615 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3978$427_Y + connect \Y $and$ls180.v:4007$491_Y end - attribute \src "ls180.v:3978.7-3978.114" - cell $and $and$ls180.v:3978$429 + attribute \src "ls180.v:4007.7-4007.114" + cell $and $and$ls180.v:4007$493 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3978$427_Y - connect \B $eq$ls180.v:3978$428_Y - connect \Y $and$ls180.v:3978$429_Y + connect \A $and$ls180.v:4007$491_Y + connect \B $eq$ls180.v:4007$492_Y + connect \Y $and$ls180.v:4007$493_Y end - attribute \src "ls180.v:4003.71-4003.151" - cell $and $and$ls180.v:4003$434 + attribute \src "ls180.v:4032.71-4032.151" + cell $and $and$ls180.v:4032$498 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_ras - connect \B $not$ls180.v:4003$433_Y - connect \Y $and$ls180.v:4003$434_Y + connect \B $not$ls180.v:4032$497_Y + connect \Y $and$ls180.v:4032$498_Y end - attribute \src "ls180.v:4003.70-4003.194" - cell $and $and$ls180.v:4003$436 + attribute \src "ls180.v:4032.70-4032.194" + cell $and $and$ls180.v:4032$500 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4003$434_Y - connect \B $not$ls180.v:4003$435_Y - connect \Y $and$ls180.v:4003$436_Y + connect \A $and$ls180.v:4032$498_Y + connect \B $not$ls180.v:4032$499_Y + connect \Y $and$ls180.v:4032$500_Y end - attribute \src "ls180.v:4003.41-4003.222" - cell $and $and$ls180.v:4003$439 + attribute \src "ls180.v:4032.41-4032.222" + cell $and $and$ls180.v:4032$503 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_cas_allowed - connect \B $or$ls180.v:4003$438_Y - connect \Y $and$ls180.v:4003$439_Y + connect \B $or$ls180.v:4032$502_Y + connect \Y $and$ls180.v:4032$503_Y end - attribute \src "ls180.v:4041.71-4041.151" - cell $and $and$ls180.v:4041$443 + attribute \src "ls180.v:4070.71-4070.151" + cell $and $and$ls180.v:4070$507 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_ras - connect \B $not$ls180.v:4041$442_Y - connect \Y $and$ls180.v:4041$443_Y + connect \B $not$ls180.v:4070$506_Y + connect \Y $and$ls180.v:4070$507_Y end - attribute \src "ls180.v:4041.70-4041.194" - cell $and $and$ls180.v:4041$445 + attribute \src "ls180.v:4070.70-4070.194" + cell $and $and$ls180.v:4070$509 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4041$443_Y - connect \B $not$ls180.v:4041$444_Y - connect \Y $and$ls180.v:4041$445_Y + connect \A $and$ls180.v:4070$507_Y + connect \B $not$ls180.v:4070$508_Y + connect \Y $and$ls180.v:4070$509_Y end - attribute \src "ls180.v:4041.41-4041.222" - cell $and $and$ls180.v:4041$448 + attribute \src "ls180.v:4070.41-4070.222" + cell $and $and$ls180.v:4070$512 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_cas_allowed - connect \B $or$ls180.v:4041$447_Y - connect \Y $and$ls180.v:4041$448_Y + connect \B $or$ls180.v:4070$511_Y + connect \Y $and$ls180.v:4070$512_Y end - attribute \src "ls180.v:4059.110-4059.179" - cell $and $and$ls180.v:4059$453 + attribute \src "ls180.v:4088.110-4088.179" + cell $and $and$ls180.v:4088$517 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:4059$452_Y - connect \Y $and$ls180.v:4059$453_Y + connect \B $eq$ls180.v:4088$516_Y + connect \Y $and$ls180.v:4088$517_Y end - attribute \src "ls180.v:4059.185-4059.254" - cell $and $and$ls180.v:4059$456 + attribute \src "ls180.v:4088.185-4088.254" + cell $and $and$ls180.v:4088$520 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:4059$455_Y - connect \Y $and$ls180.v:4059$456_Y + connect \B $eq$ls180.v:4088$519_Y + connect \Y $and$ls180.v:4088$520_Y end - attribute \src "ls180.v:4059.260-4059.329" - cell $and $and$ls180.v:4059$459 + attribute \src "ls180.v:4088.260-4088.329" + cell $and $and$ls180.v:4088$523 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:4059$458_Y - connect \Y $and$ls180.v:4059$459_Y + connect \B $eq$ls180.v:4088$522_Y + connect \Y $and$ls180.v:4088$523_Y end - attribute \src "ls180.v:4059.41-4059.332" - cell $and $and$ls180.v:4059$462 + attribute \src "ls180.v:4088.41-4088.332" + cell $and $and$ls180.v:4088$526 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4059$451_Y - connect \B $not$ls180.v:4059$461_Y - connect \Y $and$ls180.v:4059$462_Y + connect \A $eq$ls180.v:4088$515_Y + connect \B $not$ls180.v:4088$525_Y + connect \Y $and$ls180.v:4088$526_Y end - attribute \src "ls180.v:4059.40-4059.355" - cell $and $and$ls180.v:4059$463 + attribute \src "ls180.v:4088.40-4088.355" + cell $and $and$ls180.v:4088$527 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4059$462_Y + connect \A $and$ls180.v:4088$526_Y connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:4059$463_Y + connect \Y $and$ls180.v:4088$527_Y end - attribute \src "ls180.v:4060.34-4060.106" - cell $and $and$ls180.v:4060$466 + attribute \src "ls180.v:4089.34-4089.106" + cell $and $and$ls180.v:4089$530 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4060$464_Y - connect \B $not$ls180.v:4060$465_Y - connect \Y $and$ls180.v:4060$466_Y + connect \A $not$ls180.v:4089$528_Y + connect \B $not$ls180.v:4089$529_Y + connect \Y $and$ls180.v:4089$530_Y end - attribute \src "ls180.v:4064.110-4064.179" - cell $and $and$ls180.v:4064$469 + attribute \src "ls180.v:4093.110-4093.179" + cell $and $and$ls180.v:4093$533 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:4064$468_Y - connect \Y $and$ls180.v:4064$469_Y + connect \B $eq$ls180.v:4093$532_Y + connect \Y $and$ls180.v:4093$533_Y end - attribute \src "ls180.v:4064.185-4064.254" - cell $and $and$ls180.v:4064$472 + attribute \src "ls180.v:4093.185-4093.254" + cell $and $and$ls180.v:4093$536 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:4064$471_Y - connect \Y $and$ls180.v:4064$472_Y + connect \B $eq$ls180.v:4093$535_Y + connect \Y $and$ls180.v:4093$536_Y end - attribute \src "ls180.v:4064.260-4064.329" - cell $and $and$ls180.v:4064$475 + attribute \src "ls180.v:4093.260-4093.329" + cell $and $and$ls180.v:4093$539 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:4064$474_Y - connect \Y $and$ls180.v:4064$475_Y + connect \B $eq$ls180.v:4093$538_Y + connect \Y $and$ls180.v:4093$539_Y end - attribute \src "ls180.v:4064.41-4064.332" - cell $and $and$ls180.v:4064$478 + attribute \src "ls180.v:4093.41-4093.332" + cell $and $and$ls180.v:4093$542 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4064$467_Y - connect \B $not$ls180.v:4064$477_Y - connect \Y $and$ls180.v:4064$478_Y + connect \A $eq$ls180.v:4093$531_Y + connect \B $not$ls180.v:4093$541_Y + connect \Y $and$ls180.v:4093$542_Y end - attribute \src "ls180.v:4064.40-4064.355" - cell $and $and$ls180.v:4064$479 + attribute \src "ls180.v:4093.40-4093.355" + cell $and $and$ls180.v:4093$543 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4064$478_Y + connect \A $and$ls180.v:4093$542_Y connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:4064$479_Y + connect \Y $and$ls180.v:4093$543_Y end - attribute \src "ls180.v:4065.34-4065.106" - cell $and $and$ls180.v:4065$482 + attribute \src "ls180.v:4094.34-4094.106" + cell $and $and$ls180.v:4094$546 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4065$480_Y - connect \B $not$ls180.v:4065$481_Y - connect \Y $and$ls180.v:4065$482_Y + connect \A $not$ls180.v:4094$544_Y + connect \B $not$ls180.v:4094$545_Y + connect \Y $and$ls180.v:4094$546_Y end - attribute \src "ls180.v:4069.110-4069.179" - cell $and $and$ls180.v:4069$485 + attribute \src "ls180.v:4098.110-4098.179" + cell $and $and$ls180.v:4098$549 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:4069$484_Y - connect \Y $and$ls180.v:4069$485_Y + connect \B $eq$ls180.v:4098$548_Y + connect \Y $and$ls180.v:4098$549_Y end - attribute \src "ls180.v:4069.185-4069.254" - cell $and $and$ls180.v:4069$488 + attribute \src "ls180.v:4098.185-4098.254" + cell $and $and$ls180.v:4098$552 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:4069$487_Y - connect \Y $and$ls180.v:4069$488_Y + connect \B $eq$ls180.v:4098$551_Y + connect \Y $and$ls180.v:4098$552_Y end - attribute \src "ls180.v:4069.260-4069.329" - cell $and $and$ls180.v:4069$491 + attribute \src "ls180.v:4098.260-4098.329" + cell $and $and$ls180.v:4098$555 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:4069$490_Y - connect \Y $and$ls180.v:4069$491_Y + connect \B $eq$ls180.v:4098$554_Y + connect \Y $and$ls180.v:4098$555_Y end - attribute \src "ls180.v:4069.41-4069.332" - cell $and $and$ls180.v:4069$494 + attribute \src "ls180.v:4098.41-4098.332" + cell $and $and$ls180.v:4098$558 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4069$483_Y - connect \B $not$ls180.v:4069$493_Y - connect \Y $and$ls180.v:4069$494_Y + connect \A $eq$ls180.v:4098$547_Y + connect \B $not$ls180.v:4098$557_Y + connect \Y $and$ls180.v:4098$558_Y end - attribute \src "ls180.v:4069.40-4069.355" - cell $and $and$ls180.v:4069$495 + attribute \src "ls180.v:4098.40-4098.355" + cell $and $and$ls180.v:4098$559 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4069$494_Y + connect \A $and$ls180.v:4098$558_Y connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:4069$495_Y + connect \Y $and$ls180.v:4098$559_Y end - attribute \src "ls180.v:4070.34-4070.106" - cell $and $and$ls180.v:4070$498 + attribute \src "ls180.v:4099.34-4099.106" + cell $and $and$ls180.v:4099$562 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4070$496_Y - connect \B $not$ls180.v:4070$497_Y - connect \Y $and$ls180.v:4070$498_Y + connect \A $not$ls180.v:4099$560_Y + connect \B $not$ls180.v:4099$561_Y + connect \Y $and$ls180.v:4099$562_Y end - attribute \src "ls180.v:4074.110-4074.179" - cell $and $and$ls180.v:4074$501 + attribute \src "ls180.v:4103.110-4103.179" + cell $and $and$ls180.v:4103$565 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:4074$500_Y - connect \Y $and$ls180.v:4074$501_Y + connect \B $eq$ls180.v:4103$564_Y + connect \Y $and$ls180.v:4103$565_Y end - attribute \src "ls180.v:4074.185-4074.254" - cell $and $and$ls180.v:4074$504 + attribute \src "ls180.v:4103.185-4103.254" + cell $and $and$ls180.v:4103$568 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:4074$503_Y - connect \Y $and$ls180.v:4074$504_Y + connect \B $eq$ls180.v:4103$567_Y + connect \Y $and$ls180.v:4103$568_Y end - attribute \src "ls180.v:4074.260-4074.329" - cell $and $and$ls180.v:4074$507 + attribute \src "ls180.v:4103.260-4103.329" + cell $and $and$ls180.v:4103$571 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:4074$506_Y - connect \Y $and$ls180.v:4074$507_Y + connect \B $eq$ls180.v:4103$570_Y + connect \Y $and$ls180.v:4103$571_Y end - attribute \src "ls180.v:4074.41-4074.332" - cell $and $and$ls180.v:4074$510 + attribute \src "ls180.v:4103.41-4103.332" + cell $and $and$ls180.v:4103$574 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4074$499_Y - connect \B $not$ls180.v:4074$509_Y - connect \Y $and$ls180.v:4074$510_Y + connect \A $eq$ls180.v:4103$563_Y + connect \B $not$ls180.v:4103$573_Y + connect \Y $and$ls180.v:4103$574_Y end - attribute \src "ls180.v:4074.40-4074.355" - cell $and $and$ls180.v:4074$511 + attribute \src "ls180.v:4103.40-4103.355" + cell $and $and$ls180.v:4103$575 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4074$510_Y + connect \A $and$ls180.v:4103$574_Y connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:4074$511_Y + connect \Y $and$ls180.v:4103$575_Y end - attribute \src "ls180.v:4075.34-4075.106" - cell $and $and$ls180.v:4075$514 + attribute \src "ls180.v:4104.34-4104.106" + cell $and $and$ls180.v:4104$578 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4075$512_Y - connect \B $not$ls180.v:4075$513_Y - connect \Y $and$ls180.v:4075$514_Y + connect \A $not$ls180.v:4104$576_Y + connect \B $not$ls180.v:4104$577_Y + connect \Y $and$ls180.v:4104$578_Y end - attribute \src "ls180.v:4079.151-4079.220" - cell $and $and$ls180.v:4079$518 + attribute \src "ls180.v:4108.151-4108.220" + cell $and $and$ls180.v:4108$582 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:4079$517_Y - connect \Y $and$ls180.v:4079$518_Y + connect \B $eq$ls180.v:4108$581_Y + connect \Y $and$ls180.v:4108$582_Y end - attribute \src "ls180.v:4079.226-4079.295" - cell $and $and$ls180.v:4079$521 + attribute \src "ls180.v:4108.226-4108.295" + cell $and $and$ls180.v:4108$585 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:4079$520_Y - connect \Y $and$ls180.v:4079$521_Y + connect \B $eq$ls180.v:4108$584_Y + connect \Y $and$ls180.v:4108$585_Y end - attribute \src "ls180.v:4079.301-4079.370" - cell $and $and$ls180.v:4079$524 + attribute \src "ls180.v:4108.301-4108.370" + cell $and $and$ls180.v:4108$588 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:4079$523_Y - connect \Y $and$ls180.v:4079$524_Y + connect \B $eq$ls180.v:4108$587_Y + connect \Y $and$ls180.v:4108$588_Y end - attribute \src "ls180.v:4079.82-4079.373" - cell $and $and$ls180.v:4079$527 + attribute \src "ls180.v:4108.82-4108.373" + cell $and $and$ls180.v:4108$591 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4079$516_Y - connect \B $not$ls180.v:4079$526_Y - connect \Y $and$ls180.v:4079$527_Y + connect \A $eq$ls180.v:4108$580_Y + connect \B $not$ls180.v:4108$590_Y + connect \Y $and$ls180.v:4108$591_Y end - attribute \src "ls180.v:4079.43-4079.374" - cell $and $and$ls180.v:4079$528 + attribute \src "ls180.v:4108.43-4108.374" + cell $and $and$ls180.v:4108$592 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4079$515_Y - connect \B $and$ls180.v:4079$527_Y - connect \Y $and$ls180.v:4079$528_Y + connect \A $eq$ls180.v:4108$579_Y + connect \B $and$ls180.v:4108$591_Y + connect \Y $and$ls180.v:4108$592_Y end - attribute \src "ls180.v:4079.42-4079.410" - cell $and $and$ls180.v:4079$529 + attribute \src "ls180.v:4108.42-4108.410" + cell $and $and$ls180.v:4108$593 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4079$528_Y + connect \A $and$ls180.v:4108$592_Y connect \B \main_sdram_interface_bank0_ready - connect \Y $and$ls180.v:4079$529_Y + connect \Y $and$ls180.v:4108$593_Y end - attribute \src "ls180.v:4079.525-4079.594" - cell $and $and$ls180.v:4079$534 + attribute \src "ls180.v:4108.525-4108.594" + cell $and $and$ls180.v:4108$598 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:4079$533_Y - connect \Y $and$ls180.v:4079$534_Y + connect \B $eq$ls180.v:4108$597_Y + connect \Y $and$ls180.v:4108$598_Y end - attribute \src "ls180.v:4079.600-4079.669" - cell $and $and$ls180.v:4079$537 + attribute \src "ls180.v:4108.600-4108.669" + cell $and $and$ls180.v:4108$601 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:4079$536_Y - connect \Y $and$ls180.v:4079$537_Y + connect \B $eq$ls180.v:4108$600_Y + connect \Y $and$ls180.v:4108$601_Y end - attribute \src "ls180.v:4079.675-4079.744" - cell $and $and$ls180.v:4079$540 + attribute \src "ls180.v:4108.675-4108.744" + cell $and $and$ls180.v:4108$604 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:4079$539_Y - connect \Y $and$ls180.v:4079$540_Y + connect \B $eq$ls180.v:4108$603_Y + connect \Y $and$ls180.v:4108$604_Y end - attribute \src "ls180.v:4079.456-4079.747" - cell $and $and$ls180.v:4079$543 + attribute \src "ls180.v:4108.456-4108.747" + cell $and $and$ls180.v:4108$607 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4079$532_Y - connect \B $not$ls180.v:4079$542_Y - connect \Y $and$ls180.v:4079$543_Y + connect \A $eq$ls180.v:4108$596_Y + connect \B $not$ls180.v:4108$606_Y + connect \Y $and$ls180.v:4108$607_Y end - attribute \src "ls180.v:4079.417-4079.748" - cell $and $and$ls180.v:4079$544 + attribute \src "ls180.v:4108.417-4108.748" + cell $and $and$ls180.v:4108$608 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4079$531_Y - connect \B $and$ls180.v:4079$543_Y - connect \Y $and$ls180.v:4079$544_Y + connect \A $eq$ls180.v:4108$595_Y + connect \B $and$ls180.v:4108$607_Y + connect \Y $and$ls180.v:4108$608_Y end - attribute \src "ls180.v:4079.416-4079.784" - cell $and $and$ls180.v:4079$545 + attribute \src "ls180.v:4108.416-4108.784" + cell $and $and$ls180.v:4108$609 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4079$544_Y + connect \A $and$ls180.v:4108$608_Y connect \B \main_sdram_interface_bank1_ready - connect \Y $and$ls180.v:4079$545_Y + connect \Y $and$ls180.v:4108$609_Y end - attribute \src "ls180.v:4079.899-4079.968" - cell $and $and$ls180.v:4079$550 + attribute \src "ls180.v:4108.899-4108.968" + cell $and $and$ls180.v:4108$614 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:4079$549_Y - connect \Y $and$ls180.v:4079$550_Y + connect \B $eq$ls180.v:4108$613_Y + connect \Y $and$ls180.v:4108$614_Y end - attribute \src "ls180.v:4079.974-4079.1043" - cell $and $and$ls180.v:4079$553 + attribute \src "ls180.v:4108.974-4108.1043" + cell $and $and$ls180.v:4108$617 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:4079$552_Y - connect \Y $and$ls180.v:4079$553_Y + connect \B $eq$ls180.v:4108$616_Y + connect \Y $and$ls180.v:4108$617_Y end - attribute \src "ls180.v:4079.1049-4079.1118" - cell $and $and$ls180.v:4079$556 + attribute \src "ls180.v:4108.1049-4108.1118" + cell $and $and$ls180.v:4108$620 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:4079$555_Y - connect \Y $and$ls180.v:4079$556_Y + connect \B $eq$ls180.v:4108$619_Y + connect \Y $and$ls180.v:4108$620_Y end - attribute \src "ls180.v:4079.830-4079.1121" - cell $and $and$ls180.v:4079$559 + attribute \src "ls180.v:4108.830-4108.1121" + cell $and $and$ls180.v:4108$623 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4079$548_Y - connect \B $not$ls180.v:4079$558_Y - connect \Y $and$ls180.v:4079$559_Y + connect \A $eq$ls180.v:4108$612_Y + connect \B $not$ls180.v:4108$622_Y + connect \Y $and$ls180.v:4108$623_Y end - attribute \src "ls180.v:4079.791-4079.1122" - cell $and $and$ls180.v:4079$560 + attribute \src "ls180.v:4108.791-4108.1122" + cell $and $and$ls180.v:4108$624 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4079$547_Y - connect \B $and$ls180.v:4079$559_Y - connect \Y $and$ls180.v:4079$560_Y + connect \A $eq$ls180.v:4108$611_Y + connect \B $and$ls180.v:4108$623_Y + connect \Y $and$ls180.v:4108$624_Y end - attribute \src "ls180.v:4079.790-4079.1158" - cell $and $and$ls180.v:4079$561 + attribute \src "ls180.v:4108.790-4108.1158" + cell $and $and$ls180.v:4108$625 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4079$560_Y + connect \A $and$ls180.v:4108$624_Y connect \B \main_sdram_interface_bank2_ready - connect \Y $and$ls180.v:4079$561_Y + connect \Y $and$ls180.v:4108$625_Y end - attribute \src "ls180.v:4079.1273-4079.1342" - cell $and $and$ls180.v:4079$566 + attribute \src "ls180.v:4108.1273-4108.1342" + cell $and $and$ls180.v:4108$630 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:4079$565_Y - connect \Y $and$ls180.v:4079$566_Y + connect \B $eq$ls180.v:4108$629_Y + connect \Y $and$ls180.v:4108$630_Y end - attribute \src "ls180.v:4079.1348-4079.1417" - cell $and $and$ls180.v:4079$569 + attribute \src "ls180.v:4108.1348-4108.1417" + cell $and $and$ls180.v:4108$633 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:4079$568_Y - connect \Y $and$ls180.v:4079$569_Y + connect \B $eq$ls180.v:4108$632_Y + connect \Y $and$ls180.v:4108$633_Y end - attribute \src "ls180.v:4079.1423-4079.1492" - cell $and $and$ls180.v:4079$572 + attribute \src "ls180.v:4108.1423-4108.1492" + cell $and $and$ls180.v:4108$636 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:4079$571_Y - connect \Y $and$ls180.v:4079$572_Y + connect \B $eq$ls180.v:4108$635_Y + connect \Y $and$ls180.v:4108$636_Y end - attribute \src "ls180.v:4079.1204-4079.1495" - cell $and $and$ls180.v:4079$575 + attribute \src "ls180.v:4108.1204-4108.1495" + cell $and $and$ls180.v:4108$639 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4079$564_Y - connect \B $not$ls180.v:4079$574_Y - connect \Y $and$ls180.v:4079$575_Y + connect \A $eq$ls180.v:4108$628_Y + connect \B $not$ls180.v:4108$638_Y + connect \Y $and$ls180.v:4108$639_Y end - attribute \src "ls180.v:4079.1165-4079.1496" - cell $and $and$ls180.v:4079$576 + attribute \src "ls180.v:4108.1165-4108.1496" + cell $and $and$ls180.v:4108$640 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4079$563_Y - connect \B $and$ls180.v:4079$575_Y - connect \Y $and$ls180.v:4079$576_Y + connect \A $eq$ls180.v:4108$627_Y + connect \B $and$ls180.v:4108$639_Y + connect \Y $and$ls180.v:4108$640_Y end - attribute \src "ls180.v:4079.1164-4079.1532" - cell $and $and$ls180.v:4079$577 + attribute \src "ls180.v:4108.1164-4108.1532" + cell $and $and$ls180.v:4108$641 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4079$576_Y + connect \A $and$ls180.v:4108$640_Y connect \B \main_sdram_interface_bank3_ready - connect \Y $and$ls180.v:4079$577_Y + connect \Y $and$ls180.v:4108$641_Y end - attribute \src "ls180.v:4137.9-4137.46" - cell $and $and$ls180.v:4137$583 + attribute \src "ls180.v:4166.9-4166.46" + cell $and $and$ls180.v:4166$647 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239039,10 +239907,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_wb_sdram_stb connect \B \main_wb_sdram_cyc - connect \Y $and$ls180.v:4137$583_Y + connect \Y $and$ls180.v:4166$647_Y end - attribute \src "ls180.v:4155.9-4155.46" - cell $and $and$ls180.v:4155$590 + attribute \src "ls180.v:4184.9-4184.46" + cell $and $and$ls180.v:4184$654 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239050,10 +239918,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_wb_sdram_stb connect \B \main_wb_sdram_cyc - connect \Y $and$ls180.v:4155$590_Y + connect \Y $and$ls180.v:4184$654_Y end - attribute \src "ls180.v:4168.32-4168.75" - cell $and $and$ls180.v:4168$594 + attribute \src "ls180.v:4197.32-4197.75" + cell $and $and$ls180.v:4197$658 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239061,54 +239929,54 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_litedram_wb_cyc connect \B \main_litedram_wb_stb - connect \Y $and$ls180.v:4168$594_Y + connect \Y $and$ls180.v:4197$658_Y end - attribute \src "ls180.v:4168.31-4168.99" - cell $and $and$ls180.v:4168$596 + attribute \src "ls180.v:4197.31-4197.99" + cell $and $and$ls180.v:4197$660 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4168$594_Y - connect \B $not$ls180.v:4168$595_Y - connect \Y $and$ls180.v:4168$596_Y + connect \A $and$ls180.v:4197$658_Y + connect \B $not$ls180.v:4197$659_Y + connect \Y $and$ls180.v:4197$660_Y end - attribute \src "ls180.v:4169.34-4169.102" - cell $and $and$ls180.v:4169$598 + attribute \src "ls180.v:4198.34-4198.102" + cell $and $and$ls180.v:4198$662 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4169$597_Y + connect \A $or$ls180.v:4198$661_Y connect \B \main_port_cmd_payload_we - connect \Y $and$ls180.v:4169$598_Y + connect \Y $and$ls180.v:4198$662_Y end - attribute \src "ls180.v:4169.33-4169.128" - cell $and $and$ls180.v:4169$600 + attribute \src "ls180.v:4198.33-4198.128" + cell $and $and$ls180.v:4198$664 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4169$598_Y - connect \B $not$ls180.v:4169$599_Y - connect \Y $and$ls180.v:4169$600_Y + connect \A $and$ls180.v:4198$662_Y + connect \B $not$ls180.v:4198$663_Y + connect \Y $and$ls180.v:4198$664_Y end - attribute \src "ls180.v:4170.33-4170.104" - cell $and $and$ls180.v:4170$603 + attribute \src "ls180.v:4199.33-4199.104" + cell $and $and$ls180.v:4199$667 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4170$601_Y - connect \B $not$ls180.v:4170$602_Y - connect \Y $and$ls180.v:4170$603_Y + connect \A $or$ls180.v:4199$665_Y + connect \B $not$ls180.v:4199$666_Y + connect \Y $and$ls180.v:4199$667_Y end - attribute \src "ls180.v:4171.49-4171.85" - cell $and $and$ls180.v:4171$604 + attribute \src "ls180.v:4200.49-4200.85" + cell $and $and$ls180.v:4200$668 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239116,32 +239984,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_litedram_wb_we connect \B \main_ack_wdata - connect \Y $and$ls180.v:4171$604_Y + connect \Y $and$ls180.v:4200$668_Y end - attribute \src "ls180.v:4171.90-4171.129" - cell $and $and$ls180.v:4171$606 + attribute \src "ls180.v:4200.90-4200.129" + cell $and $and$ls180.v:4200$670 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4171$605_Y + connect \A $not$ls180.v:4200$669_Y connect \B \main_ack_rdata - connect \Y $and$ls180.v:4171$606_Y + connect \Y $and$ls180.v:4200$670_Y end - attribute \src "ls180.v:4171.32-4171.131" - cell $and $and$ls180.v:4171$608 + attribute \src "ls180.v:4200.32-4200.131" + cell $and $and$ls180.v:4200$672 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_ack_cmd - connect \B $or$ls180.v:4171$607_Y - connect \Y $and$ls180.v:4171$608_Y + connect \B $or$ls180.v:4200$671_Y + connect \Y $and$ls180.v:4200$672_Y end - attribute \src "ls180.v:4172.25-4172.66" - cell $and $and$ls180.v:4172$609 + attribute \src "ls180.v:4201.25-4201.66" + cell $and $and$ls180.v:4201$673 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239149,10 +240017,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_valid connect \B \main_port_cmd_ready - connect \Y $and$ls180.v:4172$609_Y + connect \Y $and$ls180.v:4201$673_Y end - attribute \src "ls180.v:4173.27-4173.72" - cell $and $and$ls180.v:4173$611 + attribute \src "ls180.v:4202.27-4202.72" + cell $and $and$ls180.v:4202$675 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239160,10 +240028,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_wdata_valid connect \B \main_port_wdata_ready - connect \Y $and$ls180.v:4173$611_Y + connect \Y $and$ls180.v:4202$675_Y end - attribute \src "ls180.v:4174.26-4174.71" - cell $and $and$ls180.v:4174$613 + attribute \src "ls180.v:4203.26-4203.71" + cell $and $and$ls180.v:4203$677 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239171,10 +240039,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_rdata_valid connect \B \main_port_rdata_ready - connect \Y $and$ls180.v:4174$613_Y + connect \Y $and$ls180.v:4203$677_Y end - attribute \src "ls180.v:4203.64-4203.88" - cell $and $and$ls180.v:4203$619 + attribute \src "ls180.v:4232.64-4232.88" + cell $and $and$ls180.v:4232$683 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239182,10 +240050,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A 1'0 connect \B \main_uart_rxtx_we - connect \Y $and$ls180.v:4203$619_Y + connect \Y $and$ls180.v:4232$683_Y end - attribute \src "ls180.v:4207.7-4207.78" - cell $and $and$ls180.v:4207$623 + attribute \src "ls180.v:4236.7-4236.78" + cell $and $and$ls180.v:4236$687 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239193,10 +240061,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_eventmanager_pending_re connect \B \main_uart_eventmanager_pending_r [0] - connect \Y $and$ls180.v:4207$623_Y + connect \Y $and$ls180.v:4236$687_Y end - attribute \src "ls180.v:4218.7-4218.78" - cell $and $and$ls180.v:4218$626 + attribute \src "ls180.v:4247.7-4247.78" + cell $and $and$ls180.v:4247$690 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239204,10 +240072,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_eventmanager_pending_re connect \B \main_uart_eventmanager_pending_r [1] - connect \Y $and$ls180.v:4218$626_Y + connect \Y $and$ls180.v:4247$690_Y end - attribute \src "ls180.v:4227.26-4227.97" - cell $and $and$ls180.v:4227$628 + attribute \src "ls180.v:4256.26-4256.97" + cell $and $and$ls180.v:4256$692 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239215,10 +240083,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_eventmanager_pending_w [0] connect \B \main_uart_eventmanager_storage [0] - connect \Y $and$ls180.v:4227$628_Y + connect \Y $and$ls180.v:4256$692_Y end - attribute \src "ls180.v:4227.102-4227.173" - cell $and $and$ls180.v:4227$629 + attribute \src "ls180.v:4256.102-4256.173" + cell $and $and$ls180.v:4256$693 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239226,32 +240094,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_eventmanager_pending_w [1] connect \B \main_uart_eventmanager_storage [1] - connect \Y $and$ls180.v:4227$629_Y + connect \Y $and$ls180.v:4256$693_Y end - attribute \src "ls180.v:4242.41-4242.133" - cell $and $and$ls180.v:4242$633 + attribute \src "ls180.v:4271.41-4271.133" + cell $and $and$ls180.v:4271$697 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_syncfifo_readable - connect \B $or$ls180.v:4242$632_Y - connect \Y $and$ls180.v:4242$633_Y + connect \B $or$ls180.v:4271$696_Y + connect \Y $and$ls180.v:4271$697_Y end - attribute \src "ls180.v:4253.39-4253.136" - cell $and $and$ls180.v:4253$638 + attribute \src "ls180.v:4282.39-4282.136" + cell $and $and$ls180.v:4282$702 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_syncfifo_we - connect \B $or$ls180.v:4253$637_Y - connect \Y $and$ls180.v:4253$638_Y + connect \B $or$ls180.v:4282$701_Y + connect \Y $and$ls180.v:4282$702_Y end - attribute \src "ls180.v:4254.37-4254.104" - cell $and $and$ls180.v:4254$639 + attribute \src "ls180.v:4283.37-4283.104" + cell $and $and$ls180.v:4283$703 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239259,32 +240127,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_syncfifo_readable connect \B \main_uart_tx_fifo_syncfifo_re - connect \Y $and$ls180.v:4254$639_Y + connect \Y $and$ls180.v:4283$703_Y end - attribute \src "ls180.v:4272.41-4272.133" - cell $and $and$ls180.v:4272$644 + attribute \src "ls180.v:4301.41-4301.133" + cell $and $and$ls180.v:4301$708 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_syncfifo_readable - connect \B $or$ls180.v:4272$643_Y - connect \Y $and$ls180.v:4272$644_Y + connect \B $or$ls180.v:4301$707_Y + connect \Y $and$ls180.v:4301$708_Y end - attribute \src "ls180.v:4283.39-4283.136" - cell $and $and$ls180.v:4283$649 + attribute \src "ls180.v:4312.39-4312.136" + cell $and $and$ls180.v:4312$713 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_syncfifo_we - connect \B $or$ls180.v:4283$648_Y - connect \Y $and$ls180.v:4283$649_Y + connect \B $or$ls180.v:4312$712_Y + connect \Y $and$ls180.v:4312$713_Y end - attribute \src "ls180.v:4284.37-4284.104" - cell $and $and$ls180.v:4284$650 + attribute \src "ls180.v:4313.37-4313.104" + cell $and $and$ls180.v:4313$714 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239292,21 +240160,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_syncfifo_readable connect \B \main_uart_rx_fifo_syncfifo_re - connect \Y $and$ls180.v:4284$650_Y + connect \Y $and$ls180.v:4313$714_Y end - attribute \src "ls180.v:4472.33-4472.86" - cell $and $and$ls180.v:4472$692 + attribute \src "ls180.v:4512.33-4512.86" + cell $and $and$ls180.v:4512$758 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_clocker_clk1 - connect \B $not$ls180.v:4472$691_Y - connect \Y $and$ls180.v:4472$692_Y + connect \B $not$ls180.v:4512$757_Y + connect \Y $and$ls180.v:4512$758_Y end - attribute \src "ls180.v:4576.9-4576.68" - cell $and $and$ls180.v:4576$701 + attribute \src "ls180.v:4616.9-4616.68" + cell $and $and$ls180.v:4616$767 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239314,21 +240182,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdw_sink_valid connect \B \main_sdphy_cmdw_pads_out_ready - connect \Y $and$ls180.v:4576$701_Y + connect \Y $and$ls180.v:4616$767_Y end - attribute \src "ls180.v:4596.53-4596.145" - cell $and $and$ls180.v:4596$704 + attribute \src "ls180.v:4636.53-4636.145" + cell $and $and$ls180.v:4636$770 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_pads_in_valid - connect \B $or$ls180.v:4596$703_Y - connect \Y $and$ls180.v:4596$704_Y + connect \B $or$ls180.v:4636$769_Y + connect \Y $and$ls180.v:4636$770_Y end - attribute \src "ls180.v:4615.52-4615.137" - cell $and $and$ls180.v:4615$707 + attribute \src "ls180.v:4655.52-4655.137" + cell $and $and$ls180.v:4655$773 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239336,10 +240204,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_converter_sink_valid connect \B \main_sdphy_cmdr_cmdr_converter_sink_ready - connect \Y $and$ls180.v:4615$707_Y + connect \Y $and$ls180.v:4655$773_Y end - attribute \src "ls180.v:4656.9-4656.68" - cell $and $and$ls180.v:4656$715 + attribute \src "ls180.v:4696.9-4696.68" + cell $and $and$ls180.v:4696$781 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239347,10 +240215,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_source_valid connect \B \main_sdphy_cmdr_source_ready - connect \Y $and$ls180.v:4656$715_Y + connect \Y $and$ls180.v:4696$781_Y end - attribute \src "ls180.v:4694.9-4694.68" - cell $and $and$ls180.v:4694$721 + attribute \src "ls180.v:4734.9-4734.68" + cell $and $and$ls180.v:4734$787 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239358,10 +240226,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_source_valid connect \B \main_sdphy_cmdr_source_ready - connect \Y $and$ls180.v:4694$721_Y + connect \Y $and$ls180.v:4734$787_Y end - attribute \src "ls180.v:4703.10-4703.69" - cell $and $and$ls180.v:4703$722 + attribute \src "ls180.v:4743.10-4743.69" + cell $and $and$ls180.v:4743$788 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239369,21 +240237,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_sink_valid connect \B \main_sdphy_cmdr_pads_out_ready - connect \Y $and$ls180.v:4703$722_Y + connect \Y $and$ls180.v:4743$788_Y end - attribute \src "ls180.v:4703.9-4703.93" - cell $and $and$ls180.v:4703$723 + attribute \src "ls180.v:4743.9-4743.93" + cell $and $and$ls180.v:4743$789 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4703$722_Y + connect \A $and$ls180.v:4743$788_Y connect \B \main_sdphy_cmdw_done - connect \Y $and$ls180.v:4703$723_Y + connect \Y $and$ls180.v:4743$789_Y end - attribute \src "ls180.v:4723.54-4723.117" - cell $and $and$ls180.v:4723$725 + attribute \src "ls180.v:4763.54-4763.117" + cell $and $and$ls180.v:4763$791 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239391,10 +240259,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_pads_in_valid connect \B \main_sdphy_dataw_crcr_run - connect \Y $and$ls180.v:4723$725_Y + connect \Y $and$ls180.v:4763$791_Y end - attribute \src "ls180.v:4742.53-4742.140" - cell $and $and$ls180.v:4742$728 + attribute \src "ls180.v:4782.53-4782.140" + cell $and $and$ls180.v:4782$794 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239402,10 +240270,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_converter_sink_valid connect \B \main_sdphy_dataw_crcr_converter_sink_ready - connect \Y $and$ls180.v:4742$728_Y + connect \Y $and$ls180.v:4782$794_Y end - attribute \src "ls180.v:4839.9-4839.70" - cell $and $and$ls180.v:4839$738 + attribute \src "ls180.v:4879.9-4879.70" + cell $and $and$ls180.v:4879$804 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239413,10 +240281,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_sink_valid connect \B \main_sdphy_dataw_pads_out_ready - connect \Y $and$ls180.v:4839$738_Y + connect \Y $and$ls180.v:4879$804_Y end - attribute \src "ls180.v:4857.55-4857.120" - cell $and $and$ls180.v:4857$740 + attribute \src "ls180.v:4897.55-4897.120" + cell $and $and$ls180.v:4897$806 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239424,10 +240292,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_pads_in_valid connect \B \main_sdphy_datar_datar_run - connect \Y $and$ls180.v:4857$740_Y + connect \Y $and$ls180.v:4897$806_Y end - attribute \src "ls180.v:4876.54-4876.143" - cell $and $and$ls180.v:4876$743 + attribute \src "ls180.v:4916.54-4916.143" + cell $and $and$ls180.v:4916$809 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239435,10 +240303,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_converter_sink_valid connect \B \main_sdphy_datar_datar_converter_sink_ready - connect \Y $and$ls180.v:4876$743_Y + connect \Y $and$ls180.v:4916$809_Y end - attribute \src "ls180.v:4958.9-4958.70" - cell $and $and$ls180.v:4958$758 + attribute \src "ls180.v:4998.9-4998.70" + cell $and $and$ls180.v:4998$824 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239446,10 +240314,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_source_valid connect \B \main_sdphy_datar_source_ready - connect \Y $and$ls180.v:4958$758_Y + connect \Y $and$ls180.v:4998$824_Y end - attribute \src "ls180.v:4965.9-4965.70" - cell $and $and$ls180.v:4965$759 + attribute \src "ls180.v:5005.9-5005.70" + cell $and $and$ls180.v:5005$825 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239457,10 +240325,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_sink_valid connect \B \main_sdphy_datar_pads_out_ready - connect \Y $and$ls180.v:4965$759_Y + connect \Y $and$ls180.v:5005$825_Y end - attribute \src "ls180.v:5046.48-5046.124" - cell $and $and$ls180.v:5046$882 + attribute \src "ls180.v:5086.48-5086.124" + cell $and $and$ls180.v:5086$948 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239468,21 +240336,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_sink_last connect \B \main_sdcore_crc16_inserter_sink_valid - connect \Y $and$ls180.v:5046$882_Y + connect \Y $and$ls180.v:5086$948_Y end - attribute \src "ls180.v:5046.47-5046.165" - cell $and $and$ls180.v:5046$883 + attribute \src "ls180.v:5086.47-5086.165" + cell $and $and$ls180.v:5086$949 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5046$882_Y + connect \A $and$ls180.v:5086$948_Y connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:5046$883_Y + connect \Y $and$ls180.v:5086$949_Y end - attribute \src "ls180.v:5047.50-5047.127" - cell $and $and$ls180.v:5047$884 + attribute \src "ls180.v:5087.50-5087.127" + cell $and $and$ls180.v:5087$950 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239490,10 +240358,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_sink_valid connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:5047$884_Y + connect \Y $and$ls180.v:5087$950_Y end - attribute \src "ls180.v:5049.48-5049.124" - cell $and $and$ls180.v:5049$885 + attribute \src "ls180.v:5089.48-5089.124" + cell $and $and$ls180.v:5089$951 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239501,21 +240369,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_sink_last connect \B \main_sdcore_crc16_inserter_sink_valid - connect \Y $and$ls180.v:5049$885_Y + connect \Y $and$ls180.v:5089$951_Y end - attribute \src "ls180.v:5049.47-5049.165" - cell $and $and$ls180.v:5049$886 + attribute \src "ls180.v:5089.47-5089.165" + cell $and $and$ls180.v:5089$952 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5049$885_Y + connect \A $and$ls180.v:5089$951_Y connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:5049$886_Y + connect \Y $and$ls180.v:5089$952_Y end - attribute \src "ls180.v:5050.50-5050.127" - cell $and $and$ls180.v:5050$887 + attribute \src "ls180.v:5090.50-5090.127" + cell $and $and$ls180.v:5090$953 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239523,10 +240391,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_sink_valid connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:5050$887_Y + connect \Y $and$ls180.v:5090$953_Y end - attribute \src "ls180.v:5052.48-5052.124" - cell $and $and$ls180.v:5052$888 + attribute \src "ls180.v:5092.48-5092.124" + cell $and $and$ls180.v:5092$954 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239534,21 +240402,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_sink_last connect \B \main_sdcore_crc16_inserter_sink_valid - connect \Y $and$ls180.v:5052$888_Y + connect \Y $and$ls180.v:5092$954_Y end - attribute \src "ls180.v:5052.47-5052.165" - cell $and $and$ls180.v:5052$889 + attribute \src "ls180.v:5092.47-5092.165" + cell $and $and$ls180.v:5092$955 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5052$888_Y + connect \A $and$ls180.v:5092$954_Y connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:5052$889_Y + connect \Y $and$ls180.v:5092$955_Y end - attribute \src "ls180.v:5053.50-5053.127" - cell $and $and$ls180.v:5053$890 + attribute \src "ls180.v:5093.50-5093.127" + cell $and $and$ls180.v:5093$956 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239556,10 +240424,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_sink_valid connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:5053$890_Y + connect \Y $and$ls180.v:5093$956_Y end - attribute \src "ls180.v:5055.48-5055.124" - cell $and $and$ls180.v:5055$891 + attribute \src "ls180.v:5095.48-5095.124" + cell $and $and$ls180.v:5095$957 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239567,21 +240435,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_sink_last connect \B \main_sdcore_crc16_inserter_sink_valid - connect \Y $and$ls180.v:5055$891_Y + connect \Y $and$ls180.v:5095$957_Y end - attribute \src "ls180.v:5055.47-5055.165" - cell $and $and$ls180.v:5055$892 + attribute \src "ls180.v:5095.47-5095.165" + cell $and $and$ls180.v:5095$958 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5055$891_Y + connect \A $and$ls180.v:5095$957_Y connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:5055$892_Y + connect \Y $and$ls180.v:5095$958_Y end - attribute \src "ls180.v:5056.50-5056.127" - cell $and $and$ls180.v:5056$893 + attribute \src "ls180.v:5096.50-5096.127" + cell $and $and$ls180.v:5096$959 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239589,10 +240457,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_sink_valid connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:5056$893_Y + connect \Y $and$ls180.v:5096$959_Y end - attribute \src "ls180.v:5169.10-5169.86" - cell $and $and$ls180.v:5169$942 + attribute \src "ls180.v:5209.10-5209.86" + cell $and $and$ls180.v:5209$1008 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239600,54 +240468,54 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_sink_valid connect \B \main_sdcore_crc16_inserter_sink_last - connect \Y $and$ls180.v:5169$942_Y + connect \Y $and$ls180.v:5209$1008_Y end - attribute \src "ls180.v:5169.9-5169.127" - cell $and $and$ls180.v:5169$943 + attribute \src "ls180.v:5209.9-5209.127" + cell $and $and$ls180.v:5209$1009 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5169$942_Y + connect \A $and$ls180.v:5209$1008_Y connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:5169$943_Y + connect \Y $and$ls180.v:5209$1009_Y end - attribute \src "ls180.v:5179.9-5179.152" - cell $and $and$ls180.v:5179$947 + attribute \src "ls180.v:5219.9-5219.152" + cell $and $and$ls180.v:5219$1013 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:5179$945_Y - connect \B $eq$ls180.v:5179$946_Y - connect \Y $and$ls180.v:5179$947_Y + connect \A $eq$ls180.v:5219$1011_Y + connect \B $eq$ls180.v:5219$1012_Y + connect \Y $and$ls180.v:5219$1013_Y end - attribute \src "ls180.v:5179.8-5179.226" - cell $and $and$ls180.v:5179$949 + attribute \src "ls180.v:5219.8-5219.226" + cell $and $and$ls180.v:5219$1015 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5179$947_Y - connect \B $eq$ls180.v:5179$948_Y - connect \Y $and$ls180.v:5179$949_Y + connect \A $and$ls180.v:5219$1013_Y + connect \B $eq$ls180.v:5219$1014_Y + connect \Y $and$ls180.v:5219$1015_Y end - attribute \src "ls180.v:5179.7-5179.300" - cell $and $and$ls180.v:5179$951 + attribute \src "ls180.v:5219.7-5219.300" + cell $and $and$ls180.v:5219$1017 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5179$949_Y - connect \B $eq$ls180.v:5179$950_Y - connect \Y $and$ls180.v:5179$951_Y + connect \A $and$ls180.v:5219$1015_Y + connect \B $eq$ls180.v:5219$1016_Y + connect \Y $and$ls180.v:5219$1017_Y end - attribute \src "ls180.v:5184.49-5184.124" - cell $and $and$ls180.v:5184$952 + attribute \src "ls180.v:5224.49-5224.124" + cell $and $and$ls180.v:5224$1018 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239655,10 +240523,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_valid connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:5184$952_Y + connect \Y $and$ls180.v:5224$1018_Y end - attribute \src "ls180.v:5194.49-5194.124" - cell $and $and$ls180.v:5194$955 + attribute \src "ls180.v:5234.49-5234.124" + cell $and $and$ls180.v:5234$1021 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239666,10 +240534,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_valid connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:5194$955_Y + connect \Y $and$ls180.v:5234$1021_Y end - attribute \src "ls180.v:5204.49-5204.124" - cell $and $and$ls180.v:5204$958 + attribute \src "ls180.v:5244.49-5244.124" + cell $and $and$ls180.v:5244$1024 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239677,10 +240545,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_valid connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:5204$958_Y + connect \Y $and$ls180.v:5244$1024_Y end - attribute \src "ls180.v:5214.49-5214.124" - cell $and $and$ls180.v:5214$961 + attribute \src "ls180.v:5254.49-5254.124" + cell $and $and$ls180.v:5254$1027 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239688,21 +240556,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_valid connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:5214$961_Y + connect \Y $and$ls180.v:5254$1027_Y end - attribute \src "ls180.v:5226.7-5226.84" - cell $and $and$ls180.v:5226$966 + attribute \src "ls180.v:5266.7-5266.84" + cell $and $and$ls180.v:5266$1032 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_valid - connect \B $gt$ls180.v:5226$965_Y - connect \Y $and$ls180.v:5226$966_Y + connect \B $gt$ls180.v:5266$1031_Y + connect \Y $and$ls180.v:5266$1032_Y end - attribute \src "ls180.v:5344.9-5344.64" - cell $and $and$ls180.v:5344$1015 + attribute \src "ls180.v:5384.9-5384.64" + cell $and $and$ls180.v:5384$1081 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239710,10 +240578,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdw_sink_valid connect \B \main_sdphy_cmdw_sink_ready - connect \Y $and$ls180.v:5344$1015_Y + connect \Y $and$ls180.v:5384$1081_Y end - attribute \src "ls180.v:5396.10-5396.66" - cell $and $and$ls180.v:5396$1024 + attribute \src "ls180.v:5436.10-5436.66" + cell $and $and$ls180.v:5436$1090 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239721,21 +240589,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_sink_valid connect \B \main_sdphy_dataw_sink_last - connect \Y $and$ls180.v:5396$1024_Y + connect \Y $and$ls180.v:5436$1090_Y end - attribute \src "ls180.v:5396.9-5396.97" - cell $and $and$ls180.v:5396$1025 + attribute \src "ls180.v:5436.9-5436.97" + cell $and $and$ls180.v:5436$1091 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5396$1024_Y + connect \A $and$ls180.v:5436$1090_Y connect \B \main_sdphy_dataw_sink_ready - connect \Y $and$ls180.v:5396$1025_Y + connect \Y $and$ls180.v:5436$1091_Y end - attribute \src "ls180.v:5422.11-5422.71" - cell $and $and$ls180.v:5422$1033 + attribute \src "ls180.v:5462.11-5462.71" + cell $and $and$ls180.v:5462$1099 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239743,21 +240611,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_source_last connect \B \main_sdphy_datar_source_ready - connect \Y $and$ls180.v:5422$1033_Y + connect \Y $and$ls180.v:5462$1099_Y end - attribute \src "ls180.v:5506.43-5506.152" - cell $and $and$ls180.v:5506$1041 + attribute \src "ls180.v:5546.43-5546.152" + cell $and $and$ls180.v:5546$1107 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_fifo_syncfifo_we - connect \B $or$ls180.v:5506$1040_Y - connect \Y $and$ls180.v:5506$1041_Y + connect \B $or$ls180.v:5546$1106_Y + connect \Y $and$ls180.v:5546$1107_Y end - attribute \src "ls180.v:5507.41-5507.116" - cell $and $and$ls180.v:5507$1042 + attribute \src "ls180.v:5547.41-5547.116" + cell $and $and$ls180.v:5547$1108 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239765,10 +240633,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_fifo_syncfifo_readable connect \B \main_sdblock2mem_fifo_syncfifo_re - connect \Y $and$ls180.v:5507$1042_Y + connect \Y $and$ls180.v:5547$1108_Y end - attribute \src "ls180.v:5519.48-5519.125" - cell $and $and$ls180.v:5519$1047 + attribute \src "ls180.v:5559.48-5559.125" + cell $and $and$ls180.v:5559$1113 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239776,10 +240644,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_converter_sink_valid connect \B \main_sdblock2mem_converter_sink_ready - connect \Y $and$ls180.v:5519$1047_Y + connect \Y $and$ls180.v:5559$1113_Y end - attribute \src "ls180.v:5546.9-5546.102" - cell $and $and$ls180.v:5546$1051 + attribute \src "ls180.v:5586.9-5586.102" + cell $and $and$ls180.v:5586$1117 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239787,10 +240655,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_wishbonedmawriter_sink_valid connect \B \main_sdblock2mem_wishbonedmawriter_sink_ready - connect \Y $and$ls180.v:5546$1051_Y + connect \Y $and$ls180.v:5586$1117_Y end - attribute \src "ls180.v:5619.9-5619.58" - cell $and $and$ls180.v:5619$1057 + attribute \src "ls180.v:5659.9-5659.58" + cell $and $and$ls180.v:5659$1123 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239798,10 +240666,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_interface1_bus_stb connect \B \main_interface1_bus_ack - connect \Y $and$ls180.v:5619$1057_Y + connect \Y $and$ls180.v:5659$1123_Y end - attribute \src "ls180.v:5672.51-5672.123" - cell $and $and$ls180.v:5672$1065 + attribute \src "ls180.v:5712.51-5712.123" + cell $and $and$ls180.v:5712$1131 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239809,10 +240677,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_converter_sink_first connect \B \main_sdmem2block_converter_first - connect \Y $and$ls180.v:5672$1065_Y + connect \Y $and$ls180.v:5712$1131_Y end - attribute \src "ls180.v:5673.50-5673.120" - cell $and $and$ls180.v:5673$1066 + attribute \src "ls180.v:5713.50-5713.120" + cell $and $and$ls180.v:5713$1132 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239820,10 +240688,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_converter_sink_last connect \B \main_sdmem2block_converter_last - connect \Y $and$ls180.v:5673$1066_Y + connect \Y $and$ls180.v:5713$1132_Y end - attribute \src "ls180.v:5674.49-5674.122" - cell $and $and$ls180.v:5674$1067 + attribute \src "ls180.v:5714.49-5714.122" + cell $and $and$ls180.v:5714$1133 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239831,21 +240699,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_converter_last connect \B \main_sdmem2block_converter_source_ready - connect \Y $and$ls180.v:5674$1067_Y + connect \Y $and$ls180.v:5714$1133_Y end - attribute \src "ls180.v:5714.43-5714.152" - cell $and $and$ls180.v:5714$1072 + attribute \src "ls180.v:5766.43-5766.152" + cell $and $and$ls180.v:5766$1138 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_fifo_syncfifo_we - connect \B $or$ls180.v:5714$1071_Y - connect \Y $and$ls180.v:5714$1072_Y + connect \B $or$ls180.v:5766$1137_Y + connect \Y $and$ls180.v:5766$1138_Y end - attribute \src "ls180.v:5715.41-5715.116" - cell $and $and$ls180.v:5715$1073 + attribute \src "ls180.v:5767.41-5767.116" + cell $and $and$ls180.v:5767$1139 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239853,10 +240721,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_fifo_syncfifo_readable connect \B \main_sdmem2block_fifo_syncfifo_re - connect \Y $and$ls180.v:5715$1073_Y + connect \Y $and$ls180.v:5767$1139_Y end - attribute \src "ls180.v:5747.9-5747.76" - cell $and $and$ls180.v:5747$1077 + attribute \src "ls180.v:5799.9-5799.76" + cell $and $and$ls180.v:5799$1143 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239864,131 +240732,131 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_libresocsim_wishbone_cyc connect \B \builder_libresocsim_wishbone_stb - connect \Y $and$ls180.v:5747$1077_Y + connect \Y $and$ls180.v:5799$1143_Y end - attribute \src "ls180.v:5750.44-5750.120" - cell $and $and$ls180.v:5750$1079 + attribute \src "ls180.v:5802.44-5802.120" + cell $and $and$ls180.v:5802$1145 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_libresocsim_wishbone_we - connect \B $ne$ls180.v:5750$1078_Y - connect \Y $and$ls180.v:5750$1079_Y + connect \B $ne$ls180.v:5802$1144_Y + connect \Y $and$ls180.v:5802$1145_Y end - attribute \src "ls180.v:5770.63-5770.107" - cell $and $and$ls180.v:5770$1081 + attribute \src "ls180.v:5822.46-5822.90" + cell $and $and$ls180.v:5822$1147 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_shared_ack - connect \B $eq$ls180.v:5770$1080_Y - connect \Y $and$ls180.v:5770$1081_Y + connect \B $eq$ls180.v:5822$1146_Y + connect \Y $and$ls180.v:5822$1147_Y end - attribute \src "ls180.v:5771.63-5771.107" - cell $and $and$ls180.v:5771$1083 + attribute \src "ls180.v:5823.46-5823.90" + cell $and $and$ls180.v:5823$1149 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_shared_ack - connect \B $eq$ls180.v:5771$1082_Y - connect \Y $and$ls180.v:5771$1083_Y + connect \B $eq$ls180.v:5823$1148_Y + connect \Y $and$ls180.v:5823$1149_Y end - attribute \src "ls180.v:5772.63-5772.107" - cell $and $and$ls180.v:5772$1085 + attribute \src "ls180.v:5824.49-5824.93" + cell $and $and$ls180.v:5824$1151 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_shared_ack - connect \B $eq$ls180.v:5772$1084_Y - connect \Y $and$ls180.v:5772$1085_Y + connect \B $eq$ls180.v:5824$1150_Y + connect \Y $and$ls180.v:5824$1151_Y end - attribute \src "ls180.v:5773.35-5773.79" - cell $and $and$ls180.v:5773$1087 + attribute \src "ls180.v:5825.35-5825.79" + cell $and $and$ls180.v:5825$1153 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_shared_ack - connect \B $eq$ls180.v:5773$1086_Y - connect \Y $and$ls180.v:5773$1087_Y + connect \B $eq$ls180.v:5825$1152_Y + connect \Y $and$ls180.v:5825$1153_Y end - attribute \src "ls180.v:5774.35-5774.79" - cell $and $and$ls180.v:5774$1089 + attribute \src "ls180.v:5826.35-5826.79" + cell $and $and$ls180.v:5826$1155 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_shared_ack - connect \B $eq$ls180.v:5774$1088_Y - connect \Y $and$ls180.v:5774$1089_Y + connect \B $eq$ls180.v:5826$1154_Y + connect \Y $and$ls180.v:5826$1155_Y end - attribute \src "ls180.v:5775.63-5775.107" - cell $and $and$ls180.v:5775$1091 + attribute \src "ls180.v:5827.46-5827.90" + cell $and $and$ls180.v:5827$1157 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_shared_err - connect \B $eq$ls180.v:5775$1090_Y - connect \Y $and$ls180.v:5775$1091_Y + connect \B $eq$ls180.v:5827$1156_Y + connect \Y $and$ls180.v:5827$1157_Y end - attribute \src "ls180.v:5776.63-5776.107" - cell $and $and$ls180.v:5776$1093 + attribute \src "ls180.v:5828.46-5828.90" + cell $and $and$ls180.v:5828$1159 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_shared_err - connect \B $eq$ls180.v:5776$1092_Y - connect \Y $and$ls180.v:5776$1093_Y + connect \B $eq$ls180.v:5828$1158_Y + connect \Y $and$ls180.v:5828$1159_Y end - attribute \src "ls180.v:5777.63-5777.107" - cell $and $and$ls180.v:5777$1095 + attribute \src "ls180.v:5829.49-5829.93" + cell $and $and$ls180.v:5829$1161 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_shared_err - connect \B $eq$ls180.v:5777$1094_Y - connect \Y $and$ls180.v:5777$1095_Y + connect \B $eq$ls180.v:5829$1160_Y + connect \Y $and$ls180.v:5829$1161_Y end - attribute \src "ls180.v:5778.35-5778.79" - cell $and $and$ls180.v:5778$1097 + attribute \src "ls180.v:5830.35-5830.79" + cell $and $and$ls180.v:5830$1163 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_shared_err - connect \B $eq$ls180.v:5778$1096_Y - connect \Y $and$ls180.v:5778$1097_Y + connect \B $eq$ls180.v:5830$1162_Y + connect \Y $and$ls180.v:5830$1163_Y end - attribute \src "ls180.v:5779.35-5779.79" - cell $and $and$ls180.v:5779$1099 + attribute \src "ls180.v:5831.35-5831.79" + cell $and $and$ls180.v:5831$1165 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_shared_err - connect \B $eq$ls180.v:5779$1098_Y - connect \Y $and$ls180.v:5779$1099_Y + connect \B $eq$ls180.v:5831$1164_Y + connect \Y $and$ls180.v:5831$1165_Y end - attribute \src "ls180.v:5848.40-5848.81" - cell $and $and$ls180.v:5848$1109 + attribute \src "ls180.v:5900.40-5900.81" + cell $and $and$ls180.v:5900$1175 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239996,10 +240864,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_shared_cyc connect \B \builder_slave_sel [0] - connect \Y $and$ls180.v:5848$1109_Y + connect \Y $and$ls180.v:5900$1175_Y end - attribute \src "ls180.v:5849.39-5849.80" - cell $and $and$ls180.v:5849$1110 + attribute \src "ls180.v:5901.39-5901.80" + cell $and $and$ls180.v:5901$1176 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240007,10 +240875,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_shared_cyc connect \B \builder_slave_sel [1] - connect \Y $and$ls180.v:5849$1110_Y + connect \Y $and$ls180.v:5901$1176_Y end - attribute \src "ls180.v:5850.39-5850.80" - cell $and $and$ls180.v:5850$1111 + attribute \src "ls180.v:5902.39-5902.80" + cell $and $and$ls180.v:5902$1177 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240018,10 +240886,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_shared_cyc connect \B \builder_slave_sel [2] - connect \Y $and$ls180.v:5850$1111_Y + connect \Y $and$ls180.v:5902$1177_Y end - attribute \src "ls180.v:5851.39-5851.80" - cell $and $and$ls180.v:5851$1112 + attribute \src "ls180.v:5903.39-5903.80" + cell $and $and$ls180.v:5903$1178 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240029,10 +240897,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_shared_cyc connect \B \builder_slave_sel [3] - connect \Y $and$ls180.v:5851$1112_Y + connect \Y $and$ls180.v:5903$1178_Y end - attribute \src "ls180.v:5852.50-5852.91" - cell $and $and$ls180.v:5852$1113 + attribute \src "ls180.v:5904.51-5904.92" + cell $and $and$ls180.v:5904$1179 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240040,10 +240908,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_shared_cyc connect \B \builder_slave_sel [4] - connect \Y $and$ls180.v:5852$1113_Y + connect \Y $and$ls180.v:5904$1179_Y end - attribute \src "ls180.v:5853.50-5853.91" - cell $and $and$ls180.v:5853$1114 + attribute \src "ls180.v:5905.51-5905.92" + cell $and $and$ls180.v:5905$1180 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240051,10 +240919,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_shared_cyc connect \B \builder_slave_sel [5] - connect \Y $and$ls180.v:5853$1114_Y + connect \Y $and$ls180.v:5905$1180_Y end - attribute \src "ls180.v:5854.29-5854.70" - cell $and $and$ls180.v:5854$1115 + attribute \src "ls180.v:5906.54-5906.95" + cell $and $and$ls180.v:5906$1181 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240062,10 +240930,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_shared_cyc connect \B \builder_slave_sel [6] - connect \Y $and$ls180.v:5854$1115_Y + connect \Y $and$ls180.v:5906$1181_Y end - attribute \src "ls180.v:5855.44-5855.85" - cell $and $and$ls180.v:5855$1116 + attribute \src "ls180.v:5907.55-5907.96" + cell $and $and$ls180.v:5907$1182 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240073,10 +240941,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_shared_cyc connect \B \builder_slave_sel [7] - connect \Y $and$ls180.v:5855$1116_Y + connect \Y $and$ls180.v:5907$1182_Y end - attribute \src "ls180.v:5857.25-5857.64" - cell $and $and$ls180.v:5857$1124 + attribute \src "ls180.v:5909.25-5909.64" + cell $and $and$ls180.v:5909$1190 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240084,109 +240952,109 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_shared_stb connect \B \builder_shared_cyc - connect \Y $and$ls180.v:5857$1124_Y + connect \Y $and$ls180.v:5909$1190_Y end - attribute \src "ls180.v:5857.24-5857.89" - cell $and $and$ls180.v:5857$1126 + attribute \src "ls180.v:5909.24-5909.89" + cell $and $and$ls180.v:5909$1192 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5857$1124_Y - connect \B $not$ls180.v:5857$1125_Y - connect \Y $and$ls180.v:5857$1126_Y + connect \A $and$ls180.v:5909$1190_Y + connect \B $not$ls180.v:5909$1191_Y + connect \Y $and$ls180.v:5909$1192_Y end - attribute \src "ls180.v:5863.34-5863.95" - cell $and $and$ls180.v:5863$1135 + attribute \src "ls180.v:5915.34-5915.95" + cell $and $and$ls180.v:5915$1201 parameter \A_SIGNED 0 - parameter \A_WIDTH 32 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A { \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] } + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] } connect \B \main_libresocsim_ram_bus_dat_r - connect \Y $and$ls180.v:5863$1135_Y + connect \Y $and$ls180.v:5915$1201_Y end - attribute \src "ls180.v:5863.100-5863.160" - cell $and $and$ls180.v:5863$1136 + attribute \src "ls180.v:5915.100-5915.160" + cell $and $and$ls180.v:5915$1202 parameter \A_SIGNED 0 - parameter \A_WIDTH 32 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A { \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] } + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] } connect \B \main_interface0_ram_bus_dat_r - connect \Y $and$ls180.v:5863$1136_Y + connect \Y $and$ls180.v:5915$1202_Y end - attribute \src "ls180.v:5863.166-5863.226" - cell $and $and$ls180.v:5863$1138 + attribute \src "ls180.v:5915.166-5915.226" + cell $and $and$ls180.v:5915$1204 parameter \A_SIGNED 0 - parameter \A_WIDTH 32 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A { \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] } + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] } connect \B \main_interface1_ram_bus_dat_r - connect \Y $and$ls180.v:5863$1138_Y + connect \Y $and$ls180.v:5915$1204_Y end - attribute \src "ls180.v:5863.232-5863.292" - cell $and $and$ls180.v:5863$1140 + attribute \src "ls180.v:5915.232-5915.292" + cell $and $and$ls180.v:5915$1206 parameter \A_SIGNED 0 - parameter \A_WIDTH 32 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A { \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] } + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] } connect \B \main_interface2_ram_bus_dat_r - connect \Y $and$ls180.v:5863$1140_Y + connect \Y $and$ls180.v:5915$1206_Y end - attribute \src "ls180.v:5863.298-5863.369" - cell $and $and$ls180.v:5863$1142 + attribute \src "ls180.v:5915.298-5915.370" + cell $and $and$ls180.v:5915$1208 parameter \A_SIGNED 0 - parameter \A_WIDTH 32 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A { \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] } - connect \B \main_libresocsim_libresoc_xics_icp_dat_r - connect \Y $and$ls180.v:5863$1142_Y + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] } + connect \B \main_interface0_converted_interface_dat_r + connect \Y $and$ls180.v:5915$1208_Y end - attribute \src "ls180.v:5863.375-5863.446" - cell $and $and$ls180.v:5863$1144 + attribute \src "ls180.v:5915.376-5915.448" + cell $and $and$ls180.v:5915$1210 parameter \A_SIGNED 0 - parameter \A_WIDTH 32 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A { \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] } - connect \B \main_libresocsim_libresoc_xics_ics_dat_r - connect \Y $and$ls180.v:5863$1144_Y + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] } + connect \B \main_interface1_converted_interface_dat_r + connect \Y $and$ls180.v:5915$1210_Y end - attribute \src "ls180.v:5863.452-5863.502" - cell $and $and$ls180.v:5863$1146 + attribute \src "ls180.v:5915.454-5915.529" + cell $and $and$ls180.v:5915$1212 parameter \A_SIGNED 0 - parameter \A_WIDTH 32 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A { \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] } - connect \B \main_wb_sdram_dat_r - connect \Y $and$ls180.v:5863$1146_Y + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] } + connect \B \main_socbushandler_converted_interface_dat_r + connect \Y $and$ls180.v:5915$1212_Y end - attribute \src "ls180.v:5863.508-5863.573" - cell $and $and$ls180.v:5863$1148 + attribute \src "ls180.v:5915.535-5915.611" + cell $and $and$ls180.v:5915$1214 parameter \A_SIGNED 0 - parameter \A_WIDTH 32 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A { \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] } - connect \B \builder_libresocsim_wishbone_dat_r - connect \Y $and$ls180.v:5863$1148_Y + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] } + connect \B \builder_libresocsim_converted_interface_dat_r + connect \Y $and$ls180.v:5915$1214_Y end - attribute \src "ls180.v:5873.39-5873.92" - cell $and $and$ls180.v:5873$1152 + attribute \src "ls180.v:5925.39-5925.92" + cell $and $and$ls180.v:5925$1218 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240194,43 +241062,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:5873$1152_Y + connect \Y $and$ls180.v:5925$1218_Y end - attribute \src "ls180.v:5873.38-5873.142" - cell $and $and$ls180.v:5873$1154 + attribute \src "ls180.v:5925.38-5925.142" + cell $and $and$ls180.v:5925$1220 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5873$1152_Y - connect \B $eq$ls180.v:5873$1153_Y - connect \Y $and$ls180.v:5873$1154_Y + connect \A $and$ls180.v:5925$1218_Y + connect \B $eq$ls180.v:5925$1219_Y + connect \Y $and$ls180.v:5925$1220_Y end - attribute \src "ls180.v:5874.39-5874.95" - cell $and $and$ls180.v:5874$1156 + attribute \src "ls180.v:5926.39-5926.95" + cell $and $and$ls180.v:5926$1222 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:5874$1155_Y - connect \Y $and$ls180.v:5874$1156_Y + connect \B $not$ls180.v:5926$1221_Y + connect \Y $and$ls180.v:5926$1222_Y end - attribute \src "ls180.v:5874.38-5874.145" - cell $and $and$ls180.v:5874$1158 + attribute \src "ls180.v:5926.38-5926.145" + cell $and $and$ls180.v:5926$1224 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5874$1156_Y - connect \B $eq$ls180.v:5874$1157_Y - connect \Y $and$ls180.v:5874$1158_Y + connect \A $and$ls180.v:5926$1222_Y + connect \B $eq$ls180.v:5926$1223_Y + connect \Y $and$ls180.v:5926$1224_Y end - attribute \src "ls180.v:5876.41-5876.94" - cell $and $and$ls180.v:5876$1159 + attribute \src "ls180.v:5928.41-5928.94" + cell $and $and$ls180.v:5928$1225 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240238,43 +241106,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:5876$1159_Y + connect \Y $and$ls180.v:5928$1225_Y end - attribute \src "ls180.v:5876.40-5876.144" - cell $and $and$ls180.v:5876$1161 + attribute \src "ls180.v:5928.40-5928.144" + cell $and $and$ls180.v:5928$1227 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5876$1159_Y - connect \B $eq$ls180.v:5876$1160_Y - connect \Y $and$ls180.v:5876$1161_Y + connect \A $and$ls180.v:5928$1225_Y + connect \B $eq$ls180.v:5928$1226_Y + connect \Y $and$ls180.v:5928$1227_Y end - attribute \src "ls180.v:5877.41-5877.97" - cell $and $and$ls180.v:5877$1163 + attribute \src "ls180.v:5929.41-5929.97" + cell $and $and$ls180.v:5929$1229 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:5877$1162_Y - connect \Y $and$ls180.v:5877$1163_Y + connect \B $not$ls180.v:5929$1228_Y + connect \Y $and$ls180.v:5929$1229_Y end - attribute \src "ls180.v:5877.40-5877.147" - cell $and $and$ls180.v:5877$1165 + attribute \src "ls180.v:5929.40-5929.147" + cell $and $and$ls180.v:5929$1231 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5877$1163_Y - connect \B $eq$ls180.v:5877$1164_Y - connect \Y $and$ls180.v:5877$1165_Y + connect \A $and$ls180.v:5929$1229_Y + connect \B $eq$ls180.v:5929$1230_Y + connect \Y $and$ls180.v:5929$1231_Y end - attribute \src "ls180.v:5879.41-5879.94" - cell $and $and$ls180.v:5879$1166 + attribute \src "ls180.v:5931.41-5931.94" + cell $and $and$ls180.v:5931$1232 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240282,43 +241150,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:5879$1166_Y + connect \Y $and$ls180.v:5931$1232_Y end - attribute \src "ls180.v:5879.40-5879.144" - cell $and $and$ls180.v:5879$1168 + attribute \src "ls180.v:5931.40-5931.144" + cell $and $and$ls180.v:5931$1234 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5879$1166_Y - connect \B $eq$ls180.v:5879$1167_Y - connect \Y $and$ls180.v:5879$1168_Y + connect \A $and$ls180.v:5931$1232_Y + connect \B $eq$ls180.v:5931$1233_Y + connect \Y $and$ls180.v:5931$1234_Y end - attribute \src "ls180.v:5880.41-5880.97" - cell $and $and$ls180.v:5880$1170 + attribute \src "ls180.v:5932.41-5932.97" + cell $and $and$ls180.v:5932$1236 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:5880$1169_Y - connect \Y $and$ls180.v:5880$1170_Y + connect \B $not$ls180.v:5932$1235_Y + connect \Y $and$ls180.v:5932$1236_Y end - attribute \src "ls180.v:5880.40-5880.147" - cell $and $and$ls180.v:5880$1172 + attribute \src "ls180.v:5932.40-5932.147" + cell $and $and$ls180.v:5932$1238 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5880$1170_Y - connect \B $eq$ls180.v:5880$1171_Y - connect \Y $and$ls180.v:5880$1172_Y + connect \A $and$ls180.v:5932$1236_Y + connect \B $eq$ls180.v:5932$1237_Y + connect \Y $and$ls180.v:5932$1238_Y end - attribute \src "ls180.v:5882.41-5882.94" - cell $and $and$ls180.v:5882$1173 + attribute \src "ls180.v:5934.41-5934.94" + cell $and $and$ls180.v:5934$1239 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240326,43 +241194,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:5882$1173_Y + connect \Y $and$ls180.v:5934$1239_Y end - attribute \src "ls180.v:5882.40-5882.144" - cell $and $and$ls180.v:5882$1175 + attribute \src "ls180.v:5934.40-5934.144" + cell $and $and$ls180.v:5934$1241 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5882$1173_Y - connect \B $eq$ls180.v:5882$1174_Y - connect \Y $and$ls180.v:5882$1175_Y + connect \A $and$ls180.v:5934$1239_Y + connect \B $eq$ls180.v:5934$1240_Y + connect \Y $and$ls180.v:5934$1241_Y end - attribute \src "ls180.v:5883.41-5883.97" - cell $and $and$ls180.v:5883$1177 + attribute \src "ls180.v:5935.41-5935.97" + cell $and $and$ls180.v:5935$1243 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:5883$1176_Y - connect \Y $and$ls180.v:5883$1177_Y + connect \B $not$ls180.v:5935$1242_Y + connect \Y $and$ls180.v:5935$1243_Y end - attribute \src "ls180.v:5883.40-5883.147" - cell $and $and$ls180.v:5883$1179 + attribute \src "ls180.v:5935.40-5935.147" + cell $and $and$ls180.v:5935$1245 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5883$1177_Y - connect \B $eq$ls180.v:5883$1178_Y - connect \Y $and$ls180.v:5883$1179_Y + connect \A $and$ls180.v:5935$1243_Y + connect \B $eq$ls180.v:5935$1244_Y + connect \Y $and$ls180.v:5935$1245_Y end - attribute \src "ls180.v:5885.41-5885.94" - cell $and $and$ls180.v:5885$1180 + attribute \src "ls180.v:5937.41-5937.94" + cell $and $and$ls180.v:5937$1246 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240370,43 +241238,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:5885$1180_Y + connect \Y $and$ls180.v:5937$1246_Y end - attribute \src "ls180.v:5885.40-5885.144" - cell $and $and$ls180.v:5885$1182 + attribute \src "ls180.v:5937.40-5937.144" + cell $and $and$ls180.v:5937$1248 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5885$1180_Y - connect \B $eq$ls180.v:5885$1181_Y - connect \Y $and$ls180.v:5885$1182_Y + connect \A $and$ls180.v:5937$1246_Y + connect \B $eq$ls180.v:5937$1247_Y + connect \Y $and$ls180.v:5937$1248_Y end - attribute \src "ls180.v:5886.41-5886.97" - cell $and $and$ls180.v:5886$1184 + attribute \src "ls180.v:5938.41-5938.97" + cell $and $and$ls180.v:5938$1250 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:5886$1183_Y - connect \Y $and$ls180.v:5886$1184_Y + connect \B $not$ls180.v:5938$1249_Y + connect \Y $and$ls180.v:5938$1250_Y end - attribute \src "ls180.v:5886.40-5886.147" - cell $and $and$ls180.v:5886$1186 + attribute \src "ls180.v:5938.40-5938.147" + cell $and $and$ls180.v:5938$1252 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5886$1184_Y - connect \B $eq$ls180.v:5886$1185_Y - connect \Y $and$ls180.v:5886$1186_Y + connect \A $and$ls180.v:5938$1250_Y + connect \B $eq$ls180.v:5938$1251_Y + connect \Y $and$ls180.v:5938$1252_Y end - attribute \src "ls180.v:5888.44-5888.97" - cell $and $and$ls180.v:5888$1187 + attribute \src "ls180.v:5940.44-5940.97" + cell $and $and$ls180.v:5940$1253 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240414,43 +241282,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:5888$1187_Y + connect \Y $and$ls180.v:5940$1253_Y end - attribute \src "ls180.v:5888.43-5888.147" - cell $and $and$ls180.v:5888$1189 + attribute \src "ls180.v:5940.43-5940.147" + cell $and $and$ls180.v:5940$1255 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5888$1187_Y - connect \B $eq$ls180.v:5888$1188_Y - connect \Y $and$ls180.v:5888$1189_Y + connect \A $and$ls180.v:5940$1253_Y + connect \B $eq$ls180.v:5940$1254_Y + connect \Y $and$ls180.v:5940$1255_Y end - attribute \src "ls180.v:5889.44-5889.100" - cell $and $and$ls180.v:5889$1191 + attribute \src "ls180.v:5941.44-5941.100" + cell $and $and$ls180.v:5941$1257 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:5889$1190_Y - connect \Y $and$ls180.v:5889$1191_Y + connect \B $not$ls180.v:5941$1256_Y + connect \Y $and$ls180.v:5941$1257_Y end - attribute \src "ls180.v:5889.43-5889.150" - cell $and $and$ls180.v:5889$1193 + attribute \src "ls180.v:5941.43-5941.150" + cell $and $and$ls180.v:5941$1259 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5889$1191_Y - connect \B $eq$ls180.v:5889$1192_Y - connect \Y $and$ls180.v:5889$1193_Y + connect \A $and$ls180.v:5941$1257_Y + connect \B $eq$ls180.v:5941$1258_Y + connect \Y $and$ls180.v:5941$1259_Y end - attribute \src "ls180.v:5891.44-5891.97" - cell $and $and$ls180.v:5891$1194 + attribute \src "ls180.v:5943.44-5943.97" + cell $and $and$ls180.v:5943$1260 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240458,43 +241326,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:5891$1194_Y + connect \Y $and$ls180.v:5943$1260_Y end - attribute \src "ls180.v:5891.43-5891.147" - cell $and $and$ls180.v:5891$1196 + attribute \src "ls180.v:5943.43-5943.147" + cell $and $and$ls180.v:5943$1262 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5891$1194_Y - connect \B $eq$ls180.v:5891$1195_Y - connect \Y $and$ls180.v:5891$1196_Y + connect \A $and$ls180.v:5943$1260_Y + connect \B $eq$ls180.v:5943$1261_Y + connect \Y $and$ls180.v:5943$1262_Y end - attribute \src "ls180.v:5892.44-5892.100" - cell $and $and$ls180.v:5892$1198 + attribute \src "ls180.v:5944.44-5944.100" + cell $and $and$ls180.v:5944$1264 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:5892$1197_Y - connect \Y $and$ls180.v:5892$1198_Y + connect \B $not$ls180.v:5944$1263_Y + connect \Y $and$ls180.v:5944$1264_Y end - attribute \src "ls180.v:5892.43-5892.150" - cell $and $and$ls180.v:5892$1200 + attribute \src "ls180.v:5944.43-5944.150" + cell $and $and$ls180.v:5944$1266 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5892$1198_Y - connect \B $eq$ls180.v:5892$1199_Y - connect \Y $and$ls180.v:5892$1200_Y + connect \A $and$ls180.v:5944$1264_Y + connect \B $eq$ls180.v:5944$1265_Y + connect \Y $and$ls180.v:5944$1266_Y end - attribute \src "ls180.v:5894.44-5894.97" - cell $and $and$ls180.v:5894$1201 + attribute \src "ls180.v:5946.44-5946.97" + cell $and $and$ls180.v:5946$1267 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240502,43 +241370,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:5894$1201_Y + connect \Y $and$ls180.v:5946$1267_Y end - attribute \src "ls180.v:5894.43-5894.147" - cell $and $and$ls180.v:5894$1203 + attribute \src "ls180.v:5946.43-5946.147" + cell $and $and$ls180.v:5946$1269 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5894$1201_Y - connect \B $eq$ls180.v:5894$1202_Y - connect \Y $and$ls180.v:5894$1203_Y + connect \A $and$ls180.v:5946$1267_Y + connect \B $eq$ls180.v:5946$1268_Y + connect \Y $and$ls180.v:5946$1269_Y end - attribute \src "ls180.v:5895.44-5895.100" - cell $and $and$ls180.v:5895$1205 + attribute \src "ls180.v:5947.44-5947.100" + cell $and $and$ls180.v:5947$1271 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:5895$1204_Y - connect \Y $and$ls180.v:5895$1205_Y + connect \B $not$ls180.v:5947$1270_Y + connect \Y $and$ls180.v:5947$1271_Y end - attribute \src "ls180.v:5895.43-5895.150" - cell $and $and$ls180.v:5895$1207 + attribute \src "ls180.v:5947.43-5947.150" + cell $and $and$ls180.v:5947$1273 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5895$1205_Y - connect \B $eq$ls180.v:5895$1206_Y - connect \Y $and$ls180.v:5895$1207_Y + connect \A $and$ls180.v:5947$1271_Y + connect \B $eq$ls180.v:5947$1272_Y + connect \Y $and$ls180.v:5947$1273_Y end - attribute \src "ls180.v:5897.44-5897.97" - cell $and $and$ls180.v:5897$1208 + attribute \src "ls180.v:5949.44-5949.97" + cell $and $and$ls180.v:5949$1274 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240546,43 +241414,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:5897$1208_Y + connect \Y $and$ls180.v:5949$1274_Y end - attribute \src "ls180.v:5897.43-5897.147" - cell $and $and$ls180.v:5897$1210 + attribute \src "ls180.v:5949.43-5949.147" + cell $and $and$ls180.v:5949$1276 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5897$1208_Y - connect \B $eq$ls180.v:5897$1209_Y - connect \Y $and$ls180.v:5897$1210_Y + connect \A $and$ls180.v:5949$1274_Y + connect \B $eq$ls180.v:5949$1275_Y + connect \Y $and$ls180.v:5949$1276_Y end - attribute \src "ls180.v:5898.44-5898.100" - cell $and $and$ls180.v:5898$1212 + attribute \src "ls180.v:5950.44-5950.100" + cell $and $and$ls180.v:5950$1278 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:5898$1211_Y - connect \Y $and$ls180.v:5898$1212_Y + connect \B $not$ls180.v:5950$1277_Y + connect \Y $and$ls180.v:5950$1278_Y end - attribute \src "ls180.v:5898.43-5898.150" - cell $and $and$ls180.v:5898$1214 + attribute \src "ls180.v:5950.43-5950.150" + cell $and $and$ls180.v:5950$1280 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5898$1212_Y - connect \B $eq$ls180.v:5898$1213_Y - connect \Y $and$ls180.v:5898$1214_Y + connect \A $and$ls180.v:5950$1278_Y + connect \B $eq$ls180.v:5950$1279_Y + connect \Y $and$ls180.v:5950$1280_Y end - attribute \src "ls180.v:5911.36-5911.89" - cell $and $and$ls180.v:5911$1216 + attribute \src "ls180.v:5963.36-5963.89" + cell $and $and$ls180.v:5963$1282 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240590,43 +241458,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank1_sel connect \B \builder_interface1_bank_bus_we - connect \Y $and$ls180.v:5911$1216_Y + connect \Y $and$ls180.v:5963$1282_Y end - attribute \src "ls180.v:5911.35-5911.139" - cell $and $and$ls180.v:5911$1218 + attribute \src "ls180.v:5963.35-5963.139" + cell $and $and$ls180.v:5963$1284 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5911$1216_Y - connect \B $eq$ls180.v:5911$1217_Y - connect \Y $and$ls180.v:5911$1218_Y + connect \A $and$ls180.v:5963$1282_Y + connect \B $eq$ls180.v:5963$1283_Y + connect \Y $and$ls180.v:5963$1284_Y end - attribute \src "ls180.v:5912.36-5912.92" - cell $and $and$ls180.v:5912$1220 + attribute \src "ls180.v:5964.36-5964.92" + cell $and $and$ls180.v:5964$1286 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank1_sel - connect \B $not$ls180.v:5912$1219_Y - connect \Y $and$ls180.v:5912$1220_Y + connect \B $not$ls180.v:5964$1285_Y + connect \Y $and$ls180.v:5964$1286_Y end - attribute \src "ls180.v:5912.35-5912.142" - cell $and $and$ls180.v:5912$1222 + attribute \src "ls180.v:5964.35-5964.142" + cell $and $and$ls180.v:5964$1288 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5912$1220_Y - connect \B $eq$ls180.v:5912$1221_Y - connect \Y $and$ls180.v:5912$1222_Y + connect \A $and$ls180.v:5964$1286_Y + connect \B $eq$ls180.v:5964$1287_Y + connect \Y $and$ls180.v:5964$1288_Y end - attribute \src "ls180.v:5914.36-5914.89" - cell $and $and$ls180.v:5914$1223 + attribute \src "ls180.v:5966.36-5966.89" + cell $and $and$ls180.v:5966$1289 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240634,43 +241502,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank1_sel connect \B \builder_interface1_bank_bus_we - connect \Y $and$ls180.v:5914$1223_Y + connect \Y $and$ls180.v:5966$1289_Y end - attribute \src "ls180.v:5914.35-5914.139" - cell $and $and$ls180.v:5914$1225 + attribute \src "ls180.v:5966.35-5966.139" + cell $and $and$ls180.v:5966$1291 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5914$1223_Y - connect \B $eq$ls180.v:5914$1224_Y - connect \Y $and$ls180.v:5914$1225_Y + connect \A $and$ls180.v:5966$1289_Y + connect \B $eq$ls180.v:5966$1290_Y + connect \Y $and$ls180.v:5966$1291_Y end - attribute \src "ls180.v:5915.36-5915.92" - cell $and $and$ls180.v:5915$1227 + attribute \src "ls180.v:5967.36-5967.92" + cell $and $and$ls180.v:5967$1293 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank1_sel - connect \B $not$ls180.v:5915$1226_Y - connect \Y $and$ls180.v:5915$1227_Y + connect \B $not$ls180.v:5967$1292_Y + connect \Y $and$ls180.v:5967$1293_Y end - attribute \src "ls180.v:5915.35-5915.142" - cell $and $and$ls180.v:5915$1229 + attribute \src "ls180.v:5967.35-5967.142" + cell $and $and$ls180.v:5967$1295 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5915$1227_Y - connect \B $eq$ls180.v:5915$1228_Y - connect \Y $and$ls180.v:5915$1229_Y + connect \A $and$ls180.v:5967$1293_Y + connect \B $eq$ls180.v:5967$1294_Y + connect \Y $and$ls180.v:5967$1295_Y end - attribute \src "ls180.v:5917.36-5917.89" - cell $and $and$ls180.v:5917$1230 + attribute \src "ls180.v:5969.36-5969.89" + cell $and $and$ls180.v:5969$1296 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240678,43 +241546,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank1_sel connect \B \builder_interface1_bank_bus_we - connect \Y $and$ls180.v:5917$1230_Y + connect \Y $and$ls180.v:5969$1296_Y end - attribute \src "ls180.v:5917.35-5917.139" - cell $and $and$ls180.v:5917$1232 + attribute \src "ls180.v:5969.35-5969.139" + cell $and $and$ls180.v:5969$1298 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5917$1230_Y - connect \B $eq$ls180.v:5917$1231_Y - connect \Y $and$ls180.v:5917$1232_Y + connect \A $and$ls180.v:5969$1296_Y + connect \B $eq$ls180.v:5969$1297_Y + connect \Y $and$ls180.v:5969$1298_Y end - attribute \src "ls180.v:5918.36-5918.92" - cell $and $and$ls180.v:5918$1234 + attribute \src "ls180.v:5970.36-5970.92" + cell $and $and$ls180.v:5970$1300 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank1_sel - connect \B $not$ls180.v:5918$1233_Y - connect \Y $and$ls180.v:5918$1234_Y + connect \B $not$ls180.v:5970$1299_Y + connect \Y $and$ls180.v:5970$1300_Y end - attribute \src "ls180.v:5918.35-5918.142" - cell $and $and$ls180.v:5918$1236 + attribute \src "ls180.v:5970.35-5970.142" + cell $and $and$ls180.v:5970$1302 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5918$1234_Y - connect \B $eq$ls180.v:5918$1235_Y - connect \Y $and$ls180.v:5918$1236_Y + connect \A $and$ls180.v:5970$1300_Y + connect \B $eq$ls180.v:5970$1301_Y + connect \Y $and$ls180.v:5970$1302_Y end - attribute \src "ls180.v:5920.36-5920.89" - cell $and $and$ls180.v:5920$1237 + attribute \src "ls180.v:5972.36-5972.89" + cell $and $and$ls180.v:5972$1303 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240722,43 +241590,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank1_sel connect \B \builder_interface1_bank_bus_we - connect \Y $and$ls180.v:5920$1237_Y + connect \Y $and$ls180.v:5972$1303_Y end - attribute \src "ls180.v:5920.35-5920.139" - cell $and $and$ls180.v:5920$1239 + attribute \src "ls180.v:5972.35-5972.139" + cell $and $and$ls180.v:5972$1305 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5920$1237_Y - connect \B $eq$ls180.v:5920$1238_Y - connect \Y $and$ls180.v:5920$1239_Y + connect \A $and$ls180.v:5972$1303_Y + connect \B $eq$ls180.v:5972$1304_Y + connect \Y $and$ls180.v:5972$1305_Y end - attribute \src "ls180.v:5921.36-5921.92" - cell $and $and$ls180.v:5921$1241 + attribute \src "ls180.v:5973.36-5973.92" + cell $and $and$ls180.v:5973$1307 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank1_sel - connect \B $not$ls180.v:5921$1240_Y - connect \Y $and$ls180.v:5921$1241_Y + connect \B $not$ls180.v:5973$1306_Y + connect \Y $and$ls180.v:5973$1307_Y end - attribute \src "ls180.v:5921.35-5921.142" - cell $and $and$ls180.v:5921$1243 + attribute \src "ls180.v:5973.35-5973.142" + cell $and $and$ls180.v:5973$1309 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5921$1241_Y - connect \B $eq$ls180.v:5921$1242_Y - connect \Y $and$ls180.v:5921$1243_Y + connect \A $and$ls180.v:5973$1307_Y + connect \B $eq$ls180.v:5973$1308_Y + connect \Y $and$ls180.v:5973$1309_Y end - attribute \src "ls180.v:5923.37-5923.90" - cell $and $and$ls180.v:5923$1244 + attribute \src "ls180.v:5975.37-5975.90" + cell $and $and$ls180.v:5975$1310 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240766,43 +241634,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank1_sel connect \B \builder_interface1_bank_bus_we - connect \Y $and$ls180.v:5923$1244_Y + connect \Y $and$ls180.v:5975$1310_Y end - attribute \src "ls180.v:5923.36-5923.140" - cell $and $and$ls180.v:5923$1246 + attribute \src "ls180.v:5975.36-5975.140" + cell $and $and$ls180.v:5975$1312 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5923$1244_Y - connect \B $eq$ls180.v:5923$1245_Y - connect \Y $and$ls180.v:5923$1246_Y + connect \A $and$ls180.v:5975$1310_Y + connect \B $eq$ls180.v:5975$1311_Y + connect \Y $and$ls180.v:5975$1312_Y end - attribute \src "ls180.v:5924.37-5924.93" - cell $and $and$ls180.v:5924$1248 + attribute \src "ls180.v:5976.37-5976.93" + cell $and $and$ls180.v:5976$1314 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank1_sel - connect \B $not$ls180.v:5924$1247_Y - connect \Y $and$ls180.v:5924$1248_Y + connect \B $not$ls180.v:5976$1313_Y + connect \Y $and$ls180.v:5976$1314_Y end - attribute \src "ls180.v:5924.36-5924.143" - cell $and $and$ls180.v:5924$1250 + attribute \src "ls180.v:5976.36-5976.143" + cell $and $and$ls180.v:5976$1316 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5924$1248_Y - connect \B $eq$ls180.v:5924$1249_Y - connect \Y $and$ls180.v:5924$1250_Y + connect \A $and$ls180.v:5976$1314_Y + connect \B $eq$ls180.v:5976$1315_Y + connect \Y $and$ls180.v:5976$1316_Y end - attribute \src "ls180.v:5926.37-5926.90" - cell $and $and$ls180.v:5926$1251 + attribute \src "ls180.v:5978.37-5978.90" + cell $and $and$ls180.v:5978$1317 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240810,43 +241678,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank1_sel connect \B \builder_interface1_bank_bus_we - connect \Y $and$ls180.v:5926$1251_Y + connect \Y $and$ls180.v:5978$1317_Y end - attribute \src "ls180.v:5926.36-5926.140" - cell $and $and$ls180.v:5926$1253 + attribute \src "ls180.v:5978.36-5978.140" + cell $and $and$ls180.v:5978$1319 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5926$1251_Y - connect \B $eq$ls180.v:5926$1252_Y - connect \Y $and$ls180.v:5926$1253_Y + connect \A $and$ls180.v:5978$1317_Y + connect \B $eq$ls180.v:5978$1318_Y + connect \Y $and$ls180.v:5978$1319_Y end - attribute \src "ls180.v:5927.37-5927.93" - cell $and $and$ls180.v:5927$1255 + attribute \src "ls180.v:5979.37-5979.93" + cell $and $and$ls180.v:5979$1321 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank1_sel - connect \B $not$ls180.v:5927$1254_Y - connect \Y $and$ls180.v:5927$1255_Y + connect \B $not$ls180.v:5979$1320_Y + connect \Y $and$ls180.v:5979$1321_Y end - attribute \src "ls180.v:5927.36-5927.143" - cell $and $and$ls180.v:5927$1257 + attribute \src "ls180.v:5979.36-5979.143" + cell $and $and$ls180.v:5979$1323 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5927$1255_Y - connect \B $eq$ls180.v:5927$1256_Y - connect \Y $and$ls180.v:5927$1257_Y + connect \A $and$ls180.v:5979$1321_Y + connect \B $eq$ls180.v:5979$1322_Y + connect \Y $and$ls180.v:5979$1323_Y end - attribute \src "ls180.v:5937.35-5937.88" - cell $and $and$ls180.v:5937$1259 + attribute \src "ls180.v:5989.35-5989.88" + cell $and $and$ls180.v:5989$1325 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240854,43 +241722,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank2_sel connect \B \builder_interface2_bank_bus_we - connect \Y $and$ls180.v:5937$1259_Y + connect \Y $and$ls180.v:5989$1325_Y end - attribute \src "ls180.v:5937.34-5937.136" - cell $and $and$ls180.v:5937$1261 + attribute \src "ls180.v:5989.34-5989.136" + cell $and $and$ls180.v:5989$1327 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5937$1259_Y - connect \B $eq$ls180.v:5937$1260_Y - connect \Y $and$ls180.v:5937$1261_Y + connect \A $and$ls180.v:5989$1325_Y + connect \B $eq$ls180.v:5989$1326_Y + connect \Y $and$ls180.v:5989$1327_Y end - attribute \src "ls180.v:5938.35-5938.91" - cell $and $and$ls180.v:5938$1263 + attribute \src "ls180.v:5990.35-5990.91" + cell $and $and$ls180.v:5990$1329 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank2_sel - connect \B $not$ls180.v:5938$1262_Y - connect \Y $and$ls180.v:5938$1263_Y + connect \B $not$ls180.v:5990$1328_Y + connect \Y $and$ls180.v:5990$1329_Y end - attribute \src "ls180.v:5938.34-5938.139" - cell $and $and$ls180.v:5938$1265 + attribute \src "ls180.v:5990.34-5990.139" + cell $and $and$ls180.v:5990$1331 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5938$1263_Y - connect \B $eq$ls180.v:5938$1264_Y - connect \Y $and$ls180.v:5938$1265_Y + connect \A $and$ls180.v:5990$1329_Y + connect \B $eq$ls180.v:5990$1330_Y + connect \Y $and$ls180.v:5990$1331_Y end - attribute \src "ls180.v:5940.34-5940.87" - cell $and $and$ls180.v:5940$1266 + attribute \src "ls180.v:5992.34-5992.87" + cell $and $and$ls180.v:5992$1332 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240898,43 +241766,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank2_sel connect \B \builder_interface2_bank_bus_we - connect \Y $and$ls180.v:5940$1266_Y + connect \Y $and$ls180.v:5992$1332_Y end - attribute \src "ls180.v:5940.33-5940.135" - cell $and $and$ls180.v:5940$1268 + attribute \src "ls180.v:5992.33-5992.135" + cell $and $and$ls180.v:5992$1334 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5940$1266_Y - connect \B $eq$ls180.v:5940$1267_Y - connect \Y $and$ls180.v:5940$1268_Y + connect \A $and$ls180.v:5992$1332_Y + connect \B $eq$ls180.v:5992$1333_Y + connect \Y $and$ls180.v:5992$1334_Y end - attribute \src "ls180.v:5941.34-5941.90" - cell $and $and$ls180.v:5941$1270 + attribute \src "ls180.v:5993.34-5993.90" + cell $and $and$ls180.v:5993$1336 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank2_sel - connect \B $not$ls180.v:5941$1269_Y - connect \Y $and$ls180.v:5941$1270_Y + connect \B $not$ls180.v:5993$1335_Y + connect \Y $and$ls180.v:5993$1336_Y end - attribute \src "ls180.v:5941.33-5941.138" - cell $and $and$ls180.v:5941$1272 + attribute \src "ls180.v:5993.33-5993.138" + cell $and $and$ls180.v:5993$1338 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5941$1270_Y - connect \B $eq$ls180.v:5941$1271_Y - connect \Y $and$ls180.v:5941$1272_Y + connect \A $and$ls180.v:5993$1336_Y + connect \B $eq$ls180.v:5993$1337_Y + connect \Y $and$ls180.v:5993$1338_Y end - attribute \src "ls180.v:5951.40-5951.93" - cell $and $and$ls180.v:5951$1274 + attribute \src "ls180.v:6003.40-6003.93" + cell $and $and$ls180.v:6003$1340 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240942,43 +241810,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5951$1274_Y + connect \Y $and$ls180.v:6003$1340_Y end - attribute \src "ls180.v:5951.39-5951.143" - cell $and $and$ls180.v:5951$1276 + attribute \src "ls180.v:6003.39-6003.143" + cell $and $and$ls180.v:6003$1342 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5951$1274_Y - connect \B $eq$ls180.v:5951$1275_Y - connect \Y $and$ls180.v:5951$1276_Y + connect \A $and$ls180.v:6003$1340_Y + connect \B $eq$ls180.v:6003$1341_Y + connect \Y $and$ls180.v:6003$1342_Y end - attribute \src "ls180.v:5952.40-5952.96" - cell $and $and$ls180.v:5952$1278 + attribute \src "ls180.v:6004.40-6004.96" + cell $and $and$ls180.v:6004$1344 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5952$1277_Y - connect \Y $and$ls180.v:5952$1278_Y + connect \B $not$ls180.v:6004$1343_Y + connect \Y $and$ls180.v:6004$1344_Y end - attribute \src "ls180.v:5952.39-5952.146" - cell $and $and$ls180.v:5952$1280 + attribute \src "ls180.v:6004.39-6004.146" + cell $and $and$ls180.v:6004$1346 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5952$1278_Y - connect \B $eq$ls180.v:5952$1279_Y - connect \Y $and$ls180.v:5952$1280_Y + connect \A $and$ls180.v:6004$1344_Y + connect \B $eq$ls180.v:6004$1345_Y + connect \Y $and$ls180.v:6004$1346_Y end - attribute \src "ls180.v:5954.39-5954.92" - cell $and $and$ls180.v:5954$1281 + attribute \src "ls180.v:6006.39-6006.92" + cell $and $and$ls180.v:6006$1347 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240986,43 +241854,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5954$1281_Y + connect \Y $and$ls180.v:6006$1347_Y end - attribute \src "ls180.v:5954.38-5954.142" - cell $and $and$ls180.v:5954$1283 + attribute \src "ls180.v:6006.38-6006.142" + cell $and $and$ls180.v:6006$1349 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5954$1281_Y - connect \B $eq$ls180.v:5954$1282_Y - connect \Y $and$ls180.v:5954$1283_Y + connect \A $and$ls180.v:6006$1347_Y + connect \B $eq$ls180.v:6006$1348_Y + connect \Y $and$ls180.v:6006$1349_Y end - attribute \src "ls180.v:5955.39-5955.95" - cell $and $and$ls180.v:5955$1285 + attribute \src "ls180.v:6007.39-6007.95" + cell $and $and$ls180.v:6007$1351 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5955$1284_Y - connect \Y $and$ls180.v:5955$1285_Y + connect \B $not$ls180.v:6007$1350_Y + connect \Y $and$ls180.v:6007$1351_Y end - attribute \src "ls180.v:5955.38-5955.145" - cell $and $and$ls180.v:5955$1287 + attribute \src "ls180.v:6007.38-6007.145" + cell $and $and$ls180.v:6007$1353 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5955$1285_Y - connect \B $eq$ls180.v:5955$1286_Y - connect \Y $and$ls180.v:5955$1287_Y + connect \A $and$ls180.v:6007$1351_Y + connect \B $eq$ls180.v:6007$1352_Y + connect \Y $and$ls180.v:6007$1353_Y end - attribute \src "ls180.v:5957.39-5957.92" - cell $and $and$ls180.v:5957$1288 + attribute \src "ls180.v:6009.39-6009.92" + cell $and $and$ls180.v:6009$1354 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241030,43 +241898,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5957$1288_Y + connect \Y $and$ls180.v:6009$1354_Y end - attribute \src "ls180.v:5957.38-5957.142" - cell $and $and$ls180.v:5957$1290 + attribute \src "ls180.v:6009.38-6009.142" + cell $and $and$ls180.v:6009$1356 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5957$1288_Y - connect \B $eq$ls180.v:5957$1289_Y - connect \Y $and$ls180.v:5957$1290_Y + connect \A $and$ls180.v:6009$1354_Y + connect \B $eq$ls180.v:6009$1355_Y + connect \Y $and$ls180.v:6009$1356_Y end - attribute \src "ls180.v:5958.39-5958.95" - cell $and $and$ls180.v:5958$1292 + attribute \src "ls180.v:6010.39-6010.95" + cell $and $and$ls180.v:6010$1358 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5958$1291_Y - connect \Y $and$ls180.v:5958$1292_Y + connect \B $not$ls180.v:6010$1357_Y + connect \Y $and$ls180.v:6010$1358_Y end - attribute \src "ls180.v:5958.38-5958.145" - cell $and $and$ls180.v:5958$1294 + attribute \src "ls180.v:6010.38-6010.145" + cell $and $and$ls180.v:6010$1360 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5958$1292_Y - connect \B $eq$ls180.v:5958$1293_Y - connect \Y $and$ls180.v:5958$1294_Y + connect \A $and$ls180.v:6010$1358_Y + connect \B $eq$ls180.v:6010$1359_Y + connect \Y $and$ls180.v:6010$1360_Y end - attribute \src "ls180.v:5960.39-5960.92" - cell $and $and$ls180.v:5960$1295 + attribute \src "ls180.v:6012.39-6012.92" + cell $and $and$ls180.v:6012$1361 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241074,43 +241942,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5960$1295_Y + connect \Y $and$ls180.v:6012$1361_Y end - attribute \src "ls180.v:5960.38-5960.142" - cell $and $and$ls180.v:5960$1297 + attribute \src "ls180.v:6012.38-6012.142" + cell $and $and$ls180.v:6012$1363 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5960$1295_Y - connect \B $eq$ls180.v:5960$1296_Y - connect \Y $and$ls180.v:5960$1297_Y + connect \A $and$ls180.v:6012$1361_Y + connect \B $eq$ls180.v:6012$1362_Y + connect \Y $and$ls180.v:6012$1363_Y end - attribute \src "ls180.v:5961.39-5961.95" - cell $and $and$ls180.v:5961$1299 + attribute \src "ls180.v:6013.39-6013.95" + cell $and $and$ls180.v:6013$1365 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5961$1298_Y - connect \Y $and$ls180.v:5961$1299_Y + connect \B $not$ls180.v:6013$1364_Y + connect \Y $and$ls180.v:6013$1365_Y end - attribute \src "ls180.v:5961.38-5961.145" - cell $and $and$ls180.v:5961$1301 + attribute \src "ls180.v:6013.38-6013.145" + cell $and $and$ls180.v:6013$1367 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5961$1299_Y - connect \B $eq$ls180.v:5961$1300_Y - connect \Y $and$ls180.v:5961$1301_Y + connect \A $and$ls180.v:6013$1365_Y + connect \B $eq$ls180.v:6013$1366_Y + connect \Y $and$ls180.v:6013$1367_Y end - attribute \src "ls180.v:5963.39-5963.92" - cell $and $and$ls180.v:5963$1302 + attribute \src "ls180.v:6015.39-6015.92" + cell $and $and$ls180.v:6015$1368 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241118,43 +241986,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5963$1302_Y + connect \Y $and$ls180.v:6015$1368_Y end - attribute \src "ls180.v:5963.38-5963.142" - cell $and $and$ls180.v:5963$1304 + attribute \src "ls180.v:6015.38-6015.142" + cell $and $and$ls180.v:6015$1370 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5963$1302_Y - connect \B $eq$ls180.v:5963$1303_Y - connect \Y $and$ls180.v:5963$1304_Y + connect \A $and$ls180.v:6015$1368_Y + connect \B $eq$ls180.v:6015$1369_Y + connect \Y $and$ls180.v:6015$1370_Y end - attribute \src "ls180.v:5964.39-5964.95" - cell $and $and$ls180.v:5964$1306 + attribute \src "ls180.v:6016.39-6016.95" + cell $and $and$ls180.v:6016$1372 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5964$1305_Y - connect \Y $and$ls180.v:5964$1306_Y + connect \B $not$ls180.v:6016$1371_Y + connect \Y $and$ls180.v:6016$1372_Y end - attribute \src "ls180.v:5964.38-5964.145" - cell $and $and$ls180.v:5964$1308 + attribute \src "ls180.v:6016.38-6016.145" + cell $and $and$ls180.v:6016$1374 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5964$1306_Y - connect \B $eq$ls180.v:5964$1307_Y - connect \Y $and$ls180.v:5964$1308_Y + connect \A $and$ls180.v:6016$1372_Y + connect \B $eq$ls180.v:6016$1373_Y + connect \Y $and$ls180.v:6016$1374_Y end - attribute \src "ls180.v:5966.40-5966.93" - cell $and $and$ls180.v:5966$1309 + attribute \src "ls180.v:6018.40-6018.93" + cell $and $and$ls180.v:6018$1375 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241162,43 +242030,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5966$1309_Y + connect \Y $and$ls180.v:6018$1375_Y end - attribute \src "ls180.v:5966.39-5966.143" - cell $and $and$ls180.v:5966$1311 + attribute \src "ls180.v:6018.39-6018.143" + cell $and $and$ls180.v:6018$1377 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5966$1309_Y - connect \B $eq$ls180.v:5966$1310_Y - connect \Y $and$ls180.v:5966$1311_Y + connect \A $and$ls180.v:6018$1375_Y + connect \B $eq$ls180.v:6018$1376_Y + connect \Y $and$ls180.v:6018$1377_Y end - attribute \src "ls180.v:5967.40-5967.96" - cell $and $and$ls180.v:5967$1313 + attribute \src "ls180.v:6019.40-6019.96" + cell $and $and$ls180.v:6019$1379 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5967$1312_Y - connect \Y $and$ls180.v:5967$1313_Y + connect \B $not$ls180.v:6019$1378_Y + connect \Y $and$ls180.v:6019$1379_Y end - attribute \src "ls180.v:5967.39-5967.146" - cell $and $and$ls180.v:5967$1315 + attribute \src "ls180.v:6019.39-6019.146" + cell $and $and$ls180.v:6019$1381 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5967$1313_Y - connect \B $eq$ls180.v:5967$1314_Y - connect \Y $and$ls180.v:5967$1315_Y + connect \A $and$ls180.v:6019$1379_Y + connect \B $eq$ls180.v:6019$1380_Y + connect \Y $and$ls180.v:6019$1381_Y end - attribute \src "ls180.v:5969.40-5969.93" - cell $and $and$ls180.v:5969$1316 + attribute \src "ls180.v:6021.40-6021.93" + cell $and $and$ls180.v:6021$1382 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241206,43 +242074,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5969$1316_Y + connect \Y $and$ls180.v:6021$1382_Y end - attribute \src "ls180.v:5969.39-5969.143" - cell $and $and$ls180.v:5969$1318 + attribute \src "ls180.v:6021.39-6021.143" + cell $and $and$ls180.v:6021$1384 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5969$1316_Y - connect \B $eq$ls180.v:5969$1317_Y - connect \Y $and$ls180.v:5969$1318_Y + connect \A $and$ls180.v:6021$1382_Y + connect \B $eq$ls180.v:6021$1383_Y + connect \Y $and$ls180.v:6021$1384_Y end - attribute \src "ls180.v:5970.40-5970.96" - cell $and $and$ls180.v:5970$1320 + attribute \src "ls180.v:6022.40-6022.96" + cell $and $and$ls180.v:6022$1386 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5970$1319_Y - connect \Y $and$ls180.v:5970$1320_Y + connect \B $not$ls180.v:6022$1385_Y + connect \Y $and$ls180.v:6022$1386_Y end - attribute \src "ls180.v:5970.39-5970.146" - cell $and $and$ls180.v:5970$1322 + attribute \src "ls180.v:6022.39-6022.146" + cell $and $and$ls180.v:6022$1388 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5970$1320_Y - connect \B $eq$ls180.v:5970$1321_Y - connect \Y $and$ls180.v:5970$1322_Y + connect \A $and$ls180.v:6022$1386_Y + connect \B $eq$ls180.v:6022$1387_Y + connect \Y $and$ls180.v:6022$1388_Y end - attribute \src "ls180.v:5972.40-5972.93" - cell $and $and$ls180.v:5972$1323 + attribute \src "ls180.v:6024.40-6024.93" + cell $and $and$ls180.v:6024$1389 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241250,43 +242118,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5972$1323_Y + connect \Y $and$ls180.v:6024$1389_Y end - attribute \src "ls180.v:5972.39-5972.143" - cell $and $and$ls180.v:5972$1325 + attribute \src "ls180.v:6024.39-6024.143" + cell $and $and$ls180.v:6024$1391 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5972$1323_Y - connect \B $eq$ls180.v:5972$1324_Y - connect \Y $and$ls180.v:5972$1325_Y + connect \A $and$ls180.v:6024$1389_Y + connect \B $eq$ls180.v:6024$1390_Y + connect \Y $and$ls180.v:6024$1391_Y end - attribute \src "ls180.v:5973.40-5973.96" - cell $and $and$ls180.v:5973$1327 + attribute \src "ls180.v:6025.40-6025.96" + cell $and $and$ls180.v:6025$1393 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5973$1326_Y - connect \Y $and$ls180.v:5973$1327_Y + connect \B $not$ls180.v:6025$1392_Y + connect \Y $and$ls180.v:6025$1393_Y end - attribute \src "ls180.v:5973.39-5973.146" - cell $and $and$ls180.v:5973$1329 + attribute \src "ls180.v:6025.39-6025.146" + cell $and $and$ls180.v:6025$1395 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5973$1327_Y - connect \B $eq$ls180.v:5973$1328_Y - connect \Y $and$ls180.v:5973$1329_Y + connect \A $and$ls180.v:6025$1393_Y + connect \B $eq$ls180.v:6025$1394_Y + connect \Y $and$ls180.v:6025$1395_Y end - attribute \src "ls180.v:5975.40-5975.93" - cell $and $and$ls180.v:5975$1330 + attribute \src "ls180.v:6027.40-6027.93" + cell $and $and$ls180.v:6027$1396 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241294,43 +242162,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5975$1330_Y + connect \Y $and$ls180.v:6027$1396_Y end - attribute \src "ls180.v:5975.39-5975.143" - cell $and $and$ls180.v:5975$1332 + attribute \src "ls180.v:6027.39-6027.143" + cell $and $and$ls180.v:6027$1398 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5975$1330_Y - connect \B $eq$ls180.v:5975$1331_Y - connect \Y $and$ls180.v:5975$1332_Y + connect \A $and$ls180.v:6027$1396_Y + connect \B $eq$ls180.v:6027$1397_Y + connect \Y $and$ls180.v:6027$1398_Y end - attribute \src "ls180.v:5976.40-5976.96" - cell $and $and$ls180.v:5976$1334 + attribute \src "ls180.v:6028.40-6028.96" + cell $and $and$ls180.v:6028$1400 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5976$1333_Y - connect \Y $and$ls180.v:5976$1334_Y + connect \B $not$ls180.v:6028$1399_Y + connect \Y $and$ls180.v:6028$1400_Y end - attribute \src "ls180.v:5976.39-5976.146" - cell $and $and$ls180.v:5976$1336 + attribute \src "ls180.v:6028.39-6028.146" + cell $and $and$ls180.v:6028$1402 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5976$1334_Y - connect \B $eq$ls180.v:5976$1335_Y - connect \Y $and$ls180.v:5976$1336_Y + connect \A $and$ls180.v:6028$1400_Y + connect \B $eq$ls180.v:6028$1401_Y + connect \Y $and$ls180.v:6028$1402_Y end - attribute \src "ls180.v:5988.40-5988.93" - cell $and $and$ls180.v:5988$1338 + attribute \src "ls180.v:6040.40-6040.93" + cell $and $and$ls180.v:6040$1404 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241338,43 +242206,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5988$1338_Y + connect \Y $and$ls180.v:6040$1404_Y end - attribute \src "ls180.v:5988.39-5988.143" - cell $and $and$ls180.v:5988$1340 + attribute \src "ls180.v:6040.39-6040.143" + cell $and $and$ls180.v:6040$1406 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5988$1338_Y - connect \B $eq$ls180.v:5988$1339_Y - connect \Y $and$ls180.v:5988$1340_Y + connect \A $and$ls180.v:6040$1404_Y + connect \B $eq$ls180.v:6040$1405_Y + connect \Y $and$ls180.v:6040$1406_Y end - attribute \src "ls180.v:5989.40-5989.96" - cell $and $and$ls180.v:5989$1342 + attribute \src "ls180.v:6041.40-6041.96" + cell $and $and$ls180.v:6041$1408 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5989$1341_Y - connect \Y $and$ls180.v:5989$1342_Y + connect \B $not$ls180.v:6041$1407_Y + connect \Y $and$ls180.v:6041$1408_Y end - attribute \src "ls180.v:5989.39-5989.146" - cell $and $and$ls180.v:5989$1344 + attribute \src "ls180.v:6041.39-6041.146" + cell $and $and$ls180.v:6041$1410 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5989$1342_Y - connect \B $eq$ls180.v:5989$1343_Y - connect \Y $and$ls180.v:5989$1344_Y + connect \A $and$ls180.v:6041$1408_Y + connect \B $eq$ls180.v:6041$1409_Y + connect \Y $and$ls180.v:6041$1410_Y end - attribute \src "ls180.v:5991.39-5991.92" - cell $and $and$ls180.v:5991$1345 + attribute \src "ls180.v:6043.39-6043.92" + cell $and $and$ls180.v:6043$1411 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241382,43 +242250,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5991$1345_Y + connect \Y $and$ls180.v:6043$1411_Y end - attribute \src "ls180.v:5991.38-5991.142" - cell $and $and$ls180.v:5991$1347 + attribute \src "ls180.v:6043.38-6043.142" + cell $and $and$ls180.v:6043$1413 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5991$1345_Y - connect \B $eq$ls180.v:5991$1346_Y - connect \Y $and$ls180.v:5991$1347_Y + connect \A $and$ls180.v:6043$1411_Y + connect \B $eq$ls180.v:6043$1412_Y + connect \Y $and$ls180.v:6043$1413_Y end - attribute \src "ls180.v:5992.39-5992.95" - cell $and $and$ls180.v:5992$1349 + attribute \src "ls180.v:6044.39-6044.95" + cell $and $and$ls180.v:6044$1415 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5992$1348_Y - connect \Y $and$ls180.v:5992$1349_Y + connect \B $not$ls180.v:6044$1414_Y + connect \Y $and$ls180.v:6044$1415_Y end - attribute \src "ls180.v:5992.38-5992.145" - cell $and $and$ls180.v:5992$1351 + attribute \src "ls180.v:6044.38-6044.145" + cell $and $and$ls180.v:6044$1417 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5992$1349_Y - connect \B $eq$ls180.v:5992$1350_Y - connect \Y $and$ls180.v:5992$1351_Y + connect \A $and$ls180.v:6044$1415_Y + connect \B $eq$ls180.v:6044$1416_Y + connect \Y $and$ls180.v:6044$1417_Y end - attribute \src "ls180.v:5994.39-5994.92" - cell $and $and$ls180.v:5994$1352 + attribute \src "ls180.v:6046.39-6046.92" + cell $and $and$ls180.v:6046$1418 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241426,43 +242294,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5994$1352_Y + connect \Y $and$ls180.v:6046$1418_Y end - attribute \src "ls180.v:5994.38-5994.142" - cell $and $and$ls180.v:5994$1354 + attribute \src "ls180.v:6046.38-6046.142" + cell $and $and$ls180.v:6046$1420 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5994$1352_Y - connect \B $eq$ls180.v:5994$1353_Y - connect \Y $and$ls180.v:5994$1354_Y + connect \A $and$ls180.v:6046$1418_Y + connect \B $eq$ls180.v:6046$1419_Y + connect \Y $and$ls180.v:6046$1420_Y end - attribute \src "ls180.v:5995.39-5995.95" - cell $and $and$ls180.v:5995$1356 + attribute \src "ls180.v:6047.39-6047.95" + cell $and $and$ls180.v:6047$1422 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5995$1355_Y - connect \Y $and$ls180.v:5995$1356_Y + connect \B $not$ls180.v:6047$1421_Y + connect \Y $and$ls180.v:6047$1422_Y end - attribute \src "ls180.v:5995.38-5995.145" - cell $and $and$ls180.v:5995$1358 + attribute \src "ls180.v:6047.38-6047.145" + cell $and $and$ls180.v:6047$1424 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5995$1356_Y - connect \B $eq$ls180.v:5995$1357_Y - connect \Y $and$ls180.v:5995$1358_Y + connect \A $and$ls180.v:6047$1422_Y + connect \B $eq$ls180.v:6047$1423_Y + connect \Y $and$ls180.v:6047$1424_Y end - attribute \src "ls180.v:5997.39-5997.92" - cell $and $and$ls180.v:5997$1359 + attribute \src "ls180.v:6049.39-6049.92" + cell $and $and$ls180.v:6049$1425 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241470,43 +242338,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5997$1359_Y + connect \Y $and$ls180.v:6049$1425_Y end - attribute \src "ls180.v:5997.38-5997.142" - cell $and $and$ls180.v:5997$1361 + attribute \src "ls180.v:6049.38-6049.142" + cell $and $and$ls180.v:6049$1427 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5997$1359_Y - connect \B $eq$ls180.v:5997$1360_Y - connect \Y $and$ls180.v:5997$1361_Y + connect \A $and$ls180.v:6049$1425_Y + connect \B $eq$ls180.v:6049$1426_Y + connect \Y $and$ls180.v:6049$1427_Y end - attribute \src "ls180.v:5998.39-5998.95" - cell $and $and$ls180.v:5998$1363 + attribute \src "ls180.v:6050.39-6050.95" + cell $and $and$ls180.v:6050$1429 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5998$1362_Y - connect \Y $and$ls180.v:5998$1363_Y + connect \B $not$ls180.v:6050$1428_Y + connect \Y $and$ls180.v:6050$1429_Y end - attribute \src "ls180.v:5998.38-5998.145" - cell $and $and$ls180.v:5998$1365 + attribute \src "ls180.v:6050.38-6050.145" + cell $and $and$ls180.v:6050$1431 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5998$1363_Y - connect \B $eq$ls180.v:5998$1364_Y - connect \Y $and$ls180.v:5998$1365_Y + connect \A $and$ls180.v:6050$1429_Y + connect \B $eq$ls180.v:6050$1430_Y + connect \Y $and$ls180.v:6050$1431_Y end - attribute \src "ls180.v:6000.39-6000.92" - cell $and $and$ls180.v:6000$1366 + attribute \src "ls180.v:6052.39-6052.92" + cell $and $and$ls180.v:6052$1432 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241514,43 +242382,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:6000$1366_Y + connect \Y $and$ls180.v:6052$1432_Y end - attribute \src "ls180.v:6000.38-6000.142" - cell $and $and$ls180.v:6000$1368 + attribute \src "ls180.v:6052.38-6052.142" + cell $and $and$ls180.v:6052$1434 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6000$1366_Y - connect \B $eq$ls180.v:6000$1367_Y - connect \Y $and$ls180.v:6000$1368_Y + connect \A $and$ls180.v:6052$1432_Y + connect \B $eq$ls180.v:6052$1433_Y + connect \Y $and$ls180.v:6052$1434_Y end - attribute \src "ls180.v:6001.39-6001.95" - cell $and $and$ls180.v:6001$1370 + attribute \src "ls180.v:6053.39-6053.95" + cell $and $and$ls180.v:6053$1436 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:6001$1369_Y - connect \Y $and$ls180.v:6001$1370_Y + connect \B $not$ls180.v:6053$1435_Y + connect \Y $and$ls180.v:6053$1436_Y end - attribute \src "ls180.v:6001.38-6001.145" - cell $and $and$ls180.v:6001$1372 + attribute \src "ls180.v:6053.38-6053.145" + cell $and $and$ls180.v:6053$1438 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6001$1370_Y - connect \B $eq$ls180.v:6001$1371_Y - connect \Y $and$ls180.v:6001$1372_Y + connect \A $and$ls180.v:6053$1436_Y + connect \B $eq$ls180.v:6053$1437_Y + connect \Y $and$ls180.v:6053$1438_Y end - attribute \src "ls180.v:6003.40-6003.93" - cell $and $and$ls180.v:6003$1373 + attribute \src "ls180.v:6055.40-6055.93" + cell $and $and$ls180.v:6055$1439 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241558,43 +242426,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:6003$1373_Y + connect \Y $and$ls180.v:6055$1439_Y end - attribute \src "ls180.v:6003.39-6003.143" - cell $and $and$ls180.v:6003$1375 + attribute \src "ls180.v:6055.39-6055.143" + cell $and $and$ls180.v:6055$1441 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6003$1373_Y - connect \B $eq$ls180.v:6003$1374_Y - connect \Y $and$ls180.v:6003$1375_Y + connect \A $and$ls180.v:6055$1439_Y + connect \B $eq$ls180.v:6055$1440_Y + connect \Y $and$ls180.v:6055$1441_Y end - attribute \src "ls180.v:6004.40-6004.96" - cell $and $and$ls180.v:6004$1377 + attribute \src "ls180.v:6056.40-6056.96" + cell $and $and$ls180.v:6056$1443 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:6004$1376_Y - connect \Y $and$ls180.v:6004$1377_Y + connect \B $not$ls180.v:6056$1442_Y + connect \Y $and$ls180.v:6056$1443_Y end - attribute \src "ls180.v:6004.39-6004.146" - cell $and $and$ls180.v:6004$1379 + attribute \src "ls180.v:6056.39-6056.146" + cell $and $and$ls180.v:6056$1445 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6004$1377_Y - connect \B $eq$ls180.v:6004$1378_Y - connect \Y $and$ls180.v:6004$1379_Y + connect \A $and$ls180.v:6056$1443_Y + connect \B $eq$ls180.v:6056$1444_Y + connect \Y $and$ls180.v:6056$1445_Y end - attribute \src "ls180.v:6006.40-6006.93" - cell $and $and$ls180.v:6006$1380 + attribute \src "ls180.v:6058.40-6058.93" + cell $and $and$ls180.v:6058$1446 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241602,43 +242470,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:6006$1380_Y + connect \Y $and$ls180.v:6058$1446_Y end - attribute \src "ls180.v:6006.39-6006.143" - cell $and $and$ls180.v:6006$1382 + attribute \src "ls180.v:6058.39-6058.143" + cell $and $and$ls180.v:6058$1448 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6006$1380_Y - connect \B $eq$ls180.v:6006$1381_Y - connect \Y $and$ls180.v:6006$1382_Y + connect \A $and$ls180.v:6058$1446_Y + connect \B $eq$ls180.v:6058$1447_Y + connect \Y $and$ls180.v:6058$1448_Y end - attribute \src "ls180.v:6007.40-6007.96" - cell $and $and$ls180.v:6007$1384 + attribute \src "ls180.v:6059.40-6059.96" + cell $and $and$ls180.v:6059$1450 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:6007$1383_Y - connect \Y $and$ls180.v:6007$1384_Y + connect \B $not$ls180.v:6059$1449_Y + connect \Y $and$ls180.v:6059$1450_Y end - attribute \src "ls180.v:6007.39-6007.146" - cell $and $and$ls180.v:6007$1386 + attribute \src "ls180.v:6059.39-6059.146" + cell $and $and$ls180.v:6059$1452 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6007$1384_Y - connect \B $eq$ls180.v:6007$1385_Y - connect \Y $and$ls180.v:6007$1386_Y + connect \A $and$ls180.v:6059$1450_Y + connect \B $eq$ls180.v:6059$1451_Y + connect \Y $and$ls180.v:6059$1452_Y end - attribute \src "ls180.v:6009.40-6009.93" - cell $and $and$ls180.v:6009$1387 + attribute \src "ls180.v:6061.40-6061.93" + cell $and $and$ls180.v:6061$1453 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241646,43 +242514,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:6009$1387_Y + connect \Y $and$ls180.v:6061$1453_Y end - attribute \src "ls180.v:6009.39-6009.143" - cell $and $and$ls180.v:6009$1389 + attribute \src "ls180.v:6061.39-6061.143" + cell $and $and$ls180.v:6061$1455 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6009$1387_Y - connect \B $eq$ls180.v:6009$1388_Y - connect \Y $and$ls180.v:6009$1389_Y + connect \A $and$ls180.v:6061$1453_Y + connect \B $eq$ls180.v:6061$1454_Y + connect \Y $and$ls180.v:6061$1455_Y end - attribute \src "ls180.v:6010.40-6010.96" - cell $and $and$ls180.v:6010$1391 + attribute \src "ls180.v:6062.40-6062.96" + cell $and $and$ls180.v:6062$1457 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:6010$1390_Y - connect \Y $and$ls180.v:6010$1391_Y + connect \B $not$ls180.v:6062$1456_Y + connect \Y $and$ls180.v:6062$1457_Y end - attribute \src "ls180.v:6010.39-6010.146" - cell $and $and$ls180.v:6010$1393 + attribute \src "ls180.v:6062.39-6062.146" + cell $and $and$ls180.v:6062$1459 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6010$1391_Y - connect \B $eq$ls180.v:6010$1392_Y - connect \Y $and$ls180.v:6010$1393_Y + connect \A $and$ls180.v:6062$1457_Y + connect \B $eq$ls180.v:6062$1458_Y + connect \Y $and$ls180.v:6062$1459_Y end - attribute \src "ls180.v:6012.40-6012.93" - cell $and $and$ls180.v:6012$1394 + attribute \src "ls180.v:6064.40-6064.93" + cell $and $and$ls180.v:6064$1460 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241690,43 +242558,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:6012$1394_Y + connect \Y $and$ls180.v:6064$1460_Y end - attribute \src "ls180.v:6012.39-6012.143" - cell $and $and$ls180.v:6012$1396 + attribute \src "ls180.v:6064.39-6064.143" + cell $and $and$ls180.v:6064$1462 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6012$1394_Y - connect \B $eq$ls180.v:6012$1395_Y - connect \Y $and$ls180.v:6012$1396_Y + connect \A $and$ls180.v:6064$1460_Y + connect \B $eq$ls180.v:6064$1461_Y + connect \Y $and$ls180.v:6064$1462_Y end - attribute \src "ls180.v:6013.40-6013.96" - cell $and $and$ls180.v:6013$1398 + attribute \src "ls180.v:6065.40-6065.96" + cell $and $and$ls180.v:6065$1464 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:6013$1397_Y - connect \Y $and$ls180.v:6013$1398_Y + connect \B $not$ls180.v:6065$1463_Y + connect \Y $and$ls180.v:6065$1464_Y end - attribute \src "ls180.v:6013.39-6013.146" - cell $and $and$ls180.v:6013$1400 + attribute \src "ls180.v:6065.39-6065.146" + cell $and $and$ls180.v:6065$1466 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6013$1398_Y - connect \B $eq$ls180.v:6013$1399_Y - connect \Y $and$ls180.v:6013$1400_Y + connect \A $and$ls180.v:6065$1464_Y + connect \B $eq$ls180.v:6065$1465_Y + connect \Y $and$ls180.v:6065$1466_Y end - attribute \src "ls180.v:6025.42-6025.95" - cell $and $and$ls180.v:6025$1402 + attribute \src "ls180.v:6077.42-6077.95" + cell $and $and$ls180.v:6077$1468 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241734,43 +242602,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6025$1402_Y + connect \Y $and$ls180.v:6077$1468_Y end - attribute \src "ls180.v:6025.41-6025.145" - cell $and $and$ls180.v:6025$1404 + attribute \src "ls180.v:6077.41-6077.145" + cell $and $and$ls180.v:6077$1470 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6025$1402_Y - connect \B $eq$ls180.v:6025$1403_Y - connect \Y $and$ls180.v:6025$1404_Y + connect \A $and$ls180.v:6077$1468_Y + connect \B $eq$ls180.v:6077$1469_Y + connect \Y $and$ls180.v:6077$1470_Y end - attribute \src "ls180.v:6026.42-6026.98" - cell $and $and$ls180.v:6026$1406 + attribute \src "ls180.v:6078.42-6078.98" + cell $and $and$ls180.v:6078$1472 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6026$1405_Y - connect \Y $and$ls180.v:6026$1406_Y + connect \B $not$ls180.v:6078$1471_Y + connect \Y $and$ls180.v:6078$1472_Y end - attribute \src "ls180.v:6026.41-6026.148" - cell $and $and$ls180.v:6026$1408 + attribute \src "ls180.v:6078.41-6078.148" + cell $and $and$ls180.v:6078$1474 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6026$1406_Y - connect \B $eq$ls180.v:6026$1407_Y - connect \Y $and$ls180.v:6026$1408_Y + connect \A $and$ls180.v:6078$1472_Y + connect \B $eq$ls180.v:6078$1473_Y + connect \Y $and$ls180.v:6078$1474_Y end - attribute \src "ls180.v:6028.42-6028.95" - cell $and $and$ls180.v:6028$1409 + attribute \src "ls180.v:6080.42-6080.95" + cell $and $and$ls180.v:6080$1475 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241778,43 +242646,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6028$1409_Y + connect \Y $and$ls180.v:6080$1475_Y end - attribute \src "ls180.v:6028.41-6028.145" - cell $and $and$ls180.v:6028$1411 + attribute \src "ls180.v:6080.41-6080.145" + cell $and $and$ls180.v:6080$1477 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6028$1409_Y - connect \B $eq$ls180.v:6028$1410_Y - connect \Y $and$ls180.v:6028$1411_Y + connect \A $and$ls180.v:6080$1475_Y + connect \B $eq$ls180.v:6080$1476_Y + connect \Y $and$ls180.v:6080$1477_Y end - attribute \src "ls180.v:6029.42-6029.98" - cell $and $and$ls180.v:6029$1413 + attribute \src "ls180.v:6081.42-6081.98" + cell $and $and$ls180.v:6081$1479 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6029$1412_Y - connect \Y $and$ls180.v:6029$1413_Y + connect \B $not$ls180.v:6081$1478_Y + connect \Y $and$ls180.v:6081$1479_Y end - attribute \src "ls180.v:6029.41-6029.148" - cell $and $and$ls180.v:6029$1415 + attribute \src "ls180.v:6081.41-6081.148" + cell $and $and$ls180.v:6081$1481 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6029$1413_Y - connect \B $eq$ls180.v:6029$1414_Y - connect \Y $and$ls180.v:6029$1415_Y + connect \A $and$ls180.v:6081$1479_Y + connect \B $eq$ls180.v:6081$1480_Y + connect \Y $and$ls180.v:6081$1481_Y end - attribute \src "ls180.v:6031.42-6031.95" - cell $and $and$ls180.v:6031$1416 + attribute \src "ls180.v:6083.42-6083.95" + cell $and $and$ls180.v:6083$1482 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241822,43 +242690,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6031$1416_Y + connect \Y $and$ls180.v:6083$1482_Y end - attribute \src "ls180.v:6031.41-6031.145" - cell $and $and$ls180.v:6031$1418 + attribute \src "ls180.v:6083.41-6083.145" + cell $and $and$ls180.v:6083$1484 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6031$1416_Y - connect \B $eq$ls180.v:6031$1417_Y - connect \Y $and$ls180.v:6031$1418_Y + connect \A $and$ls180.v:6083$1482_Y + connect \B $eq$ls180.v:6083$1483_Y + connect \Y $and$ls180.v:6083$1484_Y end - attribute \src "ls180.v:6032.42-6032.98" - cell $and $and$ls180.v:6032$1420 + attribute \src "ls180.v:6084.42-6084.98" + cell $and $and$ls180.v:6084$1486 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6032$1419_Y - connect \Y $and$ls180.v:6032$1420_Y + connect \B $not$ls180.v:6084$1485_Y + connect \Y $and$ls180.v:6084$1486_Y end - attribute \src "ls180.v:6032.41-6032.148" - cell $and $and$ls180.v:6032$1422 + attribute \src "ls180.v:6084.41-6084.148" + cell $and $and$ls180.v:6084$1488 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6032$1420_Y - connect \B $eq$ls180.v:6032$1421_Y - connect \Y $and$ls180.v:6032$1422_Y + connect \A $and$ls180.v:6084$1486_Y + connect \B $eq$ls180.v:6084$1487_Y + connect \Y $and$ls180.v:6084$1488_Y end - attribute \src "ls180.v:6034.42-6034.95" - cell $and $and$ls180.v:6034$1423 + attribute \src "ls180.v:6086.42-6086.95" + cell $and $and$ls180.v:6086$1489 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241866,43 +242734,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6034$1423_Y + connect \Y $and$ls180.v:6086$1489_Y end - attribute \src "ls180.v:6034.41-6034.145" - cell $and $and$ls180.v:6034$1425 + attribute \src "ls180.v:6086.41-6086.145" + cell $and $and$ls180.v:6086$1491 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6034$1423_Y - connect \B $eq$ls180.v:6034$1424_Y - connect \Y $and$ls180.v:6034$1425_Y + connect \A $and$ls180.v:6086$1489_Y + connect \B $eq$ls180.v:6086$1490_Y + connect \Y $and$ls180.v:6086$1491_Y end - attribute \src "ls180.v:6035.42-6035.98" - cell $and $and$ls180.v:6035$1427 + attribute \src "ls180.v:6087.42-6087.98" + cell $and $and$ls180.v:6087$1493 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6035$1426_Y - connect \Y $and$ls180.v:6035$1427_Y + connect \B $not$ls180.v:6087$1492_Y + connect \Y $and$ls180.v:6087$1493_Y end - attribute \src "ls180.v:6035.41-6035.148" - cell $and $and$ls180.v:6035$1429 + attribute \src "ls180.v:6087.41-6087.148" + cell $and $and$ls180.v:6087$1495 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6035$1427_Y - connect \B $eq$ls180.v:6035$1428_Y - connect \Y $and$ls180.v:6035$1429_Y + connect \A $and$ls180.v:6087$1493_Y + connect \B $eq$ls180.v:6087$1494_Y + connect \Y $and$ls180.v:6087$1495_Y end - attribute \src "ls180.v:6037.42-6037.95" - cell $and $and$ls180.v:6037$1430 + attribute \src "ls180.v:6089.42-6089.95" + cell $and $and$ls180.v:6089$1496 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241910,43 +242778,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6037$1430_Y + connect \Y $and$ls180.v:6089$1496_Y end - attribute \src "ls180.v:6037.41-6037.145" - cell $and $and$ls180.v:6037$1432 + attribute \src "ls180.v:6089.41-6089.145" + cell $and $and$ls180.v:6089$1498 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6037$1430_Y - connect \B $eq$ls180.v:6037$1431_Y - connect \Y $and$ls180.v:6037$1432_Y + connect \A $and$ls180.v:6089$1496_Y + connect \B $eq$ls180.v:6089$1497_Y + connect \Y $and$ls180.v:6089$1498_Y end - attribute \src "ls180.v:6038.42-6038.98" - cell $and $and$ls180.v:6038$1434 + attribute \src "ls180.v:6090.42-6090.98" + cell $and $and$ls180.v:6090$1500 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6038$1433_Y - connect \Y $and$ls180.v:6038$1434_Y + connect \B $not$ls180.v:6090$1499_Y + connect \Y $and$ls180.v:6090$1500_Y end - attribute \src "ls180.v:6038.41-6038.148" - cell $and $and$ls180.v:6038$1436 + attribute \src "ls180.v:6090.41-6090.148" + cell $and $and$ls180.v:6090$1502 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6038$1434_Y - connect \B $eq$ls180.v:6038$1435_Y - connect \Y $and$ls180.v:6038$1436_Y + connect \A $and$ls180.v:6090$1500_Y + connect \B $eq$ls180.v:6090$1501_Y + connect \Y $and$ls180.v:6090$1502_Y end - attribute \src "ls180.v:6040.42-6040.95" - cell $and $and$ls180.v:6040$1437 + attribute \src "ls180.v:6092.42-6092.95" + cell $and $and$ls180.v:6092$1503 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241954,43 +242822,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6040$1437_Y + connect \Y $and$ls180.v:6092$1503_Y end - attribute \src "ls180.v:6040.41-6040.145" - cell $and $and$ls180.v:6040$1439 + attribute \src "ls180.v:6092.41-6092.145" + cell $and $and$ls180.v:6092$1505 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6040$1437_Y - connect \B $eq$ls180.v:6040$1438_Y - connect \Y $and$ls180.v:6040$1439_Y + connect \A $and$ls180.v:6092$1503_Y + connect \B $eq$ls180.v:6092$1504_Y + connect \Y $and$ls180.v:6092$1505_Y end - attribute \src "ls180.v:6041.42-6041.98" - cell $and $and$ls180.v:6041$1441 + attribute \src "ls180.v:6093.42-6093.98" + cell $and $and$ls180.v:6093$1507 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6041$1440_Y - connect \Y $and$ls180.v:6041$1441_Y + connect \B $not$ls180.v:6093$1506_Y + connect \Y $and$ls180.v:6093$1507_Y end - attribute \src "ls180.v:6041.41-6041.148" - cell $and $and$ls180.v:6041$1443 + attribute \src "ls180.v:6093.41-6093.148" + cell $and $and$ls180.v:6093$1509 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6041$1441_Y - connect \B $eq$ls180.v:6041$1442_Y - connect \Y $and$ls180.v:6041$1443_Y + connect \A $and$ls180.v:6093$1507_Y + connect \B $eq$ls180.v:6093$1508_Y + connect \Y $and$ls180.v:6093$1509_Y end - attribute \src "ls180.v:6043.42-6043.95" - cell $and $and$ls180.v:6043$1444 + attribute \src "ls180.v:6095.42-6095.95" + cell $and $and$ls180.v:6095$1510 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241998,43 +242866,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6043$1444_Y + connect \Y $and$ls180.v:6095$1510_Y end - attribute \src "ls180.v:6043.41-6043.145" - cell $and $and$ls180.v:6043$1446 + attribute \src "ls180.v:6095.41-6095.145" + cell $and $and$ls180.v:6095$1512 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6043$1444_Y - connect \B $eq$ls180.v:6043$1445_Y - connect \Y $and$ls180.v:6043$1446_Y + connect \A $and$ls180.v:6095$1510_Y + connect \B $eq$ls180.v:6095$1511_Y + connect \Y $and$ls180.v:6095$1512_Y end - attribute \src "ls180.v:6044.42-6044.98" - cell $and $and$ls180.v:6044$1448 + attribute \src "ls180.v:6096.42-6096.98" + cell $and $and$ls180.v:6096$1514 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6044$1447_Y - connect \Y $and$ls180.v:6044$1448_Y + connect \B $not$ls180.v:6096$1513_Y + connect \Y $and$ls180.v:6096$1514_Y end - attribute \src "ls180.v:6044.41-6044.148" - cell $and $and$ls180.v:6044$1450 + attribute \src "ls180.v:6096.41-6096.148" + cell $and $and$ls180.v:6096$1516 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6044$1448_Y - connect \B $eq$ls180.v:6044$1449_Y - connect \Y $and$ls180.v:6044$1450_Y + connect \A $and$ls180.v:6096$1514_Y + connect \B $eq$ls180.v:6096$1515_Y + connect \Y $and$ls180.v:6096$1516_Y end - attribute \src "ls180.v:6046.42-6046.95" - cell $and $and$ls180.v:6046$1451 + attribute \src "ls180.v:6098.42-6098.95" + cell $and $and$ls180.v:6098$1517 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242042,43 +242910,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6046$1451_Y + connect \Y $and$ls180.v:6098$1517_Y end - attribute \src "ls180.v:6046.41-6046.145" - cell $and $and$ls180.v:6046$1453 + attribute \src "ls180.v:6098.41-6098.145" + cell $and $and$ls180.v:6098$1519 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6046$1451_Y - connect \B $eq$ls180.v:6046$1452_Y - connect \Y $and$ls180.v:6046$1453_Y + connect \A $and$ls180.v:6098$1517_Y + connect \B $eq$ls180.v:6098$1518_Y + connect \Y $and$ls180.v:6098$1519_Y end - attribute \src "ls180.v:6047.42-6047.98" - cell $and $and$ls180.v:6047$1455 + attribute \src "ls180.v:6099.42-6099.98" + cell $and $and$ls180.v:6099$1521 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6047$1454_Y - connect \Y $and$ls180.v:6047$1455_Y + connect \B $not$ls180.v:6099$1520_Y + connect \Y $and$ls180.v:6099$1521_Y end - attribute \src "ls180.v:6047.41-6047.148" - cell $and $and$ls180.v:6047$1457 + attribute \src "ls180.v:6099.41-6099.148" + cell $and $and$ls180.v:6099$1523 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6047$1455_Y - connect \B $eq$ls180.v:6047$1456_Y - connect \Y $and$ls180.v:6047$1457_Y + connect \A $and$ls180.v:6099$1521_Y + connect \B $eq$ls180.v:6099$1522_Y + connect \Y $and$ls180.v:6099$1523_Y end - attribute \src "ls180.v:6049.44-6049.97" - cell $and $and$ls180.v:6049$1458 + attribute \src "ls180.v:6101.44-6101.97" + cell $and $and$ls180.v:6101$1524 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242086,43 +242954,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6049$1458_Y + connect \Y $and$ls180.v:6101$1524_Y end - attribute \src "ls180.v:6049.43-6049.147" - cell $and $and$ls180.v:6049$1460 + attribute \src "ls180.v:6101.43-6101.147" + cell $and $and$ls180.v:6101$1526 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6049$1458_Y - connect \B $eq$ls180.v:6049$1459_Y - connect \Y $and$ls180.v:6049$1460_Y + connect \A $and$ls180.v:6101$1524_Y + connect \B $eq$ls180.v:6101$1525_Y + connect \Y $and$ls180.v:6101$1526_Y end - attribute \src "ls180.v:6050.44-6050.100" - cell $and $and$ls180.v:6050$1462 + attribute \src "ls180.v:6102.44-6102.100" + cell $and $and$ls180.v:6102$1528 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6050$1461_Y - connect \Y $and$ls180.v:6050$1462_Y + connect \B $not$ls180.v:6102$1527_Y + connect \Y $and$ls180.v:6102$1528_Y end - attribute \src "ls180.v:6050.43-6050.150" - cell $and $and$ls180.v:6050$1464 + attribute \src "ls180.v:6102.43-6102.150" + cell $and $and$ls180.v:6102$1530 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6050$1462_Y - connect \B $eq$ls180.v:6050$1463_Y - connect \Y $and$ls180.v:6050$1464_Y + connect \A $and$ls180.v:6102$1528_Y + connect \B $eq$ls180.v:6102$1529_Y + connect \Y $and$ls180.v:6102$1530_Y end - attribute \src "ls180.v:6052.44-6052.97" - cell $and $and$ls180.v:6052$1465 + attribute \src "ls180.v:6104.44-6104.97" + cell $and $and$ls180.v:6104$1531 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242130,43 +242998,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6052$1465_Y + connect \Y $and$ls180.v:6104$1531_Y end - attribute \src "ls180.v:6052.43-6052.147" - cell $and $and$ls180.v:6052$1467 + attribute \src "ls180.v:6104.43-6104.147" + cell $and $and$ls180.v:6104$1533 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6052$1465_Y - connect \B $eq$ls180.v:6052$1466_Y - connect \Y $and$ls180.v:6052$1467_Y + connect \A $and$ls180.v:6104$1531_Y + connect \B $eq$ls180.v:6104$1532_Y + connect \Y $and$ls180.v:6104$1533_Y end - attribute \src "ls180.v:6053.44-6053.100" - cell $and $and$ls180.v:6053$1469 + attribute \src "ls180.v:6105.44-6105.100" + cell $and $and$ls180.v:6105$1535 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6053$1468_Y - connect \Y $and$ls180.v:6053$1469_Y + connect \B $not$ls180.v:6105$1534_Y + connect \Y $and$ls180.v:6105$1535_Y end - attribute \src "ls180.v:6053.43-6053.150" - cell $and $and$ls180.v:6053$1471 + attribute \src "ls180.v:6105.43-6105.150" + cell $and $and$ls180.v:6105$1537 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6053$1469_Y - connect \B $eq$ls180.v:6053$1470_Y - connect \Y $and$ls180.v:6053$1471_Y + connect \A $and$ls180.v:6105$1535_Y + connect \B $eq$ls180.v:6105$1536_Y + connect \Y $and$ls180.v:6105$1537_Y end - attribute \src "ls180.v:6055.44-6055.97" - cell $and $and$ls180.v:6055$1472 + attribute \src "ls180.v:6107.44-6107.97" + cell $and $and$ls180.v:6107$1538 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242174,43 +243042,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6055$1472_Y + connect \Y $and$ls180.v:6107$1538_Y end - attribute \src "ls180.v:6055.43-6055.148" - cell $and $and$ls180.v:6055$1474 + attribute \src "ls180.v:6107.43-6107.148" + cell $and $and$ls180.v:6107$1540 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6055$1472_Y - connect \B $eq$ls180.v:6055$1473_Y - connect \Y $and$ls180.v:6055$1474_Y + connect \A $and$ls180.v:6107$1538_Y + connect \B $eq$ls180.v:6107$1539_Y + connect \Y $and$ls180.v:6107$1540_Y end - attribute \src "ls180.v:6056.44-6056.100" - cell $and $and$ls180.v:6056$1476 + attribute \src "ls180.v:6108.44-6108.100" + cell $and $and$ls180.v:6108$1542 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6056$1475_Y - connect \Y $and$ls180.v:6056$1476_Y + connect \B $not$ls180.v:6108$1541_Y + connect \Y $and$ls180.v:6108$1542_Y end - attribute \src "ls180.v:6056.43-6056.151" - cell $and $and$ls180.v:6056$1478 + attribute \src "ls180.v:6108.43-6108.151" + cell $and $and$ls180.v:6108$1544 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6056$1476_Y - connect \B $eq$ls180.v:6056$1477_Y - connect \Y $and$ls180.v:6056$1478_Y + connect \A $and$ls180.v:6108$1542_Y + connect \B $eq$ls180.v:6108$1543_Y + connect \Y $and$ls180.v:6108$1544_Y end - attribute \src "ls180.v:6058.44-6058.97" - cell $and $and$ls180.v:6058$1479 + attribute \src "ls180.v:6110.44-6110.97" + cell $and $and$ls180.v:6110$1545 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242218,43 +243086,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6058$1479_Y + connect \Y $and$ls180.v:6110$1545_Y end - attribute \src "ls180.v:6058.43-6058.148" - cell $and $and$ls180.v:6058$1481 + attribute \src "ls180.v:6110.43-6110.148" + cell $and $and$ls180.v:6110$1547 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6058$1479_Y - connect \B $eq$ls180.v:6058$1480_Y - connect \Y $and$ls180.v:6058$1481_Y + connect \A $and$ls180.v:6110$1545_Y + connect \B $eq$ls180.v:6110$1546_Y + connect \Y $and$ls180.v:6110$1547_Y end - attribute \src "ls180.v:6059.44-6059.100" - cell $and $and$ls180.v:6059$1483 + attribute \src "ls180.v:6111.44-6111.100" + cell $and $and$ls180.v:6111$1549 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6059$1482_Y - connect \Y $and$ls180.v:6059$1483_Y + connect \B $not$ls180.v:6111$1548_Y + connect \Y $and$ls180.v:6111$1549_Y end - attribute \src "ls180.v:6059.43-6059.151" - cell $and $and$ls180.v:6059$1485 + attribute \src "ls180.v:6111.43-6111.151" + cell $and $and$ls180.v:6111$1551 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6059$1483_Y - connect \B $eq$ls180.v:6059$1484_Y - connect \Y $and$ls180.v:6059$1485_Y + connect \A $and$ls180.v:6111$1549_Y + connect \B $eq$ls180.v:6111$1550_Y + connect \Y $and$ls180.v:6111$1551_Y end - attribute \src "ls180.v:6061.44-6061.97" - cell $and $and$ls180.v:6061$1486 + attribute \src "ls180.v:6113.44-6113.97" + cell $and $and$ls180.v:6113$1552 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242262,43 +243130,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6061$1486_Y + connect \Y $and$ls180.v:6113$1552_Y end - attribute \src "ls180.v:6061.43-6061.148" - cell $and $and$ls180.v:6061$1488 + attribute \src "ls180.v:6113.43-6113.148" + cell $and $and$ls180.v:6113$1554 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6061$1486_Y - connect \B $eq$ls180.v:6061$1487_Y - connect \Y $and$ls180.v:6061$1488_Y + connect \A $and$ls180.v:6113$1552_Y + connect \B $eq$ls180.v:6113$1553_Y + connect \Y $and$ls180.v:6113$1554_Y end - attribute \src "ls180.v:6062.44-6062.100" - cell $and $and$ls180.v:6062$1490 + attribute \src "ls180.v:6114.44-6114.100" + cell $and $and$ls180.v:6114$1556 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6062$1489_Y - connect \Y $and$ls180.v:6062$1490_Y + connect \B $not$ls180.v:6114$1555_Y + connect \Y $and$ls180.v:6114$1556_Y end - attribute \src "ls180.v:6062.43-6062.151" - cell $and $and$ls180.v:6062$1492 + attribute \src "ls180.v:6114.43-6114.151" + cell $and $and$ls180.v:6114$1558 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6062$1490_Y - connect \B $eq$ls180.v:6062$1491_Y - connect \Y $and$ls180.v:6062$1492_Y + connect \A $and$ls180.v:6114$1556_Y + connect \B $eq$ls180.v:6114$1557_Y + connect \Y $and$ls180.v:6114$1558_Y end - attribute \src "ls180.v:6064.41-6064.94" - cell $and $and$ls180.v:6064$1493 + attribute \src "ls180.v:6116.41-6116.94" + cell $and $and$ls180.v:6116$1559 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242306,43 +243174,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6064$1493_Y + connect \Y $and$ls180.v:6116$1559_Y end - attribute \src "ls180.v:6064.40-6064.145" - cell $and $and$ls180.v:6064$1495 + attribute \src "ls180.v:6116.40-6116.145" + cell $and $and$ls180.v:6116$1561 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6064$1493_Y - connect \B $eq$ls180.v:6064$1494_Y - connect \Y $and$ls180.v:6064$1495_Y + connect \A $and$ls180.v:6116$1559_Y + connect \B $eq$ls180.v:6116$1560_Y + connect \Y $and$ls180.v:6116$1561_Y end - attribute \src "ls180.v:6065.41-6065.97" - cell $and $and$ls180.v:6065$1497 + attribute \src "ls180.v:6117.41-6117.97" + cell $and $and$ls180.v:6117$1563 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6065$1496_Y - connect \Y $and$ls180.v:6065$1497_Y + connect \B $not$ls180.v:6117$1562_Y + connect \Y $and$ls180.v:6117$1563_Y end - attribute \src "ls180.v:6065.40-6065.148" - cell $and $and$ls180.v:6065$1499 + attribute \src "ls180.v:6117.40-6117.148" + cell $and $and$ls180.v:6117$1565 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6065$1497_Y - connect \B $eq$ls180.v:6065$1498_Y - connect \Y $and$ls180.v:6065$1499_Y + connect \A $and$ls180.v:6117$1563_Y + connect \B $eq$ls180.v:6117$1564_Y + connect \Y $and$ls180.v:6117$1565_Y end - attribute \src "ls180.v:6067.42-6067.95" - cell $and $and$ls180.v:6067$1500 + attribute \src "ls180.v:6119.42-6119.95" + cell $and $and$ls180.v:6119$1566 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242350,43 +243218,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6067$1500_Y + connect \Y $and$ls180.v:6119$1566_Y end - attribute \src "ls180.v:6067.41-6067.146" - cell $and $and$ls180.v:6067$1502 + attribute \src "ls180.v:6119.41-6119.146" + cell $and $and$ls180.v:6119$1568 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6067$1500_Y - connect \B $eq$ls180.v:6067$1501_Y - connect \Y $and$ls180.v:6067$1502_Y + connect \A $and$ls180.v:6119$1566_Y + connect \B $eq$ls180.v:6119$1567_Y + connect \Y $and$ls180.v:6119$1568_Y end - attribute \src "ls180.v:6068.42-6068.98" - cell $and $and$ls180.v:6068$1504 + attribute \src "ls180.v:6120.42-6120.98" + cell $and $and$ls180.v:6120$1570 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6068$1503_Y - connect \Y $and$ls180.v:6068$1504_Y + connect \B $not$ls180.v:6120$1569_Y + connect \Y $and$ls180.v:6120$1570_Y end - attribute \src "ls180.v:6068.41-6068.149" - cell $and $and$ls180.v:6068$1506 + attribute \src "ls180.v:6120.41-6120.149" + cell $and $and$ls180.v:6120$1572 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6068$1504_Y - connect \B $eq$ls180.v:6068$1505_Y - connect \Y $and$ls180.v:6068$1506_Y + connect \A $and$ls180.v:6120$1570_Y + connect \B $eq$ls180.v:6120$1571_Y + connect \Y $and$ls180.v:6120$1572_Y end - attribute \src "ls180.v:6087.46-6087.99" - cell $and $and$ls180.v:6087$1508 + attribute \src "ls180.v:6139.46-6139.99" + cell $and $and$ls180.v:6139$1574 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242394,43 +243262,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6087$1508_Y + connect \Y $and$ls180.v:6139$1574_Y end - attribute \src "ls180.v:6087.45-6087.149" - cell $and $and$ls180.v:6087$1510 + attribute \src "ls180.v:6139.45-6139.149" + cell $and $and$ls180.v:6139$1576 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6087$1508_Y - connect \B $eq$ls180.v:6087$1509_Y - connect \Y $and$ls180.v:6087$1510_Y + connect \A $and$ls180.v:6139$1574_Y + connect \B $eq$ls180.v:6139$1575_Y + connect \Y $and$ls180.v:6139$1576_Y end - attribute \src "ls180.v:6088.46-6088.102" - cell $and $and$ls180.v:6088$1512 + attribute \src "ls180.v:6140.46-6140.102" + cell $and $and$ls180.v:6140$1578 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6088$1511_Y - connect \Y $and$ls180.v:6088$1512_Y + connect \B $not$ls180.v:6140$1577_Y + connect \Y $and$ls180.v:6140$1578_Y end - attribute \src "ls180.v:6088.45-6088.152" - cell $and $and$ls180.v:6088$1514 + attribute \src "ls180.v:6140.45-6140.152" + cell $and $and$ls180.v:6140$1580 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6088$1512_Y - connect \B $eq$ls180.v:6088$1513_Y - connect \Y $and$ls180.v:6088$1514_Y + connect \A $and$ls180.v:6140$1578_Y + connect \B $eq$ls180.v:6140$1579_Y + connect \Y $and$ls180.v:6140$1580_Y end - attribute \src "ls180.v:6090.46-6090.99" - cell $and $and$ls180.v:6090$1515 + attribute \src "ls180.v:6142.46-6142.99" + cell $and $and$ls180.v:6142$1581 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242438,43 +243306,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6090$1515_Y + connect \Y $and$ls180.v:6142$1581_Y end - attribute \src "ls180.v:6090.45-6090.149" - cell $and $and$ls180.v:6090$1517 + attribute \src "ls180.v:6142.45-6142.149" + cell $and $and$ls180.v:6142$1583 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6090$1515_Y - connect \B $eq$ls180.v:6090$1516_Y - connect \Y $and$ls180.v:6090$1517_Y + connect \A $and$ls180.v:6142$1581_Y + connect \B $eq$ls180.v:6142$1582_Y + connect \Y $and$ls180.v:6142$1583_Y end - attribute \src "ls180.v:6091.46-6091.102" - cell $and $and$ls180.v:6091$1519 + attribute \src "ls180.v:6143.46-6143.102" + cell $and $and$ls180.v:6143$1585 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6091$1518_Y - connect \Y $and$ls180.v:6091$1519_Y + connect \B $not$ls180.v:6143$1584_Y + connect \Y $and$ls180.v:6143$1585_Y end - attribute \src "ls180.v:6091.45-6091.152" - cell $and $and$ls180.v:6091$1521 + attribute \src "ls180.v:6143.45-6143.152" + cell $and $and$ls180.v:6143$1587 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6091$1519_Y - connect \B $eq$ls180.v:6091$1520_Y - connect \Y $and$ls180.v:6091$1521_Y + connect \A $and$ls180.v:6143$1585_Y + connect \B $eq$ls180.v:6143$1586_Y + connect \Y $and$ls180.v:6143$1587_Y end - attribute \src "ls180.v:6093.46-6093.99" - cell $and $and$ls180.v:6093$1522 + attribute \src "ls180.v:6145.46-6145.99" + cell $and $and$ls180.v:6145$1588 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242482,43 +243350,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6093$1522_Y + connect \Y $and$ls180.v:6145$1588_Y end - attribute \src "ls180.v:6093.45-6093.149" - cell $and $and$ls180.v:6093$1524 + attribute \src "ls180.v:6145.45-6145.149" + cell $and $and$ls180.v:6145$1590 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6093$1522_Y - connect \B $eq$ls180.v:6093$1523_Y - connect \Y $and$ls180.v:6093$1524_Y + connect \A $and$ls180.v:6145$1588_Y + connect \B $eq$ls180.v:6145$1589_Y + connect \Y $and$ls180.v:6145$1590_Y end - attribute \src "ls180.v:6094.46-6094.102" - cell $and $and$ls180.v:6094$1526 + attribute \src "ls180.v:6146.46-6146.102" + cell $and $and$ls180.v:6146$1592 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6094$1525_Y - connect \Y $and$ls180.v:6094$1526_Y + connect \B $not$ls180.v:6146$1591_Y + connect \Y $and$ls180.v:6146$1592_Y end - attribute \src "ls180.v:6094.45-6094.152" - cell $and $and$ls180.v:6094$1528 + attribute \src "ls180.v:6146.45-6146.152" + cell $and $and$ls180.v:6146$1594 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6094$1526_Y - connect \B $eq$ls180.v:6094$1527_Y - connect \Y $and$ls180.v:6094$1528_Y + connect \A $and$ls180.v:6146$1592_Y + connect \B $eq$ls180.v:6146$1593_Y + connect \Y $and$ls180.v:6146$1594_Y end - attribute \src "ls180.v:6096.46-6096.99" - cell $and $and$ls180.v:6096$1529 + attribute \src "ls180.v:6148.46-6148.99" + cell $and $and$ls180.v:6148$1595 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242526,43 +243394,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6096$1529_Y + connect \Y $and$ls180.v:6148$1595_Y end - attribute \src "ls180.v:6096.45-6096.149" - cell $and $and$ls180.v:6096$1531 + attribute \src "ls180.v:6148.45-6148.149" + cell $and $and$ls180.v:6148$1597 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6096$1529_Y - connect \B $eq$ls180.v:6096$1530_Y - connect \Y $and$ls180.v:6096$1531_Y + connect \A $and$ls180.v:6148$1595_Y + connect \B $eq$ls180.v:6148$1596_Y + connect \Y $and$ls180.v:6148$1597_Y end - attribute \src "ls180.v:6097.46-6097.102" - cell $and $and$ls180.v:6097$1533 + attribute \src "ls180.v:6149.46-6149.102" + cell $and $and$ls180.v:6149$1599 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6097$1532_Y - connect \Y $and$ls180.v:6097$1533_Y + connect \B $not$ls180.v:6149$1598_Y + connect \Y $and$ls180.v:6149$1599_Y end - attribute \src "ls180.v:6097.45-6097.152" - cell $and $and$ls180.v:6097$1535 + attribute \src "ls180.v:6149.45-6149.152" + cell $and $and$ls180.v:6149$1601 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6097$1533_Y - connect \B $eq$ls180.v:6097$1534_Y - connect \Y $and$ls180.v:6097$1535_Y + connect \A $and$ls180.v:6149$1599_Y + connect \B $eq$ls180.v:6149$1600_Y + connect \Y $and$ls180.v:6149$1601_Y end - attribute \src "ls180.v:6099.45-6099.98" - cell $and $and$ls180.v:6099$1536 + attribute \src "ls180.v:6151.45-6151.98" + cell $and $and$ls180.v:6151$1602 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242570,43 +243438,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6099$1536_Y + connect \Y $and$ls180.v:6151$1602_Y end - attribute \src "ls180.v:6099.44-6099.148" - cell $and $and$ls180.v:6099$1538 + attribute \src "ls180.v:6151.44-6151.148" + cell $and $and$ls180.v:6151$1604 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6099$1536_Y - connect \B $eq$ls180.v:6099$1537_Y - connect \Y $and$ls180.v:6099$1538_Y + connect \A $and$ls180.v:6151$1602_Y + connect \B $eq$ls180.v:6151$1603_Y + connect \Y $and$ls180.v:6151$1604_Y end - attribute \src "ls180.v:6100.45-6100.101" - cell $and $and$ls180.v:6100$1540 + attribute \src "ls180.v:6152.45-6152.101" + cell $and $and$ls180.v:6152$1606 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6100$1539_Y - connect \Y $and$ls180.v:6100$1540_Y + connect \B $not$ls180.v:6152$1605_Y + connect \Y $and$ls180.v:6152$1606_Y end - attribute \src "ls180.v:6100.44-6100.151" - cell $and $and$ls180.v:6100$1542 + attribute \src "ls180.v:6152.44-6152.151" + cell $and $and$ls180.v:6152$1608 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6100$1540_Y - connect \B $eq$ls180.v:6100$1541_Y - connect \Y $and$ls180.v:6100$1542_Y + connect \A $and$ls180.v:6152$1606_Y + connect \B $eq$ls180.v:6152$1607_Y + connect \Y $and$ls180.v:6152$1608_Y end - attribute \src "ls180.v:6102.45-6102.98" - cell $and $and$ls180.v:6102$1543 + attribute \src "ls180.v:6154.45-6154.98" + cell $and $and$ls180.v:6154$1609 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242614,43 +243482,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6102$1543_Y + connect \Y $and$ls180.v:6154$1609_Y end - attribute \src "ls180.v:6102.44-6102.148" - cell $and $and$ls180.v:6102$1545 + attribute \src "ls180.v:6154.44-6154.148" + cell $and $and$ls180.v:6154$1611 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6102$1543_Y - connect \B $eq$ls180.v:6102$1544_Y - connect \Y $and$ls180.v:6102$1545_Y + connect \A $and$ls180.v:6154$1609_Y + connect \B $eq$ls180.v:6154$1610_Y + connect \Y $and$ls180.v:6154$1611_Y end - attribute \src "ls180.v:6103.45-6103.101" - cell $and $and$ls180.v:6103$1547 + attribute \src "ls180.v:6155.45-6155.101" + cell $and $and$ls180.v:6155$1613 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6103$1546_Y - connect \Y $and$ls180.v:6103$1547_Y + connect \B $not$ls180.v:6155$1612_Y + connect \Y $and$ls180.v:6155$1613_Y end - attribute \src "ls180.v:6103.44-6103.151" - cell $and $and$ls180.v:6103$1549 + attribute \src "ls180.v:6155.44-6155.151" + cell $and $and$ls180.v:6155$1615 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6103$1547_Y - connect \B $eq$ls180.v:6103$1548_Y - connect \Y $and$ls180.v:6103$1549_Y + connect \A $and$ls180.v:6155$1613_Y + connect \B $eq$ls180.v:6155$1614_Y + connect \Y $and$ls180.v:6155$1615_Y end - attribute \src "ls180.v:6105.45-6105.98" - cell $and $and$ls180.v:6105$1550 + attribute \src "ls180.v:6157.45-6157.98" + cell $and $and$ls180.v:6157$1616 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242658,43 +243526,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6105$1550_Y + connect \Y $and$ls180.v:6157$1616_Y end - attribute \src "ls180.v:6105.44-6105.148" - cell $and $and$ls180.v:6105$1552 + attribute \src "ls180.v:6157.44-6157.148" + cell $and $and$ls180.v:6157$1618 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6105$1550_Y - connect \B $eq$ls180.v:6105$1551_Y - connect \Y $and$ls180.v:6105$1552_Y + connect \A $and$ls180.v:6157$1616_Y + connect \B $eq$ls180.v:6157$1617_Y + connect \Y $and$ls180.v:6157$1618_Y end - attribute \src "ls180.v:6106.45-6106.101" - cell $and $and$ls180.v:6106$1554 + attribute \src "ls180.v:6158.45-6158.101" + cell $and $and$ls180.v:6158$1620 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6106$1553_Y - connect \Y $and$ls180.v:6106$1554_Y + connect \B $not$ls180.v:6158$1619_Y + connect \Y $and$ls180.v:6158$1620_Y end - attribute \src "ls180.v:6106.44-6106.151" - cell $and $and$ls180.v:6106$1556 + attribute \src "ls180.v:6158.44-6158.151" + cell $and $and$ls180.v:6158$1622 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6106$1554_Y - connect \B $eq$ls180.v:6106$1555_Y - connect \Y $and$ls180.v:6106$1556_Y + connect \A $and$ls180.v:6158$1620_Y + connect \B $eq$ls180.v:6158$1621_Y + connect \Y $and$ls180.v:6158$1622_Y end - attribute \src "ls180.v:6108.45-6108.98" - cell $and $and$ls180.v:6108$1557 + attribute \src "ls180.v:6160.45-6160.98" + cell $and $and$ls180.v:6160$1623 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242702,43 +243570,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6108$1557_Y + connect \Y $and$ls180.v:6160$1623_Y end - attribute \src "ls180.v:6108.44-6108.148" - cell $and $and$ls180.v:6108$1559 + attribute \src "ls180.v:6160.44-6160.148" + cell $and $and$ls180.v:6160$1625 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6108$1557_Y - connect \B $eq$ls180.v:6108$1558_Y - connect \Y $and$ls180.v:6108$1559_Y + connect \A $and$ls180.v:6160$1623_Y + connect \B $eq$ls180.v:6160$1624_Y + connect \Y $and$ls180.v:6160$1625_Y end - attribute \src "ls180.v:6109.45-6109.101" - cell $and $and$ls180.v:6109$1561 + attribute \src "ls180.v:6161.45-6161.101" + cell $and $and$ls180.v:6161$1627 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6109$1560_Y - connect \Y $and$ls180.v:6109$1561_Y + connect \B $not$ls180.v:6161$1626_Y + connect \Y $and$ls180.v:6161$1627_Y end - attribute \src "ls180.v:6109.44-6109.151" - cell $and $and$ls180.v:6109$1563 + attribute \src "ls180.v:6161.44-6161.151" + cell $and $and$ls180.v:6161$1629 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6109$1561_Y - connect \B $eq$ls180.v:6109$1562_Y - connect \Y $and$ls180.v:6109$1563_Y + connect \A $and$ls180.v:6161$1627_Y + connect \B $eq$ls180.v:6161$1628_Y + connect \Y $and$ls180.v:6161$1629_Y end - attribute \src "ls180.v:6111.36-6111.89" - cell $and $and$ls180.v:6111$1564 + attribute \src "ls180.v:6163.36-6163.89" + cell $and $and$ls180.v:6163$1630 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242746,43 +243614,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6111$1564_Y + connect \Y $and$ls180.v:6163$1630_Y end - attribute \src "ls180.v:6111.35-6111.139" - cell $and $and$ls180.v:6111$1566 + attribute \src "ls180.v:6163.35-6163.139" + cell $and $and$ls180.v:6163$1632 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6111$1564_Y - connect \B $eq$ls180.v:6111$1565_Y - connect \Y $and$ls180.v:6111$1566_Y + connect \A $and$ls180.v:6163$1630_Y + connect \B $eq$ls180.v:6163$1631_Y + connect \Y $and$ls180.v:6163$1632_Y end - attribute \src "ls180.v:6112.36-6112.92" - cell $and $and$ls180.v:6112$1568 + attribute \src "ls180.v:6164.36-6164.92" + cell $and $and$ls180.v:6164$1634 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6112$1567_Y - connect \Y $and$ls180.v:6112$1568_Y + connect \B $not$ls180.v:6164$1633_Y + connect \Y $and$ls180.v:6164$1634_Y end - attribute \src "ls180.v:6112.35-6112.142" - cell $and $and$ls180.v:6112$1570 + attribute \src "ls180.v:6164.35-6164.142" + cell $and $and$ls180.v:6164$1636 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6112$1568_Y - connect \B $eq$ls180.v:6112$1569_Y - connect \Y $and$ls180.v:6112$1570_Y + connect \A $and$ls180.v:6164$1634_Y + connect \B $eq$ls180.v:6164$1635_Y + connect \Y $and$ls180.v:6164$1636_Y end - attribute \src "ls180.v:6114.47-6114.100" - cell $and $and$ls180.v:6114$1571 + attribute \src "ls180.v:6166.47-6166.100" + cell $and $and$ls180.v:6166$1637 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242790,43 +243658,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6114$1571_Y + connect \Y $and$ls180.v:6166$1637_Y end - attribute \src "ls180.v:6114.46-6114.150" - cell $and $and$ls180.v:6114$1573 + attribute \src "ls180.v:6166.46-6166.150" + cell $and $and$ls180.v:6166$1639 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6114$1571_Y - connect \B $eq$ls180.v:6114$1572_Y - connect \Y $and$ls180.v:6114$1573_Y + connect \A $and$ls180.v:6166$1637_Y + connect \B $eq$ls180.v:6166$1638_Y + connect \Y $and$ls180.v:6166$1639_Y end - attribute \src "ls180.v:6115.47-6115.103" - cell $and $and$ls180.v:6115$1575 + attribute \src "ls180.v:6167.47-6167.103" + cell $and $and$ls180.v:6167$1641 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6115$1574_Y - connect \Y $and$ls180.v:6115$1575_Y + connect \B $not$ls180.v:6167$1640_Y + connect \Y $and$ls180.v:6167$1641_Y end - attribute \src "ls180.v:6115.46-6115.153" - cell $and $and$ls180.v:6115$1577 + attribute \src "ls180.v:6167.46-6167.153" + cell $and $and$ls180.v:6167$1643 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6115$1575_Y - connect \B $eq$ls180.v:6115$1576_Y - connect \Y $and$ls180.v:6115$1577_Y + connect \A $and$ls180.v:6167$1641_Y + connect \B $eq$ls180.v:6167$1642_Y + connect \Y $and$ls180.v:6167$1643_Y end - attribute \src "ls180.v:6117.47-6117.100" - cell $and $and$ls180.v:6117$1578 + attribute \src "ls180.v:6169.47-6169.100" + cell $and $and$ls180.v:6169$1644 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242834,43 +243702,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6117$1578_Y + connect \Y $and$ls180.v:6169$1644_Y end - attribute \src "ls180.v:6117.46-6117.151" - cell $and $and$ls180.v:6117$1580 + attribute \src "ls180.v:6169.46-6169.151" + cell $and $and$ls180.v:6169$1646 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6117$1578_Y - connect \B $eq$ls180.v:6117$1579_Y - connect \Y $and$ls180.v:6117$1580_Y + connect \A $and$ls180.v:6169$1644_Y + connect \B $eq$ls180.v:6169$1645_Y + connect \Y $and$ls180.v:6169$1646_Y end - attribute \src "ls180.v:6118.47-6118.103" - cell $and $and$ls180.v:6118$1582 + attribute \src "ls180.v:6170.47-6170.103" + cell $and $and$ls180.v:6170$1648 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6118$1581_Y - connect \Y $and$ls180.v:6118$1582_Y + connect \B $not$ls180.v:6170$1647_Y + connect \Y $and$ls180.v:6170$1648_Y end - attribute \src "ls180.v:6118.46-6118.154" - cell $and $and$ls180.v:6118$1584 + attribute \src "ls180.v:6170.46-6170.154" + cell $and $and$ls180.v:6170$1650 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6118$1582_Y - connect \B $eq$ls180.v:6118$1583_Y - connect \Y $and$ls180.v:6118$1584_Y + connect \A $and$ls180.v:6170$1648_Y + connect \B $eq$ls180.v:6170$1649_Y + connect \Y $and$ls180.v:6170$1650_Y end - attribute \src "ls180.v:6120.47-6120.100" - cell $and $and$ls180.v:6120$1585 + attribute \src "ls180.v:6172.47-6172.100" + cell $and $and$ls180.v:6172$1651 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242878,43 +243746,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6120$1585_Y + connect \Y $and$ls180.v:6172$1651_Y end - attribute \src "ls180.v:6120.46-6120.151" - cell $and $and$ls180.v:6120$1587 + attribute \src "ls180.v:6172.46-6172.151" + cell $and $and$ls180.v:6172$1653 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6120$1585_Y - connect \B $eq$ls180.v:6120$1586_Y - connect \Y $and$ls180.v:6120$1587_Y + connect \A $and$ls180.v:6172$1651_Y + connect \B $eq$ls180.v:6172$1652_Y + connect \Y $and$ls180.v:6172$1653_Y end - attribute \src "ls180.v:6121.47-6121.103" - cell $and $and$ls180.v:6121$1589 + attribute \src "ls180.v:6173.47-6173.103" + cell $and $and$ls180.v:6173$1655 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6121$1588_Y - connect \Y $and$ls180.v:6121$1589_Y + connect \B $not$ls180.v:6173$1654_Y + connect \Y $and$ls180.v:6173$1655_Y end - attribute \src "ls180.v:6121.46-6121.154" - cell $and $and$ls180.v:6121$1591 + attribute \src "ls180.v:6173.46-6173.154" + cell $and $and$ls180.v:6173$1657 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6121$1589_Y - connect \B $eq$ls180.v:6121$1590_Y - connect \Y $and$ls180.v:6121$1591_Y + connect \A $and$ls180.v:6173$1655_Y + connect \B $eq$ls180.v:6173$1656_Y + connect \Y $and$ls180.v:6173$1657_Y end - attribute \src "ls180.v:6123.47-6123.100" - cell $and $and$ls180.v:6123$1592 + attribute \src "ls180.v:6175.47-6175.100" + cell $and $and$ls180.v:6175$1658 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242922,43 +243790,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6123$1592_Y + connect \Y $and$ls180.v:6175$1658_Y end - attribute \src "ls180.v:6123.46-6123.151" - cell $and $and$ls180.v:6123$1594 + attribute \src "ls180.v:6175.46-6175.151" + cell $and $and$ls180.v:6175$1660 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6123$1592_Y - connect \B $eq$ls180.v:6123$1593_Y - connect \Y $and$ls180.v:6123$1594_Y + connect \A $and$ls180.v:6175$1658_Y + connect \B $eq$ls180.v:6175$1659_Y + connect \Y $and$ls180.v:6175$1660_Y end - attribute \src "ls180.v:6124.47-6124.103" - cell $and $and$ls180.v:6124$1596 + attribute \src "ls180.v:6176.47-6176.103" + cell $and $and$ls180.v:6176$1662 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6124$1595_Y - connect \Y $and$ls180.v:6124$1596_Y + connect \B $not$ls180.v:6176$1661_Y + connect \Y $and$ls180.v:6176$1662_Y end - attribute \src "ls180.v:6124.46-6124.154" - cell $and $and$ls180.v:6124$1598 + attribute \src "ls180.v:6176.46-6176.154" + cell $and $and$ls180.v:6176$1664 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6124$1596_Y - connect \B $eq$ls180.v:6124$1597_Y - connect \Y $and$ls180.v:6124$1598_Y + connect \A $and$ls180.v:6176$1662_Y + connect \B $eq$ls180.v:6176$1663_Y + connect \Y $and$ls180.v:6176$1664_Y end - attribute \src "ls180.v:6126.47-6126.100" - cell $and $and$ls180.v:6126$1599 + attribute \src "ls180.v:6178.47-6178.100" + cell $and $and$ls180.v:6178$1665 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242966,43 +243834,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6126$1599_Y + connect \Y $and$ls180.v:6178$1665_Y end - attribute \src "ls180.v:6126.46-6126.151" - cell $and $and$ls180.v:6126$1601 + attribute \src "ls180.v:6178.46-6178.151" + cell $and $and$ls180.v:6178$1667 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6126$1599_Y - connect \B $eq$ls180.v:6126$1600_Y - connect \Y $and$ls180.v:6126$1601_Y + connect \A $and$ls180.v:6178$1665_Y + connect \B $eq$ls180.v:6178$1666_Y + connect \Y $and$ls180.v:6178$1667_Y end - attribute \src "ls180.v:6127.47-6127.103" - cell $and $and$ls180.v:6127$1603 + attribute \src "ls180.v:6179.47-6179.103" + cell $and $and$ls180.v:6179$1669 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6127$1602_Y - connect \Y $and$ls180.v:6127$1603_Y + connect \B $not$ls180.v:6179$1668_Y + connect \Y $and$ls180.v:6179$1669_Y end - attribute \src "ls180.v:6127.46-6127.154" - cell $and $and$ls180.v:6127$1605 + attribute \src "ls180.v:6179.46-6179.154" + cell $and $and$ls180.v:6179$1671 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6127$1603_Y - connect \B $eq$ls180.v:6127$1604_Y - connect \Y $and$ls180.v:6127$1605_Y + connect \A $and$ls180.v:6179$1669_Y + connect \B $eq$ls180.v:6179$1670_Y + connect \Y $and$ls180.v:6179$1671_Y end - attribute \src "ls180.v:6129.47-6129.100" - cell $and $and$ls180.v:6129$1606 + attribute \src "ls180.v:6181.47-6181.100" + cell $and $and$ls180.v:6181$1672 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243010,43 +243878,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6129$1606_Y + connect \Y $and$ls180.v:6181$1672_Y end - attribute \src "ls180.v:6129.46-6129.151" - cell $and $and$ls180.v:6129$1608 + attribute \src "ls180.v:6181.46-6181.151" + cell $and $and$ls180.v:6181$1674 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6129$1606_Y - connect \B $eq$ls180.v:6129$1607_Y - connect \Y $and$ls180.v:6129$1608_Y + connect \A $and$ls180.v:6181$1672_Y + connect \B $eq$ls180.v:6181$1673_Y + connect \Y $and$ls180.v:6181$1674_Y end - attribute \src "ls180.v:6130.47-6130.103" - cell $and $and$ls180.v:6130$1610 + attribute \src "ls180.v:6182.47-6182.103" + cell $and $and$ls180.v:6182$1676 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6130$1609_Y - connect \Y $and$ls180.v:6130$1610_Y + connect \B $not$ls180.v:6182$1675_Y + connect \Y $and$ls180.v:6182$1676_Y end - attribute \src "ls180.v:6130.46-6130.154" - cell $and $and$ls180.v:6130$1612 + attribute \src "ls180.v:6182.46-6182.154" + cell $and $and$ls180.v:6182$1678 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6130$1610_Y - connect \B $eq$ls180.v:6130$1611_Y - connect \Y $and$ls180.v:6130$1612_Y + connect \A $and$ls180.v:6182$1676_Y + connect \B $eq$ls180.v:6182$1677_Y + connect \Y $and$ls180.v:6182$1678_Y end - attribute \src "ls180.v:6132.46-6132.99" - cell $and $and$ls180.v:6132$1613 + attribute \src "ls180.v:6184.46-6184.99" + cell $and $and$ls180.v:6184$1679 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243054,43 +243922,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6132$1613_Y + connect \Y $and$ls180.v:6184$1679_Y end - attribute \src "ls180.v:6132.45-6132.150" - cell $and $and$ls180.v:6132$1615 + attribute \src "ls180.v:6184.45-6184.150" + cell $and $and$ls180.v:6184$1681 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6132$1613_Y - connect \B $eq$ls180.v:6132$1614_Y - connect \Y $and$ls180.v:6132$1615_Y + connect \A $and$ls180.v:6184$1679_Y + connect \B $eq$ls180.v:6184$1680_Y + connect \Y $and$ls180.v:6184$1681_Y end - attribute \src "ls180.v:6133.46-6133.102" - cell $and $and$ls180.v:6133$1617 + attribute \src "ls180.v:6185.46-6185.102" + cell $and $and$ls180.v:6185$1683 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6133$1616_Y - connect \Y $and$ls180.v:6133$1617_Y + connect \B $not$ls180.v:6185$1682_Y + connect \Y $and$ls180.v:6185$1683_Y end - attribute \src "ls180.v:6133.45-6133.153" - cell $and $and$ls180.v:6133$1619 + attribute \src "ls180.v:6185.45-6185.153" + cell $and $and$ls180.v:6185$1685 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6133$1617_Y - connect \B $eq$ls180.v:6133$1618_Y - connect \Y $and$ls180.v:6133$1619_Y + connect \A $and$ls180.v:6185$1683_Y + connect \B $eq$ls180.v:6185$1684_Y + connect \Y $and$ls180.v:6185$1685_Y end - attribute \src "ls180.v:6135.46-6135.99" - cell $and $and$ls180.v:6135$1620 + attribute \src "ls180.v:6187.46-6187.99" + cell $and $and$ls180.v:6187$1686 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243098,43 +243966,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6135$1620_Y + connect \Y $and$ls180.v:6187$1686_Y end - attribute \src "ls180.v:6135.45-6135.150" - cell $and $and$ls180.v:6135$1622 + attribute \src "ls180.v:6187.45-6187.150" + cell $and $and$ls180.v:6187$1688 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6135$1620_Y - connect \B $eq$ls180.v:6135$1621_Y - connect \Y $and$ls180.v:6135$1622_Y + connect \A $and$ls180.v:6187$1686_Y + connect \B $eq$ls180.v:6187$1687_Y + connect \Y $and$ls180.v:6187$1688_Y end - attribute \src "ls180.v:6136.46-6136.102" - cell $and $and$ls180.v:6136$1624 + attribute \src "ls180.v:6188.46-6188.102" + cell $and $and$ls180.v:6188$1690 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6136$1623_Y - connect \Y $and$ls180.v:6136$1624_Y + connect \B $not$ls180.v:6188$1689_Y + connect \Y $and$ls180.v:6188$1690_Y end - attribute \src "ls180.v:6136.45-6136.153" - cell $and $and$ls180.v:6136$1626 + attribute \src "ls180.v:6188.45-6188.153" + cell $and $and$ls180.v:6188$1692 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6136$1624_Y - connect \B $eq$ls180.v:6136$1625_Y - connect \Y $and$ls180.v:6136$1626_Y + connect \A $and$ls180.v:6188$1690_Y + connect \B $eq$ls180.v:6188$1691_Y + connect \Y $and$ls180.v:6188$1692_Y end - attribute \src "ls180.v:6138.46-6138.99" - cell $and $and$ls180.v:6138$1627 + attribute \src "ls180.v:6190.46-6190.99" + cell $and $and$ls180.v:6190$1693 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243142,43 +244010,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6138$1627_Y + connect \Y $and$ls180.v:6190$1693_Y end - attribute \src "ls180.v:6138.45-6138.150" - cell $and $and$ls180.v:6138$1629 + attribute \src "ls180.v:6190.45-6190.150" + cell $and $and$ls180.v:6190$1695 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6138$1627_Y - connect \B $eq$ls180.v:6138$1628_Y - connect \Y $and$ls180.v:6138$1629_Y + connect \A $and$ls180.v:6190$1693_Y + connect \B $eq$ls180.v:6190$1694_Y + connect \Y $and$ls180.v:6190$1695_Y end - attribute \src "ls180.v:6139.46-6139.102" - cell $and $and$ls180.v:6139$1631 + attribute \src "ls180.v:6191.46-6191.102" + cell $and $and$ls180.v:6191$1697 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6139$1630_Y - connect \Y $and$ls180.v:6139$1631_Y + connect \B $not$ls180.v:6191$1696_Y + connect \Y $and$ls180.v:6191$1697_Y end - attribute \src "ls180.v:6139.45-6139.153" - cell $and $and$ls180.v:6139$1633 + attribute \src "ls180.v:6191.45-6191.153" + cell $and $and$ls180.v:6191$1699 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6139$1631_Y - connect \B $eq$ls180.v:6139$1632_Y - connect \Y $and$ls180.v:6139$1633_Y + connect \A $and$ls180.v:6191$1697_Y + connect \B $eq$ls180.v:6191$1698_Y + connect \Y $and$ls180.v:6191$1699_Y end - attribute \src "ls180.v:6141.46-6141.99" - cell $and $and$ls180.v:6141$1634 + attribute \src "ls180.v:6193.46-6193.99" + cell $and $and$ls180.v:6193$1700 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243186,43 +244054,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6141$1634_Y + connect \Y $and$ls180.v:6193$1700_Y end - attribute \src "ls180.v:6141.45-6141.150" - cell $and $and$ls180.v:6141$1636 + attribute \src "ls180.v:6193.45-6193.150" + cell $and $and$ls180.v:6193$1702 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6141$1634_Y - connect \B $eq$ls180.v:6141$1635_Y - connect \Y $and$ls180.v:6141$1636_Y + connect \A $and$ls180.v:6193$1700_Y + connect \B $eq$ls180.v:6193$1701_Y + connect \Y $and$ls180.v:6193$1702_Y end - attribute \src "ls180.v:6142.46-6142.102" - cell $and $and$ls180.v:6142$1638 + attribute \src "ls180.v:6194.46-6194.102" + cell $and $and$ls180.v:6194$1704 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6142$1637_Y - connect \Y $and$ls180.v:6142$1638_Y + connect \B $not$ls180.v:6194$1703_Y + connect \Y $and$ls180.v:6194$1704_Y end - attribute \src "ls180.v:6142.45-6142.153" - cell $and $and$ls180.v:6142$1640 + attribute \src "ls180.v:6194.45-6194.153" + cell $and $and$ls180.v:6194$1706 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6142$1638_Y - connect \B $eq$ls180.v:6142$1639_Y - connect \Y $and$ls180.v:6142$1640_Y + connect \A $and$ls180.v:6194$1704_Y + connect \B $eq$ls180.v:6194$1705_Y + connect \Y $and$ls180.v:6194$1706_Y end - attribute \src "ls180.v:6144.46-6144.99" - cell $and $and$ls180.v:6144$1641 + attribute \src "ls180.v:6196.46-6196.99" + cell $and $and$ls180.v:6196$1707 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243230,43 +244098,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6144$1641_Y + connect \Y $and$ls180.v:6196$1707_Y end - attribute \src "ls180.v:6144.45-6144.150" - cell $and $and$ls180.v:6144$1643 + attribute \src "ls180.v:6196.45-6196.150" + cell $and $and$ls180.v:6196$1709 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6144$1641_Y - connect \B $eq$ls180.v:6144$1642_Y - connect \Y $and$ls180.v:6144$1643_Y + connect \A $and$ls180.v:6196$1707_Y + connect \B $eq$ls180.v:6196$1708_Y + connect \Y $and$ls180.v:6196$1709_Y end - attribute \src "ls180.v:6145.46-6145.102" - cell $and $and$ls180.v:6145$1645 + attribute \src "ls180.v:6197.46-6197.102" + cell $and $and$ls180.v:6197$1711 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6145$1644_Y - connect \Y $and$ls180.v:6145$1645_Y + connect \B $not$ls180.v:6197$1710_Y + connect \Y $and$ls180.v:6197$1711_Y end - attribute \src "ls180.v:6145.45-6145.153" - cell $and $and$ls180.v:6145$1647 + attribute \src "ls180.v:6197.45-6197.153" + cell $and $and$ls180.v:6197$1713 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6145$1645_Y - connect \B $eq$ls180.v:6145$1646_Y - connect \Y $and$ls180.v:6145$1647_Y + connect \A $and$ls180.v:6197$1711_Y + connect \B $eq$ls180.v:6197$1712_Y + connect \Y $and$ls180.v:6197$1713_Y end - attribute \src "ls180.v:6147.46-6147.99" - cell $and $and$ls180.v:6147$1648 + attribute \src "ls180.v:6199.46-6199.99" + cell $and $and$ls180.v:6199$1714 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243274,43 +244142,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6147$1648_Y + connect \Y $and$ls180.v:6199$1714_Y end - attribute \src "ls180.v:6147.45-6147.150" - cell $and $and$ls180.v:6147$1650 + attribute \src "ls180.v:6199.45-6199.150" + cell $and $and$ls180.v:6199$1716 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6147$1648_Y - connect \B $eq$ls180.v:6147$1649_Y - connect \Y $and$ls180.v:6147$1650_Y + connect \A $and$ls180.v:6199$1714_Y + connect \B $eq$ls180.v:6199$1715_Y + connect \Y $and$ls180.v:6199$1716_Y end - attribute \src "ls180.v:6148.46-6148.102" - cell $and $and$ls180.v:6148$1652 + attribute \src "ls180.v:6200.46-6200.102" + cell $and $and$ls180.v:6200$1718 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6148$1651_Y - connect \Y $and$ls180.v:6148$1652_Y + connect \B $not$ls180.v:6200$1717_Y + connect \Y $and$ls180.v:6200$1718_Y end - attribute \src "ls180.v:6148.45-6148.153" - cell $and $and$ls180.v:6148$1654 + attribute \src "ls180.v:6200.45-6200.153" + cell $and $and$ls180.v:6200$1720 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6148$1652_Y - connect \B $eq$ls180.v:6148$1653_Y - connect \Y $and$ls180.v:6148$1654_Y + connect \A $and$ls180.v:6200$1718_Y + connect \B $eq$ls180.v:6200$1719_Y + connect \Y $and$ls180.v:6200$1720_Y end - attribute \src "ls180.v:6150.46-6150.99" - cell $and $and$ls180.v:6150$1655 + attribute \src "ls180.v:6202.46-6202.99" + cell $and $and$ls180.v:6202$1721 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243318,43 +244186,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6150$1655_Y + connect \Y $and$ls180.v:6202$1721_Y end - attribute \src "ls180.v:6150.45-6150.150" - cell $and $and$ls180.v:6150$1657 + attribute \src "ls180.v:6202.45-6202.150" + cell $and $and$ls180.v:6202$1723 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6150$1655_Y - connect \B $eq$ls180.v:6150$1656_Y - connect \Y $and$ls180.v:6150$1657_Y + connect \A $and$ls180.v:6202$1721_Y + connect \B $eq$ls180.v:6202$1722_Y + connect \Y $and$ls180.v:6202$1723_Y end - attribute \src "ls180.v:6151.46-6151.102" - cell $and $and$ls180.v:6151$1659 + attribute \src "ls180.v:6203.46-6203.102" + cell $and $and$ls180.v:6203$1725 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6151$1658_Y - connect \Y $and$ls180.v:6151$1659_Y + connect \B $not$ls180.v:6203$1724_Y + connect \Y $and$ls180.v:6203$1725_Y end - attribute \src "ls180.v:6151.45-6151.153" - cell $and $and$ls180.v:6151$1661 + attribute \src "ls180.v:6203.45-6203.153" + cell $and $and$ls180.v:6203$1727 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6151$1659_Y - connect \B $eq$ls180.v:6151$1660_Y - connect \Y $and$ls180.v:6151$1661_Y + connect \A $and$ls180.v:6203$1725_Y + connect \B $eq$ls180.v:6203$1726_Y + connect \Y $and$ls180.v:6203$1727_Y end - attribute \src "ls180.v:6153.46-6153.99" - cell $and $and$ls180.v:6153$1662 + attribute \src "ls180.v:6205.46-6205.99" + cell $and $and$ls180.v:6205$1728 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243362,43 +244230,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6153$1662_Y + connect \Y $and$ls180.v:6205$1728_Y end - attribute \src "ls180.v:6153.45-6153.150" - cell $and $and$ls180.v:6153$1664 + attribute \src "ls180.v:6205.45-6205.150" + cell $and $and$ls180.v:6205$1730 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6153$1662_Y - connect \B $eq$ls180.v:6153$1663_Y - connect \Y $and$ls180.v:6153$1664_Y + connect \A $and$ls180.v:6205$1728_Y + connect \B $eq$ls180.v:6205$1729_Y + connect \Y $and$ls180.v:6205$1730_Y end - attribute \src "ls180.v:6154.46-6154.102" - cell $and $and$ls180.v:6154$1666 + attribute \src "ls180.v:6206.46-6206.102" + cell $and $and$ls180.v:6206$1732 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6154$1665_Y - connect \Y $and$ls180.v:6154$1666_Y + connect \B $not$ls180.v:6206$1731_Y + connect \Y $and$ls180.v:6206$1732_Y end - attribute \src "ls180.v:6154.45-6154.153" - cell $and $and$ls180.v:6154$1668 + attribute \src "ls180.v:6206.45-6206.153" + cell $and $and$ls180.v:6206$1734 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6154$1666_Y - connect \B $eq$ls180.v:6154$1667_Y - connect \Y $and$ls180.v:6154$1668_Y + connect \A $and$ls180.v:6206$1732_Y + connect \B $eq$ls180.v:6206$1733_Y + connect \Y $and$ls180.v:6206$1734_Y end - attribute \src "ls180.v:6156.46-6156.99" - cell $and $and$ls180.v:6156$1669 + attribute \src "ls180.v:6208.46-6208.99" + cell $and $and$ls180.v:6208$1735 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243406,43 +244274,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6156$1669_Y + connect \Y $and$ls180.v:6208$1735_Y end - attribute \src "ls180.v:6156.45-6156.150" - cell $and $and$ls180.v:6156$1671 + attribute \src "ls180.v:6208.45-6208.150" + cell $and $and$ls180.v:6208$1737 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6156$1669_Y - connect \B $eq$ls180.v:6156$1670_Y - connect \Y $and$ls180.v:6156$1671_Y + connect \A $and$ls180.v:6208$1735_Y + connect \B $eq$ls180.v:6208$1736_Y + connect \Y $and$ls180.v:6208$1737_Y end - attribute \src "ls180.v:6157.46-6157.102" - cell $and $and$ls180.v:6157$1673 + attribute \src "ls180.v:6209.46-6209.102" + cell $and $and$ls180.v:6209$1739 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6157$1672_Y - connect \Y $and$ls180.v:6157$1673_Y + connect \B $not$ls180.v:6209$1738_Y + connect \Y $and$ls180.v:6209$1739_Y end - attribute \src "ls180.v:6157.45-6157.153" - cell $and $and$ls180.v:6157$1675 + attribute \src "ls180.v:6209.45-6209.153" + cell $and $and$ls180.v:6209$1741 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6157$1673_Y - connect \B $eq$ls180.v:6157$1674_Y - connect \Y $and$ls180.v:6157$1675_Y + connect \A $and$ls180.v:6209$1739_Y + connect \B $eq$ls180.v:6209$1740_Y + connect \Y $and$ls180.v:6209$1741_Y end - attribute \src "ls180.v:6159.46-6159.99" - cell $and $and$ls180.v:6159$1676 + attribute \src "ls180.v:6211.46-6211.99" + cell $and $and$ls180.v:6211$1742 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243450,43 +244318,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6159$1676_Y + connect \Y $and$ls180.v:6211$1742_Y end - attribute \src "ls180.v:6159.45-6159.150" - cell $and $and$ls180.v:6159$1678 + attribute \src "ls180.v:6211.45-6211.150" + cell $and $and$ls180.v:6211$1744 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6159$1676_Y - connect \B $eq$ls180.v:6159$1677_Y - connect \Y $and$ls180.v:6159$1678_Y + connect \A $and$ls180.v:6211$1742_Y + connect \B $eq$ls180.v:6211$1743_Y + connect \Y $and$ls180.v:6211$1744_Y end - attribute \src "ls180.v:6160.46-6160.102" - cell $and $and$ls180.v:6160$1680 + attribute \src "ls180.v:6212.46-6212.102" + cell $and $and$ls180.v:6212$1746 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6160$1679_Y - connect \Y $and$ls180.v:6160$1680_Y + connect \B $not$ls180.v:6212$1745_Y + connect \Y $and$ls180.v:6212$1746_Y end - attribute \src "ls180.v:6160.45-6160.153" - cell $and $and$ls180.v:6160$1682 + attribute \src "ls180.v:6212.45-6212.153" + cell $and $and$ls180.v:6212$1748 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6160$1680_Y - connect \B $eq$ls180.v:6160$1681_Y - connect \Y $and$ls180.v:6160$1682_Y + connect \A $and$ls180.v:6212$1746_Y + connect \B $eq$ls180.v:6212$1747_Y + connect \Y $and$ls180.v:6212$1748_Y end - attribute \src "ls180.v:6162.42-6162.95" - cell $and $and$ls180.v:6162$1683 + attribute \src "ls180.v:6214.42-6214.95" + cell $and $and$ls180.v:6214$1749 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243494,43 +244362,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6162$1683_Y + connect \Y $and$ls180.v:6214$1749_Y end - attribute \src "ls180.v:6162.41-6162.146" - cell $and $and$ls180.v:6162$1685 + attribute \src "ls180.v:6214.41-6214.146" + cell $and $and$ls180.v:6214$1751 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6162$1683_Y - connect \B $eq$ls180.v:6162$1684_Y - connect \Y $and$ls180.v:6162$1685_Y + connect \A $and$ls180.v:6214$1749_Y + connect \B $eq$ls180.v:6214$1750_Y + connect \Y $and$ls180.v:6214$1751_Y end - attribute \src "ls180.v:6163.42-6163.98" - cell $and $and$ls180.v:6163$1687 + attribute \src "ls180.v:6215.42-6215.98" + cell $and $and$ls180.v:6215$1753 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6163$1686_Y - connect \Y $and$ls180.v:6163$1687_Y + connect \B $not$ls180.v:6215$1752_Y + connect \Y $and$ls180.v:6215$1753_Y end - attribute \src "ls180.v:6163.41-6163.149" - cell $and $and$ls180.v:6163$1689 + attribute \src "ls180.v:6215.41-6215.149" + cell $and $and$ls180.v:6215$1755 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6163$1687_Y - connect \B $eq$ls180.v:6163$1688_Y - connect \Y $and$ls180.v:6163$1689_Y + connect \A $and$ls180.v:6215$1753_Y + connect \B $eq$ls180.v:6215$1754_Y + connect \Y $and$ls180.v:6215$1755_Y end - attribute \src "ls180.v:6165.43-6165.96" - cell $and $and$ls180.v:6165$1690 + attribute \src "ls180.v:6217.43-6217.96" + cell $and $and$ls180.v:6217$1756 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243538,43 +244406,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6165$1690_Y + connect \Y $and$ls180.v:6217$1756_Y end - attribute \src "ls180.v:6165.42-6165.147" - cell $and $and$ls180.v:6165$1692 + attribute \src "ls180.v:6217.42-6217.147" + cell $and $and$ls180.v:6217$1758 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6165$1690_Y - connect \B $eq$ls180.v:6165$1691_Y - connect \Y $and$ls180.v:6165$1692_Y + connect \A $and$ls180.v:6217$1756_Y + connect \B $eq$ls180.v:6217$1757_Y + connect \Y $and$ls180.v:6217$1758_Y end - attribute \src "ls180.v:6166.43-6166.99" - cell $and $and$ls180.v:6166$1694 + attribute \src "ls180.v:6218.43-6218.99" + cell $and $and$ls180.v:6218$1760 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6166$1693_Y - connect \Y $and$ls180.v:6166$1694_Y + connect \B $not$ls180.v:6218$1759_Y + connect \Y $and$ls180.v:6218$1760_Y end - attribute \src "ls180.v:6166.42-6166.150" - cell $and $and$ls180.v:6166$1696 + attribute \src "ls180.v:6218.42-6218.150" + cell $and $and$ls180.v:6218$1762 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6166$1694_Y - connect \B $eq$ls180.v:6166$1695_Y - connect \Y $and$ls180.v:6166$1696_Y + connect \A $and$ls180.v:6218$1760_Y + connect \B $eq$ls180.v:6218$1761_Y + connect \Y $and$ls180.v:6218$1762_Y end - attribute \src "ls180.v:6168.46-6168.99" - cell $and $and$ls180.v:6168$1697 + attribute \src "ls180.v:6220.46-6220.99" + cell $and $and$ls180.v:6220$1763 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243582,43 +244450,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6168$1697_Y + connect \Y $and$ls180.v:6220$1763_Y end - attribute \src "ls180.v:6168.45-6168.150" - cell $and $and$ls180.v:6168$1699 + attribute \src "ls180.v:6220.45-6220.150" + cell $and $and$ls180.v:6220$1765 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6168$1697_Y - connect \B $eq$ls180.v:6168$1698_Y - connect \Y $and$ls180.v:6168$1699_Y + connect \A $and$ls180.v:6220$1763_Y + connect \B $eq$ls180.v:6220$1764_Y + connect \Y $and$ls180.v:6220$1765_Y end - attribute \src "ls180.v:6169.46-6169.102" - cell $and $and$ls180.v:6169$1701 + attribute \src "ls180.v:6221.46-6221.102" + cell $and $and$ls180.v:6221$1767 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6169$1700_Y - connect \Y $and$ls180.v:6169$1701_Y + connect \B $not$ls180.v:6221$1766_Y + connect \Y $and$ls180.v:6221$1767_Y end - attribute \src "ls180.v:6169.45-6169.153" - cell $and $and$ls180.v:6169$1703 + attribute \src "ls180.v:6221.45-6221.153" + cell $and $and$ls180.v:6221$1769 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6169$1701_Y - connect \B $eq$ls180.v:6169$1702_Y - connect \Y $and$ls180.v:6169$1703_Y + connect \A $and$ls180.v:6221$1767_Y + connect \B $eq$ls180.v:6221$1768_Y + connect \Y $and$ls180.v:6221$1769_Y end - attribute \src "ls180.v:6171.46-6171.99" - cell $and $and$ls180.v:6171$1704 + attribute \src "ls180.v:6223.46-6223.99" + cell $and $and$ls180.v:6223$1770 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243626,43 +244494,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6171$1704_Y + connect \Y $and$ls180.v:6223$1770_Y end - attribute \src "ls180.v:6171.45-6171.150" - cell $and $and$ls180.v:6171$1706 + attribute \src "ls180.v:6223.45-6223.150" + cell $and $and$ls180.v:6223$1772 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6171$1704_Y - connect \B $eq$ls180.v:6171$1705_Y - connect \Y $and$ls180.v:6171$1706_Y + connect \A $and$ls180.v:6223$1770_Y + connect \B $eq$ls180.v:6223$1771_Y + connect \Y $and$ls180.v:6223$1772_Y end - attribute \src "ls180.v:6172.46-6172.102" - cell $and $and$ls180.v:6172$1708 + attribute \src "ls180.v:6224.46-6224.102" + cell $and $and$ls180.v:6224$1774 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6172$1707_Y - connect \Y $and$ls180.v:6172$1708_Y + connect \B $not$ls180.v:6224$1773_Y + connect \Y $and$ls180.v:6224$1774_Y end - attribute \src "ls180.v:6172.45-6172.153" - cell $and $and$ls180.v:6172$1710 + attribute \src "ls180.v:6224.45-6224.153" + cell $and $and$ls180.v:6224$1776 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6172$1708_Y - connect \B $eq$ls180.v:6172$1709_Y - connect \Y $and$ls180.v:6172$1710_Y + connect \A $and$ls180.v:6224$1774_Y + connect \B $eq$ls180.v:6224$1775_Y + connect \Y $and$ls180.v:6224$1776_Y end - attribute \src "ls180.v:6174.45-6174.98" - cell $and $and$ls180.v:6174$1711 + attribute \src "ls180.v:6226.45-6226.98" + cell $and $and$ls180.v:6226$1777 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243670,43 +244538,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6174$1711_Y + connect \Y $and$ls180.v:6226$1777_Y end - attribute \src "ls180.v:6174.44-6174.149" - cell $and $and$ls180.v:6174$1713 + attribute \src "ls180.v:6226.44-6226.149" + cell $and $and$ls180.v:6226$1779 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6174$1711_Y - connect \B $eq$ls180.v:6174$1712_Y - connect \Y $and$ls180.v:6174$1713_Y + connect \A $and$ls180.v:6226$1777_Y + connect \B $eq$ls180.v:6226$1778_Y + connect \Y $and$ls180.v:6226$1779_Y end - attribute \src "ls180.v:6175.45-6175.101" - cell $and $and$ls180.v:6175$1715 + attribute \src "ls180.v:6227.45-6227.101" + cell $and $and$ls180.v:6227$1781 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6175$1714_Y - connect \Y $and$ls180.v:6175$1715_Y + connect \B $not$ls180.v:6227$1780_Y + connect \Y $and$ls180.v:6227$1781_Y end - attribute \src "ls180.v:6175.44-6175.152" - cell $and $and$ls180.v:6175$1717 + attribute \src "ls180.v:6227.44-6227.152" + cell $and $and$ls180.v:6227$1783 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6175$1715_Y - connect \B $eq$ls180.v:6175$1716_Y - connect \Y $and$ls180.v:6175$1717_Y + connect \A $and$ls180.v:6227$1781_Y + connect \B $eq$ls180.v:6227$1782_Y + connect \Y $and$ls180.v:6227$1783_Y end - attribute \src "ls180.v:6177.45-6177.98" - cell $and $and$ls180.v:6177$1718 + attribute \src "ls180.v:6229.45-6229.98" + cell $and $and$ls180.v:6229$1784 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243714,43 +244582,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6177$1718_Y + connect \Y $and$ls180.v:6229$1784_Y end - attribute \src "ls180.v:6177.44-6177.149" - cell $and $and$ls180.v:6177$1720 + attribute \src "ls180.v:6229.44-6229.149" + cell $and $and$ls180.v:6229$1786 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6177$1718_Y - connect \B $eq$ls180.v:6177$1719_Y - connect \Y $and$ls180.v:6177$1720_Y + connect \A $and$ls180.v:6229$1784_Y + connect \B $eq$ls180.v:6229$1785_Y + connect \Y $and$ls180.v:6229$1786_Y end - attribute \src "ls180.v:6178.45-6178.101" - cell $and $and$ls180.v:6178$1722 + attribute \src "ls180.v:6230.45-6230.101" + cell $and $and$ls180.v:6230$1788 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6178$1721_Y - connect \Y $and$ls180.v:6178$1722_Y + connect \B $not$ls180.v:6230$1787_Y + connect \Y $and$ls180.v:6230$1788_Y end - attribute \src "ls180.v:6178.44-6178.152" - cell $and $and$ls180.v:6178$1724 + attribute \src "ls180.v:6230.44-6230.152" + cell $and $and$ls180.v:6230$1790 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6178$1722_Y - connect \B $eq$ls180.v:6178$1723_Y - connect \Y $and$ls180.v:6178$1724_Y + connect \A $and$ls180.v:6230$1788_Y + connect \B $eq$ls180.v:6230$1789_Y + connect \Y $and$ls180.v:6230$1790_Y end - attribute \src "ls180.v:6180.45-6180.98" - cell $and $and$ls180.v:6180$1725 + attribute \src "ls180.v:6232.45-6232.98" + cell $and $and$ls180.v:6232$1791 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243758,43 +244626,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6180$1725_Y + connect \Y $and$ls180.v:6232$1791_Y end - attribute \src "ls180.v:6180.44-6180.149" - cell $and $and$ls180.v:6180$1727 + attribute \src "ls180.v:6232.44-6232.149" + cell $and $and$ls180.v:6232$1793 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6180$1725_Y - connect \B $eq$ls180.v:6180$1726_Y - connect \Y $and$ls180.v:6180$1727_Y + connect \A $and$ls180.v:6232$1791_Y + connect \B $eq$ls180.v:6232$1792_Y + connect \Y $and$ls180.v:6232$1793_Y end - attribute \src "ls180.v:6181.45-6181.101" - cell $and $and$ls180.v:6181$1729 + attribute \src "ls180.v:6233.45-6233.101" + cell $and $and$ls180.v:6233$1795 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6181$1728_Y - connect \Y $and$ls180.v:6181$1729_Y + connect \B $not$ls180.v:6233$1794_Y + connect \Y $and$ls180.v:6233$1795_Y end - attribute \src "ls180.v:6181.44-6181.152" - cell $and $and$ls180.v:6181$1731 + attribute \src "ls180.v:6233.44-6233.152" + cell $and $and$ls180.v:6233$1797 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6181$1729_Y - connect \B $eq$ls180.v:6181$1730_Y - connect \Y $and$ls180.v:6181$1731_Y + connect \A $and$ls180.v:6233$1795_Y + connect \B $eq$ls180.v:6233$1796_Y + connect \Y $and$ls180.v:6233$1797_Y end - attribute \src "ls180.v:6183.45-6183.98" - cell $and $and$ls180.v:6183$1732 + attribute \src "ls180.v:6235.45-6235.98" + cell $and $and$ls180.v:6235$1798 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243802,43 +244670,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6183$1732_Y + connect \Y $and$ls180.v:6235$1798_Y end - attribute \src "ls180.v:6183.44-6183.149" - cell $and $and$ls180.v:6183$1734 + attribute \src "ls180.v:6235.44-6235.149" + cell $and $and$ls180.v:6235$1800 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6183$1732_Y - connect \B $eq$ls180.v:6183$1733_Y - connect \Y $and$ls180.v:6183$1734_Y + connect \A $and$ls180.v:6235$1798_Y + connect \B $eq$ls180.v:6235$1799_Y + connect \Y $and$ls180.v:6235$1800_Y end - attribute \src "ls180.v:6184.45-6184.101" - cell $and $and$ls180.v:6184$1736 + attribute \src "ls180.v:6236.45-6236.101" + cell $and $and$ls180.v:6236$1802 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6184$1735_Y - connect \Y $and$ls180.v:6184$1736_Y + connect \B $not$ls180.v:6236$1801_Y + connect \Y $and$ls180.v:6236$1802_Y end - attribute \src "ls180.v:6184.44-6184.152" - cell $and $and$ls180.v:6184$1738 + attribute \src "ls180.v:6236.44-6236.152" + cell $and $and$ls180.v:6236$1804 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6184$1736_Y - connect \B $eq$ls180.v:6184$1737_Y - connect \Y $and$ls180.v:6184$1738_Y + connect \A $and$ls180.v:6236$1802_Y + connect \B $eq$ls180.v:6236$1803_Y + connect \Y $and$ls180.v:6236$1804_Y end - attribute \src "ls180.v:6222.42-6222.95" - cell $and $and$ls180.v:6222$1740 + attribute \src "ls180.v:6274.42-6274.95" + cell $and $and$ls180.v:6274$1806 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243846,43 +244714,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6222$1740_Y + connect \Y $and$ls180.v:6274$1806_Y end - attribute \src "ls180.v:6222.41-6222.145" - cell $and $and$ls180.v:6222$1742 + attribute \src "ls180.v:6274.41-6274.145" + cell $and $and$ls180.v:6274$1808 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6222$1740_Y - connect \B $eq$ls180.v:6222$1741_Y - connect \Y $and$ls180.v:6222$1742_Y + connect \A $and$ls180.v:6274$1806_Y + connect \B $eq$ls180.v:6274$1807_Y + connect \Y $and$ls180.v:6274$1808_Y end - attribute \src "ls180.v:6223.42-6223.98" - cell $and $and$ls180.v:6223$1744 + attribute \src "ls180.v:6275.42-6275.98" + cell $and $and$ls180.v:6275$1810 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6223$1743_Y - connect \Y $and$ls180.v:6223$1744_Y + connect \B $not$ls180.v:6275$1809_Y + connect \Y $and$ls180.v:6275$1810_Y end - attribute \src "ls180.v:6223.41-6223.148" - cell $and $and$ls180.v:6223$1746 + attribute \src "ls180.v:6275.41-6275.148" + cell $and $and$ls180.v:6275$1812 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6223$1744_Y - connect \B $eq$ls180.v:6223$1745_Y - connect \Y $and$ls180.v:6223$1746_Y + connect \A $and$ls180.v:6275$1810_Y + connect \B $eq$ls180.v:6275$1811_Y + connect \Y $and$ls180.v:6275$1812_Y end - attribute \src "ls180.v:6225.42-6225.95" - cell $and $and$ls180.v:6225$1747 + attribute \src "ls180.v:6277.42-6277.95" + cell $and $and$ls180.v:6277$1813 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243890,43 +244758,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6225$1747_Y + connect \Y $and$ls180.v:6277$1813_Y end - attribute \src "ls180.v:6225.41-6225.145" - cell $and $and$ls180.v:6225$1749 + attribute \src "ls180.v:6277.41-6277.145" + cell $and $and$ls180.v:6277$1815 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6225$1747_Y - connect \B $eq$ls180.v:6225$1748_Y - connect \Y $and$ls180.v:6225$1749_Y + connect \A $and$ls180.v:6277$1813_Y + connect \B $eq$ls180.v:6277$1814_Y + connect \Y $and$ls180.v:6277$1815_Y end - attribute \src "ls180.v:6226.42-6226.98" - cell $and $and$ls180.v:6226$1751 + attribute \src "ls180.v:6278.42-6278.98" + cell $and $and$ls180.v:6278$1817 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6226$1750_Y - connect \Y $and$ls180.v:6226$1751_Y + connect \B $not$ls180.v:6278$1816_Y + connect \Y $and$ls180.v:6278$1817_Y end - attribute \src "ls180.v:6226.41-6226.148" - cell $and $and$ls180.v:6226$1753 + attribute \src "ls180.v:6278.41-6278.148" + cell $and $and$ls180.v:6278$1819 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6226$1751_Y - connect \B $eq$ls180.v:6226$1752_Y - connect \Y $and$ls180.v:6226$1753_Y + connect \A $and$ls180.v:6278$1817_Y + connect \B $eq$ls180.v:6278$1818_Y + connect \Y $and$ls180.v:6278$1819_Y end - attribute \src "ls180.v:6228.42-6228.95" - cell $and $and$ls180.v:6228$1754 + attribute \src "ls180.v:6280.42-6280.95" + cell $and $and$ls180.v:6280$1820 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243934,43 +244802,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6228$1754_Y + connect \Y $and$ls180.v:6280$1820_Y end - attribute \src "ls180.v:6228.41-6228.145" - cell $and $and$ls180.v:6228$1756 + attribute \src "ls180.v:6280.41-6280.145" + cell $and $and$ls180.v:6280$1822 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6228$1754_Y - connect \B $eq$ls180.v:6228$1755_Y - connect \Y $and$ls180.v:6228$1756_Y + connect \A $and$ls180.v:6280$1820_Y + connect \B $eq$ls180.v:6280$1821_Y + connect \Y $and$ls180.v:6280$1822_Y end - attribute \src "ls180.v:6229.42-6229.98" - cell $and $and$ls180.v:6229$1758 + attribute \src "ls180.v:6281.42-6281.98" + cell $and $and$ls180.v:6281$1824 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6229$1757_Y - connect \Y $and$ls180.v:6229$1758_Y + connect \B $not$ls180.v:6281$1823_Y + connect \Y $and$ls180.v:6281$1824_Y end - attribute \src "ls180.v:6229.41-6229.148" - cell $and $and$ls180.v:6229$1760 + attribute \src "ls180.v:6281.41-6281.148" + cell $and $and$ls180.v:6281$1826 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6229$1758_Y - connect \B $eq$ls180.v:6229$1759_Y - connect \Y $and$ls180.v:6229$1760_Y + connect \A $and$ls180.v:6281$1824_Y + connect \B $eq$ls180.v:6281$1825_Y + connect \Y $and$ls180.v:6281$1826_Y end - attribute \src "ls180.v:6231.42-6231.95" - cell $and $and$ls180.v:6231$1761 + attribute \src "ls180.v:6283.42-6283.95" + cell $and $and$ls180.v:6283$1827 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243978,43 +244846,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6231$1761_Y + connect \Y $and$ls180.v:6283$1827_Y end - attribute \src "ls180.v:6231.41-6231.145" - cell $and $and$ls180.v:6231$1763 + attribute \src "ls180.v:6283.41-6283.145" + cell $and $and$ls180.v:6283$1829 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6231$1761_Y - connect \B $eq$ls180.v:6231$1762_Y - connect \Y $and$ls180.v:6231$1763_Y + connect \A $and$ls180.v:6283$1827_Y + connect \B $eq$ls180.v:6283$1828_Y + connect \Y $and$ls180.v:6283$1829_Y end - attribute \src "ls180.v:6232.42-6232.98" - cell $and $and$ls180.v:6232$1765 + attribute \src "ls180.v:6284.42-6284.98" + cell $and $and$ls180.v:6284$1831 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6232$1764_Y - connect \Y $and$ls180.v:6232$1765_Y + connect \B $not$ls180.v:6284$1830_Y + connect \Y $and$ls180.v:6284$1831_Y end - attribute \src "ls180.v:6232.41-6232.148" - cell $and $and$ls180.v:6232$1767 + attribute \src "ls180.v:6284.41-6284.148" + cell $and $and$ls180.v:6284$1833 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6232$1765_Y - connect \B $eq$ls180.v:6232$1766_Y - connect \Y $and$ls180.v:6232$1767_Y + connect \A $and$ls180.v:6284$1831_Y + connect \B $eq$ls180.v:6284$1832_Y + connect \Y $and$ls180.v:6284$1833_Y end - attribute \src "ls180.v:6234.42-6234.95" - cell $and $and$ls180.v:6234$1768 + attribute \src "ls180.v:6286.42-6286.95" + cell $and $and$ls180.v:6286$1834 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -244022,43 +244890,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6234$1768_Y + connect \Y $and$ls180.v:6286$1834_Y end - attribute \src "ls180.v:6234.41-6234.145" - cell $and $and$ls180.v:6234$1770 + attribute \src "ls180.v:6286.41-6286.145" + cell $and $and$ls180.v:6286$1836 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6234$1768_Y - connect \B $eq$ls180.v:6234$1769_Y - connect \Y $and$ls180.v:6234$1770_Y + connect \A $and$ls180.v:6286$1834_Y + connect \B $eq$ls180.v:6286$1835_Y + connect \Y $and$ls180.v:6286$1836_Y end - attribute \src "ls180.v:6235.42-6235.98" - cell $and $and$ls180.v:6235$1772 + attribute \src "ls180.v:6287.42-6287.98" + cell $and $and$ls180.v:6287$1838 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6235$1771_Y - connect \Y $and$ls180.v:6235$1772_Y + connect \B $not$ls180.v:6287$1837_Y + connect \Y $and$ls180.v:6287$1838_Y end - attribute \src "ls180.v:6235.41-6235.148" - cell $and $and$ls180.v:6235$1774 + attribute \src "ls180.v:6287.41-6287.148" + cell $and $and$ls180.v:6287$1840 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6235$1772_Y - connect \B $eq$ls180.v:6235$1773_Y - connect \Y $and$ls180.v:6235$1774_Y + connect \A $and$ls180.v:6287$1838_Y + connect \B $eq$ls180.v:6287$1839_Y + connect \Y $and$ls180.v:6287$1840_Y end - attribute \src "ls180.v:6237.42-6237.95" - cell $and $and$ls180.v:6237$1775 + attribute \src "ls180.v:6289.42-6289.95" + cell $and $and$ls180.v:6289$1841 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -244066,43 +244934,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6237$1775_Y + connect \Y $and$ls180.v:6289$1841_Y end - attribute \src "ls180.v:6237.41-6237.145" - cell $and $and$ls180.v:6237$1777 + attribute \src "ls180.v:6289.41-6289.145" + cell $and $and$ls180.v:6289$1843 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6237$1775_Y - connect \B $eq$ls180.v:6237$1776_Y - connect \Y $and$ls180.v:6237$1777_Y + connect \A $and$ls180.v:6289$1841_Y + connect \B $eq$ls180.v:6289$1842_Y + connect \Y $and$ls180.v:6289$1843_Y end - attribute \src "ls180.v:6238.42-6238.98" - cell $and $and$ls180.v:6238$1779 + attribute \src "ls180.v:6290.42-6290.98" + cell $and $and$ls180.v:6290$1845 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6238$1778_Y - connect \Y $and$ls180.v:6238$1779_Y + connect \B $not$ls180.v:6290$1844_Y + connect \Y $and$ls180.v:6290$1845_Y end - attribute \src "ls180.v:6238.41-6238.148" - cell $and $and$ls180.v:6238$1781 + attribute \src "ls180.v:6290.41-6290.148" + cell $and $and$ls180.v:6290$1847 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6238$1779_Y - connect \B $eq$ls180.v:6238$1780_Y - connect \Y $and$ls180.v:6238$1781_Y + connect \A $and$ls180.v:6290$1845_Y + connect \B $eq$ls180.v:6290$1846_Y + connect \Y $and$ls180.v:6290$1847_Y end - attribute \src "ls180.v:6240.42-6240.95" - cell $and $and$ls180.v:6240$1782 + attribute \src "ls180.v:6292.42-6292.95" + cell $and $and$ls180.v:6292$1848 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -244110,43 +244978,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6240$1782_Y + connect \Y $and$ls180.v:6292$1848_Y end - attribute \src "ls180.v:6240.41-6240.145" - cell $and $and$ls180.v:6240$1784 + attribute \src "ls180.v:6292.41-6292.145" + cell $and $and$ls180.v:6292$1850 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6240$1782_Y - connect \B $eq$ls180.v:6240$1783_Y - connect \Y $and$ls180.v:6240$1784_Y + connect \A $and$ls180.v:6292$1848_Y + connect \B $eq$ls180.v:6292$1849_Y + connect \Y $and$ls180.v:6292$1850_Y end - attribute \src "ls180.v:6241.42-6241.98" - cell $and $and$ls180.v:6241$1786 + attribute \src "ls180.v:6293.42-6293.98" + cell $and $and$ls180.v:6293$1852 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6241$1785_Y - connect \Y $and$ls180.v:6241$1786_Y + connect \B $not$ls180.v:6293$1851_Y + connect \Y $and$ls180.v:6293$1852_Y end - attribute \src "ls180.v:6241.41-6241.148" - cell $and $and$ls180.v:6241$1788 + attribute \src "ls180.v:6293.41-6293.148" + cell $and $and$ls180.v:6293$1854 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6241$1786_Y - connect \B $eq$ls180.v:6241$1787_Y - connect \Y $and$ls180.v:6241$1788_Y + connect \A $and$ls180.v:6293$1852_Y + connect \B $eq$ls180.v:6293$1853_Y + connect \Y $and$ls180.v:6293$1854_Y end - attribute \src "ls180.v:6243.42-6243.95" - cell $and $and$ls180.v:6243$1789 + attribute \src "ls180.v:6295.42-6295.95" + cell $and $and$ls180.v:6295$1855 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -244154,43 +245022,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6243$1789_Y + connect \Y $and$ls180.v:6295$1855_Y end - attribute \src "ls180.v:6243.41-6243.145" - cell $and $and$ls180.v:6243$1791 + attribute \src "ls180.v:6295.41-6295.145" + cell $and $and$ls180.v:6295$1857 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6243$1789_Y - connect \B $eq$ls180.v:6243$1790_Y - connect \Y $and$ls180.v:6243$1791_Y + connect \A $and$ls180.v:6295$1855_Y + connect \B $eq$ls180.v:6295$1856_Y + connect \Y $and$ls180.v:6295$1857_Y end - attribute \src "ls180.v:6244.42-6244.98" - cell $and $and$ls180.v:6244$1793 + attribute \src "ls180.v:6296.42-6296.98" + cell $and $and$ls180.v:6296$1859 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6244$1792_Y - connect \Y $and$ls180.v:6244$1793_Y + connect \B $not$ls180.v:6296$1858_Y + connect \Y $and$ls180.v:6296$1859_Y end - attribute \src "ls180.v:6244.41-6244.148" - cell $and $and$ls180.v:6244$1795 + attribute \src "ls180.v:6296.41-6296.148" + cell $and $and$ls180.v:6296$1861 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6244$1793_Y - connect \B $eq$ls180.v:6244$1794_Y - connect \Y $and$ls180.v:6244$1795_Y + connect \A $and$ls180.v:6296$1859_Y + connect \B $eq$ls180.v:6296$1860_Y + connect \Y $and$ls180.v:6296$1861_Y end - attribute \src "ls180.v:6246.44-6246.97" - cell $and $and$ls180.v:6246$1796 + attribute \src "ls180.v:6298.44-6298.97" + cell $and $and$ls180.v:6298$1862 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -244198,43 +245066,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6246$1796_Y + connect \Y $and$ls180.v:6298$1862_Y end - attribute \src "ls180.v:6246.43-6246.147" - cell $and $and$ls180.v:6246$1798 + attribute \src "ls180.v:6298.43-6298.147" + cell $and $and$ls180.v:6298$1864 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6246$1796_Y - connect \B $eq$ls180.v:6246$1797_Y - connect \Y $and$ls180.v:6246$1798_Y + connect \A $and$ls180.v:6298$1862_Y + connect \B $eq$ls180.v:6298$1863_Y + connect \Y $and$ls180.v:6298$1864_Y end - attribute \src "ls180.v:6247.44-6247.100" - cell $and $and$ls180.v:6247$1800 + attribute \src "ls180.v:6299.44-6299.100" + cell $and $and$ls180.v:6299$1866 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6247$1799_Y - connect \Y $and$ls180.v:6247$1800_Y + connect \B $not$ls180.v:6299$1865_Y + connect \Y $and$ls180.v:6299$1866_Y end - attribute \src "ls180.v:6247.43-6247.150" - cell $and $and$ls180.v:6247$1802 + attribute \src "ls180.v:6299.43-6299.150" + cell $and $and$ls180.v:6299$1868 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6247$1800_Y - connect \B $eq$ls180.v:6247$1801_Y - connect \Y $and$ls180.v:6247$1802_Y + connect \A $and$ls180.v:6299$1866_Y + connect \B $eq$ls180.v:6299$1867_Y + connect \Y $and$ls180.v:6299$1868_Y end - attribute \src "ls180.v:6249.44-6249.97" - cell $and $and$ls180.v:6249$1803 + attribute \src "ls180.v:6301.44-6301.97" + cell $and $and$ls180.v:6301$1869 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -244242,43 +245110,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6249$1803_Y + connect \Y $and$ls180.v:6301$1869_Y end - attribute \src "ls180.v:6249.43-6249.147" - cell $and $and$ls180.v:6249$1805 + attribute \src "ls180.v:6301.43-6301.147" + cell $and $and$ls180.v:6301$1871 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6249$1803_Y - connect \B $eq$ls180.v:6249$1804_Y - connect \Y $and$ls180.v:6249$1805_Y + connect \A $and$ls180.v:6301$1869_Y + connect \B $eq$ls180.v:6301$1870_Y + connect \Y $and$ls180.v:6301$1871_Y end - attribute \src "ls180.v:6250.44-6250.100" - cell $and $and$ls180.v:6250$1807 + attribute \src "ls180.v:6302.44-6302.100" + cell $and $and$ls180.v:6302$1873 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6250$1806_Y - connect \Y $and$ls180.v:6250$1807_Y + connect \B $not$ls180.v:6302$1872_Y + connect \Y $and$ls180.v:6302$1873_Y end - attribute \src "ls180.v:6250.43-6250.150" - cell $and $and$ls180.v:6250$1809 + attribute \src "ls180.v:6302.43-6302.150" + cell $and $and$ls180.v:6302$1875 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6250$1807_Y - connect \B $eq$ls180.v:6250$1808_Y - connect \Y $and$ls180.v:6250$1809_Y + connect \A $and$ls180.v:6302$1873_Y + connect \B $eq$ls180.v:6302$1874_Y + connect \Y $and$ls180.v:6302$1875_Y end - attribute \src "ls180.v:6252.44-6252.97" - cell $and $and$ls180.v:6252$1810 + attribute \src "ls180.v:6304.44-6304.97" + cell $and $and$ls180.v:6304$1876 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -244286,43 +245154,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6252$1810_Y + connect \Y $and$ls180.v:6304$1876_Y end - attribute \src "ls180.v:6252.43-6252.148" - cell $and $and$ls180.v:6252$1812 + attribute \src "ls180.v:6304.43-6304.148" + cell $and $and$ls180.v:6304$1878 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6252$1810_Y - connect \B $eq$ls180.v:6252$1811_Y - connect \Y $and$ls180.v:6252$1812_Y + connect \A $and$ls180.v:6304$1876_Y + connect \B $eq$ls180.v:6304$1877_Y + connect \Y $and$ls180.v:6304$1878_Y end - attribute \src "ls180.v:6253.44-6253.100" - cell $and $and$ls180.v:6253$1814 + attribute \src "ls180.v:6305.44-6305.100" + cell $and $and$ls180.v:6305$1880 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6253$1813_Y - connect \Y $and$ls180.v:6253$1814_Y + connect \B $not$ls180.v:6305$1879_Y + connect \Y $and$ls180.v:6305$1880_Y end - attribute \src "ls180.v:6253.43-6253.151" - cell $and $and$ls180.v:6253$1816 + attribute \src "ls180.v:6305.43-6305.151" + cell $and $and$ls180.v:6305$1882 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6253$1814_Y - connect \B $eq$ls180.v:6253$1815_Y - connect \Y $and$ls180.v:6253$1816_Y + connect \A $and$ls180.v:6305$1880_Y + connect \B $eq$ls180.v:6305$1881_Y + connect \Y $and$ls180.v:6305$1882_Y end - attribute \src "ls180.v:6255.44-6255.97" - cell $and $and$ls180.v:6255$1817 + attribute \src "ls180.v:6307.44-6307.97" + cell $and $and$ls180.v:6307$1883 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -244330,43 +245198,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6255$1817_Y + connect \Y $and$ls180.v:6307$1883_Y end - attribute \src "ls180.v:6255.43-6255.148" - cell $and $and$ls180.v:6255$1819 + attribute \src "ls180.v:6307.43-6307.148" + cell $and $and$ls180.v:6307$1885 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6255$1817_Y - connect \B $eq$ls180.v:6255$1818_Y - connect \Y $and$ls180.v:6255$1819_Y + connect \A $and$ls180.v:6307$1883_Y + connect \B $eq$ls180.v:6307$1884_Y + connect \Y $and$ls180.v:6307$1885_Y end - attribute \src "ls180.v:6256.44-6256.100" - cell $and $and$ls180.v:6256$1821 + attribute \src "ls180.v:6308.44-6308.100" + cell $and $and$ls180.v:6308$1887 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6256$1820_Y - connect \Y $and$ls180.v:6256$1821_Y + connect \B $not$ls180.v:6308$1886_Y + connect \Y $and$ls180.v:6308$1887_Y end - attribute \src "ls180.v:6256.43-6256.151" - cell $and $and$ls180.v:6256$1823 + attribute \src "ls180.v:6308.43-6308.151" + cell $and $and$ls180.v:6308$1889 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6256$1821_Y - connect \B $eq$ls180.v:6256$1822_Y - connect \Y $and$ls180.v:6256$1823_Y + connect \A $and$ls180.v:6308$1887_Y + connect \B $eq$ls180.v:6308$1888_Y + connect \Y $and$ls180.v:6308$1889_Y end - attribute \src "ls180.v:6258.44-6258.97" - cell $and $and$ls180.v:6258$1824 + attribute \src "ls180.v:6310.44-6310.97" + cell $and $and$ls180.v:6310$1890 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -244374,43 +245242,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6258$1824_Y + connect \Y $and$ls180.v:6310$1890_Y end - attribute \src "ls180.v:6258.43-6258.148" - cell $and $and$ls180.v:6258$1826 + attribute \src "ls180.v:6310.43-6310.148" + cell $and $and$ls180.v:6310$1892 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6258$1824_Y - connect \B $eq$ls180.v:6258$1825_Y - connect \Y $and$ls180.v:6258$1826_Y + connect \A $and$ls180.v:6310$1890_Y + connect \B $eq$ls180.v:6310$1891_Y + connect \Y $and$ls180.v:6310$1892_Y end - attribute \src "ls180.v:6259.44-6259.100" - cell $and $and$ls180.v:6259$1828 + attribute \src "ls180.v:6311.44-6311.100" + cell $and $and$ls180.v:6311$1894 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6259$1827_Y - connect \Y $and$ls180.v:6259$1828_Y + connect \B $not$ls180.v:6311$1893_Y + connect \Y $and$ls180.v:6311$1894_Y end - attribute \src "ls180.v:6259.43-6259.151" - cell $and $and$ls180.v:6259$1830 + attribute \src "ls180.v:6311.43-6311.151" + cell $and $and$ls180.v:6311$1896 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6259$1828_Y - connect \B $eq$ls180.v:6259$1829_Y - connect \Y $and$ls180.v:6259$1830_Y + connect \A $and$ls180.v:6311$1894_Y + connect \B $eq$ls180.v:6311$1895_Y + connect \Y $and$ls180.v:6311$1896_Y end - attribute \src "ls180.v:6261.41-6261.94" - cell $and $and$ls180.v:6261$1831 + attribute \src "ls180.v:6313.41-6313.94" + cell $and $and$ls180.v:6313$1897 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -244418,43 +245286,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6261$1831_Y + connect \Y $and$ls180.v:6313$1897_Y end - attribute \src "ls180.v:6261.40-6261.145" - cell $and $and$ls180.v:6261$1833 + attribute \src "ls180.v:6313.40-6313.145" + cell $and $and$ls180.v:6313$1899 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6261$1831_Y - connect \B $eq$ls180.v:6261$1832_Y - connect \Y $and$ls180.v:6261$1833_Y + connect \A $and$ls180.v:6313$1897_Y + connect \B $eq$ls180.v:6313$1898_Y + connect \Y $and$ls180.v:6313$1899_Y end - attribute \src "ls180.v:6262.41-6262.97" - cell $and $and$ls180.v:6262$1835 + attribute \src "ls180.v:6314.41-6314.97" + cell $and $and$ls180.v:6314$1901 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6262$1834_Y - connect \Y $and$ls180.v:6262$1835_Y + connect \B $not$ls180.v:6314$1900_Y + connect \Y $and$ls180.v:6314$1901_Y end - attribute \src "ls180.v:6262.40-6262.148" - cell $and $and$ls180.v:6262$1837 + attribute \src "ls180.v:6314.40-6314.148" + cell $and $and$ls180.v:6314$1903 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6262$1835_Y - connect \B $eq$ls180.v:6262$1836_Y - connect \Y $and$ls180.v:6262$1837_Y + connect \A $and$ls180.v:6314$1901_Y + connect \B $eq$ls180.v:6314$1902_Y + connect \Y $and$ls180.v:6314$1903_Y end - attribute \src "ls180.v:6264.42-6264.95" - cell $and $and$ls180.v:6264$1838 + attribute \src "ls180.v:6316.42-6316.95" + cell $and $and$ls180.v:6316$1904 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -244462,43 +245330,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6264$1838_Y + connect \Y $and$ls180.v:6316$1904_Y end - attribute \src "ls180.v:6264.41-6264.146" - cell $and $and$ls180.v:6264$1840 + attribute \src "ls180.v:6316.41-6316.146" + cell $and $and$ls180.v:6316$1906 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6264$1838_Y - connect \B $eq$ls180.v:6264$1839_Y - connect \Y $and$ls180.v:6264$1840_Y + connect \A $and$ls180.v:6316$1904_Y + connect \B $eq$ls180.v:6316$1905_Y + connect \Y $and$ls180.v:6316$1906_Y end - attribute \src "ls180.v:6265.42-6265.98" - cell $and $and$ls180.v:6265$1842 + attribute \src "ls180.v:6317.42-6317.98" + cell $and $and$ls180.v:6317$1908 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6265$1841_Y - connect \Y $and$ls180.v:6265$1842_Y + connect \B $not$ls180.v:6317$1907_Y + connect \Y $and$ls180.v:6317$1908_Y end - attribute \src "ls180.v:6265.41-6265.149" - cell $and $and$ls180.v:6265$1844 + attribute \src "ls180.v:6317.41-6317.149" + cell $and $and$ls180.v:6317$1910 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6265$1842_Y - connect \B $eq$ls180.v:6265$1843_Y - connect \Y $and$ls180.v:6265$1844_Y + connect \A $and$ls180.v:6317$1908_Y + connect \B $eq$ls180.v:6317$1909_Y + connect \Y $and$ls180.v:6317$1910_Y end - attribute \src "ls180.v:6267.44-6267.97" - cell $and $and$ls180.v:6267$1845 + attribute \src "ls180.v:6319.44-6319.97" + cell $and $and$ls180.v:6319$1911 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -244506,43 +245374,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6267$1845_Y + connect \Y $and$ls180.v:6319$1911_Y end - attribute \src "ls180.v:6267.43-6267.148" - cell $and $and$ls180.v:6267$1847 + attribute \src "ls180.v:6319.43-6319.148" + cell $and $and$ls180.v:6319$1913 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6267$1845_Y - connect \B $eq$ls180.v:6267$1846_Y - connect \Y $and$ls180.v:6267$1847_Y + connect \A $and$ls180.v:6319$1911_Y + connect \B $eq$ls180.v:6319$1912_Y + connect \Y $and$ls180.v:6319$1913_Y end - attribute \src "ls180.v:6268.44-6268.100" - cell $and $and$ls180.v:6268$1849 + attribute \src "ls180.v:6320.44-6320.100" + cell $and $and$ls180.v:6320$1915 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6268$1848_Y - connect \Y $and$ls180.v:6268$1849_Y + connect \B $not$ls180.v:6320$1914_Y + connect \Y $and$ls180.v:6320$1915_Y end - attribute \src "ls180.v:6268.43-6268.151" - cell $and $and$ls180.v:6268$1851 + attribute \src "ls180.v:6320.43-6320.151" + cell $and $and$ls180.v:6320$1917 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6268$1849_Y - connect \B $eq$ls180.v:6268$1850_Y - connect \Y $and$ls180.v:6268$1851_Y + connect \A $and$ls180.v:6320$1915_Y + connect \B $eq$ls180.v:6320$1916_Y + connect \Y $and$ls180.v:6320$1917_Y end - attribute \src "ls180.v:6270.44-6270.97" - cell $and $and$ls180.v:6270$1852 + attribute \src "ls180.v:6322.44-6322.97" + cell $and $and$ls180.v:6322$1918 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -244550,43 +245418,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6270$1852_Y + connect \Y $and$ls180.v:6322$1918_Y end - attribute \src "ls180.v:6270.43-6270.148" - cell $and $and$ls180.v:6270$1854 + attribute \src "ls180.v:6322.43-6322.148" + cell $and $and$ls180.v:6322$1920 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6270$1852_Y - connect \B $eq$ls180.v:6270$1853_Y - connect \Y $and$ls180.v:6270$1854_Y + connect \A $and$ls180.v:6322$1918_Y + connect \B $eq$ls180.v:6322$1919_Y + connect \Y $and$ls180.v:6322$1920_Y end - attribute \src "ls180.v:6271.44-6271.100" - cell $and $and$ls180.v:6271$1856 + attribute \src "ls180.v:6323.44-6323.100" + cell $and $and$ls180.v:6323$1922 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6271$1855_Y - connect \Y $and$ls180.v:6271$1856_Y + connect \B $not$ls180.v:6323$1921_Y + connect \Y $and$ls180.v:6323$1922_Y end - attribute \src "ls180.v:6271.43-6271.151" - cell $and $and$ls180.v:6271$1858 + attribute \src "ls180.v:6323.43-6323.151" + cell $and $and$ls180.v:6323$1924 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6271$1856_Y - connect \B $eq$ls180.v:6271$1857_Y - connect \Y $and$ls180.v:6271$1858_Y + connect \A $and$ls180.v:6323$1922_Y + connect \B $eq$ls180.v:6323$1923_Y + connect \Y $and$ls180.v:6323$1924_Y end - attribute \src "ls180.v:6273.44-6273.97" - cell $and $and$ls180.v:6273$1859 + attribute \src "ls180.v:6325.44-6325.97" + cell $and $and$ls180.v:6325$1925 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -244594,43 +245462,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6273$1859_Y + connect \Y $and$ls180.v:6325$1925_Y end - attribute \src "ls180.v:6273.43-6273.148" - cell $and $and$ls180.v:6273$1861 + attribute \src "ls180.v:6325.43-6325.148" + cell $and $and$ls180.v:6325$1927 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6273$1859_Y - connect \B $eq$ls180.v:6273$1860_Y - connect \Y $and$ls180.v:6273$1861_Y + connect \A $and$ls180.v:6325$1925_Y + connect \B $eq$ls180.v:6325$1926_Y + connect \Y $and$ls180.v:6325$1927_Y end - attribute \src "ls180.v:6274.44-6274.100" - cell $and $and$ls180.v:6274$1863 + attribute \src "ls180.v:6326.44-6326.100" + cell $and $and$ls180.v:6326$1929 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6274$1862_Y - connect \Y $and$ls180.v:6274$1863_Y + connect \B $not$ls180.v:6326$1928_Y + connect \Y $and$ls180.v:6326$1929_Y end - attribute \src "ls180.v:6274.43-6274.151" - cell $and $and$ls180.v:6274$1865 + attribute \src "ls180.v:6326.43-6326.151" + cell $and $and$ls180.v:6326$1931 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6274$1863_Y - connect \B $eq$ls180.v:6274$1864_Y - connect \Y $and$ls180.v:6274$1865_Y + connect \A $and$ls180.v:6326$1929_Y + connect \B $eq$ls180.v:6326$1930_Y + connect \Y $and$ls180.v:6326$1931_Y end - attribute \src "ls180.v:6276.44-6276.97" - cell $and $and$ls180.v:6276$1866 + attribute \src "ls180.v:6328.44-6328.97" + cell $and $and$ls180.v:6328$1932 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -244638,43 +245506,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6276$1866_Y + connect \Y $and$ls180.v:6328$1932_Y end - attribute \src "ls180.v:6276.43-6276.148" - cell $and $and$ls180.v:6276$1868 + attribute \src "ls180.v:6328.43-6328.148" + cell $and $and$ls180.v:6328$1934 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6276$1866_Y - connect \B $eq$ls180.v:6276$1867_Y - connect \Y $and$ls180.v:6276$1868_Y + connect \A $and$ls180.v:6328$1932_Y + connect \B $eq$ls180.v:6328$1933_Y + connect \Y $and$ls180.v:6328$1934_Y end - attribute \src "ls180.v:6277.44-6277.100" - cell $and $and$ls180.v:6277$1870 + attribute \src "ls180.v:6329.44-6329.100" + cell $and $and$ls180.v:6329$1936 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6277$1869_Y - connect \Y $and$ls180.v:6277$1870_Y + connect \B $not$ls180.v:6329$1935_Y + connect \Y $and$ls180.v:6329$1936_Y end - attribute \src "ls180.v:6277.43-6277.151" - cell $and $and$ls180.v:6277$1872 + attribute \src "ls180.v:6329.43-6329.151" + cell $and $and$ls180.v:6329$1938 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6277$1870_Y - connect \B $eq$ls180.v:6277$1871_Y - connect \Y $and$ls180.v:6277$1872_Y + connect \A $and$ls180.v:6329$1936_Y + connect \B $eq$ls180.v:6329$1937_Y + connect \Y $and$ls180.v:6329$1938_Y end - attribute \src "ls180.v:6301.44-6301.97" - cell $and $and$ls180.v:6301$1874 + attribute \src "ls180.v:6353.44-6353.97" + cell $and $and$ls180.v:6353$1940 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -244682,43 +245550,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank8_sel connect \B \builder_interface8_bank_bus_we - connect \Y $and$ls180.v:6301$1874_Y + connect \Y $and$ls180.v:6353$1940_Y end - attribute \src "ls180.v:6301.43-6301.147" - cell $and $and$ls180.v:6301$1876 + attribute \src "ls180.v:6353.43-6353.147" + cell $and $and$ls180.v:6353$1942 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6301$1874_Y - connect \B $eq$ls180.v:6301$1875_Y - connect \Y $and$ls180.v:6301$1876_Y + connect \A $and$ls180.v:6353$1940_Y + connect \B $eq$ls180.v:6353$1941_Y + connect \Y $and$ls180.v:6353$1942_Y end - attribute \src "ls180.v:6302.44-6302.100" - cell $and $and$ls180.v:6302$1878 + attribute \src "ls180.v:6354.44-6354.100" + cell $and $and$ls180.v:6354$1944 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank8_sel - connect \B $not$ls180.v:6302$1877_Y - connect \Y $and$ls180.v:6302$1878_Y + connect \B $not$ls180.v:6354$1943_Y + connect \Y $and$ls180.v:6354$1944_Y end - attribute \src "ls180.v:6302.43-6302.150" - cell $and $and$ls180.v:6302$1880 + attribute \src "ls180.v:6354.43-6354.150" + cell $and $and$ls180.v:6354$1946 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6302$1878_Y - connect \B $eq$ls180.v:6302$1879_Y - connect \Y $and$ls180.v:6302$1880_Y + connect \A $and$ls180.v:6354$1944_Y + connect \B $eq$ls180.v:6354$1945_Y + connect \Y $and$ls180.v:6354$1946_Y end - attribute \src "ls180.v:6304.49-6304.102" - cell $and $and$ls180.v:6304$1881 + attribute \src "ls180.v:6356.49-6356.102" + cell $and $and$ls180.v:6356$1947 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -244726,43 +245594,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank8_sel connect \B \builder_interface8_bank_bus_we - connect \Y $and$ls180.v:6304$1881_Y + connect \Y $and$ls180.v:6356$1947_Y end - attribute \src "ls180.v:6304.48-6304.152" - cell $and $and$ls180.v:6304$1883 + attribute \src "ls180.v:6356.48-6356.152" + cell $and $and$ls180.v:6356$1949 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6304$1881_Y - connect \B $eq$ls180.v:6304$1882_Y - connect \Y $and$ls180.v:6304$1883_Y + connect \A $and$ls180.v:6356$1947_Y + connect \B $eq$ls180.v:6356$1948_Y + connect \Y $and$ls180.v:6356$1949_Y end - attribute \src "ls180.v:6305.49-6305.105" - cell $and $and$ls180.v:6305$1885 + attribute \src "ls180.v:6357.49-6357.105" + cell $and $and$ls180.v:6357$1951 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank8_sel - connect \B $not$ls180.v:6305$1884_Y - connect \Y $and$ls180.v:6305$1885_Y + connect \B $not$ls180.v:6357$1950_Y + connect \Y $and$ls180.v:6357$1951_Y end - attribute \src "ls180.v:6305.48-6305.155" - cell $and $and$ls180.v:6305$1887 + attribute \src "ls180.v:6357.48-6357.155" + cell $and $and$ls180.v:6357$1953 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6305$1885_Y - connect \B $eq$ls180.v:6305$1886_Y - connect \Y $and$ls180.v:6305$1887_Y + connect \A $and$ls180.v:6357$1951_Y + connect \B $eq$ls180.v:6357$1952_Y + connect \Y $and$ls180.v:6357$1953_Y end - attribute \src "ls180.v:6307.49-6307.102" - cell $and $and$ls180.v:6307$1888 + attribute \src "ls180.v:6359.49-6359.102" + cell $and $and$ls180.v:6359$1954 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -244770,43 +245638,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank8_sel connect \B \builder_interface8_bank_bus_we - connect \Y $and$ls180.v:6307$1888_Y + connect \Y $and$ls180.v:6359$1954_Y end - attribute \src "ls180.v:6307.48-6307.152" - cell $and $and$ls180.v:6307$1890 + attribute \src "ls180.v:6359.48-6359.152" + cell $and $and$ls180.v:6359$1956 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6307$1888_Y - connect \B $eq$ls180.v:6307$1889_Y - connect \Y $and$ls180.v:6307$1890_Y + connect \A $and$ls180.v:6359$1954_Y + connect \B $eq$ls180.v:6359$1955_Y + connect \Y $and$ls180.v:6359$1956_Y end - attribute \src "ls180.v:6308.49-6308.105" - cell $and $and$ls180.v:6308$1892 + attribute \src "ls180.v:6360.49-6360.105" + cell $and $and$ls180.v:6360$1958 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank8_sel - connect \B $not$ls180.v:6308$1891_Y - connect \Y $and$ls180.v:6308$1892_Y + connect \B $not$ls180.v:6360$1957_Y + connect \Y $and$ls180.v:6360$1958_Y end - attribute \src "ls180.v:6308.48-6308.155" - cell $and $and$ls180.v:6308$1894 + attribute \src "ls180.v:6360.48-6360.155" + cell $and $and$ls180.v:6360$1960 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6308$1892_Y - connect \B $eq$ls180.v:6308$1893_Y - connect \Y $and$ls180.v:6308$1894_Y + connect \A $and$ls180.v:6360$1958_Y + connect \B $eq$ls180.v:6360$1959_Y + connect \Y $and$ls180.v:6360$1960_Y end - attribute \src "ls180.v:6310.42-6310.95" - cell $and $and$ls180.v:6310$1895 + attribute \src "ls180.v:6362.42-6362.95" + cell $and $and$ls180.v:6362$1961 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -244814,43 +245682,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank8_sel connect \B \builder_interface8_bank_bus_we - connect \Y $and$ls180.v:6310$1895_Y + connect \Y $and$ls180.v:6362$1961_Y end - attribute \src "ls180.v:6310.41-6310.145" - cell $and $and$ls180.v:6310$1897 + attribute \src "ls180.v:6362.41-6362.145" + cell $and $and$ls180.v:6362$1963 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6310$1895_Y - connect \B $eq$ls180.v:6310$1896_Y - connect \Y $and$ls180.v:6310$1897_Y + connect \A $and$ls180.v:6362$1961_Y + connect \B $eq$ls180.v:6362$1962_Y + connect \Y $and$ls180.v:6362$1963_Y end - attribute \src "ls180.v:6311.42-6311.98" - cell $and $and$ls180.v:6311$1899 + attribute \src "ls180.v:6363.42-6363.98" + cell $and $and$ls180.v:6363$1965 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank8_sel - connect \B $not$ls180.v:6311$1898_Y - connect \Y $and$ls180.v:6311$1899_Y + connect \B $not$ls180.v:6363$1964_Y + connect \Y $and$ls180.v:6363$1965_Y end - attribute \src "ls180.v:6311.41-6311.148" - cell $and $and$ls180.v:6311$1901 + attribute \src "ls180.v:6363.41-6363.148" + cell $and $and$ls180.v:6363$1967 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6311$1899_Y - connect \B $eq$ls180.v:6311$1900_Y - connect \Y $and$ls180.v:6311$1901_Y + connect \A $and$ls180.v:6363$1965_Y + connect \B $eq$ls180.v:6363$1966_Y + connect \Y $and$ls180.v:6363$1967_Y end - attribute \src "ls180.v:6318.46-6318.99" - cell $and $and$ls180.v:6318$1903 + attribute \src "ls180.v:6370.46-6370.99" + cell $and $and$ls180.v:6370$1969 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -244858,43 +245726,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6318$1903_Y + connect \Y $and$ls180.v:6370$1969_Y end - attribute \src "ls180.v:6318.45-6318.149" - cell $and $and$ls180.v:6318$1905 + attribute \src "ls180.v:6370.45-6370.149" + cell $and $and$ls180.v:6370$1971 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6318$1903_Y - connect \B $eq$ls180.v:6318$1904_Y - connect \Y $and$ls180.v:6318$1905_Y + connect \A $and$ls180.v:6370$1969_Y + connect \B $eq$ls180.v:6370$1970_Y + connect \Y $and$ls180.v:6370$1971_Y end - attribute \src "ls180.v:6319.46-6319.102" - cell $and $and$ls180.v:6319$1907 + attribute \src "ls180.v:6371.46-6371.102" + cell $and $and$ls180.v:6371$1973 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6319$1906_Y - connect \Y $and$ls180.v:6319$1907_Y + connect \B $not$ls180.v:6371$1972_Y + connect \Y $and$ls180.v:6371$1973_Y end - attribute \src "ls180.v:6319.45-6319.152" - cell $and $and$ls180.v:6319$1909 + attribute \src "ls180.v:6371.45-6371.152" + cell $and $and$ls180.v:6371$1975 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6319$1907_Y - connect \B $eq$ls180.v:6319$1908_Y - connect \Y $and$ls180.v:6319$1909_Y + connect \A $and$ls180.v:6371$1973_Y + connect \B $eq$ls180.v:6371$1974_Y + connect \Y $and$ls180.v:6371$1975_Y end - attribute \src "ls180.v:6321.50-6321.103" - cell $and $and$ls180.v:6321$1910 + attribute \src "ls180.v:6373.50-6373.103" + cell $and $and$ls180.v:6373$1976 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -244902,43 +245770,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6321$1910_Y + connect \Y $and$ls180.v:6373$1976_Y end - attribute \src "ls180.v:6321.49-6321.153" - cell $and $and$ls180.v:6321$1912 + attribute \src "ls180.v:6373.49-6373.153" + cell $and $and$ls180.v:6373$1978 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6321$1910_Y - connect \B $eq$ls180.v:6321$1911_Y - connect \Y $and$ls180.v:6321$1912_Y + connect \A $and$ls180.v:6373$1976_Y + connect \B $eq$ls180.v:6373$1977_Y + connect \Y $and$ls180.v:6373$1978_Y end - attribute \src "ls180.v:6322.50-6322.106" - cell $and $and$ls180.v:6322$1914 + attribute \src "ls180.v:6374.50-6374.106" + cell $and $and$ls180.v:6374$1980 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6322$1913_Y - connect \Y $and$ls180.v:6322$1914_Y + connect \B $not$ls180.v:6374$1979_Y + connect \Y $and$ls180.v:6374$1980_Y end - attribute \src "ls180.v:6322.49-6322.156" - cell $and $and$ls180.v:6322$1916 + attribute \src "ls180.v:6374.49-6374.156" + cell $and $and$ls180.v:6374$1982 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6322$1914_Y - connect \B $eq$ls180.v:6322$1915_Y - connect \Y $and$ls180.v:6322$1916_Y + connect \A $and$ls180.v:6374$1980_Y + connect \B $eq$ls180.v:6374$1981_Y + connect \Y $and$ls180.v:6374$1982_Y end - attribute \src "ls180.v:6324.40-6324.93" - cell $and $and$ls180.v:6324$1917 + attribute \src "ls180.v:6376.40-6376.93" + cell $and $and$ls180.v:6376$1983 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -244946,43 +245814,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6324$1917_Y + connect \Y $and$ls180.v:6376$1983_Y end - attribute \src "ls180.v:6324.39-6324.143" - cell $and $and$ls180.v:6324$1919 + attribute \src "ls180.v:6376.39-6376.143" + cell $and $and$ls180.v:6376$1985 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6324$1917_Y - connect \B $eq$ls180.v:6324$1918_Y - connect \Y $and$ls180.v:6324$1919_Y + connect \A $and$ls180.v:6376$1983_Y + connect \B $eq$ls180.v:6376$1984_Y + connect \Y $and$ls180.v:6376$1985_Y end - attribute \src "ls180.v:6325.40-6325.96" - cell $and $and$ls180.v:6325$1921 + attribute \src "ls180.v:6377.40-6377.96" + cell $and $and$ls180.v:6377$1987 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6325$1920_Y - connect \Y $and$ls180.v:6325$1921_Y + connect \B $not$ls180.v:6377$1986_Y + connect \Y $and$ls180.v:6377$1987_Y end - attribute \src "ls180.v:6325.39-6325.146" - cell $and $and$ls180.v:6325$1923 + attribute \src "ls180.v:6377.39-6377.146" + cell $and $and$ls180.v:6377$1989 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6325$1921_Y - connect \B $eq$ls180.v:6325$1922_Y - connect \Y $and$ls180.v:6325$1923_Y + connect \A $and$ls180.v:6377$1987_Y + connect \B $eq$ls180.v:6377$1988_Y + connect \Y $and$ls180.v:6377$1989_Y end - attribute \src "ls180.v:6327.50-6327.103" - cell $and $and$ls180.v:6327$1924 + attribute \src "ls180.v:6379.50-6379.103" + cell $and $and$ls180.v:6379$1990 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -244990,43 +245858,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6327$1924_Y + connect \Y $and$ls180.v:6379$1990_Y end - attribute \src "ls180.v:6327.49-6327.153" - cell $and $and$ls180.v:6327$1926 + attribute \src "ls180.v:6379.49-6379.153" + cell $and $and$ls180.v:6379$1992 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6327$1924_Y - connect \B $eq$ls180.v:6327$1925_Y - connect \Y $and$ls180.v:6327$1926_Y + connect \A $and$ls180.v:6379$1990_Y + connect \B $eq$ls180.v:6379$1991_Y + connect \Y $and$ls180.v:6379$1992_Y end - attribute \src "ls180.v:6328.50-6328.106" - cell $and $and$ls180.v:6328$1928 + attribute \src "ls180.v:6380.50-6380.106" + cell $and $and$ls180.v:6380$1994 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6328$1927_Y - connect \Y $and$ls180.v:6328$1928_Y + connect \B $not$ls180.v:6380$1993_Y + connect \Y $and$ls180.v:6380$1994_Y end - attribute \src "ls180.v:6328.49-6328.156" - cell $and $and$ls180.v:6328$1930 + attribute \src "ls180.v:6380.49-6380.156" + cell $and $and$ls180.v:6380$1996 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6328$1928_Y - connect \B $eq$ls180.v:6328$1929_Y - connect \Y $and$ls180.v:6328$1930_Y + connect \A $and$ls180.v:6380$1994_Y + connect \B $eq$ls180.v:6380$1995_Y + connect \Y $and$ls180.v:6380$1996_Y end - attribute \src "ls180.v:6330.50-6330.103" - cell $and $and$ls180.v:6330$1931 + attribute \src "ls180.v:6382.50-6382.103" + cell $and $and$ls180.v:6382$1997 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -245034,43 +245902,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6330$1931_Y + connect \Y $and$ls180.v:6382$1997_Y end - attribute \src "ls180.v:6330.49-6330.153" - cell $and $and$ls180.v:6330$1933 + attribute \src "ls180.v:6382.49-6382.153" + cell $and $and$ls180.v:6382$1999 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6330$1931_Y - connect \B $eq$ls180.v:6330$1932_Y - connect \Y $and$ls180.v:6330$1933_Y + connect \A $and$ls180.v:6382$1997_Y + connect \B $eq$ls180.v:6382$1998_Y + connect \Y $and$ls180.v:6382$1999_Y end - attribute \src "ls180.v:6331.50-6331.106" - cell $and $and$ls180.v:6331$1935 + attribute \src "ls180.v:6383.50-6383.106" + cell $and $and$ls180.v:6383$2001 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6331$1934_Y - connect \Y $and$ls180.v:6331$1935_Y + connect \B $not$ls180.v:6383$2000_Y + connect \Y $and$ls180.v:6383$2001_Y end - attribute \src "ls180.v:6331.49-6331.156" - cell $and $and$ls180.v:6331$1937 + attribute \src "ls180.v:6383.49-6383.156" + cell $and $and$ls180.v:6383$2003 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6331$1935_Y - connect \B $eq$ls180.v:6331$1936_Y - connect \Y $and$ls180.v:6331$1937_Y + connect \A $and$ls180.v:6383$2001_Y + connect \B $eq$ls180.v:6383$2002_Y + connect \Y $and$ls180.v:6383$2003_Y end - attribute \src "ls180.v:6333.51-6333.104" - cell $and $and$ls180.v:6333$1938 + attribute \src "ls180.v:6385.51-6385.104" + cell $and $and$ls180.v:6385$2004 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -245078,43 +245946,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6333$1938_Y + connect \Y $and$ls180.v:6385$2004_Y end - attribute \src "ls180.v:6333.50-6333.154" - cell $and $and$ls180.v:6333$1940 + attribute \src "ls180.v:6385.50-6385.154" + cell $and $and$ls180.v:6385$2006 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6333$1938_Y - connect \B $eq$ls180.v:6333$1939_Y - connect \Y $and$ls180.v:6333$1940_Y + connect \A $and$ls180.v:6385$2004_Y + connect \B $eq$ls180.v:6385$2005_Y + connect \Y $and$ls180.v:6385$2006_Y end - attribute \src "ls180.v:6334.51-6334.107" - cell $and $and$ls180.v:6334$1942 + attribute \src "ls180.v:6386.51-6386.107" + cell $and $and$ls180.v:6386$2008 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6334$1941_Y - connect \Y $and$ls180.v:6334$1942_Y + connect \B $not$ls180.v:6386$2007_Y + connect \Y $and$ls180.v:6386$2008_Y end - attribute \src "ls180.v:6334.50-6334.157" - cell $and $and$ls180.v:6334$1944 + attribute \src "ls180.v:6386.50-6386.157" + cell $and $and$ls180.v:6386$2010 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6334$1942_Y - connect \B $eq$ls180.v:6334$1943_Y - connect \Y $and$ls180.v:6334$1944_Y + connect \A $and$ls180.v:6386$2008_Y + connect \B $eq$ls180.v:6386$2009_Y + connect \Y $and$ls180.v:6386$2010_Y end - attribute \src "ls180.v:6336.49-6336.102" - cell $and $and$ls180.v:6336$1945 + attribute \src "ls180.v:6388.49-6388.102" + cell $and $and$ls180.v:6388$2011 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -245122,43 +245990,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6336$1945_Y + connect \Y $and$ls180.v:6388$2011_Y end - attribute \src "ls180.v:6336.48-6336.152" - cell $and $and$ls180.v:6336$1947 + attribute \src "ls180.v:6388.48-6388.152" + cell $and $and$ls180.v:6388$2013 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6336$1945_Y - connect \B $eq$ls180.v:6336$1946_Y - connect \Y $and$ls180.v:6336$1947_Y + connect \A $and$ls180.v:6388$2011_Y + connect \B $eq$ls180.v:6388$2012_Y + connect \Y $and$ls180.v:6388$2013_Y end - attribute \src "ls180.v:6337.49-6337.105" - cell $and $and$ls180.v:6337$1949 + attribute \src "ls180.v:6389.49-6389.105" + cell $and $and$ls180.v:6389$2015 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6337$1948_Y - connect \Y $and$ls180.v:6337$1949_Y + connect \B $not$ls180.v:6389$2014_Y + connect \Y $and$ls180.v:6389$2015_Y end - attribute \src "ls180.v:6337.48-6337.155" - cell $and $and$ls180.v:6337$1951 + attribute \src "ls180.v:6389.48-6389.155" + cell $and $and$ls180.v:6389$2017 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6337$1949_Y - connect \B $eq$ls180.v:6337$1950_Y - connect \Y $and$ls180.v:6337$1951_Y + connect \A $and$ls180.v:6389$2015_Y + connect \B $eq$ls180.v:6389$2016_Y + connect \Y $and$ls180.v:6389$2017_Y end - attribute \src "ls180.v:6339.49-6339.102" - cell $and $and$ls180.v:6339$1952 + attribute \src "ls180.v:6391.49-6391.102" + cell $and $and$ls180.v:6391$2018 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -245166,43 +246034,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6339$1952_Y + connect \Y $and$ls180.v:6391$2018_Y end - attribute \src "ls180.v:6339.48-6339.152" - cell $and $and$ls180.v:6339$1954 + attribute \src "ls180.v:6391.48-6391.152" + cell $and $and$ls180.v:6391$2020 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6339$1952_Y - connect \B $eq$ls180.v:6339$1953_Y - connect \Y $and$ls180.v:6339$1954_Y + connect \A $and$ls180.v:6391$2018_Y + connect \B $eq$ls180.v:6391$2019_Y + connect \Y $and$ls180.v:6391$2020_Y end - attribute \src "ls180.v:6340.49-6340.105" - cell $and $and$ls180.v:6340$1956 + attribute \src "ls180.v:6392.49-6392.105" + cell $and $and$ls180.v:6392$2022 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6340$1955_Y - connect \Y $and$ls180.v:6340$1956_Y + connect \B $not$ls180.v:6392$2021_Y + connect \Y $and$ls180.v:6392$2022_Y end - attribute \src "ls180.v:6340.48-6340.155" - cell $and $and$ls180.v:6340$1958 + attribute \src "ls180.v:6392.48-6392.155" + cell $and $and$ls180.v:6392$2024 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6340$1956_Y - connect \B $eq$ls180.v:6340$1957_Y - connect \Y $and$ls180.v:6340$1958_Y + connect \A $and$ls180.v:6392$2022_Y + connect \B $eq$ls180.v:6392$2023_Y + connect \Y $and$ls180.v:6392$2024_Y end - attribute \src "ls180.v:6342.49-6342.102" - cell $and $and$ls180.v:6342$1959 + attribute \src "ls180.v:6394.49-6394.102" + cell $and $and$ls180.v:6394$2025 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -245210,43 +246078,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6342$1959_Y + connect \Y $and$ls180.v:6394$2025_Y end - attribute \src "ls180.v:6342.48-6342.152" - cell $and $and$ls180.v:6342$1961 + attribute \src "ls180.v:6394.48-6394.152" + cell $and $and$ls180.v:6394$2027 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6342$1959_Y - connect \B $eq$ls180.v:6342$1960_Y - connect \Y $and$ls180.v:6342$1961_Y + connect \A $and$ls180.v:6394$2025_Y + connect \B $eq$ls180.v:6394$2026_Y + connect \Y $and$ls180.v:6394$2027_Y end - attribute \src "ls180.v:6343.49-6343.105" - cell $and $and$ls180.v:6343$1963 + attribute \src "ls180.v:6395.49-6395.105" + cell $and $and$ls180.v:6395$2029 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6343$1962_Y - connect \Y $and$ls180.v:6343$1963_Y + connect \B $not$ls180.v:6395$2028_Y + connect \Y $and$ls180.v:6395$2029_Y end - attribute \src "ls180.v:6343.48-6343.155" - cell $and $and$ls180.v:6343$1965 + attribute \src "ls180.v:6395.48-6395.155" + cell $and $and$ls180.v:6395$2031 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6343$1963_Y - connect \B $eq$ls180.v:6343$1964_Y - connect \Y $and$ls180.v:6343$1965_Y + connect \A $and$ls180.v:6395$2029_Y + connect \B $eq$ls180.v:6395$2030_Y + connect \Y $and$ls180.v:6395$2031_Y end - attribute \src "ls180.v:6345.49-6345.102" - cell $and $and$ls180.v:6345$1966 + attribute \src "ls180.v:6397.49-6397.102" + cell $and $and$ls180.v:6397$2032 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -245254,43 +246122,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6345$1966_Y + connect \Y $and$ls180.v:6397$2032_Y end - attribute \src "ls180.v:6345.48-6345.152" - cell $and $and$ls180.v:6345$1968 + attribute \src "ls180.v:6397.48-6397.152" + cell $and $and$ls180.v:6397$2034 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6345$1966_Y - connect \B $eq$ls180.v:6345$1967_Y - connect \Y $and$ls180.v:6345$1968_Y + connect \A $and$ls180.v:6397$2032_Y + connect \B $eq$ls180.v:6397$2033_Y + connect \Y $and$ls180.v:6397$2034_Y end - attribute \src "ls180.v:6346.49-6346.105" - cell $and $and$ls180.v:6346$1970 + attribute \src "ls180.v:6398.49-6398.105" + cell $and $and$ls180.v:6398$2036 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6346$1969_Y - connect \Y $and$ls180.v:6346$1970_Y + connect \B $not$ls180.v:6398$2035_Y + connect \Y $and$ls180.v:6398$2036_Y end - attribute \src "ls180.v:6346.48-6346.155" - cell $and $and$ls180.v:6346$1972 + attribute \src "ls180.v:6398.48-6398.155" + cell $and $and$ls180.v:6398$2038 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6346$1970_Y - connect \B $eq$ls180.v:6346$1971_Y - connect \Y $and$ls180.v:6346$1972_Y + connect \A $and$ls180.v:6398$2036_Y + connect \B $eq$ls180.v:6398$2037_Y + connect \Y $and$ls180.v:6398$2038_Y end - attribute \src "ls180.v:6363.42-6363.97" - cell $and $and$ls180.v:6363$1974 + attribute \src "ls180.v:6415.42-6415.97" + cell $and $and$ls180.v:6415$2040 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -245298,43 +246166,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6363$1974_Y + connect \Y $and$ls180.v:6415$2040_Y end - attribute \src "ls180.v:6363.41-6363.148" - cell $and $and$ls180.v:6363$1976 + attribute \src "ls180.v:6415.41-6415.148" + cell $and $and$ls180.v:6415$2042 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6363$1974_Y - connect \B $eq$ls180.v:6363$1975_Y - connect \Y $and$ls180.v:6363$1976_Y + connect \A $and$ls180.v:6415$2040_Y + connect \B $eq$ls180.v:6415$2041_Y + connect \Y $and$ls180.v:6415$2042_Y end - attribute \src "ls180.v:6364.42-6364.100" - cell $and $and$ls180.v:6364$1978 + attribute \src "ls180.v:6416.42-6416.100" + cell $and $and$ls180.v:6416$2044 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6364$1977_Y - connect \Y $and$ls180.v:6364$1978_Y + connect \B $not$ls180.v:6416$2043_Y + connect \Y $and$ls180.v:6416$2044_Y end - attribute \src "ls180.v:6364.41-6364.151" - cell $and $and$ls180.v:6364$1980 + attribute \src "ls180.v:6416.41-6416.151" + cell $and $and$ls180.v:6416$2046 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6364$1978_Y - connect \B $eq$ls180.v:6364$1979_Y - connect \Y $and$ls180.v:6364$1980_Y + connect \A $and$ls180.v:6416$2044_Y + connect \B $eq$ls180.v:6416$2045_Y + connect \Y $and$ls180.v:6416$2046_Y end - attribute \src "ls180.v:6366.42-6366.97" - cell $and $and$ls180.v:6366$1981 + attribute \src "ls180.v:6418.42-6418.97" + cell $and $and$ls180.v:6418$2047 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -245342,43 +246210,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6366$1981_Y + connect \Y $and$ls180.v:6418$2047_Y end - attribute \src "ls180.v:6366.41-6366.148" - cell $and $and$ls180.v:6366$1983 + attribute \src "ls180.v:6418.41-6418.148" + cell $and $and$ls180.v:6418$2049 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6366$1981_Y - connect \B $eq$ls180.v:6366$1982_Y - connect \Y $and$ls180.v:6366$1983_Y + connect \A $and$ls180.v:6418$2047_Y + connect \B $eq$ls180.v:6418$2048_Y + connect \Y $and$ls180.v:6418$2049_Y end - attribute \src "ls180.v:6367.42-6367.100" - cell $and $and$ls180.v:6367$1985 + attribute \src "ls180.v:6419.42-6419.100" + cell $and $and$ls180.v:6419$2051 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6367$1984_Y - connect \Y $and$ls180.v:6367$1985_Y + connect \B $not$ls180.v:6419$2050_Y + connect \Y $and$ls180.v:6419$2051_Y end - attribute \src "ls180.v:6367.41-6367.151" - cell $and $and$ls180.v:6367$1987 + attribute \src "ls180.v:6419.41-6419.151" + cell $and $and$ls180.v:6419$2053 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6367$1985_Y - connect \B $eq$ls180.v:6367$1986_Y - connect \Y $and$ls180.v:6367$1987_Y + connect \A $and$ls180.v:6419$2051_Y + connect \B $eq$ls180.v:6419$2052_Y + connect \Y $and$ls180.v:6419$2053_Y end - attribute \src "ls180.v:6369.40-6369.95" - cell $and $and$ls180.v:6369$1988 + attribute \src "ls180.v:6421.40-6421.95" + cell $and $and$ls180.v:6421$2054 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -245386,43 +246254,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6369$1988_Y + connect \Y $and$ls180.v:6421$2054_Y end - attribute \src "ls180.v:6369.39-6369.146" - cell $and $and$ls180.v:6369$1990 + attribute \src "ls180.v:6421.39-6421.146" + cell $and $and$ls180.v:6421$2056 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6369$1988_Y - connect \B $eq$ls180.v:6369$1989_Y - connect \Y $and$ls180.v:6369$1990_Y + connect \A $and$ls180.v:6421$2054_Y + connect \B $eq$ls180.v:6421$2055_Y + connect \Y $and$ls180.v:6421$2056_Y end - attribute \src "ls180.v:6370.40-6370.98" - cell $and $and$ls180.v:6370$1992 + attribute \src "ls180.v:6422.40-6422.98" + cell $and $and$ls180.v:6422$2058 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6370$1991_Y - connect \Y $and$ls180.v:6370$1992_Y + connect \B $not$ls180.v:6422$2057_Y + connect \Y $and$ls180.v:6422$2058_Y end - attribute \src "ls180.v:6370.39-6370.149" - cell $and $and$ls180.v:6370$1994 + attribute \src "ls180.v:6422.39-6422.149" + cell $and $and$ls180.v:6422$2060 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6370$1992_Y - connect \B $eq$ls180.v:6370$1993_Y - connect \Y $and$ls180.v:6370$1994_Y + connect \A $and$ls180.v:6422$2058_Y + connect \B $eq$ls180.v:6422$2059_Y + connect \Y $and$ls180.v:6422$2060_Y end - attribute \src "ls180.v:6372.39-6372.94" - cell $and $and$ls180.v:6372$1995 + attribute \src "ls180.v:6424.39-6424.94" + cell $and $and$ls180.v:6424$2061 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -245430,43 +246298,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6372$1995_Y + connect \Y $and$ls180.v:6424$2061_Y end - attribute \src "ls180.v:6372.38-6372.145" - cell $and $and$ls180.v:6372$1997 + attribute \src "ls180.v:6424.38-6424.145" + cell $and $and$ls180.v:6424$2063 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6372$1995_Y - connect \B $eq$ls180.v:6372$1996_Y - connect \Y $and$ls180.v:6372$1997_Y + connect \A $and$ls180.v:6424$2061_Y + connect \B $eq$ls180.v:6424$2062_Y + connect \Y $and$ls180.v:6424$2063_Y end - attribute \src "ls180.v:6373.39-6373.97" - cell $and $and$ls180.v:6373$1999 + attribute \src "ls180.v:6425.39-6425.97" + cell $and $and$ls180.v:6425$2065 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6373$1998_Y - connect \Y $and$ls180.v:6373$1999_Y + connect \B $not$ls180.v:6425$2064_Y + connect \Y $and$ls180.v:6425$2065_Y end - attribute \src "ls180.v:6373.38-6373.148" - cell $and $and$ls180.v:6373$2001 + attribute \src "ls180.v:6425.38-6425.148" + cell $and $and$ls180.v:6425$2067 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6373$1999_Y - connect \B $eq$ls180.v:6373$2000_Y - connect \Y $and$ls180.v:6373$2001_Y + connect \A $and$ls180.v:6425$2065_Y + connect \B $eq$ls180.v:6425$2066_Y + connect \Y $and$ls180.v:6425$2067_Y end - attribute \src "ls180.v:6375.38-6375.93" - cell $and $and$ls180.v:6375$2002 + attribute \src "ls180.v:6427.38-6427.93" + cell $and $and$ls180.v:6427$2068 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -245474,43 +246342,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6375$2002_Y + connect \Y $and$ls180.v:6427$2068_Y end - attribute \src "ls180.v:6375.37-6375.144" - cell $and $and$ls180.v:6375$2004 + attribute \src "ls180.v:6427.37-6427.144" + cell $and $and$ls180.v:6427$2070 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6375$2002_Y - connect \B $eq$ls180.v:6375$2003_Y - connect \Y $and$ls180.v:6375$2004_Y + connect \A $and$ls180.v:6427$2068_Y + connect \B $eq$ls180.v:6427$2069_Y + connect \Y $and$ls180.v:6427$2070_Y end - attribute \src "ls180.v:6376.38-6376.96" - cell $and $and$ls180.v:6376$2006 + attribute \src "ls180.v:6428.38-6428.96" + cell $and $and$ls180.v:6428$2072 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6376$2005_Y - connect \Y $and$ls180.v:6376$2006_Y + connect \B $not$ls180.v:6428$2071_Y + connect \Y $and$ls180.v:6428$2072_Y end - attribute \src "ls180.v:6376.37-6376.147" - cell $and $and$ls180.v:6376$2008 + attribute \src "ls180.v:6428.37-6428.147" + cell $and $and$ls180.v:6428$2074 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6376$2006_Y - connect \B $eq$ls180.v:6376$2007_Y - connect \Y $and$ls180.v:6376$2008_Y + connect \A $and$ls180.v:6428$2072_Y + connect \B $eq$ls180.v:6428$2073_Y + connect \Y $and$ls180.v:6428$2074_Y end - attribute \src "ls180.v:6378.37-6378.92" - cell $and $and$ls180.v:6378$2009 + attribute \src "ls180.v:6430.37-6430.92" + cell $and $and$ls180.v:6430$2075 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -245518,43 +246386,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6378$2009_Y + connect \Y $and$ls180.v:6430$2075_Y end - attribute \src "ls180.v:6378.36-6378.143" - cell $and $and$ls180.v:6378$2011 + attribute \src "ls180.v:6430.36-6430.143" + cell $and $and$ls180.v:6430$2077 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6378$2009_Y - connect \B $eq$ls180.v:6378$2010_Y - connect \Y $and$ls180.v:6378$2011_Y + connect \A $and$ls180.v:6430$2075_Y + connect \B $eq$ls180.v:6430$2076_Y + connect \Y $and$ls180.v:6430$2077_Y end - attribute \src "ls180.v:6379.37-6379.95" - cell $and $and$ls180.v:6379$2013 + attribute \src "ls180.v:6431.37-6431.95" + cell $and $and$ls180.v:6431$2079 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6379$2012_Y - connect \Y $and$ls180.v:6379$2013_Y + connect \B $not$ls180.v:6431$2078_Y + connect \Y $and$ls180.v:6431$2079_Y end - attribute \src "ls180.v:6379.36-6379.146" - cell $and $and$ls180.v:6379$2015 + attribute \src "ls180.v:6431.36-6431.146" + cell $and $and$ls180.v:6431$2081 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6379$2013_Y - connect \B $eq$ls180.v:6379$2014_Y - connect \Y $and$ls180.v:6379$2015_Y + connect \A $and$ls180.v:6431$2079_Y + connect \B $eq$ls180.v:6431$2080_Y + connect \Y $and$ls180.v:6431$2081_Y end - attribute \src "ls180.v:6381.43-6381.98" - cell $and $and$ls180.v:6381$2016 + attribute \src "ls180.v:6433.43-6433.98" + cell $and $and$ls180.v:6433$2082 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -245562,43 +246430,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6381$2016_Y + connect \Y $and$ls180.v:6433$2082_Y end - attribute \src "ls180.v:6381.42-6381.149" - cell $and $and$ls180.v:6381$2018 + attribute \src "ls180.v:6433.42-6433.149" + cell $and $and$ls180.v:6433$2084 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6381$2016_Y - connect \B $eq$ls180.v:6381$2017_Y - connect \Y $and$ls180.v:6381$2018_Y + connect \A $and$ls180.v:6433$2082_Y + connect \B $eq$ls180.v:6433$2083_Y + connect \Y $and$ls180.v:6433$2084_Y end - attribute \src "ls180.v:6382.43-6382.101" - cell $and $and$ls180.v:6382$2020 + attribute \src "ls180.v:6434.43-6434.101" + cell $and $and$ls180.v:6434$2086 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6382$2019_Y - connect \Y $and$ls180.v:6382$2020_Y + connect \B $not$ls180.v:6434$2085_Y + connect \Y $and$ls180.v:6434$2086_Y end - attribute \src "ls180.v:6382.42-6382.152" - cell $and $and$ls180.v:6382$2022 + attribute \src "ls180.v:6434.42-6434.152" + cell $and $and$ls180.v:6434$2088 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6382$2020_Y - connect \B $eq$ls180.v:6382$2021_Y - connect \Y $and$ls180.v:6382$2022_Y + connect \A $and$ls180.v:6434$2086_Y + connect \B $eq$ls180.v:6434$2087_Y + connect \Y $and$ls180.v:6434$2088_Y end - attribute \src "ls180.v:6403.42-6403.97" - cell $and $and$ls180.v:6403$2025 + attribute \src "ls180.v:6455.42-6455.97" + cell $and $and$ls180.v:6455$2091 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -245606,43 +246474,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6403$2025_Y + connect \Y $and$ls180.v:6455$2091_Y end - attribute \src "ls180.v:6403.41-6403.148" - cell $and $and$ls180.v:6403$2027 + attribute \src "ls180.v:6455.41-6455.148" + cell $and $and$ls180.v:6455$2093 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6403$2025_Y - connect \B $eq$ls180.v:6403$2026_Y - connect \Y $and$ls180.v:6403$2027_Y + connect \A $and$ls180.v:6455$2091_Y + connect \B $eq$ls180.v:6455$2092_Y + connect \Y $and$ls180.v:6455$2093_Y end - attribute \src "ls180.v:6404.42-6404.100" - cell $and $and$ls180.v:6404$2029 + attribute \src "ls180.v:6456.42-6456.100" + cell $and $and$ls180.v:6456$2095 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6404$2028_Y - connect \Y $and$ls180.v:6404$2029_Y + connect \B $not$ls180.v:6456$2094_Y + connect \Y $and$ls180.v:6456$2095_Y end - attribute \src "ls180.v:6404.41-6404.151" - cell $and $and$ls180.v:6404$2031 + attribute \src "ls180.v:6456.41-6456.151" + cell $and $and$ls180.v:6456$2097 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6404$2029_Y - connect \B $eq$ls180.v:6404$2030_Y - connect \Y $and$ls180.v:6404$2031_Y + connect \A $and$ls180.v:6456$2095_Y + connect \B $eq$ls180.v:6456$2096_Y + connect \Y $and$ls180.v:6456$2097_Y end - attribute \src "ls180.v:6406.42-6406.97" - cell $and $and$ls180.v:6406$2032 + attribute \src "ls180.v:6458.42-6458.97" + cell $and $and$ls180.v:6458$2098 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -245650,43 +246518,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6406$2032_Y + connect \Y $and$ls180.v:6458$2098_Y end - attribute \src "ls180.v:6406.41-6406.148" - cell $and $and$ls180.v:6406$2034 + attribute \src "ls180.v:6458.41-6458.148" + cell $and $and$ls180.v:6458$2100 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6406$2032_Y - connect \B $eq$ls180.v:6406$2033_Y - connect \Y $and$ls180.v:6406$2034_Y + connect \A $and$ls180.v:6458$2098_Y + connect \B $eq$ls180.v:6458$2099_Y + connect \Y $and$ls180.v:6458$2100_Y end - attribute \src "ls180.v:6407.42-6407.100" - cell $and $and$ls180.v:6407$2036 + attribute \src "ls180.v:6459.42-6459.100" + cell $and $and$ls180.v:6459$2102 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6407$2035_Y - connect \Y $and$ls180.v:6407$2036_Y + connect \B $not$ls180.v:6459$2101_Y + connect \Y $and$ls180.v:6459$2102_Y end - attribute \src "ls180.v:6407.41-6407.151" - cell $and $and$ls180.v:6407$2038 + attribute \src "ls180.v:6459.41-6459.151" + cell $and $and$ls180.v:6459$2104 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6407$2036_Y - connect \B $eq$ls180.v:6407$2037_Y - connect \Y $and$ls180.v:6407$2038_Y + connect \A $and$ls180.v:6459$2102_Y + connect \B $eq$ls180.v:6459$2103_Y + connect \Y $and$ls180.v:6459$2104_Y end - attribute \src "ls180.v:6409.40-6409.95" - cell $and $and$ls180.v:6409$2039 + attribute \src "ls180.v:6461.40-6461.95" + cell $and $and$ls180.v:6461$2105 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -245694,43 +246562,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6409$2039_Y + connect \Y $and$ls180.v:6461$2105_Y end - attribute \src "ls180.v:6409.39-6409.146" - cell $and $and$ls180.v:6409$2041 + attribute \src "ls180.v:6461.39-6461.146" + cell $and $and$ls180.v:6461$2107 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6409$2039_Y - connect \B $eq$ls180.v:6409$2040_Y - connect \Y $and$ls180.v:6409$2041_Y + connect \A $and$ls180.v:6461$2105_Y + connect \B $eq$ls180.v:6461$2106_Y + connect \Y $and$ls180.v:6461$2107_Y end - attribute \src "ls180.v:6410.40-6410.98" - cell $and $and$ls180.v:6410$2043 + attribute \src "ls180.v:6462.40-6462.98" + cell $and $and$ls180.v:6462$2109 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6410$2042_Y - connect \Y $and$ls180.v:6410$2043_Y + connect \B $not$ls180.v:6462$2108_Y + connect \Y $and$ls180.v:6462$2109_Y end - attribute \src "ls180.v:6410.39-6410.149" - cell $and $and$ls180.v:6410$2045 + attribute \src "ls180.v:6462.39-6462.149" + cell $and $and$ls180.v:6462$2111 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6410$2043_Y - connect \B $eq$ls180.v:6410$2044_Y - connect \Y $and$ls180.v:6410$2045_Y + connect \A $and$ls180.v:6462$2109_Y + connect \B $eq$ls180.v:6462$2110_Y + connect \Y $and$ls180.v:6462$2111_Y end - attribute \src "ls180.v:6412.39-6412.94" - cell $and $and$ls180.v:6412$2046 + attribute \src "ls180.v:6464.39-6464.94" + cell $and $and$ls180.v:6464$2112 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -245738,43 +246606,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6412$2046_Y + connect \Y $and$ls180.v:6464$2112_Y end - attribute \src "ls180.v:6412.38-6412.145" - cell $and $and$ls180.v:6412$2048 + attribute \src "ls180.v:6464.38-6464.145" + cell $and $and$ls180.v:6464$2114 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6412$2046_Y - connect \B $eq$ls180.v:6412$2047_Y - connect \Y $and$ls180.v:6412$2048_Y + connect \A $and$ls180.v:6464$2112_Y + connect \B $eq$ls180.v:6464$2113_Y + connect \Y $and$ls180.v:6464$2114_Y end - attribute \src "ls180.v:6413.39-6413.97" - cell $and $and$ls180.v:6413$2050 + attribute \src "ls180.v:6465.39-6465.97" + cell $and $and$ls180.v:6465$2116 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6413$2049_Y - connect \Y $and$ls180.v:6413$2050_Y + connect \B $not$ls180.v:6465$2115_Y + connect \Y $and$ls180.v:6465$2116_Y end - attribute \src "ls180.v:6413.38-6413.148" - cell $and $and$ls180.v:6413$2052 + attribute \src "ls180.v:6465.38-6465.148" + cell $and $and$ls180.v:6465$2118 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6413$2050_Y - connect \B $eq$ls180.v:6413$2051_Y - connect \Y $and$ls180.v:6413$2052_Y + connect \A $and$ls180.v:6465$2116_Y + connect \B $eq$ls180.v:6465$2117_Y + connect \Y $and$ls180.v:6465$2118_Y end - attribute \src "ls180.v:6415.38-6415.93" - cell $and $and$ls180.v:6415$2053 + attribute \src "ls180.v:6467.38-6467.93" + cell $and $and$ls180.v:6467$2119 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -245782,43 +246650,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6415$2053_Y + connect \Y $and$ls180.v:6467$2119_Y end - attribute \src "ls180.v:6415.37-6415.144" - cell $and $and$ls180.v:6415$2055 + attribute \src "ls180.v:6467.37-6467.144" + cell $and $and$ls180.v:6467$2121 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6415$2053_Y - connect \B $eq$ls180.v:6415$2054_Y - connect \Y $and$ls180.v:6415$2055_Y + connect \A $and$ls180.v:6467$2119_Y + connect \B $eq$ls180.v:6467$2120_Y + connect \Y $and$ls180.v:6467$2121_Y end - attribute \src "ls180.v:6416.38-6416.96" - cell $and $and$ls180.v:6416$2057 + attribute \src "ls180.v:6468.38-6468.96" + cell $and $and$ls180.v:6468$2123 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6416$2056_Y - connect \Y $and$ls180.v:6416$2057_Y + connect \B $not$ls180.v:6468$2122_Y + connect \Y $and$ls180.v:6468$2123_Y end - attribute \src "ls180.v:6416.37-6416.147" - cell $and $and$ls180.v:6416$2059 + attribute \src "ls180.v:6468.37-6468.147" + cell $and $and$ls180.v:6468$2125 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6416$2057_Y - connect \B $eq$ls180.v:6416$2058_Y - connect \Y $and$ls180.v:6416$2059_Y + connect \A $and$ls180.v:6468$2123_Y + connect \B $eq$ls180.v:6468$2124_Y + connect \Y $and$ls180.v:6468$2125_Y end - attribute \src "ls180.v:6418.37-6418.92" - cell $and $and$ls180.v:6418$2060 + attribute \src "ls180.v:6470.37-6470.92" + cell $and $and$ls180.v:6470$2126 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -245826,43 +246694,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6418$2060_Y + connect \Y $and$ls180.v:6470$2126_Y end - attribute \src "ls180.v:6418.36-6418.143" - cell $and $and$ls180.v:6418$2062 + attribute \src "ls180.v:6470.36-6470.143" + cell $and $and$ls180.v:6470$2128 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6418$2060_Y - connect \B $eq$ls180.v:6418$2061_Y - connect \Y $and$ls180.v:6418$2062_Y + connect \A $and$ls180.v:6470$2126_Y + connect \B $eq$ls180.v:6470$2127_Y + connect \Y $and$ls180.v:6470$2128_Y end - attribute \src "ls180.v:6419.37-6419.95" - cell $and $and$ls180.v:6419$2064 + attribute \src "ls180.v:6471.37-6471.95" + cell $and $and$ls180.v:6471$2130 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6419$2063_Y - connect \Y $and$ls180.v:6419$2064_Y + connect \B $not$ls180.v:6471$2129_Y + connect \Y $and$ls180.v:6471$2130_Y end - attribute \src "ls180.v:6419.36-6419.146" - cell $and $and$ls180.v:6419$2066 + attribute \src "ls180.v:6471.36-6471.146" + cell $and $and$ls180.v:6471$2132 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6419$2064_Y - connect \B $eq$ls180.v:6419$2065_Y - connect \Y $and$ls180.v:6419$2066_Y + connect \A $and$ls180.v:6471$2130_Y + connect \B $eq$ls180.v:6471$2131_Y + connect \Y $and$ls180.v:6471$2132_Y end - attribute \src "ls180.v:6421.43-6421.98" - cell $and $and$ls180.v:6421$2067 + attribute \src "ls180.v:6473.43-6473.98" + cell $and $and$ls180.v:6473$2133 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -245870,43 +246738,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6421$2067_Y + connect \Y $and$ls180.v:6473$2133_Y end - attribute \src "ls180.v:6421.42-6421.149" - cell $and $and$ls180.v:6421$2069 + attribute \src "ls180.v:6473.42-6473.149" + cell $and $and$ls180.v:6473$2135 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6421$2067_Y - connect \B $eq$ls180.v:6421$2068_Y - connect \Y $and$ls180.v:6421$2069_Y + connect \A $and$ls180.v:6473$2133_Y + connect \B $eq$ls180.v:6473$2134_Y + connect \Y $and$ls180.v:6473$2135_Y end - attribute \src "ls180.v:6422.43-6422.101" - cell $and $and$ls180.v:6422$2071 + attribute \src "ls180.v:6474.43-6474.101" + cell $and $and$ls180.v:6474$2137 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6422$2070_Y - connect \Y $and$ls180.v:6422$2071_Y + connect \B $not$ls180.v:6474$2136_Y + connect \Y $and$ls180.v:6474$2137_Y end - attribute \src "ls180.v:6422.42-6422.152" - cell $and $and$ls180.v:6422$2073 + attribute \src "ls180.v:6474.42-6474.152" + cell $and $and$ls180.v:6474$2139 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6422$2071_Y - connect \B $eq$ls180.v:6422$2072_Y - connect \Y $and$ls180.v:6422$2073_Y + connect \A $and$ls180.v:6474$2137_Y + connect \B $eq$ls180.v:6474$2138_Y + connect \Y $and$ls180.v:6474$2139_Y end - attribute \src "ls180.v:6424.46-6424.101" - cell $and $and$ls180.v:6424$2074 + attribute \src "ls180.v:6476.46-6476.101" + cell $and $and$ls180.v:6476$2140 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -245914,43 +246782,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6424$2074_Y + connect \Y $and$ls180.v:6476$2140_Y end - attribute \src "ls180.v:6424.45-6424.152" - cell $and $and$ls180.v:6424$2076 + attribute \src "ls180.v:6476.45-6476.152" + cell $and $and$ls180.v:6476$2142 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6424$2074_Y - connect \B $eq$ls180.v:6424$2075_Y - connect \Y $and$ls180.v:6424$2076_Y + connect \A $and$ls180.v:6476$2140_Y + connect \B $eq$ls180.v:6476$2141_Y + connect \Y $and$ls180.v:6476$2142_Y end - attribute \src "ls180.v:6425.46-6425.104" - cell $and $and$ls180.v:6425$2078 + attribute \src "ls180.v:6477.46-6477.104" + cell $and $and$ls180.v:6477$2144 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6425$2077_Y - connect \Y $and$ls180.v:6425$2078_Y + connect \B $not$ls180.v:6477$2143_Y + connect \Y $and$ls180.v:6477$2144_Y end - attribute \src "ls180.v:6425.45-6425.155" - cell $and $and$ls180.v:6425$2080 + attribute \src "ls180.v:6477.45-6477.155" + cell $and $and$ls180.v:6477$2146 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6425$2078_Y - connect \B $eq$ls180.v:6425$2079_Y - connect \Y $and$ls180.v:6425$2080_Y + connect \A $and$ls180.v:6477$2144_Y + connect \B $eq$ls180.v:6477$2145_Y + connect \Y $and$ls180.v:6477$2146_Y end - attribute \src "ls180.v:6427.46-6427.101" - cell $and $and$ls180.v:6427$2081 + attribute \src "ls180.v:6479.46-6479.101" + cell $and $and$ls180.v:6479$2147 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -245958,43 +246826,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6427$2081_Y + connect \Y $and$ls180.v:6479$2147_Y end - attribute \src "ls180.v:6427.45-6427.152" - cell $and $and$ls180.v:6427$2083 + attribute \src "ls180.v:6479.45-6479.152" + cell $and $and$ls180.v:6479$2149 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6427$2081_Y - connect \B $eq$ls180.v:6427$2082_Y - connect \Y $and$ls180.v:6427$2083_Y + connect \A $and$ls180.v:6479$2147_Y + connect \B $eq$ls180.v:6479$2148_Y + connect \Y $and$ls180.v:6479$2149_Y end - attribute \src "ls180.v:6428.46-6428.104" - cell $and $and$ls180.v:6428$2085 + attribute \src "ls180.v:6480.46-6480.104" + cell $and $and$ls180.v:6480$2151 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6428$2084_Y - connect \Y $and$ls180.v:6428$2085_Y + connect \B $not$ls180.v:6480$2150_Y + connect \Y $and$ls180.v:6480$2151_Y end - attribute \src "ls180.v:6428.45-6428.155" - cell $and $and$ls180.v:6428$2087 + attribute \src "ls180.v:6480.45-6480.155" + cell $and $and$ls180.v:6480$2153 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6428$2085_Y - connect \B $eq$ls180.v:6428$2086_Y - connect \Y $and$ls180.v:6428$2087_Y + connect \A $and$ls180.v:6480$2151_Y + connect \B $eq$ls180.v:6480$2152_Y + connect \Y $and$ls180.v:6480$2153_Y end - attribute \src "ls180.v:6451.39-6451.94" - cell $and $and$ls180.v:6451$2090 + attribute \src "ls180.v:6503.39-6503.94" + cell $and $and$ls180.v:6503$2156 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -246002,43 +246870,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6451$2090_Y + connect \Y $and$ls180.v:6503$2156_Y end - attribute \src "ls180.v:6451.38-6451.145" - cell $and $and$ls180.v:6451$2092 + attribute \src "ls180.v:6503.38-6503.145" + cell $and $and$ls180.v:6503$2158 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6451$2090_Y - connect \B $eq$ls180.v:6451$2091_Y - connect \Y $and$ls180.v:6451$2092_Y + connect \A $and$ls180.v:6503$2156_Y + connect \B $eq$ls180.v:6503$2157_Y + connect \Y $and$ls180.v:6503$2158_Y end - attribute \src "ls180.v:6452.39-6452.97" - cell $and $and$ls180.v:6452$2094 + attribute \src "ls180.v:6504.39-6504.97" + cell $and $and$ls180.v:6504$2160 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6452$2093_Y - connect \Y $and$ls180.v:6452$2094_Y + connect \B $not$ls180.v:6504$2159_Y + connect \Y $and$ls180.v:6504$2160_Y end - attribute \src "ls180.v:6452.38-6452.148" - cell $and $and$ls180.v:6452$2096 + attribute \src "ls180.v:6504.38-6504.148" + cell $and $and$ls180.v:6504$2162 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6452$2094_Y - connect \B $eq$ls180.v:6452$2095_Y - connect \Y $and$ls180.v:6452$2096_Y + connect \A $and$ls180.v:6504$2160_Y + connect \B $eq$ls180.v:6504$2161_Y + connect \Y $and$ls180.v:6504$2162_Y end - attribute \src "ls180.v:6454.39-6454.94" - cell $and $and$ls180.v:6454$2097 + attribute \src "ls180.v:6506.39-6506.94" + cell $and $and$ls180.v:6506$2163 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -246046,43 +246914,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6454$2097_Y + connect \Y $and$ls180.v:6506$2163_Y end - attribute \src "ls180.v:6454.38-6454.145" - cell $and $and$ls180.v:6454$2099 + attribute \src "ls180.v:6506.38-6506.145" + cell $and $and$ls180.v:6506$2165 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6454$2097_Y - connect \B $eq$ls180.v:6454$2098_Y - connect \Y $and$ls180.v:6454$2099_Y + connect \A $and$ls180.v:6506$2163_Y + connect \B $eq$ls180.v:6506$2164_Y + connect \Y $and$ls180.v:6506$2165_Y end - attribute \src "ls180.v:6455.39-6455.97" - cell $and $and$ls180.v:6455$2101 + attribute \src "ls180.v:6507.39-6507.97" + cell $and $and$ls180.v:6507$2167 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6455$2100_Y - connect \Y $and$ls180.v:6455$2101_Y + connect \B $not$ls180.v:6507$2166_Y + connect \Y $and$ls180.v:6507$2167_Y end - attribute \src "ls180.v:6455.38-6455.148" - cell $and $and$ls180.v:6455$2103 + attribute \src "ls180.v:6507.38-6507.148" + cell $and $and$ls180.v:6507$2169 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6455$2101_Y - connect \B $eq$ls180.v:6455$2102_Y - connect \Y $and$ls180.v:6455$2103_Y + connect \A $and$ls180.v:6507$2167_Y + connect \B $eq$ls180.v:6507$2168_Y + connect \Y $and$ls180.v:6507$2169_Y end - attribute \src "ls180.v:6457.39-6457.94" - cell $and $and$ls180.v:6457$2104 + attribute \src "ls180.v:6509.39-6509.94" + cell $and $and$ls180.v:6509$2170 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -246090,43 +246958,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6457$2104_Y + connect \Y $and$ls180.v:6509$2170_Y end - attribute \src "ls180.v:6457.38-6457.145" - cell $and $and$ls180.v:6457$2106 + attribute \src "ls180.v:6509.38-6509.145" + cell $and $and$ls180.v:6509$2172 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6457$2104_Y - connect \B $eq$ls180.v:6457$2105_Y - connect \Y $and$ls180.v:6457$2106_Y + connect \A $and$ls180.v:6509$2170_Y + connect \B $eq$ls180.v:6509$2171_Y + connect \Y $and$ls180.v:6509$2172_Y end - attribute \src "ls180.v:6458.39-6458.97" - cell $and $and$ls180.v:6458$2108 + attribute \src "ls180.v:6510.39-6510.97" + cell $and $and$ls180.v:6510$2174 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6458$2107_Y - connect \Y $and$ls180.v:6458$2108_Y + connect \B $not$ls180.v:6510$2173_Y + connect \Y $and$ls180.v:6510$2174_Y end - attribute \src "ls180.v:6458.38-6458.148" - cell $and $and$ls180.v:6458$2110 + attribute \src "ls180.v:6510.38-6510.148" + cell $and $and$ls180.v:6510$2176 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6458$2108_Y - connect \B $eq$ls180.v:6458$2109_Y - connect \Y $and$ls180.v:6458$2110_Y + connect \A $and$ls180.v:6510$2174_Y + connect \B $eq$ls180.v:6510$2175_Y + connect \Y $and$ls180.v:6510$2176_Y end - attribute \src "ls180.v:6460.39-6460.94" - cell $and $and$ls180.v:6460$2111 + attribute \src "ls180.v:6512.39-6512.94" + cell $and $and$ls180.v:6512$2177 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -246134,43 +247002,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6460$2111_Y + connect \Y $and$ls180.v:6512$2177_Y end - attribute \src "ls180.v:6460.38-6460.145" - cell $and $and$ls180.v:6460$2113 + attribute \src "ls180.v:6512.38-6512.145" + cell $and $and$ls180.v:6512$2179 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6460$2111_Y - connect \B $eq$ls180.v:6460$2112_Y - connect \Y $and$ls180.v:6460$2113_Y + connect \A $and$ls180.v:6512$2177_Y + connect \B $eq$ls180.v:6512$2178_Y + connect \Y $and$ls180.v:6512$2179_Y end - attribute \src "ls180.v:6461.39-6461.97" - cell $and $and$ls180.v:6461$2115 + attribute \src "ls180.v:6513.39-6513.97" + cell $and $and$ls180.v:6513$2181 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6461$2114_Y - connect \Y $and$ls180.v:6461$2115_Y + connect \B $not$ls180.v:6513$2180_Y + connect \Y $and$ls180.v:6513$2181_Y end - attribute \src "ls180.v:6461.38-6461.148" - cell $and $and$ls180.v:6461$2117 + attribute \src "ls180.v:6513.38-6513.148" + cell $and $and$ls180.v:6513$2183 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6461$2115_Y - connect \B $eq$ls180.v:6461$2116_Y - connect \Y $and$ls180.v:6461$2117_Y + connect \A $and$ls180.v:6513$2181_Y + connect \B $eq$ls180.v:6513$2182_Y + connect \Y $and$ls180.v:6513$2183_Y end - attribute \src "ls180.v:6463.41-6463.96" - cell $and $and$ls180.v:6463$2118 + attribute \src "ls180.v:6515.41-6515.96" + cell $and $and$ls180.v:6515$2184 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -246178,43 +247046,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6463$2118_Y + connect \Y $and$ls180.v:6515$2184_Y end - attribute \src "ls180.v:6463.40-6463.147" - cell $and $and$ls180.v:6463$2120 + attribute \src "ls180.v:6515.40-6515.147" + cell $and $and$ls180.v:6515$2186 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6463$2118_Y - connect \B $eq$ls180.v:6463$2119_Y - connect \Y $and$ls180.v:6463$2120_Y + connect \A $and$ls180.v:6515$2184_Y + connect \B $eq$ls180.v:6515$2185_Y + connect \Y $and$ls180.v:6515$2186_Y end - attribute \src "ls180.v:6464.41-6464.99" - cell $and $and$ls180.v:6464$2122 + attribute \src "ls180.v:6516.41-6516.99" + cell $and $and$ls180.v:6516$2188 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6464$2121_Y - connect \Y $and$ls180.v:6464$2122_Y + connect \B $not$ls180.v:6516$2187_Y + connect \Y $and$ls180.v:6516$2188_Y end - attribute \src "ls180.v:6464.40-6464.150" - cell $and $and$ls180.v:6464$2124 + attribute \src "ls180.v:6516.40-6516.150" + cell $and $and$ls180.v:6516$2190 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6464$2122_Y - connect \B $eq$ls180.v:6464$2123_Y - connect \Y $and$ls180.v:6464$2124_Y + connect \A $and$ls180.v:6516$2188_Y + connect \B $eq$ls180.v:6516$2189_Y + connect \Y $and$ls180.v:6516$2190_Y end - attribute \src "ls180.v:6466.41-6466.96" - cell $and $and$ls180.v:6466$2125 + attribute \src "ls180.v:6518.41-6518.96" + cell $and $and$ls180.v:6518$2191 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -246222,43 +247090,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6466$2125_Y + connect \Y $and$ls180.v:6518$2191_Y end - attribute \src "ls180.v:6466.40-6466.147" - cell $and $and$ls180.v:6466$2127 + attribute \src "ls180.v:6518.40-6518.147" + cell $and $and$ls180.v:6518$2193 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6466$2125_Y - connect \B $eq$ls180.v:6466$2126_Y - connect \Y $and$ls180.v:6466$2127_Y + connect \A $and$ls180.v:6518$2191_Y + connect \B $eq$ls180.v:6518$2192_Y + connect \Y $and$ls180.v:6518$2193_Y end - attribute \src "ls180.v:6467.41-6467.99" - cell $and $and$ls180.v:6467$2129 + attribute \src "ls180.v:6519.41-6519.99" + cell $and $and$ls180.v:6519$2195 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6467$2128_Y - connect \Y $and$ls180.v:6467$2129_Y + connect \B $not$ls180.v:6519$2194_Y + connect \Y $and$ls180.v:6519$2195_Y end - attribute \src "ls180.v:6467.40-6467.150" - cell $and $and$ls180.v:6467$2131 + attribute \src "ls180.v:6519.40-6519.150" + cell $and $and$ls180.v:6519$2197 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6467$2129_Y - connect \B $eq$ls180.v:6467$2130_Y - connect \Y $and$ls180.v:6467$2131_Y + connect \A $and$ls180.v:6519$2195_Y + connect \B $eq$ls180.v:6519$2196_Y + connect \Y $and$ls180.v:6519$2197_Y end - attribute \src "ls180.v:6469.41-6469.96" - cell $and $and$ls180.v:6469$2132 + attribute \src "ls180.v:6521.41-6521.96" + cell $and $and$ls180.v:6521$2198 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -246266,43 +247134,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6469$2132_Y + connect \Y $and$ls180.v:6521$2198_Y end - attribute \src "ls180.v:6469.40-6469.147" - cell $and $and$ls180.v:6469$2134 + attribute \src "ls180.v:6521.40-6521.147" + cell $and $and$ls180.v:6521$2200 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6469$2132_Y - connect \B $eq$ls180.v:6469$2133_Y - connect \Y $and$ls180.v:6469$2134_Y + connect \A $and$ls180.v:6521$2198_Y + connect \B $eq$ls180.v:6521$2199_Y + connect \Y $and$ls180.v:6521$2200_Y end - attribute \src "ls180.v:6470.41-6470.99" - cell $and $and$ls180.v:6470$2136 + attribute \src "ls180.v:6522.41-6522.99" + cell $and $and$ls180.v:6522$2202 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6470$2135_Y - connect \Y $and$ls180.v:6470$2136_Y + connect \B $not$ls180.v:6522$2201_Y + connect \Y $and$ls180.v:6522$2202_Y end - attribute \src "ls180.v:6470.40-6470.150" - cell $and $and$ls180.v:6470$2138 + attribute \src "ls180.v:6522.40-6522.150" + cell $and $and$ls180.v:6522$2204 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6470$2136_Y - connect \B $eq$ls180.v:6470$2137_Y - connect \Y $and$ls180.v:6470$2138_Y + connect \A $and$ls180.v:6522$2202_Y + connect \B $eq$ls180.v:6522$2203_Y + connect \Y $and$ls180.v:6522$2204_Y end - attribute \src "ls180.v:6472.41-6472.96" - cell $and $and$ls180.v:6472$2139 + attribute \src "ls180.v:6524.41-6524.96" + cell $and $and$ls180.v:6524$2205 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -246310,43 +247178,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6472$2139_Y + connect \Y $and$ls180.v:6524$2205_Y end - attribute \src "ls180.v:6472.40-6472.147" - cell $and $and$ls180.v:6472$2141 + attribute \src "ls180.v:6524.40-6524.147" + cell $and $and$ls180.v:6524$2207 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6472$2139_Y - connect \B $eq$ls180.v:6472$2140_Y - connect \Y $and$ls180.v:6472$2141_Y + connect \A $and$ls180.v:6524$2205_Y + connect \B $eq$ls180.v:6524$2206_Y + connect \Y $and$ls180.v:6524$2207_Y end - attribute \src "ls180.v:6473.41-6473.99" - cell $and $and$ls180.v:6473$2143 + attribute \src "ls180.v:6525.41-6525.99" + cell $and $and$ls180.v:6525$2209 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6473$2142_Y - connect \Y $and$ls180.v:6473$2143_Y + connect \B $not$ls180.v:6525$2208_Y + connect \Y $and$ls180.v:6525$2209_Y end - attribute \src "ls180.v:6473.40-6473.150" - cell $and $and$ls180.v:6473$2145 + attribute \src "ls180.v:6525.40-6525.150" + cell $and $and$ls180.v:6525$2211 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6473$2143_Y - connect \B $eq$ls180.v:6473$2144_Y - connect \Y $and$ls180.v:6473$2145_Y + connect \A $and$ls180.v:6525$2209_Y + connect \B $eq$ls180.v:6525$2210_Y + connect \Y $and$ls180.v:6525$2211_Y end - attribute \src "ls180.v:6475.37-6475.92" - cell $and $and$ls180.v:6475$2146 + attribute \src "ls180.v:6527.37-6527.92" + cell $and $and$ls180.v:6527$2212 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -246354,43 +247222,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6475$2146_Y + connect \Y $and$ls180.v:6527$2212_Y end - attribute \src "ls180.v:6475.36-6475.143" - cell $and $and$ls180.v:6475$2148 + attribute \src "ls180.v:6527.36-6527.143" + cell $and $and$ls180.v:6527$2214 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6475$2146_Y - connect \B $eq$ls180.v:6475$2147_Y - connect \Y $and$ls180.v:6475$2148_Y + connect \A $and$ls180.v:6527$2212_Y + connect \B $eq$ls180.v:6527$2213_Y + connect \Y $and$ls180.v:6527$2214_Y end - attribute \src "ls180.v:6476.37-6476.95" - cell $and $and$ls180.v:6476$2150 + attribute \src "ls180.v:6528.37-6528.95" + cell $and $and$ls180.v:6528$2216 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6476$2149_Y - connect \Y $and$ls180.v:6476$2150_Y + connect \B $not$ls180.v:6528$2215_Y + connect \Y $and$ls180.v:6528$2216_Y end - attribute \src "ls180.v:6476.36-6476.146" - cell $and $and$ls180.v:6476$2152 + attribute \src "ls180.v:6528.36-6528.146" + cell $and $and$ls180.v:6528$2218 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6476$2150_Y - connect \B $eq$ls180.v:6476$2151_Y - connect \Y $and$ls180.v:6476$2152_Y + connect \A $and$ls180.v:6528$2216_Y + connect \B $eq$ls180.v:6528$2217_Y + connect \Y $and$ls180.v:6528$2218_Y end - attribute \src "ls180.v:6478.47-6478.102" - cell $and $and$ls180.v:6478$2153 + attribute \src "ls180.v:6530.47-6530.102" + cell $and $and$ls180.v:6530$2219 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -246398,43 +247266,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6478$2153_Y + connect \Y $and$ls180.v:6530$2219_Y end - attribute \src "ls180.v:6478.46-6478.153" - cell $and $and$ls180.v:6478$2155 + attribute \src "ls180.v:6530.46-6530.153" + cell $and $and$ls180.v:6530$2221 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6478$2153_Y - connect \B $eq$ls180.v:6478$2154_Y - connect \Y $and$ls180.v:6478$2155_Y + connect \A $and$ls180.v:6530$2219_Y + connect \B $eq$ls180.v:6530$2220_Y + connect \Y $and$ls180.v:6530$2221_Y end - attribute \src "ls180.v:6479.47-6479.105" - cell $and $and$ls180.v:6479$2157 + attribute \src "ls180.v:6531.47-6531.105" + cell $and $and$ls180.v:6531$2223 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6479$2156_Y - connect \Y $and$ls180.v:6479$2157_Y + connect \B $not$ls180.v:6531$2222_Y + connect \Y $and$ls180.v:6531$2223_Y end - attribute \src "ls180.v:6479.46-6479.156" - cell $and $and$ls180.v:6479$2159 + attribute \src "ls180.v:6531.46-6531.156" + cell $and $and$ls180.v:6531$2225 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6479$2157_Y - connect \B $eq$ls180.v:6479$2158_Y - connect \Y $and$ls180.v:6479$2159_Y + connect \A $and$ls180.v:6531$2223_Y + connect \B $eq$ls180.v:6531$2224_Y + connect \Y $and$ls180.v:6531$2225_Y end - attribute \src "ls180.v:6481.40-6481.95" - cell $and $and$ls180.v:6481$2160 + attribute \src "ls180.v:6533.40-6533.95" + cell $and $and$ls180.v:6533$2226 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -246442,43 +247310,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6481$2160_Y + connect \Y $and$ls180.v:6533$2226_Y end - attribute \src "ls180.v:6481.39-6481.147" - cell $and $and$ls180.v:6481$2162 + attribute \src "ls180.v:6533.39-6533.147" + cell $and $and$ls180.v:6533$2228 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6481$2160_Y - connect \B $eq$ls180.v:6481$2161_Y - connect \Y $and$ls180.v:6481$2162_Y + connect \A $and$ls180.v:6533$2226_Y + connect \B $eq$ls180.v:6533$2227_Y + connect \Y $and$ls180.v:6533$2228_Y end - attribute \src "ls180.v:6482.40-6482.98" - cell $and $and$ls180.v:6482$2164 + attribute \src "ls180.v:6534.40-6534.98" + cell $and $and$ls180.v:6534$2230 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6482$2163_Y - connect \Y $and$ls180.v:6482$2164_Y + connect \B $not$ls180.v:6534$2229_Y + connect \Y $and$ls180.v:6534$2230_Y end - attribute \src "ls180.v:6482.39-6482.150" - cell $and $and$ls180.v:6482$2166 + attribute \src "ls180.v:6534.39-6534.150" + cell $and $and$ls180.v:6534$2232 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6482$2164_Y - connect \B $eq$ls180.v:6482$2165_Y - connect \Y $and$ls180.v:6482$2166_Y + connect \A $and$ls180.v:6534$2230_Y + connect \B $eq$ls180.v:6534$2231_Y + connect \Y $and$ls180.v:6534$2232_Y end - attribute \src "ls180.v:6484.40-6484.95" - cell $and $and$ls180.v:6484$2167 + attribute \src "ls180.v:6536.40-6536.95" + cell $and $and$ls180.v:6536$2233 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -246486,43 +247354,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6484$2167_Y + connect \Y $and$ls180.v:6536$2233_Y end - attribute \src "ls180.v:6484.39-6484.147" - cell $and $and$ls180.v:6484$2169 + attribute \src "ls180.v:6536.39-6536.147" + cell $and $and$ls180.v:6536$2235 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6484$2167_Y - connect \B $eq$ls180.v:6484$2168_Y - connect \Y $and$ls180.v:6484$2169_Y + connect \A $and$ls180.v:6536$2233_Y + connect \B $eq$ls180.v:6536$2234_Y + connect \Y $and$ls180.v:6536$2235_Y end - attribute \src "ls180.v:6485.40-6485.98" - cell $and $and$ls180.v:6485$2171 + attribute \src "ls180.v:6537.40-6537.98" + cell $and $and$ls180.v:6537$2237 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6485$2170_Y - connect \Y $and$ls180.v:6485$2171_Y + connect \B $not$ls180.v:6537$2236_Y + connect \Y $and$ls180.v:6537$2237_Y end - attribute \src "ls180.v:6485.39-6485.150" - cell $and $and$ls180.v:6485$2173 + attribute \src "ls180.v:6537.39-6537.150" + cell $and $and$ls180.v:6537$2239 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6485$2171_Y - connect \B $eq$ls180.v:6485$2172_Y - connect \Y $and$ls180.v:6485$2173_Y + connect \A $and$ls180.v:6537$2237_Y + connect \B $eq$ls180.v:6537$2238_Y + connect \Y $and$ls180.v:6537$2239_Y end - attribute \src "ls180.v:6487.40-6487.95" - cell $and $and$ls180.v:6487$2174 + attribute \src "ls180.v:6539.40-6539.95" + cell $and $and$ls180.v:6539$2240 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -246530,43 +247398,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6487$2174_Y + connect \Y $and$ls180.v:6539$2240_Y end - attribute \src "ls180.v:6487.39-6487.147" - cell $and $and$ls180.v:6487$2176 + attribute \src "ls180.v:6539.39-6539.147" + cell $and $and$ls180.v:6539$2242 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6487$2174_Y - connect \B $eq$ls180.v:6487$2175_Y - connect \Y $and$ls180.v:6487$2176_Y + connect \A $and$ls180.v:6539$2240_Y + connect \B $eq$ls180.v:6539$2241_Y + connect \Y $and$ls180.v:6539$2242_Y end - attribute \src "ls180.v:6488.40-6488.98" - cell $and $and$ls180.v:6488$2178 + attribute \src "ls180.v:6540.40-6540.98" + cell $and $and$ls180.v:6540$2244 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6488$2177_Y - connect \Y $and$ls180.v:6488$2178_Y + connect \B $not$ls180.v:6540$2243_Y + connect \Y $and$ls180.v:6540$2244_Y end - attribute \src "ls180.v:6488.39-6488.150" - cell $and $and$ls180.v:6488$2180 + attribute \src "ls180.v:6540.39-6540.150" + cell $and $and$ls180.v:6540$2246 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6488$2178_Y - connect \B $eq$ls180.v:6488$2179_Y - connect \Y $and$ls180.v:6488$2180_Y + connect \A $and$ls180.v:6540$2244_Y + connect \B $eq$ls180.v:6540$2245_Y + connect \Y $and$ls180.v:6540$2246_Y end - attribute \src "ls180.v:6490.40-6490.95" - cell $and $and$ls180.v:6490$2181 + attribute \src "ls180.v:6542.40-6542.95" + cell $and $and$ls180.v:6542$2247 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -246574,43 +247442,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6490$2181_Y + connect \Y $and$ls180.v:6542$2247_Y end - attribute \src "ls180.v:6490.39-6490.147" - cell $and $and$ls180.v:6490$2183 + attribute \src "ls180.v:6542.39-6542.147" + cell $and $and$ls180.v:6542$2249 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6490$2181_Y - connect \B $eq$ls180.v:6490$2182_Y - connect \Y $and$ls180.v:6490$2183_Y + connect \A $and$ls180.v:6542$2247_Y + connect \B $eq$ls180.v:6542$2248_Y + connect \Y $and$ls180.v:6542$2249_Y end - attribute \src "ls180.v:6491.40-6491.98" - cell $and $and$ls180.v:6491$2185 + attribute \src "ls180.v:6543.40-6543.98" + cell $and $and$ls180.v:6543$2251 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6491$2184_Y - connect \Y $and$ls180.v:6491$2185_Y + connect \B $not$ls180.v:6543$2250_Y + connect \Y $and$ls180.v:6543$2251_Y end - attribute \src "ls180.v:6491.39-6491.150" - cell $and $and$ls180.v:6491$2187 + attribute \src "ls180.v:6543.39-6543.150" + cell $and $and$ls180.v:6543$2253 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6491$2185_Y - connect \B $eq$ls180.v:6491$2186_Y - connect \Y $and$ls180.v:6491$2187_Y + connect \A $and$ls180.v:6543$2251_Y + connect \B $eq$ls180.v:6543$2252_Y + connect \Y $and$ls180.v:6543$2253_Y end - attribute \src "ls180.v:6493.52-6493.107" - cell $and $and$ls180.v:6493$2188 + attribute \src "ls180.v:6545.52-6545.107" + cell $and $and$ls180.v:6545$2254 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -246618,43 +247486,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6493$2188_Y + connect \Y $and$ls180.v:6545$2254_Y end - attribute \src "ls180.v:6493.51-6493.159" - cell $and $and$ls180.v:6493$2190 + attribute \src "ls180.v:6545.51-6545.159" + cell $and $and$ls180.v:6545$2256 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6493$2188_Y - connect \B $eq$ls180.v:6493$2189_Y - connect \Y $and$ls180.v:6493$2190_Y + connect \A $and$ls180.v:6545$2254_Y + connect \B $eq$ls180.v:6545$2255_Y + connect \Y $and$ls180.v:6545$2256_Y end - attribute \src "ls180.v:6494.52-6494.110" - cell $and $and$ls180.v:6494$2192 + attribute \src "ls180.v:6546.52-6546.110" + cell $and $and$ls180.v:6546$2258 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6494$2191_Y - connect \Y $and$ls180.v:6494$2192_Y + connect \B $not$ls180.v:6546$2257_Y + connect \Y $and$ls180.v:6546$2258_Y end - attribute \src "ls180.v:6494.51-6494.162" - cell $and $and$ls180.v:6494$2194 + attribute \src "ls180.v:6546.51-6546.162" + cell $and $and$ls180.v:6546$2260 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6494$2192_Y - connect \B $eq$ls180.v:6494$2193_Y - connect \Y $and$ls180.v:6494$2194_Y + connect \A $and$ls180.v:6546$2258_Y + connect \B $eq$ls180.v:6546$2259_Y + connect \Y $and$ls180.v:6546$2260_Y end - attribute \src "ls180.v:6496.53-6496.108" - cell $and $and$ls180.v:6496$2195 + attribute \src "ls180.v:6548.53-6548.108" + cell $and $and$ls180.v:6548$2261 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -246662,43 +247530,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6496$2195_Y + connect \Y $and$ls180.v:6548$2261_Y end - attribute \src "ls180.v:6496.52-6496.160" - cell $and $and$ls180.v:6496$2197 + attribute \src "ls180.v:6548.52-6548.160" + cell $and $and$ls180.v:6548$2263 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6496$2195_Y - connect \B $eq$ls180.v:6496$2196_Y - connect \Y $and$ls180.v:6496$2197_Y + connect \A $and$ls180.v:6548$2261_Y + connect \B $eq$ls180.v:6548$2262_Y + connect \Y $and$ls180.v:6548$2263_Y end - attribute \src "ls180.v:6497.53-6497.111" - cell $and $and$ls180.v:6497$2199 + attribute \src "ls180.v:6549.53-6549.111" + cell $and $and$ls180.v:6549$2265 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6497$2198_Y - connect \Y $and$ls180.v:6497$2199_Y + connect \B $not$ls180.v:6549$2264_Y + connect \Y $and$ls180.v:6549$2265_Y end - attribute \src "ls180.v:6497.52-6497.163" - cell $and $and$ls180.v:6497$2201 + attribute \src "ls180.v:6549.52-6549.163" + cell $and $and$ls180.v:6549$2267 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6497$2199_Y - connect \B $eq$ls180.v:6497$2200_Y - connect \Y $and$ls180.v:6497$2201_Y + connect \A $and$ls180.v:6549$2265_Y + connect \B $eq$ls180.v:6549$2266_Y + connect \Y $and$ls180.v:6549$2267_Y end - attribute \src "ls180.v:6499.44-6499.99" - cell $and $and$ls180.v:6499$2202 + attribute \src "ls180.v:6551.44-6551.99" + cell $and $and$ls180.v:6551$2268 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -246706,43 +247574,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6499$2202_Y + connect \Y $and$ls180.v:6551$2268_Y end - attribute \src "ls180.v:6499.43-6499.151" - cell $and $and$ls180.v:6499$2204 + attribute \src "ls180.v:6551.43-6551.151" + cell $and $and$ls180.v:6551$2270 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6499$2202_Y - connect \B $eq$ls180.v:6499$2203_Y - connect \Y $and$ls180.v:6499$2204_Y + connect \A $and$ls180.v:6551$2268_Y + connect \B $eq$ls180.v:6551$2269_Y + connect \Y $and$ls180.v:6551$2270_Y end - attribute \src "ls180.v:6500.44-6500.102" - cell $and $and$ls180.v:6500$2206 + attribute \src "ls180.v:6552.44-6552.102" + cell $and $and$ls180.v:6552$2272 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6500$2205_Y - connect \Y $and$ls180.v:6500$2206_Y + connect \B $not$ls180.v:6552$2271_Y + connect \Y $and$ls180.v:6552$2272_Y end - attribute \src "ls180.v:6500.43-6500.154" - cell $and $and$ls180.v:6500$2208 + attribute \src "ls180.v:6552.43-6552.154" + cell $and $and$ls180.v:6552$2274 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6500$2206_Y - connect \B $eq$ls180.v:6500$2207_Y - connect \Y $and$ls180.v:6500$2208_Y + connect \A $and$ls180.v:6552$2272_Y + connect \B $eq$ls180.v:6552$2273_Y + connect \Y $and$ls180.v:6552$2274_Y end - attribute \src "ls180.v:6519.30-6519.85" - cell $and $and$ls180.v:6519$2210 + attribute \src "ls180.v:6571.30-6571.85" + cell $and $and$ls180.v:6571$2276 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -246750,43 +247618,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6519$2210_Y + connect \Y $and$ls180.v:6571$2276_Y end - attribute \src "ls180.v:6519.29-6519.136" - cell $and $and$ls180.v:6519$2212 + attribute \src "ls180.v:6571.29-6571.136" + cell $and $and$ls180.v:6571$2278 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6519$2210_Y - connect \B $eq$ls180.v:6519$2211_Y - connect \Y $and$ls180.v:6519$2212_Y + connect \A $and$ls180.v:6571$2276_Y + connect \B $eq$ls180.v:6571$2277_Y + connect \Y $and$ls180.v:6571$2278_Y end - attribute \src "ls180.v:6520.30-6520.88" - cell $and $and$ls180.v:6520$2214 + attribute \src "ls180.v:6572.30-6572.88" + cell $and $and$ls180.v:6572$2280 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6520$2213_Y - connect \Y $and$ls180.v:6520$2214_Y + connect \B $not$ls180.v:6572$2279_Y + connect \Y $and$ls180.v:6572$2280_Y end - attribute \src "ls180.v:6520.29-6520.139" - cell $and $and$ls180.v:6520$2216 + attribute \src "ls180.v:6572.29-6572.139" + cell $and $and$ls180.v:6572$2282 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6520$2214_Y - connect \B $eq$ls180.v:6520$2215_Y - connect \Y $and$ls180.v:6520$2216_Y + connect \A $and$ls180.v:6572$2280_Y + connect \B $eq$ls180.v:6572$2281_Y + connect \Y $and$ls180.v:6572$2282_Y end - attribute \src "ls180.v:6522.40-6522.95" - cell $and $and$ls180.v:6522$2217 + attribute \src "ls180.v:6574.40-6574.95" + cell $and $and$ls180.v:6574$2283 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -246794,43 +247662,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6522$2217_Y + connect \Y $and$ls180.v:6574$2283_Y end - attribute \src "ls180.v:6522.39-6522.146" - cell $and $and$ls180.v:6522$2219 + attribute \src "ls180.v:6574.39-6574.146" + cell $and $and$ls180.v:6574$2285 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6522$2217_Y - connect \B $eq$ls180.v:6522$2218_Y - connect \Y $and$ls180.v:6522$2219_Y + connect \A $and$ls180.v:6574$2283_Y + connect \B $eq$ls180.v:6574$2284_Y + connect \Y $and$ls180.v:6574$2285_Y end - attribute \src "ls180.v:6523.40-6523.98" - cell $and $and$ls180.v:6523$2221 + attribute \src "ls180.v:6575.40-6575.98" + cell $and $and$ls180.v:6575$2287 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6523$2220_Y - connect \Y $and$ls180.v:6523$2221_Y + connect \B $not$ls180.v:6575$2286_Y + connect \Y $and$ls180.v:6575$2287_Y end - attribute \src "ls180.v:6523.39-6523.149" - cell $and $and$ls180.v:6523$2223 + attribute \src "ls180.v:6575.39-6575.149" + cell $and $and$ls180.v:6575$2289 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6523$2221_Y - connect \B $eq$ls180.v:6523$2222_Y - connect \Y $and$ls180.v:6523$2223_Y + connect \A $and$ls180.v:6575$2287_Y + connect \B $eq$ls180.v:6575$2288_Y + connect \Y $and$ls180.v:6575$2289_Y end - attribute \src "ls180.v:6525.41-6525.96" - cell $and $and$ls180.v:6525$2224 + attribute \src "ls180.v:6577.41-6577.96" + cell $and $and$ls180.v:6577$2290 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -246838,43 +247706,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6525$2224_Y + connect \Y $and$ls180.v:6577$2290_Y end - attribute \src "ls180.v:6525.40-6525.147" - cell $and $and$ls180.v:6525$2226 + attribute \src "ls180.v:6577.40-6577.147" + cell $and $and$ls180.v:6577$2292 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6525$2224_Y - connect \B $eq$ls180.v:6525$2225_Y - connect \Y $and$ls180.v:6525$2226_Y + connect \A $and$ls180.v:6577$2290_Y + connect \B $eq$ls180.v:6577$2291_Y + connect \Y $and$ls180.v:6577$2292_Y end - attribute \src "ls180.v:6526.41-6526.99" - cell $and $and$ls180.v:6526$2228 + attribute \src "ls180.v:6578.41-6578.99" + cell $and $and$ls180.v:6578$2294 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6526$2227_Y - connect \Y $and$ls180.v:6526$2228_Y + connect \B $not$ls180.v:6578$2293_Y + connect \Y $and$ls180.v:6578$2294_Y end - attribute \src "ls180.v:6526.40-6526.150" - cell $and $and$ls180.v:6526$2230 + attribute \src "ls180.v:6578.40-6578.150" + cell $and $and$ls180.v:6578$2296 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6526$2228_Y - connect \B $eq$ls180.v:6526$2229_Y - connect \Y $and$ls180.v:6526$2230_Y + connect \A $and$ls180.v:6578$2294_Y + connect \B $eq$ls180.v:6578$2295_Y + connect \Y $and$ls180.v:6578$2296_Y end - attribute \src "ls180.v:6528.45-6528.100" - cell $and $and$ls180.v:6528$2231 + attribute \src "ls180.v:6580.45-6580.100" + cell $and $and$ls180.v:6580$2297 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -246882,43 +247750,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6528$2231_Y + connect \Y $and$ls180.v:6580$2297_Y end - attribute \src "ls180.v:6528.44-6528.151" - cell $and $and$ls180.v:6528$2233 + attribute \src "ls180.v:6580.44-6580.151" + cell $and $and$ls180.v:6580$2299 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6528$2231_Y - connect \B $eq$ls180.v:6528$2232_Y - connect \Y $and$ls180.v:6528$2233_Y + connect \A $and$ls180.v:6580$2297_Y + connect \B $eq$ls180.v:6580$2298_Y + connect \Y $and$ls180.v:6580$2299_Y end - attribute \src "ls180.v:6529.45-6529.103" - cell $and $and$ls180.v:6529$2235 + attribute \src "ls180.v:6581.45-6581.103" + cell $and $and$ls180.v:6581$2301 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6529$2234_Y - connect \Y $and$ls180.v:6529$2235_Y + connect \B $not$ls180.v:6581$2300_Y + connect \Y $and$ls180.v:6581$2301_Y end - attribute \src "ls180.v:6529.44-6529.154" - cell $and $and$ls180.v:6529$2237 + attribute \src "ls180.v:6581.44-6581.154" + cell $and $and$ls180.v:6581$2303 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6529$2235_Y - connect \B $eq$ls180.v:6529$2236_Y - connect \Y $and$ls180.v:6529$2237_Y + connect \A $and$ls180.v:6581$2301_Y + connect \B $eq$ls180.v:6581$2302_Y + connect \Y $and$ls180.v:6581$2303_Y end - attribute \src "ls180.v:6531.46-6531.101" - cell $and $and$ls180.v:6531$2238 + attribute \src "ls180.v:6583.46-6583.101" + cell $and $and$ls180.v:6583$2304 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -246926,43 +247794,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6531$2238_Y + connect \Y $and$ls180.v:6583$2304_Y end - attribute \src "ls180.v:6531.45-6531.152" - cell $and $and$ls180.v:6531$2240 + attribute \src "ls180.v:6583.45-6583.152" + cell $and $and$ls180.v:6583$2306 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6531$2238_Y - connect \B $eq$ls180.v:6531$2239_Y - connect \Y $and$ls180.v:6531$2240_Y + connect \A $and$ls180.v:6583$2304_Y + connect \B $eq$ls180.v:6583$2305_Y + connect \Y $and$ls180.v:6583$2306_Y end - attribute \src "ls180.v:6532.46-6532.104" - cell $and $and$ls180.v:6532$2242 + attribute \src "ls180.v:6584.46-6584.104" + cell $and $and$ls180.v:6584$2308 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6532$2241_Y - connect \Y $and$ls180.v:6532$2242_Y + connect \B $not$ls180.v:6584$2307_Y + connect \Y $and$ls180.v:6584$2308_Y end - attribute \src "ls180.v:6532.45-6532.155" - cell $and $and$ls180.v:6532$2244 + attribute \src "ls180.v:6584.45-6584.155" + cell $and $and$ls180.v:6584$2310 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6532$2242_Y - connect \B $eq$ls180.v:6532$2243_Y - connect \Y $and$ls180.v:6532$2244_Y + connect \A $and$ls180.v:6584$2308_Y + connect \B $eq$ls180.v:6584$2309_Y + connect \Y $and$ls180.v:6584$2310_Y end - attribute \src "ls180.v:6534.44-6534.99" - cell $and $and$ls180.v:6534$2245 + attribute \src "ls180.v:6586.44-6586.99" + cell $and $and$ls180.v:6586$2311 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -246970,43 +247838,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6534$2245_Y + connect \Y $and$ls180.v:6586$2311_Y end - attribute \src "ls180.v:6534.43-6534.150" - cell $and $and$ls180.v:6534$2247 + attribute \src "ls180.v:6586.43-6586.150" + cell $and $and$ls180.v:6586$2313 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6534$2245_Y - connect \B $eq$ls180.v:6534$2246_Y - connect \Y $and$ls180.v:6534$2247_Y + connect \A $and$ls180.v:6586$2311_Y + connect \B $eq$ls180.v:6586$2312_Y + connect \Y $and$ls180.v:6586$2313_Y end - attribute \src "ls180.v:6535.44-6535.102" - cell $and $and$ls180.v:6535$2249 + attribute \src "ls180.v:6587.44-6587.102" + cell $and $and$ls180.v:6587$2315 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6535$2248_Y - connect \Y $and$ls180.v:6535$2249_Y + connect \B $not$ls180.v:6587$2314_Y + connect \Y $and$ls180.v:6587$2315_Y end - attribute \src "ls180.v:6535.43-6535.153" - cell $and $and$ls180.v:6535$2251 + attribute \src "ls180.v:6587.43-6587.153" + cell $and $and$ls180.v:6587$2317 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6535$2249_Y - connect \B $eq$ls180.v:6535$2250_Y - connect \Y $and$ls180.v:6535$2251_Y + connect \A $and$ls180.v:6587$2315_Y + connect \B $eq$ls180.v:6587$2316_Y + connect \Y $and$ls180.v:6587$2317_Y end - attribute \src "ls180.v:6537.41-6537.96" - cell $and $and$ls180.v:6537$2252 + attribute \src "ls180.v:6589.41-6589.96" + cell $and $and$ls180.v:6589$2318 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247014,43 +247882,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6537$2252_Y + connect \Y $and$ls180.v:6589$2318_Y end - attribute \src "ls180.v:6537.40-6537.147" - cell $and $and$ls180.v:6537$2254 + attribute \src "ls180.v:6589.40-6589.147" + cell $and $and$ls180.v:6589$2320 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6537$2252_Y - connect \B $eq$ls180.v:6537$2253_Y - connect \Y $and$ls180.v:6537$2254_Y + connect \A $and$ls180.v:6589$2318_Y + connect \B $eq$ls180.v:6589$2319_Y + connect \Y $and$ls180.v:6589$2320_Y end - attribute \src "ls180.v:6538.41-6538.99" - cell $and $and$ls180.v:6538$2256 + attribute \src "ls180.v:6590.41-6590.99" + cell $and $and$ls180.v:6590$2322 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6538$2255_Y - connect \Y $and$ls180.v:6538$2256_Y + connect \B $not$ls180.v:6590$2321_Y + connect \Y $and$ls180.v:6590$2322_Y end - attribute \src "ls180.v:6538.40-6538.150" - cell $and $and$ls180.v:6538$2258 + attribute \src "ls180.v:6590.40-6590.150" + cell $and $and$ls180.v:6590$2324 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6538$2256_Y - connect \B $eq$ls180.v:6538$2257_Y - connect \Y $and$ls180.v:6538$2258_Y + connect \A $and$ls180.v:6590$2322_Y + connect \B $eq$ls180.v:6590$2323_Y + connect \Y $and$ls180.v:6590$2324_Y end - attribute \src "ls180.v:6540.40-6540.95" - cell $and $and$ls180.v:6540$2259 + attribute \src "ls180.v:6592.40-6592.95" + cell $and $and$ls180.v:6592$2325 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247058,43 +247926,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6540$2259_Y + connect \Y $and$ls180.v:6592$2325_Y end - attribute \src "ls180.v:6540.39-6540.146" - cell $and $and$ls180.v:6540$2261 + attribute \src "ls180.v:6592.39-6592.146" + cell $and $and$ls180.v:6592$2327 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6540$2259_Y - connect \B $eq$ls180.v:6540$2260_Y - connect \Y $and$ls180.v:6540$2261_Y + connect \A $and$ls180.v:6592$2325_Y + connect \B $eq$ls180.v:6592$2326_Y + connect \Y $and$ls180.v:6592$2327_Y end - attribute \src "ls180.v:6541.40-6541.98" - cell $and $and$ls180.v:6541$2263 + attribute \src "ls180.v:6593.40-6593.98" + cell $and $and$ls180.v:6593$2329 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6541$2262_Y - connect \Y $and$ls180.v:6541$2263_Y + connect \B $not$ls180.v:6593$2328_Y + connect \Y $and$ls180.v:6593$2329_Y end - attribute \src "ls180.v:6541.39-6541.149" - cell $and $and$ls180.v:6541$2265 + attribute \src "ls180.v:6593.39-6593.149" + cell $and $and$ls180.v:6593$2331 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6541$2263_Y - connect \B $eq$ls180.v:6541$2264_Y - connect \Y $and$ls180.v:6541$2265_Y + connect \A $and$ls180.v:6593$2329_Y + connect \B $eq$ls180.v:6593$2330_Y + connect \Y $and$ls180.v:6593$2331_Y end - attribute \src "ls180.v:6553.46-6553.101" - cell $and $and$ls180.v:6553$2267 + attribute \src "ls180.v:6605.46-6605.101" + cell $and $and$ls180.v:6605$2333 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247102,43 +247970,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank14_sel connect \B \builder_interface14_bank_bus_we - connect \Y $and$ls180.v:6553$2267_Y + connect \Y $and$ls180.v:6605$2333_Y end - attribute \src "ls180.v:6553.45-6553.152" - cell $and $and$ls180.v:6553$2269 + attribute \src "ls180.v:6605.45-6605.152" + cell $and $and$ls180.v:6605$2335 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6553$2267_Y - connect \B $eq$ls180.v:6553$2268_Y - connect \Y $and$ls180.v:6553$2269_Y + connect \A $and$ls180.v:6605$2333_Y + connect \B $eq$ls180.v:6605$2334_Y + connect \Y $and$ls180.v:6605$2335_Y end - attribute \src "ls180.v:6554.46-6554.104" - cell $and $and$ls180.v:6554$2271 + attribute \src "ls180.v:6606.46-6606.104" + cell $and $and$ls180.v:6606$2337 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank14_sel - connect \B $not$ls180.v:6554$2270_Y - connect \Y $and$ls180.v:6554$2271_Y + connect \B $not$ls180.v:6606$2336_Y + connect \Y $and$ls180.v:6606$2337_Y end - attribute \src "ls180.v:6554.45-6554.155" - cell $and $and$ls180.v:6554$2273 + attribute \src "ls180.v:6606.45-6606.155" + cell $and $and$ls180.v:6606$2339 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6554$2271_Y - connect \B $eq$ls180.v:6554$2272_Y - connect \Y $and$ls180.v:6554$2273_Y + connect \A $and$ls180.v:6606$2337_Y + connect \B $eq$ls180.v:6606$2338_Y + connect \Y $and$ls180.v:6606$2339_Y end - attribute \src "ls180.v:6556.46-6556.101" - cell $and $and$ls180.v:6556$2274 + attribute \src "ls180.v:6608.46-6608.101" + cell $and $and$ls180.v:6608$2340 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247146,43 +248014,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank14_sel connect \B \builder_interface14_bank_bus_we - connect \Y $and$ls180.v:6556$2274_Y + connect \Y $and$ls180.v:6608$2340_Y end - attribute \src "ls180.v:6556.45-6556.152" - cell $and $and$ls180.v:6556$2276 + attribute \src "ls180.v:6608.45-6608.152" + cell $and $and$ls180.v:6608$2342 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6556$2274_Y - connect \B $eq$ls180.v:6556$2275_Y - connect \Y $and$ls180.v:6556$2276_Y + connect \A $and$ls180.v:6608$2340_Y + connect \B $eq$ls180.v:6608$2341_Y + connect \Y $and$ls180.v:6608$2342_Y end - attribute \src "ls180.v:6557.46-6557.104" - cell $and $and$ls180.v:6557$2278 + attribute \src "ls180.v:6609.46-6609.104" + cell $and $and$ls180.v:6609$2344 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank14_sel - connect \B $not$ls180.v:6557$2277_Y - connect \Y $and$ls180.v:6557$2278_Y + connect \B $not$ls180.v:6609$2343_Y + connect \Y $and$ls180.v:6609$2344_Y end - attribute \src "ls180.v:6557.45-6557.155" - cell $and $and$ls180.v:6557$2280 + attribute \src "ls180.v:6609.45-6609.155" + cell $and $and$ls180.v:6609$2346 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6557$2278_Y - connect \B $eq$ls180.v:6557$2279_Y - connect \Y $and$ls180.v:6557$2280_Y + connect \A $and$ls180.v:6609$2344_Y + connect \B $eq$ls180.v:6609$2345_Y + connect \Y $and$ls180.v:6609$2346_Y end - attribute \src "ls180.v:6559.46-6559.101" - cell $and $and$ls180.v:6559$2281 + attribute \src "ls180.v:6611.46-6611.101" + cell $and $and$ls180.v:6611$2347 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247190,43 +248058,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank14_sel connect \B \builder_interface14_bank_bus_we - connect \Y $and$ls180.v:6559$2281_Y + connect \Y $and$ls180.v:6611$2347_Y end - attribute \src "ls180.v:6559.45-6559.152" - cell $and $and$ls180.v:6559$2283 + attribute \src "ls180.v:6611.45-6611.152" + cell $and $and$ls180.v:6611$2349 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6559$2281_Y - connect \B $eq$ls180.v:6559$2282_Y - connect \Y $and$ls180.v:6559$2283_Y + connect \A $and$ls180.v:6611$2347_Y + connect \B $eq$ls180.v:6611$2348_Y + connect \Y $and$ls180.v:6611$2349_Y end - attribute \src "ls180.v:6560.46-6560.104" - cell $and $and$ls180.v:6560$2285 + attribute \src "ls180.v:6612.46-6612.104" + cell $and $and$ls180.v:6612$2351 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank14_sel - connect \B $not$ls180.v:6560$2284_Y - connect \Y $and$ls180.v:6560$2285_Y + connect \B $not$ls180.v:6612$2350_Y + connect \Y $and$ls180.v:6612$2351_Y end - attribute \src "ls180.v:6560.45-6560.155" - cell $and $and$ls180.v:6560$2287 + attribute \src "ls180.v:6612.45-6612.155" + cell $and $and$ls180.v:6612$2353 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6560$2285_Y - connect \B $eq$ls180.v:6560$2286_Y - connect \Y $and$ls180.v:6560$2287_Y + connect \A $and$ls180.v:6612$2351_Y + connect \B $eq$ls180.v:6612$2352_Y + connect \Y $and$ls180.v:6612$2353_Y end - attribute \src "ls180.v:6562.46-6562.101" - cell $and $and$ls180.v:6562$2288 + attribute \src "ls180.v:6614.46-6614.101" + cell $and $and$ls180.v:6614$2354 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247234,263 +248102,263 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank14_sel connect \B \builder_interface14_bank_bus_we - connect \Y $and$ls180.v:6562$2288_Y + connect \Y $and$ls180.v:6614$2354_Y end - attribute \src "ls180.v:6562.45-6562.152" - cell $and $and$ls180.v:6562$2290 + attribute \src "ls180.v:6614.45-6614.152" + cell $and $and$ls180.v:6614$2356 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6562$2288_Y - connect \B $eq$ls180.v:6562$2289_Y - connect \Y $and$ls180.v:6562$2290_Y + connect \A $and$ls180.v:6614$2354_Y + connect \B $eq$ls180.v:6614$2355_Y + connect \Y $and$ls180.v:6614$2356_Y end - attribute \src "ls180.v:6563.46-6563.104" - cell $and $and$ls180.v:6563$2292 + attribute \src "ls180.v:6615.46-6615.104" + cell $and $and$ls180.v:6615$2358 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank14_sel - connect \B $not$ls180.v:6563$2291_Y - connect \Y $and$ls180.v:6563$2292_Y + connect \B $not$ls180.v:6615$2357_Y + connect \Y $and$ls180.v:6615$2358_Y end - attribute \src "ls180.v:6563.45-6563.155" - cell $and $and$ls180.v:6563$2294 + attribute \src "ls180.v:6615.45-6615.155" + cell $and $and$ls180.v:6615$2360 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6563$2292_Y - connect \B $eq$ls180.v:6563$2293_Y - connect \Y $and$ls180.v:6563$2294_Y + connect \A $and$ls180.v:6615$2358_Y + connect \B $eq$ls180.v:6615$2359_Y + connect \Y $and$ls180.v:6615$2360_Y end - attribute \src "ls180.v:6944.109-6944.178" - cell $and $and$ls180.v:6944$2332 + attribute \src "ls180.v:6996.109-6996.178" + cell $and $and$ls180.v:6996$2398 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:6944$2331_Y - connect \Y $and$ls180.v:6944$2332_Y + connect \B $eq$ls180.v:6996$2397_Y + connect \Y $and$ls180.v:6996$2398_Y end - attribute \src "ls180.v:6944.184-6944.253" - cell $and $and$ls180.v:6944$2335 + attribute \src "ls180.v:6996.184-6996.253" + cell $and $and$ls180.v:6996$2401 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:6944$2334_Y - connect \Y $and$ls180.v:6944$2335_Y + connect \B $eq$ls180.v:6996$2400_Y + connect \Y $and$ls180.v:6996$2401_Y end - attribute \src "ls180.v:6944.259-6944.328" - cell $and $and$ls180.v:6944$2338 + attribute \src "ls180.v:6996.259-6996.328" + cell $and $and$ls180.v:6996$2404 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:6944$2337_Y - connect \Y $and$ls180.v:6944$2338_Y + connect \B $eq$ls180.v:6996$2403_Y + connect \Y $and$ls180.v:6996$2404_Y end - attribute \src "ls180.v:6944.40-6944.331" - cell $and $and$ls180.v:6944$2341 + attribute \src "ls180.v:6996.40-6996.331" + cell $and $and$ls180.v:6996$2407 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:6944$2330_Y - connect \B $not$ls180.v:6944$2340_Y - connect \Y $and$ls180.v:6944$2341_Y + connect \A $eq$ls180.v:6996$2396_Y + connect \B $not$ls180.v:6996$2406_Y + connect \Y $and$ls180.v:6996$2407_Y end - attribute \src "ls180.v:6944.39-6944.354" - cell $and $and$ls180.v:6944$2342 + attribute \src "ls180.v:6996.39-6996.354" + cell $and $and$ls180.v:6996$2408 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6944$2341_Y + connect \A $and$ls180.v:6996$2407_Y connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:6944$2342_Y + connect \Y $and$ls180.v:6996$2408_Y end - attribute \src "ls180.v:6968.109-6968.178" - cell $and $and$ls180.v:6968$2348 + attribute \src "ls180.v:7020.109-7020.178" + cell $and $and$ls180.v:7020$2414 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:6968$2347_Y - connect \Y $and$ls180.v:6968$2348_Y + connect \B $eq$ls180.v:7020$2413_Y + connect \Y $and$ls180.v:7020$2414_Y end - attribute \src "ls180.v:6968.184-6968.253" - cell $and $and$ls180.v:6968$2351 + attribute \src "ls180.v:7020.184-7020.253" + cell $and $and$ls180.v:7020$2417 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:6968$2350_Y - connect \Y $and$ls180.v:6968$2351_Y + connect \B $eq$ls180.v:7020$2416_Y + connect \Y $and$ls180.v:7020$2417_Y end - attribute \src "ls180.v:6968.259-6968.328" - cell $and $and$ls180.v:6968$2354 + attribute \src "ls180.v:7020.259-7020.328" + cell $and $and$ls180.v:7020$2420 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:6968$2353_Y - connect \Y $and$ls180.v:6968$2354_Y + connect \B $eq$ls180.v:7020$2419_Y + connect \Y $and$ls180.v:7020$2420_Y end - attribute \src "ls180.v:6968.40-6968.331" - cell $and $and$ls180.v:6968$2357 + attribute \src "ls180.v:7020.40-7020.331" + cell $and $and$ls180.v:7020$2423 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:6968$2346_Y - connect \B $not$ls180.v:6968$2356_Y - connect \Y $and$ls180.v:6968$2357_Y + connect \A $eq$ls180.v:7020$2412_Y + connect \B $not$ls180.v:7020$2422_Y + connect \Y $and$ls180.v:7020$2423_Y end - attribute \src "ls180.v:6968.39-6968.354" - cell $and $and$ls180.v:6968$2358 + attribute \src "ls180.v:7020.39-7020.354" + cell $and $and$ls180.v:7020$2424 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6968$2357_Y + connect \A $and$ls180.v:7020$2423_Y connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:6968$2358_Y + connect \Y $and$ls180.v:7020$2424_Y end - attribute \src "ls180.v:6992.109-6992.178" - cell $and $and$ls180.v:6992$2364 + attribute \src "ls180.v:7044.109-7044.178" + cell $and $and$ls180.v:7044$2430 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:6992$2363_Y - connect \Y $and$ls180.v:6992$2364_Y + connect \B $eq$ls180.v:7044$2429_Y + connect \Y $and$ls180.v:7044$2430_Y end - attribute \src "ls180.v:6992.184-6992.253" - cell $and $and$ls180.v:6992$2367 + attribute \src "ls180.v:7044.184-7044.253" + cell $and $and$ls180.v:7044$2433 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:6992$2366_Y - connect \Y $and$ls180.v:6992$2367_Y + connect \B $eq$ls180.v:7044$2432_Y + connect \Y $and$ls180.v:7044$2433_Y end - attribute \src "ls180.v:6992.259-6992.328" - cell $and $and$ls180.v:6992$2370 + attribute \src "ls180.v:7044.259-7044.328" + cell $and $and$ls180.v:7044$2436 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:6992$2369_Y - connect \Y $and$ls180.v:6992$2370_Y + connect \B $eq$ls180.v:7044$2435_Y + connect \Y $and$ls180.v:7044$2436_Y end - attribute \src "ls180.v:6992.40-6992.331" - cell $and $and$ls180.v:6992$2373 + attribute \src "ls180.v:7044.40-7044.331" + cell $and $and$ls180.v:7044$2439 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:6992$2362_Y - connect \B $not$ls180.v:6992$2372_Y - connect \Y $and$ls180.v:6992$2373_Y + connect \A $eq$ls180.v:7044$2428_Y + connect \B $not$ls180.v:7044$2438_Y + connect \Y $and$ls180.v:7044$2439_Y end - attribute \src "ls180.v:6992.39-6992.354" - cell $and $and$ls180.v:6992$2374 + attribute \src "ls180.v:7044.39-7044.354" + cell $and $and$ls180.v:7044$2440 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6992$2373_Y + connect \A $and$ls180.v:7044$2439_Y connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:6992$2374_Y + connect \Y $and$ls180.v:7044$2440_Y end - attribute \src "ls180.v:7016.109-7016.178" - cell $and $and$ls180.v:7016$2380 + attribute \src "ls180.v:7068.109-7068.178" + cell $and $and$ls180.v:7068$2446 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:7016$2379_Y - connect \Y $and$ls180.v:7016$2380_Y + connect \B $eq$ls180.v:7068$2445_Y + connect \Y $and$ls180.v:7068$2446_Y end - attribute \src "ls180.v:7016.184-7016.253" - cell $and $and$ls180.v:7016$2383 + attribute \src "ls180.v:7068.184-7068.253" + cell $and $and$ls180.v:7068$2449 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:7016$2382_Y - connect \Y $and$ls180.v:7016$2383_Y + connect \B $eq$ls180.v:7068$2448_Y + connect \Y $and$ls180.v:7068$2449_Y end - attribute \src "ls180.v:7016.259-7016.328" - cell $and $and$ls180.v:7016$2386 + attribute \src "ls180.v:7068.259-7068.328" + cell $and $and$ls180.v:7068$2452 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:7016$2385_Y - connect \Y $and$ls180.v:7016$2386_Y + connect \B $eq$ls180.v:7068$2451_Y + connect \Y $and$ls180.v:7068$2452_Y end - attribute \src "ls180.v:7016.40-7016.331" - cell $and $and$ls180.v:7016$2389 + attribute \src "ls180.v:7068.40-7068.331" + cell $and $and$ls180.v:7068$2455 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:7016$2378_Y - connect \B $not$ls180.v:7016$2388_Y - connect \Y $and$ls180.v:7016$2389_Y + connect \A $eq$ls180.v:7068$2444_Y + connect \B $not$ls180.v:7068$2454_Y + connect \Y $and$ls180.v:7068$2455_Y end - attribute \src "ls180.v:7016.39-7016.354" - cell $and $and$ls180.v:7016$2390 + attribute \src "ls180.v:7068.39-7068.354" + cell $and $and$ls180.v:7068$2456 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7016$2389_Y + connect \A $and$ls180.v:7068$2455_Y connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:7016$2390_Y + connect \Y $and$ls180.v:7068$2456_Y end - attribute \src "ls180.v:7221.39-7221.104" - cell $and $and$ls180.v:7221$2402 + attribute \src "ls180.v:7273.39-7273.104" + cell $and $and$ls180.v:7273$2468 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247498,21 +248366,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7221$2402_Y + connect \Y $and$ls180.v:7273$2468_Y end - attribute \src "ls180.v:7221.38-7221.145" - cell $and $and$ls180.v:7221$2403 + attribute \src "ls180.v:7273.38-7273.145" + cell $and $and$ls180.v:7273$2469 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7221$2402_Y + connect \A $and$ls180.v:7273$2468_Y connect \B \main_sdram_choose_req_cmd_payload_cas - connect \Y $and$ls180.v:7221$2403_Y + connect \Y $and$ls180.v:7273$2469_Y end - attribute \src "ls180.v:7224.39-7224.104" - cell $and $and$ls180.v:7224$2404 + attribute \src "ls180.v:7276.39-7276.104" + cell $and $and$ls180.v:7276$2470 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247520,21 +248388,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7224$2404_Y + connect \Y $and$ls180.v:7276$2470_Y end - attribute \src "ls180.v:7224.38-7224.145" - cell $and $and$ls180.v:7224$2405 + attribute \src "ls180.v:7276.38-7276.145" + cell $and $and$ls180.v:7276$2471 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7224$2404_Y + connect \A $and$ls180.v:7276$2470_Y connect \B \main_sdram_choose_req_cmd_payload_cas - connect \Y $and$ls180.v:7224$2405_Y + connect \Y $and$ls180.v:7276$2471_Y end - attribute \src "ls180.v:7227.39-7227.82" - cell $and $and$ls180.v:7227$2406 + attribute \src "ls180.v:7279.39-7279.82" + cell $and $and$ls180.v:7279$2472 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247542,21 +248410,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_cmd_valid connect \B \main_sdram_cmd_ready - connect \Y $and$ls180.v:7227$2406_Y + connect \Y $and$ls180.v:7279$2472_Y end - attribute \src "ls180.v:7227.38-7227.112" - cell $and $and$ls180.v:7227$2407 + attribute \src "ls180.v:7279.38-7279.112" + cell $and $and$ls180.v:7279$2473 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7227$2406_Y + connect \A $and$ls180.v:7279$2472_Y connect \B \main_sdram_cmd_payload_cas - connect \Y $and$ls180.v:7227$2407_Y + connect \Y $and$ls180.v:7279$2473_Y end - attribute \src "ls180.v:7238.39-7238.104" - cell $and $and$ls180.v:7238$2409 + attribute \src "ls180.v:7290.39-7290.104" + cell $and $and$ls180.v:7290$2475 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247564,21 +248432,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7238$2409_Y + connect \Y $and$ls180.v:7290$2475_Y end - attribute \src "ls180.v:7238.38-7238.145" - cell $and $and$ls180.v:7238$2410 + attribute \src "ls180.v:7290.38-7290.145" + cell $and $and$ls180.v:7290$2476 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7238$2409_Y + connect \A $and$ls180.v:7290$2475_Y connect \B \main_sdram_choose_req_cmd_payload_ras - connect \Y $and$ls180.v:7238$2410_Y + connect \Y $and$ls180.v:7290$2476_Y end - attribute \src "ls180.v:7241.39-7241.104" - cell $and $and$ls180.v:7241$2411 + attribute \src "ls180.v:7293.39-7293.104" + cell $and $and$ls180.v:7293$2477 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247586,21 +248454,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7241$2411_Y + connect \Y $and$ls180.v:7293$2477_Y end - attribute \src "ls180.v:7241.38-7241.145" - cell $and $and$ls180.v:7241$2412 + attribute \src "ls180.v:7293.38-7293.145" + cell $and $and$ls180.v:7293$2478 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7241$2411_Y + connect \A $and$ls180.v:7293$2477_Y connect \B \main_sdram_choose_req_cmd_payload_ras - connect \Y $and$ls180.v:7241$2412_Y + connect \Y $and$ls180.v:7293$2478_Y end - attribute \src "ls180.v:7244.39-7244.82" - cell $and $and$ls180.v:7244$2413 + attribute \src "ls180.v:7296.39-7296.82" + cell $and $and$ls180.v:7296$2479 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247608,21 +248476,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_cmd_valid connect \B \main_sdram_cmd_ready - connect \Y $and$ls180.v:7244$2413_Y + connect \Y $and$ls180.v:7296$2479_Y end - attribute \src "ls180.v:7244.38-7244.112" - cell $and $and$ls180.v:7244$2414 + attribute \src "ls180.v:7296.38-7296.112" + cell $and $and$ls180.v:7296$2480 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7244$2413_Y + connect \A $and$ls180.v:7296$2479_Y connect \B \main_sdram_cmd_payload_ras - connect \Y $and$ls180.v:7244$2414_Y + connect \Y $and$ls180.v:7296$2480_Y end - attribute \src "ls180.v:7255.39-7255.104" - cell $and $and$ls180.v:7255$2416 + attribute \src "ls180.v:7307.39-7307.104" + cell $and $and$ls180.v:7307$2482 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247630,21 +248498,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7255$2416_Y + connect \Y $and$ls180.v:7307$2482_Y end - attribute \src "ls180.v:7255.38-7255.144" - cell $and $and$ls180.v:7255$2417 + attribute \src "ls180.v:7307.38-7307.144" + cell $and $and$ls180.v:7307$2483 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7255$2416_Y + connect \A $and$ls180.v:7307$2482_Y connect \B \main_sdram_choose_req_cmd_payload_we - connect \Y $and$ls180.v:7255$2417_Y + connect \Y $and$ls180.v:7307$2483_Y end - attribute \src "ls180.v:7258.39-7258.104" - cell $and $and$ls180.v:7258$2418 + attribute \src "ls180.v:7310.39-7310.104" + cell $and $and$ls180.v:7310$2484 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247652,21 +248520,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7258$2418_Y + connect \Y $and$ls180.v:7310$2484_Y end - attribute \src "ls180.v:7258.38-7258.144" - cell $and $and$ls180.v:7258$2419 + attribute \src "ls180.v:7310.38-7310.144" + cell $and $and$ls180.v:7310$2485 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7258$2418_Y + connect \A $and$ls180.v:7310$2484_Y connect \B \main_sdram_choose_req_cmd_payload_we - connect \Y $and$ls180.v:7258$2419_Y + connect \Y $and$ls180.v:7310$2485_Y end - attribute \src "ls180.v:7261.39-7261.82" - cell $and $and$ls180.v:7261$2420 + attribute \src "ls180.v:7313.39-7313.82" + cell $and $and$ls180.v:7313$2486 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247674,21 +248542,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_cmd_valid connect \B \main_sdram_cmd_ready - connect \Y $and$ls180.v:7261$2420_Y + connect \Y $and$ls180.v:7313$2486_Y end - attribute \src "ls180.v:7261.38-7261.111" - cell $and $and$ls180.v:7261$2421 + attribute \src "ls180.v:7313.38-7313.111" + cell $and $and$ls180.v:7313$2487 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7261$2420_Y + connect \A $and$ls180.v:7313$2486_Y connect \B \main_sdram_cmd_payload_we - connect \Y $and$ls180.v:7261$2421_Y + connect \Y $and$ls180.v:7313$2487_Y end - attribute \src "ls180.v:7272.39-7272.104" - cell $and $and$ls180.v:7272$2423 + attribute \src "ls180.v:7324.39-7324.104" + cell $and $and$ls180.v:7324$2489 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247696,21 +248564,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7272$2423_Y + connect \Y $and$ls180.v:7324$2489_Y end - attribute \src "ls180.v:7272.38-7272.149" - cell $and $and$ls180.v:7272$2424 + attribute \src "ls180.v:7324.38-7324.149" + cell $and $and$ls180.v:7324$2490 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7272$2423_Y + connect \A $and$ls180.v:7324$2489_Y connect \B \main_sdram_choose_req_cmd_payload_is_read - connect \Y $and$ls180.v:7272$2424_Y + connect \Y $and$ls180.v:7324$2490_Y end - attribute \src "ls180.v:7275.39-7275.104" - cell $and $and$ls180.v:7275$2425 + attribute \src "ls180.v:7327.39-7327.104" + cell $and $and$ls180.v:7327$2491 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247718,21 +248586,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7275$2425_Y + connect \Y $and$ls180.v:7327$2491_Y end - attribute \src "ls180.v:7275.38-7275.149" - cell $and $and$ls180.v:7275$2426 + attribute \src "ls180.v:7327.38-7327.149" + cell $and $and$ls180.v:7327$2492 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7275$2425_Y + connect \A $and$ls180.v:7327$2491_Y connect \B \main_sdram_choose_req_cmd_payload_is_read - connect \Y $and$ls180.v:7275$2426_Y + connect \Y $and$ls180.v:7327$2492_Y end - attribute \src "ls180.v:7278.39-7278.82" - cell $and $and$ls180.v:7278$2427 + attribute \src "ls180.v:7330.39-7330.82" + cell $and $and$ls180.v:7330$2493 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247740,21 +248608,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_cmd_valid connect \B \main_sdram_cmd_ready - connect \Y $and$ls180.v:7278$2427_Y + connect \Y $and$ls180.v:7330$2493_Y end - attribute \src "ls180.v:7278.38-7278.116" - cell $and $and$ls180.v:7278$2428 + attribute \src "ls180.v:7330.38-7330.116" + cell $and $and$ls180.v:7330$2494 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7278$2427_Y + connect \A $and$ls180.v:7330$2493_Y connect \B \main_sdram_cmd_payload_is_read - connect \Y $and$ls180.v:7278$2428_Y + connect \Y $and$ls180.v:7330$2494_Y end - attribute \src "ls180.v:7289.39-7289.104" - cell $and $and$ls180.v:7289$2430 + attribute \src "ls180.v:7341.39-7341.104" + cell $and $and$ls180.v:7341$2496 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247762,21 +248630,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7289$2430_Y + connect \Y $and$ls180.v:7341$2496_Y end - attribute \src "ls180.v:7289.38-7289.150" - cell $and $and$ls180.v:7289$2431 + attribute \src "ls180.v:7341.38-7341.150" + cell $and $and$ls180.v:7341$2497 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7289$2430_Y + connect \A $and$ls180.v:7341$2496_Y connect \B \main_sdram_choose_req_cmd_payload_is_write - connect \Y $and$ls180.v:7289$2431_Y + connect \Y $and$ls180.v:7341$2497_Y end - attribute \src "ls180.v:7292.39-7292.104" - cell $and $and$ls180.v:7292$2432 + attribute \src "ls180.v:7344.39-7344.104" + cell $and $and$ls180.v:7344$2498 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247784,21 +248652,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7292$2432_Y + connect \Y $and$ls180.v:7344$2498_Y end - attribute \src "ls180.v:7292.38-7292.150" - cell $and $and$ls180.v:7292$2433 + attribute \src "ls180.v:7344.38-7344.150" + cell $and $and$ls180.v:7344$2499 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7292$2432_Y + connect \A $and$ls180.v:7344$2498_Y connect \B \main_sdram_choose_req_cmd_payload_is_write - connect \Y $and$ls180.v:7292$2433_Y + connect \Y $and$ls180.v:7344$2499_Y end - attribute \src "ls180.v:7295.39-7295.82" - cell $and $and$ls180.v:7295$2434 + attribute \src "ls180.v:7347.39-7347.82" + cell $and $and$ls180.v:7347$2500 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247806,32 +248674,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_cmd_valid connect \B \main_sdram_cmd_ready - connect \Y $and$ls180.v:7295$2434_Y + connect \Y $and$ls180.v:7347$2500_Y end - attribute \src "ls180.v:7295.38-7295.117" - cell $and $and$ls180.v:7295$2435 + attribute \src "ls180.v:7347.38-7347.117" + cell $and $and$ls180.v:7347$2501 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7295$2434_Y + connect \A $and$ls180.v:7347$2500_Y connect \B \main_sdram_cmd_payload_is_write - connect \Y $and$ls180.v:7295$2435_Y + connect \Y $and$ls180.v:7347$2501_Y end - attribute \src "ls180.v:7514.17-7514.67" - cell $and $and$ls180.v:7514$2442 + attribute \src "ls180.v:7569.17-7569.67" + cell $and $and$ls180.v:7569$2509 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7514$2441_Y + connect \A $not$ls180.v:7569$2508_Y connect \B \main_sdphy_sdpads_clk - connect \Y $and$ls180.v:7514$2442_Y + connect \Y $and$ls180.v:7569$2509_Y end - attribute \src "ls180.v:7593.8-7593.67" - cell $and $and$ls180.v:7593$2473 + attribute \src "ls180.v:7648.8-7648.67" + cell $and $and$ls180.v:7648$2540 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247839,32 +248707,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_ram_bus_cyc connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:7593$2473_Y + connect \Y $and$ls180.v:7648$2540_Y end - attribute \src "ls180.v:7593.7-7593.102" - cell $and $and$ls180.v:7593$2475 + attribute \src "ls180.v:7648.7-7648.102" + cell $and $and$ls180.v:7648$2542 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7593$2473_Y - connect \B $not$ls180.v:7593$2474_Y - connect \Y $and$ls180.v:7593$2475_Y + connect \A $and$ls180.v:7648$2540_Y + connect \B $not$ls180.v:7648$2541_Y + connect \Y $and$ls180.v:7648$2542_Y end - attribute \src "ls180.v:7612.7-7612.75" - cell $and $and$ls180.v:7612$2479 + attribute \src "ls180.v:7667.7-7667.75" + cell $and $and$ls180.v:7667$2546 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7612$2478_Y + connect \A $not$ls180.v:7667$2545_Y connect \B \main_libresocsim_zero_old_trigger - connect \Y $and$ls180.v:7612$2479_Y + connect \Y $and$ls180.v:7667$2546_Y end - attribute \src "ls180.v:7616.8-7616.65" - cell $and $and$ls180.v:7616$2480 + attribute \src "ls180.v:7671.8-7671.65" + cell $and $and$ls180.v:7671$2547 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247872,21 +248740,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_interface0_ram_bus_cyc connect \B \main_interface0_ram_bus_stb - connect \Y $and$ls180.v:7616$2480_Y + connect \Y $and$ls180.v:7671$2547_Y end - attribute \src "ls180.v:7616.7-7616.99" - cell $and $and$ls180.v:7616$2482 + attribute \src "ls180.v:7671.7-7671.99" + cell $and $and$ls180.v:7671$2549 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7616$2480_Y - connect \B $not$ls180.v:7616$2481_Y - connect \Y $and$ls180.v:7616$2482_Y + connect \A $and$ls180.v:7671$2547_Y + connect \B $not$ls180.v:7671$2548_Y + connect \Y $and$ls180.v:7671$2549_Y end - attribute \src "ls180.v:7620.8-7620.65" - cell $and $and$ls180.v:7620$2483 + attribute \src "ls180.v:7675.8-7675.65" + cell $and $and$ls180.v:7675$2550 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247894,21 +248762,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_interface1_ram_bus_cyc connect \B \main_interface1_ram_bus_stb - connect \Y $and$ls180.v:7620$2483_Y + connect \Y $and$ls180.v:7675$2550_Y end - attribute \src "ls180.v:7620.7-7620.99" - cell $and $and$ls180.v:7620$2485 + attribute \src "ls180.v:7675.7-7675.99" + cell $and $and$ls180.v:7675$2552 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7620$2483_Y - connect \B $not$ls180.v:7620$2484_Y - connect \Y $and$ls180.v:7620$2485_Y + connect \A $and$ls180.v:7675$2550_Y + connect \B $not$ls180.v:7675$2551_Y + connect \Y $and$ls180.v:7675$2552_Y end - attribute \src "ls180.v:7624.8-7624.65" - cell $and $and$ls180.v:7624$2486 + attribute \src "ls180.v:7679.8-7679.65" + cell $and $and$ls180.v:7679$2553 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247916,43 +248784,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_interface2_ram_bus_cyc connect \B \main_interface2_ram_bus_stb - connect \Y $and$ls180.v:7624$2486_Y + connect \Y $and$ls180.v:7679$2553_Y end - attribute \src "ls180.v:7624.7-7624.99" - cell $and $and$ls180.v:7624$2488 + attribute \src "ls180.v:7679.7-7679.99" + cell $and $and$ls180.v:7679$2555 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7624$2486_Y - connect \B $not$ls180.v:7624$2487_Y - connect \Y $and$ls180.v:7624$2488_Y + connect \A $and$ls180.v:7679$2553_Y + connect \B $not$ls180.v:7679$2554_Y + connect \Y $and$ls180.v:7679$2555_Y end - attribute \src "ls180.v:7632.7-7632.56" - cell $and $and$ls180.v:7632$2490 + attribute \src "ls180.v:7687.7-7687.56" + cell $and $and$ls180.v:7687$2557 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_timer_wait - connect \B $not$ls180.v:7632$2489_Y - connect \Y $and$ls180.v:7632$2490_Y + connect \B $not$ls180.v:7687$2556_Y + connect \Y $and$ls180.v:7687$2557_Y end - attribute \src "ls180.v:7660.7-7660.75" - cell $and $and$ls180.v:7660$2497 + attribute \src "ls180.v:7715.7-7715.75" + cell $and $and$ls180.v:7715$2564 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_start1 - connect \B $eq$ls180.v:7660$2496_Y - connect \Y $and$ls180.v:7660$2497_Y + connect \B $eq$ls180.v:7715$2563_Y + connect \Y $and$ls180.v:7715$2564_Y end - attribute \src "ls180.v:7702.8-7702.131" - cell $and $and$ls180.v:7702$2503 + attribute \src "ls180.v:7757.8-7757.131" + cell $and $and$ls180.v:7757$2570 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247960,21 +248828,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable - connect \Y $and$ls180.v:7702$2503_Y + connect \Y $and$ls180.v:7757$2570_Y end - attribute \src "ls180.v:7702.7-7702.190" - cell $and $and$ls180.v:7702$2505 + attribute \src "ls180.v:7757.7-7757.190" + cell $and $and$ls180.v:7757$2572 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7702$2503_Y - connect \B $not$ls180.v:7702$2504_Y - connect \Y $and$ls180.v:7702$2505_Y + connect \A $and$ls180.v:7757$2570_Y + connect \B $not$ls180.v:7757$2571_Y + connect \Y $and$ls180.v:7757$2572_Y end - attribute \src "ls180.v:7708.8-7708.131" - cell $and $and$ls180.v:7708$2508 + attribute \src "ls180.v:7763.8-7763.131" + cell $and $and$ls180.v:7763$2575 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -247982,21 +248850,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable - connect \Y $and$ls180.v:7708$2508_Y + connect \Y $and$ls180.v:7763$2575_Y end - attribute \src "ls180.v:7708.7-7708.190" - cell $and $and$ls180.v:7708$2510 + attribute \src "ls180.v:7763.7-7763.190" + cell $and $and$ls180.v:7763$2577 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7708$2508_Y - connect \B $not$ls180.v:7708$2509_Y - connect \Y $and$ls180.v:7708$2510_Y + connect \A $and$ls180.v:7763$2575_Y + connect \B $not$ls180.v:7763$2576_Y + connect \Y $and$ls180.v:7763$2577_Y end - attribute \src "ls180.v:7748.8-7748.131" - cell $and $and$ls180.v:7748$2519 + attribute \src "ls180.v:7803.8-7803.131" + cell $and $and$ls180.v:7803$2586 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248004,21 +248872,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable - connect \Y $and$ls180.v:7748$2519_Y + connect \Y $and$ls180.v:7803$2586_Y end - attribute \src "ls180.v:7748.7-7748.190" - cell $and $and$ls180.v:7748$2521 + attribute \src "ls180.v:7803.7-7803.190" + cell $and $and$ls180.v:7803$2588 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7748$2519_Y - connect \B $not$ls180.v:7748$2520_Y - connect \Y $and$ls180.v:7748$2521_Y + connect \A $and$ls180.v:7803$2586_Y + connect \B $not$ls180.v:7803$2587_Y + connect \Y $and$ls180.v:7803$2588_Y end - attribute \src "ls180.v:7754.8-7754.131" - cell $and $and$ls180.v:7754$2524 + attribute \src "ls180.v:7809.8-7809.131" + cell $and $and$ls180.v:7809$2591 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248026,21 +248894,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable - connect \Y $and$ls180.v:7754$2524_Y + connect \Y $and$ls180.v:7809$2591_Y end - attribute \src "ls180.v:7754.7-7754.190" - cell $and $and$ls180.v:7754$2526 + attribute \src "ls180.v:7809.7-7809.190" + cell $and $and$ls180.v:7809$2593 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7754$2524_Y - connect \B $not$ls180.v:7754$2525_Y - connect \Y $and$ls180.v:7754$2526_Y + connect \A $and$ls180.v:7809$2591_Y + connect \B $not$ls180.v:7809$2592_Y + connect \Y $and$ls180.v:7809$2593_Y end - attribute \src "ls180.v:7794.8-7794.131" - cell $and $and$ls180.v:7794$2535 + attribute \src "ls180.v:7849.8-7849.131" + cell $and $and$ls180.v:7849$2602 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248048,21 +248916,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable - connect \Y $and$ls180.v:7794$2535_Y + connect \Y $and$ls180.v:7849$2602_Y end - attribute \src "ls180.v:7794.7-7794.190" - cell $and $and$ls180.v:7794$2537 + attribute \src "ls180.v:7849.7-7849.190" + cell $and $and$ls180.v:7849$2604 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7794$2535_Y - connect \B $not$ls180.v:7794$2536_Y - connect \Y $and$ls180.v:7794$2537_Y + connect \A $and$ls180.v:7849$2602_Y + connect \B $not$ls180.v:7849$2603_Y + connect \Y $and$ls180.v:7849$2604_Y end - attribute \src "ls180.v:7800.8-7800.131" - cell $and $and$ls180.v:7800$2540 + attribute \src "ls180.v:7855.8-7855.131" + cell $and $and$ls180.v:7855$2607 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248070,21 +248938,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable - connect \Y $and$ls180.v:7800$2540_Y + connect \Y $and$ls180.v:7855$2607_Y end - attribute \src "ls180.v:7800.7-7800.190" - cell $and $and$ls180.v:7800$2542 + attribute \src "ls180.v:7855.7-7855.190" + cell $and $and$ls180.v:7855$2609 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7800$2540_Y - connect \B $not$ls180.v:7800$2541_Y - connect \Y $and$ls180.v:7800$2542_Y + connect \A $and$ls180.v:7855$2607_Y + connect \B $not$ls180.v:7855$2608_Y + connect \Y $and$ls180.v:7855$2609_Y end - attribute \src "ls180.v:7840.8-7840.131" - cell $and $and$ls180.v:7840$2551 + attribute \src "ls180.v:7895.8-7895.131" + cell $and $and$ls180.v:7895$2618 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248092,21 +248960,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable - connect \Y $and$ls180.v:7840$2551_Y + connect \Y $and$ls180.v:7895$2618_Y end - attribute \src "ls180.v:7840.7-7840.190" - cell $and $and$ls180.v:7840$2553 + attribute \src "ls180.v:7895.7-7895.190" + cell $and $and$ls180.v:7895$2620 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7840$2551_Y - connect \B $not$ls180.v:7840$2552_Y - connect \Y $and$ls180.v:7840$2553_Y + connect \A $and$ls180.v:7895$2618_Y + connect \B $not$ls180.v:7895$2619_Y + connect \Y $and$ls180.v:7895$2620_Y end - attribute \src "ls180.v:7846.8-7846.131" - cell $and $and$ls180.v:7846$2556 + attribute \src "ls180.v:7901.8-7901.131" + cell $and $and$ls180.v:7901$2623 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248114,109 +248982,109 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable - connect \Y $and$ls180.v:7846$2556_Y + connect \Y $and$ls180.v:7901$2623_Y end - attribute \src "ls180.v:7846.7-7846.190" - cell $and $and$ls180.v:7846$2558 + attribute \src "ls180.v:7901.7-7901.190" + cell $and $and$ls180.v:7901$2625 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7846$2556_Y - connect \B $not$ls180.v:7846$2557_Y - connect \Y $and$ls180.v:7846$2558_Y + connect \A $and$ls180.v:7901$2623_Y + connect \B $not$ls180.v:7901$2624_Y + connect \Y $and$ls180.v:7901$2625_Y end - attribute \src "ls180.v:8043.48-8043.124" - cell $and $and$ls180.v:8043$2583 + attribute \src "ls180.v:8098.48-8098.124" + cell $and $and$ls180.v:8098$2650 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8043$2582_Y + connect \A $eq$ls180.v:8098$2649_Y connect \B \main_sdram_interface_bank0_wdata_ready - connect \Y $and$ls180.v:8043$2583_Y + connect \Y $and$ls180.v:8098$2650_Y end - attribute \src "ls180.v:8043.130-8043.206" - cell $and $and$ls180.v:8043$2586 + attribute \src "ls180.v:8098.130-8098.206" + cell $and $and$ls180.v:8098$2653 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8043$2585_Y + connect \A $eq$ls180.v:8098$2652_Y connect \B \main_sdram_interface_bank1_wdata_ready - connect \Y $and$ls180.v:8043$2586_Y + connect \Y $and$ls180.v:8098$2653_Y end - attribute \src "ls180.v:8043.212-8043.288" - cell $and $and$ls180.v:8043$2589 + attribute \src "ls180.v:8098.212-8098.288" + cell $and $and$ls180.v:8098$2656 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8043$2588_Y + connect \A $eq$ls180.v:8098$2655_Y connect \B \main_sdram_interface_bank2_wdata_ready - connect \Y $and$ls180.v:8043$2589_Y + connect \Y $and$ls180.v:8098$2656_Y end - attribute \src "ls180.v:8043.294-8043.370" - cell $and $and$ls180.v:8043$2592 + attribute \src "ls180.v:8098.294-8098.370" + cell $and $and$ls180.v:8098$2659 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8043$2591_Y + connect \A $eq$ls180.v:8098$2658_Y connect \B \main_sdram_interface_bank3_wdata_ready - connect \Y $and$ls180.v:8043$2592_Y + connect \Y $and$ls180.v:8098$2659_Y end - attribute \src "ls180.v:8044.49-8044.125" - cell $and $and$ls180.v:8044$2595 + attribute \src "ls180.v:8099.49-8099.125" + cell $and $and$ls180.v:8099$2662 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8044$2594_Y + connect \A $eq$ls180.v:8099$2661_Y connect \B \main_sdram_interface_bank0_rdata_valid - connect \Y $and$ls180.v:8044$2595_Y + connect \Y $and$ls180.v:8099$2662_Y end - attribute \src "ls180.v:8044.131-8044.207" - cell $and $and$ls180.v:8044$2598 + attribute \src "ls180.v:8099.131-8099.207" + cell $and $and$ls180.v:8099$2665 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8044$2597_Y + connect \A $eq$ls180.v:8099$2664_Y connect \B \main_sdram_interface_bank1_rdata_valid - connect \Y $and$ls180.v:8044$2598_Y + connect \Y $and$ls180.v:8099$2665_Y end - attribute \src "ls180.v:8044.213-8044.289" - cell $and $and$ls180.v:8044$2601 + attribute \src "ls180.v:8099.213-8099.289" + cell $and $and$ls180.v:8099$2668 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8044$2600_Y + connect \A $eq$ls180.v:8099$2667_Y connect \B \main_sdram_interface_bank2_rdata_valid - connect \Y $and$ls180.v:8044$2601_Y + connect \Y $and$ls180.v:8099$2668_Y end - attribute \src "ls180.v:8044.295-8044.371" - cell $and $and$ls180.v:8044$2604 + attribute \src "ls180.v:8099.295-8099.371" + cell $and $and$ls180.v:8099$2671 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8044$2603_Y + connect \A $eq$ls180.v:8099$2670_Y connect \B \main_sdram_interface_bank3_rdata_valid - connect \Y $and$ls180.v:8044$2604_Y + connect \Y $and$ls180.v:8099$2671_Y end - attribute \src "ls180.v:8063.8-8063.49" - cell $and $and$ls180.v:8063$2607 + attribute \src "ls180.v:8118.8-8118.49" + cell $and $and$ls180.v:8118$2674 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248224,10 +249092,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_valid connect \B \main_port_cmd_ready - connect \Y $and$ls180.v:8063$2607_Y + connect \Y $and$ls180.v:8118$2674_Y end - attribute \src "ls180.v:8066.8-8066.53" - cell $and $and$ls180.v:8066$2608 + attribute \src "ls180.v:8121.8-8121.53" + cell $and $and$ls180.v:8121$2675 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248235,32 +249103,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_wdata_valid connect \B \main_port_wdata_ready - connect \Y $and$ls180.v:8066$2608_Y + connect \Y $and$ls180.v:8121$2675_Y end - attribute \src "ls180.v:8071.8-8071.59" - cell $and $and$ls180.v:8071$2610 + attribute \src "ls180.v:8126.8-8126.59" + cell $and $and$ls180.v:8126$2677 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_phy_sink_valid - connect \B $not$ls180.v:8071$2609_Y - connect \Y $and$ls180.v:8071$2610_Y + connect \B $not$ls180.v:8126$2676_Y + connect \Y $and$ls180.v:8126$2677_Y end - attribute \src "ls180.v:8071.7-8071.90" - cell $and $and$ls180.v:8071$2612 + attribute \src "ls180.v:8126.7-8126.90" + cell $and $and$ls180.v:8126$2679 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8071$2610_Y - connect \B $not$ls180.v:8071$2611_Y - connect \Y $and$ls180.v:8071$2612_Y + connect \A $and$ls180.v:8126$2677_Y + connect \B $not$ls180.v:8126$2678_Y + connect \Y $and$ls180.v:8126$2679_Y end - attribute \src "ls180.v:8077.8-8077.59" - cell $and $and$ls180.v:8077$2613 + attribute \src "ls180.v:8132.8-8132.59" + cell $and $and$ls180.v:8132$2680 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248268,43 +249136,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_phy_uart_clk_txen connect \B \main_uart_phy_tx_busy - connect \Y $and$ls180.v:8077$2613_Y + connect \Y $and$ls180.v:8132$2680_Y end - attribute \src "ls180.v:8101.8-8101.48" - cell $and $and$ls180.v:8101$2620 + attribute \src "ls180.v:8156.8-8156.48" + cell $and $and$ls180.v:8156$2687 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8101$2619_Y + connect \A $not$ls180.v:8156$2686_Y connect \B \main_uart_phy_rx_r - connect \Y $and$ls180.v:8101$2620_Y + connect \Y $and$ls180.v:8156$2687_Y end - attribute \src "ls180.v:8134.7-8134.57" - cell $and $and$ls180.v:8134$2626 + attribute \src "ls180.v:8189.7-8189.57" + cell $and $and$ls180.v:8189$2693 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8134$2625_Y + connect \A $not$ls180.v:8189$2692_Y connect \B \main_uart_tx_old_trigger - connect \Y $and$ls180.v:8134$2626_Y + connect \Y $and$ls180.v:8189$2693_Y end - attribute \src "ls180.v:8141.7-8141.57" - cell $and $and$ls180.v:8141$2628 + attribute \src "ls180.v:8196.7-8196.57" + cell $and $and$ls180.v:8196$2695 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8141$2627_Y + connect \A $not$ls180.v:8196$2694_Y connect \B \main_uart_rx_old_trigger - connect \Y $and$ls180.v:8141$2628_Y + connect \Y $and$ls180.v:8196$2695_Y end - attribute \src "ls180.v:8151.8-8151.75" - cell $and $and$ls180.v:8151$2629 + attribute \src "ls180.v:8206.8-8206.75" + cell $and $and$ls180.v:8206$2696 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248312,21 +249180,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_syncfifo_we connect \B \main_uart_tx_fifo_syncfifo_writable - connect \Y $and$ls180.v:8151$2629_Y + connect \Y $and$ls180.v:8206$2696_Y end - attribute \src "ls180.v:8151.7-8151.107" - cell $and $and$ls180.v:8151$2631 + attribute \src "ls180.v:8206.7-8206.107" + cell $and $and$ls180.v:8206$2698 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8151$2629_Y - connect \B $not$ls180.v:8151$2630_Y - connect \Y $and$ls180.v:8151$2631_Y + connect \A $and$ls180.v:8206$2696_Y + connect \B $not$ls180.v:8206$2697_Y + connect \Y $and$ls180.v:8206$2698_Y end - attribute \src "ls180.v:8157.8-8157.75" - cell $and $and$ls180.v:8157$2634 + attribute \src "ls180.v:8212.8-8212.75" + cell $and $and$ls180.v:8212$2701 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248334,21 +249202,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_syncfifo_we connect \B \main_uart_tx_fifo_syncfifo_writable - connect \Y $and$ls180.v:8157$2634_Y + connect \Y $and$ls180.v:8212$2701_Y end - attribute \src "ls180.v:8157.7-8157.107" - cell $and $and$ls180.v:8157$2636 + attribute \src "ls180.v:8212.7-8212.107" + cell $and $and$ls180.v:8212$2703 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8157$2634_Y - connect \B $not$ls180.v:8157$2635_Y - connect \Y $and$ls180.v:8157$2636_Y + connect \A $and$ls180.v:8212$2701_Y + connect \B $not$ls180.v:8212$2702_Y + connect \Y $and$ls180.v:8212$2703_Y end - attribute \src "ls180.v:8173.8-8173.75" - cell $and $and$ls180.v:8173$2640 + attribute \src "ls180.v:8228.8-8228.75" + cell $and $and$ls180.v:8228$2707 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248356,21 +249224,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_syncfifo_we connect \B \main_uart_rx_fifo_syncfifo_writable - connect \Y $and$ls180.v:8173$2640_Y + connect \Y $and$ls180.v:8228$2707_Y end - attribute \src "ls180.v:8173.7-8173.107" - cell $and $and$ls180.v:8173$2642 + attribute \src "ls180.v:8228.7-8228.107" + cell $and $and$ls180.v:8228$2709 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8173$2640_Y - connect \B $not$ls180.v:8173$2641_Y - connect \Y $and$ls180.v:8173$2642_Y + connect \A $and$ls180.v:8228$2707_Y + connect \B $not$ls180.v:8228$2708_Y + connect \Y $and$ls180.v:8228$2709_Y end - attribute \src "ls180.v:8179.8-8179.75" - cell $and $and$ls180.v:8179$2645 + attribute \src "ls180.v:8234.8-8234.75" + cell $and $and$ls180.v:8234$2712 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248378,21 +249246,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_syncfifo_we connect \B \main_uart_rx_fifo_syncfifo_writable - connect \Y $and$ls180.v:8179$2645_Y + connect \Y $and$ls180.v:8234$2712_Y end - attribute \src "ls180.v:8179.7-8179.107" - cell $and $and$ls180.v:8179$2647 + attribute \src "ls180.v:8234.7-8234.107" + cell $and $and$ls180.v:8234$2714 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8179$2645_Y - connect \B $not$ls180.v:8179$2646_Y - connect \Y $and$ls180.v:8179$2647_Y + connect \A $and$ls180.v:8234$2712_Y + connect \B $not$ls180.v:8234$2713_Y + connect \Y $and$ls180.v:8234$2714_Y end - attribute \src "ls180.v:8327.7-8327.96" - cell $and $and$ls180.v:8327$2675 + attribute \src "ls180.v:8382.7-8382.96" + cell $and $and$ls180.v:8382$2742 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248400,10 +249268,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_converter_source_valid connect \B \main_sdphy_cmdr_cmdr_converter_source_ready - connect \Y $and$ls180.v:8327$2675_Y + connect \Y $and$ls180.v:8382$2742_Y end - attribute \src "ls180.v:8328.8-8328.93" - cell $and $and$ls180.v:8328$2676 + attribute \src "ls180.v:8383.8-8383.93" + cell $and $and$ls180.v:8383$2743 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248411,10 +249279,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_converter_sink_valid connect \B \main_sdphy_cmdr_cmdr_converter_sink_ready - connect \Y $and$ls180.v:8328$2676_Y + connect \Y $and$ls180.v:8383$2743_Y end - attribute \src "ls180.v:8336.8-8336.93" - cell $and $and$ls180.v:8336$2677 + attribute \src "ls180.v:8391.8-8391.93" + cell $and $and$ls180.v:8391$2744 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248422,10 +249290,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_converter_sink_valid connect \B \main_sdphy_cmdr_cmdr_converter_sink_ready - connect \Y $and$ls180.v:8336$2677_Y + connect \Y $and$ls180.v:8391$2744_Y end - attribute \src "ls180.v:8408.7-8408.98" - cell $and $and$ls180.v:8408$2687 + attribute \src "ls180.v:8463.7-8463.98" + cell $and $and$ls180.v:8463$2754 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248433,10 +249301,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_converter_source_valid connect \B \main_sdphy_dataw_crcr_converter_source_ready - connect \Y $and$ls180.v:8408$2687_Y + connect \Y $and$ls180.v:8463$2754_Y end - attribute \src "ls180.v:8409.8-8409.95" - cell $and $and$ls180.v:8409$2688 + attribute \src "ls180.v:8464.8-8464.95" + cell $and $and$ls180.v:8464$2755 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248444,10 +249312,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_converter_sink_valid connect \B \main_sdphy_dataw_crcr_converter_sink_ready - connect \Y $and$ls180.v:8409$2688_Y + connect \Y $and$ls180.v:8464$2755_Y end - attribute \src "ls180.v:8417.8-8417.95" - cell $and $and$ls180.v:8417$2689 + attribute \src "ls180.v:8472.8-8472.95" + cell $and $and$ls180.v:8472$2756 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248455,10 +249323,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_converter_sink_valid connect \B \main_sdphy_dataw_crcr_converter_sink_ready - connect \Y $and$ls180.v:8417$2689_Y + connect \Y $and$ls180.v:8472$2756_Y end - attribute \src "ls180.v:8487.7-8487.100" - cell $and $and$ls180.v:8487$2699 + attribute \src "ls180.v:8542.7-8542.100" + cell $and $and$ls180.v:8542$2766 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248466,10 +249334,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_converter_source_valid connect \B \main_sdphy_datar_datar_converter_source_ready - connect \Y $and$ls180.v:8487$2699_Y + connect \Y $and$ls180.v:8542$2766_Y end - attribute \src "ls180.v:8488.8-8488.97" - cell $and $and$ls180.v:8488$2700 + attribute \src "ls180.v:8543.8-8543.97" + cell $and $and$ls180.v:8543$2767 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248477,10 +249345,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_converter_sink_valid connect \B \main_sdphy_datar_datar_converter_sink_ready - connect \Y $and$ls180.v:8488$2700_Y + connect \Y $and$ls180.v:8543$2767_Y end - attribute \src "ls180.v:8496.8-8496.97" - cell $and $and$ls180.v:8496$2701 + attribute \src "ls180.v:8551.8-8551.97" + cell $and $and$ls180.v:8551$2768 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248488,10 +249356,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_converter_sink_valid connect \B \main_sdphy_datar_datar_converter_sink_ready - connect \Y $and$ls180.v:8496$2701_Y + connect \Y $and$ls180.v:8551$2768_Y end - attribute \src "ls180.v:8587.7-8587.82" - cell $and $and$ls180.v:8587$2707 + attribute \src "ls180.v:8642.7-8642.82" + cell $and $and$ls180.v:8642$2774 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248499,10 +249367,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_ready connect \B \main_sdcore_crc16_checker_sink_valid - connect \Y $and$ls180.v:8587$2707_Y + connect \Y $and$ls180.v:8642$2774_Y end - attribute \src "ls180.v:8590.7-8590.82" - cell $and $and$ls180.v:8590$2708 + attribute \src "ls180.v:8645.7-8645.82" + cell $and $and$ls180.v:8645$2775 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248510,10 +249378,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_ready connect \B \main_sdcore_crc16_checker_sink_valid - connect \Y $and$ls180.v:8590$2708_Y + connect \Y $and$ls180.v:8645$2775_Y end - attribute \src "ls180.v:8593.7-8593.82" - cell $and $and$ls180.v:8593$2709 + attribute \src "ls180.v:8648.7-8648.82" + cell $and $and$ls180.v:8648$2776 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248521,10 +249389,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_ready connect \B \main_sdcore_crc16_checker_sink_valid - connect \Y $and$ls180.v:8593$2709_Y + connect \Y $and$ls180.v:8648$2776_Y end - attribute \src "ls180.v:8596.7-8596.82" - cell $and $and$ls180.v:8596$2710 + attribute \src "ls180.v:8651.7-8651.82" + cell $and $and$ls180.v:8651$2777 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248532,10 +249400,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_ready connect \B \main_sdcore_crc16_checker_sink_valid - connect \Y $and$ls180.v:8596$2710_Y + connect \Y $and$ls180.v:8651$2777_Y end - attribute \src "ls180.v:8599.7-8599.82" - cell $and $and$ls180.v:8599$2711 + attribute \src "ls180.v:8654.7-8654.82" + cell $and $and$ls180.v:8654$2778 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248543,10 +249411,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_valid connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:8599$2711_Y + connect \Y $and$ls180.v:8654$2778_Y end - attribute \src "ls180.v:8604.7-8604.82" - cell $and $and$ls180.v:8604$2712 + attribute \src "ls180.v:8659.7-8659.82" + cell $and $and$ls180.v:8659$2779 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248554,10 +249422,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_valid connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:8604$2712_Y + connect \Y $and$ls180.v:8659$2779_Y end - attribute \src "ls180.v:8609.7-8609.82" - cell $and $and$ls180.v:8609$2713 + attribute \src "ls180.v:8664.7-8664.82" + cell $and $and$ls180.v:8664$2780 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248565,10 +249433,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_valid connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:8609$2713_Y + connect \Y $and$ls180.v:8664$2780_Y end - attribute \src "ls180.v:8614.7-8614.82" - cell $and $and$ls180.v:8614$2714 + attribute \src "ls180.v:8669.7-8669.82" + cell $and $and$ls180.v:8669$2781 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248576,10 +249444,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_valid connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:8614$2714_Y + connect \Y $and$ls180.v:8669$2781_Y end - attribute \src "ls180.v:8619.7-8619.82" - cell $and $and$ls180.v:8619$2715 + attribute \src "ls180.v:8674.7-8674.82" + cell $and $and$ls180.v:8674$2782 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248587,10 +249455,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_valid connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:8619$2715_Y + connect \Y $and$ls180.v:8674$2782_Y end - attribute \src "ls180.v:8684.8-8684.83" - cell $and $and$ls180.v:8684$2718 + attribute \src "ls180.v:8739.8-8739.83" + cell $and $and$ls180.v:8739$2785 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248598,21 +249466,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_fifo_syncfifo_we connect \B \main_sdblock2mem_fifo_syncfifo_writable - connect \Y $and$ls180.v:8684$2718_Y + connect \Y $and$ls180.v:8739$2785_Y end - attribute \src "ls180.v:8684.7-8684.119" - cell $and $and$ls180.v:8684$2720 + attribute \src "ls180.v:8739.7-8739.119" + cell $and $and$ls180.v:8739$2787 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8684$2718_Y - connect \B $not$ls180.v:8684$2719_Y - connect \Y $and$ls180.v:8684$2720_Y + connect \A $and$ls180.v:8739$2785_Y + connect \B $not$ls180.v:8739$2786_Y + connect \Y $and$ls180.v:8739$2787_Y end - attribute \src "ls180.v:8690.8-8690.83" - cell $and $and$ls180.v:8690$2723 + attribute \src "ls180.v:8745.8-8745.83" + cell $and $and$ls180.v:8745$2790 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248620,21 +249488,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_fifo_syncfifo_we connect \B \main_sdblock2mem_fifo_syncfifo_writable - connect \Y $and$ls180.v:8690$2723_Y + connect \Y $and$ls180.v:8745$2790_Y end - attribute \src "ls180.v:8690.7-8690.119" - cell $and $and$ls180.v:8690$2725 + attribute \src "ls180.v:8745.7-8745.119" + cell $and $and$ls180.v:8745$2792 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8690$2723_Y - connect \B $not$ls180.v:8690$2724_Y - connect \Y $and$ls180.v:8690$2725_Y + connect \A $and$ls180.v:8745$2790_Y + connect \B $not$ls180.v:8745$2791_Y + connect \Y $and$ls180.v:8745$2792_Y end - attribute \src "ls180.v:8710.7-8710.88" - cell $and $and$ls180.v:8710$2732 + attribute \src "ls180.v:8765.7-8765.88" + cell $and $and$ls180.v:8765$2799 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248642,10 +249510,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_converter_source_valid connect \B \main_sdblock2mem_converter_source_ready - connect \Y $and$ls180.v:8710$2732_Y + connect \Y $and$ls180.v:8765$2799_Y end - attribute \src "ls180.v:8711.8-8711.85" - cell $and $and$ls180.v:8711$2733 + attribute \src "ls180.v:8766.8-8766.85" + cell $and $and$ls180.v:8766$2800 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248653,10 +249521,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_converter_sink_valid connect \B \main_sdblock2mem_converter_sink_ready - connect \Y $and$ls180.v:8711$2733_Y + connect \Y $and$ls180.v:8766$2800_Y end - attribute \src "ls180.v:8719.8-8719.85" - cell $and $and$ls180.v:8719$2734 + attribute \src "ls180.v:8774.8-8774.85" + cell $and $and$ls180.v:8774$2801 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248664,10 +249532,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_converter_sink_valid connect \B \main_sdblock2mem_converter_sink_ready - connect \Y $and$ls180.v:8719$2734_Y + connect \Y $and$ls180.v:8774$2801_Y end - attribute \src "ls180.v:8763.7-8763.88" - cell $and $and$ls180.v:8763$2738 + attribute \src "ls180.v:8830.7-8830.88" + cell $and $and$ls180.v:8830$2805 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248675,10 +249543,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_converter_source_valid connect \B \main_sdmem2block_converter_source_ready - connect \Y $and$ls180.v:8763$2738_Y + connect \Y $and$ls180.v:8830$2805_Y end - attribute \src "ls180.v:8770.8-8770.83" - cell $and $and$ls180.v:8770$2740 + attribute \src "ls180.v:8837.8-8837.83" + cell $and $and$ls180.v:8837$2807 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248686,21 +249554,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_fifo_syncfifo_we connect \B \main_sdmem2block_fifo_syncfifo_writable - connect \Y $and$ls180.v:8770$2740_Y + connect \Y $and$ls180.v:8837$2807_Y end - attribute \src "ls180.v:8770.7-8770.119" - cell $and $and$ls180.v:8770$2742 + attribute \src "ls180.v:8837.7-8837.119" + cell $and $and$ls180.v:8837$2809 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8770$2740_Y - connect \B $not$ls180.v:8770$2741_Y - connect \Y $and$ls180.v:8770$2742_Y + connect \A $and$ls180.v:8837$2807_Y + connect \B $not$ls180.v:8837$2808_Y + connect \Y $and$ls180.v:8837$2809_Y end - attribute \src "ls180.v:8776.8-8776.83" - cell $and $and$ls180.v:8776$2745 + attribute \src "ls180.v:8843.8-8843.83" + cell $and $and$ls180.v:8843$2812 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248708,87 +249576,87 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_fifo_syncfifo_we connect \B \main_sdmem2block_fifo_syncfifo_writable - connect \Y $and$ls180.v:8776$2745_Y + connect \Y $and$ls180.v:8843$2812_Y end - attribute \src "ls180.v:8776.7-8776.119" - cell $and $and$ls180.v:8776$2747 + attribute \src "ls180.v:8843.7-8843.119" + cell $and $and$ls180.v:8843$2814 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8776$2745_Y - connect \B $not$ls180.v:8776$2746_Y - connect \Y $and$ls180.v:8776$2747_Y + connect \A $and$ls180.v:8843$2812_Y + connect \B $not$ls180.v:8843$2813_Y + connect \Y $and$ls180.v:8843$2814_Y end - attribute \src "ls180.v:2855.42-2855.101" - cell $eq $eq$ls180.v:2855$30 + attribute \src "ls180.v:2868.30-2868.76" + cell $eq $eq$ls180.v:2868$46 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_interface0_converted_interface_sel + connect \A \main_libresocsim_libresoc_xics_icp_sel connect \B 1'0 - connect \Y $eq$ls180.v:2855$30_Y + connect \Y $eq$ls180.v:2868$46_Y end - attribute \src "ls180.v:2862.11-2862.54" - cell $eq $eq$ls180.v:2862$35 + attribute \src "ls180.v:2875.11-2875.42" + cell $eq $eq$ls180.v:2875$51 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_converter0_counter + connect \A \main_converter0_counter connect \B 1'1 - connect \Y $eq$ls180.v:2862$35_Y + connect \Y $eq$ls180.v:2875$51_Y end - attribute \src "ls180.v:2915.42-2915.101" - cell $eq $eq$ls180.v:2915$41 + attribute \src "ls180.v:2928.30-2928.76" + cell $eq $eq$ls180.v:2928$57 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_interface1_converted_interface_sel + connect \A \main_libresocsim_libresoc_xics_ics_sel connect \B 1'0 - connect \Y $eq$ls180.v:2915$41_Y + connect \Y $eq$ls180.v:2928$57_Y end - attribute \src "ls180.v:2922.11-2922.54" - cell $eq $eq$ls180.v:2922$46 + attribute \src "ls180.v:2935.11-2935.42" + cell $eq $eq$ls180.v:2935$62 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_converter1_counter + connect \A \main_converter1_counter connect \B 1'1 - connect \Y $eq$ls180.v:2922$46_Y + connect \Y $eq$ls180.v:2935$62_Y end - attribute \src "ls180.v:2975.42-2975.101" - cell $eq $eq$ls180.v:2975$52 + attribute \src "ls180.v:2988.33-2988.58" + cell $eq $eq$ls180.v:2988$68 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_interface2_converted_interface_sel + connect \A \main_wb_sdram_sel connect \B 1'0 - connect \Y $eq$ls180.v:2975$52_Y + connect \Y $eq$ls180.v:2988$68_Y end - attribute \src "ls180.v:2982.11-2982.54" - cell $eq $eq$ls180.v:2982$57 + attribute \src "ls180.v:2995.11-2995.45" + cell $eq $eq$ls180.v:2995$73 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_converter2_counter + connect \A \main_socbushandler_counter connect \B 1'1 - connect \Y $eq$ls180.v:2982$57_Y + connect \Y $eq$ls180.v:2995$73_Y end - attribute \src "ls180.v:3198.34-3198.65" - cell $eq $eq$ls180.v:3198$124 + attribute \src "ls180.v:3227.34-3227.65" + cell $eq $eq$ls180.v:3227$188 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -248796,10 +249664,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_timer_count1 connect \B 1'0 - connect \Y $eq$ls180.v:3198$124_Y + connect \Y $eq$ls180.v:3227$188_Y end - attribute \src "ls180.v:3202.68-3202.102" - cell $eq $eq$ls180.v:3202$127 + attribute \src "ls180.v:3231.68-3231.102" + cell $eq $eq$ls180.v:3231$191 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248807,10 +249675,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_count connect \B 1'0 - connect \Y $eq$ls180.v:3202$127_Y + connect \Y $eq$ls180.v:3231$191_Y end - attribute \src "ls180.v:3246.43-3246.134" - cell $eq $eq$ls180.v:3246$132 + attribute \src "ls180.v:3275.43-3275.134" + cell $eq $eq$ls180.v:3275$196 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 @@ -248818,10 +249686,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_row connect \B \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] - connect \Y $eq$ls180.v:3246$132_Y + connect \Y $eq$ls180.v:3275$196_Y end - attribute \src "ls180.v:3263.47-3263.88" - cell $eq $eq$ls180.v:3263$145 + attribute \src "ls180.v:3292.47-3292.88" + cell $eq $eq$ls180.v:3292$209 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248829,10 +249697,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_row_close connect \B 1'0 - connect \Y $eq$ls180.v:3263$145_Y + connect \Y $eq$ls180.v:3292$209_Y end - attribute \src "ls180.v:3403.43-3403.134" - cell $eq $eq$ls180.v:3403$162 + attribute \src "ls180.v:3432.43-3432.134" + cell $eq $eq$ls180.v:3432$226 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 @@ -248840,10 +249708,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_row connect \B \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] - connect \Y $eq$ls180.v:3403$162_Y + connect \Y $eq$ls180.v:3432$226_Y end - attribute \src "ls180.v:3420.47-3420.88" - cell $eq $eq$ls180.v:3420$175 + attribute \src "ls180.v:3449.47-3449.88" + cell $eq $eq$ls180.v:3449$239 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248851,10 +249719,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_row_close connect \B 1'0 - connect \Y $eq$ls180.v:3420$175_Y + connect \Y $eq$ls180.v:3449$239_Y end - attribute \src "ls180.v:3560.43-3560.134" - cell $eq $eq$ls180.v:3560$192 + attribute \src "ls180.v:3589.43-3589.134" + cell $eq $eq$ls180.v:3589$256 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 @@ -248862,10 +249730,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_row connect \B \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] - connect \Y $eq$ls180.v:3560$192_Y + connect \Y $eq$ls180.v:3589$256_Y end - attribute \src "ls180.v:3577.47-3577.88" - cell $eq $eq$ls180.v:3577$205 + attribute \src "ls180.v:3606.47-3606.88" + cell $eq $eq$ls180.v:3606$269 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248873,10 +249741,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_row_close connect \B 1'0 - connect \Y $eq$ls180.v:3577$205_Y + connect \Y $eq$ls180.v:3606$269_Y end - attribute \src "ls180.v:3717.43-3717.134" - cell $eq $eq$ls180.v:3717$222 + attribute \src "ls180.v:3746.43-3746.134" + cell $eq $eq$ls180.v:3746$286 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 @@ -248884,10 +249752,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_row connect \B \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] - connect \Y $eq$ls180.v:3717$222_Y + connect \Y $eq$ls180.v:3746$286_Y end - attribute \src "ls180.v:3734.47-3734.88" - cell $eq $eq$ls180.v:3734$235 + attribute \src "ls180.v:3763.47-3763.88" + cell $eq $eq$ls180.v:3763$299 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248895,10 +249763,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_row_close connect \B 1'0 - connect \Y $eq$ls180.v:3734$235_Y + connect \Y $eq$ls180.v:3763$299_Y end - attribute \src "ls180.v:3871.32-3871.56" - cell $eq $eq$ls180.v:3871$282 + attribute \src "ls180.v:3900.32-3900.56" + cell $eq $eq$ls180.v:3900$346 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -248906,10 +249774,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_time0 connect \B 1'0 - connect \Y $eq$ls180.v:3871$282_Y + connect \Y $eq$ls180.v:3900$346_Y end - attribute \src "ls180.v:3872.32-3872.56" - cell $eq $eq$ls180.v:3872$283 + attribute \src "ls180.v:3901.32-3901.56" + cell $eq $eq$ls180.v:3901$347 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -248917,10 +249785,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_time1 connect \B 1'0 - connect \Y $eq$ls180.v:3872$283_Y + connect \Y $eq$ls180.v:3901$347_Y end - attribute \src "ls180.v:3883.339-3883.418" - cell $eq $eq$ls180.v:3883$297 + attribute \src "ls180.v:3912.339-3912.418" + cell $eq $eq$ls180.v:3912$361 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248928,10 +249796,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_payload_is_read connect \B \main_sdram_choose_cmd_want_reads - connect \Y $eq$ls180.v:3883$297_Y + connect \Y $eq$ls180.v:3912$361_Y end - attribute \src "ls180.v:3883.423-3883.504" - cell $eq $eq$ls180.v:3883$298 + attribute \src "ls180.v:3912.423-3912.504" + cell $eq $eq$ls180.v:3912$362 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248939,10 +249807,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_payload_is_write connect \B \main_sdram_choose_cmd_want_writes - connect \Y $eq$ls180.v:3883$298_Y + connect \Y $eq$ls180.v:3912$362_Y end - attribute \src "ls180.v:3884.339-3884.418" - cell $eq $eq$ls180.v:3884$310 + attribute \src "ls180.v:3913.339-3913.418" + cell $eq $eq$ls180.v:3913$374 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248950,10 +249818,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_payload_is_read connect \B \main_sdram_choose_cmd_want_reads - connect \Y $eq$ls180.v:3884$310_Y + connect \Y $eq$ls180.v:3913$374_Y end - attribute \src "ls180.v:3884.423-3884.504" - cell $eq $eq$ls180.v:3884$311 + attribute \src "ls180.v:3913.423-3913.504" + cell $eq $eq$ls180.v:3913$375 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248961,10 +249829,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_payload_is_write connect \B \main_sdram_choose_cmd_want_writes - connect \Y $eq$ls180.v:3884$311_Y + connect \Y $eq$ls180.v:3913$375_Y end - attribute \src "ls180.v:3885.339-3885.418" - cell $eq $eq$ls180.v:3885$323 + attribute \src "ls180.v:3914.339-3914.418" + cell $eq $eq$ls180.v:3914$387 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248972,10 +249840,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_payload_is_read connect \B \main_sdram_choose_cmd_want_reads - connect \Y $eq$ls180.v:3885$323_Y + connect \Y $eq$ls180.v:3914$387_Y end - attribute \src "ls180.v:3885.423-3885.504" - cell $eq $eq$ls180.v:3885$324 + attribute \src "ls180.v:3914.423-3914.504" + cell $eq $eq$ls180.v:3914$388 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248983,10 +249851,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_payload_is_write connect \B \main_sdram_choose_cmd_want_writes - connect \Y $eq$ls180.v:3885$324_Y + connect \Y $eq$ls180.v:3914$388_Y end - attribute \src "ls180.v:3886.339-3886.418" - cell $eq $eq$ls180.v:3886$336 + attribute \src "ls180.v:3915.339-3915.418" + cell $eq $eq$ls180.v:3915$400 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248994,10 +249862,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_payload_is_read connect \B \main_sdram_choose_cmd_want_reads - connect \Y $eq$ls180.v:3886$336_Y + connect \Y $eq$ls180.v:3915$400_Y end - attribute \src "ls180.v:3886.423-3886.504" - cell $eq $eq$ls180.v:3886$337 + attribute \src "ls180.v:3915.423-3915.504" + cell $eq $eq$ls180.v:3915$401 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249005,10 +249873,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_payload_is_write connect \B \main_sdram_choose_cmd_want_writes - connect \Y $eq$ls180.v:3886$337_Y + connect \Y $eq$ls180.v:3915$401_Y end - attribute \src "ls180.v:3916.339-3916.418" - cell $eq $eq$ls180.v:3916$355 + attribute \src "ls180.v:3945.339-3945.418" + cell $eq $eq$ls180.v:3945$419 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249016,10 +249884,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_payload_is_read connect \B \main_sdram_choose_req_want_reads - connect \Y $eq$ls180.v:3916$355_Y + connect \Y $eq$ls180.v:3945$419_Y end - attribute \src "ls180.v:3916.423-3916.504" - cell $eq $eq$ls180.v:3916$356 + attribute \src "ls180.v:3945.423-3945.504" + cell $eq $eq$ls180.v:3945$420 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249027,10 +249895,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_payload_is_write connect \B \main_sdram_choose_req_want_writes - connect \Y $eq$ls180.v:3916$356_Y + connect \Y $eq$ls180.v:3945$420_Y end - attribute \src "ls180.v:3917.339-3917.418" - cell $eq $eq$ls180.v:3917$368 + attribute \src "ls180.v:3946.339-3946.418" + cell $eq $eq$ls180.v:3946$432 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249038,10 +249906,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_payload_is_read connect \B \main_sdram_choose_req_want_reads - connect \Y $eq$ls180.v:3917$368_Y + connect \Y $eq$ls180.v:3946$432_Y end - attribute \src "ls180.v:3917.423-3917.504" - cell $eq $eq$ls180.v:3917$369 + attribute \src "ls180.v:3946.423-3946.504" + cell $eq $eq$ls180.v:3946$433 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249049,10 +249917,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_payload_is_write connect \B \main_sdram_choose_req_want_writes - connect \Y $eq$ls180.v:3917$369_Y + connect \Y $eq$ls180.v:3946$433_Y end - attribute \src "ls180.v:3918.339-3918.418" - cell $eq $eq$ls180.v:3918$381 + attribute \src "ls180.v:3947.339-3947.418" + cell $eq $eq$ls180.v:3947$445 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249060,10 +249928,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_payload_is_read connect \B \main_sdram_choose_req_want_reads - connect \Y $eq$ls180.v:3918$381_Y + connect \Y $eq$ls180.v:3947$445_Y end - attribute \src "ls180.v:3918.423-3918.504" - cell $eq $eq$ls180.v:3918$382 + attribute \src "ls180.v:3947.423-3947.504" + cell $eq $eq$ls180.v:3947$446 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249071,10 +249939,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_payload_is_write connect \B \main_sdram_choose_req_want_writes - connect \Y $eq$ls180.v:3918$382_Y + connect \Y $eq$ls180.v:3947$446_Y end - attribute \src "ls180.v:3919.339-3919.418" - cell $eq $eq$ls180.v:3919$394 + attribute \src "ls180.v:3948.339-3948.418" + cell $eq $eq$ls180.v:3948$458 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249082,10 +249950,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_payload_is_read connect \B \main_sdram_choose_req_want_reads - connect \Y $eq$ls180.v:3919$394_Y + connect \Y $eq$ls180.v:3948$458_Y end - attribute \src "ls180.v:3919.423-3919.504" - cell $eq $eq$ls180.v:3919$395 + attribute \src "ls180.v:3948.423-3948.504" + cell $eq $eq$ls180.v:3948$459 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249093,10 +249961,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_payload_is_write connect \B \main_sdram_choose_req_want_writes - connect \Y $eq$ls180.v:3919$395_Y + connect \Y $eq$ls180.v:3948$459_Y end - attribute \src "ls180.v:3948.78-3948.113" - cell $eq $eq$ls180.v:3948$404 + attribute \src "ls180.v:3977.78-3977.113" + cell $eq $eq$ls180.v:3977$468 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -249104,10 +249972,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_cmd_grant connect \B 1'0 - connect \Y $eq$ls180.v:3948$404_Y + connect \Y $eq$ls180.v:3977$468_Y end - attribute \src "ls180.v:3951.78-3951.113" - cell $eq $eq$ls180.v:3951$407 + attribute \src "ls180.v:3980.78-3980.113" + cell $eq $eq$ls180.v:3980$471 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -249115,10 +249983,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_grant connect \B 1'0 - connect \Y $eq$ls180.v:3951$407_Y + connect \Y $eq$ls180.v:3980$471_Y end - attribute \src "ls180.v:3957.78-3957.113" - cell $eq $eq$ls180.v:3957$411 + attribute \src "ls180.v:3986.78-3986.113" + cell $eq $eq$ls180.v:3986$475 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -249126,10 +249994,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_cmd_grant connect \B 1'1 - connect \Y $eq$ls180.v:3957$411_Y + connect \Y $eq$ls180.v:3986$475_Y end - attribute \src "ls180.v:3960.78-3960.113" - cell $eq $eq$ls180.v:3960$414 + attribute \src "ls180.v:3989.78-3989.113" + cell $eq $eq$ls180.v:3989$478 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -249137,10 +250005,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_grant connect \B 1'1 - connect \Y $eq$ls180.v:3960$414_Y + connect \Y $eq$ls180.v:3989$478_Y end - attribute \src "ls180.v:3966.78-3966.113" - cell $eq $eq$ls180.v:3966$418 + attribute \src "ls180.v:3995.78-3995.113" + cell $eq $eq$ls180.v:3995$482 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -249148,10 +250016,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_cmd_grant connect \B 2'10 - connect \Y $eq$ls180.v:3966$418_Y + connect \Y $eq$ls180.v:3995$482_Y end - attribute \src "ls180.v:3969.78-3969.113" - cell $eq $eq$ls180.v:3969$421 + attribute \src "ls180.v:3998.78-3998.113" + cell $eq $eq$ls180.v:3998$485 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -249159,10 +250027,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_grant connect \B 2'10 - connect \Y $eq$ls180.v:3969$421_Y + connect \Y $eq$ls180.v:3998$485_Y end - attribute \src "ls180.v:3975.78-3975.113" - cell $eq $eq$ls180.v:3975$425 + attribute \src "ls180.v:4004.78-4004.113" + cell $eq $eq$ls180.v:4004$489 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -249170,10 +250038,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_cmd_grant connect \B 2'11 - connect \Y $eq$ls180.v:3975$425_Y + connect \Y $eq$ls180.v:4004$489_Y end - attribute \src "ls180.v:3978.78-3978.113" - cell $eq $eq$ls180.v:3978$428 + attribute \src "ls180.v:4007.78-4007.113" + cell $eq $eq$ls180.v:4007$492 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -249181,10 +250049,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_grant connect \B 2'11 - connect \Y $eq$ls180.v:3978$428_Y + connect \Y $eq$ls180.v:4007$492_Y end - attribute \src "ls180.v:4059.42-4059.82" - cell $eq $eq$ls180.v:4059$451 + attribute \src "ls180.v:4088.42-4088.82" + cell $eq $eq$ls180.v:4088$515 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -249192,10 +250060,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_addr [10:9] connect \B 1'0 - connect \Y $eq$ls180.v:4059$451_Y + connect \Y $eq$ls180.v:4088$515_Y end - attribute \src "ls180.v:4059.145-4059.178" - cell $eq $eq$ls180.v:4059$452 + attribute \src "ls180.v:4088.145-4088.178" + cell $eq $eq$ls180.v:4088$516 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249203,10 +250071,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:4059$452_Y + connect \Y $eq$ls180.v:4088$516_Y end - attribute \src "ls180.v:4059.220-4059.253" - cell $eq $eq$ls180.v:4059$455 + attribute \src "ls180.v:4088.220-4088.253" + cell $eq $eq$ls180.v:4088$519 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249214,10 +250082,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:4059$455_Y + connect \Y $eq$ls180.v:4088$519_Y end - attribute \src "ls180.v:4059.295-4059.328" - cell $eq $eq$ls180.v:4059$458 + attribute \src "ls180.v:4088.295-4088.328" + cell $eq $eq$ls180.v:4088$522 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249225,10 +250093,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:4059$458_Y + connect \Y $eq$ls180.v:4088$522_Y end - attribute \src "ls180.v:4064.42-4064.82" - cell $eq $eq$ls180.v:4064$467 + attribute \src "ls180.v:4093.42-4093.82" + cell $eq $eq$ls180.v:4093$531 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -249236,10 +250104,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_addr [10:9] connect \B 1'1 - connect \Y $eq$ls180.v:4064$467_Y + connect \Y $eq$ls180.v:4093$531_Y end - attribute \src "ls180.v:4064.145-4064.178" - cell $eq $eq$ls180.v:4064$468 + attribute \src "ls180.v:4093.145-4093.178" + cell $eq $eq$ls180.v:4093$532 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249247,10 +250115,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:4064$468_Y + connect \Y $eq$ls180.v:4093$532_Y end - attribute \src "ls180.v:4064.220-4064.253" - cell $eq $eq$ls180.v:4064$471 + attribute \src "ls180.v:4093.220-4093.253" + cell $eq $eq$ls180.v:4093$535 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249258,10 +250126,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:4064$471_Y + connect \Y $eq$ls180.v:4093$535_Y end - attribute \src "ls180.v:4064.295-4064.328" - cell $eq $eq$ls180.v:4064$474 + attribute \src "ls180.v:4093.295-4093.328" + cell $eq $eq$ls180.v:4093$538 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249269,10 +250137,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:4064$474_Y + connect \Y $eq$ls180.v:4093$538_Y end - attribute \src "ls180.v:4069.42-4069.82" - cell $eq $eq$ls180.v:4069$483 + attribute \src "ls180.v:4098.42-4098.82" + cell $eq $eq$ls180.v:4098$547 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -249280,10 +250148,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_addr [10:9] connect \B 2'10 - connect \Y $eq$ls180.v:4069$483_Y + connect \Y $eq$ls180.v:4098$547_Y end - attribute \src "ls180.v:4069.145-4069.178" - cell $eq $eq$ls180.v:4069$484 + attribute \src "ls180.v:4098.145-4098.178" + cell $eq $eq$ls180.v:4098$548 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249291,10 +250159,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:4069$484_Y + connect \Y $eq$ls180.v:4098$548_Y end - attribute \src "ls180.v:4069.220-4069.253" - cell $eq $eq$ls180.v:4069$487 + attribute \src "ls180.v:4098.220-4098.253" + cell $eq $eq$ls180.v:4098$551 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249302,10 +250170,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:4069$487_Y + connect \Y $eq$ls180.v:4098$551_Y end - attribute \src "ls180.v:4069.295-4069.328" - cell $eq $eq$ls180.v:4069$490 + attribute \src "ls180.v:4098.295-4098.328" + cell $eq $eq$ls180.v:4098$554 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249313,10 +250181,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:4069$490_Y + connect \Y $eq$ls180.v:4098$554_Y end - attribute \src "ls180.v:4074.42-4074.82" - cell $eq $eq$ls180.v:4074$499 + attribute \src "ls180.v:4103.42-4103.82" + cell $eq $eq$ls180.v:4103$563 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -249324,10 +250192,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_addr [10:9] connect \B 2'11 - connect \Y $eq$ls180.v:4074$499_Y + connect \Y $eq$ls180.v:4103$563_Y end - attribute \src "ls180.v:4074.145-4074.178" - cell $eq $eq$ls180.v:4074$500 + attribute \src "ls180.v:4103.145-4103.178" + cell $eq $eq$ls180.v:4103$564 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249335,10 +250203,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:4074$500_Y + connect \Y $eq$ls180.v:4103$564_Y end - attribute \src "ls180.v:4074.220-4074.253" - cell $eq $eq$ls180.v:4074$503 + attribute \src "ls180.v:4103.220-4103.253" + cell $eq $eq$ls180.v:4103$567 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249346,10 +250214,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:4074$503_Y + connect \Y $eq$ls180.v:4103$567_Y end - attribute \src "ls180.v:4074.295-4074.328" - cell $eq $eq$ls180.v:4074$506 + attribute \src "ls180.v:4103.295-4103.328" + cell $eq $eq$ls180.v:4103$570 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249357,10 +250225,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:4074$506_Y + connect \Y $eq$ls180.v:4103$570_Y end - attribute \src "ls180.v:4079.44-4079.77" - cell $eq $eq$ls180.v:4079$515 + attribute \src "ls180.v:4108.44-4108.77" + cell $eq $eq$ls180.v:4108$579 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249368,10 +250236,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:4079$515_Y + connect \Y $eq$ls180.v:4108$579_Y end - attribute \src "ls180.v:4079.83-4079.123" - cell $eq $eq$ls180.v:4079$516 + attribute \src "ls180.v:4108.83-4108.123" + cell $eq $eq$ls180.v:4108$580 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -249379,10 +250247,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_addr [10:9] connect \B 1'0 - connect \Y $eq$ls180.v:4079$516_Y + connect \Y $eq$ls180.v:4108$580_Y end - attribute \src "ls180.v:4079.186-4079.219" - cell $eq $eq$ls180.v:4079$517 + attribute \src "ls180.v:4108.186-4108.219" + cell $eq $eq$ls180.v:4108$581 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249390,10 +250258,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:4079$517_Y + connect \Y $eq$ls180.v:4108$581_Y end - attribute \src "ls180.v:4079.261-4079.294" - cell $eq $eq$ls180.v:4079$520 + attribute \src "ls180.v:4108.261-4108.294" + cell $eq $eq$ls180.v:4108$584 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249401,10 +250269,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:4079$520_Y + connect \Y $eq$ls180.v:4108$584_Y end - attribute \src "ls180.v:4079.336-4079.369" - cell $eq $eq$ls180.v:4079$523 + attribute \src "ls180.v:4108.336-4108.369" + cell $eq $eq$ls180.v:4108$587 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249412,10 +250280,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:4079$523_Y + connect \Y $eq$ls180.v:4108$587_Y end - attribute \src "ls180.v:4079.418-4079.451" - cell $eq $eq$ls180.v:4079$531 + attribute \src "ls180.v:4108.418-4108.451" + cell $eq $eq$ls180.v:4108$595 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249423,10 +250291,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:4079$531_Y + connect \Y $eq$ls180.v:4108$595_Y end - attribute \src "ls180.v:4079.457-4079.497" - cell $eq $eq$ls180.v:4079$532 + attribute \src "ls180.v:4108.457-4108.497" + cell $eq $eq$ls180.v:4108$596 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -249434,10 +250302,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_addr [10:9] connect \B 1'1 - connect \Y $eq$ls180.v:4079$532_Y + connect \Y $eq$ls180.v:4108$596_Y end - attribute \src "ls180.v:4079.560-4079.593" - cell $eq $eq$ls180.v:4079$533 + attribute \src "ls180.v:4108.560-4108.593" + cell $eq $eq$ls180.v:4108$597 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249445,10 +250313,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:4079$533_Y + connect \Y $eq$ls180.v:4108$597_Y end - attribute \src "ls180.v:4079.635-4079.668" - cell $eq $eq$ls180.v:4079$536 + attribute \src "ls180.v:4108.635-4108.668" + cell $eq $eq$ls180.v:4108$600 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249456,10 +250324,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:4079$536_Y + connect \Y $eq$ls180.v:4108$600_Y end - attribute \src "ls180.v:4079.710-4079.743" - cell $eq $eq$ls180.v:4079$539 + attribute \src "ls180.v:4108.710-4108.743" + cell $eq $eq$ls180.v:4108$603 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249467,10 +250335,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:4079$539_Y + connect \Y $eq$ls180.v:4108$603_Y end - attribute \src "ls180.v:4079.792-4079.825" - cell $eq $eq$ls180.v:4079$547 + attribute \src "ls180.v:4108.792-4108.825" + cell $eq $eq$ls180.v:4108$611 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249478,10 +250346,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:4079$547_Y + connect \Y $eq$ls180.v:4108$611_Y end - attribute \src "ls180.v:4079.831-4079.871" - cell $eq $eq$ls180.v:4079$548 + attribute \src "ls180.v:4108.831-4108.871" + cell $eq $eq$ls180.v:4108$612 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -249489,10 +250357,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_addr [10:9] connect \B 2'10 - connect \Y $eq$ls180.v:4079$548_Y + connect \Y $eq$ls180.v:4108$612_Y end - attribute \src "ls180.v:4079.934-4079.967" - cell $eq $eq$ls180.v:4079$549 + attribute \src "ls180.v:4108.934-4108.967" + cell $eq $eq$ls180.v:4108$613 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249500,10 +250368,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:4079$549_Y + connect \Y $eq$ls180.v:4108$613_Y end - attribute \src "ls180.v:4079.1009-4079.1042" - cell $eq $eq$ls180.v:4079$552 + attribute \src "ls180.v:4108.1009-4108.1042" + cell $eq $eq$ls180.v:4108$616 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249511,10 +250379,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:4079$552_Y + connect \Y $eq$ls180.v:4108$616_Y end - attribute \src "ls180.v:4079.1084-4079.1117" - cell $eq $eq$ls180.v:4079$555 + attribute \src "ls180.v:4108.1084-4108.1117" + cell $eq $eq$ls180.v:4108$619 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249522,10 +250390,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:4079$555_Y + connect \Y $eq$ls180.v:4108$619_Y end - attribute \src "ls180.v:4079.1166-4079.1199" - cell $eq $eq$ls180.v:4079$563 + attribute \src "ls180.v:4108.1166-4108.1199" + cell $eq $eq$ls180.v:4108$627 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249533,10 +250401,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:4079$563_Y + connect \Y $eq$ls180.v:4108$627_Y end - attribute \src "ls180.v:4079.1205-4079.1245" - cell $eq $eq$ls180.v:4079$564 + attribute \src "ls180.v:4108.1205-4108.1245" + cell $eq $eq$ls180.v:4108$628 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -249544,10 +250412,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_addr [10:9] connect \B 2'11 - connect \Y $eq$ls180.v:4079$564_Y + connect \Y $eq$ls180.v:4108$628_Y end - attribute \src "ls180.v:4079.1308-4079.1341" - cell $eq $eq$ls180.v:4079$565 + attribute \src "ls180.v:4108.1308-4108.1341" + cell $eq $eq$ls180.v:4108$629 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249555,10 +250423,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:4079$565_Y + connect \Y $eq$ls180.v:4108$629_Y end - attribute \src "ls180.v:4079.1383-4079.1416" - cell $eq $eq$ls180.v:4079$568 + attribute \src "ls180.v:4108.1383-4108.1416" + cell $eq $eq$ls180.v:4108$632 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249566,10 +250434,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:4079$568_Y + connect \Y $eq$ls180.v:4108$632_Y end - attribute \src "ls180.v:4079.1458-4079.1491" - cell $eq $eq$ls180.v:4079$571 + attribute \src "ls180.v:4108.1458-4108.1491" + cell $eq $eq$ls180.v:4108$635 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249577,10 +250445,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:4079$571_Y + connect \Y $eq$ls180.v:4108$635_Y end - attribute \src "ls180.v:4138.29-4138.57" - cell $eq $eq$ls180.v:4138$584 + attribute \src "ls180.v:4167.29-4167.57" + cell $eq $eq$ls180.v:4167$648 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -249588,10 +250456,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_litedram_wb_sel connect \B 1'0 - connect \Y $eq$ls180.v:4138$584_Y + connect \Y $eq$ls180.v:4167$648_Y end - attribute \src "ls180.v:4145.11-4145.41" - cell $eq $eq$ls180.v:4145$589 + attribute \src "ls180.v:4174.11-4174.41" + cell $eq $eq$ls180.v:4174$653 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249599,76 +250467,76 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_converter_counter connect \B 1'1 - connect \Y $eq$ls180.v:4145$589_Y + connect \Y $eq$ls180.v:4174$653_Y end - attribute \src "ls180.v:4302.37-4302.111" - cell $eq $eq$ls180.v:4302$654 + attribute \src "ls180.v:4342.37-4342.111" + cell $eq $eq$ls180.v:4342$720 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 parameter \B_WIDTH 16 parameter \Y_WIDTH 1 connect \A \main_spimaster30_clk_divider - connect \B $sub$ls180.v:4302$653_Y - connect \Y $eq$ls180.v:4302$654_Y + connect \B $sub$ls180.v:4342$719_Y + connect \Y $eq$ls180.v:4342$720_Y end - attribute \src "ls180.v:4303.37-4303.105" - cell $eq $eq$ls180.v:4303$656 + attribute \src "ls180.v:4343.37-4343.105" + cell $eq $eq$ls180.v:4343$722 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 parameter \B_WIDTH 16 parameter \Y_WIDTH 1 connect \A \main_spimaster30_clk_divider - connect \B $sub$ls180.v:4303$655_Y - connect \Y $eq$ls180.v:4303$656_Y + connect \B $sub$ls180.v:4343$721_Y + connect \Y $eq$ls180.v:4343$722_Y end - attribute \src "ls180.v:4330.10-4330.67" - cell $eq $eq$ls180.v:4330$660 + attribute \src "ls180.v:4370.10-4370.67" + cell $eq $eq$ls180.v:4370$726 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \main_spimaster27_count - connect \B $sub$ls180.v:4330$659_Y - connect \Y $eq$ls180.v:4330$660_Y + connect \B $sub$ls180.v:4370$725_Y + connect \Y $eq$ls180.v:4370$726_Y end - attribute \src "ls180.v:4360.35-4360.108" - cell $eq $eq$ls180.v:4360$662 + attribute \src "ls180.v:4400.35-4400.108" + cell $eq $eq$ls180.v:4400$728 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 parameter \B_WIDTH 16 parameter \Y_WIDTH 1 connect \A \main_spisdcard_clk_divider1 - connect \B $sub$ls180.v:4360$661_Y - connect \Y $eq$ls180.v:4360$662_Y + connect \B $sub$ls180.v:4400$727_Y + connect \Y $eq$ls180.v:4400$728_Y end - attribute \src "ls180.v:4361.35-4361.102" - cell $eq $eq$ls180.v:4361$664 + attribute \src "ls180.v:4401.35-4401.102" + cell $eq $eq$ls180.v:4401$730 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 parameter \B_WIDTH 16 parameter \Y_WIDTH 1 connect \A \main_spisdcard_clk_divider1 - connect \B $sub$ls180.v:4361$663_Y - connect \Y $eq$ls180.v:4361$664_Y + connect \B $sub$ls180.v:4401$729_Y + connect \Y $eq$ls180.v:4401$730_Y end - attribute \src "ls180.v:4389.10-4389.65" - cell $eq $eq$ls180.v:4389$668 + attribute \src "ls180.v:4429.10-4429.65" + cell $eq $eq$ls180.v:4429$734 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \main_spisdcard_count - connect \B $sub$ls180.v:4389$667_Y - connect \Y $eq$ls180.v:4389$668_Y + connect \B $sub$ls180.v:4429$733_Y + connect \Y $eq$ls180.v:4429$734_Y end - attribute \src "ls180.v:4493.10-4493.40" - cell $eq $eq$ls180.v:4493$695 + attribute \src "ls180.v:4533.10-4533.40" + cell $eq $eq$ls180.v:4533$761 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -249676,10 +250544,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_init_count connect \B 7'1001111 - connect \Y $eq$ls180.v:4493$695_Y + connect \Y $eq$ls180.v:4533$761_Y end - attribute \src "ls180.v:4550.10-4550.39" - cell $eq $eq$ls180.v:4550$698 + attribute \src "ls180.v:4590.10-4590.39" + cell $eq $eq$ls180.v:4590$764 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -249687,10 +250555,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdw_count connect \B 3'111 - connect \Y $eq$ls180.v:4550$698_Y + connect \Y $eq$ls180.v:4590$764_Y end - attribute \src "ls180.v:4567.10-4567.39" - cell $eq $eq$ls180.v:4567$700 + attribute \src "ls180.v:4607.10-4607.39" + cell $eq $eq$ls180.v:4607$766 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -249698,10 +250566,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdw_count connect \B 3'111 - connect \Y $eq$ls180.v:4567$700_Y + connect \Y $eq$ls180.v:4607$766_Y end - attribute \src "ls180.v:4595.38-4595.88" - cell $eq $eq$ls180.v:4595$702 + attribute \src "ls180.v:4635.38-4635.88" + cell $eq $eq$ls180.v:4635$768 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249709,10 +250577,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_i connect \B 1'0 - connect \Y $eq$ls180.v:4595$702_Y + connect \Y $eq$ls180.v:4635$768_Y end - attribute \src "ls180.v:4645.9-4645.40" - cell $eq $eq$ls180.v:4645$712 + attribute \src "ls180.v:4685.9-4685.40" + cell $eq $eq$ls180.v:4685$778 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -249720,21 +250588,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_timeout connect \B 1'0 - connect \Y $eq$ls180.v:4645$712_Y + connect \Y $eq$ls180.v:4685$778_Y end - attribute \src "ls180.v:4654.36-4654.105" - cell $eq $eq$ls180.v:4654$714 + attribute \src "ls180.v:4694.36-4694.105" + cell $eq $eq$ls180.v:4694$780 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_count - connect \B $sub$ls180.v:4654$713_Y - connect \Y $eq$ls180.v:4654$714_Y + connect \B $sub$ls180.v:4694$779_Y + connect \Y $eq$ls180.v:4694$780_Y end - attribute \src "ls180.v:4673.9-4673.40" - cell $eq $eq$ls180.v:4673$718 + attribute \src "ls180.v:4713.9-4713.40" + cell $eq $eq$ls180.v:4713$784 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -249742,10 +250610,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_timeout connect \B 1'0 - connect \Y $eq$ls180.v:4673$718_Y + connect \Y $eq$ls180.v:4713$784_Y end - attribute \src "ls180.v:4685.10-4685.39" - cell $eq $eq$ls180.v:4685$720 + attribute \src "ls180.v:4725.10-4725.39" + cell $eq $eq$ls180.v:4725$786 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -249753,10 +250621,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_count connect \B 3'111 - connect \Y $eq$ls180.v:4685$720_Y + connect \Y $eq$ls180.v:4725$786_Y end - attribute \src "ls180.v:4722.39-4722.94" - cell $eq $eq$ls180.v:4722$724 + attribute \src "ls180.v:4762.39-4762.94" + cell $eq $eq$ls180.v:4762$790 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249764,10 +250632,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_pads_in_payload_data_i [0] connect \B 1'0 - connect \Y $eq$ls180.v:4722$724_Y + connect \Y $eq$ls180.v:4762$790_Y end - attribute \src "ls180.v:4759.32-4759.89" - cell $eq $eq$ls180.v:4759$733 + attribute \src "ls180.v:4799.32-4799.89" + cell $eq $eq$ls180.v:4799$799 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -249775,10 +250643,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_source_source_payload_data0 connect \B 3'101 - connect \Y $eq$ls180.v:4759$733_Y + connect \Y $eq$ls180.v:4799$799_Y end - attribute \src "ls180.v:4807.10-4807.40" - cell $eq $eq$ls180.v:4807$737 + attribute \src "ls180.v:4847.10-4847.40" + cell $eq $eq$ls180.v:4847$803 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -249786,10 +250654,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_count connect \B 1'1 - connect \Y $eq$ls180.v:4807$737_Y + connect \Y $eq$ls180.v:4847$803_Y end - attribute \src "ls180.v:4856.40-4856.98" - cell $eq $eq$ls180.v:4856$739 + attribute \src "ls180.v:4896.40-4896.98" + cell $eq $eq$ls180.v:4896$805 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -249797,10 +250665,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_pads_in_payload_data_i connect \B 1'0 - connect \Y $eq$ls180.v:4856$739_Y + connect \Y $eq$ls180.v:4896$805_Y end - attribute \src "ls180.v:4907.9-4907.41" - cell $eq $eq$ls180.v:4907$749 + attribute \src "ls180.v:4947.9-4947.41" + cell $eq $eq$ls180.v:4947$815 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -249808,21 +250676,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_timeout connect \B 1'0 - connect \Y $eq$ls180.v:4907$749_Y + connect \Y $eq$ls180.v:4947$815_Y end - attribute \src "ls180.v:4916.37-4916.123" - cell $eq $eq$ls180.v:4916$752 + attribute \src "ls180.v:4956.37-4956.123" + cell $eq $eq$ls180.v:4956$818 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 parameter \B_WIDTH 10 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_count - connect \B $sub$ls180.v:4916$751_Y - connect \Y $eq$ls180.v:4916$752_Y + connect \B $sub$ls180.v:4956$817_Y + connect \Y $eq$ls180.v:4956$818_Y end - attribute \src "ls180.v:4939.9-4939.41" - cell $eq $eq$ls180.v:4939$755 + attribute \src "ls180.v:4979.9-4979.41" + cell $eq $eq$ls180.v:4979$821 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -249830,10 +250698,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_timeout connect \B 1'0 - connect \Y $eq$ls180.v:4939$755_Y + connect \Y $eq$ls180.v:4979$821_Y end - attribute \src "ls180.v:4949.10-4949.41" - cell $eq $eq$ls180.v:4949$757 + attribute \src "ls180.v:4989.10-4989.41" + cell $eq $eq$ls180.v:4989$823 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -249841,10 +250709,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_count connect \B 6'100111 - connect \Y $eq$ls180.v:4949$757_Y + connect \Y $eq$ls180.v:4989$823_Y end - attribute \src "ls180.v:5118.9-5118.47" - cell $eq $eq$ls180.v:5118$939 + attribute \src "ls180.v:5158.9-5158.47" + cell $eq $eq$ls180.v:5158$1005 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -249852,10 +250720,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_cnt connect \B 3'111 - connect \Y $eq$ls180.v:5118$939_Y + connect \Y $eq$ls180.v:5158$1005_Y end - attribute \src "ls180.v:5148.10-5148.48" - cell $eq $eq$ls180.v:5148$940 + attribute \src "ls180.v:5188.10-5188.48" + cell $eq $eq$ls180.v:5188$1006 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -249863,10 +250731,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_cnt connect \B 3'111 - connect \Y $eq$ls180.v:5148$940_Y + connect \Y $eq$ls180.v:5188$1006_Y end - attribute \src "ls180.v:5179.10-5179.78" - cell $eq $eq$ls180.v:5179$945 + attribute \src "ls180.v:5219.10-5219.78" + cell $eq $eq$ls180.v:5219$1011 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -249874,10 +250742,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_fifo0 connect \B \main_sdcore_crc16_checker_crctmp0 - connect \Y $eq$ls180.v:5179$945_Y + connect \Y $eq$ls180.v:5219$1011_Y end - attribute \src "ls180.v:5179.83-5179.151" - cell $eq $eq$ls180.v:5179$946 + attribute \src "ls180.v:5219.83-5219.151" + cell $eq $eq$ls180.v:5219$1012 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -249885,10 +250753,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_fifo1 connect \B \main_sdcore_crc16_checker_crctmp1 - connect \Y $eq$ls180.v:5179$946_Y + connect \Y $eq$ls180.v:5219$1012_Y end - attribute \src "ls180.v:5179.157-5179.225" - cell $eq $eq$ls180.v:5179$948 + attribute \src "ls180.v:5219.157-5219.225" + cell $eq $eq$ls180.v:5219$1014 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -249896,10 +250764,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_fifo2 connect \B \main_sdcore_crc16_checker_crctmp2 - connect \Y $eq$ls180.v:5179$948_Y + connect \Y $eq$ls180.v:5219$1014_Y end - attribute \src "ls180.v:5179.231-5179.299" - cell $eq $eq$ls180.v:5179$950 + attribute \src "ls180.v:5219.231-5219.299" + cell $eq $eq$ls180.v:5219$1016 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -249907,10 +250775,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_fifo3 connect \B \main_sdcore_crc16_checker_crctmp3 - connect \Y $eq$ls180.v:5179$950_Y + connect \Y $eq$ls180.v:5219$1016_Y end - attribute \src "ls180.v:5187.7-5187.44" - cell $eq $eq$ls180.v:5187$954 + attribute \src "ls180.v:5227.7-5227.44" + cell $eq $eq$ls180.v:5227$1020 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -249918,10 +250786,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_cnt connect \B 3'111 - connect \Y $eq$ls180.v:5187$954_Y + connect \Y $eq$ls180.v:5227$1020_Y end - attribute \src "ls180.v:5197.7-5197.44" - cell $eq $eq$ls180.v:5197$957 + attribute \src "ls180.v:5237.7-5237.44" + cell $eq $eq$ls180.v:5237$1023 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -249929,10 +250797,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_cnt connect \B 3'111 - connect \Y $eq$ls180.v:5197$957_Y + connect \Y $eq$ls180.v:5237$1023_Y end - attribute \src "ls180.v:5207.7-5207.44" - cell $eq $eq$ls180.v:5207$960 + attribute \src "ls180.v:5247.7-5247.44" + cell $eq $eq$ls180.v:5247$1026 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -249940,10 +250808,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_cnt connect \B 3'111 - connect \Y $eq$ls180.v:5207$960_Y + connect \Y $eq$ls180.v:5247$1026_Y end - attribute \src "ls180.v:5217.7-5217.44" - cell $eq $eq$ls180.v:5217$963 + attribute \src "ls180.v:5257.7-5257.44" + cell $eq $eq$ls180.v:5257$1029 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -249951,10 +250819,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_cnt connect \B 3'111 - connect \Y $eq$ls180.v:5217$963_Y + connect \Y $eq$ls180.v:5257$1029_Y end - attribute \src "ls180.v:5341.36-5341.64" - cell $eq $eq$ls180.v:5341$1014 + attribute \src "ls180.v:5381.36-5381.64" + cell $eq $eq$ls180.v:5381$1080 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -249962,10 +250830,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_cmd_type connect \B 1'0 - connect \Y $eq$ls180.v:5341$1014_Y + connect \Y $eq$ls180.v:5381$1080_Y end - attribute \src "ls180.v:5347.10-5347.39" - cell $eq $eq$ls180.v:5347$1017 + attribute \src "ls180.v:5387.10-5387.39" + cell $eq $eq$ls180.v:5387$1083 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -249973,10 +250841,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_cmd_count connect \B 3'101 - connect \Y $eq$ls180.v:5347$1017_Y + connect \Y $eq$ls180.v:5387$1083_Y end - attribute \src "ls180.v:5348.11-5348.39" - cell $eq $eq$ls180.v:5348$1018 + attribute \src "ls180.v:5388.11-5388.39" + cell $eq $eq$ls180.v:5388$1084 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -249984,10 +250852,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_cmd_type connect \B 1'0 - connect \Y $eq$ls180.v:5348$1018_Y + connect \Y $eq$ls180.v:5388$1084_Y end - attribute \src "ls180.v:5360.34-5360.63" - cell $eq $eq$ls180.v:5360$1019 + attribute \src "ls180.v:5400.34-5400.63" + cell $eq $eq$ls180.v:5400$1085 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -249995,10 +250863,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_data_type connect \B 1'0 - connect \Y $eq$ls180.v:5360$1019_Y + connect \Y $eq$ls180.v:5400$1085_Y end - attribute \src "ls180.v:5361.9-5361.37" - cell $eq $eq$ls180.v:5361$1020 + attribute \src "ls180.v:5401.9-5401.37" + cell $eq $eq$ls180.v:5401$1086 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -250006,10 +250874,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_cmd_type connect \B 2'10 - connect \Y $eq$ls180.v:5361$1020_Y + connect \Y $eq$ls180.v:5401$1086_Y end - attribute \src "ls180.v:5368.10-5368.55" - cell $eq $eq$ls180.v:5368$1021 + attribute \src "ls180.v:5408.10-5408.55" + cell $eq $eq$ls180.v:5408$1087 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -250017,10 +250885,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_source_payload_status connect \B 1'1 - connect \Y $eq$ls180.v:5368$1021_Y + connect \Y $eq$ls180.v:5408$1087_Y end - attribute \src "ls180.v:5374.12-5374.41" - cell $eq $eq$ls180.v:5374$1022 + attribute \src "ls180.v:5414.12-5414.41" + cell $eq $eq$ls180.v:5414$1088 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -250028,10 +250896,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_data_type connect \B 2'10 - connect \Y $eq$ls180.v:5374$1022_Y + connect \Y $eq$ls180.v:5414$1088_Y end - attribute \src "ls180.v:5377.13-5377.42" - cell $eq $eq$ls180.v:5377$1023 + attribute \src "ls180.v:5417.13-5417.42" + cell $eq $eq$ls180.v:5417$1089 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -250039,32 +250907,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_data_type connect \B 1'1 - connect \Y $eq$ls180.v:5377$1023_Y + connect \Y $eq$ls180.v:5417$1089_Y end - attribute \src "ls180.v:5399.10-5399.76" - cell $eq $eq$ls180.v:5399$1028 + attribute \src "ls180.v:5439.10-5439.76" + cell $eq $eq$ls180.v:5439$1094 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 1 connect \A \main_sdcore_data_count - connect \B $sub$ls180.v:5399$1027_Y - connect \Y $eq$ls180.v:5399$1028_Y + connect \B $sub$ls180.v:5439$1093_Y + connect \Y $eq$ls180.v:5439$1094_Y end - attribute \src "ls180.v:5414.35-5414.101" - cell $eq $eq$ls180.v:5414$1031 + attribute \src "ls180.v:5454.35-5454.101" + cell $eq $eq$ls180.v:5454$1097 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 1 connect \A \main_sdcore_data_count - connect \B $sub$ls180.v:5414$1030_Y - connect \Y $eq$ls180.v:5414$1031_Y + connect \B $sub$ls180.v:5454$1096_Y + connect \Y $eq$ls180.v:5454$1097_Y end - attribute \src "ls180.v:5416.10-5416.56" - cell $eq $eq$ls180.v:5416$1032 + attribute \src "ls180.v:5456.10-5456.56" + cell $eq $eq$ls180.v:5456$1098 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -250072,21 +250940,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_source_payload_status connect \B 1'0 - connect \Y $eq$ls180.v:5416$1032_Y + connect \Y $eq$ls180.v:5456$1098_Y end - attribute \src "ls180.v:5425.12-5425.78" - cell $eq $eq$ls180.v:5425$1036 + attribute \src "ls180.v:5465.12-5465.78" + cell $eq $eq$ls180.v:5465$1102 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 1 connect \A \main_sdcore_data_count - connect \B $sub$ls180.v:5425$1035_Y - connect \Y $eq$ls180.v:5425$1036_Y + connect \B $sub$ls180.v:5465$1101_Y + connect \Y $eq$ls180.v:5465$1102_Y end - attribute \src "ls180.v:5432.11-5432.57" - cell $eq $eq$ls180.v:5432$1037 + attribute \src "ls180.v:5472.11-5472.57" + cell $eq $eq$ls180.v:5472$1103 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -250094,54 +250962,54 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_source_payload_status connect \B 1'1 - connect \Y $eq$ls180.v:5432$1037_Y + connect \Y $eq$ls180.v:5472$1103_Y end - attribute \src "ls180.v:5549.10-5549.105" - cell $eq $eq$ls180.v:5549$1054 + attribute \src "ls180.v:5589.10-5589.105" + cell $eq $eq$ls180.v:5589$1120 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_wishbonedmawriter_offset - connect \B $sub$ls180.v:5549$1053_Y - connect \Y $eq$ls180.v:5549$1054_Y + connect \B $sub$ls180.v:5589$1119_Y + connect \Y $eq$ls180.v:5589$1120_Y end - attribute \src "ls180.v:5639.39-5639.106" - cell $eq $eq$ls180.v:5639$1060 + attribute \src "ls180.v:5679.39-5679.106" + cell $eq $eq$ls180.v:5679$1126 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_dma_offset - connect \B $sub$ls180.v:5639$1059_Y - connect \Y $eq$ls180.v:5639$1060_Y + connect \B $sub$ls180.v:5679$1125_Y + connect \Y $eq$ls180.v:5679$1126_Y end - attribute \src "ls180.v:5669.44-5669.82" - cell $eq $eq$ls180.v:5669$1063 + attribute \src "ls180.v:5709.44-5709.82" + cell $eq $eq$ls180.v:5709$1129 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_converter_mux connect \B 1'0 - connect \Y $eq$ls180.v:5669$1063_Y + connect \Y $eq$ls180.v:5709$1129_Y end - attribute \src "ls180.v:5670.43-5670.81" - cell $eq $eq$ls180.v:5670$1064 + attribute \src "ls180.v:5710.43-5710.81" + cell $eq $eq$ls180.v:5710$1130 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 - parameter \B_WIDTH 2 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_converter_mux - connect \B 2'11 - connect \Y $eq$ls180.v:5670$1064_Y + connect \B 3'111 + connect \Y $eq$ls180.v:5710$1130_Y end - attribute \src "ls180.v:5770.85-5770.106" - cell $eq $eq$ls180.v:5770$1080 + attribute \src "ls180.v:5822.68-5822.89" + cell $eq $eq$ls180.v:5822$1146 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -250149,10 +251017,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_grant connect \B 1'0 - connect \Y $eq$ls180.v:5770$1080_Y + connect \Y $eq$ls180.v:5822$1146_Y end - attribute \src "ls180.v:5771.85-5771.106" - cell $eq $eq$ls180.v:5771$1082 + attribute \src "ls180.v:5823.68-5823.89" + cell $eq $eq$ls180.v:5823$1148 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -250160,10 +251028,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_grant connect \B 1'1 - connect \Y $eq$ls180.v:5771$1082_Y + connect \Y $eq$ls180.v:5823$1148_Y end - attribute \src "ls180.v:5772.85-5772.106" - cell $eq $eq$ls180.v:5772$1084 + attribute \src "ls180.v:5824.71-5824.92" + cell $eq $eq$ls180.v:5824$1150 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -250171,10 +251039,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_grant connect \B 2'10 - connect \Y $eq$ls180.v:5772$1084_Y + connect \Y $eq$ls180.v:5824$1150_Y end - attribute \src "ls180.v:5773.57-5773.78" - cell $eq $eq$ls180.v:5773$1086 + attribute \src "ls180.v:5825.57-5825.78" + cell $eq $eq$ls180.v:5825$1152 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -250182,10 +251050,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_grant connect \B 2'11 - connect \Y $eq$ls180.v:5773$1086_Y + connect \Y $eq$ls180.v:5825$1152_Y end - attribute \src "ls180.v:5774.57-5774.78" - cell $eq $eq$ls180.v:5774$1088 + attribute \src "ls180.v:5826.57-5826.78" + cell $eq $eq$ls180.v:5826$1154 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -250193,10 +251061,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_grant connect \B 3'100 - connect \Y $eq$ls180.v:5774$1088_Y + connect \Y $eq$ls180.v:5826$1154_Y end - attribute \src "ls180.v:5775.85-5775.106" - cell $eq $eq$ls180.v:5775$1090 + attribute \src "ls180.v:5827.68-5827.89" + cell $eq $eq$ls180.v:5827$1156 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -250204,10 +251072,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_grant connect \B 1'0 - connect \Y $eq$ls180.v:5775$1090_Y + connect \Y $eq$ls180.v:5827$1156_Y end - attribute \src "ls180.v:5776.85-5776.106" - cell $eq $eq$ls180.v:5776$1092 + attribute \src "ls180.v:5828.68-5828.89" + cell $eq $eq$ls180.v:5828$1158 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -250215,10 +251083,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_grant connect \B 1'1 - connect \Y $eq$ls180.v:5776$1092_Y + connect \Y $eq$ls180.v:5828$1158_Y end - attribute \src "ls180.v:5777.85-5777.106" - cell $eq $eq$ls180.v:5777$1094 + attribute \src "ls180.v:5829.71-5829.92" + cell $eq $eq$ls180.v:5829$1160 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -250226,10 +251094,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_grant connect \B 2'10 - connect \Y $eq$ls180.v:5777$1094_Y + connect \Y $eq$ls180.v:5829$1160_Y end - attribute \src "ls180.v:5778.57-5778.78" - cell $eq $eq$ls180.v:5778$1096 + attribute \src "ls180.v:5830.57-5830.78" + cell $eq $eq$ls180.v:5830$1162 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -250237,10 +251105,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_grant connect \B 2'11 - connect \Y $eq$ls180.v:5778$1096_Y + connect \Y $eq$ls180.v:5830$1162_Y end - attribute \src "ls180.v:5779.57-5779.78" - cell $eq $eq$ls180.v:5779$1098 + attribute \src "ls180.v:5831.57-5831.78" + cell $eq $eq$ls180.v:5831$1164 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -250248,98 +251116,98 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_grant connect \B 3'100 - connect \Y $eq$ls180.v:5779$1098_Y + connect \Y $eq$ls180.v:5831$1164_Y end - attribute \src "ls180.v:5783.27-5783.59" - cell $eq $eq$ls180.v:5783$1101 + attribute \src "ls180.v:5835.27-5835.59" + cell $eq $eq$ls180.v:5835$1167 parameter \A_SIGNED 0 - parameter \A_WIDTH 23 + parameter \A_WIDTH 24 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_shared_adr [29:7] + connect \A \builder_shared_adr [29:6] connect \B 1'0 - connect \Y $eq$ls180.v:5783$1101_Y + connect \Y $eq$ls180.v:5835$1167_Y end - attribute \src "ls180.v:5784.27-5784.59" - cell $eq $eq$ls180.v:5784$1102 + attribute \src "ls180.v:5836.27-5836.59" + cell $eq $eq$ls180.v:5836$1168 parameter \A_SIGNED 0 - parameter \A_WIDTH 23 + parameter \A_WIDTH 24 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_shared_adr [29:7] + connect \A \builder_shared_adr [29:6] connect \B 4'1000 - connect \Y $eq$ls180.v:5784$1102_Y + connect \Y $eq$ls180.v:5836$1168_Y end - attribute \src "ls180.v:5785.27-5785.60" - cell $eq $eq$ls180.v:5785$1103 + attribute \src "ls180.v:5837.27-5837.60" + cell $eq $eq$ls180.v:5837$1169 parameter \A_SIGNED 0 - parameter \A_WIDTH 23 + parameter \A_WIDTH 24 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 - connect \A \builder_shared_adr [29:7] + connect \A \builder_shared_adr [29:6] connect \B 5'10000 - connect \Y $eq$ls180.v:5785$1103_Y + connect \Y $eq$ls180.v:5837$1169_Y end - attribute \src "ls180.v:5786.27-5786.60" - cell $eq $eq$ls180.v:5786$1104 + attribute \src "ls180.v:5838.27-5838.60" + cell $eq $eq$ls180.v:5838$1170 parameter \A_SIGNED 0 - parameter \A_WIDTH 23 + parameter \A_WIDTH 24 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 - connect \A \builder_shared_adr [29:7] + connect \A \builder_shared_adr [29:6] connect \B 5'11000 - connect \Y $eq$ls180.v:5786$1104_Y + connect \Y $eq$ls180.v:5838$1170_Y end - attribute \src "ls180.v:5787.27-5787.68" - cell $eq $eq$ls180.v:5787$1105 + attribute \src "ls180.v:5839.27-5839.68" + cell $eq $eq$ls180.v:5839$1171 parameter \A_SIGNED 0 - parameter \A_WIDTH 27 + parameter \A_WIDTH 28 parameter \B_SIGNED 0 parameter \B_WIDTH 27 parameter \Y_WIDTH 1 - connect \A \builder_shared_adr [29:3] + connect \A \builder_shared_adr [29:2] connect \B 27'110000000000000100000000000 - connect \Y $eq$ls180.v:5787$1105_Y + connect \Y $eq$ls180.v:5839$1171_Y end - attribute \src "ls180.v:5788.27-5788.66" - cell $eq $eq$ls180.v:5788$1106 + attribute \src "ls180.v:5840.27-5840.65" + cell $eq $eq$ls180.v:5840$1172 parameter \A_SIGNED 0 - parameter \A_WIDTH 20 + parameter \A_WIDTH 21 parameter \B_SIGNED 0 parameter \B_WIDTH 20 parameter \Y_WIDTH 1 - connect \A \builder_shared_adr [29:10] + connect \A \builder_shared_adr [29:9] connect \B 20'11000000000000010001 - connect \Y $eq$ls180.v:5788$1106_Y + connect \Y $eq$ls180.v:5840$1172_Y end - attribute \src "ls180.v:5789.27-5789.61" - cell $eq $eq$ls180.v:5789$1107 + attribute \src "ls180.v:5841.27-5841.61" + cell $eq $eq$ls180.v:5841$1173 parameter \A_SIGNED 0 - parameter \A_WIDTH 7 + parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 - connect \A \builder_shared_adr [29:23] + connect \A \builder_shared_adr [29:22] connect \B 7'1001000 - connect \Y $eq$ls180.v:5789$1107_Y + connect \Y $eq$ls180.v:5841$1173_Y end - attribute \src "ls180.v:5790.27-5790.65" - cell $eq $eq$ls180.v:5790$1108 + attribute \src "ls180.v:5842.27-5842.65" + cell $eq $eq$ls180.v:5842$1174 parameter \A_SIGNED 0 - parameter \A_WIDTH 16 + parameter \A_WIDTH 17 parameter \B_SIGNED 0 parameter \B_WIDTH 16 parameter \Y_WIDTH 1 - connect \A \builder_shared_adr [29:14] + connect \A \builder_shared_adr [29:13] connect \B 16'1100000000000000 - connect \Y $eq$ls180.v:5790$1108_Y + connect \Y $eq$ls180.v:5842$1174_Y end - attribute \src "ls180.v:5870.24-5870.45" - cell $eq $eq$ls180.v:5870$1150 + attribute \src "ls180.v:5922.24-5922.45" + cell $eq $eq$ls180.v:5922$1216 parameter \A_SIGNED 0 parameter \A_WIDTH 20 parameter \B_SIGNED 0 @@ -250347,21 +251215,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_count connect \B 1'0 - connect \Y $eq$ls180.v:5870$1150_Y + connect \Y $eq$ls180.v:5922$1216_Y end - attribute \src "ls180.v:5871.32-5871.77" - cell $eq $eq$ls180.v:5871$1151 + attribute \src "ls180.v:5923.32-5923.77" + cell $eq $eq$ls180.v:5923$1217 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [13:9] + connect \A \builder_interface0_bank_bus_adr [13:8] connect \B 1'0 - connect \Y $eq$ls180.v:5871$1151_Y + connect \Y $eq$ls180.v:5923$1217_Y end - attribute \src "ls180.v:5873.97-5873.141" - cell $eq $eq$ls180.v:5873$1153 + attribute \src "ls180.v:5925.97-5925.141" + cell $eq $eq$ls180.v:5925$1219 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250369,10 +251237,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:5873$1153_Y + connect \Y $eq$ls180.v:5925$1219_Y end - attribute \src "ls180.v:5874.100-5874.144" - cell $eq $eq$ls180.v:5874$1157 + attribute \src "ls180.v:5926.100-5926.144" + cell $eq $eq$ls180.v:5926$1223 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250380,10 +251248,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:5874$1157_Y + connect \Y $eq$ls180.v:5926$1223_Y end - attribute \src "ls180.v:5876.99-5876.143" - cell $eq $eq$ls180.v:5876$1160 + attribute \src "ls180.v:5928.99-5928.143" + cell $eq $eq$ls180.v:5928$1226 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250391,10 +251259,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:5876$1160_Y + connect \Y $eq$ls180.v:5928$1226_Y end - attribute \src "ls180.v:5877.102-5877.146" - cell $eq $eq$ls180.v:5877$1164 + attribute \src "ls180.v:5929.102-5929.146" + cell $eq $eq$ls180.v:5929$1230 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250402,10 +251270,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:5877$1164_Y + connect \Y $eq$ls180.v:5929$1230_Y end - attribute \src "ls180.v:5879.99-5879.143" - cell $eq $eq$ls180.v:5879$1167 + attribute \src "ls180.v:5931.99-5931.143" + cell $eq $eq$ls180.v:5931$1233 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250413,10 +251281,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:5879$1167_Y + connect \Y $eq$ls180.v:5931$1233_Y end - attribute \src "ls180.v:5880.102-5880.146" - cell $eq $eq$ls180.v:5880$1171 + attribute \src "ls180.v:5932.102-5932.146" + cell $eq $eq$ls180.v:5932$1237 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250424,10 +251292,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:5880$1171_Y + connect \Y $eq$ls180.v:5932$1237_Y end - attribute \src "ls180.v:5882.99-5882.143" - cell $eq $eq$ls180.v:5882$1174 + attribute \src "ls180.v:5934.99-5934.143" + cell $eq $eq$ls180.v:5934$1240 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250435,10 +251303,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:5882$1174_Y + connect \Y $eq$ls180.v:5934$1240_Y end - attribute \src "ls180.v:5883.102-5883.146" - cell $eq $eq$ls180.v:5883$1178 + attribute \src "ls180.v:5935.102-5935.146" + cell $eq $eq$ls180.v:5935$1244 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250446,10 +251314,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:5883$1178_Y + connect \Y $eq$ls180.v:5935$1244_Y end - attribute \src "ls180.v:5885.99-5885.143" - cell $eq $eq$ls180.v:5885$1181 + attribute \src "ls180.v:5937.99-5937.143" + cell $eq $eq$ls180.v:5937$1247 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250457,10 +251325,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:5885$1181_Y + connect \Y $eq$ls180.v:5937$1247_Y end - attribute \src "ls180.v:5886.102-5886.146" - cell $eq $eq$ls180.v:5886$1185 + attribute \src "ls180.v:5938.102-5938.146" + cell $eq $eq$ls180.v:5938$1251 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250468,10 +251336,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:5886$1185_Y + connect \Y $eq$ls180.v:5938$1251_Y end - attribute \src "ls180.v:5888.102-5888.146" - cell $eq $eq$ls180.v:5888$1188 + attribute \src "ls180.v:5940.102-5940.146" + cell $eq $eq$ls180.v:5940$1254 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250479,10 +251347,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:5888$1188_Y + connect \Y $eq$ls180.v:5940$1254_Y end - attribute \src "ls180.v:5889.105-5889.149" - cell $eq $eq$ls180.v:5889$1192 + attribute \src "ls180.v:5941.105-5941.149" + cell $eq $eq$ls180.v:5941$1258 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250490,10 +251358,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:5889$1192_Y + connect \Y $eq$ls180.v:5941$1258_Y end - attribute \src "ls180.v:5891.102-5891.146" - cell $eq $eq$ls180.v:5891$1195 + attribute \src "ls180.v:5943.102-5943.146" + cell $eq $eq$ls180.v:5943$1261 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250501,10 +251369,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:5891$1195_Y + connect \Y $eq$ls180.v:5943$1261_Y end - attribute \src "ls180.v:5892.105-5892.149" - cell $eq $eq$ls180.v:5892$1199 + attribute \src "ls180.v:5944.105-5944.149" + cell $eq $eq$ls180.v:5944$1265 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250512,10 +251380,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:5892$1199_Y + connect \Y $eq$ls180.v:5944$1265_Y end - attribute \src "ls180.v:5894.102-5894.146" - cell $eq $eq$ls180.v:5894$1202 + attribute \src "ls180.v:5946.102-5946.146" + cell $eq $eq$ls180.v:5946$1268 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250523,10 +251391,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:5894$1202_Y + connect \Y $eq$ls180.v:5946$1268_Y end - attribute \src "ls180.v:5895.105-5895.149" - cell $eq $eq$ls180.v:5895$1206 + attribute \src "ls180.v:5947.105-5947.149" + cell $eq $eq$ls180.v:5947$1272 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250534,10 +251402,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:5895$1206_Y + connect \Y $eq$ls180.v:5947$1272_Y end - attribute \src "ls180.v:5897.102-5897.146" - cell $eq $eq$ls180.v:5897$1209 + attribute \src "ls180.v:5949.102-5949.146" + cell $eq $eq$ls180.v:5949$1275 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250545,10 +251413,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:5897$1209_Y + connect \Y $eq$ls180.v:5949$1275_Y end - attribute \src "ls180.v:5898.105-5898.149" - cell $eq $eq$ls180.v:5898$1213 + attribute \src "ls180.v:5950.105-5950.149" + cell $eq $eq$ls180.v:5950$1279 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250556,21 +251424,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:5898$1213_Y + connect \Y $eq$ls180.v:5950$1279_Y end - attribute \src "ls180.v:5909.32-5909.77" - cell $eq $eq$ls180.v:5909$1215 + attribute \src "ls180.v:5961.32-5961.77" + cell $eq $eq$ls180.v:5961$1281 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_adr [13:9] + connect \A \builder_interface1_bank_bus_adr [13:8] connect \B 3'110 - connect \Y $eq$ls180.v:5909$1215_Y + connect \Y $eq$ls180.v:5961$1281_Y end - attribute \src "ls180.v:5911.94-5911.138" - cell $eq $eq$ls180.v:5911$1217 + attribute \src "ls180.v:5963.94-5963.138" + cell $eq $eq$ls180.v:5963$1283 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -250578,10 +251446,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [2:0] connect \B 1'0 - connect \Y $eq$ls180.v:5911$1217_Y + connect \Y $eq$ls180.v:5963$1283_Y end - attribute \src "ls180.v:5912.97-5912.141" - cell $eq $eq$ls180.v:5912$1221 + attribute \src "ls180.v:5964.97-5964.141" + cell $eq $eq$ls180.v:5964$1287 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -250589,10 +251457,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [2:0] connect \B 1'0 - connect \Y $eq$ls180.v:5912$1221_Y + connect \Y $eq$ls180.v:5964$1287_Y end - attribute \src "ls180.v:5914.94-5914.138" - cell $eq $eq$ls180.v:5914$1224 + attribute \src "ls180.v:5966.94-5966.138" + cell $eq $eq$ls180.v:5966$1290 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -250600,10 +251468,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [2:0] connect \B 1'1 - connect \Y $eq$ls180.v:5914$1224_Y + connect \Y $eq$ls180.v:5966$1290_Y end - attribute \src "ls180.v:5915.97-5915.141" - cell $eq $eq$ls180.v:5915$1228 + attribute \src "ls180.v:5967.97-5967.141" + cell $eq $eq$ls180.v:5967$1294 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -250611,10 +251479,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [2:0] connect \B 1'1 - connect \Y $eq$ls180.v:5915$1228_Y + connect \Y $eq$ls180.v:5967$1294_Y end - attribute \src "ls180.v:5917.94-5917.138" - cell $eq $eq$ls180.v:5917$1231 + attribute \src "ls180.v:5969.94-5969.138" + cell $eq $eq$ls180.v:5969$1297 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -250622,10 +251490,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [2:0] connect \B 2'10 - connect \Y $eq$ls180.v:5917$1231_Y + connect \Y $eq$ls180.v:5969$1297_Y end - attribute \src "ls180.v:5918.97-5918.141" - cell $eq $eq$ls180.v:5918$1235 + attribute \src "ls180.v:5970.97-5970.141" + cell $eq $eq$ls180.v:5970$1301 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -250633,10 +251501,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [2:0] connect \B 2'10 - connect \Y $eq$ls180.v:5918$1235_Y + connect \Y $eq$ls180.v:5970$1301_Y end - attribute \src "ls180.v:5920.94-5920.138" - cell $eq $eq$ls180.v:5920$1238 + attribute \src "ls180.v:5972.94-5972.138" + cell $eq $eq$ls180.v:5972$1304 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -250644,10 +251512,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [2:0] connect \B 2'11 - connect \Y $eq$ls180.v:5920$1238_Y + connect \Y $eq$ls180.v:5972$1304_Y end - attribute \src "ls180.v:5921.97-5921.141" - cell $eq $eq$ls180.v:5921$1242 + attribute \src "ls180.v:5973.97-5973.141" + cell $eq $eq$ls180.v:5973$1308 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -250655,10 +251523,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [2:0] connect \B 2'11 - connect \Y $eq$ls180.v:5921$1242_Y + connect \Y $eq$ls180.v:5973$1308_Y end - attribute \src "ls180.v:5923.95-5923.139" - cell $eq $eq$ls180.v:5923$1245 + attribute \src "ls180.v:5975.95-5975.139" + cell $eq $eq$ls180.v:5975$1311 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -250666,10 +251534,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [2:0] connect \B 3'100 - connect \Y $eq$ls180.v:5923$1245_Y + connect \Y $eq$ls180.v:5975$1311_Y end - attribute \src "ls180.v:5924.98-5924.142" - cell $eq $eq$ls180.v:5924$1249 + attribute \src "ls180.v:5976.98-5976.142" + cell $eq $eq$ls180.v:5976$1315 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -250677,10 +251545,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [2:0] connect \B 3'100 - connect \Y $eq$ls180.v:5924$1249_Y + connect \Y $eq$ls180.v:5976$1315_Y end - attribute \src "ls180.v:5926.95-5926.139" - cell $eq $eq$ls180.v:5926$1252 + attribute \src "ls180.v:5978.95-5978.139" + cell $eq $eq$ls180.v:5978$1318 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -250688,10 +251556,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [2:0] connect \B 3'101 - connect \Y $eq$ls180.v:5926$1252_Y + connect \Y $eq$ls180.v:5978$1318_Y end - attribute \src "ls180.v:5927.98-5927.142" - cell $eq $eq$ls180.v:5927$1256 + attribute \src "ls180.v:5979.98-5979.142" + cell $eq $eq$ls180.v:5979$1322 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -250699,21 +251567,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [2:0] connect \B 3'101 - connect \Y $eq$ls180.v:5927$1256_Y + connect \Y $eq$ls180.v:5979$1322_Y end - attribute \src "ls180.v:5935.32-5935.78" - cell $eq $eq$ls180.v:5935$1258 + attribute \src "ls180.v:5987.32-5987.78" + cell $eq $eq$ls180.v:5987$1324 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface2_bank_bus_adr [13:9] - connect \B 4'1011 - connect \Y $eq$ls180.v:5935$1258_Y + connect \A \builder_interface2_bank_bus_adr [13:8] + connect \B 4'1100 + connect \Y $eq$ls180.v:5987$1324_Y end - attribute \src "ls180.v:5937.93-5937.135" - cell $eq $eq$ls180.v:5937$1260 + attribute \src "ls180.v:5989.93-5989.135" + cell $eq $eq$ls180.v:5989$1326 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -250721,10 +251589,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface2_bank_bus_adr [0] connect \B 1'0 - connect \Y $eq$ls180.v:5937$1260_Y + connect \Y $eq$ls180.v:5989$1326_Y end - attribute \src "ls180.v:5938.96-5938.138" - cell $eq $eq$ls180.v:5938$1264 + attribute \src "ls180.v:5990.96-5990.138" + cell $eq $eq$ls180.v:5990$1330 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -250732,10 +251600,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface2_bank_bus_adr [0] connect \B 1'0 - connect \Y $eq$ls180.v:5938$1264_Y + connect \Y $eq$ls180.v:5990$1330_Y end - attribute \src "ls180.v:5940.92-5940.134" - cell $eq $eq$ls180.v:5940$1267 + attribute \src "ls180.v:5992.92-5992.134" + cell $eq $eq$ls180.v:5992$1333 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -250743,10 +251611,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface2_bank_bus_adr [0] connect \B 1'1 - connect \Y $eq$ls180.v:5940$1267_Y + connect \Y $eq$ls180.v:5992$1333_Y end - attribute \src "ls180.v:5941.95-5941.137" - cell $eq $eq$ls180.v:5941$1271 + attribute \src "ls180.v:5993.95-5993.137" + cell $eq $eq$ls180.v:5993$1337 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -250754,21 +251622,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface2_bank_bus_adr [0] connect \B 1'1 - connect \Y $eq$ls180.v:5941$1271_Y + connect \Y $eq$ls180.v:5993$1337_Y end - attribute \src "ls180.v:5949.32-5949.77" - cell $eq $eq$ls180.v:5949$1273 + attribute \src "ls180.v:6001.32-6001.78" + cell $eq $eq$ls180.v:6001$1339 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [13:9] - connect \B 4'1001 - connect \Y $eq$ls180.v:5949$1273_Y + connect \A \builder_interface3_bank_bus_adr [13:8] + connect \B 4'1010 + connect \Y $eq$ls180.v:6001$1339_Y end - attribute \src "ls180.v:5951.98-5951.142" - cell $eq $eq$ls180.v:5951$1275 + attribute \src "ls180.v:6003.98-6003.142" + cell $eq $eq$ls180.v:6003$1341 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250776,10 +251644,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:5951$1275_Y + connect \Y $eq$ls180.v:6003$1341_Y end - attribute \src "ls180.v:5952.101-5952.145" - cell $eq $eq$ls180.v:5952$1279 + attribute \src "ls180.v:6004.101-6004.145" + cell $eq $eq$ls180.v:6004$1345 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250787,10 +251655,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:5952$1279_Y + connect \Y $eq$ls180.v:6004$1345_Y end - attribute \src "ls180.v:5954.97-5954.141" - cell $eq $eq$ls180.v:5954$1282 + attribute \src "ls180.v:6006.97-6006.141" + cell $eq $eq$ls180.v:6006$1348 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250798,10 +251666,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:5954$1282_Y + connect \Y $eq$ls180.v:6006$1348_Y end - attribute \src "ls180.v:5955.100-5955.144" - cell $eq $eq$ls180.v:5955$1286 + attribute \src "ls180.v:6007.100-6007.144" + cell $eq $eq$ls180.v:6007$1352 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250809,10 +251677,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:5955$1286_Y + connect \Y $eq$ls180.v:6007$1352_Y end - attribute \src "ls180.v:5957.97-5957.141" - cell $eq $eq$ls180.v:5957$1289 + attribute \src "ls180.v:6009.97-6009.141" + cell $eq $eq$ls180.v:6009$1355 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250820,10 +251688,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:5957$1289_Y + connect \Y $eq$ls180.v:6009$1355_Y end - attribute \src "ls180.v:5958.100-5958.144" - cell $eq $eq$ls180.v:5958$1293 + attribute \src "ls180.v:6010.100-6010.144" + cell $eq $eq$ls180.v:6010$1359 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250831,10 +251699,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:5958$1293_Y + connect \Y $eq$ls180.v:6010$1359_Y end - attribute \src "ls180.v:5960.97-5960.141" - cell $eq $eq$ls180.v:5960$1296 + attribute \src "ls180.v:6012.97-6012.141" + cell $eq $eq$ls180.v:6012$1362 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250842,10 +251710,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:5960$1296_Y + connect \Y $eq$ls180.v:6012$1362_Y end - attribute \src "ls180.v:5961.100-5961.144" - cell $eq $eq$ls180.v:5961$1300 + attribute \src "ls180.v:6013.100-6013.144" + cell $eq $eq$ls180.v:6013$1366 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250853,10 +251721,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:5961$1300_Y + connect \Y $eq$ls180.v:6013$1366_Y end - attribute \src "ls180.v:5963.97-5963.141" - cell $eq $eq$ls180.v:5963$1303 + attribute \src "ls180.v:6015.97-6015.141" + cell $eq $eq$ls180.v:6015$1369 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250864,10 +251732,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:5963$1303_Y + connect \Y $eq$ls180.v:6015$1369_Y end - attribute \src "ls180.v:5964.100-5964.144" - cell $eq $eq$ls180.v:5964$1307 + attribute \src "ls180.v:6016.100-6016.144" + cell $eq $eq$ls180.v:6016$1373 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250875,10 +251743,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:5964$1307_Y + connect \Y $eq$ls180.v:6016$1373_Y end - attribute \src "ls180.v:5966.98-5966.142" - cell $eq $eq$ls180.v:5966$1310 + attribute \src "ls180.v:6018.98-6018.142" + cell $eq $eq$ls180.v:6018$1376 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250886,10 +251754,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:5966$1310_Y + connect \Y $eq$ls180.v:6018$1376_Y end - attribute \src "ls180.v:5967.101-5967.145" - cell $eq $eq$ls180.v:5967$1314 + attribute \src "ls180.v:6019.101-6019.145" + cell $eq $eq$ls180.v:6019$1380 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250897,10 +251765,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:5967$1314_Y + connect \Y $eq$ls180.v:6019$1380_Y end - attribute \src "ls180.v:5969.98-5969.142" - cell $eq $eq$ls180.v:5969$1317 + attribute \src "ls180.v:6021.98-6021.142" + cell $eq $eq$ls180.v:6021$1383 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250908,10 +251776,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:5969$1317_Y + connect \Y $eq$ls180.v:6021$1383_Y end - attribute \src "ls180.v:5970.101-5970.145" - cell $eq $eq$ls180.v:5970$1321 + attribute \src "ls180.v:6022.101-6022.145" + cell $eq $eq$ls180.v:6022$1387 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250919,10 +251787,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:5970$1321_Y + connect \Y $eq$ls180.v:6022$1387_Y end - attribute \src "ls180.v:5972.98-5972.142" - cell $eq $eq$ls180.v:5972$1324 + attribute \src "ls180.v:6024.98-6024.142" + cell $eq $eq$ls180.v:6024$1390 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250930,10 +251798,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:5972$1324_Y + connect \Y $eq$ls180.v:6024$1390_Y end - attribute \src "ls180.v:5973.101-5973.145" - cell $eq $eq$ls180.v:5973$1328 + attribute \src "ls180.v:6025.101-6025.145" + cell $eq $eq$ls180.v:6025$1394 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250941,10 +251809,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:5973$1328_Y + connect \Y $eq$ls180.v:6025$1394_Y end - attribute \src "ls180.v:5975.98-5975.142" - cell $eq $eq$ls180.v:5975$1331 + attribute \src "ls180.v:6027.98-6027.142" + cell $eq $eq$ls180.v:6027$1397 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250952,10 +251820,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:5975$1331_Y + connect \Y $eq$ls180.v:6027$1397_Y end - attribute \src "ls180.v:5976.101-5976.145" - cell $eq $eq$ls180.v:5976$1335 + attribute \src "ls180.v:6028.101-6028.145" + cell $eq $eq$ls180.v:6028$1401 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250963,21 +251831,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:5976$1335_Y + connect \Y $eq$ls180.v:6028$1401_Y end - attribute \src "ls180.v:5986.32-5986.78" - cell $eq $eq$ls180.v:5986$1337 + attribute \src "ls180.v:6038.32-6038.78" + cell $eq $eq$ls180.v:6038$1403 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [13:9] - connect \B 4'1010 - connect \Y $eq$ls180.v:5986$1337_Y + connect \A \builder_interface4_bank_bus_adr [13:8] + connect \B 4'1011 + connect \Y $eq$ls180.v:6038$1403_Y end - attribute \src "ls180.v:5988.98-5988.142" - cell $eq $eq$ls180.v:5988$1339 + attribute \src "ls180.v:6040.98-6040.142" + cell $eq $eq$ls180.v:6040$1405 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250985,10 +251853,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:5988$1339_Y + connect \Y $eq$ls180.v:6040$1405_Y end - attribute \src "ls180.v:5989.101-5989.145" - cell $eq $eq$ls180.v:5989$1343 + attribute \src "ls180.v:6041.101-6041.145" + cell $eq $eq$ls180.v:6041$1409 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -250996,10 +251864,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:5989$1343_Y + connect \Y $eq$ls180.v:6041$1409_Y end - attribute \src "ls180.v:5991.97-5991.141" - cell $eq $eq$ls180.v:5991$1346 + attribute \src "ls180.v:6043.97-6043.141" + cell $eq $eq$ls180.v:6043$1412 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251007,10 +251875,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:5991$1346_Y + connect \Y $eq$ls180.v:6043$1412_Y end - attribute \src "ls180.v:5992.100-5992.144" - cell $eq $eq$ls180.v:5992$1350 + attribute \src "ls180.v:6044.100-6044.144" + cell $eq $eq$ls180.v:6044$1416 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251018,10 +251886,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:5992$1350_Y + connect \Y $eq$ls180.v:6044$1416_Y end - attribute \src "ls180.v:5994.97-5994.141" - cell $eq $eq$ls180.v:5994$1353 + attribute \src "ls180.v:6046.97-6046.141" + cell $eq $eq$ls180.v:6046$1419 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251029,10 +251897,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:5994$1353_Y + connect \Y $eq$ls180.v:6046$1419_Y end - attribute \src "ls180.v:5995.100-5995.144" - cell $eq $eq$ls180.v:5995$1357 + attribute \src "ls180.v:6047.100-6047.144" + cell $eq $eq$ls180.v:6047$1423 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251040,10 +251908,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:5995$1357_Y + connect \Y $eq$ls180.v:6047$1423_Y end - attribute \src "ls180.v:5997.97-5997.141" - cell $eq $eq$ls180.v:5997$1360 + attribute \src "ls180.v:6049.97-6049.141" + cell $eq $eq$ls180.v:6049$1426 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251051,10 +251919,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:5997$1360_Y + connect \Y $eq$ls180.v:6049$1426_Y end - attribute \src "ls180.v:5998.100-5998.144" - cell $eq $eq$ls180.v:5998$1364 + attribute \src "ls180.v:6050.100-6050.144" + cell $eq $eq$ls180.v:6050$1430 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251062,10 +251930,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:5998$1364_Y + connect \Y $eq$ls180.v:6050$1430_Y end - attribute \src "ls180.v:6000.97-6000.141" - cell $eq $eq$ls180.v:6000$1367 + attribute \src "ls180.v:6052.97-6052.141" + cell $eq $eq$ls180.v:6052$1433 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251073,10 +251941,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:6000$1367_Y + connect \Y $eq$ls180.v:6052$1433_Y end - attribute \src "ls180.v:6001.100-6001.144" - cell $eq $eq$ls180.v:6001$1371 + attribute \src "ls180.v:6053.100-6053.144" + cell $eq $eq$ls180.v:6053$1437 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251084,10 +251952,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:6001$1371_Y + connect \Y $eq$ls180.v:6053$1437_Y end - attribute \src "ls180.v:6003.98-6003.142" - cell $eq $eq$ls180.v:6003$1374 + attribute \src "ls180.v:6055.98-6055.142" + cell $eq $eq$ls180.v:6055$1440 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251095,10 +251963,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:6003$1374_Y + connect \Y $eq$ls180.v:6055$1440_Y end - attribute \src "ls180.v:6004.101-6004.145" - cell $eq $eq$ls180.v:6004$1378 + attribute \src "ls180.v:6056.101-6056.145" + cell $eq $eq$ls180.v:6056$1444 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251106,10 +251974,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:6004$1378_Y + connect \Y $eq$ls180.v:6056$1444_Y end - attribute \src "ls180.v:6006.98-6006.142" - cell $eq $eq$ls180.v:6006$1381 + attribute \src "ls180.v:6058.98-6058.142" + cell $eq $eq$ls180.v:6058$1447 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251117,10 +251985,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:6006$1381_Y + connect \Y $eq$ls180.v:6058$1447_Y end - attribute \src "ls180.v:6007.101-6007.145" - cell $eq $eq$ls180.v:6007$1385 + attribute \src "ls180.v:6059.101-6059.145" + cell $eq $eq$ls180.v:6059$1451 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251128,10 +251996,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:6007$1385_Y + connect \Y $eq$ls180.v:6059$1451_Y end - attribute \src "ls180.v:6009.98-6009.142" - cell $eq $eq$ls180.v:6009$1388 + attribute \src "ls180.v:6061.98-6061.142" + cell $eq $eq$ls180.v:6061$1454 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251139,10 +252007,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:6009$1388_Y + connect \Y $eq$ls180.v:6061$1454_Y end - attribute \src "ls180.v:6010.101-6010.145" - cell $eq $eq$ls180.v:6010$1392 + attribute \src "ls180.v:6062.101-6062.145" + cell $eq $eq$ls180.v:6062$1458 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251150,10 +252018,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:6010$1392_Y + connect \Y $eq$ls180.v:6062$1458_Y end - attribute \src "ls180.v:6012.98-6012.142" - cell $eq $eq$ls180.v:6012$1395 + attribute \src "ls180.v:6064.98-6064.142" + cell $eq $eq$ls180.v:6064$1461 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251161,10 +252029,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6012$1395_Y + connect \Y $eq$ls180.v:6064$1461_Y end - attribute \src "ls180.v:6013.101-6013.145" - cell $eq $eq$ls180.v:6013$1399 + attribute \src "ls180.v:6065.101-6065.145" + cell $eq $eq$ls180.v:6065$1465 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251172,21 +252040,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6013$1399_Y + connect \Y $eq$ls180.v:6065$1465_Y end - attribute \src "ls180.v:6023.32-6023.78" - cell $eq $eq$ls180.v:6023$1401 + attribute \src "ls180.v:6075.32-6075.78" + cell $eq $eq$ls180.v:6075$1467 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [13:9] - connect \B 4'1110 - connect \Y $eq$ls180.v:6023$1401_Y + connect \A \builder_interface5_bank_bus_adr [13:8] + connect \B 4'1111 + connect \Y $eq$ls180.v:6075$1467_Y end - attribute \src "ls180.v:6025.100-6025.144" - cell $eq $eq$ls180.v:6025$1403 + attribute \src "ls180.v:6077.100-6077.144" + cell $eq $eq$ls180.v:6077$1469 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251194,10 +252062,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:6025$1403_Y + connect \Y $eq$ls180.v:6077$1469_Y end - attribute \src "ls180.v:6026.103-6026.147" - cell $eq $eq$ls180.v:6026$1407 + attribute \src "ls180.v:6078.103-6078.147" + cell $eq $eq$ls180.v:6078$1473 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251205,10 +252073,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:6026$1407_Y + connect \Y $eq$ls180.v:6078$1473_Y end - attribute \src "ls180.v:6028.100-6028.144" - cell $eq $eq$ls180.v:6028$1410 + attribute \src "ls180.v:6080.100-6080.144" + cell $eq $eq$ls180.v:6080$1476 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251216,10 +252084,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:6028$1410_Y + connect \Y $eq$ls180.v:6080$1476_Y end - attribute \src "ls180.v:6029.103-6029.147" - cell $eq $eq$ls180.v:6029$1414 + attribute \src "ls180.v:6081.103-6081.147" + cell $eq $eq$ls180.v:6081$1480 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251227,10 +252095,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:6029$1414_Y + connect \Y $eq$ls180.v:6081$1480_Y end - attribute \src "ls180.v:6031.100-6031.144" - cell $eq $eq$ls180.v:6031$1417 + attribute \src "ls180.v:6083.100-6083.144" + cell $eq $eq$ls180.v:6083$1483 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251238,10 +252106,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:6031$1417_Y + connect \Y $eq$ls180.v:6083$1483_Y end - attribute \src "ls180.v:6032.103-6032.147" - cell $eq $eq$ls180.v:6032$1421 + attribute \src "ls180.v:6084.103-6084.147" + cell $eq $eq$ls180.v:6084$1487 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251249,10 +252117,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:6032$1421_Y + connect \Y $eq$ls180.v:6084$1487_Y end - attribute \src "ls180.v:6034.100-6034.144" - cell $eq $eq$ls180.v:6034$1424 + attribute \src "ls180.v:6086.100-6086.144" + cell $eq $eq$ls180.v:6086$1490 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251260,10 +252128,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:6034$1424_Y + connect \Y $eq$ls180.v:6086$1490_Y end - attribute \src "ls180.v:6035.103-6035.147" - cell $eq $eq$ls180.v:6035$1428 + attribute \src "ls180.v:6087.103-6087.147" + cell $eq $eq$ls180.v:6087$1494 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251271,10 +252139,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:6035$1428_Y + connect \Y $eq$ls180.v:6087$1494_Y end - attribute \src "ls180.v:6037.100-6037.144" - cell $eq $eq$ls180.v:6037$1431 + attribute \src "ls180.v:6089.100-6089.144" + cell $eq $eq$ls180.v:6089$1497 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251282,10 +252150,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:6037$1431_Y + connect \Y $eq$ls180.v:6089$1497_Y end - attribute \src "ls180.v:6038.103-6038.147" - cell $eq $eq$ls180.v:6038$1435 + attribute \src "ls180.v:6090.103-6090.147" + cell $eq $eq$ls180.v:6090$1501 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251293,10 +252161,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:6038$1435_Y + connect \Y $eq$ls180.v:6090$1501_Y end - attribute \src "ls180.v:6040.100-6040.144" - cell $eq $eq$ls180.v:6040$1438 + attribute \src "ls180.v:6092.100-6092.144" + cell $eq $eq$ls180.v:6092$1504 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251304,10 +252172,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:6040$1438_Y + connect \Y $eq$ls180.v:6092$1504_Y end - attribute \src "ls180.v:6041.103-6041.147" - cell $eq $eq$ls180.v:6041$1442 + attribute \src "ls180.v:6093.103-6093.147" + cell $eq $eq$ls180.v:6093$1508 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251315,10 +252183,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:6041$1442_Y + connect \Y $eq$ls180.v:6093$1508_Y end - attribute \src "ls180.v:6043.100-6043.144" - cell $eq $eq$ls180.v:6043$1445 + attribute \src "ls180.v:6095.100-6095.144" + cell $eq $eq$ls180.v:6095$1511 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251326,10 +252194,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:6043$1445_Y + connect \Y $eq$ls180.v:6095$1511_Y end - attribute \src "ls180.v:6044.103-6044.147" - cell $eq $eq$ls180.v:6044$1449 + attribute \src "ls180.v:6096.103-6096.147" + cell $eq $eq$ls180.v:6096$1515 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251337,10 +252205,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:6044$1449_Y + connect \Y $eq$ls180.v:6096$1515_Y end - attribute \src "ls180.v:6046.100-6046.144" - cell $eq $eq$ls180.v:6046$1452 + attribute \src "ls180.v:6098.100-6098.144" + cell $eq $eq$ls180.v:6098$1518 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251348,10 +252216,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:6046$1452_Y + connect \Y $eq$ls180.v:6098$1518_Y end - attribute \src "ls180.v:6047.103-6047.147" - cell $eq $eq$ls180.v:6047$1456 + attribute \src "ls180.v:6099.103-6099.147" + cell $eq $eq$ls180.v:6099$1522 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251359,10 +252227,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:6047$1456_Y + connect \Y $eq$ls180.v:6099$1522_Y end - attribute \src "ls180.v:6049.102-6049.146" - cell $eq $eq$ls180.v:6049$1459 + attribute \src "ls180.v:6101.102-6101.146" + cell $eq $eq$ls180.v:6101$1525 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251370,10 +252238,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6049$1459_Y + connect \Y $eq$ls180.v:6101$1525_Y end - attribute \src "ls180.v:6050.105-6050.149" - cell $eq $eq$ls180.v:6050$1463 + attribute \src "ls180.v:6102.105-6102.149" + cell $eq $eq$ls180.v:6102$1529 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251381,10 +252249,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6050$1463_Y + connect \Y $eq$ls180.v:6102$1529_Y end - attribute \src "ls180.v:6052.102-6052.146" - cell $eq $eq$ls180.v:6052$1466 + attribute \src "ls180.v:6104.102-6104.146" + cell $eq $eq$ls180.v:6104$1532 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251392,10 +252260,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 4'1001 - connect \Y $eq$ls180.v:6052$1466_Y + connect \Y $eq$ls180.v:6104$1532_Y end - attribute \src "ls180.v:6053.105-6053.149" - cell $eq $eq$ls180.v:6053$1470 + attribute \src "ls180.v:6105.105-6105.149" + cell $eq $eq$ls180.v:6105$1536 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251403,10 +252271,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 4'1001 - connect \Y $eq$ls180.v:6053$1470_Y + connect \Y $eq$ls180.v:6105$1536_Y end - attribute \src "ls180.v:6055.102-6055.147" - cell $eq $eq$ls180.v:6055$1473 + attribute \src "ls180.v:6107.102-6107.147" + cell $eq $eq$ls180.v:6107$1539 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251414,10 +252282,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 4'1010 - connect \Y $eq$ls180.v:6055$1473_Y + connect \Y $eq$ls180.v:6107$1539_Y end - attribute \src "ls180.v:6056.105-6056.150" - cell $eq $eq$ls180.v:6056$1477 + attribute \src "ls180.v:6108.105-6108.150" + cell $eq $eq$ls180.v:6108$1543 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251425,10 +252293,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 4'1010 - connect \Y $eq$ls180.v:6056$1477_Y + connect \Y $eq$ls180.v:6108$1543_Y end - attribute \src "ls180.v:6058.102-6058.147" - cell $eq $eq$ls180.v:6058$1480 + attribute \src "ls180.v:6110.102-6110.147" + cell $eq $eq$ls180.v:6110$1546 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251436,10 +252304,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 4'1011 - connect \Y $eq$ls180.v:6058$1480_Y + connect \Y $eq$ls180.v:6110$1546_Y end - attribute \src "ls180.v:6059.105-6059.150" - cell $eq $eq$ls180.v:6059$1484 + attribute \src "ls180.v:6111.105-6111.150" + cell $eq $eq$ls180.v:6111$1550 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251447,10 +252315,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 4'1011 - connect \Y $eq$ls180.v:6059$1484_Y + connect \Y $eq$ls180.v:6111$1550_Y end - attribute \src "ls180.v:6061.102-6061.147" - cell $eq $eq$ls180.v:6061$1487 + attribute \src "ls180.v:6113.102-6113.147" + cell $eq $eq$ls180.v:6113$1553 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251458,10 +252326,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 4'1100 - connect \Y $eq$ls180.v:6061$1487_Y + connect \Y $eq$ls180.v:6113$1553_Y end - attribute \src "ls180.v:6062.105-6062.150" - cell $eq $eq$ls180.v:6062$1491 + attribute \src "ls180.v:6114.105-6114.150" + cell $eq $eq$ls180.v:6114$1557 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251469,10 +252337,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 4'1100 - connect \Y $eq$ls180.v:6062$1491_Y + connect \Y $eq$ls180.v:6114$1557_Y end - attribute \src "ls180.v:6064.99-6064.144" - cell $eq $eq$ls180.v:6064$1494 + attribute \src "ls180.v:6116.99-6116.144" + cell $eq $eq$ls180.v:6116$1560 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251480,10 +252348,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 4'1101 - connect \Y $eq$ls180.v:6064$1494_Y + connect \Y $eq$ls180.v:6116$1560_Y end - attribute \src "ls180.v:6065.102-6065.147" - cell $eq $eq$ls180.v:6065$1498 + attribute \src "ls180.v:6117.102-6117.147" + cell $eq $eq$ls180.v:6117$1564 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251491,10 +252359,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 4'1101 - connect \Y $eq$ls180.v:6065$1498_Y + connect \Y $eq$ls180.v:6117$1564_Y end - attribute \src "ls180.v:6067.100-6067.145" - cell $eq $eq$ls180.v:6067$1501 + attribute \src "ls180.v:6119.100-6119.145" + cell $eq $eq$ls180.v:6119$1567 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251502,10 +252370,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 4'1110 - connect \Y $eq$ls180.v:6067$1501_Y + connect \Y $eq$ls180.v:6119$1567_Y end - attribute \src "ls180.v:6068.103-6068.148" - cell $eq $eq$ls180.v:6068$1505 + attribute \src "ls180.v:6120.103-6120.148" + cell $eq $eq$ls180.v:6120$1571 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -251513,21 +252381,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 4'1110 - connect \Y $eq$ls180.v:6068$1505_Y + connect \Y $eq$ls180.v:6120$1571_Y end - attribute \src "ls180.v:6085.32-6085.78" - cell $eq $eq$ls180.v:6085$1507 + attribute \src "ls180.v:6137.32-6137.78" + cell $eq $eq$ls180.v:6137$1573 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [13:9] - connect \B 4'1101 - connect \Y $eq$ls180.v:6085$1507_Y + connect \A \builder_interface6_bank_bus_adr [13:8] + connect \B 4'1110 + connect \Y $eq$ls180.v:6137$1573_Y end - attribute \src "ls180.v:6087.104-6087.148" - cell $eq $eq$ls180.v:6087$1509 + attribute \src "ls180.v:6139.104-6139.148" + cell $eq $eq$ls180.v:6139$1575 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251535,10 +252403,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 1'0 - connect \Y $eq$ls180.v:6087$1509_Y + connect \Y $eq$ls180.v:6139$1575_Y end - attribute \src "ls180.v:6088.107-6088.151" - cell $eq $eq$ls180.v:6088$1513 + attribute \src "ls180.v:6140.107-6140.151" + cell $eq $eq$ls180.v:6140$1579 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251546,10 +252414,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 1'0 - connect \Y $eq$ls180.v:6088$1513_Y + connect \Y $eq$ls180.v:6140$1579_Y end - attribute \src "ls180.v:6090.104-6090.148" - cell $eq $eq$ls180.v:6090$1516 + attribute \src "ls180.v:6142.104-6142.148" + cell $eq $eq$ls180.v:6142$1582 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251557,10 +252425,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 1'1 - connect \Y $eq$ls180.v:6090$1516_Y + connect \Y $eq$ls180.v:6142$1582_Y end - attribute \src "ls180.v:6091.107-6091.151" - cell $eq $eq$ls180.v:6091$1520 + attribute \src "ls180.v:6143.107-6143.151" + cell $eq $eq$ls180.v:6143$1586 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251568,10 +252436,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 1'1 - connect \Y $eq$ls180.v:6091$1520_Y + connect \Y $eq$ls180.v:6143$1586_Y end - attribute \src "ls180.v:6093.104-6093.148" - cell $eq $eq$ls180.v:6093$1523 + attribute \src "ls180.v:6145.104-6145.148" + cell $eq $eq$ls180.v:6145$1589 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251579,10 +252447,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 2'10 - connect \Y $eq$ls180.v:6093$1523_Y + connect \Y $eq$ls180.v:6145$1589_Y end - attribute \src "ls180.v:6094.107-6094.151" - cell $eq $eq$ls180.v:6094$1527 + attribute \src "ls180.v:6146.107-6146.151" + cell $eq $eq$ls180.v:6146$1593 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251590,10 +252458,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 2'10 - connect \Y $eq$ls180.v:6094$1527_Y + connect \Y $eq$ls180.v:6146$1593_Y end - attribute \src "ls180.v:6096.104-6096.148" - cell $eq $eq$ls180.v:6096$1530 + attribute \src "ls180.v:6148.104-6148.148" + cell $eq $eq$ls180.v:6148$1596 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251601,10 +252469,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 2'11 - connect \Y $eq$ls180.v:6096$1530_Y + connect \Y $eq$ls180.v:6148$1596_Y end - attribute \src "ls180.v:6097.107-6097.151" - cell $eq $eq$ls180.v:6097$1534 + attribute \src "ls180.v:6149.107-6149.151" + cell $eq $eq$ls180.v:6149$1600 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251612,10 +252480,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 2'11 - connect \Y $eq$ls180.v:6097$1534_Y + connect \Y $eq$ls180.v:6149$1600_Y end - attribute \src "ls180.v:6099.103-6099.147" - cell $eq $eq$ls180.v:6099$1537 + attribute \src "ls180.v:6151.103-6151.147" + cell $eq $eq$ls180.v:6151$1603 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251623,10 +252491,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 3'100 - connect \Y $eq$ls180.v:6099$1537_Y + connect \Y $eq$ls180.v:6151$1603_Y end - attribute \src "ls180.v:6100.106-6100.150" - cell $eq $eq$ls180.v:6100$1541 + attribute \src "ls180.v:6152.106-6152.150" + cell $eq $eq$ls180.v:6152$1607 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251634,10 +252502,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 3'100 - connect \Y $eq$ls180.v:6100$1541_Y + connect \Y $eq$ls180.v:6152$1607_Y end - attribute \src "ls180.v:6102.103-6102.147" - cell $eq $eq$ls180.v:6102$1544 + attribute \src "ls180.v:6154.103-6154.147" + cell $eq $eq$ls180.v:6154$1610 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251645,10 +252513,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 3'101 - connect \Y $eq$ls180.v:6102$1544_Y + connect \Y $eq$ls180.v:6154$1610_Y end - attribute \src "ls180.v:6103.106-6103.150" - cell $eq $eq$ls180.v:6103$1548 + attribute \src "ls180.v:6155.106-6155.150" + cell $eq $eq$ls180.v:6155$1614 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251656,10 +252524,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 3'101 - connect \Y $eq$ls180.v:6103$1548_Y + connect \Y $eq$ls180.v:6155$1614_Y end - attribute \src "ls180.v:6105.103-6105.147" - cell $eq $eq$ls180.v:6105$1551 + attribute \src "ls180.v:6157.103-6157.147" + cell $eq $eq$ls180.v:6157$1617 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251667,10 +252535,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 3'110 - connect \Y $eq$ls180.v:6105$1551_Y + connect \Y $eq$ls180.v:6157$1617_Y end - attribute \src "ls180.v:6106.106-6106.150" - cell $eq $eq$ls180.v:6106$1555 + attribute \src "ls180.v:6158.106-6158.150" + cell $eq $eq$ls180.v:6158$1621 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251678,10 +252546,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 3'110 - connect \Y $eq$ls180.v:6106$1555_Y + connect \Y $eq$ls180.v:6158$1621_Y end - attribute \src "ls180.v:6108.103-6108.147" - cell $eq $eq$ls180.v:6108$1558 + attribute \src "ls180.v:6160.103-6160.147" + cell $eq $eq$ls180.v:6160$1624 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251689,10 +252557,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 3'111 - connect \Y $eq$ls180.v:6108$1558_Y + connect \Y $eq$ls180.v:6160$1624_Y end - attribute \src "ls180.v:6109.106-6109.150" - cell $eq $eq$ls180.v:6109$1562 + attribute \src "ls180.v:6161.106-6161.150" + cell $eq $eq$ls180.v:6161$1628 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251700,10 +252568,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 3'111 - connect \Y $eq$ls180.v:6109$1562_Y + connect \Y $eq$ls180.v:6161$1628_Y end - attribute \src "ls180.v:6111.94-6111.138" - cell $eq $eq$ls180.v:6111$1565 + attribute \src "ls180.v:6163.94-6163.138" + cell $eq $eq$ls180.v:6163$1631 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251711,10 +252579,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6111$1565_Y + connect \Y $eq$ls180.v:6163$1631_Y end - attribute \src "ls180.v:6112.97-6112.141" - cell $eq $eq$ls180.v:6112$1569 + attribute \src "ls180.v:6164.97-6164.141" + cell $eq $eq$ls180.v:6164$1635 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251722,10 +252590,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6112$1569_Y + connect \Y $eq$ls180.v:6164$1635_Y end - attribute \src "ls180.v:6114.105-6114.149" - cell $eq $eq$ls180.v:6114$1572 + attribute \src "ls180.v:6166.105-6166.149" + cell $eq $eq$ls180.v:6166$1638 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251733,10 +252601,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1001 - connect \Y $eq$ls180.v:6114$1572_Y + connect \Y $eq$ls180.v:6166$1638_Y end - attribute \src "ls180.v:6115.108-6115.152" - cell $eq $eq$ls180.v:6115$1576 + attribute \src "ls180.v:6167.108-6167.152" + cell $eq $eq$ls180.v:6167$1642 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251744,10 +252612,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1001 - connect \Y $eq$ls180.v:6115$1576_Y + connect \Y $eq$ls180.v:6167$1642_Y end - attribute \src "ls180.v:6117.105-6117.150" - cell $eq $eq$ls180.v:6117$1579 + attribute \src "ls180.v:6169.105-6169.150" + cell $eq $eq$ls180.v:6169$1645 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251755,10 +252623,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1010 - connect \Y $eq$ls180.v:6117$1579_Y + connect \Y $eq$ls180.v:6169$1645_Y end - attribute \src "ls180.v:6118.108-6118.153" - cell $eq $eq$ls180.v:6118$1583 + attribute \src "ls180.v:6170.108-6170.153" + cell $eq $eq$ls180.v:6170$1649 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251766,10 +252634,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1010 - connect \Y $eq$ls180.v:6118$1583_Y + connect \Y $eq$ls180.v:6170$1649_Y end - attribute \src "ls180.v:6120.105-6120.150" - cell $eq $eq$ls180.v:6120$1586 + attribute \src "ls180.v:6172.105-6172.150" + cell $eq $eq$ls180.v:6172$1652 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251777,10 +252645,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1011 - connect \Y $eq$ls180.v:6120$1586_Y + connect \Y $eq$ls180.v:6172$1652_Y end - attribute \src "ls180.v:6121.108-6121.153" - cell $eq $eq$ls180.v:6121$1590 + attribute \src "ls180.v:6173.108-6173.153" + cell $eq $eq$ls180.v:6173$1656 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251788,10 +252656,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1011 - connect \Y $eq$ls180.v:6121$1590_Y + connect \Y $eq$ls180.v:6173$1656_Y end - attribute \src "ls180.v:6123.105-6123.150" - cell $eq $eq$ls180.v:6123$1593 + attribute \src "ls180.v:6175.105-6175.150" + cell $eq $eq$ls180.v:6175$1659 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251799,10 +252667,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1100 - connect \Y $eq$ls180.v:6123$1593_Y + connect \Y $eq$ls180.v:6175$1659_Y end - attribute \src "ls180.v:6124.108-6124.153" - cell $eq $eq$ls180.v:6124$1597 + attribute \src "ls180.v:6176.108-6176.153" + cell $eq $eq$ls180.v:6176$1663 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251810,10 +252678,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1100 - connect \Y $eq$ls180.v:6124$1597_Y + connect \Y $eq$ls180.v:6176$1663_Y end - attribute \src "ls180.v:6126.105-6126.150" - cell $eq $eq$ls180.v:6126$1600 + attribute \src "ls180.v:6178.105-6178.150" + cell $eq $eq$ls180.v:6178$1666 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251821,10 +252689,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1101 - connect \Y $eq$ls180.v:6126$1600_Y + connect \Y $eq$ls180.v:6178$1666_Y end - attribute \src "ls180.v:6127.108-6127.153" - cell $eq $eq$ls180.v:6127$1604 + attribute \src "ls180.v:6179.108-6179.153" + cell $eq $eq$ls180.v:6179$1670 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251832,10 +252700,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1101 - connect \Y $eq$ls180.v:6127$1604_Y + connect \Y $eq$ls180.v:6179$1670_Y end - attribute \src "ls180.v:6129.105-6129.150" - cell $eq $eq$ls180.v:6129$1607 + attribute \src "ls180.v:6181.105-6181.150" + cell $eq $eq$ls180.v:6181$1673 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251843,10 +252711,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1110 - connect \Y $eq$ls180.v:6129$1607_Y + connect \Y $eq$ls180.v:6181$1673_Y end - attribute \src "ls180.v:6130.108-6130.153" - cell $eq $eq$ls180.v:6130$1611 + attribute \src "ls180.v:6182.108-6182.153" + cell $eq $eq$ls180.v:6182$1677 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251854,10 +252722,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1110 - connect \Y $eq$ls180.v:6130$1611_Y + connect \Y $eq$ls180.v:6182$1677_Y end - attribute \src "ls180.v:6132.104-6132.149" - cell $eq $eq$ls180.v:6132$1614 + attribute \src "ls180.v:6184.104-6184.149" + cell $eq $eq$ls180.v:6184$1680 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251865,10 +252733,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1111 - connect \Y $eq$ls180.v:6132$1614_Y + connect \Y $eq$ls180.v:6184$1680_Y end - attribute \src "ls180.v:6133.107-6133.152" - cell $eq $eq$ls180.v:6133$1618 + attribute \src "ls180.v:6185.107-6185.152" + cell $eq $eq$ls180.v:6185$1684 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251876,10 +252744,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1111 - connect \Y $eq$ls180.v:6133$1618_Y + connect \Y $eq$ls180.v:6185$1684_Y end - attribute \src "ls180.v:6135.104-6135.149" - cell $eq $eq$ls180.v:6135$1621 + attribute \src "ls180.v:6187.104-6187.149" + cell $eq $eq$ls180.v:6187$1687 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251887,10 +252755,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10000 - connect \Y $eq$ls180.v:6135$1621_Y + connect \Y $eq$ls180.v:6187$1687_Y end - attribute \src "ls180.v:6136.107-6136.152" - cell $eq $eq$ls180.v:6136$1625 + attribute \src "ls180.v:6188.107-6188.152" + cell $eq $eq$ls180.v:6188$1691 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251898,10 +252766,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10000 - connect \Y $eq$ls180.v:6136$1625_Y + connect \Y $eq$ls180.v:6188$1691_Y end - attribute \src "ls180.v:6138.104-6138.149" - cell $eq $eq$ls180.v:6138$1628 + attribute \src "ls180.v:6190.104-6190.149" + cell $eq $eq$ls180.v:6190$1694 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251909,10 +252777,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10001 - connect \Y $eq$ls180.v:6138$1628_Y + connect \Y $eq$ls180.v:6190$1694_Y end - attribute \src "ls180.v:6139.107-6139.152" - cell $eq $eq$ls180.v:6139$1632 + attribute \src "ls180.v:6191.107-6191.152" + cell $eq $eq$ls180.v:6191$1698 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251920,10 +252788,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10001 - connect \Y $eq$ls180.v:6139$1632_Y + connect \Y $eq$ls180.v:6191$1698_Y end - attribute \src "ls180.v:6141.104-6141.149" - cell $eq $eq$ls180.v:6141$1635 + attribute \src "ls180.v:6193.104-6193.149" + cell $eq $eq$ls180.v:6193$1701 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251931,10 +252799,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10010 - connect \Y $eq$ls180.v:6141$1635_Y + connect \Y $eq$ls180.v:6193$1701_Y end - attribute \src "ls180.v:6142.107-6142.152" - cell $eq $eq$ls180.v:6142$1639 + attribute \src "ls180.v:6194.107-6194.152" + cell $eq $eq$ls180.v:6194$1705 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251942,10 +252810,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10010 - connect \Y $eq$ls180.v:6142$1639_Y + connect \Y $eq$ls180.v:6194$1705_Y end - attribute \src "ls180.v:6144.104-6144.149" - cell $eq $eq$ls180.v:6144$1642 + attribute \src "ls180.v:6196.104-6196.149" + cell $eq $eq$ls180.v:6196$1708 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251953,10 +252821,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10011 - connect \Y $eq$ls180.v:6144$1642_Y + connect \Y $eq$ls180.v:6196$1708_Y end - attribute \src "ls180.v:6145.107-6145.152" - cell $eq $eq$ls180.v:6145$1646 + attribute \src "ls180.v:6197.107-6197.152" + cell $eq $eq$ls180.v:6197$1712 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251964,10 +252832,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10011 - connect \Y $eq$ls180.v:6145$1646_Y + connect \Y $eq$ls180.v:6197$1712_Y end - attribute \src "ls180.v:6147.104-6147.149" - cell $eq $eq$ls180.v:6147$1649 + attribute \src "ls180.v:6199.104-6199.149" + cell $eq $eq$ls180.v:6199$1715 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251975,10 +252843,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10100 - connect \Y $eq$ls180.v:6147$1649_Y + connect \Y $eq$ls180.v:6199$1715_Y end - attribute \src "ls180.v:6148.107-6148.152" - cell $eq $eq$ls180.v:6148$1653 + attribute \src "ls180.v:6200.107-6200.152" + cell $eq $eq$ls180.v:6200$1719 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251986,10 +252854,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10100 - connect \Y $eq$ls180.v:6148$1653_Y + connect \Y $eq$ls180.v:6200$1719_Y end - attribute \src "ls180.v:6150.104-6150.149" - cell $eq $eq$ls180.v:6150$1656 + attribute \src "ls180.v:6202.104-6202.149" + cell $eq $eq$ls180.v:6202$1722 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -251997,10 +252865,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10101 - connect \Y $eq$ls180.v:6150$1656_Y + connect \Y $eq$ls180.v:6202$1722_Y end - attribute \src "ls180.v:6151.107-6151.152" - cell $eq $eq$ls180.v:6151$1660 + attribute \src "ls180.v:6203.107-6203.152" + cell $eq $eq$ls180.v:6203$1726 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -252008,10 +252876,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10101 - connect \Y $eq$ls180.v:6151$1660_Y + connect \Y $eq$ls180.v:6203$1726_Y end - attribute \src "ls180.v:6153.104-6153.149" - cell $eq $eq$ls180.v:6153$1663 + attribute \src "ls180.v:6205.104-6205.149" + cell $eq $eq$ls180.v:6205$1729 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -252019,10 +252887,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10110 - connect \Y $eq$ls180.v:6153$1663_Y + connect \Y $eq$ls180.v:6205$1729_Y end - attribute \src "ls180.v:6154.107-6154.152" - cell $eq $eq$ls180.v:6154$1667 + attribute \src "ls180.v:6206.107-6206.152" + cell $eq $eq$ls180.v:6206$1733 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -252030,10 +252898,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10110 - connect \Y $eq$ls180.v:6154$1667_Y + connect \Y $eq$ls180.v:6206$1733_Y end - attribute \src "ls180.v:6156.104-6156.149" - cell $eq $eq$ls180.v:6156$1670 + attribute \src "ls180.v:6208.104-6208.149" + cell $eq $eq$ls180.v:6208$1736 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -252041,10 +252909,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10111 - connect \Y $eq$ls180.v:6156$1670_Y + connect \Y $eq$ls180.v:6208$1736_Y end - attribute \src "ls180.v:6157.107-6157.152" - cell $eq $eq$ls180.v:6157$1674 + attribute \src "ls180.v:6209.107-6209.152" + cell $eq $eq$ls180.v:6209$1740 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -252052,10 +252920,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10111 - connect \Y $eq$ls180.v:6157$1674_Y + connect \Y $eq$ls180.v:6209$1740_Y end - attribute \src "ls180.v:6159.104-6159.149" - cell $eq $eq$ls180.v:6159$1677 + attribute \src "ls180.v:6211.104-6211.149" + cell $eq $eq$ls180.v:6211$1743 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -252063,10 +252931,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11000 - connect \Y $eq$ls180.v:6159$1677_Y + connect \Y $eq$ls180.v:6211$1743_Y end - attribute \src "ls180.v:6160.107-6160.152" - cell $eq $eq$ls180.v:6160$1681 + attribute \src "ls180.v:6212.107-6212.152" + cell $eq $eq$ls180.v:6212$1747 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -252074,10 +252942,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11000 - connect \Y $eq$ls180.v:6160$1681_Y + connect \Y $eq$ls180.v:6212$1747_Y end - attribute \src "ls180.v:6162.100-6162.145" - cell $eq $eq$ls180.v:6162$1684 + attribute \src "ls180.v:6214.100-6214.145" + cell $eq $eq$ls180.v:6214$1750 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -252085,10 +252953,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11001 - connect \Y $eq$ls180.v:6162$1684_Y + connect \Y $eq$ls180.v:6214$1750_Y end - attribute \src "ls180.v:6163.103-6163.148" - cell $eq $eq$ls180.v:6163$1688 + attribute \src "ls180.v:6215.103-6215.148" + cell $eq $eq$ls180.v:6215$1754 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -252096,10 +252964,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11001 - connect \Y $eq$ls180.v:6163$1688_Y + connect \Y $eq$ls180.v:6215$1754_Y end - attribute \src "ls180.v:6165.101-6165.146" - cell $eq $eq$ls180.v:6165$1691 + attribute \src "ls180.v:6217.101-6217.146" + cell $eq $eq$ls180.v:6217$1757 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -252107,10 +252975,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11010 - connect \Y $eq$ls180.v:6165$1691_Y + connect \Y $eq$ls180.v:6217$1757_Y end - attribute \src "ls180.v:6166.104-6166.149" - cell $eq $eq$ls180.v:6166$1695 + attribute \src "ls180.v:6218.104-6218.149" + cell $eq $eq$ls180.v:6218$1761 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -252118,10 +252986,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11010 - connect \Y $eq$ls180.v:6166$1695_Y + connect \Y $eq$ls180.v:6218$1761_Y end - attribute \src "ls180.v:6168.104-6168.149" - cell $eq $eq$ls180.v:6168$1698 + attribute \src "ls180.v:6220.104-6220.149" + cell $eq $eq$ls180.v:6220$1764 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -252129,10 +252997,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11011 - connect \Y $eq$ls180.v:6168$1698_Y + connect \Y $eq$ls180.v:6220$1764_Y end - attribute \src "ls180.v:6169.107-6169.152" - cell $eq $eq$ls180.v:6169$1702 + attribute \src "ls180.v:6221.107-6221.152" + cell $eq $eq$ls180.v:6221$1768 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -252140,10 +253008,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11011 - connect \Y $eq$ls180.v:6169$1702_Y + connect \Y $eq$ls180.v:6221$1768_Y end - attribute \src "ls180.v:6171.104-6171.149" - cell $eq $eq$ls180.v:6171$1705 + attribute \src "ls180.v:6223.104-6223.149" + cell $eq $eq$ls180.v:6223$1771 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -252151,10 +253019,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11100 - connect \Y $eq$ls180.v:6171$1705_Y + connect \Y $eq$ls180.v:6223$1771_Y end - attribute \src "ls180.v:6172.107-6172.152" - cell $eq $eq$ls180.v:6172$1709 + attribute \src "ls180.v:6224.107-6224.152" + cell $eq $eq$ls180.v:6224$1775 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -252162,10 +253030,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11100 - connect \Y $eq$ls180.v:6172$1709_Y + connect \Y $eq$ls180.v:6224$1775_Y end - attribute \src "ls180.v:6174.103-6174.148" - cell $eq $eq$ls180.v:6174$1712 + attribute \src "ls180.v:6226.103-6226.148" + cell $eq $eq$ls180.v:6226$1778 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -252173,10 +253041,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11101 - connect \Y $eq$ls180.v:6174$1712_Y + connect \Y $eq$ls180.v:6226$1778_Y end - attribute \src "ls180.v:6175.106-6175.151" - cell $eq $eq$ls180.v:6175$1716 + attribute \src "ls180.v:6227.106-6227.151" + cell $eq $eq$ls180.v:6227$1782 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -252184,10 +253052,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11101 - connect \Y $eq$ls180.v:6175$1716_Y + connect \Y $eq$ls180.v:6227$1782_Y end - attribute \src "ls180.v:6177.103-6177.148" - cell $eq $eq$ls180.v:6177$1719 + attribute \src "ls180.v:6229.103-6229.148" + cell $eq $eq$ls180.v:6229$1785 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -252195,10 +253063,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11110 - connect \Y $eq$ls180.v:6177$1719_Y + connect \Y $eq$ls180.v:6229$1785_Y end - attribute \src "ls180.v:6178.106-6178.151" - cell $eq $eq$ls180.v:6178$1723 + attribute \src "ls180.v:6230.106-6230.151" + cell $eq $eq$ls180.v:6230$1789 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -252206,10 +253074,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11110 - connect \Y $eq$ls180.v:6178$1723_Y + connect \Y $eq$ls180.v:6230$1789_Y end - attribute \src "ls180.v:6180.103-6180.148" - cell $eq $eq$ls180.v:6180$1726 + attribute \src "ls180.v:6232.103-6232.148" + cell $eq $eq$ls180.v:6232$1792 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -252217,10 +253085,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11111 - connect \Y $eq$ls180.v:6180$1726_Y + connect \Y $eq$ls180.v:6232$1792_Y end - attribute \src "ls180.v:6181.106-6181.151" - cell $eq $eq$ls180.v:6181$1730 + attribute \src "ls180.v:6233.106-6233.151" + cell $eq $eq$ls180.v:6233$1796 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -252228,10 +253096,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11111 - connect \Y $eq$ls180.v:6181$1730_Y + connect \Y $eq$ls180.v:6233$1796_Y end - attribute \src "ls180.v:6183.103-6183.148" - cell $eq $eq$ls180.v:6183$1733 + attribute \src "ls180.v:6235.103-6235.148" + cell $eq $eq$ls180.v:6235$1799 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -252239,10 +253107,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 6'100000 - connect \Y $eq$ls180.v:6183$1733_Y + connect \Y $eq$ls180.v:6235$1799_Y end - attribute \src "ls180.v:6184.106-6184.151" - cell $eq $eq$ls180.v:6184$1737 + attribute \src "ls180.v:6236.106-6236.151" + cell $eq $eq$ls180.v:6236$1803 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -252250,21 +253118,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 6'100000 - connect \Y $eq$ls180.v:6184$1737_Y + connect \Y $eq$ls180.v:6236$1803_Y end - attribute \src "ls180.v:6220.32-6220.78" - cell $eq $eq$ls180.v:6220$1739 + attribute \src "ls180.v:6272.32-6272.78" + cell $eq $eq$ls180.v:6272$1805 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 + parameter \B_WIDTH 5 parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [13:9] - connect \B 4'1111 - connect \Y $eq$ls180.v:6220$1739_Y + connect \A \builder_interface7_bank_bus_adr [13:8] + connect \B 5'10000 + connect \Y $eq$ls180.v:6272$1805_Y end - attribute \src "ls180.v:6222.100-6222.144" - cell $eq $eq$ls180.v:6222$1741 + attribute \src "ls180.v:6274.100-6274.144" + cell $eq $eq$ls180.v:6274$1807 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252272,10 +253140,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 1'0 - connect \Y $eq$ls180.v:6222$1741_Y + connect \Y $eq$ls180.v:6274$1807_Y end - attribute \src "ls180.v:6223.103-6223.147" - cell $eq $eq$ls180.v:6223$1745 + attribute \src "ls180.v:6275.103-6275.147" + cell $eq $eq$ls180.v:6275$1811 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252283,10 +253151,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 1'0 - connect \Y $eq$ls180.v:6223$1745_Y + connect \Y $eq$ls180.v:6275$1811_Y end - attribute \src "ls180.v:6225.100-6225.144" - cell $eq $eq$ls180.v:6225$1748 + attribute \src "ls180.v:6277.100-6277.144" + cell $eq $eq$ls180.v:6277$1814 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252294,10 +253162,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 1'1 - connect \Y $eq$ls180.v:6225$1748_Y + connect \Y $eq$ls180.v:6277$1814_Y end - attribute \src "ls180.v:6226.103-6226.147" - cell $eq $eq$ls180.v:6226$1752 + attribute \src "ls180.v:6278.103-6278.147" + cell $eq $eq$ls180.v:6278$1818 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252305,10 +253173,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 1'1 - connect \Y $eq$ls180.v:6226$1752_Y + connect \Y $eq$ls180.v:6278$1818_Y end - attribute \src "ls180.v:6228.100-6228.144" - cell $eq $eq$ls180.v:6228$1755 + attribute \src "ls180.v:6280.100-6280.144" + cell $eq $eq$ls180.v:6280$1821 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252316,10 +253184,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 2'10 - connect \Y $eq$ls180.v:6228$1755_Y + connect \Y $eq$ls180.v:6280$1821_Y end - attribute \src "ls180.v:6229.103-6229.147" - cell $eq $eq$ls180.v:6229$1759 + attribute \src "ls180.v:6281.103-6281.147" + cell $eq $eq$ls180.v:6281$1825 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252327,10 +253195,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 2'10 - connect \Y $eq$ls180.v:6229$1759_Y + connect \Y $eq$ls180.v:6281$1825_Y end - attribute \src "ls180.v:6231.100-6231.144" - cell $eq $eq$ls180.v:6231$1762 + attribute \src "ls180.v:6283.100-6283.144" + cell $eq $eq$ls180.v:6283$1828 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252338,10 +253206,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 2'11 - connect \Y $eq$ls180.v:6231$1762_Y + connect \Y $eq$ls180.v:6283$1828_Y end - attribute \src "ls180.v:6232.103-6232.147" - cell $eq $eq$ls180.v:6232$1766 + attribute \src "ls180.v:6284.103-6284.147" + cell $eq $eq$ls180.v:6284$1832 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252349,10 +253217,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 2'11 - connect \Y $eq$ls180.v:6232$1766_Y + connect \Y $eq$ls180.v:6284$1832_Y end - attribute \src "ls180.v:6234.100-6234.144" - cell $eq $eq$ls180.v:6234$1769 + attribute \src "ls180.v:6286.100-6286.144" + cell $eq $eq$ls180.v:6286$1835 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252360,10 +253228,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 3'100 - connect \Y $eq$ls180.v:6234$1769_Y + connect \Y $eq$ls180.v:6286$1835_Y end - attribute \src "ls180.v:6235.103-6235.147" - cell $eq $eq$ls180.v:6235$1773 + attribute \src "ls180.v:6287.103-6287.147" + cell $eq $eq$ls180.v:6287$1839 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252371,10 +253239,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 3'100 - connect \Y $eq$ls180.v:6235$1773_Y + connect \Y $eq$ls180.v:6287$1839_Y end - attribute \src "ls180.v:6237.100-6237.144" - cell $eq $eq$ls180.v:6237$1776 + attribute \src "ls180.v:6289.100-6289.144" + cell $eq $eq$ls180.v:6289$1842 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252382,10 +253250,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 3'101 - connect \Y $eq$ls180.v:6237$1776_Y + connect \Y $eq$ls180.v:6289$1842_Y end - attribute \src "ls180.v:6238.103-6238.147" - cell $eq $eq$ls180.v:6238$1780 + attribute \src "ls180.v:6290.103-6290.147" + cell $eq $eq$ls180.v:6290$1846 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252393,10 +253261,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 3'101 - connect \Y $eq$ls180.v:6238$1780_Y + connect \Y $eq$ls180.v:6290$1846_Y end - attribute \src "ls180.v:6240.100-6240.144" - cell $eq $eq$ls180.v:6240$1783 + attribute \src "ls180.v:6292.100-6292.144" + cell $eq $eq$ls180.v:6292$1849 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252404,10 +253272,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 3'110 - connect \Y $eq$ls180.v:6240$1783_Y + connect \Y $eq$ls180.v:6292$1849_Y end - attribute \src "ls180.v:6241.103-6241.147" - cell $eq $eq$ls180.v:6241$1787 + attribute \src "ls180.v:6293.103-6293.147" + cell $eq $eq$ls180.v:6293$1853 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252415,10 +253283,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 3'110 - connect \Y $eq$ls180.v:6241$1787_Y + connect \Y $eq$ls180.v:6293$1853_Y end - attribute \src "ls180.v:6243.100-6243.144" - cell $eq $eq$ls180.v:6243$1790 + attribute \src "ls180.v:6295.100-6295.144" + cell $eq $eq$ls180.v:6295$1856 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252426,10 +253294,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 3'111 - connect \Y $eq$ls180.v:6243$1790_Y + connect \Y $eq$ls180.v:6295$1856_Y end - attribute \src "ls180.v:6244.103-6244.147" - cell $eq $eq$ls180.v:6244$1794 + attribute \src "ls180.v:6296.103-6296.147" + cell $eq $eq$ls180.v:6296$1860 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252437,10 +253305,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 3'111 - connect \Y $eq$ls180.v:6244$1794_Y + connect \Y $eq$ls180.v:6296$1860_Y end - attribute \src "ls180.v:6246.102-6246.146" - cell $eq $eq$ls180.v:6246$1797 + attribute \src "ls180.v:6298.102-6298.146" + cell $eq $eq$ls180.v:6298$1863 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252448,10 +253316,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6246$1797_Y + connect \Y $eq$ls180.v:6298$1863_Y end - attribute \src "ls180.v:6247.105-6247.149" - cell $eq $eq$ls180.v:6247$1801 + attribute \src "ls180.v:6299.105-6299.149" + cell $eq $eq$ls180.v:6299$1867 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252459,10 +253327,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6247$1801_Y + connect \Y $eq$ls180.v:6299$1867_Y end - attribute \src "ls180.v:6249.102-6249.146" - cell $eq $eq$ls180.v:6249$1804 + attribute \src "ls180.v:6301.102-6301.146" + cell $eq $eq$ls180.v:6301$1870 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252470,10 +253338,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1001 - connect \Y $eq$ls180.v:6249$1804_Y + connect \Y $eq$ls180.v:6301$1870_Y end - attribute \src "ls180.v:6250.105-6250.149" - cell $eq $eq$ls180.v:6250$1808 + attribute \src "ls180.v:6302.105-6302.149" + cell $eq $eq$ls180.v:6302$1874 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252481,10 +253349,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1001 - connect \Y $eq$ls180.v:6250$1808_Y + connect \Y $eq$ls180.v:6302$1874_Y end - attribute \src "ls180.v:6252.102-6252.147" - cell $eq $eq$ls180.v:6252$1811 + attribute \src "ls180.v:6304.102-6304.147" + cell $eq $eq$ls180.v:6304$1877 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252492,10 +253360,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1010 - connect \Y $eq$ls180.v:6252$1811_Y + connect \Y $eq$ls180.v:6304$1877_Y end - attribute \src "ls180.v:6253.105-6253.150" - cell $eq $eq$ls180.v:6253$1815 + attribute \src "ls180.v:6305.105-6305.150" + cell $eq $eq$ls180.v:6305$1881 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252503,10 +253371,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1010 - connect \Y $eq$ls180.v:6253$1815_Y + connect \Y $eq$ls180.v:6305$1881_Y end - attribute \src "ls180.v:6255.102-6255.147" - cell $eq $eq$ls180.v:6255$1818 + attribute \src "ls180.v:6307.102-6307.147" + cell $eq $eq$ls180.v:6307$1884 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252514,10 +253382,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1011 - connect \Y $eq$ls180.v:6255$1818_Y + connect \Y $eq$ls180.v:6307$1884_Y end - attribute \src "ls180.v:6256.105-6256.150" - cell $eq $eq$ls180.v:6256$1822 + attribute \src "ls180.v:6308.105-6308.150" + cell $eq $eq$ls180.v:6308$1888 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252525,10 +253393,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1011 - connect \Y $eq$ls180.v:6256$1822_Y + connect \Y $eq$ls180.v:6308$1888_Y end - attribute \src "ls180.v:6258.102-6258.147" - cell $eq $eq$ls180.v:6258$1825 + attribute \src "ls180.v:6310.102-6310.147" + cell $eq $eq$ls180.v:6310$1891 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252536,10 +253404,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1100 - connect \Y $eq$ls180.v:6258$1825_Y + connect \Y $eq$ls180.v:6310$1891_Y end - attribute \src "ls180.v:6259.105-6259.150" - cell $eq $eq$ls180.v:6259$1829 + attribute \src "ls180.v:6311.105-6311.150" + cell $eq $eq$ls180.v:6311$1895 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252547,10 +253415,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1100 - connect \Y $eq$ls180.v:6259$1829_Y + connect \Y $eq$ls180.v:6311$1895_Y end - attribute \src "ls180.v:6261.99-6261.144" - cell $eq $eq$ls180.v:6261$1832 + attribute \src "ls180.v:6313.99-6313.144" + cell $eq $eq$ls180.v:6313$1898 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252558,10 +253426,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1101 - connect \Y $eq$ls180.v:6261$1832_Y + connect \Y $eq$ls180.v:6313$1898_Y end - attribute \src "ls180.v:6262.102-6262.147" - cell $eq $eq$ls180.v:6262$1836 + attribute \src "ls180.v:6314.102-6314.147" + cell $eq $eq$ls180.v:6314$1902 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252569,10 +253437,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1101 - connect \Y $eq$ls180.v:6262$1836_Y + connect \Y $eq$ls180.v:6314$1902_Y end - attribute \src "ls180.v:6264.100-6264.145" - cell $eq $eq$ls180.v:6264$1839 + attribute \src "ls180.v:6316.100-6316.145" + cell $eq $eq$ls180.v:6316$1905 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252580,10 +253448,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1110 - connect \Y $eq$ls180.v:6264$1839_Y + connect \Y $eq$ls180.v:6316$1905_Y end - attribute \src "ls180.v:6265.103-6265.148" - cell $eq $eq$ls180.v:6265$1843 + attribute \src "ls180.v:6317.103-6317.148" + cell $eq $eq$ls180.v:6317$1909 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252591,10 +253459,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1110 - connect \Y $eq$ls180.v:6265$1843_Y + connect \Y $eq$ls180.v:6317$1909_Y end - attribute \src "ls180.v:6267.102-6267.147" - cell $eq $eq$ls180.v:6267$1846 + attribute \src "ls180.v:6319.102-6319.147" + cell $eq $eq$ls180.v:6319$1912 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252602,10 +253470,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1111 - connect \Y $eq$ls180.v:6267$1846_Y + connect \Y $eq$ls180.v:6319$1912_Y end - attribute \src "ls180.v:6268.105-6268.150" - cell $eq $eq$ls180.v:6268$1850 + attribute \src "ls180.v:6320.105-6320.150" + cell $eq $eq$ls180.v:6320$1916 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252613,10 +253481,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1111 - connect \Y $eq$ls180.v:6268$1850_Y + connect \Y $eq$ls180.v:6320$1916_Y end - attribute \src "ls180.v:6270.102-6270.147" - cell $eq $eq$ls180.v:6270$1853 + attribute \src "ls180.v:6322.102-6322.147" + cell $eq $eq$ls180.v:6322$1919 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252624,10 +253492,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 5'10000 - connect \Y $eq$ls180.v:6270$1853_Y + connect \Y $eq$ls180.v:6322$1919_Y end - attribute \src "ls180.v:6271.105-6271.150" - cell $eq $eq$ls180.v:6271$1857 + attribute \src "ls180.v:6323.105-6323.150" + cell $eq $eq$ls180.v:6323$1923 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252635,10 +253503,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 5'10000 - connect \Y $eq$ls180.v:6271$1857_Y + connect \Y $eq$ls180.v:6323$1923_Y end - attribute \src "ls180.v:6273.102-6273.147" - cell $eq $eq$ls180.v:6273$1860 + attribute \src "ls180.v:6325.102-6325.147" + cell $eq $eq$ls180.v:6325$1926 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252646,10 +253514,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 5'10001 - connect \Y $eq$ls180.v:6273$1860_Y + connect \Y $eq$ls180.v:6325$1926_Y end - attribute \src "ls180.v:6274.105-6274.150" - cell $eq $eq$ls180.v:6274$1864 + attribute \src "ls180.v:6326.105-6326.150" + cell $eq $eq$ls180.v:6326$1930 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252657,10 +253525,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 5'10001 - connect \Y $eq$ls180.v:6274$1864_Y + connect \Y $eq$ls180.v:6326$1930_Y end - attribute \src "ls180.v:6276.102-6276.147" - cell $eq $eq$ls180.v:6276$1867 + attribute \src "ls180.v:6328.102-6328.147" + cell $eq $eq$ls180.v:6328$1933 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252668,10 +253536,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 5'10010 - connect \Y $eq$ls180.v:6276$1867_Y + connect \Y $eq$ls180.v:6328$1933_Y end - attribute \src "ls180.v:6277.105-6277.150" - cell $eq $eq$ls180.v:6277$1871 + attribute \src "ls180.v:6329.105-6329.150" + cell $eq $eq$ls180.v:6329$1937 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -252679,21 +253547,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 5'10010 - connect \Y $eq$ls180.v:6277$1871_Y + connect \Y $eq$ls180.v:6329$1937_Y end - attribute \src "ls180.v:6299.32-6299.78" - cell $eq $eq$ls180.v:6299$1873 + attribute \src "ls180.v:6351.32-6351.78" + cell $eq $eq$ls180.v:6351$1939 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_adr [13:9] - connect \B 4'1100 - connect \Y $eq$ls180.v:6299$1873_Y + connect \A \builder_interface8_bank_bus_adr [13:8] + connect \B 4'1101 + connect \Y $eq$ls180.v:6351$1939_Y end - attribute \src "ls180.v:6301.102-6301.146" - cell $eq $eq$ls180.v:6301$1875 + attribute \src "ls180.v:6353.102-6353.146" + cell $eq $eq$ls180.v:6353$1941 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -252701,10 +253569,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_adr [1:0] connect \B 1'0 - connect \Y $eq$ls180.v:6301$1875_Y + connect \Y $eq$ls180.v:6353$1941_Y end - attribute \src "ls180.v:6302.105-6302.149" - cell $eq $eq$ls180.v:6302$1879 + attribute \src "ls180.v:6354.105-6354.149" + cell $eq $eq$ls180.v:6354$1945 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -252712,10 +253580,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_adr [1:0] connect \B 1'0 - connect \Y $eq$ls180.v:6302$1879_Y + connect \Y $eq$ls180.v:6354$1945_Y end - attribute \src "ls180.v:6304.107-6304.151" - cell $eq $eq$ls180.v:6304$1882 + attribute \src "ls180.v:6356.107-6356.151" + cell $eq $eq$ls180.v:6356$1948 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -252723,10 +253591,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_adr [1:0] connect \B 1'1 - connect \Y $eq$ls180.v:6304$1882_Y + connect \Y $eq$ls180.v:6356$1948_Y end - attribute \src "ls180.v:6305.110-6305.154" - cell $eq $eq$ls180.v:6305$1886 + attribute \src "ls180.v:6357.110-6357.154" + cell $eq $eq$ls180.v:6357$1952 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -252734,10 +253602,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_adr [1:0] connect \B 1'1 - connect \Y $eq$ls180.v:6305$1886_Y + connect \Y $eq$ls180.v:6357$1952_Y end - attribute \src "ls180.v:6307.107-6307.151" - cell $eq $eq$ls180.v:6307$1889 + attribute \src "ls180.v:6359.107-6359.151" + cell $eq $eq$ls180.v:6359$1955 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -252745,10 +253613,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_adr [1:0] connect \B 2'10 - connect \Y $eq$ls180.v:6307$1889_Y + connect \Y $eq$ls180.v:6359$1955_Y end - attribute \src "ls180.v:6308.110-6308.154" - cell $eq $eq$ls180.v:6308$1893 + attribute \src "ls180.v:6360.110-6360.154" + cell $eq $eq$ls180.v:6360$1959 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -252756,10 +253624,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_adr [1:0] connect \B 2'10 - connect \Y $eq$ls180.v:6308$1893_Y + connect \Y $eq$ls180.v:6360$1959_Y end - attribute \src "ls180.v:6310.100-6310.144" - cell $eq $eq$ls180.v:6310$1896 + attribute \src "ls180.v:6362.100-6362.144" + cell $eq $eq$ls180.v:6362$1962 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -252767,10 +253635,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_adr [1:0] connect \B 2'11 - connect \Y $eq$ls180.v:6310$1896_Y + connect \Y $eq$ls180.v:6362$1962_Y end - attribute \src "ls180.v:6311.103-6311.147" - cell $eq $eq$ls180.v:6311$1900 + attribute \src "ls180.v:6363.103-6363.147" + cell $eq $eq$ls180.v:6363$1966 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -252778,21 +253646,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_adr [1:0] connect \B 2'11 - connect \Y $eq$ls180.v:6311$1900_Y + connect \Y $eq$ls180.v:6363$1966_Y end - attribute \src "ls180.v:6316.32-6316.77" - cell $eq $eq$ls180.v:6316$1902 + attribute \src "ls180.v:6368.32-6368.77" + cell $eq $eq$ls180.v:6368$1968 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [13:9] + connect \A \builder_interface9_bank_bus_adr [13:8] connect \B 2'11 - connect \Y $eq$ls180.v:6316$1902_Y + connect \Y $eq$ls180.v:6368$1968_Y end - attribute \src "ls180.v:6318.104-6318.148" - cell $eq $eq$ls180.v:6318$1904 + attribute \src "ls180.v:6370.104-6370.148" + cell $eq $eq$ls180.v:6370$1970 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -252800,10 +253668,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:6318$1904_Y + connect \Y $eq$ls180.v:6370$1970_Y end - attribute \src "ls180.v:6319.107-6319.151" - cell $eq $eq$ls180.v:6319$1908 + attribute \src "ls180.v:6371.107-6371.151" + cell $eq $eq$ls180.v:6371$1974 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -252811,10 +253679,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:6319$1908_Y + connect \Y $eq$ls180.v:6371$1974_Y end - attribute \src "ls180.v:6321.108-6321.152" - cell $eq $eq$ls180.v:6321$1911 + attribute \src "ls180.v:6373.108-6373.152" + cell $eq $eq$ls180.v:6373$1977 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -252822,10 +253690,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:6321$1911_Y + connect \Y $eq$ls180.v:6373$1977_Y end - attribute \src "ls180.v:6322.111-6322.155" - cell $eq $eq$ls180.v:6322$1915 + attribute \src "ls180.v:6374.111-6374.155" + cell $eq $eq$ls180.v:6374$1981 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -252833,10 +253701,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:6322$1915_Y + connect \Y $eq$ls180.v:6374$1981_Y end - attribute \src "ls180.v:6324.98-6324.142" - cell $eq $eq$ls180.v:6324$1918 + attribute \src "ls180.v:6376.98-6376.142" + cell $eq $eq$ls180.v:6376$1984 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -252844,10 +253712,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:6324$1918_Y + connect \Y $eq$ls180.v:6376$1984_Y end - attribute \src "ls180.v:6325.101-6325.145" - cell $eq $eq$ls180.v:6325$1922 + attribute \src "ls180.v:6377.101-6377.145" + cell $eq $eq$ls180.v:6377$1988 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -252855,10 +253723,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:6325$1922_Y + connect \Y $eq$ls180.v:6377$1988_Y end - attribute \src "ls180.v:6327.108-6327.152" - cell $eq $eq$ls180.v:6327$1925 + attribute \src "ls180.v:6379.108-6379.152" + cell $eq $eq$ls180.v:6379$1991 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -252866,10 +253734,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:6327$1925_Y + connect \Y $eq$ls180.v:6379$1991_Y end - attribute \src "ls180.v:6328.111-6328.155" - cell $eq $eq$ls180.v:6328$1929 + attribute \src "ls180.v:6380.111-6380.155" + cell $eq $eq$ls180.v:6380$1995 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -252877,10 +253745,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:6328$1929_Y + connect \Y $eq$ls180.v:6380$1995_Y end - attribute \src "ls180.v:6330.108-6330.152" - cell $eq $eq$ls180.v:6330$1932 + attribute \src "ls180.v:6382.108-6382.152" + cell $eq $eq$ls180.v:6382$1998 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -252888,10 +253756,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:6330$1932_Y + connect \Y $eq$ls180.v:6382$1998_Y end - attribute \src "ls180.v:6331.111-6331.155" - cell $eq $eq$ls180.v:6331$1936 + attribute \src "ls180.v:6383.111-6383.155" + cell $eq $eq$ls180.v:6383$2002 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -252899,10 +253767,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:6331$1936_Y + connect \Y $eq$ls180.v:6383$2002_Y end - attribute \src "ls180.v:6333.109-6333.153" - cell $eq $eq$ls180.v:6333$1939 + attribute \src "ls180.v:6385.109-6385.153" + cell $eq $eq$ls180.v:6385$2005 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -252910,10 +253778,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:6333$1939_Y + connect \Y $eq$ls180.v:6385$2005_Y end - attribute \src "ls180.v:6334.112-6334.156" - cell $eq $eq$ls180.v:6334$1943 + attribute \src "ls180.v:6386.112-6386.156" + cell $eq $eq$ls180.v:6386$2009 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -252921,10 +253789,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:6334$1943_Y + connect \Y $eq$ls180.v:6386$2009_Y end - attribute \src "ls180.v:6336.107-6336.151" - cell $eq $eq$ls180.v:6336$1946 + attribute \src "ls180.v:6388.107-6388.151" + cell $eq $eq$ls180.v:6388$2012 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -252932,10 +253800,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:6336$1946_Y + connect \Y $eq$ls180.v:6388$2012_Y end - attribute \src "ls180.v:6337.110-6337.154" - cell $eq $eq$ls180.v:6337$1950 + attribute \src "ls180.v:6389.110-6389.154" + cell $eq $eq$ls180.v:6389$2016 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -252943,10 +253811,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:6337$1950_Y + connect \Y $eq$ls180.v:6389$2016_Y end - attribute \src "ls180.v:6339.107-6339.151" - cell $eq $eq$ls180.v:6339$1953 + attribute \src "ls180.v:6391.107-6391.151" + cell $eq $eq$ls180.v:6391$2019 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -252954,10 +253822,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:6339$1953_Y + connect \Y $eq$ls180.v:6391$2019_Y end - attribute \src "ls180.v:6340.110-6340.154" - cell $eq $eq$ls180.v:6340$1957 + attribute \src "ls180.v:6392.110-6392.154" + cell $eq $eq$ls180.v:6392$2023 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -252965,10 +253833,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:6340$1957_Y + connect \Y $eq$ls180.v:6392$2023_Y end - attribute \src "ls180.v:6342.107-6342.151" - cell $eq $eq$ls180.v:6342$1960 + attribute \src "ls180.v:6394.107-6394.151" + cell $eq $eq$ls180.v:6394$2026 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -252976,10 +253844,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6342$1960_Y + connect \Y $eq$ls180.v:6394$2026_Y end - attribute \src "ls180.v:6343.110-6343.154" - cell $eq $eq$ls180.v:6343$1964 + attribute \src "ls180.v:6395.110-6395.154" + cell $eq $eq$ls180.v:6395$2030 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -252987,10 +253855,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6343$1964_Y + connect \Y $eq$ls180.v:6395$2030_Y end - attribute \src "ls180.v:6345.107-6345.151" - cell $eq $eq$ls180.v:6345$1967 + attribute \src "ls180.v:6397.107-6397.151" + cell $eq $eq$ls180.v:6397$2033 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -252998,10 +253866,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 4'1001 - connect \Y $eq$ls180.v:6345$1967_Y + connect \Y $eq$ls180.v:6397$2033_Y end - attribute \src "ls180.v:6346.110-6346.154" - cell $eq $eq$ls180.v:6346$1971 + attribute \src "ls180.v:6398.110-6398.154" + cell $eq $eq$ls180.v:6398$2037 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -253009,21 +253877,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 4'1001 - connect \Y $eq$ls180.v:6346$1971_Y + connect \Y $eq$ls180.v:6398$2037_Y end - attribute \src "ls180.v:6361.33-6361.79" - cell $eq $eq$ls180.v:6361$1973 + attribute \src "ls180.v:6413.33-6413.79" + cell $eq $eq$ls180.v:6413$2039 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 + parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [13:9] - connect \B 3'111 - connect \Y $eq$ls180.v:6361$1973_Y + connect \A \builder_interface10_bank_bus_adr [13:8] + connect \B 4'1000 + connect \Y $eq$ls180.v:6413$2039_Y end - attribute \src "ls180.v:6363.102-6363.147" - cell $eq $eq$ls180.v:6363$1975 + attribute \src "ls180.v:6415.102-6415.147" + cell $eq $eq$ls180.v:6415$2041 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -253031,10 +253899,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [2:0] connect \B 1'0 - connect \Y $eq$ls180.v:6363$1975_Y + connect \Y $eq$ls180.v:6415$2041_Y end - attribute \src "ls180.v:6364.105-6364.150" - cell $eq $eq$ls180.v:6364$1979 + attribute \src "ls180.v:6416.105-6416.150" + cell $eq $eq$ls180.v:6416$2045 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -253042,10 +253910,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [2:0] connect \B 1'0 - connect \Y $eq$ls180.v:6364$1979_Y + connect \Y $eq$ls180.v:6416$2045_Y end - attribute \src "ls180.v:6366.102-6366.147" - cell $eq $eq$ls180.v:6366$1982 + attribute \src "ls180.v:6418.102-6418.147" + cell $eq $eq$ls180.v:6418$2048 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -253053,10 +253921,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [2:0] connect \B 1'1 - connect \Y $eq$ls180.v:6366$1982_Y + connect \Y $eq$ls180.v:6418$2048_Y end - attribute \src "ls180.v:6367.105-6367.150" - cell $eq $eq$ls180.v:6367$1986 + attribute \src "ls180.v:6419.105-6419.150" + cell $eq $eq$ls180.v:6419$2052 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -253064,10 +253932,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [2:0] connect \B 1'1 - connect \Y $eq$ls180.v:6367$1986_Y + connect \Y $eq$ls180.v:6419$2052_Y end - attribute \src "ls180.v:6369.100-6369.145" - cell $eq $eq$ls180.v:6369$1989 + attribute \src "ls180.v:6421.100-6421.145" + cell $eq $eq$ls180.v:6421$2055 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -253075,10 +253943,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [2:0] connect \B 2'10 - connect \Y $eq$ls180.v:6369$1989_Y + connect \Y $eq$ls180.v:6421$2055_Y end - attribute \src "ls180.v:6370.103-6370.148" - cell $eq $eq$ls180.v:6370$1993 + attribute \src "ls180.v:6422.103-6422.148" + cell $eq $eq$ls180.v:6422$2059 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -253086,10 +253954,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [2:0] connect \B 2'10 - connect \Y $eq$ls180.v:6370$1993_Y + connect \Y $eq$ls180.v:6422$2059_Y end - attribute \src "ls180.v:6372.99-6372.144" - cell $eq $eq$ls180.v:6372$1996 + attribute \src "ls180.v:6424.99-6424.144" + cell $eq $eq$ls180.v:6424$2062 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -253097,10 +253965,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [2:0] connect \B 2'11 - connect \Y $eq$ls180.v:6372$1996_Y + connect \Y $eq$ls180.v:6424$2062_Y end - attribute \src "ls180.v:6373.102-6373.147" - cell $eq $eq$ls180.v:6373$2000 + attribute \src "ls180.v:6425.102-6425.147" + cell $eq $eq$ls180.v:6425$2066 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -253108,10 +253976,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [2:0] connect \B 2'11 - connect \Y $eq$ls180.v:6373$2000_Y + connect \Y $eq$ls180.v:6425$2066_Y end - attribute \src "ls180.v:6375.98-6375.143" - cell $eq $eq$ls180.v:6375$2003 + attribute \src "ls180.v:6427.98-6427.143" + cell $eq $eq$ls180.v:6427$2069 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -253119,10 +253987,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [2:0] connect \B 3'100 - connect \Y $eq$ls180.v:6375$2003_Y + connect \Y $eq$ls180.v:6427$2069_Y end - attribute \src "ls180.v:6376.101-6376.146" - cell $eq $eq$ls180.v:6376$2007 + attribute \src "ls180.v:6428.101-6428.146" + cell $eq $eq$ls180.v:6428$2073 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -253130,10 +253998,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [2:0] connect \B 3'100 - connect \Y $eq$ls180.v:6376$2007_Y + connect \Y $eq$ls180.v:6428$2073_Y end - attribute \src "ls180.v:6378.97-6378.142" - cell $eq $eq$ls180.v:6378$2010 + attribute \src "ls180.v:6430.97-6430.142" + cell $eq $eq$ls180.v:6430$2076 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -253141,10 +254009,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [2:0] connect \B 3'101 - connect \Y $eq$ls180.v:6378$2010_Y + connect \Y $eq$ls180.v:6430$2076_Y end - attribute \src "ls180.v:6379.100-6379.145" - cell $eq $eq$ls180.v:6379$2014 + attribute \src "ls180.v:6431.100-6431.145" + cell $eq $eq$ls180.v:6431$2080 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -253152,10 +254020,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [2:0] connect \B 3'101 - connect \Y $eq$ls180.v:6379$2014_Y + connect \Y $eq$ls180.v:6431$2080_Y end - attribute \src "ls180.v:6381.103-6381.148" - cell $eq $eq$ls180.v:6381$2017 + attribute \src "ls180.v:6433.103-6433.148" + cell $eq $eq$ls180.v:6433$2083 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -253163,10 +254031,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [2:0] connect \B 3'110 - connect \Y $eq$ls180.v:6381$2017_Y + connect \Y $eq$ls180.v:6433$2083_Y end - attribute \src "ls180.v:6382.106-6382.151" - cell $eq $eq$ls180.v:6382$2021 + attribute \src "ls180.v:6434.106-6434.151" + cell $eq $eq$ls180.v:6434$2087 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -253174,21 +254042,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [2:0] connect \B 3'110 - connect \Y $eq$ls180.v:6382$2021_Y + connect \Y $eq$ls180.v:6434$2087_Y end - attribute \src "ls180.v:6401.33-6401.79" - cell $eq $eq$ls180.v:6401$2024 + attribute \src "ls180.v:6453.33-6453.79" + cell $eq $eq$ls180.v:6453$2090 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [13:9] - connect \B 4'1000 - connect \Y $eq$ls180.v:6401$2024_Y + connect \A \builder_interface11_bank_bus_adr [13:8] + connect \B 4'1001 + connect \Y $eq$ls180.v:6453$2090_Y end - attribute \src "ls180.v:6403.102-6403.147" - cell $eq $eq$ls180.v:6403$2026 + attribute \src "ls180.v:6455.102-6455.147" + cell $eq $eq$ls180.v:6455$2092 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -253196,10 +254064,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:6403$2026_Y + connect \Y $eq$ls180.v:6455$2092_Y end - attribute \src "ls180.v:6404.105-6404.150" - cell $eq $eq$ls180.v:6404$2030 + attribute \src "ls180.v:6456.105-6456.150" + cell $eq $eq$ls180.v:6456$2096 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -253207,10 +254075,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:6404$2030_Y + connect \Y $eq$ls180.v:6456$2096_Y end - attribute \src "ls180.v:6406.102-6406.147" - cell $eq $eq$ls180.v:6406$2033 + attribute \src "ls180.v:6458.102-6458.147" + cell $eq $eq$ls180.v:6458$2099 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -253218,10 +254086,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:6406$2033_Y + connect \Y $eq$ls180.v:6458$2099_Y end - attribute \src "ls180.v:6407.105-6407.150" - cell $eq $eq$ls180.v:6407$2037 + attribute \src "ls180.v:6459.105-6459.150" + cell $eq $eq$ls180.v:6459$2103 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -253229,10 +254097,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:6407$2037_Y + connect \Y $eq$ls180.v:6459$2103_Y end - attribute \src "ls180.v:6409.100-6409.145" - cell $eq $eq$ls180.v:6409$2040 + attribute \src "ls180.v:6461.100-6461.145" + cell $eq $eq$ls180.v:6461$2106 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -253240,10 +254108,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:6409$2040_Y + connect \Y $eq$ls180.v:6461$2106_Y end - attribute \src "ls180.v:6410.103-6410.148" - cell $eq $eq$ls180.v:6410$2044 + attribute \src "ls180.v:6462.103-6462.148" + cell $eq $eq$ls180.v:6462$2110 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -253251,10 +254119,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:6410$2044_Y + connect \Y $eq$ls180.v:6462$2110_Y end - attribute \src "ls180.v:6412.99-6412.144" - cell $eq $eq$ls180.v:6412$2047 + attribute \src "ls180.v:6464.99-6464.144" + cell $eq $eq$ls180.v:6464$2113 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -253262,10 +254130,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:6412$2047_Y + connect \Y $eq$ls180.v:6464$2113_Y end - attribute \src "ls180.v:6413.102-6413.147" - cell $eq $eq$ls180.v:6413$2051 + attribute \src "ls180.v:6465.102-6465.147" + cell $eq $eq$ls180.v:6465$2117 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -253273,10 +254141,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:6413$2051_Y + connect \Y $eq$ls180.v:6465$2117_Y end - attribute \src "ls180.v:6415.98-6415.143" - cell $eq $eq$ls180.v:6415$2054 + attribute \src "ls180.v:6467.98-6467.143" + cell $eq $eq$ls180.v:6467$2120 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -253284,10 +254152,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:6415$2054_Y + connect \Y $eq$ls180.v:6467$2120_Y end - attribute \src "ls180.v:6416.101-6416.146" - cell $eq $eq$ls180.v:6416$2058 + attribute \src "ls180.v:6468.101-6468.146" + cell $eq $eq$ls180.v:6468$2124 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -253295,10 +254163,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:6416$2058_Y + connect \Y $eq$ls180.v:6468$2124_Y end - attribute \src "ls180.v:6418.97-6418.142" - cell $eq $eq$ls180.v:6418$2061 + attribute \src "ls180.v:6470.97-6470.142" + cell $eq $eq$ls180.v:6470$2127 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -253306,10 +254174,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:6418$2061_Y + connect \Y $eq$ls180.v:6470$2127_Y end - attribute \src "ls180.v:6419.100-6419.145" - cell $eq $eq$ls180.v:6419$2065 + attribute \src "ls180.v:6471.100-6471.145" + cell $eq $eq$ls180.v:6471$2131 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -253317,10 +254185,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:6419$2065_Y + connect \Y $eq$ls180.v:6471$2131_Y end - attribute \src "ls180.v:6421.103-6421.148" - cell $eq $eq$ls180.v:6421$2068 + attribute \src "ls180.v:6473.103-6473.148" + cell $eq $eq$ls180.v:6473$2134 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -253328,10 +254196,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:6421$2068_Y + connect \Y $eq$ls180.v:6473$2134_Y end - attribute \src "ls180.v:6422.106-6422.151" - cell $eq $eq$ls180.v:6422$2072 + attribute \src "ls180.v:6474.106-6474.151" + cell $eq $eq$ls180.v:6474$2138 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -253339,10 +254207,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:6422$2072_Y + connect \Y $eq$ls180.v:6474$2138_Y end - attribute \src "ls180.v:6424.106-6424.151" - cell $eq $eq$ls180.v:6424$2075 + attribute \src "ls180.v:6476.106-6476.151" + cell $eq $eq$ls180.v:6476$2141 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -253350,10 +254218,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:6424$2075_Y + connect \Y $eq$ls180.v:6476$2141_Y end - attribute \src "ls180.v:6425.109-6425.154" - cell $eq $eq$ls180.v:6425$2079 + attribute \src "ls180.v:6477.109-6477.154" + cell $eq $eq$ls180.v:6477$2145 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -253361,10 +254229,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:6425$2079_Y + connect \Y $eq$ls180.v:6477$2145_Y end - attribute \src "ls180.v:6427.106-6427.151" - cell $eq $eq$ls180.v:6427$2082 + attribute \src "ls180.v:6479.106-6479.151" + cell $eq $eq$ls180.v:6479$2148 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -253372,10 +254240,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6427$2082_Y + connect \Y $eq$ls180.v:6479$2148_Y end - attribute \src "ls180.v:6428.109-6428.154" - cell $eq $eq$ls180.v:6428$2086 + attribute \src "ls180.v:6480.109-6480.154" + cell $eq $eq$ls180.v:6480$2152 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -253383,21 +254251,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6428$2086_Y + connect \Y $eq$ls180.v:6480$2152_Y end - attribute \src "ls180.v:6449.33-6449.79" - cell $eq $eq$ls180.v:6449$2089 + attribute \src "ls180.v:6501.33-6501.79" + cell $eq $eq$ls180.v:6501$2155 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [13:9] + connect \A \builder_interface12_bank_bus_adr [13:8] connect \B 2'10 - connect \Y $eq$ls180.v:6449$2089_Y + connect \Y $eq$ls180.v:6501$2155_Y end - attribute \src "ls180.v:6451.99-6451.144" - cell $eq $eq$ls180.v:6451$2091 + attribute \src "ls180.v:6503.99-6503.144" + cell $eq $eq$ls180.v:6503$2157 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -253405,10 +254273,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 1'0 - connect \Y $eq$ls180.v:6451$2091_Y + connect \Y $eq$ls180.v:6503$2157_Y end - attribute \src "ls180.v:6452.102-6452.147" - cell $eq $eq$ls180.v:6452$2095 + attribute \src "ls180.v:6504.102-6504.147" + cell $eq $eq$ls180.v:6504$2161 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -253416,10 +254284,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 1'0 - connect \Y $eq$ls180.v:6452$2095_Y + connect \Y $eq$ls180.v:6504$2161_Y end - attribute \src "ls180.v:6454.99-6454.144" - cell $eq $eq$ls180.v:6454$2098 + attribute \src "ls180.v:6506.99-6506.144" + cell $eq $eq$ls180.v:6506$2164 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -253427,10 +254295,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 1'1 - connect \Y $eq$ls180.v:6454$2098_Y + connect \Y $eq$ls180.v:6506$2164_Y end - attribute \src "ls180.v:6455.102-6455.147" - cell $eq $eq$ls180.v:6455$2102 + attribute \src "ls180.v:6507.102-6507.147" + cell $eq $eq$ls180.v:6507$2168 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -253438,10 +254306,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 1'1 - connect \Y $eq$ls180.v:6455$2102_Y + connect \Y $eq$ls180.v:6507$2168_Y end - attribute \src "ls180.v:6457.99-6457.144" - cell $eq $eq$ls180.v:6457$2105 + attribute \src "ls180.v:6509.99-6509.144" + cell $eq $eq$ls180.v:6509$2171 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -253449,10 +254317,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 2'10 - connect \Y $eq$ls180.v:6457$2105_Y + connect \Y $eq$ls180.v:6509$2171_Y end - attribute \src "ls180.v:6458.102-6458.147" - cell $eq $eq$ls180.v:6458$2109 + attribute \src "ls180.v:6510.102-6510.147" + cell $eq $eq$ls180.v:6510$2175 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -253460,10 +254328,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 2'10 - connect \Y $eq$ls180.v:6458$2109_Y + connect \Y $eq$ls180.v:6510$2175_Y end - attribute \src "ls180.v:6460.99-6460.144" - cell $eq $eq$ls180.v:6460$2112 + attribute \src "ls180.v:6512.99-6512.144" + cell $eq $eq$ls180.v:6512$2178 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -253471,10 +254339,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 2'11 - connect \Y $eq$ls180.v:6460$2112_Y + connect \Y $eq$ls180.v:6512$2178_Y end - attribute \src "ls180.v:6461.102-6461.147" - cell $eq $eq$ls180.v:6461$2116 + attribute \src "ls180.v:6513.102-6513.147" + cell $eq $eq$ls180.v:6513$2182 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -253482,10 +254350,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 2'11 - connect \Y $eq$ls180.v:6461$2116_Y + connect \Y $eq$ls180.v:6513$2182_Y end - attribute \src "ls180.v:6463.101-6463.146" - cell $eq $eq$ls180.v:6463$2119 + attribute \src "ls180.v:6515.101-6515.146" + cell $eq $eq$ls180.v:6515$2185 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -253493,10 +254361,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 3'100 - connect \Y $eq$ls180.v:6463$2119_Y + connect \Y $eq$ls180.v:6515$2185_Y end - attribute \src "ls180.v:6464.104-6464.149" - cell $eq $eq$ls180.v:6464$2123 + attribute \src "ls180.v:6516.104-6516.149" + cell $eq $eq$ls180.v:6516$2189 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -253504,10 +254372,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 3'100 - connect \Y $eq$ls180.v:6464$2123_Y + connect \Y $eq$ls180.v:6516$2189_Y end - attribute \src "ls180.v:6466.101-6466.146" - cell $eq $eq$ls180.v:6466$2126 + attribute \src "ls180.v:6518.101-6518.146" + cell $eq $eq$ls180.v:6518$2192 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -253515,10 +254383,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 3'101 - connect \Y $eq$ls180.v:6466$2126_Y + connect \Y $eq$ls180.v:6518$2192_Y end - attribute \src "ls180.v:6467.104-6467.149" - cell $eq $eq$ls180.v:6467$2130 + attribute \src "ls180.v:6519.104-6519.149" + cell $eq $eq$ls180.v:6519$2196 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -253526,10 +254394,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 3'101 - connect \Y $eq$ls180.v:6467$2130_Y + connect \Y $eq$ls180.v:6519$2196_Y end - attribute \src "ls180.v:6469.101-6469.146" - cell $eq $eq$ls180.v:6469$2133 + attribute \src "ls180.v:6521.101-6521.146" + cell $eq $eq$ls180.v:6521$2199 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -253537,10 +254405,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 3'110 - connect \Y $eq$ls180.v:6469$2133_Y + connect \Y $eq$ls180.v:6521$2199_Y end - attribute \src "ls180.v:6470.104-6470.149" - cell $eq $eq$ls180.v:6470$2137 + attribute \src "ls180.v:6522.104-6522.149" + cell $eq $eq$ls180.v:6522$2203 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -253548,10 +254416,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 3'110 - connect \Y $eq$ls180.v:6470$2137_Y + connect \Y $eq$ls180.v:6522$2203_Y end - attribute \src "ls180.v:6472.101-6472.146" - cell $eq $eq$ls180.v:6472$2140 + attribute \src "ls180.v:6524.101-6524.146" + cell $eq $eq$ls180.v:6524$2206 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -253559,10 +254427,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 3'111 - connect \Y $eq$ls180.v:6472$2140_Y + connect \Y $eq$ls180.v:6524$2206_Y end - attribute \src "ls180.v:6473.104-6473.149" - cell $eq $eq$ls180.v:6473$2144 + attribute \src "ls180.v:6525.104-6525.149" + cell $eq $eq$ls180.v:6525$2210 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -253570,10 +254438,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 3'111 - connect \Y $eq$ls180.v:6473$2144_Y + connect \Y $eq$ls180.v:6525$2210_Y end - attribute \src "ls180.v:6475.97-6475.142" - cell $eq $eq$ls180.v:6475$2147 + attribute \src "ls180.v:6527.97-6527.142" + cell $eq $eq$ls180.v:6527$2213 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -253581,10 +254449,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6475$2147_Y + connect \Y $eq$ls180.v:6527$2213_Y end - attribute \src "ls180.v:6476.100-6476.145" - cell $eq $eq$ls180.v:6476$2151 + attribute \src "ls180.v:6528.100-6528.145" + cell $eq $eq$ls180.v:6528$2217 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -253592,10 +254460,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6476$2151_Y + connect \Y $eq$ls180.v:6528$2217_Y end - attribute \src "ls180.v:6478.107-6478.152" - cell $eq $eq$ls180.v:6478$2154 + attribute \src "ls180.v:6530.107-6530.152" + cell $eq $eq$ls180.v:6530$2220 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -253603,10 +254471,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1001 - connect \Y $eq$ls180.v:6478$2154_Y + connect \Y $eq$ls180.v:6530$2220_Y end - attribute \src "ls180.v:6479.110-6479.155" - cell $eq $eq$ls180.v:6479$2158 + attribute \src "ls180.v:6531.110-6531.155" + cell $eq $eq$ls180.v:6531$2224 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -253614,10 +254482,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1001 - connect \Y $eq$ls180.v:6479$2158_Y + connect \Y $eq$ls180.v:6531$2224_Y end - attribute \src "ls180.v:6481.100-6481.146" - cell $eq $eq$ls180.v:6481$2161 + attribute \src "ls180.v:6533.100-6533.146" + cell $eq $eq$ls180.v:6533$2227 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -253625,10 +254493,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1010 - connect \Y $eq$ls180.v:6481$2161_Y + connect \Y $eq$ls180.v:6533$2227_Y end - attribute \src "ls180.v:6482.103-6482.149" - cell $eq $eq$ls180.v:6482$2165 + attribute \src "ls180.v:6534.103-6534.149" + cell $eq $eq$ls180.v:6534$2231 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -253636,10 +254504,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1010 - connect \Y $eq$ls180.v:6482$2165_Y + connect \Y $eq$ls180.v:6534$2231_Y end - attribute \src "ls180.v:6484.100-6484.146" - cell $eq $eq$ls180.v:6484$2168 + attribute \src "ls180.v:6536.100-6536.146" + cell $eq $eq$ls180.v:6536$2234 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -253647,10 +254515,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1011 - connect \Y $eq$ls180.v:6484$2168_Y + connect \Y $eq$ls180.v:6536$2234_Y end - attribute \src "ls180.v:6485.103-6485.149" - cell $eq $eq$ls180.v:6485$2172 + attribute \src "ls180.v:6537.103-6537.149" + cell $eq $eq$ls180.v:6537$2238 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -253658,10 +254526,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1011 - connect \Y $eq$ls180.v:6485$2172_Y + connect \Y $eq$ls180.v:6537$2238_Y end - attribute \src "ls180.v:6487.100-6487.146" - cell $eq $eq$ls180.v:6487$2175 + attribute \src "ls180.v:6539.100-6539.146" + cell $eq $eq$ls180.v:6539$2241 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -253669,10 +254537,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1100 - connect \Y $eq$ls180.v:6487$2175_Y + connect \Y $eq$ls180.v:6539$2241_Y end - attribute \src "ls180.v:6488.103-6488.149" - cell $eq $eq$ls180.v:6488$2179 + attribute \src "ls180.v:6540.103-6540.149" + cell $eq $eq$ls180.v:6540$2245 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -253680,10 +254548,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1100 - connect \Y $eq$ls180.v:6488$2179_Y + connect \Y $eq$ls180.v:6540$2245_Y end - attribute \src "ls180.v:6490.100-6490.146" - cell $eq $eq$ls180.v:6490$2182 + attribute \src "ls180.v:6542.100-6542.146" + cell $eq $eq$ls180.v:6542$2248 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -253691,10 +254559,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1101 - connect \Y $eq$ls180.v:6490$2182_Y + connect \Y $eq$ls180.v:6542$2248_Y end - attribute \src "ls180.v:6491.103-6491.149" - cell $eq $eq$ls180.v:6491$2186 + attribute \src "ls180.v:6543.103-6543.149" + cell $eq $eq$ls180.v:6543$2252 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -253702,10 +254570,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1101 - connect \Y $eq$ls180.v:6491$2186_Y + connect \Y $eq$ls180.v:6543$2252_Y end - attribute \src "ls180.v:6493.112-6493.158" - cell $eq $eq$ls180.v:6493$2189 + attribute \src "ls180.v:6545.112-6545.158" + cell $eq $eq$ls180.v:6545$2255 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -253713,10 +254581,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1110 - connect \Y $eq$ls180.v:6493$2189_Y + connect \Y $eq$ls180.v:6545$2255_Y end - attribute \src "ls180.v:6494.115-6494.161" - cell $eq $eq$ls180.v:6494$2193 + attribute \src "ls180.v:6546.115-6546.161" + cell $eq $eq$ls180.v:6546$2259 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -253724,10 +254592,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1110 - connect \Y $eq$ls180.v:6494$2193_Y + connect \Y $eq$ls180.v:6546$2259_Y end - attribute \src "ls180.v:6496.113-6496.159" - cell $eq $eq$ls180.v:6496$2196 + attribute \src "ls180.v:6548.113-6548.159" + cell $eq $eq$ls180.v:6548$2262 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -253735,10 +254603,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1111 - connect \Y $eq$ls180.v:6496$2196_Y + connect \Y $eq$ls180.v:6548$2262_Y end - attribute \src "ls180.v:6497.116-6497.162" - cell $eq $eq$ls180.v:6497$2200 + attribute \src "ls180.v:6549.116-6549.162" + cell $eq $eq$ls180.v:6549$2266 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -253746,10 +254614,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1111 - connect \Y $eq$ls180.v:6497$2200_Y + connect \Y $eq$ls180.v:6549$2266_Y end - attribute \src "ls180.v:6499.104-6499.150" - cell $eq $eq$ls180.v:6499$2203 + attribute \src "ls180.v:6551.104-6551.150" + cell $eq $eq$ls180.v:6551$2269 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -253757,10 +254625,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 5'10000 - connect \Y $eq$ls180.v:6499$2203_Y + connect \Y $eq$ls180.v:6551$2269_Y end - attribute \src "ls180.v:6500.107-6500.153" - cell $eq $eq$ls180.v:6500$2207 + attribute \src "ls180.v:6552.107-6552.153" + cell $eq $eq$ls180.v:6552$2273 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -253768,21 +254636,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 5'10000 - connect \Y $eq$ls180.v:6500$2207_Y + connect \Y $eq$ls180.v:6552$2273_Y end - attribute \src "ls180.v:6517.33-6517.79" - cell $eq $eq$ls180.v:6517$2209 + attribute \src "ls180.v:6569.33-6569.79" + cell $eq $eq$ls180.v:6569$2275 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [13:9] + connect \A \builder_interface13_bank_bus_adr [13:8] connect \B 3'101 - connect \Y $eq$ls180.v:6517$2209_Y + connect \Y $eq$ls180.v:6569$2275_Y end - attribute \src "ls180.v:6519.90-6519.135" - cell $eq $eq$ls180.v:6519$2211 + attribute \src "ls180.v:6571.90-6571.135" + cell $eq $eq$ls180.v:6571$2277 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -253790,10 +254658,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 1'0 - connect \Y $eq$ls180.v:6519$2211_Y + connect \Y $eq$ls180.v:6571$2277_Y end - attribute \src "ls180.v:6520.93-6520.138" - cell $eq $eq$ls180.v:6520$2215 + attribute \src "ls180.v:6572.93-6572.138" + cell $eq $eq$ls180.v:6572$2281 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -253801,10 +254669,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 1'0 - connect \Y $eq$ls180.v:6520$2215_Y + connect \Y $eq$ls180.v:6572$2281_Y end - attribute \src "ls180.v:6522.100-6522.145" - cell $eq $eq$ls180.v:6522$2218 + attribute \src "ls180.v:6574.100-6574.145" + cell $eq $eq$ls180.v:6574$2284 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -253812,10 +254680,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 1'1 - connect \Y $eq$ls180.v:6522$2218_Y + connect \Y $eq$ls180.v:6574$2284_Y end - attribute \src "ls180.v:6523.103-6523.148" - cell $eq $eq$ls180.v:6523$2222 + attribute \src "ls180.v:6575.103-6575.148" + cell $eq $eq$ls180.v:6575$2288 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -253823,10 +254691,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 1'1 - connect \Y $eq$ls180.v:6523$2222_Y + connect \Y $eq$ls180.v:6575$2288_Y end - attribute \src "ls180.v:6525.101-6525.146" - cell $eq $eq$ls180.v:6525$2225 + attribute \src "ls180.v:6577.101-6577.146" + cell $eq $eq$ls180.v:6577$2291 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -253834,10 +254702,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 2'10 - connect \Y $eq$ls180.v:6525$2225_Y + connect \Y $eq$ls180.v:6577$2291_Y end - attribute \src "ls180.v:6526.104-6526.149" - cell $eq $eq$ls180.v:6526$2229 + attribute \src "ls180.v:6578.104-6578.149" + cell $eq $eq$ls180.v:6578$2295 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -253845,10 +254713,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 2'10 - connect \Y $eq$ls180.v:6526$2229_Y + connect \Y $eq$ls180.v:6578$2295_Y end - attribute \src "ls180.v:6528.105-6528.150" - cell $eq $eq$ls180.v:6528$2232 + attribute \src "ls180.v:6580.105-6580.150" + cell $eq $eq$ls180.v:6580$2298 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -253856,10 +254724,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 2'11 - connect \Y $eq$ls180.v:6528$2232_Y + connect \Y $eq$ls180.v:6580$2298_Y end - attribute \src "ls180.v:6529.108-6529.153" - cell $eq $eq$ls180.v:6529$2236 + attribute \src "ls180.v:6581.108-6581.153" + cell $eq $eq$ls180.v:6581$2302 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -253867,10 +254735,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 2'11 - connect \Y $eq$ls180.v:6529$2236_Y + connect \Y $eq$ls180.v:6581$2302_Y end - attribute \src "ls180.v:6531.106-6531.151" - cell $eq $eq$ls180.v:6531$2239 + attribute \src "ls180.v:6583.106-6583.151" + cell $eq $eq$ls180.v:6583$2305 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -253878,10 +254746,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 3'100 - connect \Y $eq$ls180.v:6531$2239_Y + connect \Y $eq$ls180.v:6583$2305_Y end - attribute \src "ls180.v:6532.109-6532.154" - cell $eq $eq$ls180.v:6532$2243 + attribute \src "ls180.v:6584.109-6584.154" + cell $eq $eq$ls180.v:6584$2309 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -253889,10 +254757,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 3'100 - connect \Y $eq$ls180.v:6532$2243_Y + connect \Y $eq$ls180.v:6584$2309_Y end - attribute \src "ls180.v:6534.104-6534.149" - cell $eq $eq$ls180.v:6534$2246 + attribute \src "ls180.v:6586.104-6586.149" + cell $eq $eq$ls180.v:6586$2312 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -253900,10 +254768,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 3'101 - connect \Y $eq$ls180.v:6534$2246_Y + connect \Y $eq$ls180.v:6586$2312_Y end - attribute \src "ls180.v:6535.107-6535.152" - cell $eq $eq$ls180.v:6535$2250 + attribute \src "ls180.v:6587.107-6587.152" + cell $eq $eq$ls180.v:6587$2316 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -253911,10 +254779,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 3'101 - connect \Y $eq$ls180.v:6535$2250_Y + connect \Y $eq$ls180.v:6587$2316_Y end - attribute \src "ls180.v:6537.101-6537.146" - cell $eq $eq$ls180.v:6537$2253 + attribute \src "ls180.v:6589.101-6589.146" + cell $eq $eq$ls180.v:6589$2319 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -253922,10 +254790,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 3'110 - connect \Y $eq$ls180.v:6537$2253_Y + connect \Y $eq$ls180.v:6589$2319_Y end - attribute \src "ls180.v:6538.104-6538.149" - cell $eq $eq$ls180.v:6538$2257 + attribute \src "ls180.v:6590.104-6590.149" + cell $eq $eq$ls180.v:6590$2323 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -253933,10 +254801,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 3'110 - connect \Y $eq$ls180.v:6538$2257_Y + connect \Y $eq$ls180.v:6590$2323_Y end - attribute \src "ls180.v:6540.100-6540.145" - cell $eq $eq$ls180.v:6540$2260 + attribute \src "ls180.v:6592.100-6592.145" + cell $eq $eq$ls180.v:6592$2326 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -253944,10 +254812,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 3'111 - connect \Y $eq$ls180.v:6540$2260_Y + connect \Y $eq$ls180.v:6592$2326_Y end - attribute \src "ls180.v:6541.103-6541.148" - cell $eq $eq$ls180.v:6541$2264 + attribute \src "ls180.v:6593.103-6593.148" + cell $eq $eq$ls180.v:6593$2330 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -253955,21 +254823,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 3'111 - connect \Y $eq$ls180.v:6541$2264_Y + connect \Y $eq$ls180.v:6593$2330_Y end - attribute \src "ls180.v:6551.33-6551.79" - cell $eq $eq$ls180.v:6551$2266 + attribute \src "ls180.v:6603.33-6603.79" + cell $eq $eq$ls180.v:6603$2332 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface14_bank_bus_adr [13:9] + connect \A \builder_interface14_bank_bus_adr [13:8] connect \B 3'100 - connect \Y $eq$ls180.v:6551$2266_Y + connect \Y $eq$ls180.v:6603$2332_Y end - attribute \src "ls180.v:6553.106-6553.151" - cell $eq $eq$ls180.v:6553$2268 + attribute \src "ls180.v:6605.106-6605.151" + cell $eq $eq$ls180.v:6605$2334 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -253977,10 +254845,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface14_bank_bus_adr [1:0] connect \B 1'0 - connect \Y $eq$ls180.v:6553$2268_Y + connect \Y $eq$ls180.v:6605$2334_Y end - attribute \src "ls180.v:6554.109-6554.154" - cell $eq $eq$ls180.v:6554$2272 + attribute \src "ls180.v:6606.109-6606.154" + cell $eq $eq$ls180.v:6606$2338 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -253988,10 +254856,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface14_bank_bus_adr [1:0] connect \B 1'0 - connect \Y $eq$ls180.v:6554$2272_Y + connect \Y $eq$ls180.v:6606$2338_Y end - attribute \src "ls180.v:6556.106-6556.151" - cell $eq $eq$ls180.v:6556$2275 + attribute \src "ls180.v:6608.106-6608.151" + cell $eq $eq$ls180.v:6608$2341 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -253999,10 +254867,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface14_bank_bus_adr [1:0] connect \B 1'1 - connect \Y $eq$ls180.v:6556$2275_Y + connect \Y $eq$ls180.v:6608$2341_Y end - attribute \src "ls180.v:6557.109-6557.154" - cell $eq $eq$ls180.v:6557$2279 + attribute \src "ls180.v:6609.109-6609.154" + cell $eq $eq$ls180.v:6609$2345 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -254010,10 +254878,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface14_bank_bus_adr [1:0] connect \B 1'1 - connect \Y $eq$ls180.v:6557$2279_Y + connect \Y $eq$ls180.v:6609$2345_Y end - attribute \src "ls180.v:6559.106-6559.151" - cell $eq $eq$ls180.v:6559$2282 + attribute \src "ls180.v:6611.106-6611.151" + cell $eq $eq$ls180.v:6611$2348 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -254021,10 +254889,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface14_bank_bus_adr [1:0] connect \B 2'10 - connect \Y $eq$ls180.v:6559$2282_Y + connect \Y $eq$ls180.v:6611$2348_Y end - attribute \src "ls180.v:6560.109-6560.154" - cell $eq $eq$ls180.v:6560$2286 + attribute \src "ls180.v:6612.109-6612.154" + cell $eq $eq$ls180.v:6612$2352 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -254032,10 +254900,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface14_bank_bus_adr [1:0] connect \B 2'10 - connect \Y $eq$ls180.v:6560$2286_Y + connect \Y $eq$ls180.v:6612$2352_Y end - attribute \src "ls180.v:6562.106-6562.151" - cell $eq $eq$ls180.v:6562$2289 + attribute \src "ls180.v:6614.106-6614.151" + cell $eq $eq$ls180.v:6614$2355 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -254043,10 +254911,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface14_bank_bus_adr [1:0] connect \B 2'11 - connect \Y $eq$ls180.v:6562$2289_Y + connect \Y $eq$ls180.v:6614$2355_Y end - attribute \src "ls180.v:6563.109-6563.154" - cell $eq $eq$ls180.v:6563$2293 + attribute \src "ls180.v:6615.109-6615.154" + cell $eq $eq$ls180.v:6615$2359 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -254054,10 +254922,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface14_bank_bus_adr [1:0] connect \B 2'11 - connect \Y $eq$ls180.v:6563$2293_Y + connect \Y $eq$ls180.v:6615$2359_Y end - attribute \src "ls180.v:6944.41-6944.81" - cell $eq $eq$ls180.v:6944$2330 + attribute \src "ls180.v:6996.41-6996.81" + cell $eq $eq$ls180.v:6996$2396 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -254065,10 +254933,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_addr [10:9] connect \B 1'0 - connect \Y $eq$ls180.v:6944$2330_Y + connect \Y $eq$ls180.v:6996$2396_Y end - attribute \src "ls180.v:6944.144-6944.177" - cell $eq $eq$ls180.v:6944$2331 + attribute \src "ls180.v:6996.144-6996.177" + cell $eq $eq$ls180.v:6996$2397 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254076,10 +254944,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:6944$2331_Y + connect \Y $eq$ls180.v:6996$2397_Y end - attribute \src "ls180.v:6944.219-6944.252" - cell $eq $eq$ls180.v:6944$2334 + attribute \src "ls180.v:6996.219-6996.252" + cell $eq $eq$ls180.v:6996$2400 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254087,10 +254955,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:6944$2334_Y + connect \Y $eq$ls180.v:6996$2400_Y end - attribute \src "ls180.v:6944.294-6944.327" - cell $eq $eq$ls180.v:6944$2337 + attribute \src "ls180.v:6996.294-6996.327" + cell $eq $eq$ls180.v:6996$2403 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254098,10 +254966,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:6944$2337_Y + connect \Y $eq$ls180.v:6996$2403_Y end - attribute \src "ls180.v:6968.41-6968.81" - cell $eq $eq$ls180.v:6968$2346 + attribute \src "ls180.v:7020.41-7020.81" + cell $eq $eq$ls180.v:7020$2412 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -254109,10 +254977,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_addr [10:9] connect \B 1'1 - connect \Y $eq$ls180.v:6968$2346_Y + connect \Y $eq$ls180.v:7020$2412_Y end - attribute \src "ls180.v:6968.144-6968.177" - cell $eq $eq$ls180.v:6968$2347 + attribute \src "ls180.v:7020.144-7020.177" + cell $eq $eq$ls180.v:7020$2413 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254120,10 +254988,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:6968$2347_Y + connect \Y $eq$ls180.v:7020$2413_Y end - attribute \src "ls180.v:6968.219-6968.252" - cell $eq $eq$ls180.v:6968$2350 + attribute \src "ls180.v:7020.219-7020.252" + cell $eq $eq$ls180.v:7020$2416 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254131,10 +254999,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:6968$2350_Y + connect \Y $eq$ls180.v:7020$2416_Y end - attribute \src "ls180.v:6968.294-6968.327" - cell $eq $eq$ls180.v:6968$2353 + attribute \src "ls180.v:7020.294-7020.327" + cell $eq $eq$ls180.v:7020$2419 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254142,10 +255010,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:6968$2353_Y + connect \Y $eq$ls180.v:7020$2419_Y end - attribute \src "ls180.v:6992.41-6992.81" - cell $eq $eq$ls180.v:6992$2362 + attribute \src "ls180.v:7044.41-7044.81" + cell $eq $eq$ls180.v:7044$2428 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -254153,10 +255021,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_addr [10:9] connect \B 2'10 - connect \Y $eq$ls180.v:6992$2362_Y + connect \Y $eq$ls180.v:7044$2428_Y end - attribute \src "ls180.v:6992.144-6992.177" - cell $eq $eq$ls180.v:6992$2363 + attribute \src "ls180.v:7044.144-7044.177" + cell $eq $eq$ls180.v:7044$2429 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254164,10 +255032,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:6992$2363_Y + connect \Y $eq$ls180.v:7044$2429_Y end - attribute \src "ls180.v:6992.219-6992.252" - cell $eq $eq$ls180.v:6992$2366 + attribute \src "ls180.v:7044.219-7044.252" + cell $eq $eq$ls180.v:7044$2432 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254175,10 +255043,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:6992$2366_Y + connect \Y $eq$ls180.v:7044$2432_Y end - attribute \src "ls180.v:6992.294-6992.327" - cell $eq $eq$ls180.v:6992$2369 + attribute \src "ls180.v:7044.294-7044.327" + cell $eq $eq$ls180.v:7044$2435 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254186,10 +255054,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:6992$2369_Y + connect \Y $eq$ls180.v:7044$2435_Y end - attribute \src "ls180.v:7016.41-7016.81" - cell $eq $eq$ls180.v:7016$2378 + attribute \src "ls180.v:7068.41-7068.81" + cell $eq $eq$ls180.v:7068$2444 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -254197,10 +255065,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_addr [10:9] connect \B 2'11 - connect \Y $eq$ls180.v:7016$2378_Y + connect \Y $eq$ls180.v:7068$2444_Y end - attribute \src "ls180.v:7016.144-7016.177" - cell $eq $eq$ls180.v:7016$2379 + attribute \src "ls180.v:7068.144-7068.177" + cell $eq $eq$ls180.v:7068$2445 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254208,10 +255076,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:7016$2379_Y + connect \Y $eq$ls180.v:7068$2445_Y end - attribute \src "ls180.v:7016.219-7016.252" - cell $eq $eq$ls180.v:7016$2382 + attribute \src "ls180.v:7068.219-7068.252" + cell $eq $eq$ls180.v:7068$2448 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254219,10 +255087,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:7016$2382_Y + connect \Y $eq$ls180.v:7068$2448_Y end - attribute \src "ls180.v:7016.294-7016.327" - cell $eq $eq$ls180.v:7016$2385 + attribute \src "ls180.v:7068.294-7068.327" + cell $eq $eq$ls180.v:7068$2451 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254230,10 +255098,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:7016$2385_Y + connect \Y $eq$ls180.v:7068$2451_Y end - attribute \src "ls180.v:7597.8-7597.38" - cell $eq $eq$ls180.v:7597$2476 + attribute \src "ls180.v:7652.8-7652.38" + cell $eq $eq$ls180.v:7652$2543 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -254241,10 +255109,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_value connect \B 1'0 - connect \Y $eq$ls180.v:7597$2476_Y + connect \Y $eq$ls180.v:7652$2543_Y end - attribute \src "ls180.v:7640.8-7640.42" - cell $eq $eq$ls180.v:7640$2493 + attribute \src "ls180.v:7695.8-7695.42" + cell $eq $eq$ls180.v:7695$2560 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254252,10 +255120,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_postponer_count connect \B 1'0 - connect \Y $eq$ls180.v:7640$2493_Y + connect \Y $eq$ls180.v:7695$2560_Y end - attribute \src "ls180.v:7660.38-7660.74" - cell $eq $eq$ls180.v:7660$2496 + attribute \src "ls180.v:7715.38-7715.74" + cell $eq $eq$ls180.v:7715$2563 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -254263,10 +255131,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_counter connect \B 1'0 - connect \Y $eq$ls180.v:7660$2496_Y + connect \Y $eq$ls180.v:7715$2563_Y end - attribute \src "ls180.v:7667.7-7667.43" - cell $eq $eq$ls180.v:7667$2498 + attribute \src "ls180.v:7722.7-7722.43" + cell $eq $eq$ls180.v:7722$2565 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -254274,10 +255142,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_counter connect \B 2'10 - connect \Y $eq$ls180.v:7667$2498_Y + connect \Y $eq$ls180.v:7722$2565_Y end - attribute \src "ls180.v:7674.7-7674.43" - cell $eq $eq$ls180.v:7674$2499 + attribute \src "ls180.v:7729.7-7729.43" + cell $eq $eq$ls180.v:7729$2566 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -254285,10 +255153,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_counter connect \B 4'1000 - connect \Y $eq$ls180.v:7674$2499_Y + connect \Y $eq$ls180.v:7729$2566_Y end - attribute \src "ls180.v:7682.7-7682.43" - cell $eq $eq$ls180.v:7682$2500 + attribute \src "ls180.v:7737.7-7737.43" + cell $eq $eq$ls180.v:7737$2567 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -254296,10 +255164,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_counter connect \B 4'1000 - connect \Y $eq$ls180.v:7682$2500_Y + connect \Y $eq$ls180.v:7737$2567_Y end - attribute \src "ls180.v:7734.9-7734.54" - cell $eq $eq$ls180.v:7734$2518 + attribute \src "ls180.v:7789.9-7789.54" + cell $eq $eq$ls180.v:7789$2585 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -254307,10 +255175,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_twtpcon_count connect \B 1'1 - connect \Y $eq$ls180.v:7734$2518_Y + connect \Y $eq$ls180.v:7789$2585_Y end - attribute \src "ls180.v:7780.9-7780.54" - cell $eq $eq$ls180.v:7780$2534 + attribute \src "ls180.v:7835.9-7835.54" + cell $eq $eq$ls180.v:7835$2601 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -254318,10 +255186,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_twtpcon_count connect \B 1'1 - connect \Y $eq$ls180.v:7780$2534_Y + connect \Y $eq$ls180.v:7835$2601_Y end - attribute \src "ls180.v:7826.9-7826.54" - cell $eq $eq$ls180.v:7826$2550 + attribute \src "ls180.v:7881.9-7881.54" + cell $eq $eq$ls180.v:7881$2617 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -254329,10 +255197,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_twtpcon_count connect \B 1'1 - connect \Y $eq$ls180.v:7826$2550_Y + connect \Y $eq$ls180.v:7881$2617_Y end - attribute \src "ls180.v:7872.9-7872.54" - cell $eq $eq$ls180.v:7872$2566 + attribute \src "ls180.v:7927.9-7927.54" + cell $eq $eq$ls180.v:7927$2633 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -254340,10 +255208,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_twtpcon_count connect \B 1'1 - connect \Y $eq$ls180.v:7872$2566_Y + connect \Y $eq$ls180.v:7927$2633_Y end - attribute \src "ls180.v:8022.9-8022.41" - cell $eq $eq$ls180.v:8022$2578 + attribute \src "ls180.v:8077.9-8077.41" + cell $eq $eq$ls180.v:8077$2645 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254351,10 +255219,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_tccdcon_count connect \B 1'1 - connect \Y $eq$ls180.v:8022$2578_Y + connect \Y $eq$ls180.v:8077$2645_Y end - attribute \src "ls180.v:8037.9-8037.41" - cell $eq $eq$ls180.v:8037$2581 + attribute \src "ls180.v:8092.9-8092.41" + cell $eq $eq$ls180.v:8092$2648 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -254362,10 +255230,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_twtrcon_count connect \B 1'1 - connect \Y $eq$ls180.v:8037$2581_Y + connect \Y $eq$ls180.v:8092$2648_Y end - attribute \src "ls180.v:8043.49-8043.82" - cell $eq $eq$ls180.v:8043$2582 + attribute \src "ls180.v:8098.49-8098.82" + cell $eq $eq$ls180.v:8098$2649 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254373,10 +255241,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:8043$2582_Y + connect \Y $eq$ls180.v:8098$2649_Y end - attribute \src "ls180.v:8043.131-8043.164" - cell $eq $eq$ls180.v:8043$2585 + attribute \src "ls180.v:8098.131-8098.164" + cell $eq $eq$ls180.v:8098$2652 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254384,10 +255252,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:8043$2585_Y + connect \Y $eq$ls180.v:8098$2652_Y end - attribute \src "ls180.v:8043.213-8043.246" - cell $eq $eq$ls180.v:8043$2588 + attribute \src "ls180.v:8098.213-8098.246" + cell $eq $eq$ls180.v:8098$2655 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254395,10 +255263,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:8043$2588_Y + connect \Y $eq$ls180.v:8098$2655_Y end - attribute \src "ls180.v:8043.295-8043.328" - cell $eq $eq$ls180.v:8043$2591 + attribute \src "ls180.v:8098.295-8098.328" + cell $eq $eq$ls180.v:8098$2658 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254406,10 +255274,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:8043$2591_Y + connect \Y $eq$ls180.v:8098$2658_Y end - attribute \src "ls180.v:8044.50-8044.83" - cell $eq $eq$ls180.v:8044$2594 + attribute \src "ls180.v:8099.50-8099.83" + cell $eq $eq$ls180.v:8099$2661 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254417,10 +255285,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:8044$2594_Y + connect \Y $eq$ls180.v:8099$2661_Y end - attribute \src "ls180.v:8044.132-8044.165" - cell $eq $eq$ls180.v:8044$2597 + attribute \src "ls180.v:8099.132-8099.165" + cell $eq $eq$ls180.v:8099$2664 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254428,10 +255296,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:8044$2597_Y + connect \Y $eq$ls180.v:8099$2664_Y end - attribute \src "ls180.v:8044.214-8044.247" - cell $eq $eq$ls180.v:8044$2600 + attribute \src "ls180.v:8099.214-8099.247" + cell $eq $eq$ls180.v:8099$2667 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254439,10 +255307,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:8044$2600_Y + connect \Y $eq$ls180.v:8099$2667_Y end - attribute \src "ls180.v:8044.296-8044.329" - cell $eq $eq$ls180.v:8044$2603 + attribute \src "ls180.v:8099.296-8099.329" + cell $eq $eq$ls180.v:8099$2670 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254450,10 +255318,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:8044$2603_Y + connect \Y $eq$ls180.v:8099$2670_Y end - attribute \src "ls180.v:8079.9-8079.42" - cell $eq $eq$ls180.v:8079$2615 + attribute \src "ls180.v:8134.9-8134.42" + cell $eq $eq$ls180.v:8134$2682 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -254461,10 +255329,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_phy_tx_bitcount connect \B 4'1000 - connect \Y $eq$ls180.v:8079$2615_Y + connect \Y $eq$ls180.v:8134$2682_Y end - attribute \src "ls180.v:8082.10-8082.43" - cell $eq $eq$ls180.v:8082$2616 + attribute \src "ls180.v:8137.10-8137.43" + cell $eq $eq$ls180.v:8137$2683 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -254472,10 +255340,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_phy_tx_bitcount connect \B 4'1001 - connect \Y $eq$ls180.v:8082$2616_Y + connect \Y $eq$ls180.v:8137$2683_Y end - attribute \src "ls180.v:8108.9-8108.42" - cell $eq $eq$ls180.v:8108$2622 + attribute \src "ls180.v:8163.9-8163.42" + cell $eq $eq$ls180.v:8163$2689 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -254483,10 +255351,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_phy_rx_bitcount connect \B 1'0 - connect \Y $eq$ls180.v:8108$2622_Y + connect \Y $eq$ls180.v:8163$2689_Y end - attribute \src "ls180.v:8113.10-8113.43" - cell $eq $eq$ls180.v:8113$2623 + attribute \src "ls180.v:8168.10-8168.43" + cell $eq $eq$ls180.v:8168$2690 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -254494,10 +255362,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_phy_rx_bitcount connect \B 4'1001 - connect \Y $eq$ls180.v:8113$2623_Y + connect \Y $eq$ls180.v:8168$2690_Y end - attribute \src "ls180.v:8320.9-8320.53" - cell $eq $eq$ls180.v:8320$2672 + attribute \src "ls180.v:8375.9-8375.53" + cell $eq $eq$ls180.v:8375$2739 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -254505,10 +255373,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_converter_demux connect \B 3'111 - connect \Y $eq$ls180.v:8320$2672_Y + connect \Y $eq$ls180.v:8375$2739_Y end - attribute \src "ls180.v:8401.9-8401.54" - cell $eq $eq$ls180.v:8401$2684 + attribute \src "ls180.v:8456.9-8456.54" + cell $eq $eq$ls180.v:8456$2751 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -254516,10 +255384,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_converter_demux connect \B 3'111 - connect \Y $eq$ls180.v:8401$2684_Y + connect \Y $eq$ls180.v:8456$2751_Y end - attribute \src "ls180.v:8480.9-8480.55" - cell $eq $eq$ls180.v:8480$2696 + attribute \src "ls180.v:8535.9-8535.55" + cell $eq $eq$ls180.v:8535$2763 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254527,43 +255395,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_converter_demux connect \B 1'1 - connect \Y $eq$ls180.v:8480$2696_Y + connect \Y $eq$ls180.v:8535$2763_Y end - attribute \src "ls180.v:8703.9-8703.49" - cell $eq $eq$ls180.v:8703$2729 + attribute \src "ls180.v:8758.9-8758.49" + cell $eq $eq$ls180.v:8758$2796 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 - parameter \B_WIDTH 2 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_converter_demux - connect \B 2'11 - connect \Y $eq$ls180.v:8703$2729_Y + connect \B 3'111 + connect \Y $eq$ls180.v:8758$2796_Y end - attribute \src "ls180.v:8279.8-8279.54" - cell $ge $ge$ls180.v:8279$2664 + attribute \src "ls180.v:8334.8-8334.54" + cell $ge $ge$ls180.v:8334$2731 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 1 connect \A \main_pwm0_counter - connect \B $sub$ls180.v:8279$2663_Y - connect \Y $ge$ls180.v:8279$2664_Y + connect \B $sub$ls180.v:8334$2730_Y + connect \Y $ge$ls180.v:8334$2731_Y end - attribute \src "ls180.v:8293.8-8293.54" - cell $ge $ge$ls180.v:8293$2668 + attribute \src "ls180.v:8348.8-8348.54" + cell $ge $ge$ls180.v:8348$2735 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 1 connect \A \main_pwm1_counter - connect \B $sub$ls180.v:8293$2667_Y - connect \Y $ge$ls180.v:8293$2668_Y + connect \B $sub$ls180.v:8348$2734_Y + connect \Y $ge$ls180.v:8348$2735_Y end - attribute \src "ls180.v:5226.47-5226.83" - cell $gt $gt$ls180.v:5226$965 + attribute \src "ls180.v:5266.47-5266.83" + cell $gt $gt$ls180.v:5266$1031 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -254571,10 +255439,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_cnt connect \B 3'111 - connect \Y $gt$ls180.v:5226$965_Y + connect \Y $gt$ls180.v:5266$1031_Y end - attribute \src "ls180.v:5232.7-5232.43" - cell $lt $lt$ls180.v:5232$968 + attribute \src "ls180.v:5272.7-5272.43" + cell $lt $lt$ls180.v:5272$1034 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -254582,10 +255450,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_cnt connect \B 4'1000 - connect \Y $lt$ls180.v:5232$968_Y + connect \Y $lt$ls180.v:5272$1034_Y end - attribute \src "ls180.v:8274.8-8274.43" - cell $lt $lt$ls180.v:8274$2662 + attribute \src "ls180.v:8329.8-8329.43" + cell $lt $lt$ls180.v:8329$2729 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -254593,10 +255461,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_pwm0_counter connect \B \main_pwm0_width - connect \Y $lt$ls180.v:8274$2662_Y + connect \Y $lt$ls180.v:8329$2729_Y end - attribute \src "ls180.v:8288.8-8288.43" - cell $lt $lt$ls180.v:8288$2666 + attribute \src "ls180.v:8343.8-8343.43" + cell $lt $lt$ls180.v:8343$2733 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -254604,62 +255472,62 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_pwm1_counter connect \B \main_pwm1_width - connect \Y $lt$ls180.v:8288$2666_Y + connect \Y $lt$ls180.v:8343$2733_Y end - attribute \src "ls180.v:10172.33-10172.36" - cell $memrd $memrd$\mem$ls180.v:10172$2771 - parameter \ABITS 7 + attribute \src "ls180.v:10247.33-10247.36" + cell $memrd $memrd$\mem$ls180.v:10247$2850 + parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem" parameter \TRANSPARENT 0 - parameter \WIDTH 32 + parameter \WIDTH 64 connect \ADDR \memadr connect \CLK 1'x - connect \DATA $memrd$\mem$ls180.v:10172$2771_DATA + connect \DATA $memrd$\mem$ls180.v:10247$2850_DATA connect \EN 1'x end - attribute \src "ls180.v:10192.27-10192.32" - cell $memrd $memrd$\mem_1$ls180.v:10192$2785 - parameter \ABITS 7 + attribute \src "ls180.v:10275.27-10275.32" + cell $memrd $memrd$\mem_1$ls180.v:10275$2876 + parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_1" parameter \TRANSPARENT 0 - parameter \WIDTH 32 + parameter \WIDTH 64 connect \ADDR \memadr_1 connect \CLK 1'x - connect \DATA $memrd$\mem_1$ls180.v:10192$2785_DATA + connect \DATA $memrd$\mem_1$ls180.v:10275$2876_DATA connect \EN 1'x end - attribute \src "ls180.v:10212.27-10212.32" - cell $memrd $memrd$\mem_2$ls180.v:10212$2799 - parameter \ABITS 7 + attribute \src "ls180.v:10303.27-10303.32" + cell $memrd $memrd$\mem_2$ls180.v:10303$2902 + parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_2" parameter \TRANSPARENT 0 - parameter \WIDTH 32 + parameter \WIDTH 64 connect \ADDR \memadr_2 connect \CLK 1'x - connect \DATA $memrd$\mem_2$ls180.v:10212$2799_DATA + connect \DATA $memrd$\mem_2$ls180.v:10303$2902_DATA connect \EN 1'x end - attribute \src "ls180.v:10232.27-10232.32" - cell $memrd $memrd$\mem_3$ls180.v:10232$2813 - parameter \ABITS 7 + attribute \src "ls180.v:10331.27-10331.32" + cell $memrd $memrd$\mem_3$ls180.v:10331$2928 + parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_3" parameter \TRANSPARENT 0 - parameter \WIDTH 32 + parameter \WIDTH 64 connect \ADDR \memadr_3 connect \CLK 1'x - connect \DATA $memrd$\mem_3$ls180.v:10232$2813_DATA + connect \DATA $memrd$\mem_3$ls180.v:10331$2928_DATA connect \EN 1'x end - attribute \src "ls180.v:10243.12-10243.19" - cell $memrd $memrd$\storage$ls180.v:10243$2818 + attribute \src "ls180.v:10342.12-10342.19" + cell $memrd $memrd$\storage$ls180.v:10342$2933 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -254668,11 +255536,11 @@ module \ls180 parameter \WIDTH 25 connect \ADDR \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr connect \CLK 1'x - connect \DATA $memrd$\storage$ls180.v:10243$2818_DATA + connect \DATA $memrd$\storage$ls180.v:10342$2933_DATA connect \EN 1'x end - attribute \src "ls180.v:10250.68-10250.75" - cell $memrd $memrd$\storage$ls180.v:10250$2820 + attribute \src "ls180.v:10349.68-10349.75" + cell $memrd $memrd$\storage$ls180.v:10349$2935 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -254681,11 +255549,11 @@ module \ls180 parameter \WIDTH 25 connect \ADDR \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr connect \CLK 1'x - connect \DATA $memrd$\storage$ls180.v:10250$2820_DATA + connect \DATA $memrd$\storage$ls180.v:10349$2935_DATA connect \EN 1'x end - attribute \src "ls180.v:10257.14-10257.23" - cell $memrd $memrd$\storage_1$ls180.v:10257$2825 + attribute \src "ls180.v:10356.14-10356.23" + cell $memrd $memrd$\storage_1$ls180.v:10356$2940 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -254694,11 +255562,11 @@ module \ls180 parameter \WIDTH 25 connect \ADDR \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_1$ls180.v:10257$2825_DATA + connect \DATA $memrd$\storage_1$ls180.v:10356$2940_DATA connect \EN 1'x end - attribute \src "ls180.v:10264.68-10264.77" - cell $memrd $memrd$\storage_1$ls180.v:10264$2827 + attribute \src "ls180.v:10363.68-10363.77" + cell $memrd $memrd$\storage_1$ls180.v:10363$2942 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -254707,11 +255575,11 @@ module \ls180 parameter \WIDTH 25 connect \ADDR \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_1$ls180.v:10264$2827_DATA + connect \DATA $memrd$\storage_1$ls180.v:10363$2942_DATA connect \EN 1'x end - attribute \src "ls180.v:10271.14-10271.23" - cell $memrd $memrd$\storage_2$ls180.v:10271$2832 + attribute \src "ls180.v:10370.14-10370.23" + cell $memrd $memrd$\storage_2$ls180.v:10370$2947 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -254720,11 +255588,11 @@ module \ls180 parameter \WIDTH 25 connect \ADDR \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_2$ls180.v:10271$2832_DATA + connect \DATA $memrd$\storage_2$ls180.v:10370$2947_DATA connect \EN 1'x end - attribute \src "ls180.v:10278.68-10278.77" - cell $memrd $memrd$\storage_2$ls180.v:10278$2834 + attribute \src "ls180.v:10377.68-10377.77" + cell $memrd $memrd$\storage_2$ls180.v:10377$2949 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -254733,11 +255601,11 @@ module \ls180 parameter \WIDTH 25 connect \ADDR \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_2$ls180.v:10278$2834_DATA + connect \DATA $memrd$\storage_2$ls180.v:10377$2949_DATA connect \EN 1'x end - attribute \src "ls180.v:10285.14-10285.23" - cell $memrd $memrd$\storage_3$ls180.v:10285$2839 + attribute \src "ls180.v:10384.14-10384.23" + cell $memrd $memrd$\storage_3$ls180.v:10384$2954 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -254746,11 +255614,11 @@ module \ls180 parameter \WIDTH 25 connect \ADDR \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_3$ls180.v:10285$2839_DATA + connect \DATA $memrd$\storage_3$ls180.v:10384$2954_DATA connect \EN 1'x end - attribute \src "ls180.v:10292.68-10292.77" - cell $memrd $memrd$\storage_3$ls180.v:10292$2841 + attribute \src "ls180.v:10391.68-10391.77" + cell $memrd $memrd$\storage_3$ls180.v:10391$2956 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -254759,11 +255627,11 @@ module \ls180 parameter \WIDTH 25 connect \ADDR \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_3$ls180.v:10292$2841_DATA + connect \DATA $memrd$\storage_3$ls180.v:10391$2956_DATA connect \EN 1'x end - attribute \src "ls180.v:10300.14-10300.23" - cell $memrd $memrd$\storage_4$ls180.v:10300$2846 + attribute \src "ls180.v:10399.14-10399.23" + cell $memrd $memrd$\storage_4$ls180.v:10399$2961 parameter \ABITS 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -254772,11 +255640,11 @@ module \ls180 parameter \WIDTH 10 connect \ADDR \main_uart_tx_fifo_wrport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_4$ls180.v:10300$2846_DATA + connect \DATA $memrd$\storage_4$ls180.v:10399$2961_DATA connect \EN 1'x end - attribute \src "ls180.v:10305.15-10305.24" - cell $memrd $memrd$\storage_4$ls180.v:10305$2848 + attribute \src "ls180.v:10404.15-10404.24" + cell $memrd $memrd$\storage_4$ls180.v:10404$2963 parameter \ABITS 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -254785,11 +255653,11 @@ module \ls180 parameter \WIDTH 10 connect \ADDR \main_uart_tx_fifo_rdport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_4$ls180.v:10305$2848_DATA + connect \DATA $memrd$\storage_4$ls180.v:10404$2963_DATA connect \EN 1'x end - attribute \src "ls180.v:10317.14-10317.23" - cell $memrd $memrd$\storage_5$ls180.v:10317$2853 + attribute \src "ls180.v:10416.14-10416.23" + cell $memrd $memrd$\storage_5$ls180.v:10416$2968 parameter \ABITS 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -254798,11 +255666,11 @@ module \ls180 parameter \WIDTH 10 connect \ADDR \main_uart_rx_fifo_wrport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_5$ls180.v:10317$2853_DATA + connect \DATA $memrd$\storage_5$ls180.v:10416$2968_DATA connect \EN 1'x end - attribute \src "ls180.v:10322.15-10322.24" - cell $memrd $memrd$\storage_5$ls180.v:10322$2855 + attribute \src "ls180.v:10421.15-10421.24" + cell $memrd $memrd$\storage_5$ls180.v:10421$2970 parameter \ABITS 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -254811,11 +255679,11 @@ module \ls180 parameter \WIDTH 10 connect \ADDR \main_uart_rx_fifo_rdport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_5$ls180.v:10322$2855_DATA + connect \DATA $memrd$\storage_5$ls180.v:10421$2970_DATA connect \EN 1'x end - attribute \src "ls180.v:10333.14-10333.23" - cell $memrd $memrd$\storage_6$ls180.v:10333$2860 + attribute \src "ls180.v:10432.14-10432.23" + cell $memrd $memrd$\storage_6$ls180.v:10432$2975 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -254824,11 +255692,11 @@ module \ls180 parameter \WIDTH 10 connect \ADDR \main_sdblock2mem_fifo_wrport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_6$ls180.v:10333$2860_DATA + connect \DATA $memrd$\storage_6$ls180.v:10432$2975_DATA connect \EN 1'x end - attribute \src "ls180.v:10340.45-10340.54" - cell $memrd $memrd$\storage_6$ls180.v:10340$2862 + attribute \src "ls180.v:10439.45-10439.54" + cell $memrd $memrd$\storage_6$ls180.v:10439$2977 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -254837,11 +255705,11 @@ module \ls180 parameter \WIDTH 10 connect \ADDR \main_sdblock2mem_fifo_rdport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_6$ls180.v:10340$2862_DATA + connect \DATA $memrd$\storage_6$ls180.v:10439$2977_DATA connect \EN 1'x end - attribute \src "ls180.v:10347.14-10347.23" - cell $memrd $memrd$\storage_7$ls180.v:10347$2867 + attribute \src "ls180.v:10446.14-10446.23" + cell $memrd $memrd$\storage_7$ls180.v:10446$2982 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -254850,11 +255718,11 @@ module \ls180 parameter \WIDTH 10 connect \ADDR \main_sdmem2block_fifo_wrport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_7$ls180.v:10347$2867_DATA + connect \DATA $memrd$\storage_7$ls180.v:10446$2982_DATA connect \EN 1'x end - attribute \src "ls180.v:10354.45-10354.54" - cell $memrd $memrd$\storage_7$ls180.v:10354$2869 + attribute \src "ls180.v:10453.45-10453.54" + cell $memrd $memrd$\storage_7$ls180.v:10453$2984 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -254863,323 +255731,531 @@ module \ls180 parameter \WIDTH 10 connect \ADDR \main_sdmem2block_fifo_rdport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_7$ls180.v:10354$2869_DATA + connect \DATA $memrd$\storage_7$ls180.v:10453$2984_DATA connect \EN 1'x end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem$ls180.v:0$2871 - parameter \ABITS 7 + cell $memwr $memwr$\mem$ls180.v:0$2986 + parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem" - parameter \PRIORITY 2871 - parameter \WIDTH 32 - connect \ADDR $memwr$\mem$ls180.v:10162$1_ADDR + parameter \PRIORITY 2986 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem$ls180.v:10229$1_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem$ls180.v:10162$1_DATA - connect \EN $memwr$\mem$ls180.v:10162$1_EN + connect \DATA $memwr$\mem$ls180.v:10229$1_DATA + connect \EN $memwr$\mem$ls180.v:10229$1_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem$ls180.v:0$2872 - parameter \ABITS 7 + cell $memwr $memwr$\mem$ls180.v:0$2987 + parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem" - parameter \PRIORITY 2872 - parameter \WIDTH 32 - connect \ADDR $memwr$\mem$ls180.v:10164$2_ADDR + parameter \PRIORITY 2987 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem$ls180.v:10231$2_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem$ls180.v:10164$2_DATA - connect \EN $memwr$\mem$ls180.v:10164$2_EN + connect \DATA $memwr$\mem$ls180.v:10231$2_DATA + connect \EN $memwr$\mem$ls180.v:10231$2_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem$ls180.v:0$2873 - parameter \ABITS 7 + cell $memwr $memwr$\mem$ls180.v:0$2988 + parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem" - parameter \PRIORITY 2873 - parameter \WIDTH 32 - connect \ADDR $memwr$\mem$ls180.v:10166$3_ADDR + parameter \PRIORITY 2988 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem$ls180.v:10233$3_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem$ls180.v:10166$3_DATA - connect \EN $memwr$\mem$ls180.v:10166$3_EN + connect \DATA $memwr$\mem$ls180.v:10233$3_DATA + connect \EN $memwr$\mem$ls180.v:10233$3_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem$ls180.v:0$2874 - parameter \ABITS 7 + cell $memwr $memwr$\mem$ls180.v:0$2989 + parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem" - parameter \PRIORITY 2874 - parameter \WIDTH 32 - connect \ADDR $memwr$\mem$ls180.v:10168$4_ADDR + parameter \PRIORITY 2989 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem$ls180.v:10235$4_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem$ls180.v:10168$4_DATA - connect \EN $memwr$\mem$ls180.v:10168$4_EN + connect \DATA $memwr$\mem$ls180.v:10235$4_DATA + connect \EN $memwr$\mem$ls180.v:10235$4_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_1$ls180.v:0$2875 - parameter \ABITS 7 + cell $memwr $memwr$\mem$ls180.v:0$2990 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem" + parameter \PRIORITY 2990 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem$ls180.v:10237$5_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem$ls180.v:10237$5_DATA + connect \EN $memwr$\mem$ls180.v:10237$5_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem$ls180.v:0$2991 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem" + parameter \PRIORITY 2991 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem$ls180.v:10239$6_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem$ls180.v:10239$6_DATA + connect \EN $memwr$\mem$ls180.v:10239$6_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem$ls180.v:0$2992 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem" + parameter \PRIORITY 2992 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem$ls180.v:10241$7_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem$ls180.v:10241$7_DATA + connect \EN $memwr$\mem$ls180.v:10241$7_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem$ls180.v:0$2993 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem" + parameter \PRIORITY 2993 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem$ls180.v:10243$8_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem$ls180.v:10243$8_DATA + connect \EN $memwr$\mem$ls180.v:10243$8_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_1$ls180.v:0$2994 + parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_1" - parameter \PRIORITY 2875 - parameter \WIDTH 32 - connect \ADDR $memwr$\mem_1$ls180.v:10182$5_ADDR + parameter \PRIORITY 2994 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_1$ls180.v:10257$9_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem_1$ls180.v:10182$5_DATA - connect \EN $memwr$\mem_1$ls180.v:10182$5_EN + connect \DATA $memwr$\mem_1$ls180.v:10257$9_DATA + connect \EN $memwr$\mem_1$ls180.v:10257$9_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_1$ls180.v:0$2876 - parameter \ABITS 7 + cell $memwr $memwr$\mem_1$ls180.v:0$2995 + parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_1" - parameter \PRIORITY 2876 - parameter \WIDTH 32 - connect \ADDR $memwr$\mem_1$ls180.v:10184$6_ADDR + parameter \PRIORITY 2995 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_1$ls180.v:10259$10_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem_1$ls180.v:10184$6_DATA - connect \EN $memwr$\mem_1$ls180.v:10184$6_EN + connect \DATA $memwr$\mem_1$ls180.v:10259$10_DATA + connect \EN $memwr$\mem_1$ls180.v:10259$10_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_1$ls180.v:0$2877 - parameter \ABITS 7 + cell $memwr $memwr$\mem_1$ls180.v:0$2996 + parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_1" - parameter \PRIORITY 2877 - parameter \WIDTH 32 - connect \ADDR $memwr$\mem_1$ls180.v:10186$7_ADDR + parameter \PRIORITY 2996 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_1$ls180.v:10261$11_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem_1$ls180.v:10186$7_DATA - connect \EN $memwr$\mem_1$ls180.v:10186$7_EN + connect \DATA $memwr$\mem_1$ls180.v:10261$11_DATA + connect \EN $memwr$\mem_1$ls180.v:10261$11_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_1$ls180.v:0$2878 - parameter \ABITS 7 + cell $memwr $memwr$\mem_1$ls180.v:0$2997 + parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_1" - parameter \PRIORITY 2878 - parameter \WIDTH 32 - connect \ADDR $memwr$\mem_1$ls180.v:10188$8_ADDR + parameter \PRIORITY 2997 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_1$ls180.v:10263$12_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem_1$ls180.v:10188$8_DATA - connect \EN $memwr$\mem_1$ls180.v:10188$8_EN + connect \DATA $memwr$\mem_1$ls180.v:10263$12_DATA + connect \EN $memwr$\mem_1$ls180.v:10263$12_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_2$ls180.v:0$2879 - parameter \ABITS 7 + cell $memwr $memwr$\mem_1$ls180.v:0$2998 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_1" + parameter \PRIORITY 2998 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_1$ls180.v:10265$13_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_1$ls180.v:10265$13_DATA + connect \EN $memwr$\mem_1$ls180.v:10265$13_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_1$ls180.v:0$2999 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_1" + parameter \PRIORITY 2999 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_1$ls180.v:10267$14_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_1$ls180.v:10267$14_DATA + connect \EN $memwr$\mem_1$ls180.v:10267$14_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_1$ls180.v:0$3000 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_1" + parameter \PRIORITY 3000 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_1$ls180.v:10269$15_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_1$ls180.v:10269$15_DATA + connect \EN $memwr$\mem_1$ls180.v:10269$15_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_1$ls180.v:0$3001 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_1" + parameter \PRIORITY 3001 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_1$ls180.v:10271$16_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_1$ls180.v:10271$16_DATA + connect \EN $memwr$\mem_1$ls180.v:10271$16_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_2$ls180.v:0$3002 + parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_2" - parameter \PRIORITY 2879 - parameter \WIDTH 32 - connect \ADDR $memwr$\mem_2$ls180.v:10202$9_ADDR + parameter \PRIORITY 3002 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_2$ls180.v:10285$17_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem_2$ls180.v:10202$9_DATA - connect \EN $memwr$\mem_2$ls180.v:10202$9_EN + connect \DATA $memwr$\mem_2$ls180.v:10285$17_DATA + connect \EN $memwr$\mem_2$ls180.v:10285$17_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_2$ls180.v:0$2880 - parameter \ABITS 7 + cell $memwr $memwr$\mem_2$ls180.v:0$3003 + parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_2" - parameter \PRIORITY 2880 - parameter \WIDTH 32 - connect \ADDR $memwr$\mem_2$ls180.v:10204$10_ADDR + parameter \PRIORITY 3003 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_2$ls180.v:10287$18_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem_2$ls180.v:10204$10_DATA - connect \EN $memwr$\mem_2$ls180.v:10204$10_EN + connect \DATA $memwr$\mem_2$ls180.v:10287$18_DATA + connect \EN $memwr$\mem_2$ls180.v:10287$18_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_2$ls180.v:0$2881 - parameter \ABITS 7 + cell $memwr $memwr$\mem_2$ls180.v:0$3004 + parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_2" - parameter \PRIORITY 2881 - parameter \WIDTH 32 - connect \ADDR $memwr$\mem_2$ls180.v:10206$11_ADDR + parameter \PRIORITY 3004 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_2$ls180.v:10289$19_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem_2$ls180.v:10206$11_DATA - connect \EN $memwr$\mem_2$ls180.v:10206$11_EN + connect \DATA $memwr$\mem_2$ls180.v:10289$19_DATA + connect \EN $memwr$\mem_2$ls180.v:10289$19_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_2$ls180.v:0$2882 - parameter \ABITS 7 + cell $memwr $memwr$\mem_2$ls180.v:0$3005 + parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_2" - parameter \PRIORITY 2882 - parameter \WIDTH 32 - connect \ADDR $memwr$\mem_2$ls180.v:10208$12_ADDR + parameter \PRIORITY 3005 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_2$ls180.v:10291$20_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem_2$ls180.v:10208$12_DATA - connect \EN $memwr$\mem_2$ls180.v:10208$12_EN + connect \DATA $memwr$\mem_2$ls180.v:10291$20_DATA + connect \EN $memwr$\mem_2$ls180.v:10291$20_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_3$ls180.v:0$2883 - parameter \ABITS 7 + cell $memwr $memwr$\mem_2$ls180.v:0$3006 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_2" + parameter \PRIORITY 3006 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_2$ls180.v:10293$21_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_2$ls180.v:10293$21_DATA + connect \EN $memwr$\mem_2$ls180.v:10293$21_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_2$ls180.v:0$3007 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_2" + parameter \PRIORITY 3007 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_2$ls180.v:10295$22_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_2$ls180.v:10295$22_DATA + connect \EN $memwr$\mem_2$ls180.v:10295$22_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_2$ls180.v:0$3008 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_2" + parameter \PRIORITY 3008 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_2$ls180.v:10297$23_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_2$ls180.v:10297$23_DATA + connect \EN $memwr$\mem_2$ls180.v:10297$23_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_2$ls180.v:0$3009 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_2" + parameter \PRIORITY 3009 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_2$ls180.v:10299$24_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_2$ls180.v:10299$24_DATA + connect \EN $memwr$\mem_2$ls180.v:10299$24_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_3$ls180.v:0$3010 + parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_3" - parameter \PRIORITY 2883 - parameter \WIDTH 32 - connect \ADDR $memwr$\mem_3$ls180.v:10222$13_ADDR + parameter \PRIORITY 3010 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_3$ls180.v:10313$25_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem_3$ls180.v:10222$13_DATA - connect \EN $memwr$\mem_3$ls180.v:10222$13_EN + connect \DATA $memwr$\mem_3$ls180.v:10313$25_DATA + connect \EN $memwr$\mem_3$ls180.v:10313$25_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_3$ls180.v:0$2884 - parameter \ABITS 7 + cell $memwr $memwr$\mem_3$ls180.v:0$3011 + parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_3" - parameter \PRIORITY 2884 - parameter \WIDTH 32 - connect \ADDR $memwr$\mem_3$ls180.v:10224$14_ADDR + parameter \PRIORITY 3011 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_3$ls180.v:10315$26_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem_3$ls180.v:10224$14_DATA - connect \EN $memwr$\mem_3$ls180.v:10224$14_EN + connect \DATA $memwr$\mem_3$ls180.v:10315$26_DATA + connect \EN $memwr$\mem_3$ls180.v:10315$26_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_3$ls180.v:0$2885 - parameter \ABITS 7 + cell $memwr $memwr$\mem_3$ls180.v:0$3012 + parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_3" - parameter \PRIORITY 2885 - parameter \WIDTH 32 - connect \ADDR $memwr$\mem_3$ls180.v:10226$15_ADDR + parameter \PRIORITY 3012 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_3$ls180.v:10317$27_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem_3$ls180.v:10226$15_DATA - connect \EN $memwr$\mem_3$ls180.v:10226$15_EN + connect \DATA $memwr$\mem_3$ls180.v:10317$27_DATA + connect \EN $memwr$\mem_3$ls180.v:10317$27_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_3$ls180.v:0$2886 - parameter \ABITS 7 + cell $memwr $memwr$\mem_3$ls180.v:0$3013 + parameter \ABITS 6 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_3" - parameter \PRIORITY 2886 - parameter \WIDTH 32 - connect \ADDR $memwr$\mem_3$ls180.v:10228$16_ADDR + parameter \PRIORITY 3013 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_3$ls180.v:10319$28_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_3$ls180.v:10319$28_DATA + connect \EN $memwr$\mem_3$ls180.v:10319$28_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_3$ls180.v:0$3014 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_3" + parameter \PRIORITY 3014 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_3$ls180.v:10321$29_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_3$ls180.v:10321$29_DATA + connect \EN $memwr$\mem_3$ls180.v:10321$29_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_3$ls180.v:0$3015 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_3" + parameter \PRIORITY 3015 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_3$ls180.v:10323$30_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_3$ls180.v:10323$30_DATA + connect \EN $memwr$\mem_3$ls180.v:10323$30_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_3$ls180.v:0$3016 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_3" + parameter \PRIORITY 3016 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_3$ls180.v:10325$31_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_3$ls180.v:10325$31_DATA + connect \EN $memwr$\mem_3$ls180.v:10325$31_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_3$ls180.v:0$3017 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_3" + parameter \PRIORITY 3017 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_3$ls180.v:10327$32_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem_3$ls180.v:10228$16_DATA - connect \EN $memwr$\mem_3$ls180.v:10228$16_EN + connect \DATA $memwr$\mem_3$ls180.v:10327$32_DATA + connect \EN $memwr$\mem_3$ls180.v:10327$32_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage$ls180.v:0$2887 + cell $memwr $memwr$\storage$ls180.v:0$3018 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\storage" - parameter \PRIORITY 2887 + parameter \PRIORITY 3018 parameter \WIDTH 25 - connect \ADDR $memwr$\storage$ls180.v:10242$17_ADDR + connect \ADDR $memwr$\storage$ls180.v:10341$33_ADDR connect \CLK 1'x - connect \DATA $memwr$\storage$ls180.v:10242$17_DATA - connect \EN $memwr$\storage$ls180.v:10242$17_EN + connect \DATA $memwr$\storage$ls180.v:10341$33_DATA + connect \EN $memwr$\storage$ls180.v:10341$33_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_1$ls180.v:0$2888 + cell $memwr $memwr$\storage_1$ls180.v:0$3019 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\storage_1" - parameter \PRIORITY 2888 + parameter \PRIORITY 3019 parameter \WIDTH 25 - connect \ADDR $memwr$\storage_1$ls180.v:10256$18_ADDR + connect \ADDR $memwr$\storage_1$ls180.v:10355$34_ADDR connect \CLK 1'x - connect \DATA $memwr$\storage_1$ls180.v:10256$18_DATA - connect \EN $memwr$\storage_1$ls180.v:10256$18_EN + connect \DATA $memwr$\storage_1$ls180.v:10355$34_DATA + connect \EN $memwr$\storage_1$ls180.v:10355$34_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_2$ls180.v:0$2889 + cell $memwr $memwr$\storage_2$ls180.v:0$3020 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\storage_2" - parameter \PRIORITY 2889 + parameter \PRIORITY 3020 parameter \WIDTH 25 - connect \ADDR $memwr$\storage_2$ls180.v:10270$19_ADDR + connect \ADDR $memwr$\storage_2$ls180.v:10369$35_ADDR connect \CLK 1'x - connect \DATA $memwr$\storage_2$ls180.v:10270$19_DATA - connect \EN $memwr$\storage_2$ls180.v:10270$19_EN + connect \DATA $memwr$\storage_2$ls180.v:10369$35_DATA + connect \EN $memwr$\storage_2$ls180.v:10369$35_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_3$ls180.v:0$2890 + cell $memwr $memwr$\storage_3$ls180.v:0$3021 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\storage_3" - parameter \PRIORITY 2890 + parameter \PRIORITY 3021 parameter \WIDTH 25 - connect \ADDR $memwr$\storage_3$ls180.v:10284$20_ADDR + connect \ADDR $memwr$\storage_3$ls180.v:10383$36_ADDR connect \CLK 1'x - connect \DATA $memwr$\storage_3$ls180.v:10284$20_DATA - connect \EN $memwr$\storage_3$ls180.v:10284$20_EN + connect \DATA $memwr$\storage_3$ls180.v:10383$36_DATA + connect \EN $memwr$\storage_3$ls180.v:10383$36_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_4$ls180.v:0$2891 + cell $memwr $memwr$\storage_4$ls180.v:0$3022 parameter \ABITS 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\storage_4" - parameter \PRIORITY 2891 + parameter \PRIORITY 3022 parameter \WIDTH 10 - connect \ADDR $memwr$\storage_4$ls180.v:10299$21_ADDR + connect \ADDR $memwr$\storage_4$ls180.v:10398$37_ADDR connect \CLK 1'x - connect \DATA $memwr$\storage_4$ls180.v:10299$21_DATA - connect \EN $memwr$\storage_4$ls180.v:10299$21_EN + connect \DATA $memwr$\storage_4$ls180.v:10398$37_DATA + connect \EN $memwr$\storage_4$ls180.v:10398$37_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_5$ls180.v:0$2892 + cell $memwr $memwr$\storage_5$ls180.v:0$3023 parameter \ABITS 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\storage_5" - parameter \PRIORITY 2892 + parameter \PRIORITY 3023 parameter \WIDTH 10 - connect \ADDR $memwr$\storage_5$ls180.v:10316$22_ADDR + connect \ADDR $memwr$\storage_5$ls180.v:10415$38_ADDR connect \CLK 1'x - connect \DATA $memwr$\storage_5$ls180.v:10316$22_DATA - connect \EN $memwr$\storage_5$ls180.v:10316$22_EN + connect \DATA $memwr$\storage_5$ls180.v:10415$38_DATA + connect \EN $memwr$\storage_5$ls180.v:10415$38_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_6$ls180.v:0$2893 + cell $memwr $memwr$\storage_6$ls180.v:0$3024 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\storage_6" - parameter \PRIORITY 2893 + parameter \PRIORITY 3024 parameter \WIDTH 10 - connect \ADDR $memwr$\storage_6$ls180.v:10332$23_ADDR + connect \ADDR $memwr$\storage_6$ls180.v:10431$39_ADDR connect \CLK 1'x - connect \DATA $memwr$\storage_6$ls180.v:10332$23_DATA - connect \EN $memwr$\storage_6$ls180.v:10332$23_EN + connect \DATA $memwr$\storage_6$ls180.v:10431$39_DATA + connect \EN $memwr$\storage_6$ls180.v:10431$39_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_7$ls180.v:0$2894 + cell $memwr $memwr$\storage_7$ls180.v:0$3025 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\storage_7" - parameter \PRIORITY 2894 + parameter \PRIORITY 3025 parameter \WIDTH 10 - connect \ADDR $memwr$\storage_7$ls180.v:10346$24_ADDR + connect \ADDR $memwr$\storage_7$ls180.v:10445$40_ADDR connect \CLK 1'x - connect \DATA $memwr$\storage_7$ls180.v:10346$24_DATA - connect \EN $memwr$\storage_7$ls180.v:10346$24_EN + connect \DATA $memwr$\storage_7$ls180.v:10445$40_DATA + connect \EN $memwr$\storage_7$ls180.v:10445$40_EN end - attribute \src "ls180.v:3010.41-3010.71" - cell $ne $ne$ls180.v:3010$72 + attribute \src "ls180.v:3027.41-3027.71" + cell $ne $ne$ls180.v:3027$100 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -255187,10 +256263,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_value connect \B 1'0 - connect \Y $ne$ls180.v:3010$72_Y + connect \Y $ne$ls180.v:3027$100_Y end - attribute \src "ls180.v:3201.70-3201.104" - cell $ne $ne$ls180.v:3201$125 + attribute \src "ls180.v:3230.70-3230.104" + cell $ne $ne$ls180.v:3230$189 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255198,10 +256274,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_count connect \B 1'0 - connect \Y $ne$ls180.v:3201$125_Y + connect \Y $ne$ls180.v:3230$189_Y end - attribute \src "ls180.v:3262.8-3262.142" - cell $ne $ne$ls180.v:3262$144 + attribute \src "ls180.v:3291.8-3291.142" + cell $ne $ne$ls180.v:3291$208 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 @@ -255209,10 +256285,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr [21:9] connect \B \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] - connect \Y $ne$ls180.v:3262$144_Y + connect \Y $ne$ls180.v:3291$208_Y end - attribute \src "ls180.v:3294.75-3294.133" - cell $ne $ne$ls180.v:3294$151 + attribute \src "ls180.v:3323.75-3323.133" + cell $ne $ne$ls180.v:3323$215 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -255220,10 +256296,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level connect \B 4'1000 - connect \Y $ne$ls180.v:3294$151_Y + connect \Y $ne$ls180.v:3323$215_Y end - attribute \src "ls180.v:3295.75-3295.133" - cell $ne $ne$ls180.v:3295$152 + attribute \src "ls180.v:3324.75-3324.133" + cell $ne $ne$ls180.v:3324$216 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -255231,10 +256307,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level connect \B 1'0 - connect \Y $ne$ls180.v:3295$152_Y + connect \Y $ne$ls180.v:3324$216_Y end - attribute \src "ls180.v:3419.8-3419.142" - cell $ne $ne$ls180.v:3419$174 + attribute \src "ls180.v:3448.8-3448.142" + cell $ne $ne$ls180.v:3448$238 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 @@ -255242,10 +256318,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr [21:9] connect \B \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] - connect \Y $ne$ls180.v:3419$174_Y + connect \Y $ne$ls180.v:3448$238_Y end - attribute \src "ls180.v:3451.75-3451.133" - cell $ne $ne$ls180.v:3451$181 + attribute \src "ls180.v:3480.75-3480.133" + cell $ne $ne$ls180.v:3480$245 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -255253,10 +256329,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level connect \B 4'1000 - connect \Y $ne$ls180.v:3451$181_Y + connect \Y $ne$ls180.v:3480$245_Y end - attribute \src "ls180.v:3452.75-3452.133" - cell $ne $ne$ls180.v:3452$182 + attribute \src "ls180.v:3481.75-3481.133" + cell $ne $ne$ls180.v:3481$246 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -255264,10 +256340,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level connect \B 1'0 - connect \Y $ne$ls180.v:3452$182_Y + connect \Y $ne$ls180.v:3481$246_Y end - attribute \src "ls180.v:3576.8-3576.142" - cell $ne $ne$ls180.v:3576$204 + attribute \src "ls180.v:3605.8-3605.142" + cell $ne $ne$ls180.v:3605$268 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 @@ -255275,10 +256351,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr [21:9] connect \B \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] - connect \Y $ne$ls180.v:3576$204_Y + connect \Y $ne$ls180.v:3605$268_Y end - attribute \src "ls180.v:3608.75-3608.133" - cell $ne $ne$ls180.v:3608$211 + attribute \src "ls180.v:3637.75-3637.133" + cell $ne $ne$ls180.v:3637$275 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -255286,10 +256362,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level connect \B 4'1000 - connect \Y $ne$ls180.v:3608$211_Y + connect \Y $ne$ls180.v:3637$275_Y end - attribute \src "ls180.v:3609.75-3609.133" - cell $ne $ne$ls180.v:3609$212 + attribute \src "ls180.v:3638.75-3638.133" + cell $ne $ne$ls180.v:3638$276 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -255297,10 +256373,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level connect \B 1'0 - connect \Y $ne$ls180.v:3609$212_Y + connect \Y $ne$ls180.v:3638$276_Y end - attribute \src "ls180.v:3733.8-3733.142" - cell $ne $ne$ls180.v:3733$234 + attribute \src "ls180.v:3762.8-3762.142" + cell $ne $ne$ls180.v:3762$298 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 @@ -255308,10 +256384,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr [21:9] connect \B \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] - connect \Y $ne$ls180.v:3733$234_Y + connect \Y $ne$ls180.v:3762$298_Y end - attribute \src "ls180.v:3765.75-3765.133" - cell $ne $ne$ls180.v:3765$241 + attribute \src "ls180.v:3794.75-3794.133" + cell $ne $ne$ls180.v:3794$305 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -255319,10 +256395,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level connect \B 4'1000 - connect \Y $ne$ls180.v:3765$241_Y + connect \Y $ne$ls180.v:3794$305_Y end - attribute \src "ls180.v:3766.75-3766.133" - cell $ne $ne$ls180.v:3766$242 + attribute \src "ls180.v:3795.75-3795.133" + cell $ne $ne$ls180.v:3795$306 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -255330,10 +256406,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level connect \B 1'0 - connect \Y $ne$ls180.v:3766$242_Y + connect \Y $ne$ls180.v:3795$306_Y end - attribute \src "ls180.v:4258.47-4258.80" - cell $ne $ne$ls180.v:4258$640 + attribute \src "ls180.v:4287.47-4287.80" + cell $ne $ne$ls180.v:4287$704 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -255341,10 +256417,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_level0 connect \B 5'10000 - connect \Y $ne$ls180.v:4258$640_Y + connect \Y $ne$ls180.v:4287$704_Y end - attribute \src "ls180.v:4259.47-4259.79" - cell $ne $ne$ls180.v:4259$641 + attribute \src "ls180.v:4288.47-4288.79" + cell $ne $ne$ls180.v:4288$705 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -255352,10 +256428,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_level0 connect \B 1'0 - connect \Y $ne$ls180.v:4259$641_Y + connect \Y $ne$ls180.v:4288$705_Y end - attribute \src "ls180.v:4288.47-4288.80" - cell $ne $ne$ls180.v:4288$651 + attribute \src "ls180.v:4317.47-4317.80" + cell $ne $ne$ls180.v:4317$715 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -255363,10 +256439,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_level0 connect \B 5'10000 - connect \Y $ne$ls180.v:4288$651_Y + connect \Y $ne$ls180.v:4317$715_Y end - attribute \src "ls180.v:4289.47-4289.79" - cell $ne $ne$ls180.v:4289$652 + attribute \src "ls180.v:4318.47-4318.79" + cell $ne $ne$ls180.v:4318$716 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -255374,10 +256450,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_level0 connect \B 1'0 - connect \Y $ne$ls180.v:4289$652_Y + connect \Y $ne$ls180.v:4318$716_Y end - attribute \src "ls180.v:4758.32-4758.89" - cell $ne $ne$ls180.v:4758$732 + attribute \src "ls180.v:4798.32-4798.89" + cell $ne $ne$ls180.v:4798$798 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -255385,10 +256461,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_source_source_payload_data0 connect \B 3'101 - connect \Y $ne$ls180.v:4758$732_Y + connect \Y $ne$ls180.v:4798$798_Y end - attribute \src "ls180.v:5405.10-5405.56" - cell $ne $ne$ls180.v:5405$1029 + attribute \src "ls180.v:5445.10-5445.56" + cell $ne $ne$ls180.v:5445$1095 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -255396,10 +256472,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_source_payload_status connect \B 2'10 - connect \Y $ne$ls180.v:5405$1029_Y + connect \Y $ne$ls180.v:5445$1095_Y end - attribute \src "ls180.v:5510.51-5510.87" - cell $ne $ne$ls180.v:5510$1043 + attribute \src "ls180.v:5550.51-5550.87" + cell $ne $ne$ls180.v:5550$1109 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -255407,10 +256483,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_fifo_level connect \B 6'100000 - connect \Y $ne$ls180.v:5510$1043_Y + connect \Y $ne$ls180.v:5550$1109_Y end - attribute \src "ls180.v:5511.51-5511.86" - cell $ne $ne$ls180.v:5511$1044 + attribute \src "ls180.v:5551.51-5551.86" + cell $ne $ne$ls180.v:5551$1110 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -255418,10 +256494,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_fifo_level connect \B 1'0 - connect \Y $ne$ls180.v:5511$1044_Y + connect \Y $ne$ls180.v:5551$1110_Y end - attribute \src "ls180.v:5718.51-5718.87" - cell $ne $ne$ls180.v:5718$1074 + attribute \src "ls180.v:5770.51-5770.87" + cell $ne $ne$ls180.v:5770$1140 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -255429,10 +256505,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_fifo_level connect \B 6'100000 - connect \Y $ne$ls180.v:5718$1074_Y + connect \Y $ne$ls180.v:5770$1140_Y end - attribute \src "ls180.v:5719.51-5719.86" - cell $ne $ne$ls180.v:5719$1075 + attribute \src "ls180.v:5771.51-5771.86" + cell $ne $ne$ls180.v:5771$1141 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -255440,10 +256516,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_fifo_level connect \B 1'0 - connect \Y $ne$ls180.v:5719$1075_Y + connect \Y $ne$ls180.v:5771$1141_Y end - attribute \src "ls180.v:5750.79-5750.119" - cell $ne $ne$ls180.v:5750$1078 + attribute \src "ls180.v:5802.79-5802.119" + cell $ne $ne$ls180.v:5802$1144 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -255451,10 +256527,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_libresocsim_wishbone_sel connect \B 1'0 - connect \Y $ne$ls180.v:5750$1078_Y + connect \Y $ne$ls180.v:5802$1144_Y end - attribute \src "ls180.v:7587.7-7587.52" - cell $ne $ne$ls180.v:7587$2471 + attribute \src "ls180.v:7642.7-7642.52" + cell $ne $ne$ls180.v:7642$2538 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -255462,10 +256538,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_bus_errors connect \B 32'11111111111111111111111111111111 - connect \Y $ne$ls180.v:7587$2471_Y + connect \Y $ne$ls180.v:7642$2538_Y end - attribute \src "ls180.v:7649.9-7649.43" - cell $ne $ne$ls180.v:7649$2494 + attribute \src "ls180.v:7704.9-7704.43" + cell $ne $ne$ls180.v:7704$2561 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255473,10 +256549,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_count connect \B 1'0 - connect \Y $ne$ls180.v:7649$2494_Y + connect \Y $ne$ls180.v:7704$2561_Y end - attribute \src "ls180.v:7685.8-7685.44" - cell $ne $ne$ls180.v:7685$2501 + attribute \src "ls180.v:7740.8-7740.44" + cell $ne $ne$ls180.v:7740$2568 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -255484,10 +256560,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_counter connect \B 1'0 - connect \Y $ne$ls180.v:7685$2501_Y + connect \Y $ne$ls180.v:7740$2568_Y end - attribute \src "ls180.v:8623.9-8623.47" - cell $ne $ne$ls180.v:8623$2716 + attribute \src "ls180.v:8678.9-8678.47" + cell $ne $ne$ls180.v:8678$2783 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -255495,2730 +256571,2730 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_cnt connect \B 4'1010 - connect \Y $ne$ls180.v:8623$2716_Y + connect \Y $ne$ls180.v:8678$2783_Y end - attribute \src "ls180.v:2818.45-2818.80" - cell $not $not$ls180.v:2818$26 + attribute \src "ls180.v:2831.33-2831.73" + cell $not $not$ls180.v:2831$42 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_libresoc_ibus_cyc - connect \Y $not$ls180.v:2818$26_Y + connect \A \main_interface0_converted_interface_cyc + connect \Y $not$ls180.v:2831$42_Y end - attribute \src "ls180.v:2857.61-2857.94" - cell $not $not$ls180.v:2857$31 + attribute \src "ls180.v:2870.48-2870.69" + cell $not $not$ls180.v:2870$47 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_converter0_skip - connect \Y $not$ls180.v:2857$31_Y + connect \A \main_converter0_skip + connect \Y $not$ls180.v:2870$47_Y end - attribute \src "ls180.v:2858.61-2858.94" - cell $not $not$ls180.v:2858$32 + attribute \src "ls180.v:2871.48-2871.69" + cell $not $not$ls180.v:2871$48 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_converter0_skip - connect \Y $not$ls180.v:2858$32_Y + connect \A \main_converter0_skip + connect \Y $not$ls180.v:2871$48_Y end - attribute \src "ls180.v:2878.45-2878.80" - cell $not $not$ls180.v:2878$37 + attribute \src "ls180.v:2891.33-2891.73" + cell $not $not$ls180.v:2891$53 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_libresoc_dbus_cyc - connect \Y $not$ls180.v:2878$37_Y + connect \A \main_interface1_converted_interface_cyc + connect \Y $not$ls180.v:2891$53_Y end - attribute \src "ls180.v:2917.61-2917.94" - cell $not $not$ls180.v:2917$42 + attribute \src "ls180.v:2930.48-2930.69" + cell $not $not$ls180.v:2930$58 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_converter1_skip - connect \Y $not$ls180.v:2917$42_Y + connect \A \main_converter1_skip + connect \Y $not$ls180.v:2930$58_Y end - attribute \src "ls180.v:2918.61-2918.94" - cell $not $not$ls180.v:2918$43 + attribute \src "ls180.v:2931.48-2931.69" + cell $not $not$ls180.v:2931$59 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_converter1_skip - connect \Y $not$ls180.v:2918$43_Y + connect \A \main_converter1_skip + connect \Y $not$ls180.v:2931$59_Y end - attribute \src "ls180.v:2938.45-2938.83" - cell $not $not$ls180.v:2938$48 + attribute \src "ls180.v:2951.36-2951.79" + cell $not $not$ls180.v:2951$64 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_libresoc_jtag_wb_cyc - connect \Y $not$ls180.v:2938$48_Y + connect \A \main_socbushandler_converted_interface_cyc + connect \Y $not$ls180.v:2951$64_Y end - attribute \src "ls180.v:2977.61-2977.94" - cell $not $not$ls180.v:2977$53 + attribute \src "ls180.v:2990.27-2990.51" + cell $not $not$ls180.v:2990$69 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_converter2_skip - connect \Y $not$ls180.v:2977$53_Y + connect \A \main_socbushandler_skip + connect \Y $not$ls180.v:2990$69_Y end - attribute \src "ls180.v:2978.61-2978.94" - cell $not $not$ls180.v:2978$54 + attribute \src "ls180.v:2991.27-2991.51" + cell $not $not$ls180.v:2991$70 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_converter2_skip - connect \Y $not$ls180.v:2978$54_Y + connect \A \main_socbushandler_skip + connect \Y $not$ls180.v:2991$70_Y end - attribute \src "ls180.v:3150.34-3150.64" - cell $not $not$ls180.v:3150$117 + attribute \src "ls180.v:3179.34-3179.64" + cell $not $not$ls180.v:3179$181 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_command_storage [0] - connect \Y $not$ls180.v:3150$117_Y + connect \Y $not$ls180.v:3179$181_Y end - attribute \src "ls180.v:3151.31-3151.61" - cell $not $not$ls180.v:3151$118 + attribute \src "ls180.v:3180.31-3180.61" + cell $not $not$ls180.v:3180$182 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_command_storage [1] - connect \Y $not$ls180.v:3151$118_Y + connect \Y $not$ls180.v:3180$182_Y end - attribute \src "ls180.v:3152.32-3152.62" - cell $not $not$ls180.v:3152$119 + attribute \src "ls180.v:3181.32-3181.62" + cell $not $not$ls180.v:3181$183 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_command_storage [2] - connect \Y $not$ls180.v:3152$119_Y + connect \Y $not$ls180.v:3181$183_Y end - attribute \src "ls180.v:3153.32-3153.62" - cell $not $not$ls180.v:3153$120 + attribute \src "ls180.v:3182.32-3182.62" + cell $not $not$ls180.v:3182$184 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_command_storage [3] - connect \Y $not$ls180.v:3153$120_Y + connect \Y $not$ls180.v:3182$184_Y end - attribute \src "ls180.v:3195.33-3195.56" - cell $not $not$ls180.v:3195$123 + attribute \src "ls180.v:3224.33-3224.56" + cell $not $not$ls180.v:3224$187 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_timer_done0 - connect \Y $not$ls180.v:3195$123_Y + connect \Y $not$ls180.v:3224$187_Y end - attribute \src "ls180.v:3296.58-3296.106" - cell $not $not$ls180.v:3296$153 + attribute \src "ls180.v:3325.58-3325.106" + cell $not $not$ls180.v:3325$217 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_source_valid - connect \Y $not$ls180.v:3296$153_Y + connect \Y $not$ls180.v:3325$217_Y end - attribute \src "ls180.v:3350.9-3350.45" - cell $not $not$ls180.v:3350$158 + attribute \src "ls180.v:3379.9-3379.45" + cell $not $not$ls180.v:3379$222 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_refresh_req - connect \Y $not$ls180.v:3350$158_Y + connect \Y $not$ls180.v:3379$222_Y end - attribute \src "ls180.v:3453.58-3453.106" - cell $not $not$ls180.v:3453$183 + attribute \src "ls180.v:3482.58-3482.106" + cell $not $not$ls180.v:3482$247 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_source_valid - connect \Y $not$ls180.v:3453$183_Y + connect \Y $not$ls180.v:3482$247_Y end - attribute \src "ls180.v:3507.9-3507.45" - cell $not $not$ls180.v:3507$188 + attribute \src "ls180.v:3536.9-3536.45" + cell $not $not$ls180.v:3536$252 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_refresh_req - connect \Y $not$ls180.v:3507$188_Y + connect \Y $not$ls180.v:3536$252_Y end - attribute \src "ls180.v:3610.58-3610.106" - cell $not $not$ls180.v:3610$213 + attribute \src "ls180.v:3639.58-3639.106" + cell $not $not$ls180.v:3639$277 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_source_valid - connect \Y $not$ls180.v:3610$213_Y + connect \Y $not$ls180.v:3639$277_Y end - attribute \src "ls180.v:3664.9-3664.45" - cell $not $not$ls180.v:3664$218 + attribute \src "ls180.v:3693.9-3693.45" + cell $not $not$ls180.v:3693$282 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_refresh_req - connect \Y $not$ls180.v:3664$218_Y + connect \Y $not$ls180.v:3693$282_Y end - attribute \src "ls180.v:3767.58-3767.106" - cell $not $not$ls180.v:3767$243 + attribute \src "ls180.v:3796.58-3796.106" + cell $not $not$ls180.v:3796$307 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_source_valid - connect \Y $not$ls180.v:3767$243_Y + connect \Y $not$ls180.v:3796$307_Y end - attribute \src "ls180.v:3821.9-3821.45" - cell $not $not$ls180.v:3821$248 + attribute \src "ls180.v:3850.9-3850.45" + cell $not $not$ls180.v:3850$312 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_refresh_req - connect \Y $not$ls180.v:3821$248_Y + connect \Y $not$ls180.v:3850$312_Y end - attribute \src "ls180.v:3863.149-3863.187" - cell $not $not$ls180.v:3863$251 + attribute \src "ls180.v:3892.149-3892.187" + cell $not $not$ls180.v:3892$315 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_cas - connect \Y $not$ls180.v:3863$251_Y + connect \Y $not$ls180.v:3892$315_Y end - attribute \src "ls180.v:3863.193-3863.230" - cell $not $not$ls180.v:3863$253 + attribute \src "ls180.v:3892.193-3892.230" + cell $not $not$ls180.v:3892$317 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_we - connect \Y $not$ls180.v:3863$253_Y + connect \Y $not$ls180.v:3892$317_Y end - attribute \src "ls180.v:3864.149-3864.187" - cell $not $not$ls180.v:3864$257 + attribute \src "ls180.v:3893.149-3893.187" + cell $not $not$ls180.v:3893$321 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_cas - connect \Y $not$ls180.v:3864$257_Y + connect \Y $not$ls180.v:3893$321_Y end - attribute \src "ls180.v:3864.193-3864.230" - cell $not $not$ls180.v:3864$259 + attribute \src "ls180.v:3893.193-3893.230" + cell $not $not$ls180.v:3893$323 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_we - connect \Y $not$ls180.v:3864$259_Y + connect \Y $not$ls180.v:3893$323_Y end - attribute \src "ls180.v:3880.43-3880.73" - cell $not $not$ls180.v:3880$287 + attribute \src "ls180.v:3909.43-3909.73" + cell $not $not$ls180.v:3909$351 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \main_sdram_interface_wdata_we - connect \Y $not$ls180.v:3880$287_Y + connect \Y $not$ls180.v:3909$351_Y end - attribute \src "ls180.v:3883.205-3883.245" - cell $not $not$ls180.v:3883$290 + attribute \src "ls180.v:3912.205-3912.245" + cell $not $not$ls180.v:3912$354 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_payload_cas - connect \Y $not$ls180.v:3883$290_Y + connect \Y $not$ls180.v:3912$354_Y end - attribute \src "ls180.v:3883.251-3883.290" - cell $not $not$ls180.v:3883$292 + attribute \src "ls180.v:3912.251-3912.290" + cell $not $not$ls180.v:3912$356 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_payload_we - connect \Y $not$ls180.v:3883$292_Y + connect \Y $not$ls180.v:3912$356_Y end - attribute \src "ls180.v:3883.159-3883.292" - cell $not $not$ls180.v:3883$294 + attribute \src "ls180.v:3912.159-3912.292" + cell $not $not$ls180.v:3912$358 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3883$293_Y - connect \Y $not$ls180.v:3883$294_Y + connect \A $and$ls180.v:3912$357_Y + connect \Y $not$ls180.v:3912$358_Y end - attribute \src "ls180.v:3884.205-3884.245" - cell $not $not$ls180.v:3884$303 + attribute \src "ls180.v:3913.205-3913.245" + cell $not $not$ls180.v:3913$367 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_payload_cas - connect \Y $not$ls180.v:3884$303_Y + connect \Y $not$ls180.v:3913$367_Y end - attribute \src "ls180.v:3884.251-3884.290" - cell $not $not$ls180.v:3884$305 + attribute \src "ls180.v:3913.251-3913.290" + cell $not $not$ls180.v:3913$369 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_payload_we - connect \Y $not$ls180.v:3884$305_Y + connect \Y $not$ls180.v:3913$369_Y end - attribute \src "ls180.v:3884.159-3884.292" - cell $not $not$ls180.v:3884$307 + attribute \src "ls180.v:3913.159-3913.292" + cell $not $not$ls180.v:3913$371 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3884$306_Y - connect \Y $not$ls180.v:3884$307_Y + connect \A $and$ls180.v:3913$370_Y + connect \Y $not$ls180.v:3913$371_Y end - attribute \src "ls180.v:3885.205-3885.245" - cell $not $not$ls180.v:3885$316 + attribute \src "ls180.v:3914.205-3914.245" + cell $not $not$ls180.v:3914$380 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_payload_cas - connect \Y $not$ls180.v:3885$316_Y + connect \Y $not$ls180.v:3914$380_Y end - attribute \src "ls180.v:3885.251-3885.290" - cell $not $not$ls180.v:3885$318 + attribute \src "ls180.v:3914.251-3914.290" + cell $not $not$ls180.v:3914$382 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_payload_we - connect \Y $not$ls180.v:3885$318_Y + connect \Y $not$ls180.v:3914$382_Y end - attribute \src "ls180.v:3885.159-3885.292" - cell $not $not$ls180.v:3885$320 + attribute \src "ls180.v:3914.159-3914.292" + cell $not $not$ls180.v:3914$384 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3885$319_Y - connect \Y $not$ls180.v:3885$320_Y + connect \A $and$ls180.v:3914$383_Y + connect \Y $not$ls180.v:3914$384_Y end - attribute \src "ls180.v:3886.205-3886.245" - cell $not $not$ls180.v:3886$329 + attribute \src "ls180.v:3915.205-3915.245" + cell $not $not$ls180.v:3915$393 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_payload_cas - connect \Y $not$ls180.v:3886$329_Y + connect \Y $not$ls180.v:3915$393_Y end - attribute \src "ls180.v:3886.251-3886.290" - cell $not $not$ls180.v:3886$331 + attribute \src "ls180.v:3915.251-3915.290" + cell $not $not$ls180.v:3915$395 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_payload_we - connect \Y $not$ls180.v:3886$331_Y + connect \Y $not$ls180.v:3915$395_Y end - attribute \src "ls180.v:3886.159-3886.292" - cell $not $not$ls180.v:3886$333 + attribute \src "ls180.v:3915.159-3915.292" + cell $not $not$ls180.v:3915$397 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3886$332_Y - connect \Y $not$ls180.v:3886$333_Y + connect \A $and$ls180.v:3915$396_Y + connect \Y $not$ls180.v:3915$397_Y end - attribute \src "ls180.v:3913.71-3913.103" - cell $not $not$ls180.v:3913$344 + attribute \src "ls180.v:3942.71-3942.103" + cell $not $not$ls180.v:3942$408 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_cmd_cmd_valid - connect \Y $not$ls180.v:3913$344_Y + connect \Y $not$ls180.v:3942$408_Y end - attribute \src "ls180.v:3916.205-3916.245" - cell $not $not$ls180.v:3916$348 + attribute \src "ls180.v:3945.205-3945.245" + cell $not $not$ls180.v:3945$412 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_payload_cas - connect \Y $not$ls180.v:3916$348_Y + connect \Y $not$ls180.v:3945$412_Y end - attribute \src "ls180.v:3916.251-3916.290" - cell $not $not$ls180.v:3916$350 + attribute \src "ls180.v:3945.251-3945.290" + cell $not $not$ls180.v:3945$414 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_payload_we - connect \Y $not$ls180.v:3916$350_Y + connect \Y $not$ls180.v:3945$414_Y end - attribute \src "ls180.v:3916.159-3916.292" - cell $not $not$ls180.v:3916$352 + attribute \src "ls180.v:3945.159-3945.292" + cell $not $not$ls180.v:3945$416 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3916$351_Y - connect \Y $not$ls180.v:3916$352_Y + connect \A $and$ls180.v:3945$415_Y + connect \Y $not$ls180.v:3945$416_Y end - attribute \src "ls180.v:3917.205-3917.245" - cell $not $not$ls180.v:3917$361 + attribute \src "ls180.v:3946.205-3946.245" + cell $not $not$ls180.v:3946$425 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_payload_cas - connect \Y $not$ls180.v:3917$361_Y + connect \Y $not$ls180.v:3946$425_Y end - attribute \src "ls180.v:3917.251-3917.290" - cell $not $not$ls180.v:3917$363 + attribute \src "ls180.v:3946.251-3946.290" + cell $not $not$ls180.v:3946$427 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_payload_we - connect \Y $not$ls180.v:3917$363_Y + connect \Y $not$ls180.v:3946$427_Y end - attribute \src "ls180.v:3917.159-3917.292" - cell $not $not$ls180.v:3917$365 + attribute \src "ls180.v:3946.159-3946.292" + cell $not $not$ls180.v:3946$429 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3917$364_Y - connect \Y $not$ls180.v:3917$365_Y + connect \A $and$ls180.v:3946$428_Y + connect \Y $not$ls180.v:3946$429_Y end - attribute \src "ls180.v:3918.205-3918.245" - cell $not $not$ls180.v:3918$374 + attribute \src "ls180.v:3947.205-3947.245" + cell $not $not$ls180.v:3947$438 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_payload_cas - connect \Y $not$ls180.v:3918$374_Y + connect \Y $not$ls180.v:3947$438_Y end - attribute \src "ls180.v:3918.251-3918.290" - cell $not $not$ls180.v:3918$376 + attribute \src "ls180.v:3947.251-3947.290" + cell $not $not$ls180.v:3947$440 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_payload_we - connect \Y $not$ls180.v:3918$376_Y + connect \Y $not$ls180.v:3947$440_Y end - attribute \src "ls180.v:3918.159-3918.292" - cell $not $not$ls180.v:3918$378 + attribute \src "ls180.v:3947.159-3947.292" + cell $not $not$ls180.v:3947$442 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3918$377_Y - connect \Y $not$ls180.v:3918$378_Y + connect \A $and$ls180.v:3947$441_Y + connect \Y $not$ls180.v:3947$442_Y end - attribute \src "ls180.v:3919.205-3919.245" - cell $not $not$ls180.v:3919$387 + attribute \src "ls180.v:3948.205-3948.245" + cell $not $not$ls180.v:3948$451 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_payload_cas - connect \Y $not$ls180.v:3919$387_Y + connect \Y $not$ls180.v:3948$451_Y end - attribute \src "ls180.v:3919.251-3919.290" - cell $not $not$ls180.v:3919$389 + attribute \src "ls180.v:3948.251-3948.290" + cell $not $not$ls180.v:3948$453 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_payload_we - connect \Y $not$ls180.v:3919$389_Y + connect \Y $not$ls180.v:3948$453_Y end - attribute \src "ls180.v:3919.159-3919.292" - cell $not $not$ls180.v:3919$391 + attribute \src "ls180.v:3948.159-3948.292" + cell $not $not$ls180.v:3948$455 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3919$390_Y - connect \Y $not$ls180.v:3919$391_Y + connect \A $and$ls180.v:3948$454_Y + connect \Y $not$ls180.v:3948$455_Y end - attribute \src "ls180.v:3982.71-3982.103" - cell $not $not$ls180.v:3982$430 + attribute \src "ls180.v:4011.71-4011.103" + cell $not $not$ls180.v:4011$494 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid - connect \Y $not$ls180.v:3982$430_Y + connect \Y $not$ls180.v:4011$494_Y end - attribute \src "ls180.v:4003.112-4003.150" - cell $not $not$ls180.v:4003$433 + attribute \src "ls180.v:4032.112-4032.150" + cell $not $not$ls180.v:4032$497 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_cas - connect \Y $not$ls180.v:4003$433_Y + connect \Y $not$ls180.v:4032$497_Y end - attribute \src "ls180.v:4003.156-4003.193" - cell $not $not$ls180.v:4003$435 + attribute \src "ls180.v:4032.156-4032.193" + cell $not $not$ls180.v:4032$499 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_we - connect \Y $not$ls180.v:4003$435_Y + connect \Y $not$ls180.v:4032$499_Y end - attribute \src "ls180.v:4003.68-4003.195" - cell $not $not$ls180.v:4003$437 + attribute \src "ls180.v:4032.68-4032.195" + cell $not $not$ls180.v:4032$501 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4003$436_Y - connect \Y $not$ls180.v:4003$437_Y + connect \A $and$ls180.v:4032$500_Y + connect \Y $not$ls180.v:4032$501_Y end - attribute \src "ls180.v:4011.11-4011.38" - cell $not $not$ls180.v:4011$440 + attribute \src "ls180.v:4040.11-4040.38" + cell $not $not$ls180.v:4040$504 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_write_available - connect \Y $not$ls180.v:4011$440_Y + connect \Y $not$ls180.v:4040$504_Y end - attribute \src "ls180.v:4041.112-4041.150" - cell $not $not$ls180.v:4041$442 + attribute \src "ls180.v:4070.112-4070.150" + cell $not $not$ls180.v:4070$506 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_cas - connect \Y $not$ls180.v:4041$442_Y + connect \Y $not$ls180.v:4070$506_Y end - attribute \src "ls180.v:4041.156-4041.193" - cell $not $not$ls180.v:4041$444 + attribute \src "ls180.v:4070.156-4070.193" + cell $not $not$ls180.v:4070$508 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_we - connect \Y $not$ls180.v:4041$444_Y + connect \Y $not$ls180.v:4070$508_Y end - attribute \src "ls180.v:4041.68-4041.195" - cell $not $not$ls180.v:4041$446 + attribute \src "ls180.v:4070.68-4070.195" + cell $not $not$ls180.v:4070$510 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4041$445_Y - connect \Y $not$ls180.v:4041$446_Y + connect \A $and$ls180.v:4070$509_Y + connect \Y $not$ls180.v:4070$510_Y end - attribute \src "ls180.v:4049.11-4049.37" - cell $not $not$ls180.v:4049$449 + attribute \src "ls180.v:4078.11-4078.37" + cell $not $not$ls180.v:4078$513 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_read_available - connect \Y $not$ls180.v:4049$449_Y + connect \Y $not$ls180.v:4078$513_Y end - attribute \src "ls180.v:4059.87-4059.331" - cell $not $not$ls180.v:4059$461 + attribute \src "ls180.v:4088.87-4088.331" + cell $not $not$ls180.v:4088$525 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4059$460_Y - connect \Y $not$ls180.v:4059$461_Y + connect \A $or$ls180.v:4088$524_Y + connect \Y $not$ls180.v:4088$525_Y end - attribute \src "ls180.v:4060.35-4060.68" - cell $not $not$ls180.v:4060$464 + attribute \src "ls180.v:4089.35-4089.68" + cell $not $not$ls180.v:4089$528 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank0_valid - connect \Y $not$ls180.v:4060$464_Y + connect \Y $not$ls180.v:4089$528_Y end - attribute \src "ls180.v:4060.73-4060.105" - cell $not $not$ls180.v:4060$465 + attribute \src "ls180.v:4089.73-4089.105" + cell $not $not$ls180.v:4089$529 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank0_lock - connect \Y $not$ls180.v:4060$465_Y + connect \Y $not$ls180.v:4089$529_Y end - attribute \src "ls180.v:4064.87-4064.331" - cell $not $not$ls180.v:4064$477 + attribute \src "ls180.v:4093.87-4093.331" + cell $not $not$ls180.v:4093$541 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4064$476_Y - connect \Y $not$ls180.v:4064$477_Y + connect \A $or$ls180.v:4093$540_Y + connect \Y $not$ls180.v:4093$541_Y end - attribute \src "ls180.v:4065.35-4065.68" - cell $not $not$ls180.v:4065$480 + attribute \src "ls180.v:4094.35-4094.68" + cell $not $not$ls180.v:4094$544 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank1_valid - connect \Y $not$ls180.v:4065$480_Y + connect \Y $not$ls180.v:4094$544_Y end - attribute \src "ls180.v:4065.73-4065.105" - cell $not $not$ls180.v:4065$481 + attribute \src "ls180.v:4094.73-4094.105" + cell $not $not$ls180.v:4094$545 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank1_lock - connect \Y $not$ls180.v:4065$481_Y + connect \Y $not$ls180.v:4094$545_Y end - attribute \src "ls180.v:4069.87-4069.331" - cell $not $not$ls180.v:4069$493 + attribute \src "ls180.v:4098.87-4098.331" + cell $not $not$ls180.v:4098$557 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4069$492_Y - connect \Y $not$ls180.v:4069$493_Y + connect \A $or$ls180.v:4098$556_Y + connect \Y $not$ls180.v:4098$557_Y end - attribute \src "ls180.v:4070.35-4070.68" - cell $not $not$ls180.v:4070$496 + attribute \src "ls180.v:4099.35-4099.68" + cell $not $not$ls180.v:4099$560 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank2_valid - connect \Y $not$ls180.v:4070$496_Y + connect \Y $not$ls180.v:4099$560_Y end - attribute \src "ls180.v:4070.73-4070.105" - cell $not $not$ls180.v:4070$497 + attribute \src "ls180.v:4099.73-4099.105" + cell $not $not$ls180.v:4099$561 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank2_lock - connect \Y $not$ls180.v:4070$497_Y + connect \Y $not$ls180.v:4099$561_Y end - attribute \src "ls180.v:4074.87-4074.331" - cell $not $not$ls180.v:4074$509 + attribute \src "ls180.v:4103.87-4103.331" + cell $not $not$ls180.v:4103$573 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4074$508_Y - connect \Y $not$ls180.v:4074$509_Y + connect \A $or$ls180.v:4103$572_Y + connect \Y $not$ls180.v:4103$573_Y end - attribute \src "ls180.v:4075.35-4075.68" - cell $not $not$ls180.v:4075$512 + attribute \src "ls180.v:4104.35-4104.68" + cell $not $not$ls180.v:4104$576 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank3_valid - connect \Y $not$ls180.v:4075$512_Y + connect \Y $not$ls180.v:4104$576_Y end - attribute \src "ls180.v:4075.73-4075.105" - cell $not $not$ls180.v:4075$513 + attribute \src "ls180.v:4104.73-4104.105" + cell $not $not$ls180.v:4104$577 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank3_lock - connect \Y $not$ls180.v:4075$513_Y + connect \Y $not$ls180.v:4104$577_Y end - attribute \src "ls180.v:4079.128-4079.372" - cell $not $not$ls180.v:4079$526 + attribute \src "ls180.v:4108.128-4108.372" + cell $not $not$ls180.v:4108$590 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4079$525_Y - connect \Y $not$ls180.v:4079$526_Y + connect \A $or$ls180.v:4108$589_Y + connect \Y $not$ls180.v:4108$590_Y end - attribute \src "ls180.v:4079.502-4079.746" - cell $not $not$ls180.v:4079$542 + attribute \src "ls180.v:4108.502-4108.746" + cell $not $not$ls180.v:4108$606 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4079$541_Y - connect \Y $not$ls180.v:4079$542_Y + connect \A $or$ls180.v:4108$605_Y + connect \Y $not$ls180.v:4108$606_Y end - attribute \src "ls180.v:4079.876-4079.1120" - cell $not $not$ls180.v:4079$558 + attribute \src "ls180.v:4108.876-4108.1120" + cell $not $not$ls180.v:4108$622 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4079$557_Y - connect \Y $not$ls180.v:4079$558_Y + connect \A $or$ls180.v:4108$621_Y + connect \Y $not$ls180.v:4108$622_Y end - attribute \src "ls180.v:4079.1250-4079.1494" - cell $not $not$ls180.v:4079$574 + attribute \src "ls180.v:4108.1250-4108.1494" + cell $not $not$ls180.v:4108$638 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4079$573_Y - connect \Y $not$ls180.v:4079$574_Y + connect \A $or$ls180.v:4108$637_Y + connect \Y $not$ls180.v:4108$638_Y end - attribute \src "ls180.v:4101.32-4101.50" - cell $not $not$ls180.v:4101$580 + attribute \src "ls180.v:4130.32-4130.50" + cell $not $not$ls180.v:4130$644 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_wb_sdram_cyc - connect \Y $not$ls180.v:4101$580_Y + connect \Y $not$ls180.v:4130$644_Y end - attribute \src "ls180.v:4140.30-4140.50" - cell $not $not$ls180.v:4140$585 + attribute \src "ls180.v:4169.30-4169.50" + cell $not $not$ls180.v:4169$649 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_converter_skip - connect \Y $not$ls180.v:4140$585_Y + connect \Y $not$ls180.v:4169$649_Y end - attribute \src "ls180.v:4141.30-4141.50" - cell $not $not$ls180.v:4141$586 + attribute \src "ls180.v:4170.30-4170.50" + cell $not $not$ls180.v:4170$650 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_converter_skip - connect \Y $not$ls180.v:4141$586_Y + connect \Y $not$ls180.v:4170$650_Y end - attribute \src "ls180.v:4166.27-4166.48" - cell $not $not$ls180.v:4166$592 + attribute \src "ls180.v:4195.27-4195.48" + cell $not $not$ls180.v:4195$656 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_litedram_wb_cyc - connect \Y $not$ls180.v:4166$592_Y + connect \Y $not$ls180.v:4195$656_Y end - attribute \src "ls180.v:4167.30-4167.50" - cell $not $not$ls180.v:4167$593 + attribute \src "ls180.v:4196.30-4196.50" + cell $not $not$ls180.v:4196$657 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_litedram_wb_we - connect \Y $not$ls180.v:4167$593_Y + connect \Y $not$ls180.v:4196$657_Y end - attribute \src "ls180.v:4168.80-4168.98" - cell $not $not$ls180.v:4168$595 + attribute \src "ls180.v:4197.80-4197.98" + cell $not $not$ls180.v:4197$659 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_cmd_consumed - connect \Y $not$ls180.v:4168$595_Y + connect \Y $not$ls180.v:4197$659_Y end - attribute \src "ls180.v:4169.107-4169.127" - cell $not $not$ls180.v:4169$599 + attribute \src "ls180.v:4198.107-4198.127" + cell $not $not$ls180.v:4198$663 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_wdata_consumed - connect \Y $not$ls180.v:4169$599_Y + connect \Y $not$ls180.v:4198$663_Y end - attribute \src "ls180.v:4170.78-4170.103" - cell $not $not$ls180.v:4170$602 + attribute \src "ls180.v:4199.78-4199.103" + cell $not $not$ls180.v:4199$666 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_we - connect \Y $not$ls180.v:4170$602_Y + connect \Y $not$ls180.v:4199$666_Y end - attribute \src "ls180.v:4171.91-4171.111" - cell $not $not$ls180.v:4171$605 + attribute \src "ls180.v:4200.91-4200.111" + cell $not $not$ls180.v:4200$669 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_litedram_wb_we - connect \Y $not$ls180.v:4171$605_Y + connect \Y $not$ls180.v:4200$669_Y end - attribute \src "ls180.v:4187.35-4187.64" - cell $not $not$ls180.v:4187$614 + attribute \src "ls180.v:4216.35-4216.64" + cell $not $not$ls180.v:4216$678 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_sink_ready - connect \Y $not$ls180.v:4187$614_Y + connect \Y $not$ls180.v:4216$678_Y end - attribute \src "ls180.v:4188.36-4188.67" - cell $not $not$ls180.v:4188$615 + attribute \src "ls180.v:4217.36-4217.67" + cell $not $not$ls180.v:4217$679 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_source_valid - connect \Y $not$ls180.v:4188$615_Y + connect \Y $not$ls180.v:4217$679_Y end - attribute \src "ls180.v:4194.32-4194.61" - cell $not $not$ls180.v:4194$616 + attribute \src "ls180.v:4223.32-4223.61" + cell $not $not$ls180.v:4223$680 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_sink_ready - connect \Y $not$ls180.v:4194$616_Y + connect \Y $not$ls180.v:4223$680_Y end - attribute \src "ls180.v:4200.36-4200.67" - cell $not $not$ls180.v:4200$617 + attribute \src "ls180.v:4229.36-4229.67" + cell $not $not$ls180.v:4229$681 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_source_valid - connect \Y $not$ls180.v:4200$617_Y + connect \Y $not$ls180.v:4229$681_Y end - attribute \src "ls180.v:4201.35-4201.64" - cell $not $not$ls180.v:4201$618 + attribute \src "ls180.v:4230.35-4230.64" + cell $not $not$ls180.v:4230$682 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_sink_ready - connect \Y $not$ls180.v:4201$618_Y + connect \Y $not$ls180.v:4230$682_Y end - attribute \src "ls180.v:4204.32-4204.63" - cell $not $not$ls180.v:4204$621 + attribute \src "ls180.v:4233.32-4233.63" + cell $not $not$ls180.v:4233$685 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_source_valid - connect \Y $not$ls180.v:4204$621_Y + connect \Y $not$ls180.v:4233$685_Y end - attribute \src "ls180.v:4242.81-4242.108" - cell $not $not$ls180.v:4242$631 + attribute \src "ls180.v:4271.81-4271.108" + cell $not $not$ls180.v:4271$695 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_readable - connect \Y $not$ls180.v:4242$631_Y + connect \Y $not$ls180.v:4271$695_Y end - attribute \src "ls180.v:4272.81-4272.108" - cell $not $not$ls180.v:4272$642 + attribute \src "ls180.v:4301.81-4301.108" + cell $not $not$ls180.v:4301$706 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_readable - connect \Y $not$ls180.v:4272$642_Y + connect \Y $not$ls180.v:4301$706_Y end - attribute \src "ls180.v:4472.60-4472.85" - cell $not $not$ls180.v:4472$691 + attribute \src "ls180.v:4512.60-4512.85" + cell $not $not$ls180.v:4512$757 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_clocker_clk_d - connect \Y $not$ls180.v:4472$691_Y + connect \Y $not$ls180.v:4512$757_Y end - attribute \src "ls180.v:4613.54-4613.96" - cell $not $not$ls180.v:4613$705 + attribute \src "ls180.v:4653.54-4653.96" + cell $not $not$ls180.v:4653$771 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_converter_strobe_all - connect \Y $not$ls180.v:4613$705_Y + connect \Y $not$ls180.v:4653$771_Y end - attribute \src "ls180.v:4616.48-4616.86" - cell $not $not$ls180.v:4616$708 + attribute \src "ls180.v:4656.48-4656.86" + cell $not $not$ls180.v:4656$774 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_buf_source_valid - connect \Y $not$ls180.v:4616$708_Y + connect \Y $not$ls180.v:4656$774_Y end - attribute \src "ls180.v:4740.55-4740.98" - cell $not $not$ls180.v:4740$726 + attribute \src "ls180.v:4780.55-4780.98" + cell $not $not$ls180.v:4780$792 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_converter_strobe_all - connect \Y $not$ls180.v:4740$726_Y + connect \Y $not$ls180.v:4780$792_Y end - attribute \src "ls180.v:4743.49-4743.88" - cell $not $not$ls180.v:4743$729 + attribute \src "ls180.v:4783.49-4783.88" + cell $not $not$ls180.v:4783$795 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_buf_source_valid - connect \Y $not$ls180.v:4743$729_Y + connect \Y $not$ls180.v:4783$795_Y end - attribute \src "ls180.v:4793.30-4793.58" - cell $not $not$ls180.v:4793$735 + attribute \src "ls180.v:4833.30-4833.58" + cell $not $not$ls180.v:4833$801 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_sink_valid - connect \Y $not$ls180.v:4793$735_Y + connect \Y $not$ls180.v:4833$801_Y end - attribute \src "ls180.v:4874.56-4874.100" - cell $not $not$ls180.v:4874$741 + attribute \src "ls180.v:4914.56-4914.100" + cell $not $not$ls180.v:4914$807 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_converter_strobe_all - connect \Y $not$ls180.v:4874$741_Y + connect \Y $not$ls180.v:4914$807_Y end - attribute \src "ls180.v:4877.50-4877.90" - cell $not $not$ls180.v:4877$744 + attribute \src "ls180.v:4917.50-4917.90" + cell $not $not$ls180.v:4917$810 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_buf_source_valid - connect \Y $not$ls180.v:4877$744_Y + connect \Y $not$ls180.v:4917$810_Y end - attribute \src "ls180.v:4993.42-4993.74" - cell $not $not$ls180.v:4993$760 + attribute \src "ls180.v:5033.42-5033.74" + cell $not $not$ls180.v:5033$826 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_valid - connect \Y $not$ls180.v:4993$760_Y + connect \Y $not$ls180.v:5033$826_Y end - attribute \src "ls180.v:5517.50-5517.88" - cell $not $not$ls180.v:5517$1045 + attribute \src "ls180.v:5557.50-5557.88" + cell $not $not$ls180.v:5557$1111 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_converter_strobe_all - connect \Y $not$ls180.v:5517$1045_Y + connect \Y $not$ls180.v:5557$1111_Y end - attribute \src "ls180.v:5529.52-5529.102" - cell $not $not$ls180.v:5529$1048 + attribute \src "ls180.v:5569.52-5569.102" + cell $not $not$ls180.v:5569$1114 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_wishbonedmawriter_enable_storage - connect \Y $not$ls180.v:5529$1048_Y + connect \Y $not$ls180.v:5569$1114_Y end - attribute \src "ls180.v:5588.38-5588.74" - cell $not $not$ls180.v:5588$1055 + attribute \src "ls180.v:5628.38-5628.74" + cell $not $not$ls180.v:5628$1121 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_dma_enable_storage - connect \Y $not$ls180.v:5588$1055_Y + connect \Y $not$ls180.v:5628$1121_Y end - attribute \src "ls180.v:5857.69-5857.88" - cell $not $not$ls180.v:5857$1125 + attribute \src "ls180.v:5909.69-5909.88" + cell $not $not$ls180.v:5909$1191 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_shared_ack - connect \Y $not$ls180.v:5857$1125_Y + connect \Y $not$ls180.v:5909$1191_Y end - attribute \src "ls180.v:5874.63-5874.94" - cell $not $not$ls180.v:5874$1155 + attribute \src "ls180.v:5926.63-5926.94" + cell $not $not$ls180.v:5926$1221 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:5874$1155_Y + connect \Y $not$ls180.v:5926$1221_Y end - attribute \src "ls180.v:5877.65-5877.96" - cell $not $not$ls180.v:5877$1162 + attribute \src "ls180.v:5929.65-5929.96" + cell $not $not$ls180.v:5929$1228 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:5877$1162_Y + connect \Y $not$ls180.v:5929$1228_Y end - attribute \src "ls180.v:5880.65-5880.96" - cell $not $not$ls180.v:5880$1169 + attribute \src "ls180.v:5932.65-5932.96" + cell $not $not$ls180.v:5932$1235 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:5880$1169_Y + connect \Y $not$ls180.v:5932$1235_Y end - attribute \src "ls180.v:5883.65-5883.96" - cell $not $not$ls180.v:5883$1176 + attribute \src "ls180.v:5935.65-5935.96" + cell $not $not$ls180.v:5935$1242 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:5883$1176_Y + connect \Y $not$ls180.v:5935$1242_Y end - attribute \src "ls180.v:5886.65-5886.96" - cell $not $not$ls180.v:5886$1183 + attribute \src "ls180.v:5938.65-5938.96" + cell $not $not$ls180.v:5938$1249 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:5886$1183_Y + connect \Y $not$ls180.v:5938$1249_Y end - attribute \src "ls180.v:5889.68-5889.99" - cell $not $not$ls180.v:5889$1190 + attribute \src "ls180.v:5941.68-5941.99" + cell $not $not$ls180.v:5941$1256 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:5889$1190_Y + connect \Y $not$ls180.v:5941$1256_Y end - attribute \src "ls180.v:5892.68-5892.99" - cell $not $not$ls180.v:5892$1197 + attribute \src "ls180.v:5944.68-5944.99" + cell $not $not$ls180.v:5944$1263 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:5892$1197_Y + connect \Y $not$ls180.v:5944$1263_Y end - attribute \src "ls180.v:5895.68-5895.99" - cell $not $not$ls180.v:5895$1204 + attribute \src "ls180.v:5947.68-5947.99" + cell $not $not$ls180.v:5947$1270 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:5895$1204_Y + connect \Y $not$ls180.v:5947$1270_Y end - attribute \src "ls180.v:5898.68-5898.99" - cell $not $not$ls180.v:5898$1211 + attribute \src "ls180.v:5950.68-5950.99" + cell $not $not$ls180.v:5950$1277 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:5898$1211_Y + connect \Y $not$ls180.v:5950$1277_Y end - attribute \src "ls180.v:5912.60-5912.91" - cell $not $not$ls180.v:5912$1219 + attribute \src "ls180.v:5964.60-5964.91" + cell $not $not$ls180.v:5964$1285 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_we - connect \Y $not$ls180.v:5912$1219_Y + connect \Y $not$ls180.v:5964$1285_Y end - attribute \src "ls180.v:5915.60-5915.91" - cell $not $not$ls180.v:5915$1226 + attribute \src "ls180.v:5967.60-5967.91" + cell $not $not$ls180.v:5967$1292 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_we - connect \Y $not$ls180.v:5915$1226_Y + connect \Y $not$ls180.v:5967$1292_Y end - attribute \src "ls180.v:5918.60-5918.91" - cell $not $not$ls180.v:5918$1233 + attribute \src "ls180.v:5970.60-5970.91" + cell $not $not$ls180.v:5970$1299 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_we - connect \Y $not$ls180.v:5918$1233_Y + connect \Y $not$ls180.v:5970$1299_Y end - attribute \src "ls180.v:5921.60-5921.91" - cell $not $not$ls180.v:5921$1240 + attribute \src "ls180.v:5973.60-5973.91" + cell $not $not$ls180.v:5973$1306 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_we - connect \Y $not$ls180.v:5921$1240_Y + connect \Y $not$ls180.v:5973$1306_Y end - attribute \src "ls180.v:5924.61-5924.92" - cell $not $not$ls180.v:5924$1247 + attribute \src "ls180.v:5976.61-5976.92" + cell $not $not$ls180.v:5976$1313 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_we - connect \Y $not$ls180.v:5924$1247_Y + connect \Y $not$ls180.v:5976$1313_Y end - attribute \src "ls180.v:5927.61-5927.92" - cell $not $not$ls180.v:5927$1254 + attribute \src "ls180.v:5979.61-5979.92" + cell $not $not$ls180.v:5979$1320 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_we - connect \Y $not$ls180.v:5927$1254_Y + connect \Y $not$ls180.v:5979$1320_Y end - attribute \src "ls180.v:5938.59-5938.90" - cell $not $not$ls180.v:5938$1262 + attribute \src "ls180.v:5990.59-5990.90" + cell $not $not$ls180.v:5990$1328 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface2_bank_bus_we - connect \Y $not$ls180.v:5938$1262_Y + connect \Y $not$ls180.v:5990$1328_Y end - attribute \src "ls180.v:5941.58-5941.89" - cell $not $not$ls180.v:5941$1269 + attribute \src "ls180.v:5993.58-5993.89" + cell $not $not$ls180.v:5993$1335 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface2_bank_bus_we - connect \Y $not$ls180.v:5941$1269_Y + connect \Y $not$ls180.v:5993$1335_Y end - attribute \src "ls180.v:5952.64-5952.95" - cell $not $not$ls180.v:5952$1277 + attribute \src "ls180.v:6004.64-6004.95" + cell $not $not$ls180.v:6004$1343 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5952$1277_Y + connect \Y $not$ls180.v:6004$1343_Y end - attribute \src "ls180.v:5955.63-5955.94" - cell $not $not$ls180.v:5955$1284 + attribute \src "ls180.v:6007.63-6007.94" + cell $not $not$ls180.v:6007$1350 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5955$1284_Y + connect \Y $not$ls180.v:6007$1350_Y end - attribute \src "ls180.v:5958.63-5958.94" - cell $not $not$ls180.v:5958$1291 + attribute \src "ls180.v:6010.63-6010.94" + cell $not $not$ls180.v:6010$1357 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5958$1291_Y + connect \Y $not$ls180.v:6010$1357_Y end - attribute \src "ls180.v:5961.63-5961.94" - cell $not $not$ls180.v:5961$1298 + attribute \src "ls180.v:6013.63-6013.94" + cell $not $not$ls180.v:6013$1364 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5961$1298_Y + connect \Y $not$ls180.v:6013$1364_Y end - attribute \src "ls180.v:5964.63-5964.94" - cell $not $not$ls180.v:5964$1305 + attribute \src "ls180.v:6016.63-6016.94" + cell $not $not$ls180.v:6016$1371 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5964$1305_Y + connect \Y $not$ls180.v:6016$1371_Y end - attribute \src "ls180.v:5967.64-5967.95" - cell $not $not$ls180.v:5967$1312 + attribute \src "ls180.v:6019.64-6019.95" + cell $not $not$ls180.v:6019$1378 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5967$1312_Y + connect \Y $not$ls180.v:6019$1378_Y end - attribute \src "ls180.v:5970.64-5970.95" - cell $not $not$ls180.v:5970$1319 + attribute \src "ls180.v:6022.64-6022.95" + cell $not $not$ls180.v:6022$1385 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5970$1319_Y + connect \Y $not$ls180.v:6022$1385_Y end - attribute \src "ls180.v:5973.64-5973.95" - cell $not $not$ls180.v:5973$1326 + attribute \src "ls180.v:6025.64-6025.95" + cell $not $not$ls180.v:6025$1392 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5973$1326_Y + connect \Y $not$ls180.v:6025$1392_Y end - attribute \src "ls180.v:5976.64-5976.95" - cell $not $not$ls180.v:5976$1333 + attribute \src "ls180.v:6028.64-6028.95" + cell $not $not$ls180.v:6028$1399 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5976$1333_Y + connect \Y $not$ls180.v:6028$1399_Y end - attribute \src "ls180.v:5989.64-5989.95" - cell $not $not$ls180.v:5989$1341 + attribute \src "ls180.v:6041.64-6041.95" + cell $not $not$ls180.v:6041$1407 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5989$1341_Y + connect \Y $not$ls180.v:6041$1407_Y end - attribute \src "ls180.v:5992.63-5992.94" - cell $not $not$ls180.v:5992$1348 + attribute \src "ls180.v:6044.63-6044.94" + cell $not $not$ls180.v:6044$1414 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5992$1348_Y + connect \Y $not$ls180.v:6044$1414_Y end - attribute \src "ls180.v:5995.63-5995.94" - cell $not $not$ls180.v:5995$1355 + attribute \src "ls180.v:6047.63-6047.94" + cell $not $not$ls180.v:6047$1421 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5995$1355_Y + connect \Y $not$ls180.v:6047$1421_Y end - attribute \src "ls180.v:5998.63-5998.94" - cell $not $not$ls180.v:5998$1362 + attribute \src "ls180.v:6050.63-6050.94" + cell $not $not$ls180.v:6050$1428 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5998$1362_Y + connect \Y $not$ls180.v:6050$1428_Y end - attribute \src "ls180.v:6001.63-6001.94" - cell $not $not$ls180.v:6001$1369 + attribute \src "ls180.v:6053.63-6053.94" + cell $not $not$ls180.v:6053$1435 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:6001$1369_Y + connect \Y $not$ls180.v:6053$1435_Y end - attribute \src "ls180.v:6004.64-6004.95" - cell $not $not$ls180.v:6004$1376 + attribute \src "ls180.v:6056.64-6056.95" + cell $not $not$ls180.v:6056$1442 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:6004$1376_Y + connect \Y $not$ls180.v:6056$1442_Y end - attribute \src "ls180.v:6007.64-6007.95" - cell $not $not$ls180.v:6007$1383 + attribute \src "ls180.v:6059.64-6059.95" + cell $not $not$ls180.v:6059$1449 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:6007$1383_Y + connect \Y $not$ls180.v:6059$1449_Y end - attribute \src "ls180.v:6010.64-6010.95" - cell $not $not$ls180.v:6010$1390 + attribute \src "ls180.v:6062.64-6062.95" + cell $not $not$ls180.v:6062$1456 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:6010$1390_Y + connect \Y $not$ls180.v:6062$1456_Y end - attribute \src "ls180.v:6013.64-6013.95" - cell $not $not$ls180.v:6013$1397 + attribute \src "ls180.v:6065.64-6065.95" + cell $not $not$ls180.v:6065$1463 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:6013$1397_Y + connect \Y $not$ls180.v:6065$1463_Y end - attribute \src "ls180.v:6026.66-6026.97" - cell $not $not$ls180.v:6026$1405 + attribute \src "ls180.v:6078.66-6078.97" + cell $not $not$ls180.v:6078$1471 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6026$1405_Y + connect \Y $not$ls180.v:6078$1471_Y end - attribute \src "ls180.v:6029.66-6029.97" - cell $not $not$ls180.v:6029$1412 + attribute \src "ls180.v:6081.66-6081.97" + cell $not $not$ls180.v:6081$1478 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6029$1412_Y + connect \Y $not$ls180.v:6081$1478_Y end - attribute \src "ls180.v:6032.66-6032.97" - cell $not $not$ls180.v:6032$1419 + attribute \src "ls180.v:6084.66-6084.97" + cell $not $not$ls180.v:6084$1485 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6032$1419_Y + connect \Y $not$ls180.v:6084$1485_Y end - attribute \src "ls180.v:6035.66-6035.97" - cell $not $not$ls180.v:6035$1426 + attribute \src "ls180.v:6087.66-6087.97" + cell $not $not$ls180.v:6087$1492 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6035$1426_Y + connect \Y $not$ls180.v:6087$1492_Y end - attribute \src "ls180.v:6038.66-6038.97" - cell $not $not$ls180.v:6038$1433 + attribute \src "ls180.v:6090.66-6090.97" + cell $not $not$ls180.v:6090$1499 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6038$1433_Y + connect \Y $not$ls180.v:6090$1499_Y end - attribute \src "ls180.v:6041.66-6041.97" - cell $not $not$ls180.v:6041$1440 + attribute \src "ls180.v:6093.66-6093.97" + cell $not $not$ls180.v:6093$1506 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6041$1440_Y + connect \Y $not$ls180.v:6093$1506_Y end - attribute \src "ls180.v:6044.66-6044.97" - cell $not $not$ls180.v:6044$1447 + attribute \src "ls180.v:6096.66-6096.97" + cell $not $not$ls180.v:6096$1513 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6044$1447_Y + connect \Y $not$ls180.v:6096$1513_Y end - attribute \src "ls180.v:6047.66-6047.97" - cell $not $not$ls180.v:6047$1454 + attribute \src "ls180.v:6099.66-6099.97" + cell $not $not$ls180.v:6099$1520 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6047$1454_Y + connect \Y $not$ls180.v:6099$1520_Y end - attribute \src "ls180.v:6050.68-6050.99" - cell $not $not$ls180.v:6050$1461 + attribute \src "ls180.v:6102.68-6102.99" + cell $not $not$ls180.v:6102$1527 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6050$1461_Y + connect \Y $not$ls180.v:6102$1527_Y end - attribute \src "ls180.v:6053.68-6053.99" - cell $not $not$ls180.v:6053$1468 + attribute \src "ls180.v:6105.68-6105.99" + cell $not $not$ls180.v:6105$1534 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6053$1468_Y + connect \Y $not$ls180.v:6105$1534_Y end - attribute \src "ls180.v:6056.68-6056.99" - cell $not $not$ls180.v:6056$1475 + attribute \src "ls180.v:6108.68-6108.99" + cell $not $not$ls180.v:6108$1541 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6056$1475_Y + connect \Y $not$ls180.v:6108$1541_Y end - attribute \src "ls180.v:6059.68-6059.99" - cell $not $not$ls180.v:6059$1482 + attribute \src "ls180.v:6111.68-6111.99" + cell $not $not$ls180.v:6111$1548 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6059$1482_Y + connect \Y $not$ls180.v:6111$1548_Y end - attribute \src "ls180.v:6062.68-6062.99" - cell $not $not$ls180.v:6062$1489 + attribute \src "ls180.v:6114.68-6114.99" + cell $not $not$ls180.v:6114$1555 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6062$1489_Y + connect \Y $not$ls180.v:6114$1555_Y end - attribute \src "ls180.v:6065.65-6065.96" - cell $not $not$ls180.v:6065$1496 + attribute \src "ls180.v:6117.65-6117.96" + cell $not $not$ls180.v:6117$1562 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6065$1496_Y + connect \Y $not$ls180.v:6117$1562_Y end - attribute \src "ls180.v:6068.66-6068.97" - cell $not $not$ls180.v:6068$1503 + attribute \src "ls180.v:6120.66-6120.97" + cell $not $not$ls180.v:6120$1569 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6068$1503_Y + connect \Y $not$ls180.v:6120$1569_Y end - attribute \src "ls180.v:6088.70-6088.101" - cell $not $not$ls180.v:6088$1511 + attribute \src "ls180.v:6140.70-6140.101" + cell $not $not$ls180.v:6140$1577 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6088$1511_Y + connect \Y $not$ls180.v:6140$1577_Y end - attribute \src "ls180.v:6091.70-6091.101" - cell $not $not$ls180.v:6091$1518 + attribute \src "ls180.v:6143.70-6143.101" + cell $not $not$ls180.v:6143$1584 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6091$1518_Y + connect \Y $not$ls180.v:6143$1584_Y end - attribute \src "ls180.v:6094.70-6094.101" - cell $not $not$ls180.v:6094$1525 + attribute \src "ls180.v:6146.70-6146.101" + cell $not $not$ls180.v:6146$1591 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6094$1525_Y + connect \Y $not$ls180.v:6146$1591_Y end - attribute \src "ls180.v:6097.70-6097.101" - cell $not $not$ls180.v:6097$1532 + attribute \src "ls180.v:6149.70-6149.101" + cell $not $not$ls180.v:6149$1598 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6097$1532_Y + connect \Y $not$ls180.v:6149$1598_Y end - attribute \src "ls180.v:6100.69-6100.100" - cell $not $not$ls180.v:6100$1539 + attribute \src "ls180.v:6152.69-6152.100" + cell $not $not$ls180.v:6152$1605 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6100$1539_Y + connect \Y $not$ls180.v:6152$1605_Y end - attribute \src "ls180.v:6103.69-6103.100" - cell $not $not$ls180.v:6103$1546 + attribute \src "ls180.v:6155.69-6155.100" + cell $not $not$ls180.v:6155$1612 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6103$1546_Y + connect \Y $not$ls180.v:6155$1612_Y end - attribute \src "ls180.v:6106.69-6106.100" - cell $not $not$ls180.v:6106$1553 + attribute \src "ls180.v:6158.69-6158.100" + cell $not $not$ls180.v:6158$1619 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6106$1553_Y + connect \Y $not$ls180.v:6158$1619_Y end - attribute \src "ls180.v:6109.69-6109.100" - cell $not $not$ls180.v:6109$1560 + attribute \src "ls180.v:6161.69-6161.100" + cell $not $not$ls180.v:6161$1626 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6109$1560_Y + connect \Y $not$ls180.v:6161$1626_Y end - attribute \src "ls180.v:6112.60-6112.91" - cell $not $not$ls180.v:6112$1567 + attribute \src "ls180.v:6164.60-6164.91" + cell $not $not$ls180.v:6164$1633 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6112$1567_Y + connect \Y $not$ls180.v:6164$1633_Y end - attribute \src "ls180.v:6115.71-6115.102" - cell $not $not$ls180.v:6115$1574 + attribute \src "ls180.v:6167.71-6167.102" + cell $not $not$ls180.v:6167$1640 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6115$1574_Y + connect \Y $not$ls180.v:6167$1640_Y end - attribute \src "ls180.v:6118.71-6118.102" - cell $not $not$ls180.v:6118$1581 + attribute \src "ls180.v:6170.71-6170.102" + cell $not $not$ls180.v:6170$1647 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6118$1581_Y + connect \Y $not$ls180.v:6170$1647_Y end - attribute \src "ls180.v:6121.71-6121.102" - cell $not $not$ls180.v:6121$1588 + attribute \src "ls180.v:6173.71-6173.102" + cell $not $not$ls180.v:6173$1654 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6121$1588_Y + connect \Y $not$ls180.v:6173$1654_Y end - attribute \src "ls180.v:6124.71-6124.102" - cell $not $not$ls180.v:6124$1595 + attribute \src "ls180.v:6176.71-6176.102" + cell $not $not$ls180.v:6176$1661 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6124$1595_Y + connect \Y $not$ls180.v:6176$1661_Y end - attribute \src "ls180.v:6127.71-6127.102" - cell $not $not$ls180.v:6127$1602 + attribute \src "ls180.v:6179.71-6179.102" + cell $not $not$ls180.v:6179$1668 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6127$1602_Y + connect \Y $not$ls180.v:6179$1668_Y end - attribute \src "ls180.v:6130.71-6130.102" - cell $not $not$ls180.v:6130$1609 + attribute \src "ls180.v:6182.71-6182.102" + cell $not $not$ls180.v:6182$1675 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6130$1609_Y + connect \Y $not$ls180.v:6182$1675_Y end - attribute \src "ls180.v:6133.70-6133.101" - cell $not $not$ls180.v:6133$1616 + attribute \src "ls180.v:6185.70-6185.101" + cell $not $not$ls180.v:6185$1682 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6133$1616_Y + connect \Y $not$ls180.v:6185$1682_Y end - attribute \src "ls180.v:6136.70-6136.101" - cell $not $not$ls180.v:6136$1623 + attribute \src "ls180.v:6188.70-6188.101" + cell $not $not$ls180.v:6188$1689 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6136$1623_Y + connect \Y $not$ls180.v:6188$1689_Y end - attribute \src "ls180.v:6139.70-6139.101" - cell $not $not$ls180.v:6139$1630 + attribute \src "ls180.v:6191.70-6191.101" + cell $not $not$ls180.v:6191$1696 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6139$1630_Y + connect \Y $not$ls180.v:6191$1696_Y end - attribute \src "ls180.v:6142.70-6142.101" - cell $not $not$ls180.v:6142$1637 + attribute \src "ls180.v:6194.70-6194.101" + cell $not $not$ls180.v:6194$1703 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6142$1637_Y + connect \Y $not$ls180.v:6194$1703_Y end - attribute \src "ls180.v:6145.70-6145.101" - cell $not $not$ls180.v:6145$1644 + attribute \src "ls180.v:6197.70-6197.101" + cell $not $not$ls180.v:6197$1710 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6145$1644_Y + connect \Y $not$ls180.v:6197$1710_Y end - attribute \src "ls180.v:6148.70-6148.101" - cell $not $not$ls180.v:6148$1651 + attribute \src "ls180.v:6200.70-6200.101" + cell $not $not$ls180.v:6200$1717 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6148$1651_Y + connect \Y $not$ls180.v:6200$1717_Y end - attribute \src "ls180.v:6151.70-6151.101" - cell $not $not$ls180.v:6151$1658 + attribute \src "ls180.v:6203.70-6203.101" + cell $not $not$ls180.v:6203$1724 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6151$1658_Y + connect \Y $not$ls180.v:6203$1724_Y end - attribute \src "ls180.v:6154.70-6154.101" - cell $not $not$ls180.v:6154$1665 + attribute \src "ls180.v:6206.70-6206.101" + cell $not $not$ls180.v:6206$1731 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6154$1665_Y + connect \Y $not$ls180.v:6206$1731_Y end - attribute \src "ls180.v:6157.70-6157.101" - cell $not $not$ls180.v:6157$1672 + attribute \src "ls180.v:6209.70-6209.101" + cell $not $not$ls180.v:6209$1738 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6157$1672_Y + connect \Y $not$ls180.v:6209$1738_Y end - attribute \src "ls180.v:6160.70-6160.101" - cell $not $not$ls180.v:6160$1679 + attribute \src "ls180.v:6212.70-6212.101" + cell $not $not$ls180.v:6212$1745 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6160$1679_Y + connect \Y $not$ls180.v:6212$1745_Y end - attribute \src "ls180.v:6163.66-6163.97" - cell $not $not$ls180.v:6163$1686 + attribute \src "ls180.v:6215.66-6215.97" + cell $not $not$ls180.v:6215$1752 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6163$1686_Y + connect \Y $not$ls180.v:6215$1752_Y end - attribute \src "ls180.v:6166.67-6166.98" - cell $not $not$ls180.v:6166$1693 + attribute \src "ls180.v:6218.67-6218.98" + cell $not $not$ls180.v:6218$1759 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6166$1693_Y + connect \Y $not$ls180.v:6218$1759_Y end - attribute \src "ls180.v:6169.70-6169.101" - cell $not $not$ls180.v:6169$1700 + attribute \src "ls180.v:6221.70-6221.101" + cell $not $not$ls180.v:6221$1766 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6169$1700_Y + connect \Y $not$ls180.v:6221$1766_Y end - attribute \src "ls180.v:6172.70-6172.101" - cell $not $not$ls180.v:6172$1707 + attribute \src "ls180.v:6224.70-6224.101" + cell $not $not$ls180.v:6224$1773 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6172$1707_Y + connect \Y $not$ls180.v:6224$1773_Y end - attribute \src "ls180.v:6175.69-6175.100" - cell $not $not$ls180.v:6175$1714 + attribute \src "ls180.v:6227.69-6227.100" + cell $not $not$ls180.v:6227$1780 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6175$1714_Y + connect \Y $not$ls180.v:6227$1780_Y end - attribute \src "ls180.v:6178.69-6178.100" - cell $not $not$ls180.v:6178$1721 + attribute \src "ls180.v:6230.69-6230.100" + cell $not $not$ls180.v:6230$1787 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6178$1721_Y + connect \Y $not$ls180.v:6230$1787_Y end - attribute \src "ls180.v:6181.69-6181.100" - cell $not $not$ls180.v:6181$1728 + attribute \src "ls180.v:6233.69-6233.100" + cell $not $not$ls180.v:6233$1794 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6181$1728_Y + connect \Y $not$ls180.v:6233$1794_Y end - attribute \src "ls180.v:6184.69-6184.100" - cell $not $not$ls180.v:6184$1735 + attribute \src "ls180.v:6236.69-6236.100" + cell $not $not$ls180.v:6236$1801 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6184$1735_Y + connect \Y $not$ls180.v:6236$1801_Y end - attribute \src "ls180.v:6223.66-6223.97" - cell $not $not$ls180.v:6223$1743 + attribute \src "ls180.v:6275.66-6275.97" + cell $not $not$ls180.v:6275$1809 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6223$1743_Y + connect \Y $not$ls180.v:6275$1809_Y end - attribute \src "ls180.v:6226.66-6226.97" - cell $not $not$ls180.v:6226$1750 + attribute \src "ls180.v:6278.66-6278.97" + cell $not $not$ls180.v:6278$1816 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6226$1750_Y + connect \Y $not$ls180.v:6278$1816_Y end - attribute \src "ls180.v:6229.66-6229.97" - cell $not $not$ls180.v:6229$1757 + attribute \src "ls180.v:6281.66-6281.97" + cell $not $not$ls180.v:6281$1823 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6229$1757_Y + connect \Y $not$ls180.v:6281$1823_Y end - attribute \src "ls180.v:6232.66-6232.97" - cell $not $not$ls180.v:6232$1764 + attribute \src "ls180.v:6284.66-6284.97" + cell $not $not$ls180.v:6284$1830 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6232$1764_Y + connect \Y $not$ls180.v:6284$1830_Y end - attribute \src "ls180.v:6235.66-6235.97" - cell $not $not$ls180.v:6235$1771 + attribute \src "ls180.v:6287.66-6287.97" + cell $not $not$ls180.v:6287$1837 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6235$1771_Y + connect \Y $not$ls180.v:6287$1837_Y end - attribute \src "ls180.v:6238.66-6238.97" - cell $not $not$ls180.v:6238$1778 + attribute \src "ls180.v:6290.66-6290.97" + cell $not $not$ls180.v:6290$1844 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6238$1778_Y + connect \Y $not$ls180.v:6290$1844_Y end - attribute \src "ls180.v:6241.66-6241.97" - cell $not $not$ls180.v:6241$1785 + attribute \src "ls180.v:6293.66-6293.97" + cell $not $not$ls180.v:6293$1851 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6241$1785_Y + connect \Y $not$ls180.v:6293$1851_Y end - attribute \src "ls180.v:6244.66-6244.97" - cell $not $not$ls180.v:6244$1792 + attribute \src "ls180.v:6296.66-6296.97" + cell $not $not$ls180.v:6296$1858 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6244$1792_Y + connect \Y $not$ls180.v:6296$1858_Y end - attribute \src "ls180.v:6247.68-6247.99" - cell $not $not$ls180.v:6247$1799 + attribute \src "ls180.v:6299.68-6299.99" + cell $not $not$ls180.v:6299$1865 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6247$1799_Y + connect \Y $not$ls180.v:6299$1865_Y end - attribute \src "ls180.v:6250.68-6250.99" - cell $not $not$ls180.v:6250$1806 + attribute \src "ls180.v:6302.68-6302.99" + cell $not $not$ls180.v:6302$1872 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6250$1806_Y + connect \Y $not$ls180.v:6302$1872_Y end - attribute \src "ls180.v:6253.68-6253.99" - cell $not $not$ls180.v:6253$1813 + attribute \src "ls180.v:6305.68-6305.99" + cell $not $not$ls180.v:6305$1879 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6253$1813_Y + connect \Y $not$ls180.v:6305$1879_Y end - attribute \src "ls180.v:6256.68-6256.99" - cell $not $not$ls180.v:6256$1820 + attribute \src "ls180.v:6308.68-6308.99" + cell $not $not$ls180.v:6308$1886 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6256$1820_Y + connect \Y $not$ls180.v:6308$1886_Y end - attribute \src "ls180.v:6259.68-6259.99" - cell $not $not$ls180.v:6259$1827 + attribute \src "ls180.v:6311.68-6311.99" + cell $not $not$ls180.v:6311$1893 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6259$1827_Y + connect \Y $not$ls180.v:6311$1893_Y end - attribute \src "ls180.v:6262.65-6262.96" - cell $not $not$ls180.v:6262$1834 + attribute \src "ls180.v:6314.65-6314.96" + cell $not $not$ls180.v:6314$1900 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6262$1834_Y + connect \Y $not$ls180.v:6314$1900_Y end - attribute \src "ls180.v:6265.66-6265.97" - cell $not $not$ls180.v:6265$1841 + attribute \src "ls180.v:6317.66-6317.97" + cell $not $not$ls180.v:6317$1907 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6265$1841_Y + connect \Y $not$ls180.v:6317$1907_Y end - attribute \src "ls180.v:6268.68-6268.99" - cell $not $not$ls180.v:6268$1848 + attribute \src "ls180.v:6320.68-6320.99" + cell $not $not$ls180.v:6320$1914 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6268$1848_Y + connect \Y $not$ls180.v:6320$1914_Y end - attribute \src "ls180.v:6271.68-6271.99" - cell $not $not$ls180.v:6271$1855 + attribute \src "ls180.v:6323.68-6323.99" + cell $not $not$ls180.v:6323$1921 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6271$1855_Y + connect \Y $not$ls180.v:6323$1921_Y end - attribute \src "ls180.v:6274.68-6274.99" - cell $not $not$ls180.v:6274$1862 + attribute \src "ls180.v:6326.68-6326.99" + cell $not $not$ls180.v:6326$1928 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6274$1862_Y + connect \Y $not$ls180.v:6326$1928_Y end - attribute \src "ls180.v:6277.68-6277.99" - cell $not $not$ls180.v:6277$1869 + attribute \src "ls180.v:6329.68-6329.99" + cell $not $not$ls180.v:6329$1935 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6277$1869_Y + connect \Y $not$ls180.v:6329$1935_Y end - attribute \src "ls180.v:6302.68-6302.99" - cell $not $not$ls180.v:6302$1877 + attribute \src "ls180.v:6354.68-6354.99" + cell $not $not$ls180.v:6354$1943 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_we - connect \Y $not$ls180.v:6302$1877_Y + connect \Y $not$ls180.v:6354$1943_Y end - attribute \src "ls180.v:6305.73-6305.104" - cell $not $not$ls180.v:6305$1884 + attribute \src "ls180.v:6357.73-6357.104" + cell $not $not$ls180.v:6357$1950 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_we - connect \Y $not$ls180.v:6305$1884_Y + connect \Y $not$ls180.v:6357$1950_Y end - attribute \src "ls180.v:6308.73-6308.104" - cell $not $not$ls180.v:6308$1891 + attribute \src "ls180.v:6360.73-6360.104" + cell $not $not$ls180.v:6360$1957 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_we - connect \Y $not$ls180.v:6308$1891_Y + connect \Y $not$ls180.v:6360$1957_Y end - attribute \src "ls180.v:6311.66-6311.97" - cell $not $not$ls180.v:6311$1898 + attribute \src "ls180.v:6363.66-6363.97" + cell $not $not$ls180.v:6363$1964 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_we - connect \Y $not$ls180.v:6311$1898_Y + connect \Y $not$ls180.v:6363$1964_Y end - attribute \src "ls180.v:6319.70-6319.101" - cell $not $not$ls180.v:6319$1906 + attribute \src "ls180.v:6371.70-6371.101" + cell $not $not$ls180.v:6371$1972 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_we - connect \Y $not$ls180.v:6319$1906_Y + connect \Y $not$ls180.v:6371$1972_Y end - attribute \src "ls180.v:6322.74-6322.105" - cell $not $not$ls180.v:6322$1913 + attribute \src "ls180.v:6374.74-6374.105" + cell $not $not$ls180.v:6374$1979 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_we - connect \Y $not$ls180.v:6322$1913_Y + connect \Y $not$ls180.v:6374$1979_Y end - attribute \src "ls180.v:6325.64-6325.95" - cell $not $not$ls180.v:6325$1920 + attribute \src "ls180.v:6377.64-6377.95" + cell $not $not$ls180.v:6377$1986 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_we - connect \Y $not$ls180.v:6325$1920_Y + connect \Y $not$ls180.v:6377$1986_Y end - attribute \src "ls180.v:6328.74-6328.105" - cell $not $not$ls180.v:6328$1927 + attribute \src "ls180.v:6380.74-6380.105" + cell $not $not$ls180.v:6380$1993 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_we - connect \Y $not$ls180.v:6328$1927_Y + connect \Y $not$ls180.v:6380$1993_Y end - attribute \src "ls180.v:6331.74-6331.105" - cell $not $not$ls180.v:6331$1934 + attribute \src "ls180.v:6383.74-6383.105" + cell $not $not$ls180.v:6383$2000 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_we - connect \Y $not$ls180.v:6331$1934_Y + connect \Y $not$ls180.v:6383$2000_Y end - attribute \src "ls180.v:6334.75-6334.106" - cell $not $not$ls180.v:6334$1941 + attribute \src "ls180.v:6386.75-6386.106" + cell $not $not$ls180.v:6386$2007 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_we - connect \Y $not$ls180.v:6334$1941_Y + connect \Y $not$ls180.v:6386$2007_Y end - attribute \src "ls180.v:6337.73-6337.104" - cell $not $not$ls180.v:6337$1948 + attribute \src "ls180.v:6389.73-6389.104" + cell $not $not$ls180.v:6389$2014 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_we - connect \Y $not$ls180.v:6337$1948_Y + connect \Y $not$ls180.v:6389$2014_Y end - attribute \src "ls180.v:6340.73-6340.104" - cell $not $not$ls180.v:6340$1955 + attribute \src "ls180.v:6392.73-6392.104" + cell $not $not$ls180.v:6392$2021 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_we - connect \Y $not$ls180.v:6340$1955_Y + connect \Y $not$ls180.v:6392$2021_Y end - attribute \src "ls180.v:6343.73-6343.104" - cell $not $not$ls180.v:6343$1962 + attribute \src "ls180.v:6395.73-6395.104" + cell $not $not$ls180.v:6395$2028 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_we - connect \Y $not$ls180.v:6343$1962_Y + connect \Y $not$ls180.v:6395$2028_Y end - attribute \src "ls180.v:6346.73-6346.104" - cell $not $not$ls180.v:6346$1969 + attribute \src "ls180.v:6398.73-6398.104" + cell $not $not$ls180.v:6398$2035 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_we - connect \Y $not$ls180.v:6346$1969_Y + connect \Y $not$ls180.v:6398$2035_Y end - attribute \src "ls180.v:6364.67-6364.99" - cell $not $not$ls180.v:6364$1977 + attribute \src "ls180.v:6416.67-6416.99" + cell $not $not$ls180.v:6416$2043 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6364$1977_Y + connect \Y $not$ls180.v:6416$2043_Y end - attribute \src "ls180.v:6367.67-6367.99" - cell $not $not$ls180.v:6367$1984 + attribute \src "ls180.v:6419.67-6419.99" + cell $not $not$ls180.v:6419$2050 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6367$1984_Y + connect \Y $not$ls180.v:6419$2050_Y end - attribute \src "ls180.v:6370.65-6370.97" - cell $not $not$ls180.v:6370$1991 + attribute \src "ls180.v:6422.65-6422.97" + cell $not $not$ls180.v:6422$2057 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6370$1991_Y + connect \Y $not$ls180.v:6422$2057_Y end - attribute \src "ls180.v:6373.64-6373.96" - cell $not $not$ls180.v:6373$1998 + attribute \src "ls180.v:6425.64-6425.96" + cell $not $not$ls180.v:6425$2064 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6373$1998_Y + connect \Y $not$ls180.v:6425$2064_Y end - attribute \src "ls180.v:6376.63-6376.95" - cell $not $not$ls180.v:6376$2005 + attribute \src "ls180.v:6428.63-6428.95" + cell $not $not$ls180.v:6428$2071 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6376$2005_Y + connect \Y $not$ls180.v:6428$2071_Y end - attribute \src "ls180.v:6379.62-6379.94" - cell $not $not$ls180.v:6379$2012 + attribute \src "ls180.v:6431.62-6431.94" + cell $not $not$ls180.v:6431$2078 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6379$2012_Y + connect \Y $not$ls180.v:6431$2078_Y end - attribute \src "ls180.v:6382.68-6382.100" - cell $not $not$ls180.v:6382$2019 + attribute \src "ls180.v:6434.68-6434.100" + cell $not $not$ls180.v:6434$2085 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6382$2019_Y + connect \Y $not$ls180.v:6434$2085_Y end - attribute \src "ls180.v:6404.67-6404.99" - cell $not $not$ls180.v:6404$2028 + attribute \src "ls180.v:6456.67-6456.99" + cell $not $not$ls180.v:6456$2094 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6404$2028_Y + connect \Y $not$ls180.v:6456$2094_Y end - attribute \src "ls180.v:6407.67-6407.99" - cell $not $not$ls180.v:6407$2035 + attribute \src "ls180.v:6459.67-6459.99" + cell $not $not$ls180.v:6459$2101 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6407$2035_Y + connect \Y $not$ls180.v:6459$2101_Y end - attribute \src "ls180.v:6410.65-6410.97" - cell $not $not$ls180.v:6410$2042 + attribute \src "ls180.v:6462.65-6462.97" + cell $not $not$ls180.v:6462$2108 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6410$2042_Y + connect \Y $not$ls180.v:6462$2108_Y end - attribute \src "ls180.v:6413.64-6413.96" - cell $not $not$ls180.v:6413$2049 + attribute \src "ls180.v:6465.64-6465.96" + cell $not $not$ls180.v:6465$2115 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6413$2049_Y + connect \Y $not$ls180.v:6465$2115_Y end - attribute \src "ls180.v:6416.63-6416.95" - cell $not $not$ls180.v:6416$2056 + attribute \src "ls180.v:6468.63-6468.95" + cell $not $not$ls180.v:6468$2122 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6416$2056_Y + connect \Y $not$ls180.v:6468$2122_Y end - attribute \src "ls180.v:6419.62-6419.94" - cell $not $not$ls180.v:6419$2063 + attribute \src "ls180.v:6471.62-6471.94" + cell $not $not$ls180.v:6471$2129 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6419$2063_Y + connect \Y $not$ls180.v:6471$2129_Y end - attribute \src "ls180.v:6422.68-6422.100" - cell $not $not$ls180.v:6422$2070 + attribute \src "ls180.v:6474.68-6474.100" + cell $not $not$ls180.v:6474$2136 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6422$2070_Y + connect \Y $not$ls180.v:6474$2136_Y end - attribute \src "ls180.v:6425.71-6425.103" - cell $not $not$ls180.v:6425$2077 + attribute \src "ls180.v:6477.71-6477.103" + cell $not $not$ls180.v:6477$2143 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6425$2077_Y + connect \Y $not$ls180.v:6477$2143_Y end - attribute \src "ls180.v:6428.71-6428.103" - cell $not $not$ls180.v:6428$2084 + attribute \src "ls180.v:6480.71-6480.103" + cell $not $not$ls180.v:6480$2150 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6428$2084_Y + connect \Y $not$ls180.v:6480$2150_Y end - attribute \src "ls180.v:6452.64-6452.96" - cell $not $not$ls180.v:6452$2093 + attribute \src "ls180.v:6504.64-6504.96" + cell $not $not$ls180.v:6504$2159 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6452$2093_Y + connect \Y $not$ls180.v:6504$2159_Y end - attribute \src "ls180.v:6455.64-6455.96" - cell $not $not$ls180.v:6455$2100 + attribute \src "ls180.v:6507.64-6507.96" + cell $not $not$ls180.v:6507$2166 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6455$2100_Y + connect \Y $not$ls180.v:6507$2166_Y end - attribute \src "ls180.v:6458.64-6458.96" - cell $not $not$ls180.v:6458$2107 + attribute \src "ls180.v:6510.64-6510.96" + cell $not $not$ls180.v:6510$2173 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6458$2107_Y + connect \Y $not$ls180.v:6510$2173_Y end - attribute \src "ls180.v:6461.64-6461.96" - cell $not $not$ls180.v:6461$2114 + attribute \src "ls180.v:6513.64-6513.96" + cell $not $not$ls180.v:6513$2180 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6461$2114_Y + connect \Y $not$ls180.v:6513$2180_Y end - attribute \src "ls180.v:6464.66-6464.98" - cell $not $not$ls180.v:6464$2121 + attribute \src "ls180.v:6516.66-6516.98" + cell $not $not$ls180.v:6516$2187 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6464$2121_Y + connect \Y $not$ls180.v:6516$2187_Y end - attribute \src "ls180.v:6467.66-6467.98" - cell $not $not$ls180.v:6467$2128 + attribute \src "ls180.v:6519.66-6519.98" + cell $not $not$ls180.v:6519$2194 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6467$2128_Y + connect \Y $not$ls180.v:6519$2194_Y end - attribute \src "ls180.v:6470.66-6470.98" - cell $not $not$ls180.v:6470$2135 + attribute \src "ls180.v:6522.66-6522.98" + cell $not $not$ls180.v:6522$2201 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6470$2135_Y + connect \Y $not$ls180.v:6522$2201_Y end - attribute \src "ls180.v:6473.66-6473.98" - cell $not $not$ls180.v:6473$2142 + attribute \src "ls180.v:6525.66-6525.98" + cell $not $not$ls180.v:6525$2208 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6473$2142_Y + connect \Y $not$ls180.v:6525$2208_Y end - attribute \src "ls180.v:6476.62-6476.94" - cell $not $not$ls180.v:6476$2149 + attribute \src "ls180.v:6528.62-6528.94" + cell $not $not$ls180.v:6528$2215 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6476$2149_Y + connect \Y $not$ls180.v:6528$2215_Y end - attribute \src "ls180.v:6479.72-6479.104" - cell $not $not$ls180.v:6479$2156 + attribute \src "ls180.v:6531.72-6531.104" + cell $not $not$ls180.v:6531$2222 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6479$2156_Y + connect \Y $not$ls180.v:6531$2222_Y end - attribute \src "ls180.v:6482.65-6482.97" - cell $not $not$ls180.v:6482$2163 + attribute \src "ls180.v:6534.65-6534.97" + cell $not $not$ls180.v:6534$2229 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6482$2163_Y + connect \Y $not$ls180.v:6534$2229_Y end - attribute \src "ls180.v:6485.65-6485.97" - cell $not $not$ls180.v:6485$2170 + attribute \src "ls180.v:6537.65-6537.97" + cell $not $not$ls180.v:6537$2236 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6485$2170_Y + connect \Y $not$ls180.v:6537$2236_Y end - attribute \src "ls180.v:6488.65-6488.97" - cell $not $not$ls180.v:6488$2177 + attribute \src "ls180.v:6540.65-6540.97" + cell $not $not$ls180.v:6540$2243 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6488$2177_Y + connect \Y $not$ls180.v:6540$2243_Y end - attribute \src "ls180.v:6491.65-6491.97" - cell $not $not$ls180.v:6491$2184 + attribute \src "ls180.v:6543.65-6543.97" + cell $not $not$ls180.v:6543$2250 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6491$2184_Y + connect \Y $not$ls180.v:6543$2250_Y end - attribute \src "ls180.v:6494.77-6494.109" - cell $not $not$ls180.v:6494$2191 + attribute \src "ls180.v:6546.77-6546.109" + cell $not $not$ls180.v:6546$2257 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6494$2191_Y + connect \Y $not$ls180.v:6546$2257_Y end - attribute \src "ls180.v:6497.78-6497.110" - cell $not $not$ls180.v:6497$2198 + attribute \src "ls180.v:6549.78-6549.110" + cell $not $not$ls180.v:6549$2264 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6497$2198_Y + connect \Y $not$ls180.v:6549$2264_Y end - attribute \src "ls180.v:6500.69-6500.101" - cell $not $not$ls180.v:6500$2205 + attribute \src "ls180.v:6552.69-6552.101" + cell $not $not$ls180.v:6552$2271 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6500$2205_Y + connect \Y $not$ls180.v:6552$2271_Y end - attribute \src "ls180.v:6520.55-6520.87" - cell $not $not$ls180.v:6520$2213 + attribute \src "ls180.v:6572.55-6572.87" + cell $not $not$ls180.v:6572$2279 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6520$2213_Y + connect \Y $not$ls180.v:6572$2279_Y end - attribute \src "ls180.v:6523.65-6523.97" - cell $not $not$ls180.v:6523$2220 + attribute \src "ls180.v:6575.65-6575.97" + cell $not $not$ls180.v:6575$2286 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6523$2220_Y + connect \Y $not$ls180.v:6575$2286_Y end - attribute \src "ls180.v:6526.66-6526.98" - cell $not $not$ls180.v:6526$2227 + attribute \src "ls180.v:6578.66-6578.98" + cell $not $not$ls180.v:6578$2293 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6526$2227_Y + connect \Y $not$ls180.v:6578$2293_Y end - attribute \src "ls180.v:6529.70-6529.102" - cell $not $not$ls180.v:6529$2234 + attribute \src "ls180.v:6581.70-6581.102" + cell $not $not$ls180.v:6581$2300 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6529$2234_Y + connect \Y $not$ls180.v:6581$2300_Y end - attribute \src "ls180.v:6532.71-6532.103" - cell $not $not$ls180.v:6532$2241 + attribute \src "ls180.v:6584.71-6584.103" + cell $not $not$ls180.v:6584$2307 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6532$2241_Y + connect \Y $not$ls180.v:6584$2307_Y end - attribute \src "ls180.v:6535.69-6535.101" - cell $not $not$ls180.v:6535$2248 + attribute \src "ls180.v:6587.69-6587.101" + cell $not $not$ls180.v:6587$2314 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6535$2248_Y + connect \Y $not$ls180.v:6587$2314_Y end - attribute \src "ls180.v:6538.66-6538.98" - cell $not $not$ls180.v:6538$2255 + attribute \src "ls180.v:6590.66-6590.98" + cell $not $not$ls180.v:6590$2321 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6538$2255_Y + connect \Y $not$ls180.v:6590$2321_Y end - attribute \src "ls180.v:6541.65-6541.97" - cell $not $not$ls180.v:6541$2262 + attribute \src "ls180.v:6593.65-6593.97" + cell $not $not$ls180.v:6593$2328 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6541$2262_Y + connect \Y $not$ls180.v:6593$2328_Y end - attribute \src "ls180.v:6554.71-6554.103" - cell $not $not$ls180.v:6554$2270 + attribute \src "ls180.v:6606.71-6606.103" + cell $not $not$ls180.v:6606$2336 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface14_bank_bus_we - connect \Y $not$ls180.v:6554$2270_Y + connect \Y $not$ls180.v:6606$2336_Y end - attribute \src "ls180.v:6557.71-6557.103" - cell $not $not$ls180.v:6557$2277 + attribute \src "ls180.v:6609.71-6609.103" + cell $not $not$ls180.v:6609$2343 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface14_bank_bus_we - connect \Y $not$ls180.v:6557$2277_Y + connect \Y $not$ls180.v:6609$2343_Y end - attribute \src "ls180.v:6560.71-6560.103" - cell $not $not$ls180.v:6560$2284 + attribute \src "ls180.v:6612.71-6612.103" + cell $not $not$ls180.v:6612$2350 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface14_bank_bus_we - connect \Y $not$ls180.v:6560$2284_Y + connect \Y $not$ls180.v:6612$2350_Y end - attribute \src "ls180.v:6563.71-6563.103" - cell $not $not$ls180.v:6563$2291 + attribute \src "ls180.v:6615.71-6615.103" + cell $not $not$ls180.v:6615$2357 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface14_bank_bus_we - connect \Y $not$ls180.v:6563$2291_Y + connect \Y $not$ls180.v:6615$2357_Y end - attribute \src "ls180.v:6944.86-6944.330" - cell $not $not$ls180.v:6944$2340 + attribute \src "ls180.v:6996.86-6996.330" + cell $not $not$ls180.v:6996$2406 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6944$2339_Y - connect \Y $not$ls180.v:6944$2340_Y + connect \A $or$ls180.v:6996$2405_Y + connect \Y $not$ls180.v:6996$2406_Y end - attribute \src "ls180.v:6968.86-6968.330" - cell $not $not$ls180.v:6968$2356 + attribute \src "ls180.v:7020.86-7020.330" + cell $not $not$ls180.v:7020$2422 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6968$2355_Y - connect \Y $not$ls180.v:6968$2356_Y + connect \A $or$ls180.v:7020$2421_Y + connect \Y $not$ls180.v:7020$2422_Y end - attribute \src "ls180.v:6992.86-6992.330" - cell $not $not$ls180.v:6992$2372 + attribute \src "ls180.v:7044.86-7044.330" + cell $not $not$ls180.v:7044$2438 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6992$2371_Y - connect \Y $not$ls180.v:6992$2372_Y + connect \A $or$ls180.v:7044$2437_Y + connect \Y $not$ls180.v:7044$2438_Y end - attribute \src "ls180.v:7016.86-7016.330" - cell $not $not$ls180.v:7016$2388 + attribute \src "ls180.v:7068.86-7068.330" + cell $not $not$ls180.v:7068$2454 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7016$2387_Y - connect \Y $not$ls180.v:7016$2388_Y + connect \A $or$ls180.v:7068$2453_Y + connect \Y $not$ls180.v:7068$2454_Y end - attribute \src "ls180.v:7514.18-7514.42" - cell $not $not$ls180.v:7514$2441 + attribute \src "ls180.v:7569.18-7569.42" + cell $not $not$ls180.v:7569$2508 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_clocker_clk0 - connect \Y $not$ls180.v:7514$2441_Y + connect \Y $not$ls180.v:7569$2508_Y end - attribute \src "ls180.v:7593.72-7593.101" - cell $not $not$ls180.v:7593$2474 + attribute \src "ls180.v:7648.72-7648.101" + cell $not $not$ls180.v:7648$2541 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_libresocsim_ram_bus_ack - connect \Y $not$ls180.v:7593$2474_Y + connect \Y $not$ls180.v:7648$2541_Y end - attribute \src "ls180.v:7612.8-7612.38" - cell $not $not$ls180.v:7612$2478 + attribute \src "ls180.v:7667.8-7667.38" + cell $not $not$ls180.v:7667$2545 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_libresocsim_zero_trigger - connect \Y $not$ls180.v:7612$2478_Y + connect \Y $not$ls180.v:7667$2545_Y end - attribute \src "ls180.v:7616.70-7616.98" - cell $not $not$ls180.v:7616$2481 + attribute \src "ls180.v:7671.70-7671.98" + cell $not $not$ls180.v:7671$2548 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_interface0_ram_bus_ack - connect \Y $not$ls180.v:7616$2481_Y + connect \Y $not$ls180.v:7671$2548_Y end - attribute \src "ls180.v:7620.70-7620.98" - cell $not $not$ls180.v:7620$2484 + attribute \src "ls180.v:7675.70-7675.98" + cell $not $not$ls180.v:7675$2551 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_interface1_ram_bus_ack - connect \Y $not$ls180.v:7620$2484_Y + connect \Y $not$ls180.v:7675$2551_Y end - attribute \src "ls180.v:7624.70-7624.98" - cell $not $not$ls180.v:7624$2487 + attribute \src "ls180.v:7679.70-7679.98" + cell $not $not$ls180.v:7679$2554 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_interface2_ram_bus_ack - connect \Y $not$ls180.v:7624$2487_Y + connect \Y $not$ls180.v:7679$2554_Y end - attribute \src "ls180.v:7632.32-7632.55" - cell $not $not$ls180.v:7632$2489 + attribute \src "ls180.v:7687.32-7687.55" + cell $not $not$ls180.v:7687$2556 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_timer_done0 - connect \Y $not$ls180.v:7632$2489_Y + connect \Y $not$ls180.v:7687$2556_Y end - attribute \src "ls180.v:7702.136-7702.189" - cell $not $not$ls180.v:7702$2504 + attribute \src "ls180.v:7757.136-7757.189" + cell $not $not$ls180.v:7757$2571 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7702$2504_Y + connect \Y $not$ls180.v:7757$2571_Y end - attribute \src "ls180.v:7708.136-7708.189" - cell $not $not$ls180.v:7708$2509 + attribute \src "ls180.v:7763.136-7763.189" + cell $not $not$ls180.v:7763$2576 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7708$2509_Y + connect \Y $not$ls180.v:7763$2576_Y end - attribute \src "ls180.v:7709.8-7709.61" - cell $not $not$ls180.v:7709$2511 + attribute \src "ls180.v:7764.8-7764.61" + cell $not $not$ls180.v:7764$2578 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read - connect \Y $not$ls180.v:7709$2511_Y + connect \Y $not$ls180.v:7764$2578_Y end - attribute \src "ls180.v:7717.8-7717.56" - cell $not $not$ls180.v:7717$2514 + attribute \src "ls180.v:7772.8-7772.56" + cell $not $not$ls180.v:7772$2581 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_source_valid - connect \Y $not$ls180.v:7717$2514_Y + connect \Y $not$ls180.v:7772$2581_Y end - attribute \src "ls180.v:7732.8-7732.46" - cell $not $not$ls180.v:7732$2516 + attribute \src "ls180.v:7787.8-7787.46" + cell $not $not$ls180.v:7787$2583 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_twtpcon_ready - connect \Y $not$ls180.v:7732$2516_Y + connect \Y $not$ls180.v:7787$2583_Y end - attribute \src "ls180.v:7748.136-7748.189" - cell $not $not$ls180.v:7748$2520 + attribute \src "ls180.v:7803.136-7803.189" + cell $not $not$ls180.v:7803$2587 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7748$2520_Y + connect \Y $not$ls180.v:7803$2587_Y end - attribute \src "ls180.v:7754.136-7754.189" - cell $not $not$ls180.v:7754$2525 + attribute \src "ls180.v:7809.136-7809.189" + cell $not $not$ls180.v:7809$2592 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7754$2525_Y + connect \Y $not$ls180.v:7809$2592_Y end - attribute \src "ls180.v:7755.8-7755.61" - cell $not $not$ls180.v:7755$2527 + attribute \src "ls180.v:7810.8-7810.61" + cell $not $not$ls180.v:7810$2594 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read - connect \Y $not$ls180.v:7755$2527_Y + connect \Y $not$ls180.v:7810$2594_Y end - attribute \src "ls180.v:7763.8-7763.56" - cell $not $not$ls180.v:7763$2530 + attribute \src "ls180.v:7818.8-7818.56" + cell $not $not$ls180.v:7818$2597 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_source_valid - connect \Y $not$ls180.v:7763$2530_Y + connect \Y $not$ls180.v:7818$2597_Y end - attribute \src "ls180.v:7778.8-7778.46" - cell $not $not$ls180.v:7778$2532 + attribute \src "ls180.v:7833.8-7833.46" + cell $not $not$ls180.v:7833$2599 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_twtpcon_ready - connect \Y $not$ls180.v:7778$2532_Y + connect \Y $not$ls180.v:7833$2599_Y end - attribute \src "ls180.v:7794.136-7794.189" - cell $not $not$ls180.v:7794$2536 + attribute \src "ls180.v:7849.136-7849.189" + cell $not $not$ls180.v:7849$2603 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7794$2536_Y + connect \Y $not$ls180.v:7849$2603_Y end - attribute \src "ls180.v:7800.136-7800.189" - cell $not $not$ls180.v:7800$2541 + attribute \src "ls180.v:7855.136-7855.189" + cell $not $not$ls180.v:7855$2608 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7800$2541_Y + connect \Y $not$ls180.v:7855$2608_Y end - attribute \src "ls180.v:7801.8-7801.61" - cell $not $not$ls180.v:7801$2543 + attribute \src "ls180.v:7856.8-7856.61" + cell $not $not$ls180.v:7856$2610 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read - connect \Y $not$ls180.v:7801$2543_Y + connect \Y $not$ls180.v:7856$2610_Y end - attribute \src "ls180.v:7809.8-7809.56" - cell $not $not$ls180.v:7809$2546 + attribute \src "ls180.v:7864.8-7864.56" + cell $not $not$ls180.v:7864$2613 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_source_valid - connect \Y $not$ls180.v:7809$2546_Y + connect \Y $not$ls180.v:7864$2613_Y end - attribute \src "ls180.v:7824.8-7824.46" - cell $not $not$ls180.v:7824$2548 + attribute \src "ls180.v:7879.8-7879.46" + cell $not $not$ls180.v:7879$2615 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_twtpcon_ready - connect \Y $not$ls180.v:7824$2548_Y + connect \Y $not$ls180.v:7879$2615_Y end - attribute \src "ls180.v:7840.136-7840.189" - cell $not $not$ls180.v:7840$2552 + attribute \src "ls180.v:7895.136-7895.189" + cell $not $not$ls180.v:7895$2619 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7840$2552_Y + connect \Y $not$ls180.v:7895$2619_Y end - attribute \src "ls180.v:7846.136-7846.189" - cell $not $not$ls180.v:7846$2557 + attribute \src "ls180.v:7901.136-7901.189" + cell $not $not$ls180.v:7901$2624 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7846$2557_Y + connect \Y $not$ls180.v:7901$2624_Y end - attribute \src "ls180.v:7847.8-7847.61" - cell $not $not$ls180.v:7847$2559 + attribute \src "ls180.v:7902.8-7902.61" + cell $not $not$ls180.v:7902$2626 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read - connect \Y $not$ls180.v:7847$2559_Y + connect \Y $not$ls180.v:7902$2626_Y end - attribute \src "ls180.v:7855.8-7855.56" - cell $not $not$ls180.v:7855$2562 + attribute \src "ls180.v:7910.8-7910.56" + cell $not $not$ls180.v:7910$2629 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_source_valid - connect \Y $not$ls180.v:7855$2562_Y + connect \Y $not$ls180.v:7910$2629_Y end - attribute \src "ls180.v:7870.8-7870.46" - cell $not $not$ls180.v:7870$2564 + attribute \src "ls180.v:7925.8-7925.46" + cell $not $not$ls180.v:7925$2631 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_twtpcon_ready - connect \Y $not$ls180.v:7870$2564_Y + connect \Y $not$ls180.v:7925$2631_Y end - attribute \src "ls180.v:7878.7-7878.22" - cell $not $not$ls180.v:7878$2567 + attribute \src "ls180.v:7933.7-7933.22" + cell $not $not$ls180.v:7933$2634 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_en0 - connect \Y $not$ls180.v:7878$2567_Y + connect \Y $not$ls180.v:7933$2634_Y end - attribute \src "ls180.v:7881.8-7881.29" - cell $not $not$ls180.v:7881$2568 + attribute \src "ls180.v:7936.8-7936.29" + cell $not $not$ls180.v:7936$2635 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_max_time0 - connect \Y $not$ls180.v:7881$2568_Y + connect \Y $not$ls180.v:7936$2635_Y end - attribute \src "ls180.v:7885.7-7885.22" - cell $not $not$ls180.v:7885$2570 + attribute \src "ls180.v:7940.7-7940.22" + cell $not $not$ls180.v:7940$2637 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_en1 - connect \Y $not$ls180.v:7885$2570_Y + connect \Y $not$ls180.v:7940$2637_Y end - attribute \src "ls180.v:7888.8-7888.29" - cell $not $not$ls180.v:7888$2571 + attribute \src "ls180.v:7943.8-7943.29" + cell $not $not$ls180.v:7943$2638 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_max_time1 - connect \Y $not$ls180.v:7888$2571_Y + connect \Y $not$ls180.v:7943$2638_Y end - attribute \src "ls180.v:8007.30-8007.60" - cell $not $not$ls180.v:8007$2573 + attribute \src "ls180.v:8062.30-8062.60" + cell $not $not$ls180.v:8062$2640 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_sync_rhs_array_muxed2 - connect \Y $not$ls180.v:8007$2573_Y + connect \Y $not$ls180.v:8062$2640_Y end - attribute \src "ls180.v:8008.30-8008.60" - cell $not $not$ls180.v:8008$2574 + attribute \src "ls180.v:8063.30-8063.60" + cell $not $not$ls180.v:8063$2641 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_sync_rhs_array_muxed3 - connect \Y $not$ls180.v:8008$2574_Y + connect \Y $not$ls180.v:8063$2641_Y end - attribute \src "ls180.v:8009.29-8009.59" - cell $not $not$ls180.v:8009$2575 + attribute \src "ls180.v:8064.29-8064.59" + cell $not $not$ls180.v:8064$2642 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_sync_rhs_array_muxed4 - connect \Y $not$ls180.v:8009$2575_Y + connect \Y $not$ls180.v:8064$2642_Y end - attribute \src "ls180.v:8020.8-8020.33" - cell $not $not$ls180.v:8020$2576 + attribute \src "ls180.v:8075.8-8075.33" + cell $not $not$ls180.v:8075$2643 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_tccdcon_ready - connect \Y $not$ls180.v:8020$2576_Y + connect \Y $not$ls180.v:8075$2643_Y end - attribute \src "ls180.v:8035.8-8035.33" - cell $not $not$ls180.v:8035$2579 + attribute \src "ls180.v:8090.8-8090.33" + cell $not $not$ls180.v:8090$2646 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_twtrcon_ready - connect \Y $not$ls180.v:8035$2579_Y + connect \Y $not$ls180.v:8090$2646_Y end - attribute \src "ls180.v:8071.36-8071.58" - cell $not $not$ls180.v:8071$2609 + attribute \src "ls180.v:8126.36-8126.58" + cell $not $not$ls180.v:8126$2676 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_phy_tx_busy - connect \Y $not$ls180.v:8071$2609_Y + connect \Y $not$ls180.v:8126$2676_Y end - attribute \src "ls180.v:8071.64-8071.89" - cell $not $not$ls180.v:8071$2611 + attribute \src "ls180.v:8126.64-8126.89" + cell $not $not$ls180.v:8126$2678 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_phy_sink_ready - connect \Y $not$ls180.v:8071$2611_Y + connect \Y $not$ls180.v:8126$2678_Y end - attribute \src "ls180.v:8100.7-8100.29" - cell $not $not$ls180.v:8100$2618 + attribute \src "ls180.v:8155.7-8155.29" + cell $not $not$ls180.v:8155$2685 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_phy_rx_busy - connect \Y $not$ls180.v:8100$2618_Y + connect \Y $not$ls180.v:8155$2685_Y end - attribute \src "ls180.v:8101.9-8101.26" - cell $not $not$ls180.v:8101$2619 + attribute \src "ls180.v:8156.9-8156.26" + cell $not $not$ls180.v:8156$2686 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_phy_rx - connect \Y $not$ls180.v:8101$2619_Y + connect \Y $not$ls180.v:8156$2686_Y end - attribute \src "ls180.v:8134.8-8134.29" - cell $not $not$ls180.v:8134$2625 + attribute \src "ls180.v:8189.8-8189.29" + cell $not $not$ls180.v:8189$2692 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_tx_trigger - connect \Y $not$ls180.v:8134$2625_Y + connect \Y $not$ls180.v:8189$2692_Y end - attribute \src "ls180.v:8141.8-8141.29" - cell $not $not$ls180.v:8141$2627 + attribute \src "ls180.v:8196.8-8196.29" + cell $not $not$ls180.v:8196$2694 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_rx_trigger - connect \Y $not$ls180.v:8141$2627_Y + connect \Y $not$ls180.v:8196$2694_Y end - attribute \src "ls180.v:8151.80-8151.106" - cell $not $not$ls180.v:8151$2630 + attribute \src "ls180.v:8206.80-8206.106" + cell $not $not$ls180.v:8206$2697 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_replace - connect \Y $not$ls180.v:8151$2630_Y + connect \Y $not$ls180.v:8206$2697_Y end - attribute \src "ls180.v:8157.80-8157.106" - cell $not $not$ls180.v:8157$2635 + attribute \src "ls180.v:8212.80-8212.106" + cell $not $not$ls180.v:8212$2702 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_replace - connect \Y $not$ls180.v:8157$2635_Y + connect \Y $not$ls180.v:8212$2702_Y end - attribute \src "ls180.v:8158.8-8158.34" - cell $not $not$ls180.v:8158$2637 + attribute \src "ls180.v:8213.8-8213.34" + cell $not $not$ls180.v:8213$2704 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_do_read - connect \Y $not$ls180.v:8158$2637_Y + connect \Y $not$ls180.v:8213$2704_Y end - attribute \src "ls180.v:8173.80-8173.106" - cell $not $not$ls180.v:8173$2641 + attribute \src "ls180.v:8228.80-8228.106" + cell $not $not$ls180.v:8228$2708 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_replace - connect \Y $not$ls180.v:8173$2641_Y + connect \Y $not$ls180.v:8228$2708_Y end - attribute \src "ls180.v:8179.80-8179.106" - cell $not $not$ls180.v:8179$2646 + attribute \src "ls180.v:8234.80-8234.106" + cell $not $not$ls180.v:8234$2713 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_replace - connect \Y $not$ls180.v:8179$2646_Y + connect \Y $not$ls180.v:8234$2713_Y end - attribute \src "ls180.v:8180.8-8180.34" - cell $not $not$ls180.v:8180$2648 + attribute \src "ls180.v:8235.8-8235.34" + cell $not $not$ls180.v:8235$2715 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_do_read - connect \Y $not$ls180.v:8180$2648_Y + connect \Y $not$ls180.v:8235$2715_Y end - attribute \src "ls180.v:8211.22-8211.41" - cell $not $not$ls180.v:8211$2652 + attribute \src "ls180.v:8266.22-8266.41" + cell $not $not$ls180.v:8266$2719 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_spimaster6_cs - connect \Y $not$ls180.v:8211$2652_Y + connect \Y $not$ls180.v:8266$2719_Y end - attribute \src "ls180.v:8211.46-8211.73" - cell $not $not$ls180.v:8211$2653 + attribute \src "ls180.v:8266.46-8266.73" + cell $not $not$ls180.v:8266$2720 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_spimaster26_cs_enable - connect \Y $not$ls180.v:8211$2653_Y + connect \Y $not$ls180.v:8266$2720_Y end - attribute \src "ls180.v:8246.22-8246.40" - cell $not $not$ls180.v:8246$2657 + attribute \src "ls180.v:8301.22-8301.40" + cell $not $not$ls180.v:8301$2724 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_spisdcard_cs - connect \Y $not$ls180.v:8246$2657_Y + connect \Y $not$ls180.v:8301$2724_Y end - attribute \src "ls180.v:8246.45-8246.70" - cell $not $not$ls180.v:8246$2658 + attribute \src "ls180.v:8301.45-8301.70" + cell $not $not$ls180.v:8301$2725 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_spisdcard_cs_enable - connect \Y $not$ls180.v:8246$2658_Y + connect \Y $not$ls180.v:8301$2725_Y end - attribute \src "ls180.v:8300.7-8300.31" - cell $not $not$ls180.v:8300$2669 + attribute \src "ls180.v:8355.7-8355.31" + cell $not $not$ls180.v:8355$2736 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_clocker_stop - connect \Y $not$ls180.v:8300$2669_Y + connect \Y $not$ls180.v:8355$2736_Y end - attribute \src "ls180.v:8372.8-8372.46" - cell $not $not$ls180.v:8372$2681 + attribute \src "ls180.v:8427.8-8427.46" + cell $not $not$ls180.v:8427$2748 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_buf_source_valid - connect \Y $not$ls180.v:8372$2681_Y + connect \Y $not$ls180.v:8427$2748_Y end - attribute \src "ls180.v:8453.8-8453.47" - cell $not $not$ls180.v:8453$2693 + attribute \src "ls180.v:8508.8-8508.47" + cell $not $not$ls180.v:8508$2760 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_buf_source_valid - connect \Y $not$ls180.v:8453$2693_Y + connect \Y $not$ls180.v:8508$2760_Y end - attribute \src "ls180.v:8514.8-8514.48" - cell $not $not$ls180.v:8514$2705 + attribute \src "ls180.v:8569.8-8569.48" + cell $not $not$ls180.v:8569$2772 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_buf_source_valid - connect \Y $not$ls180.v:8514$2705_Y + connect \Y $not$ls180.v:8569$2772_Y end - attribute \src "ls180.v:8684.88-8684.118" - cell $not $not$ls180.v:8684$2719 + attribute \src "ls180.v:8739.88-8739.118" + cell $not $not$ls180.v:8739$2786 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_fifo_replace - connect \Y $not$ls180.v:8684$2719_Y + connect \Y $not$ls180.v:8739$2786_Y end - attribute \src "ls180.v:8690.88-8690.118" - cell $not $not$ls180.v:8690$2724 + attribute \src "ls180.v:8745.88-8745.118" + cell $not $not$ls180.v:8745$2791 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_fifo_replace - connect \Y $not$ls180.v:8690$2724_Y + connect \Y $not$ls180.v:8745$2791_Y end - attribute \src "ls180.v:8691.8-8691.38" - cell $not $not$ls180.v:8691$2726 + attribute \src "ls180.v:8746.8-8746.38" + cell $not $not$ls180.v:8746$2793 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_fifo_do_read - connect \Y $not$ls180.v:8691$2726_Y + connect \Y $not$ls180.v:8746$2793_Y end - attribute \src "ls180.v:8770.88-8770.118" - cell $not $not$ls180.v:8770$2741 + attribute \src "ls180.v:8837.88-8837.118" + cell $not $not$ls180.v:8837$2808 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_fifo_replace - connect \Y $not$ls180.v:8770$2741_Y + connect \Y $not$ls180.v:8837$2808_Y end - attribute \src "ls180.v:8776.88-8776.118" - cell $not $not$ls180.v:8776$2746 + attribute \src "ls180.v:8843.88-8843.118" + cell $not $not$ls180.v:8843$2813 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_fifo_replace - connect \Y $not$ls180.v:8776$2746_Y + connect \Y $not$ls180.v:8843$2813_Y end - attribute \src "ls180.v:8777.8-8777.38" - cell $not $not$ls180.v:8777$2748 + attribute \src "ls180.v:8844.8-8844.38" + cell $not $not$ls180.v:8844$2815 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_fifo_do_read - connect \Y $not$ls180.v:8777$2748_Y + connect \Y $not$ls180.v:8844$2815_Y end - attribute \src "ls180.v:8797.9-8797.28" - cell $not $not$ls180.v:8797$2751 + attribute \src "ls180.v:8864.9-8864.28" + cell $not $not$ls180.v:8864$2818 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_request [0] - connect \Y $not$ls180.v:8797$2751_Y + connect \Y $not$ls180.v:8864$2818_Y end - attribute \src "ls180.v:8816.9-8816.28" - cell $not $not$ls180.v:8816$2752 + attribute \src "ls180.v:8883.9-8883.28" + cell $not $not$ls180.v:8883$2819 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_request [1] - connect \Y $not$ls180.v:8816$2752_Y + connect \Y $not$ls180.v:8883$2819_Y end - attribute \src "ls180.v:8835.9-8835.28" - cell $not $not$ls180.v:8835$2753 + attribute \src "ls180.v:8902.9-8902.28" + cell $not $not$ls180.v:8902$2820 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_request [2] - connect \Y $not$ls180.v:8835$2753_Y + connect \Y $not$ls180.v:8902$2820_Y end - attribute \src "ls180.v:8854.9-8854.28" - cell $not $not$ls180.v:8854$2754 + attribute \src "ls180.v:8921.9-8921.28" + cell $not $not$ls180.v:8921$2821 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_request [3] - connect \Y $not$ls180.v:8854$2754_Y + connect \Y $not$ls180.v:8921$2821_Y end - attribute \src "ls180.v:8873.9-8873.28" - cell $not $not$ls180.v:8873$2755 + attribute \src "ls180.v:8940.9-8940.28" + cell $not $not$ls180.v:8940$2822 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_request [4] - connect \Y $not$ls180.v:8873$2755_Y + connect \Y $not$ls180.v:8940$2822_Y end - attribute \src "ls180.v:8894.8-8894.21" - cell $not $not$ls180.v:8894$2756 + attribute \src "ls180.v:8961.8-8961.21" + cell $not $not$ls180.v:8961$2823 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_done - connect \Y $not$ls180.v:8894$2756_Y + connect \Y $not$ls180.v:8961$2823_Y end - attribute \src "ls180.v:10456.8-10456.51" - cell $or $or$ls180.v:10456$2870 + attribute \src "ls180.v:10555.8-10555.51" + cell $or $or$ls180.v:10555$2985 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258226,54 +259302,54 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sys_rst_1 connect \B \main_libresocsim_libresoc_reset - connect \Y $or$ls180.v:10456$2870_Y + connect \Y $or$ls180.v:10555$2985_Y end - attribute \src "ls180.v:2859.10-2859.96" - cell $or $or$ls180.v:2859$33 + attribute \src "ls180.v:2872.10-2872.71" + cell $or $or$ls180.v:2872$49 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_interface0_converted_interface_ack - connect \B \main_libresocsim_converter0_skip - connect \Y $or$ls180.v:2859$33_Y + connect \A \main_libresocsim_libresoc_xics_icp_ack + connect \B \main_converter0_skip + connect \Y $or$ls180.v:2872$49_Y end - attribute \src "ls180.v:2919.10-2919.96" - cell $or $or$ls180.v:2919$44 + attribute \src "ls180.v:2932.10-2932.71" + cell $or $or$ls180.v:2932$60 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_interface1_converted_interface_ack - connect \B \main_libresocsim_converter1_skip - connect \Y $or$ls180.v:2919$44_Y + connect \A \main_libresocsim_libresoc_xics_ics_ack + connect \B \main_converter1_skip + connect \Y $or$ls180.v:2932$60_Y end - attribute \src "ls180.v:2979.10-2979.96" - cell $or $or$ls180.v:2979$55 + attribute \src "ls180.v:2992.10-2992.53" + cell $or $or$ls180.v:2992$71 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_interface2_converted_interface_ack - connect \B \main_libresocsim_converter2_skip - connect \Y $or$ls180.v:2979$55_Y + connect \A \main_wb_sdram_ack + connect \B \main_socbushandler_skip + connect \Y $or$ls180.v:2992$71_Y end - attribute \src "ls180.v:3201.39-3201.105" - cell $or $or$ls180.v:3201$126 + attribute \src "ls180.v:3230.39-3230.105" + cell $or $or$ls180.v:3230$190 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_start0 - connect \B $ne$ls180.v:3201$125_Y - connect \Y $or$ls180.v:3201$126_Y + connect \B $ne$ls180.v:3230$189_Y + connect \Y $or$ls180.v:3230$190_Y end - attribute \src "ls180.v:3244.59-3244.140" - cell $or $or$ls180.v:3244$130 + attribute \src "ls180.v:3273.59-3273.140" + cell $or $or$ls180.v:3273$194 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258281,10 +259357,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_req_wdata_ready connect \B \main_sdram_bankmachine0_req_rdata_valid - connect \Y $or$ls180.v:3244$130_Y + connect \Y $or$ls180.v:3273$194_Y end - attribute \src "ls180.v:3245.44-3245.151" - cell $or $or$ls180.v:3245$131 + attribute \src "ls180.v:3274.44-3274.151" + cell $or $or$ls180.v:3274$195 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258292,21 +259368,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid connect \B \main_sdram_bankmachine0_cmd_buffer_source_valid - connect \Y $or$ls180.v:3245$131_Y + connect \Y $or$ls180.v:3274$195_Y end - attribute \src "ls180.v:3253.45-3253.170" - cell $or $or$ls180.v:3253$135 + attribute \src "ls180.v:3282.45-3282.170" + cell $or $or$ls180.v:3282$199 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 parameter \B_WIDTH 13 parameter \Y_WIDTH 13 - connect \A $sshl$ls180.v:3253$134_Y + connect \A $sshl$ls180.v:3282$198_Y connect \B { 4'0000 \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [8:0] } - connect \Y $or$ls180.v:3253$135_Y + connect \Y $or$ls180.v:3282$199_Y end - attribute \src "ls180.v:3290.127-3290.245" - cell $or $or$ls180.v:3290$148 + attribute \src "ls180.v:3319.127-3319.245" + cell $or $or$ls180.v:3319$212 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258314,21 +259390,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_replace - connect \Y $or$ls180.v:3290$148_Y + connect \Y $or$ls180.v:3319$212_Y end - attribute \src "ls180.v:3296.57-3296.157" - cell $or $or$ls180.v:3296$154 + attribute \src "ls180.v:3325.57-3325.157" + cell $or $or$ls180.v:3325$218 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3296$153_Y + connect \A $not$ls180.v:3325$217_Y connect \B \main_sdram_bankmachine0_cmd_buffer_source_ready - connect \Y $or$ls180.v:3296$154_Y + connect \Y $or$ls180.v:3325$218_Y end - attribute \src "ls180.v:3401.59-3401.140" - cell $or $or$ls180.v:3401$160 + attribute \src "ls180.v:3430.59-3430.140" + cell $or $or$ls180.v:3430$224 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258336,10 +259412,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_req_wdata_ready connect \B \main_sdram_bankmachine1_req_rdata_valid - connect \Y $or$ls180.v:3401$160_Y + connect \Y $or$ls180.v:3430$224_Y end - attribute \src "ls180.v:3402.44-3402.151" - cell $or $or$ls180.v:3402$161 + attribute \src "ls180.v:3431.44-3431.151" + cell $or $or$ls180.v:3431$225 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258347,21 +259423,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid connect \B \main_sdram_bankmachine1_cmd_buffer_source_valid - connect \Y $or$ls180.v:3402$161_Y + connect \Y $or$ls180.v:3431$225_Y end - attribute \src "ls180.v:3410.45-3410.170" - cell $or $or$ls180.v:3410$165 + attribute \src "ls180.v:3439.45-3439.170" + cell $or $or$ls180.v:3439$229 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 parameter \B_WIDTH 13 parameter \Y_WIDTH 13 - connect \A $sshl$ls180.v:3410$164_Y + connect \A $sshl$ls180.v:3439$228_Y connect \B { 4'0000 \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [8:0] } - connect \Y $or$ls180.v:3410$165_Y + connect \Y $or$ls180.v:3439$229_Y end - attribute \src "ls180.v:3447.127-3447.245" - cell $or $or$ls180.v:3447$178 + attribute \src "ls180.v:3476.127-3476.245" + cell $or $or$ls180.v:3476$242 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258369,21 +259445,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_replace - connect \Y $or$ls180.v:3447$178_Y + connect \Y $or$ls180.v:3476$242_Y end - attribute \src "ls180.v:3453.57-3453.157" - cell $or $or$ls180.v:3453$184 + attribute \src "ls180.v:3482.57-3482.157" + cell $or $or$ls180.v:3482$248 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3453$183_Y + connect \A $not$ls180.v:3482$247_Y connect \B \main_sdram_bankmachine1_cmd_buffer_source_ready - connect \Y $or$ls180.v:3453$184_Y + connect \Y $or$ls180.v:3482$248_Y end - attribute \src "ls180.v:3558.59-3558.140" - cell $or $or$ls180.v:3558$190 + attribute \src "ls180.v:3587.59-3587.140" + cell $or $or$ls180.v:3587$254 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258391,10 +259467,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_req_wdata_ready connect \B \main_sdram_bankmachine2_req_rdata_valid - connect \Y $or$ls180.v:3558$190_Y + connect \Y $or$ls180.v:3587$254_Y end - attribute \src "ls180.v:3559.44-3559.151" - cell $or $or$ls180.v:3559$191 + attribute \src "ls180.v:3588.44-3588.151" + cell $or $or$ls180.v:3588$255 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258402,21 +259478,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid connect \B \main_sdram_bankmachine2_cmd_buffer_source_valid - connect \Y $or$ls180.v:3559$191_Y + connect \Y $or$ls180.v:3588$255_Y end - attribute \src "ls180.v:3567.45-3567.170" - cell $or $or$ls180.v:3567$195 + attribute \src "ls180.v:3596.45-3596.170" + cell $or $or$ls180.v:3596$259 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 parameter \B_WIDTH 13 parameter \Y_WIDTH 13 - connect \A $sshl$ls180.v:3567$194_Y + connect \A $sshl$ls180.v:3596$258_Y connect \B { 4'0000 \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [8:0] } - connect \Y $or$ls180.v:3567$195_Y + connect \Y $or$ls180.v:3596$259_Y end - attribute \src "ls180.v:3604.127-3604.245" - cell $or $or$ls180.v:3604$208 + attribute \src "ls180.v:3633.127-3633.245" + cell $or $or$ls180.v:3633$272 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258424,21 +259500,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_replace - connect \Y $or$ls180.v:3604$208_Y + connect \Y $or$ls180.v:3633$272_Y end - attribute \src "ls180.v:3610.57-3610.157" - cell $or $or$ls180.v:3610$214 + attribute \src "ls180.v:3639.57-3639.157" + cell $or $or$ls180.v:3639$278 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3610$213_Y + connect \A $not$ls180.v:3639$277_Y connect \B \main_sdram_bankmachine2_cmd_buffer_source_ready - connect \Y $or$ls180.v:3610$214_Y + connect \Y $or$ls180.v:3639$278_Y end - attribute \src "ls180.v:3715.59-3715.140" - cell $or $or$ls180.v:3715$220 + attribute \src "ls180.v:3744.59-3744.140" + cell $or $or$ls180.v:3744$284 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258446,10 +259522,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_req_wdata_ready connect \B \main_sdram_bankmachine3_req_rdata_valid - connect \Y $or$ls180.v:3715$220_Y + connect \Y $or$ls180.v:3744$284_Y end - attribute \src "ls180.v:3716.44-3716.151" - cell $or $or$ls180.v:3716$221 + attribute \src "ls180.v:3745.44-3745.151" + cell $or $or$ls180.v:3745$285 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258457,21 +259533,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid connect \B \main_sdram_bankmachine3_cmd_buffer_source_valid - connect \Y $or$ls180.v:3716$221_Y + connect \Y $or$ls180.v:3745$285_Y end - attribute \src "ls180.v:3724.45-3724.170" - cell $or $or$ls180.v:3724$225 + attribute \src "ls180.v:3753.45-3753.170" + cell $or $or$ls180.v:3753$289 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 parameter \B_WIDTH 13 parameter \Y_WIDTH 13 - connect \A $sshl$ls180.v:3724$224_Y + connect \A $sshl$ls180.v:3753$288_Y connect \B { 4'0000 \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [8:0] } - connect \Y $or$ls180.v:3724$225_Y + connect \Y $or$ls180.v:3753$289_Y end - attribute \src "ls180.v:3761.127-3761.245" - cell $or $or$ls180.v:3761$238 + attribute \src "ls180.v:3790.127-3790.245" + cell $or $or$ls180.v:3790$302 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258479,21 +259555,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_replace - connect \Y $or$ls180.v:3761$238_Y + connect \Y $or$ls180.v:3790$302_Y end - attribute \src "ls180.v:3767.57-3767.157" - cell $or $or$ls180.v:3767$244 + attribute \src "ls180.v:3796.57-3796.157" + cell $or $or$ls180.v:3796$308 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3767$243_Y + connect \A $not$ls180.v:3796$307_Y connect \B \main_sdram_bankmachine3_cmd_buffer_source_ready - connect \Y $or$ls180.v:3767$244_Y + connect \Y $or$ls180.v:3796$308_Y end - attribute \src "ls180.v:3866.107-3866.193" - cell $or $or$ls180.v:3866$264 + attribute \src "ls180.v:3895.107-3895.193" + cell $or $or$ls180.v:3895$328 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258501,626 +259577,626 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_is_write connect \B \main_sdram_choose_req_cmd_payload_is_read - connect \Y $or$ls180.v:3866$264_Y + connect \Y $or$ls180.v:3895$328_Y end - attribute \src "ls180.v:3869.39-3869.204" - cell $or $or$ls180.v:3869$270 + attribute \src "ls180.v:3898.39-3898.204" + cell $or $or$ls180.v:3898$334 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3869$268_Y - connect \B $and$ls180.v:3869$269_Y - connect \Y $or$ls180.v:3869$270_Y + connect \A $and$ls180.v:3898$332_Y + connect \B $and$ls180.v:3898$333_Y + connect \Y $or$ls180.v:3898$334_Y end - attribute \src "ls180.v:3869.38-3869.289" - cell $or $or$ls180.v:3869$272 + attribute \src "ls180.v:3898.38-3898.289" + cell $or $or$ls180.v:3898$336 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3869$270_Y - connect \B $and$ls180.v:3869$271_Y - connect \Y $or$ls180.v:3869$272_Y + connect \A $or$ls180.v:3898$334_Y + connect \B $and$ls180.v:3898$335_Y + connect \Y $or$ls180.v:3898$336_Y end - attribute \src "ls180.v:3869.37-3869.374" - cell $or $or$ls180.v:3869$274 + attribute \src "ls180.v:3898.37-3898.374" + cell $or $or$ls180.v:3898$338 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3869$272_Y - connect \B $and$ls180.v:3869$273_Y - connect \Y $or$ls180.v:3869$274_Y + connect \A $or$ls180.v:3898$336_Y + connect \B $and$ls180.v:3898$337_Y + connect \Y $or$ls180.v:3898$338_Y end - attribute \src "ls180.v:3870.40-3870.207" - cell $or $or$ls180.v:3870$277 + attribute \src "ls180.v:3899.40-3899.207" + cell $or $or$ls180.v:3899$341 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3870$275_Y - connect \B $and$ls180.v:3870$276_Y - connect \Y $or$ls180.v:3870$277_Y + connect \A $and$ls180.v:3899$339_Y + connect \B $and$ls180.v:3899$340_Y + connect \Y $or$ls180.v:3899$341_Y end - attribute \src "ls180.v:3870.39-3870.293" - cell $or $or$ls180.v:3870$279 + attribute \src "ls180.v:3899.39-3899.293" + cell $or $or$ls180.v:3899$343 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3870$277_Y - connect \B $and$ls180.v:3870$278_Y - connect \Y $or$ls180.v:3870$279_Y + connect \A $or$ls180.v:3899$341_Y + connect \B $and$ls180.v:3899$342_Y + connect \Y $or$ls180.v:3899$343_Y end - attribute \src "ls180.v:3870.38-3870.379" - cell $or $or$ls180.v:3870$281 + attribute \src "ls180.v:3899.38-3899.379" + cell $or $or$ls180.v:3899$345 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3870$279_Y - connect \B $and$ls180.v:3870$280_Y - connect \Y $or$ls180.v:3870$281_Y + connect \A $or$ls180.v:3899$343_Y + connect \B $and$ls180.v:3899$344_Y + connect \Y $or$ls180.v:3899$345_Y end - attribute \src "ls180.v:3883.158-3883.332" - cell $or $or$ls180.v:3883$295 + attribute \src "ls180.v:3912.158-3912.332" + cell $or $or$ls180.v:3912$359 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3883$294_Y + connect \A $not$ls180.v:3912$358_Y connect \B \main_sdram_choose_cmd_want_activates - connect \Y $or$ls180.v:3883$295_Y + connect \Y $or$ls180.v:3912$359_Y end - attribute \src "ls180.v:3883.75-3883.506" - cell $or $or$ls180.v:3883$300 + attribute \src "ls180.v:3912.75-3912.506" + cell $or $or$ls180.v:3912$364 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3883$296_Y - connect \B $and$ls180.v:3883$299_Y - connect \Y $or$ls180.v:3883$300_Y + connect \A $and$ls180.v:3912$360_Y + connect \B $and$ls180.v:3912$363_Y + connect \Y $or$ls180.v:3912$364_Y end - attribute \src "ls180.v:3884.158-3884.332" - cell $or $or$ls180.v:3884$308 + attribute \src "ls180.v:3913.158-3913.332" + cell $or $or$ls180.v:3913$372 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3884$307_Y + connect \A $not$ls180.v:3913$371_Y connect \B \main_sdram_choose_cmd_want_activates - connect \Y $or$ls180.v:3884$308_Y + connect \Y $or$ls180.v:3913$372_Y end - attribute \src "ls180.v:3884.75-3884.506" - cell $or $or$ls180.v:3884$313 + attribute \src "ls180.v:3913.75-3913.506" + cell $or $or$ls180.v:3913$377 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3884$309_Y - connect \B $and$ls180.v:3884$312_Y - connect \Y $or$ls180.v:3884$313_Y + connect \A $and$ls180.v:3913$373_Y + connect \B $and$ls180.v:3913$376_Y + connect \Y $or$ls180.v:3913$377_Y end - attribute \src "ls180.v:3885.158-3885.332" - cell $or $or$ls180.v:3885$321 + attribute \src "ls180.v:3914.158-3914.332" + cell $or $or$ls180.v:3914$385 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3885$320_Y + connect \A $not$ls180.v:3914$384_Y connect \B \main_sdram_choose_cmd_want_activates - connect \Y $or$ls180.v:3885$321_Y + connect \Y $or$ls180.v:3914$385_Y end - attribute \src "ls180.v:3885.75-3885.506" - cell $or $or$ls180.v:3885$326 + attribute \src "ls180.v:3914.75-3914.506" + cell $or $or$ls180.v:3914$390 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3885$322_Y - connect \B $and$ls180.v:3885$325_Y - connect \Y $or$ls180.v:3885$326_Y + connect \A $and$ls180.v:3914$386_Y + connect \B $and$ls180.v:3914$389_Y + connect \Y $or$ls180.v:3914$390_Y end - attribute \src "ls180.v:3886.158-3886.332" - cell $or $or$ls180.v:3886$334 + attribute \src "ls180.v:3915.158-3915.332" + cell $or $or$ls180.v:3915$398 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3886$333_Y + connect \A $not$ls180.v:3915$397_Y connect \B \main_sdram_choose_cmd_want_activates - connect \Y $or$ls180.v:3886$334_Y + connect \Y $or$ls180.v:3915$398_Y end - attribute \src "ls180.v:3886.75-3886.506" - cell $or $or$ls180.v:3886$339 + attribute \src "ls180.v:3915.75-3915.506" + cell $or $or$ls180.v:3915$403 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3886$335_Y - connect \B $and$ls180.v:3886$338_Y - connect \Y $or$ls180.v:3886$339_Y + connect \A $and$ls180.v:3915$399_Y + connect \B $and$ls180.v:3915$402_Y + connect \Y $or$ls180.v:3915$403_Y end - attribute \src "ls180.v:3913.36-3913.104" - cell $or $or$ls180.v:3913$345 + attribute \src "ls180.v:3942.36-3942.104" + cell $or $or$ls180.v:3942$409 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_cmd_cmd_ready - connect \B $not$ls180.v:3913$344_Y - connect \Y $or$ls180.v:3913$345_Y + connect \B $not$ls180.v:3942$408_Y + connect \Y $or$ls180.v:3942$409_Y end - attribute \src "ls180.v:3916.158-3916.332" - cell $or $or$ls180.v:3916$353 + attribute \src "ls180.v:3945.158-3945.332" + cell $or $or$ls180.v:3945$417 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3916$352_Y + connect \A $not$ls180.v:3945$416_Y connect \B \main_sdram_choose_req_want_activates - connect \Y $or$ls180.v:3916$353_Y + connect \Y $or$ls180.v:3945$417_Y end - attribute \src "ls180.v:3916.75-3916.506" - cell $or $or$ls180.v:3916$358 + attribute \src "ls180.v:3945.75-3945.506" + cell $or $or$ls180.v:3945$422 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3916$354_Y - connect \B $and$ls180.v:3916$357_Y - connect \Y $or$ls180.v:3916$358_Y + connect \A $and$ls180.v:3945$418_Y + connect \B $and$ls180.v:3945$421_Y + connect \Y $or$ls180.v:3945$422_Y end - attribute \src "ls180.v:3917.158-3917.332" - cell $or $or$ls180.v:3917$366 + attribute \src "ls180.v:3946.158-3946.332" + cell $or $or$ls180.v:3946$430 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3917$365_Y + connect \A $not$ls180.v:3946$429_Y connect \B \main_sdram_choose_req_want_activates - connect \Y $or$ls180.v:3917$366_Y + connect \Y $or$ls180.v:3946$430_Y end - attribute \src "ls180.v:3917.75-3917.506" - cell $or $or$ls180.v:3917$371 + attribute \src "ls180.v:3946.75-3946.506" + cell $or $or$ls180.v:3946$435 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3917$367_Y - connect \B $and$ls180.v:3917$370_Y - connect \Y $or$ls180.v:3917$371_Y + connect \A $and$ls180.v:3946$431_Y + connect \B $and$ls180.v:3946$434_Y + connect \Y $or$ls180.v:3946$435_Y end - attribute \src "ls180.v:3918.158-3918.332" - cell $or $or$ls180.v:3918$379 + attribute \src "ls180.v:3947.158-3947.332" + cell $or $or$ls180.v:3947$443 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3918$378_Y + connect \A $not$ls180.v:3947$442_Y connect \B \main_sdram_choose_req_want_activates - connect \Y $or$ls180.v:3918$379_Y + connect \Y $or$ls180.v:3947$443_Y end - attribute \src "ls180.v:3918.75-3918.506" - cell $or $or$ls180.v:3918$384 + attribute \src "ls180.v:3947.75-3947.506" + cell $or $or$ls180.v:3947$448 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3918$380_Y - connect \B $and$ls180.v:3918$383_Y - connect \Y $or$ls180.v:3918$384_Y + connect \A $and$ls180.v:3947$444_Y + connect \B $and$ls180.v:3947$447_Y + connect \Y $or$ls180.v:3947$448_Y end - attribute \src "ls180.v:3919.158-3919.332" - cell $or $or$ls180.v:3919$392 + attribute \src "ls180.v:3948.158-3948.332" + cell $or $or$ls180.v:3948$456 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3919$391_Y + connect \A $not$ls180.v:3948$455_Y connect \B \main_sdram_choose_req_want_activates - connect \Y $or$ls180.v:3919$392_Y + connect \Y $or$ls180.v:3948$456_Y end - attribute \src "ls180.v:3919.75-3919.506" - cell $or $or$ls180.v:3919$397 + attribute \src "ls180.v:3948.75-3948.506" + cell $or $or$ls180.v:3948$461 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3919$393_Y - connect \B $and$ls180.v:3919$396_Y - connect \Y $or$ls180.v:3919$397_Y + connect \A $and$ls180.v:3948$457_Y + connect \B $and$ls180.v:3948$460_Y + connect \Y $or$ls180.v:3948$461_Y end - attribute \src "ls180.v:3982.36-3982.104" - cell $or $or$ls180.v:3982$431 + attribute \src "ls180.v:4011.36-4011.104" + cell $or $or$ls180.v:4011$495 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_ready - connect \B $not$ls180.v:3982$430_Y - connect \Y $or$ls180.v:3982$431_Y + connect \B $not$ls180.v:4011$494_Y + connect \Y $or$ls180.v:4011$495_Y end - attribute \src "ls180.v:4003.67-4003.221" - cell $or $or$ls180.v:4003$438 + attribute \src "ls180.v:4032.67-4032.221" + cell $or $or$ls180.v:4032$502 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4003$437_Y + connect \A $not$ls180.v:4032$501_Y connect \B \main_sdram_ras_allowed - connect \Y $or$ls180.v:4003$438_Y + connect \Y $or$ls180.v:4032$502_Y end - attribute \src "ls180.v:4011.10-4011.62" - cell $or $or$ls180.v:4011$441 + attribute \src "ls180.v:4040.10-4040.62" + cell $or $or$ls180.v:4040$505 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4011$440_Y + connect \A $not$ls180.v:4040$504_Y connect \B \main_sdram_max_time1 - connect \Y $or$ls180.v:4011$441_Y + connect \Y $or$ls180.v:4040$505_Y end - attribute \src "ls180.v:4041.67-4041.221" - cell $or $or$ls180.v:4041$447 + attribute \src "ls180.v:4070.67-4070.221" + cell $or $or$ls180.v:4070$511 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4041$446_Y + connect \A $not$ls180.v:4070$510_Y connect \B \main_sdram_ras_allowed - connect \Y $or$ls180.v:4041$447_Y + connect \Y $or$ls180.v:4070$511_Y end - attribute \src "ls180.v:4049.10-4049.61" - cell $or $or$ls180.v:4049$450 + attribute \src "ls180.v:4078.10-4078.61" + cell $or $or$ls180.v:4078$514 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4049$449_Y + connect \A $not$ls180.v:4078$513_Y connect \B \main_sdram_max_time0 - connect \Y $or$ls180.v:4049$450_Y + connect \Y $or$ls180.v:4078$514_Y end - attribute \src "ls180.v:4059.91-4059.180" - cell $or $or$ls180.v:4059$454 + attribute \src "ls180.v:4088.91-4088.180" + cell $or $or$ls180.v:4088$518 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_locked0 - connect \B $and$ls180.v:4059$453_Y - connect \Y $or$ls180.v:4059$454_Y + connect \B $and$ls180.v:4088$517_Y + connect \Y $or$ls180.v:4088$518_Y end - attribute \src "ls180.v:4059.90-4059.255" - cell $or $or$ls180.v:4059$457 + attribute \src "ls180.v:4088.90-4088.255" + cell $or $or$ls180.v:4088$521 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4059$454_Y - connect \B $and$ls180.v:4059$456_Y - connect \Y $or$ls180.v:4059$457_Y + connect \A $or$ls180.v:4088$518_Y + connect \B $and$ls180.v:4088$520_Y + connect \Y $or$ls180.v:4088$521_Y end - attribute \src "ls180.v:4059.89-4059.330" - cell $or $or$ls180.v:4059$460 + attribute \src "ls180.v:4088.89-4088.330" + cell $or $or$ls180.v:4088$524 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4059$457_Y - connect \B $and$ls180.v:4059$459_Y - connect \Y $or$ls180.v:4059$460_Y + connect \A $or$ls180.v:4088$521_Y + connect \B $and$ls180.v:4088$523_Y + connect \Y $or$ls180.v:4088$524_Y end - attribute \src "ls180.v:4064.91-4064.180" - cell $or $or$ls180.v:4064$470 + attribute \src "ls180.v:4093.91-4093.180" + cell $or $or$ls180.v:4093$534 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_locked1 - connect \B $and$ls180.v:4064$469_Y - connect \Y $or$ls180.v:4064$470_Y + connect \B $and$ls180.v:4093$533_Y + connect \Y $or$ls180.v:4093$534_Y end - attribute \src "ls180.v:4064.90-4064.255" - cell $or $or$ls180.v:4064$473 + attribute \src "ls180.v:4093.90-4093.255" + cell $or $or$ls180.v:4093$537 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4064$470_Y - connect \B $and$ls180.v:4064$472_Y - connect \Y $or$ls180.v:4064$473_Y + connect \A $or$ls180.v:4093$534_Y + connect \B $and$ls180.v:4093$536_Y + connect \Y $or$ls180.v:4093$537_Y end - attribute \src "ls180.v:4064.89-4064.330" - cell $or $or$ls180.v:4064$476 + attribute \src "ls180.v:4093.89-4093.330" + cell $or $or$ls180.v:4093$540 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4064$473_Y - connect \B $and$ls180.v:4064$475_Y - connect \Y $or$ls180.v:4064$476_Y + connect \A $or$ls180.v:4093$537_Y + connect \B $and$ls180.v:4093$539_Y + connect \Y $or$ls180.v:4093$540_Y end - attribute \src "ls180.v:4069.91-4069.180" - cell $or $or$ls180.v:4069$486 + attribute \src "ls180.v:4098.91-4098.180" + cell $or $or$ls180.v:4098$550 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_locked2 - connect \B $and$ls180.v:4069$485_Y - connect \Y $or$ls180.v:4069$486_Y + connect \B $and$ls180.v:4098$549_Y + connect \Y $or$ls180.v:4098$550_Y end - attribute \src "ls180.v:4069.90-4069.255" - cell $or $or$ls180.v:4069$489 + attribute \src "ls180.v:4098.90-4098.255" + cell $or $or$ls180.v:4098$553 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4069$486_Y - connect \B $and$ls180.v:4069$488_Y - connect \Y $or$ls180.v:4069$489_Y + connect \A $or$ls180.v:4098$550_Y + connect \B $and$ls180.v:4098$552_Y + connect \Y $or$ls180.v:4098$553_Y end - attribute \src "ls180.v:4069.89-4069.330" - cell $or $or$ls180.v:4069$492 + attribute \src "ls180.v:4098.89-4098.330" + cell $or $or$ls180.v:4098$556 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4069$489_Y - connect \B $and$ls180.v:4069$491_Y - connect \Y $or$ls180.v:4069$492_Y + connect \A $or$ls180.v:4098$553_Y + connect \B $and$ls180.v:4098$555_Y + connect \Y $or$ls180.v:4098$556_Y end - attribute \src "ls180.v:4074.91-4074.180" - cell $or $or$ls180.v:4074$502 + attribute \src "ls180.v:4103.91-4103.180" + cell $or $or$ls180.v:4103$566 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_locked3 - connect \B $and$ls180.v:4074$501_Y - connect \Y $or$ls180.v:4074$502_Y + connect \B $and$ls180.v:4103$565_Y + connect \Y $or$ls180.v:4103$566_Y end - attribute \src "ls180.v:4074.90-4074.255" - cell $or $or$ls180.v:4074$505 + attribute \src "ls180.v:4103.90-4103.255" + cell $or $or$ls180.v:4103$569 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4074$502_Y - connect \B $and$ls180.v:4074$504_Y - connect \Y $or$ls180.v:4074$505_Y + connect \A $or$ls180.v:4103$566_Y + connect \B $and$ls180.v:4103$568_Y + connect \Y $or$ls180.v:4103$569_Y end - attribute \src "ls180.v:4074.89-4074.330" - cell $or $or$ls180.v:4074$508 + attribute \src "ls180.v:4103.89-4103.330" + cell $or $or$ls180.v:4103$572 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4074$505_Y - connect \B $and$ls180.v:4074$507_Y - connect \Y $or$ls180.v:4074$508_Y + connect \A $or$ls180.v:4103$569_Y + connect \B $and$ls180.v:4103$571_Y + connect \Y $or$ls180.v:4103$572_Y end - attribute \src "ls180.v:4079.132-4079.221" - cell $or $or$ls180.v:4079$519 + attribute \src "ls180.v:4108.132-4108.221" + cell $or $or$ls180.v:4108$583 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_locked0 - connect \B $and$ls180.v:4079$518_Y - connect \Y $or$ls180.v:4079$519_Y + connect \B $and$ls180.v:4108$582_Y + connect \Y $or$ls180.v:4108$583_Y end - attribute \src "ls180.v:4079.131-4079.296" - cell $or $or$ls180.v:4079$522 + attribute \src "ls180.v:4108.131-4108.296" + cell $or $or$ls180.v:4108$586 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4079$519_Y - connect \B $and$ls180.v:4079$521_Y - connect \Y $or$ls180.v:4079$522_Y + connect \A $or$ls180.v:4108$583_Y + connect \B $and$ls180.v:4108$585_Y + connect \Y $or$ls180.v:4108$586_Y end - attribute \src "ls180.v:4079.130-4079.371" - cell $or $or$ls180.v:4079$525 + attribute \src "ls180.v:4108.130-4108.371" + cell $or $or$ls180.v:4108$589 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4079$522_Y - connect \B $and$ls180.v:4079$524_Y - connect \Y $or$ls180.v:4079$525_Y + connect \A $or$ls180.v:4108$586_Y + connect \B $and$ls180.v:4108$588_Y + connect \Y $or$ls180.v:4108$589_Y end - attribute \src "ls180.v:4079.34-4079.411" - cell $or $or$ls180.v:4079$530 + attribute \src "ls180.v:4108.34-4108.411" + cell $or $or$ls180.v:4108$594 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A 1'0 - connect \B $and$ls180.v:4079$529_Y - connect \Y $or$ls180.v:4079$530_Y + connect \B $and$ls180.v:4108$593_Y + connect \Y $or$ls180.v:4108$594_Y end - attribute \src "ls180.v:4079.506-4079.595" - cell $or $or$ls180.v:4079$535 + attribute \src "ls180.v:4108.506-4108.595" + cell $or $or$ls180.v:4108$599 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_locked1 - connect \B $and$ls180.v:4079$534_Y - connect \Y $or$ls180.v:4079$535_Y + connect \B $and$ls180.v:4108$598_Y + connect \Y $or$ls180.v:4108$599_Y end - attribute \src "ls180.v:4079.505-4079.670" - cell $or $or$ls180.v:4079$538 + attribute \src "ls180.v:4108.505-4108.670" + cell $or $or$ls180.v:4108$602 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4079$535_Y - connect \B $and$ls180.v:4079$537_Y - connect \Y $or$ls180.v:4079$538_Y + connect \A $or$ls180.v:4108$599_Y + connect \B $and$ls180.v:4108$601_Y + connect \Y $or$ls180.v:4108$602_Y end - attribute \src "ls180.v:4079.504-4079.745" - cell $or $or$ls180.v:4079$541 + attribute \src "ls180.v:4108.504-4108.745" + cell $or $or$ls180.v:4108$605 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4079$538_Y - connect \B $and$ls180.v:4079$540_Y - connect \Y $or$ls180.v:4079$541_Y + connect \A $or$ls180.v:4108$602_Y + connect \B $and$ls180.v:4108$604_Y + connect \Y $or$ls180.v:4108$605_Y end - attribute \src "ls180.v:4079.33-4079.785" - cell $or $or$ls180.v:4079$546 + attribute \src "ls180.v:4108.33-4108.785" + cell $or $or$ls180.v:4108$610 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4079$530_Y - connect \B $and$ls180.v:4079$545_Y - connect \Y $or$ls180.v:4079$546_Y + connect \A $or$ls180.v:4108$594_Y + connect \B $and$ls180.v:4108$609_Y + connect \Y $or$ls180.v:4108$610_Y end - attribute \src "ls180.v:4079.880-4079.969" - cell $or $or$ls180.v:4079$551 + attribute \src "ls180.v:4108.880-4108.969" + cell $or $or$ls180.v:4108$615 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_locked2 - connect \B $and$ls180.v:4079$550_Y - connect \Y $or$ls180.v:4079$551_Y + connect \B $and$ls180.v:4108$614_Y + connect \Y $or$ls180.v:4108$615_Y end - attribute \src "ls180.v:4079.879-4079.1044" - cell $or $or$ls180.v:4079$554 + attribute \src "ls180.v:4108.879-4108.1044" + cell $or $or$ls180.v:4108$618 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4079$551_Y - connect \B $and$ls180.v:4079$553_Y - connect \Y $or$ls180.v:4079$554_Y + connect \A $or$ls180.v:4108$615_Y + connect \B $and$ls180.v:4108$617_Y + connect \Y $or$ls180.v:4108$618_Y end - attribute \src "ls180.v:4079.878-4079.1119" - cell $or $or$ls180.v:4079$557 + attribute \src "ls180.v:4108.878-4108.1119" + cell $or $or$ls180.v:4108$621 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4079$554_Y - connect \B $and$ls180.v:4079$556_Y - connect \Y $or$ls180.v:4079$557_Y + connect \A $or$ls180.v:4108$618_Y + connect \B $and$ls180.v:4108$620_Y + connect \Y $or$ls180.v:4108$621_Y end - attribute \src "ls180.v:4079.32-4079.1159" - cell $or $or$ls180.v:4079$562 + attribute \src "ls180.v:4108.32-4108.1159" + cell $or $or$ls180.v:4108$626 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4079$546_Y - connect \B $and$ls180.v:4079$561_Y - connect \Y $or$ls180.v:4079$562_Y + connect \A $or$ls180.v:4108$610_Y + connect \B $and$ls180.v:4108$625_Y + connect \Y $or$ls180.v:4108$626_Y end - attribute \src "ls180.v:4079.1254-4079.1343" - cell $or $or$ls180.v:4079$567 + attribute \src "ls180.v:4108.1254-4108.1343" + cell $or $or$ls180.v:4108$631 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_locked3 - connect \B $and$ls180.v:4079$566_Y - connect \Y $or$ls180.v:4079$567_Y + connect \B $and$ls180.v:4108$630_Y + connect \Y $or$ls180.v:4108$631_Y end - attribute \src "ls180.v:4079.1253-4079.1418" - cell $or $or$ls180.v:4079$570 + attribute \src "ls180.v:4108.1253-4108.1418" + cell $or $or$ls180.v:4108$634 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4079$567_Y - connect \B $and$ls180.v:4079$569_Y - connect \Y $or$ls180.v:4079$570_Y + connect \A $or$ls180.v:4108$631_Y + connect \B $and$ls180.v:4108$633_Y + connect \Y $or$ls180.v:4108$634_Y end - attribute \src "ls180.v:4079.1252-4079.1493" - cell $or $or$ls180.v:4079$573 + attribute \src "ls180.v:4108.1252-4108.1493" + cell $or $or$ls180.v:4108$637 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4079$570_Y - connect \B $and$ls180.v:4079$572_Y - connect \Y $or$ls180.v:4079$573_Y + connect \A $or$ls180.v:4108$634_Y + connect \B $and$ls180.v:4108$636_Y + connect \Y $or$ls180.v:4108$637_Y end - attribute \src "ls180.v:4079.31-4079.1533" - cell $or $or$ls180.v:4079$578 + attribute \src "ls180.v:4108.31-4108.1533" + cell $or $or$ls180.v:4108$642 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4079$562_Y - connect \B $and$ls180.v:4079$577_Y - connect \Y $or$ls180.v:4079$578_Y + connect \A $or$ls180.v:4108$626_Y + connect \B $and$ls180.v:4108$641_Y + connect \Y $or$ls180.v:4108$642_Y end - attribute \src "ls180.v:4142.10-4142.52" - cell $or $or$ls180.v:4142$587 + attribute \src "ls180.v:4171.10-4171.52" + cell $or $or$ls180.v:4171$651 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259128,10 +260204,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_litedram_wb_ack connect \B \main_converter_skip - connect \Y $or$ls180.v:4142$587_Y + connect \Y $or$ls180.v:4171$651_Y end - attribute \src "ls180.v:4169.35-4169.74" - cell $or $or$ls180.v:4169$597 + attribute \src "ls180.v:4198.35-4198.74" + cell $or $or$ls180.v:4198$661 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259139,10 +260215,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_valid connect \B \main_cmd_consumed - connect \Y $or$ls180.v:4169$597_Y + connect \Y $or$ls180.v:4198$661_Y end - attribute \src "ls180.v:4170.34-4170.73" - cell $or $or$ls180.v:4170$601 + attribute \src "ls180.v:4199.34-4199.73" + cell $or $or$ls180.v:4199$665 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259150,76 +260226,76 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_valid connect \B \main_cmd_consumed - connect \Y $or$ls180.v:4170$601_Y + connect \Y $or$ls180.v:4199$665_Y end - attribute \src "ls180.v:4171.48-4171.130" - cell $or $or$ls180.v:4171$607 + attribute \src "ls180.v:4200.48-4200.130" + cell $or $or$ls180.v:4200$671 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4171$604_Y - connect \B $and$ls180.v:4171$606_Y - connect \Y $or$ls180.v:4171$607_Y + connect \A $and$ls180.v:4200$668_Y + connect \B $and$ls180.v:4200$670_Y + connect \Y $or$ls180.v:4200$671_Y end - attribute \src "ls180.v:4172.24-4172.87" - cell $or $or$ls180.v:4172$610 + attribute \src "ls180.v:4201.24-4201.87" + cell $or $or$ls180.v:4201$674 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4172$609_Y + connect \A $and$ls180.v:4201$673_Y connect \B \main_cmd_consumed - connect \Y $or$ls180.v:4172$610_Y + connect \Y $or$ls180.v:4201$674_Y end - attribute \src "ls180.v:4173.26-4173.95" - cell $or $or$ls180.v:4173$612 + attribute \src "ls180.v:4202.26-4202.95" + cell $or $or$ls180.v:4202$676 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4173$611_Y + connect \A $and$ls180.v:4202$675_Y connect \B \main_wdata_consumed - connect \Y $or$ls180.v:4173$612_Y + connect \Y $or$ls180.v:4202$676_Y end - attribute \src "ls180.v:4203.42-4203.89" - cell $or $or$ls180.v:4203$620 + attribute \src "ls180.v:4232.42-4232.89" + cell $or $or$ls180.v:4232$684 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_rx_clear - connect \B $and$ls180.v:4203$619_Y - connect \Y $or$ls180.v:4203$620_Y + connect \B $and$ls180.v:4232$683_Y + connect \Y $or$ls180.v:4232$684_Y end - attribute \src "ls180.v:4227.25-4227.174" - cell $or $or$ls180.v:4227$630 + attribute \src "ls180.v:4256.25-4256.174" + cell $or $or$ls180.v:4256$694 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4227$628_Y - connect \B $and$ls180.v:4227$629_Y - connect \Y $or$ls180.v:4227$630_Y + connect \A $and$ls180.v:4256$692_Y + connect \B $and$ls180.v:4256$693_Y + connect \Y $or$ls180.v:4256$694_Y end - attribute \src "ls180.v:4242.80-4242.132" - cell $or $or$ls180.v:4242$632 + attribute \src "ls180.v:4271.80-4271.132" + cell $or $or$ls180.v:4271$696 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4242$631_Y + connect \A $not$ls180.v:4271$695_Y connect \B \main_uart_tx_fifo_re - connect \Y $or$ls180.v:4242$632_Y + connect \Y $or$ls180.v:4271$696_Y end - attribute \src "ls180.v:4253.72-4253.135" - cell $or $or$ls180.v:4253$637 + attribute \src "ls180.v:4282.72-4282.135" + cell $or $or$ls180.v:4282$701 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259227,21 +260303,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_syncfifo_writable connect \B \main_uart_tx_fifo_replace - connect \Y $or$ls180.v:4253$637_Y + connect \Y $or$ls180.v:4282$701_Y end - attribute \src "ls180.v:4272.80-4272.132" - cell $or $or$ls180.v:4272$643 + attribute \src "ls180.v:4301.80-4301.132" + cell $or $or$ls180.v:4301$707 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4272$642_Y + connect \A $not$ls180.v:4301$706_Y connect \B \main_uart_rx_fifo_re - connect \Y $or$ls180.v:4272$643_Y + connect \Y $or$ls180.v:4301$707_Y end - attribute \src "ls180.v:4283.72-4283.135" - cell $or $or$ls180.v:4283$648 + attribute \src "ls180.v:4312.72-4312.135" + cell $or $or$ls180.v:4312$712 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259249,10 +260325,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_syncfifo_writable connect \B \main_uart_rx_fifo_replace - connect \Y $or$ls180.v:4283$648_Y + connect \Y $or$ls180.v:4312$712_Y end - attribute \src "ls180.v:4417.36-4417.111" - cell $or $or$ls180.v:4417$669 + attribute \src "ls180.v:4457.36-4457.111" + cell $or $or$ls180.v:4457$735 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259260,43 +260336,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_init_pads_out_payload_clk connect \B \main_sdphy_cmdw_pads_out_payload_clk - connect \Y $or$ls180.v:4417$669_Y + connect \Y $or$ls180.v:4457$735_Y end - attribute \src "ls180.v:4417.35-4417.151" - cell $or $or$ls180.v:4417$670 + attribute \src "ls180.v:4457.35-4457.151" + cell $or $or$ls180.v:4457$736 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4417$669_Y + connect \A $or$ls180.v:4457$735_Y connect \B \main_sdphy_cmdr_pads_out_payload_clk - connect \Y $or$ls180.v:4417$670_Y + connect \Y $or$ls180.v:4457$736_Y end - attribute \src "ls180.v:4417.34-4417.192" - cell $or $or$ls180.v:4417$671 + attribute \src "ls180.v:4457.34-4457.192" + cell $or $or$ls180.v:4457$737 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4417$670_Y + connect \A $or$ls180.v:4457$736_Y connect \B \main_sdphy_dataw_pads_out_payload_clk - connect \Y $or$ls180.v:4417$671_Y + connect \Y $or$ls180.v:4457$737_Y end - attribute \src "ls180.v:4417.33-4417.233" - cell $or $or$ls180.v:4417$672 + attribute \src "ls180.v:4457.33-4457.233" + cell $or $or$ls180.v:4457$738 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4417$671_Y + connect \A $or$ls180.v:4457$737_Y connect \B \main_sdphy_datar_pads_out_payload_clk - connect \Y $or$ls180.v:4417$672_Y + connect \Y $or$ls180.v:4457$738_Y end - attribute \src "ls180.v:4418.39-4418.120" - cell $or $or$ls180.v:4418$673 + attribute \src "ls180.v:4458.39-4458.120" + cell $or $or$ls180.v:4458$739 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259304,43 +260380,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_init_pads_out_payload_cmd_oe connect \B \main_sdphy_cmdw_pads_out_payload_cmd_oe - connect \Y $or$ls180.v:4418$673_Y + connect \Y $or$ls180.v:4458$739_Y end - attribute \src "ls180.v:4418.38-4418.163" - cell $or $or$ls180.v:4418$674 + attribute \src "ls180.v:4458.38-4458.163" + cell $or $or$ls180.v:4458$740 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4418$673_Y + connect \A $or$ls180.v:4458$739_Y connect \B \main_sdphy_cmdr_pads_out_payload_cmd_oe - connect \Y $or$ls180.v:4418$674_Y + connect \Y $or$ls180.v:4458$740_Y end - attribute \src "ls180.v:4418.37-4418.207" - cell $or $or$ls180.v:4418$675 + attribute \src "ls180.v:4458.37-4458.207" + cell $or $or$ls180.v:4458$741 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4418$674_Y + connect \A $or$ls180.v:4458$740_Y connect \B \main_sdphy_dataw_pads_out_payload_cmd_oe - connect \Y $or$ls180.v:4418$675_Y + connect \Y $or$ls180.v:4458$741_Y end - attribute \src "ls180.v:4418.36-4418.251" - cell $or $or$ls180.v:4418$676 + attribute \src "ls180.v:4458.36-4458.251" + cell $or $or$ls180.v:4458$742 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4418$675_Y + connect \A $or$ls180.v:4458$741_Y connect \B \main_sdphy_datar_pads_out_payload_cmd_oe - connect \Y $or$ls180.v:4418$676_Y + connect \Y $or$ls180.v:4458$742_Y end - attribute \src "ls180.v:4419.38-4419.117" - cell $or $or$ls180.v:4419$677 + attribute \src "ls180.v:4459.38-4459.117" + cell $or $or$ls180.v:4459$743 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259348,43 +260424,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_init_pads_out_payload_cmd_o connect \B \main_sdphy_cmdw_pads_out_payload_cmd_o - connect \Y $or$ls180.v:4419$677_Y + connect \Y $or$ls180.v:4459$743_Y end - attribute \src "ls180.v:4419.37-4419.159" - cell $or $or$ls180.v:4419$678 + attribute \src "ls180.v:4459.37-4459.159" + cell $or $or$ls180.v:4459$744 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4419$677_Y + connect \A $or$ls180.v:4459$743_Y connect \B \main_sdphy_cmdr_pads_out_payload_cmd_o - connect \Y $or$ls180.v:4419$678_Y + connect \Y $or$ls180.v:4459$744_Y end - attribute \src "ls180.v:4419.36-4419.202" - cell $or $or$ls180.v:4419$679 + attribute \src "ls180.v:4459.36-4459.202" + cell $or $or$ls180.v:4459$745 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4419$678_Y + connect \A $or$ls180.v:4459$744_Y connect \B \main_sdphy_dataw_pads_out_payload_cmd_o - connect \Y $or$ls180.v:4419$679_Y + connect \Y $or$ls180.v:4459$745_Y end - attribute \src "ls180.v:4419.35-4419.245" - cell $or $or$ls180.v:4419$680 + attribute \src "ls180.v:4459.35-4459.245" + cell $or $or$ls180.v:4459$746 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4419$679_Y + connect \A $or$ls180.v:4459$745_Y connect \B \main_sdphy_datar_pads_out_payload_cmd_o - connect \Y $or$ls180.v:4419$680_Y + connect \Y $or$ls180.v:4459$746_Y end - attribute \src "ls180.v:4420.40-4420.123" - cell $or $or$ls180.v:4420$681 + attribute \src "ls180.v:4460.40-4460.123" + cell $or $or$ls180.v:4460$747 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259392,43 +260468,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_init_pads_out_payload_data_oe connect \B \main_sdphy_cmdw_pads_out_payload_data_oe - connect \Y $or$ls180.v:4420$681_Y + connect \Y $or$ls180.v:4460$747_Y end - attribute \src "ls180.v:4420.39-4420.167" - cell $or $or$ls180.v:4420$682 + attribute \src "ls180.v:4460.39-4460.167" + cell $or $or$ls180.v:4460$748 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4420$681_Y + connect \A $or$ls180.v:4460$747_Y connect \B \main_sdphy_cmdr_pads_out_payload_data_oe - connect \Y $or$ls180.v:4420$682_Y + connect \Y $or$ls180.v:4460$748_Y end - attribute \src "ls180.v:4420.38-4420.212" - cell $or $or$ls180.v:4420$683 + attribute \src "ls180.v:4460.38-4460.212" + cell $or $or$ls180.v:4460$749 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4420$682_Y + connect \A $or$ls180.v:4460$748_Y connect \B \main_sdphy_dataw_pads_out_payload_data_oe - connect \Y $or$ls180.v:4420$683_Y + connect \Y $or$ls180.v:4460$749_Y end - attribute \src "ls180.v:4420.37-4420.257" - cell $or $or$ls180.v:4420$684 + attribute \src "ls180.v:4460.37-4460.257" + cell $or $or$ls180.v:4460$750 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4420$683_Y + connect \A $or$ls180.v:4460$749_Y connect \B \main_sdphy_datar_pads_out_payload_data_oe - connect \Y $or$ls180.v:4420$684_Y + connect \Y $or$ls180.v:4460$750_Y end - attribute \src "ls180.v:4421.39-4421.120" - cell $or $or$ls180.v:4421$685 + attribute \src "ls180.v:4461.39-4461.120" + cell $or $or$ls180.v:4461$751 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -259436,43 +260512,43 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdphy_init_pads_out_payload_data_o connect \B \main_sdphy_cmdw_pads_out_payload_data_o - connect \Y $or$ls180.v:4421$685_Y + connect \Y $or$ls180.v:4461$751_Y end - attribute \src "ls180.v:4421.38-4421.163" - cell $or $or$ls180.v:4421$686 + attribute \src "ls180.v:4461.38-4461.163" + cell $or $or$ls180.v:4461$752 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 - connect \A $or$ls180.v:4421$685_Y + connect \A $or$ls180.v:4461$751_Y connect \B \main_sdphy_cmdr_pads_out_payload_data_o - connect \Y $or$ls180.v:4421$686_Y + connect \Y $or$ls180.v:4461$752_Y end - attribute \src "ls180.v:4421.37-4421.207" - cell $or $or$ls180.v:4421$687 + attribute \src "ls180.v:4461.37-4461.207" + cell $or $or$ls180.v:4461$753 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 - connect \A $or$ls180.v:4421$686_Y + connect \A $or$ls180.v:4461$752_Y connect \B \main_sdphy_dataw_pads_out_payload_data_o - connect \Y $or$ls180.v:4421$687_Y + connect \Y $or$ls180.v:4461$753_Y end - attribute \src "ls180.v:4421.36-4421.251" - cell $or $or$ls180.v:4421$688 + attribute \src "ls180.v:4461.36-4461.251" + cell $or $or$ls180.v:4461$754 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 - connect \A $or$ls180.v:4421$687_Y + connect \A $or$ls180.v:4461$753_Y connect \B \main_sdphy_datar_pads_out_payload_data_o - connect \Y $or$ls180.v:4421$688_Y + connect \Y $or$ls180.v:4461$754_Y end - attribute \src "ls180.v:4442.35-4442.80" - cell $or $or$ls180.v:4442$689 + attribute \src "ls180.v:4482.35-4482.80" + cell $or $or$ls180.v:4482$755 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259480,10 +260556,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_stop connect \B \main_sdphy_datar_stop - connect \Y $or$ls180.v:4442$689_Y + connect \Y $or$ls180.v:4482$755_Y end - attribute \src "ls180.v:4596.91-4596.144" - cell $or $or$ls180.v:4596$703 + attribute \src "ls180.v:4636.91-4636.144" + cell $or $or$ls180.v:4636$769 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259491,76 +260567,76 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_start connect \B \main_sdphy_cmdr_cmdr_run - connect \Y $or$ls180.v:4596$703_Y + connect \Y $or$ls180.v:4636$769_Y end - attribute \src "ls180.v:4613.53-4613.143" - cell $or $or$ls180.v:4613$706 + attribute \src "ls180.v:4653.53-4653.143" + cell $or $or$ls180.v:4653$772 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4613$705_Y + connect \A $not$ls180.v:4653$771_Y connect \B \main_sdphy_cmdr_cmdr_converter_source_ready - connect \Y $or$ls180.v:4613$706_Y + connect \Y $or$ls180.v:4653$772_Y end - attribute \src "ls180.v:4616.47-4616.127" - cell $or $or$ls180.v:4616$709 + attribute \src "ls180.v:4656.47-4656.127" + cell $or $or$ls180.v:4656$775 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4616$708_Y + connect \A $not$ls180.v:4656$774_Y connect \B \main_sdphy_cmdr_cmdr_buf_source_ready - connect \Y $or$ls180.v:4616$709_Y + connect \Y $or$ls180.v:4656$775_Y end - attribute \src "ls180.v:4740.54-4740.146" - cell $or $or$ls180.v:4740$727 + attribute \src "ls180.v:4780.54-4780.146" + cell $or $or$ls180.v:4780$793 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4740$726_Y + connect \A $not$ls180.v:4780$792_Y connect \B \main_sdphy_dataw_crcr_converter_source_ready - connect \Y $or$ls180.v:4740$727_Y + connect \Y $or$ls180.v:4780$793_Y end - attribute \src "ls180.v:4743.48-4743.130" - cell $or $or$ls180.v:4743$730 + attribute \src "ls180.v:4783.48-4783.130" + cell $or $or$ls180.v:4783$796 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4743$729_Y + connect \A $not$ls180.v:4783$795_Y connect \B \main_sdphy_dataw_crcr_buf_source_ready - connect \Y $or$ls180.v:4743$730_Y + connect \Y $or$ls180.v:4783$796_Y end - attribute \src "ls180.v:4874.55-4874.149" - cell $or $or$ls180.v:4874$742 + attribute \src "ls180.v:4914.55-4914.149" + cell $or $or$ls180.v:4914$808 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4874$741_Y + connect \A $not$ls180.v:4914$807_Y connect \B \main_sdphy_datar_datar_converter_source_ready - connect \Y $or$ls180.v:4874$742_Y + connect \Y $or$ls180.v:4914$808_Y end - attribute \src "ls180.v:4877.49-4877.133" - cell $or $or$ls180.v:4877$745 + attribute \src "ls180.v:4917.49-4917.133" + cell $or $or$ls180.v:4917$811 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4877$744_Y + connect \A $not$ls180.v:4917$810_Y connect \B \main_sdphy_datar_datar_buf_source_ready - connect \Y $or$ls180.v:4877$745_Y + connect \Y $or$ls180.v:4917$811_Y end - attribute \src "ls180.v:5506.80-5506.151" - cell $or $or$ls180.v:5506$1040 + attribute \src "ls180.v:5546.80-5546.151" + cell $or $or$ls180.v:5546$1106 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259568,21 +260644,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_fifo_syncfifo_writable connect \B \main_sdblock2mem_fifo_replace - connect \Y $or$ls180.v:5506$1040_Y + connect \Y $or$ls180.v:5546$1106_Y end - attribute \src "ls180.v:5517.49-5517.131" - cell $or $or$ls180.v:5517$1046 + attribute \src "ls180.v:5557.49-5557.131" + cell $or $or$ls180.v:5557$1112 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:5517$1045_Y + connect \A $not$ls180.v:5557$1111_Y connect \B \main_sdblock2mem_converter_source_ready - connect \Y $or$ls180.v:5517$1046_Y + connect \Y $or$ls180.v:5557$1112_Y end - attribute \src "ls180.v:5714.80-5714.151" - cell $or $or$ls180.v:5714$1071 + attribute \src "ls180.v:5766.80-5766.151" + cell $or $or$ls180.v:5766$1137 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259590,10 +260666,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_fifo_syncfifo_writable connect \B \main_sdmem2block_fifo_replace - connect \Y $or$ls180.v:5714$1071_Y + connect \Y $or$ls180.v:5766$1137_Y end - attribute \src "ls180.v:5856.36-5856.94" - cell $or $or$ls180.v:5856$1117 + attribute \src "ls180.v:5908.36-5908.94" + cell $or $or$ls180.v:5908$1183 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259601,76 +260677,76 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_ram_bus_err connect \B \main_interface0_ram_bus_err - connect \Y $or$ls180.v:5856$1117_Y + connect \Y $or$ls180.v:5908$1183_Y end - attribute \src "ls180.v:5856.35-5856.125" - cell $or $or$ls180.v:5856$1118 + attribute \src "ls180.v:5908.35-5908.125" + cell $or $or$ls180.v:5908$1184 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:5856$1117_Y + connect \A $or$ls180.v:5908$1183_Y connect \B \main_interface1_ram_bus_err - connect \Y $or$ls180.v:5856$1118_Y + connect \Y $or$ls180.v:5908$1184_Y end - attribute \src "ls180.v:5856.34-5856.156" - cell $or $or$ls180.v:5856$1119 + attribute \src "ls180.v:5908.34-5908.156" + cell $or $or$ls180.v:5908$1185 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:5856$1118_Y + connect \A $or$ls180.v:5908$1184_Y connect \B \main_interface2_ram_bus_err - connect \Y $or$ls180.v:5856$1119_Y + connect \Y $or$ls180.v:5908$1185_Y end - attribute \src "ls180.v:5856.33-5856.198" - cell $or $or$ls180.v:5856$1120 + attribute \src "ls180.v:5908.33-5908.199" + cell $or $or$ls180.v:5908$1186 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:5856$1119_Y - connect \B \main_libresocsim_libresoc_xics_icp_err - connect \Y $or$ls180.v:5856$1120_Y + connect \A $or$ls180.v:5908$1185_Y + connect \B \main_interface0_converted_interface_err + connect \Y $or$ls180.v:5908$1186_Y end - attribute \src "ls180.v:5856.32-5856.240" - cell $or $or$ls180.v:5856$1121 + attribute \src "ls180.v:5908.32-5908.242" + cell $or $or$ls180.v:5908$1187 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:5856$1120_Y - connect \B \main_libresocsim_libresoc_xics_ics_err - connect \Y $or$ls180.v:5856$1121_Y + connect \A $or$ls180.v:5908$1186_Y + connect \B \main_interface1_converted_interface_err + connect \Y $or$ls180.v:5908$1187_Y end - attribute \src "ls180.v:5856.31-5856.261" - cell $or $or$ls180.v:5856$1122 + attribute \src "ls180.v:5908.31-5908.288" + cell $or $or$ls180.v:5908$1188 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:5856$1121_Y - connect \B \main_wb_sdram_err - connect \Y $or$ls180.v:5856$1122_Y + connect \A $or$ls180.v:5908$1187_Y + connect \B \main_socbushandler_converted_interface_err + connect \Y $or$ls180.v:5908$1188_Y end - attribute \src "ls180.v:5856.30-5856.297" - cell $or $or$ls180.v:5856$1123 + attribute \src "ls180.v:5908.30-5908.335" + cell $or $or$ls180.v:5908$1189 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:5856$1122_Y - connect \B \builder_libresocsim_wishbone_err - connect \Y $or$ls180.v:5856$1123_Y + connect \A $or$ls180.v:5908$1188_Y + connect \B \builder_libresocsim_converted_interface_err + connect \Y $or$ls180.v:5908$1189_Y end - attribute \src "ls180.v:5862.31-5862.89" - cell $or $or$ls180.v:5862$1128 + attribute \src "ls180.v:5914.31-5914.89" + cell $or $or$ls180.v:5914$1194 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259678,153 +260754,153 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_ram_bus_ack connect \B \main_interface0_ram_bus_ack - connect \Y $or$ls180.v:5862$1128_Y + connect \Y $or$ls180.v:5914$1194_Y end - attribute \src "ls180.v:5862.30-5862.120" - cell $or $or$ls180.v:5862$1129 + attribute \src "ls180.v:5914.30-5914.120" + cell $or $or$ls180.v:5914$1195 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:5862$1128_Y + connect \A $or$ls180.v:5914$1194_Y connect \B \main_interface1_ram_bus_ack - connect \Y $or$ls180.v:5862$1129_Y + connect \Y $or$ls180.v:5914$1195_Y end - attribute \src "ls180.v:5862.29-5862.151" - cell $or $or$ls180.v:5862$1130 + attribute \src "ls180.v:5914.29-5914.151" + cell $or $or$ls180.v:5914$1196 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:5862$1129_Y + connect \A $or$ls180.v:5914$1195_Y connect \B \main_interface2_ram_bus_ack - connect \Y $or$ls180.v:5862$1130_Y + connect \Y $or$ls180.v:5914$1196_Y end - attribute \src "ls180.v:5862.28-5862.193" - cell $or $or$ls180.v:5862$1131 + attribute \src "ls180.v:5914.28-5914.194" + cell $or $or$ls180.v:5914$1197 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:5862$1130_Y - connect \B \main_libresocsim_libresoc_xics_icp_ack - connect \Y $or$ls180.v:5862$1131_Y + connect \A $or$ls180.v:5914$1196_Y + connect \B \main_interface0_converted_interface_ack + connect \Y $or$ls180.v:5914$1197_Y end - attribute \src "ls180.v:5862.27-5862.235" - cell $or $or$ls180.v:5862$1132 + attribute \src "ls180.v:5914.27-5914.237" + cell $or $or$ls180.v:5914$1198 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:5862$1131_Y - connect \B \main_libresocsim_libresoc_xics_ics_ack - connect \Y $or$ls180.v:5862$1132_Y + connect \A $or$ls180.v:5914$1197_Y + connect \B \main_interface1_converted_interface_ack + connect \Y $or$ls180.v:5914$1198_Y end - attribute \src "ls180.v:5862.26-5862.256" - cell $or $or$ls180.v:5862$1133 + attribute \src "ls180.v:5914.26-5914.283" + cell $or $or$ls180.v:5914$1199 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:5862$1132_Y - connect \B \main_wb_sdram_ack - connect \Y $or$ls180.v:5862$1133_Y + connect \A $or$ls180.v:5914$1198_Y + connect \B \main_socbushandler_converted_interface_ack + connect \Y $or$ls180.v:5914$1199_Y end - attribute \src "ls180.v:5862.25-5862.292" - cell $or $or$ls180.v:5862$1134 + attribute \src "ls180.v:5914.25-5914.330" + cell $or $or$ls180.v:5914$1200 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:5862$1133_Y - connect \B \builder_libresocsim_wishbone_ack - connect \Y $or$ls180.v:5862$1134_Y + connect \A $or$ls180.v:5914$1199_Y + connect \B \builder_libresocsim_converted_interface_ack + connect \Y $or$ls180.v:5914$1200_Y end - attribute \src "ls180.v:5863.33-5863.161" - cell $or $or$ls180.v:5863$1137 + attribute \src "ls180.v:5915.33-5915.161" + cell $or $or$ls180.v:5915$1203 parameter \A_SIGNED 0 - parameter \A_WIDTH 32 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A $and$ls180.v:5863$1135_Y - connect \B $and$ls180.v:5863$1136_Y - connect \Y $or$ls180.v:5863$1137_Y + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $and$ls180.v:5915$1201_Y + connect \B $and$ls180.v:5915$1202_Y + connect \Y $or$ls180.v:5915$1203_Y end - attribute \src "ls180.v:5863.32-5863.227" - cell $or $or$ls180.v:5863$1139 + attribute \src "ls180.v:5915.32-5915.227" + cell $or $or$ls180.v:5915$1205 parameter \A_SIGNED 0 - parameter \A_WIDTH 32 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A $or$ls180.v:5863$1137_Y - connect \B $and$ls180.v:5863$1138_Y - connect \Y $or$ls180.v:5863$1139_Y + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $or$ls180.v:5915$1203_Y + connect \B $and$ls180.v:5915$1204_Y + connect \Y $or$ls180.v:5915$1205_Y end - attribute \src "ls180.v:5863.31-5863.293" - cell $or $or$ls180.v:5863$1141 + attribute \src "ls180.v:5915.31-5915.293" + cell $or $or$ls180.v:5915$1207 parameter \A_SIGNED 0 - parameter \A_WIDTH 32 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A $or$ls180.v:5863$1139_Y - connect \B $and$ls180.v:5863$1140_Y - connect \Y $or$ls180.v:5863$1141_Y + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $or$ls180.v:5915$1205_Y + connect \B $and$ls180.v:5915$1206_Y + connect \Y $or$ls180.v:5915$1207_Y end - attribute \src "ls180.v:5863.30-5863.370" - cell $or $or$ls180.v:5863$1143 + attribute \src "ls180.v:5915.30-5915.371" + cell $or $or$ls180.v:5915$1209 parameter \A_SIGNED 0 - parameter \A_WIDTH 32 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A $or$ls180.v:5863$1141_Y - connect \B $and$ls180.v:5863$1142_Y - connect \Y $or$ls180.v:5863$1143_Y + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $or$ls180.v:5915$1207_Y + connect \B $and$ls180.v:5915$1208_Y + connect \Y $or$ls180.v:5915$1209_Y end - attribute \src "ls180.v:5863.29-5863.447" - cell $or $or$ls180.v:5863$1145 + attribute \src "ls180.v:5915.29-5915.449" + cell $or $or$ls180.v:5915$1211 parameter \A_SIGNED 0 - parameter \A_WIDTH 32 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A $or$ls180.v:5863$1143_Y - connect \B $and$ls180.v:5863$1144_Y - connect \Y $or$ls180.v:5863$1145_Y + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $or$ls180.v:5915$1209_Y + connect \B $and$ls180.v:5915$1210_Y + connect \Y $or$ls180.v:5915$1211_Y end - attribute \src "ls180.v:5863.28-5863.503" - cell $or $or$ls180.v:5863$1147 + attribute \src "ls180.v:5915.28-5915.530" + cell $or $or$ls180.v:5915$1213 parameter \A_SIGNED 0 - parameter \A_WIDTH 32 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A $or$ls180.v:5863$1145_Y - connect \B $and$ls180.v:5863$1146_Y - connect \Y $or$ls180.v:5863$1147_Y + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $or$ls180.v:5915$1211_Y + connect \B $and$ls180.v:5915$1212_Y + connect \Y $or$ls180.v:5915$1213_Y end - attribute \src "ls180.v:5863.27-5863.574" - cell $or $or$ls180.v:5863$1149 + attribute \src "ls180.v:5915.27-5915.612" + cell $or $or$ls180.v:5915$1215 parameter \A_SIGNED 0 - parameter \A_WIDTH 32 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A $or$ls180.v:5863$1147_Y - connect \B $and$ls180.v:5863$1148_Y - connect \Y $or$ls180.v:5863$1149_Y + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $or$ls180.v:5915$1213_Y + connect \B $and$ls180.v:5915$1214_Y + connect \Y $or$ls180.v:5915$1215_Y end - attribute \src "ls180.v:6617.55-6617.124" - cell $or $or$ls180.v:6617$2295 + attribute \src "ls180.v:6669.55-6669.124" + cell $or $or$ls180.v:6669$2361 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -259832,285 +260908,285 @@ module \ls180 parameter \Y_WIDTH 8 connect \A \builder_interface0_bank_bus_dat_r connect \B \builder_interface1_bank_bus_dat_r - connect \Y $or$ls180.v:6617$2295_Y + connect \Y $or$ls180.v:6669$2361_Y end - attribute \src "ls180.v:6617.54-6617.161" - cell $or $or$ls180.v:6617$2296 + attribute \src "ls180.v:6669.54-6669.161" + cell $or $or$ls180.v:6669$2362 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6617$2295_Y + connect \A $or$ls180.v:6669$2361_Y connect \B \builder_interface2_bank_bus_dat_r - connect \Y $or$ls180.v:6617$2296_Y + connect \Y $or$ls180.v:6669$2362_Y end - attribute \src "ls180.v:6617.53-6617.198" - cell $or $or$ls180.v:6617$2297 + attribute \src "ls180.v:6669.53-6669.198" + cell $or $or$ls180.v:6669$2363 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6617$2296_Y + connect \A $or$ls180.v:6669$2362_Y connect \B \builder_interface3_bank_bus_dat_r - connect \Y $or$ls180.v:6617$2297_Y + connect \Y $or$ls180.v:6669$2363_Y end - attribute \src "ls180.v:6617.52-6617.235" - cell $or $or$ls180.v:6617$2298 + attribute \src "ls180.v:6669.52-6669.235" + cell $or $or$ls180.v:6669$2364 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6617$2297_Y + connect \A $or$ls180.v:6669$2363_Y connect \B \builder_interface4_bank_bus_dat_r - connect \Y $or$ls180.v:6617$2298_Y + connect \Y $or$ls180.v:6669$2364_Y end - attribute \src "ls180.v:6617.51-6617.272" - cell $or $or$ls180.v:6617$2299 + attribute \src "ls180.v:6669.51-6669.272" + cell $or $or$ls180.v:6669$2365 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6617$2298_Y + connect \A $or$ls180.v:6669$2364_Y connect \B \builder_interface5_bank_bus_dat_r - connect \Y $or$ls180.v:6617$2299_Y + connect \Y $or$ls180.v:6669$2365_Y end - attribute \src "ls180.v:6617.50-6617.309" - cell $or $or$ls180.v:6617$2300 + attribute \src "ls180.v:6669.50-6669.309" + cell $or $or$ls180.v:6669$2366 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6617$2299_Y + connect \A $or$ls180.v:6669$2365_Y connect \B \builder_interface6_bank_bus_dat_r - connect \Y $or$ls180.v:6617$2300_Y + connect \Y $or$ls180.v:6669$2366_Y end - attribute \src "ls180.v:6617.49-6617.346" - cell $or $or$ls180.v:6617$2301 + attribute \src "ls180.v:6669.49-6669.346" + cell $or $or$ls180.v:6669$2367 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6617$2300_Y + connect \A $or$ls180.v:6669$2366_Y connect \B \builder_interface7_bank_bus_dat_r - connect \Y $or$ls180.v:6617$2301_Y + connect \Y $or$ls180.v:6669$2367_Y end - attribute \src "ls180.v:6617.48-6617.383" - cell $or $or$ls180.v:6617$2302 + attribute \src "ls180.v:6669.48-6669.383" + cell $or $or$ls180.v:6669$2368 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6617$2301_Y + connect \A $or$ls180.v:6669$2367_Y connect \B \builder_interface8_bank_bus_dat_r - connect \Y $or$ls180.v:6617$2302_Y + connect \Y $or$ls180.v:6669$2368_Y end - attribute \src "ls180.v:6617.47-6617.420" - cell $or $or$ls180.v:6617$2303 + attribute \src "ls180.v:6669.47-6669.420" + cell $or $or$ls180.v:6669$2369 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6617$2302_Y + connect \A $or$ls180.v:6669$2368_Y connect \B \builder_interface9_bank_bus_dat_r - connect \Y $or$ls180.v:6617$2303_Y + connect \Y $or$ls180.v:6669$2369_Y end - attribute \src "ls180.v:6617.46-6617.458" - cell $or $or$ls180.v:6617$2304 + attribute \src "ls180.v:6669.46-6669.458" + cell $or $or$ls180.v:6669$2370 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6617$2303_Y + connect \A $or$ls180.v:6669$2369_Y connect \B \builder_interface10_bank_bus_dat_r - connect \Y $or$ls180.v:6617$2304_Y + connect \Y $or$ls180.v:6669$2370_Y end - attribute \src "ls180.v:6617.45-6617.496" - cell $or $or$ls180.v:6617$2305 + attribute \src "ls180.v:6669.45-6669.496" + cell $or $or$ls180.v:6669$2371 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6617$2304_Y + connect \A $or$ls180.v:6669$2370_Y connect \B \builder_interface11_bank_bus_dat_r - connect \Y $or$ls180.v:6617$2305_Y + connect \Y $or$ls180.v:6669$2371_Y end - attribute \src "ls180.v:6617.44-6617.534" - cell $or $or$ls180.v:6617$2306 + attribute \src "ls180.v:6669.44-6669.534" + cell $or $or$ls180.v:6669$2372 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6617$2305_Y + connect \A $or$ls180.v:6669$2371_Y connect \B \builder_interface12_bank_bus_dat_r - connect \Y $or$ls180.v:6617$2306_Y + connect \Y $or$ls180.v:6669$2372_Y end - attribute \src "ls180.v:6617.43-6617.572" - cell $or $or$ls180.v:6617$2307 + attribute \src "ls180.v:6669.43-6669.572" + cell $or $or$ls180.v:6669$2373 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6617$2306_Y + connect \A $or$ls180.v:6669$2372_Y connect \B \builder_interface13_bank_bus_dat_r - connect \Y $or$ls180.v:6617$2307_Y + connect \Y $or$ls180.v:6669$2373_Y end - attribute \src "ls180.v:6617.42-6617.610" - cell $or $or$ls180.v:6617$2308 + attribute \src "ls180.v:6669.42-6669.610" + cell $or $or$ls180.v:6669$2374 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6617$2307_Y + connect \A $or$ls180.v:6669$2373_Y connect \B \builder_interface14_bank_bus_dat_r - connect \Y $or$ls180.v:6617$2308_Y + connect \Y $or$ls180.v:6669$2374_Y end - attribute \src "ls180.v:6944.90-6944.179" - cell $or $or$ls180.v:6944$2333 + attribute \src "ls180.v:6996.90-6996.179" + cell $or $or$ls180.v:6996$2399 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_locked0 - connect \B $and$ls180.v:6944$2332_Y - connect \Y $or$ls180.v:6944$2333_Y + connect \B $and$ls180.v:6996$2398_Y + connect \Y $or$ls180.v:6996$2399_Y end - attribute \src "ls180.v:6944.89-6944.254" - cell $or $or$ls180.v:6944$2336 + attribute \src "ls180.v:6996.89-6996.254" + cell $or $or$ls180.v:6996$2402 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6944$2333_Y - connect \B $and$ls180.v:6944$2335_Y - connect \Y $or$ls180.v:6944$2336_Y + connect \A $or$ls180.v:6996$2399_Y + connect \B $and$ls180.v:6996$2401_Y + connect \Y $or$ls180.v:6996$2402_Y end - attribute \src "ls180.v:6944.88-6944.329" - cell $or $or$ls180.v:6944$2339 + attribute \src "ls180.v:6996.88-6996.329" + cell $or $or$ls180.v:6996$2405 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6944$2336_Y - connect \B $and$ls180.v:6944$2338_Y - connect \Y $or$ls180.v:6944$2339_Y + connect \A $or$ls180.v:6996$2402_Y + connect \B $and$ls180.v:6996$2404_Y + connect \Y $or$ls180.v:6996$2405_Y end - attribute \src "ls180.v:6968.90-6968.179" - cell $or $or$ls180.v:6968$2349 + attribute \src "ls180.v:7020.90-7020.179" + cell $or $or$ls180.v:7020$2415 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_locked1 - connect \B $and$ls180.v:6968$2348_Y - connect \Y $or$ls180.v:6968$2349_Y + connect \B $and$ls180.v:7020$2414_Y + connect \Y $or$ls180.v:7020$2415_Y end - attribute \src "ls180.v:6968.89-6968.254" - cell $or $or$ls180.v:6968$2352 + attribute \src "ls180.v:7020.89-7020.254" + cell $or $or$ls180.v:7020$2418 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6968$2349_Y - connect \B $and$ls180.v:6968$2351_Y - connect \Y $or$ls180.v:6968$2352_Y + connect \A $or$ls180.v:7020$2415_Y + connect \B $and$ls180.v:7020$2417_Y + connect \Y $or$ls180.v:7020$2418_Y end - attribute \src "ls180.v:6968.88-6968.329" - cell $or $or$ls180.v:6968$2355 + attribute \src "ls180.v:7020.88-7020.329" + cell $or $or$ls180.v:7020$2421 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6968$2352_Y - connect \B $and$ls180.v:6968$2354_Y - connect \Y $or$ls180.v:6968$2355_Y + connect \A $or$ls180.v:7020$2418_Y + connect \B $and$ls180.v:7020$2420_Y + connect \Y $or$ls180.v:7020$2421_Y end - attribute \src "ls180.v:6992.90-6992.179" - cell $or $or$ls180.v:6992$2365 + attribute \src "ls180.v:7044.90-7044.179" + cell $or $or$ls180.v:7044$2431 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_locked2 - connect \B $and$ls180.v:6992$2364_Y - connect \Y $or$ls180.v:6992$2365_Y + connect \B $and$ls180.v:7044$2430_Y + connect \Y $or$ls180.v:7044$2431_Y end - attribute \src "ls180.v:6992.89-6992.254" - cell $or $or$ls180.v:6992$2368 + attribute \src "ls180.v:7044.89-7044.254" + cell $or $or$ls180.v:7044$2434 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6992$2365_Y - connect \B $and$ls180.v:6992$2367_Y - connect \Y $or$ls180.v:6992$2368_Y + connect \A $or$ls180.v:7044$2431_Y + connect \B $and$ls180.v:7044$2433_Y + connect \Y $or$ls180.v:7044$2434_Y end - attribute \src "ls180.v:6992.88-6992.329" - cell $or $or$ls180.v:6992$2371 + attribute \src "ls180.v:7044.88-7044.329" + cell $or $or$ls180.v:7044$2437 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6992$2368_Y - connect \B $and$ls180.v:6992$2370_Y - connect \Y $or$ls180.v:6992$2371_Y + connect \A $or$ls180.v:7044$2434_Y + connect \B $and$ls180.v:7044$2436_Y + connect \Y $or$ls180.v:7044$2437_Y end - attribute \src "ls180.v:7016.90-7016.179" - cell $or $or$ls180.v:7016$2381 + attribute \src "ls180.v:7068.90-7068.179" + cell $or $or$ls180.v:7068$2447 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_locked3 - connect \B $and$ls180.v:7016$2380_Y - connect \Y $or$ls180.v:7016$2381_Y + connect \B $and$ls180.v:7068$2446_Y + connect \Y $or$ls180.v:7068$2447_Y end - attribute \src "ls180.v:7016.89-7016.254" - cell $or $or$ls180.v:7016$2384 + attribute \src "ls180.v:7068.89-7068.254" + cell $or $or$ls180.v:7068$2450 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7016$2381_Y - connect \B $and$ls180.v:7016$2383_Y - connect \Y $or$ls180.v:7016$2384_Y + connect \A $or$ls180.v:7068$2447_Y + connect \B $and$ls180.v:7068$2449_Y + connect \Y $or$ls180.v:7068$2450_Y end - attribute \src "ls180.v:7016.88-7016.329" - cell $or $or$ls180.v:7016$2387 + attribute \src "ls180.v:7068.88-7068.329" + cell $or $or$ls180.v:7068$2453 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7016$2384_Y - connect \B $and$ls180.v:7016$2386_Y - connect \Y $or$ls180.v:7016$2387_Y + connect \A $or$ls180.v:7068$2450_Y + connect \B $and$ls180.v:7068$2452_Y + connect \Y $or$ls180.v:7068$2453_Y end - attribute \src "ls180.v:7530.20-7530.71" - cell $or $or$ls180.v:7530$2444 + attribute \src "ls180.v:7585.20-7585.71" + cell $or $or$ls180.v:7585$2511 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260118,10 +261194,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [0] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7530$2444_Y + connect \Y $or$ls180.v:7585$2511_Y end - attribute \src "ls180.v:7531.20-7531.71" - cell $or $or$ls180.v:7531$2445 + attribute \src "ls180.v:7586.20-7586.71" + cell $or $or$ls180.v:7586$2512 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260129,10 +261205,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [1] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7531$2445_Y + connect \Y $or$ls180.v:7586$2512_Y end - attribute \src "ls180.v:7532.20-7532.71" - cell $or $or$ls180.v:7532$2446 + attribute \src "ls180.v:7587.20-7587.71" + cell $or $or$ls180.v:7587$2513 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260140,10 +261216,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [2] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7532$2446_Y + connect \Y $or$ls180.v:7587$2513_Y end - attribute \src "ls180.v:7533.20-7533.71" - cell $or $or$ls180.v:7533$2447 + attribute \src "ls180.v:7588.20-7588.71" + cell $or $or$ls180.v:7588$2514 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260151,10 +261227,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [3] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7533$2447_Y + connect \Y $or$ls180.v:7588$2514_Y end - attribute \src "ls180.v:7534.20-7534.71" - cell $or $or$ls180.v:7534$2448 + attribute \src "ls180.v:7589.20-7589.71" + cell $or $or$ls180.v:7589$2515 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260162,10 +261238,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [4] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7534$2448_Y + connect \Y $or$ls180.v:7589$2515_Y end - attribute \src "ls180.v:7535.20-7535.71" - cell $or $or$ls180.v:7535$2449 + attribute \src "ls180.v:7590.20-7590.71" + cell $or $or$ls180.v:7590$2516 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260173,10 +261249,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [5] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7535$2449_Y + connect \Y $or$ls180.v:7590$2516_Y end - attribute \src "ls180.v:7536.20-7536.71" - cell $or $or$ls180.v:7536$2450 + attribute \src "ls180.v:7591.20-7591.71" + cell $or $or$ls180.v:7591$2517 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260184,10 +261260,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [6] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7536$2450_Y + connect \Y $or$ls180.v:7591$2517_Y end - attribute \src "ls180.v:7537.20-7537.71" - cell $or $or$ls180.v:7537$2451 + attribute \src "ls180.v:7592.20-7592.71" + cell $or $or$ls180.v:7592$2518 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260195,10 +261271,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [7] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7537$2451_Y + connect \Y $or$ls180.v:7592$2518_Y end - attribute \src "ls180.v:7538.20-7538.71" - cell $or $or$ls180.v:7538$2452 + attribute \src "ls180.v:7593.20-7593.71" + cell $or $or$ls180.v:7593$2519 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260206,10 +261282,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [8] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7538$2452_Y + connect \Y $or$ls180.v:7593$2519_Y end - attribute \src "ls180.v:7539.20-7539.71" - cell $or $or$ls180.v:7539$2453 + attribute \src "ls180.v:7594.20-7594.71" + cell $or $or$ls180.v:7594$2520 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260217,10 +261293,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [9] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7539$2453_Y + connect \Y $or$ls180.v:7594$2520_Y end - attribute \src "ls180.v:7540.21-7540.73" - cell $or $or$ls180.v:7540$2454 + attribute \src "ls180.v:7595.21-7595.73" + cell $or $or$ls180.v:7595$2521 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260228,10 +261304,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [10] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7540$2454_Y + connect \Y $or$ls180.v:7595$2521_Y end - attribute \src "ls180.v:7541.21-7541.73" - cell $or $or$ls180.v:7541$2455 + attribute \src "ls180.v:7596.21-7596.73" + cell $or $or$ls180.v:7596$2522 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260239,10 +261315,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [11] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7541$2455_Y + connect \Y $or$ls180.v:7596$2522_Y end - attribute \src "ls180.v:7542.21-7542.73" - cell $or $or$ls180.v:7542$2456 + attribute \src "ls180.v:7597.21-7597.73" + cell $or $or$ls180.v:7597$2523 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260250,10 +261326,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [12] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7542$2456_Y + connect \Y $or$ls180.v:7597$2523_Y end - attribute \src "ls180.v:7543.21-7543.73" - cell $or $or$ls180.v:7543$2457 + attribute \src "ls180.v:7598.21-7598.73" + cell $or $or$ls180.v:7598$2524 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260261,10 +261337,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [13] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7543$2457_Y + connect \Y $or$ls180.v:7598$2524_Y end - attribute \src "ls180.v:7544.21-7544.73" - cell $or $or$ls180.v:7544$2458 + attribute \src "ls180.v:7599.21-7599.73" + cell $or $or$ls180.v:7599$2525 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260272,10 +261348,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [14] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7544$2458_Y + connect \Y $or$ls180.v:7599$2525_Y end - attribute \src "ls180.v:7545.21-7545.73" - cell $or $or$ls180.v:7545$2459 + attribute \src "ls180.v:7600.21-7600.73" + cell $or $or$ls180.v:7600$2526 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260283,10 +261359,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [15] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7545$2459_Y + connect \Y $or$ls180.v:7600$2526_Y end - attribute \src "ls180.v:7546.21-7546.73" - cell $or $or$ls180.v:7546$2460 + attribute \src "ls180.v:7601.21-7601.73" + cell $or $or$ls180.v:7601$2527 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260294,10 +261370,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [16] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7546$2460_Y + connect \Y $or$ls180.v:7601$2527_Y end - attribute \src "ls180.v:7547.21-7547.73" - cell $or $or$ls180.v:7547$2461 + attribute \src "ls180.v:7602.21-7602.73" + cell $or $or$ls180.v:7602$2528 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260305,10 +261381,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [17] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7547$2461_Y + connect \Y $or$ls180.v:7602$2528_Y end - attribute \src "ls180.v:7548.21-7548.73" - cell $or $or$ls180.v:7548$2462 + attribute \src "ls180.v:7603.21-7603.73" + cell $or $or$ls180.v:7603$2529 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260316,10 +261392,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [18] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7548$2462_Y + connect \Y $or$ls180.v:7603$2529_Y end - attribute \src "ls180.v:7549.21-7549.73" - cell $or $or$ls180.v:7549$2463 + attribute \src "ls180.v:7604.21-7604.73" + cell $or $or$ls180.v:7604$2530 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260327,10 +261403,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [19] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7549$2463_Y + connect \Y $or$ls180.v:7604$2530_Y end - attribute \src "ls180.v:7550.21-7550.73" - cell $or $or$ls180.v:7550$2464 + attribute \src "ls180.v:7605.21-7605.73" + cell $or $or$ls180.v:7605$2531 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260338,10 +261414,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [20] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7550$2464_Y + connect \Y $or$ls180.v:7605$2531_Y end - attribute \src "ls180.v:7551.21-7551.73" - cell $or $or$ls180.v:7551$2465 + attribute \src "ls180.v:7606.21-7606.73" + cell $or $or$ls180.v:7606$2532 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260349,10 +261425,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [21] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7551$2465_Y + connect \Y $or$ls180.v:7606$2532_Y end - attribute \src "ls180.v:7552.21-7552.73" - cell $or $or$ls180.v:7552$2466 + attribute \src "ls180.v:7607.21-7607.73" + cell $or $or$ls180.v:7607$2533 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260360,10 +261436,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [22] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7552$2466_Y + connect \Y $or$ls180.v:7607$2533_Y end - attribute \src "ls180.v:7553.21-7553.73" - cell $or $or$ls180.v:7553$2467 + attribute \src "ls180.v:7608.21-7608.73" + cell $or $or$ls180.v:7608$2534 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260371,175 +261447,175 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [23] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7553$2467_Y + connect \Y $or$ls180.v:7608$2534_Y end - attribute \src "ls180.v:7554.7-7554.93" - cell $or $or$ls180.v:7554$2468 + attribute \src "ls180.v:7609.7-7609.68" + cell $or $or$ls180.v:7609$2535 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_interface0_converted_interface_ack - connect \B \main_libresocsim_converter0_skip - connect \Y $or$ls180.v:7554$2468_Y + connect \A \main_libresocsim_libresoc_xics_icp_ack + connect \B \main_converter0_skip + connect \Y $or$ls180.v:7609$2535_Y end - attribute \src "ls180.v:7565.7-7565.93" - cell $or $or$ls180.v:7565$2469 + attribute \src "ls180.v:7620.7-7620.68" + cell $or $or$ls180.v:7620$2536 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_interface1_converted_interface_ack - connect \B \main_libresocsim_converter1_skip - connect \Y $or$ls180.v:7565$2469_Y + connect \A \main_libresocsim_libresoc_xics_ics_ack + connect \B \main_converter1_skip + connect \Y $or$ls180.v:7620$2536_Y end - attribute \src "ls180.v:7576.7-7576.93" - cell $or $or$ls180.v:7576$2470 + attribute \src "ls180.v:7631.7-7631.50" + cell $or $or$ls180.v:7631$2537 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_interface2_converted_interface_ack - connect \B \main_libresocsim_converter2_skip - connect \Y $or$ls180.v:7576$2470_Y + connect \A \main_wb_sdram_ack + connect \B \main_socbushandler_skip + connect \Y $or$ls180.v:7631$2537_Y end - attribute \src "ls180.v:7717.7-7717.107" - cell $or $or$ls180.v:7717$2515 + attribute \src "ls180.v:7772.7-7772.107" + cell $or $or$ls180.v:7772$2582 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7717$2514_Y + connect \A $not$ls180.v:7772$2581_Y connect \B \main_sdram_bankmachine0_cmd_buffer_source_ready - connect \Y $or$ls180.v:7717$2515_Y + connect \Y $or$ls180.v:7772$2582_Y end - attribute \src "ls180.v:7763.7-7763.107" - cell $or $or$ls180.v:7763$2531 + attribute \src "ls180.v:7818.7-7818.107" + cell $or $or$ls180.v:7818$2598 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7763$2530_Y + connect \A $not$ls180.v:7818$2597_Y connect \B \main_sdram_bankmachine1_cmd_buffer_source_ready - connect \Y $or$ls180.v:7763$2531_Y + connect \Y $or$ls180.v:7818$2598_Y end - attribute \src "ls180.v:7809.7-7809.107" - cell $or $or$ls180.v:7809$2547 + attribute \src "ls180.v:7864.7-7864.107" + cell $or $or$ls180.v:7864$2614 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7809$2546_Y + connect \A $not$ls180.v:7864$2613_Y connect \B \main_sdram_bankmachine2_cmd_buffer_source_ready - connect \Y $or$ls180.v:7809$2547_Y + connect \Y $or$ls180.v:7864$2614_Y end - attribute \src "ls180.v:7855.7-7855.107" - cell $or $or$ls180.v:7855$2563 + attribute \src "ls180.v:7910.7-7910.107" + cell $or $or$ls180.v:7910$2630 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7855$2562_Y + connect \A $not$ls180.v:7910$2629_Y connect \B \main_sdram_bankmachine3_cmd_buffer_source_ready - connect \Y $or$ls180.v:7855$2563_Y + connect \Y $or$ls180.v:7910$2630_Y end - attribute \src "ls180.v:8043.40-8043.125" - cell $or $or$ls180.v:8043$2584 + attribute \src "ls180.v:8098.40-8098.125" + cell $or $or$ls180.v:8098$2651 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A 1'0 - connect \B $and$ls180.v:8043$2583_Y - connect \Y $or$ls180.v:8043$2584_Y + connect \B $and$ls180.v:8098$2650_Y + connect \Y $or$ls180.v:8098$2651_Y end - attribute \src "ls180.v:8043.39-8043.207" - cell $or $or$ls180.v:8043$2587 + attribute \src "ls180.v:8098.39-8098.207" + cell $or $or$ls180.v:8098$2654 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:8043$2584_Y - connect \B $and$ls180.v:8043$2586_Y - connect \Y $or$ls180.v:8043$2587_Y + connect \A $or$ls180.v:8098$2651_Y + connect \B $and$ls180.v:8098$2653_Y + connect \Y $or$ls180.v:8098$2654_Y end - attribute \src "ls180.v:8043.38-8043.289" - cell $or $or$ls180.v:8043$2590 + attribute \src "ls180.v:8098.38-8098.289" + cell $or $or$ls180.v:8098$2657 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:8043$2587_Y - connect \B $and$ls180.v:8043$2589_Y - connect \Y $or$ls180.v:8043$2590_Y + connect \A $or$ls180.v:8098$2654_Y + connect \B $and$ls180.v:8098$2656_Y + connect \Y $or$ls180.v:8098$2657_Y end - attribute \src "ls180.v:8043.37-8043.371" - cell $or $or$ls180.v:8043$2593 + attribute \src "ls180.v:8098.37-8098.371" + cell $or $or$ls180.v:8098$2660 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:8043$2590_Y - connect \B $and$ls180.v:8043$2592_Y - connect \Y $or$ls180.v:8043$2593_Y + connect \A $or$ls180.v:8098$2657_Y + connect \B $and$ls180.v:8098$2659_Y + connect \Y $or$ls180.v:8098$2660_Y end - attribute \src "ls180.v:8044.41-8044.126" - cell $or $or$ls180.v:8044$2596 + attribute \src "ls180.v:8099.41-8099.126" + cell $or $or$ls180.v:8099$2663 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A 1'0 - connect \B $and$ls180.v:8044$2595_Y - connect \Y $or$ls180.v:8044$2596_Y + connect \B $and$ls180.v:8099$2662_Y + connect \Y $or$ls180.v:8099$2663_Y end - attribute \src "ls180.v:8044.40-8044.208" - cell $or $or$ls180.v:8044$2599 + attribute \src "ls180.v:8099.40-8099.208" + cell $or $or$ls180.v:8099$2666 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:8044$2596_Y - connect \B $and$ls180.v:8044$2598_Y - connect \Y $or$ls180.v:8044$2599_Y + connect \A $or$ls180.v:8099$2663_Y + connect \B $and$ls180.v:8099$2665_Y + connect \Y $or$ls180.v:8099$2666_Y end - attribute \src "ls180.v:8044.39-8044.290" - cell $or $or$ls180.v:8044$2602 + attribute \src "ls180.v:8099.39-8099.290" + cell $or $or$ls180.v:8099$2669 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:8044$2599_Y - connect \B $and$ls180.v:8044$2601_Y - connect \Y $or$ls180.v:8044$2602_Y + connect \A $or$ls180.v:8099$2666_Y + connect \B $and$ls180.v:8099$2668_Y + connect \Y $or$ls180.v:8099$2669_Y end - attribute \src "ls180.v:8044.38-8044.372" - cell $or $or$ls180.v:8044$2605 + attribute \src "ls180.v:8099.38-8099.372" + cell $or $or$ls180.v:8099$2672 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:8044$2602_Y - connect \B $and$ls180.v:8044$2604_Y - connect \Y $or$ls180.v:8044$2605_Y + connect \A $or$ls180.v:8099$2669_Y + connect \B $and$ls180.v:8099$2671_Y + connect \Y $or$ls180.v:8099$2672_Y end - attribute \src "ls180.v:8048.7-8048.49" - cell $or $or$ls180.v:8048$2606 + attribute \src "ls180.v:8103.7-8103.49" + cell $or $or$ls180.v:8103$2673 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260547,32 +261623,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_litedram_wb_ack connect \B \main_converter_skip - connect \Y $or$ls180.v:8048$2606_Y + connect \Y $or$ls180.v:8103$2673_Y end - attribute \src "ls180.v:8211.21-8211.74" - cell $or $or$ls180.v:8211$2654 + attribute \src "ls180.v:8266.21-8266.74" + cell $or $or$ls180.v:8266$2721 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8211$2652_Y - connect \B $not$ls180.v:8211$2653_Y - connect \Y $or$ls180.v:8211$2654_Y + connect \A $not$ls180.v:8266$2719_Y + connect \B $not$ls180.v:8266$2720_Y + connect \Y $or$ls180.v:8266$2721_Y end - attribute \src "ls180.v:8246.21-8246.71" - cell $or $or$ls180.v:8246$2659 + attribute \src "ls180.v:8301.21-8301.71" + cell $or $or$ls180.v:8301$2726 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8246$2657_Y - connect \B $not$ls180.v:8246$2658_Y - connect \Y $or$ls180.v:8246$2659_Y + connect \A $not$ls180.v:8301$2724_Y + connect \B $not$ls180.v:8301$2725_Y + connect \Y $or$ls180.v:8301$2726_Y end - attribute \src "ls180.v:8314.32-8314.85" - cell $or $or$ls180.v:8314$2671 + attribute \src "ls180.v:8369.32-8369.85" + cell $or $or$ls180.v:8369$2738 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260580,21 +261656,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_start connect \B \main_sdphy_cmdr_cmdr_run - connect \Y $or$ls180.v:8314$2671_Y + connect \Y $or$ls180.v:8369$2738_Y end - attribute \src "ls180.v:8320.8-8320.97" - cell $or $or$ls180.v:8320$2673 + attribute \src "ls180.v:8375.8-8375.97" + cell $or $or$ls180.v:8375$2740 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8320$2672_Y + connect \A $eq$ls180.v:8375$2739_Y connect \B \main_sdphy_cmdr_cmdr_converter_sink_last - connect \Y $or$ls180.v:8320$2673_Y + connect \Y $or$ls180.v:8375$2740_Y end - attribute \src "ls180.v:8337.52-8337.139" - cell $or $or$ls180.v:8337$2678 + attribute \src "ls180.v:8392.52-8392.139" + cell $or $or$ls180.v:8392$2745 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260602,10 +261678,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_converter_sink_first connect \B \main_sdphy_cmdr_cmdr_converter_source_first - connect \Y $or$ls180.v:8337$2678_Y + connect \Y $or$ls180.v:8392$2745_Y end - attribute \src "ls180.v:8338.51-8338.136" - cell $or $or$ls180.v:8338$2679 + attribute \src "ls180.v:8393.51-8393.136" + cell $or $or$ls180.v:8393$2746 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260613,21 +261689,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_converter_sink_last connect \B \main_sdphy_cmdr_cmdr_converter_source_last - connect \Y $or$ls180.v:8338$2679_Y + connect \Y $or$ls180.v:8393$2746_Y end - attribute \src "ls180.v:8372.7-8372.87" - cell $or $or$ls180.v:8372$2682 + attribute \src "ls180.v:8427.7-8427.87" + cell $or $or$ls180.v:8427$2749 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8372$2681_Y + connect \A $not$ls180.v:8427$2748_Y connect \B \main_sdphy_cmdr_cmdr_buf_source_ready - connect \Y $or$ls180.v:8372$2682_Y + connect \Y $or$ls180.v:8427$2749_Y end - attribute \src "ls180.v:8395.33-8395.88" - cell $or $or$ls180.v:8395$2683 + attribute \src "ls180.v:8450.33-8450.88" + cell $or $or$ls180.v:8450$2750 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260635,21 +261711,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_start connect \B \main_sdphy_dataw_crcr_run - connect \Y $or$ls180.v:8395$2683_Y + connect \Y $or$ls180.v:8450$2750_Y end - attribute \src "ls180.v:8401.8-8401.99" - cell $or $or$ls180.v:8401$2685 + attribute \src "ls180.v:8456.8-8456.99" + cell $or $or$ls180.v:8456$2752 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8401$2684_Y + connect \A $eq$ls180.v:8456$2751_Y connect \B \main_sdphy_dataw_crcr_converter_sink_last - connect \Y $or$ls180.v:8401$2685_Y + connect \Y $or$ls180.v:8456$2752_Y end - attribute \src "ls180.v:8418.53-8418.142" - cell $or $or$ls180.v:8418$2690 + attribute \src "ls180.v:8473.53-8473.142" + cell $or $or$ls180.v:8473$2757 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260657,10 +261733,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_converter_sink_first connect \B \main_sdphy_dataw_crcr_converter_source_first - connect \Y $or$ls180.v:8418$2690_Y + connect \Y $or$ls180.v:8473$2757_Y end - attribute \src "ls180.v:8419.52-8419.139" - cell $or $or$ls180.v:8419$2691 + attribute \src "ls180.v:8474.52-8474.139" + cell $or $or$ls180.v:8474$2758 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260668,21 +261744,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_converter_sink_last connect \B \main_sdphy_dataw_crcr_converter_source_last - connect \Y $or$ls180.v:8419$2691_Y + connect \Y $or$ls180.v:8474$2758_Y end - attribute \src "ls180.v:8453.7-8453.89" - cell $or $or$ls180.v:8453$2694 + attribute \src "ls180.v:8508.7-8508.89" + cell $or $or$ls180.v:8508$2761 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8453$2693_Y + connect \A $not$ls180.v:8508$2760_Y connect \B \main_sdphy_dataw_crcr_buf_source_ready - connect \Y $or$ls180.v:8453$2694_Y + connect \Y $or$ls180.v:8508$2761_Y end - attribute \src "ls180.v:8474.34-8474.91" - cell $or $or$ls180.v:8474$2695 + attribute \src "ls180.v:8529.34-8529.91" + cell $or $or$ls180.v:8529$2762 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260690,21 +261766,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_start connect \B \main_sdphy_datar_datar_run - connect \Y $or$ls180.v:8474$2695_Y + connect \Y $or$ls180.v:8529$2762_Y end - attribute \src "ls180.v:8480.8-8480.101" - cell $or $or$ls180.v:8480$2697 + attribute \src "ls180.v:8535.8-8535.101" + cell $or $or$ls180.v:8535$2764 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8480$2696_Y + connect \A $eq$ls180.v:8535$2763_Y connect \B \main_sdphy_datar_datar_converter_sink_last - connect \Y $or$ls180.v:8480$2697_Y + connect \Y $or$ls180.v:8535$2764_Y end - attribute \src "ls180.v:8497.54-8497.145" - cell $or $or$ls180.v:8497$2702 + attribute \src "ls180.v:8552.54-8552.145" + cell $or $or$ls180.v:8552$2769 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260712,10 +261788,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_converter_sink_first connect \B \main_sdphy_datar_datar_converter_source_first - connect \Y $or$ls180.v:8497$2702_Y + connect \Y $or$ls180.v:8552$2769_Y end - attribute \src "ls180.v:8498.53-8498.142" - cell $or $or$ls180.v:8498$2703 + attribute \src "ls180.v:8553.53-8553.142" + cell $or $or$ls180.v:8553$2770 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260723,32 +261799,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_converter_sink_last connect \B \main_sdphy_datar_datar_converter_source_last - connect \Y $or$ls180.v:8498$2703_Y + connect \Y $or$ls180.v:8553$2770_Y end - attribute \src "ls180.v:8514.7-8514.91" - cell $or $or$ls180.v:8514$2706 + attribute \src "ls180.v:8569.7-8569.91" + cell $or $or$ls180.v:8569$2773 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8514$2705_Y + connect \A $not$ls180.v:8569$2772_Y connect \B \main_sdphy_datar_datar_buf_source_ready - connect \Y $or$ls180.v:8514$2706_Y + connect \Y $or$ls180.v:8569$2773_Y end - attribute \src "ls180.v:8703.8-8703.89" - cell $or $or$ls180.v:8703$2730 + attribute \src "ls180.v:8758.8-8758.89" + cell $or $or$ls180.v:8758$2797 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8703$2729_Y + connect \A $eq$ls180.v:8758$2796_Y connect \B \main_sdblock2mem_converter_sink_last - connect \Y $or$ls180.v:8703$2730_Y + connect \Y $or$ls180.v:8758$2797_Y end - attribute \src "ls180.v:8720.48-8720.127" - cell $or $or$ls180.v:8720$2735 + attribute \src "ls180.v:8775.48-8775.127" + cell $or $or$ls180.v:8775$2802 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260756,10 +261832,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_converter_sink_first connect \B \main_sdblock2mem_converter_source_first - connect \Y $or$ls180.v:8720$2735_Y + connect \Y $or$ls180.v:8775$2802_Y end - attribute \src "ls180.v:8721.47-8721.124" - cell $or $or$ls180.v:8721$2736 + attribute \src "ls180.v:8776.47-8776.124" + cell $or $or$ls180.v:8776$2803 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260767,10 +261843,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_converter_sink_last connect \B \main_sdblock2mem_converter_source_last - connect \Y $or$ls180.v:8721$2736_Y + connect \Y $or$ls180.v:8776$2803_Y end - attribute \src "ls180.v:3253.46-3253.94" - cell $sshl $sshl$ls180.v:3253$134 + attribute \src "ls180.v:3282.46-3282.94" + cell $sshl $sshl$ls180.v:3282$198 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260778,10 +261854,10 @@ module \ls180 parameter \Y_WIDTH 13 connect \A \main_sdram_bankmachine0_auto_precharge connect \B 4'1010 - connect \Y $sshl$ls180.v:3253$134_Y + connect \Y $sshl$ls180.v:3282$198_Y end - attribute \src "ls180.v:3410.46-3410.94" - cell $sshl $sshl$ls180.v:3410$164 + attribute \src "ls180.v:3439.46-3439.94" + cell $sshl $sshl$ls180.v:3439$228 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260789,10 +261865,10 @@ module \ls180 parameter \Y_WIDTH 13 connect \A \main_sdram_bankmachine1_auto_precharge connect \B 4'1010 - connect \Y $sshl$ls180.v:3410$164_Y + connect \Y $sshl$ls180.v:3439$228_Y end - attribute \src "ls180.v:3567.46-3567.94" - cell $sshl $sshl$ls180.v:3567$194 + attribute \src "ls180.v:3596.46-3596.94" + cell $sshl $sshl$ls180.v:3596$258 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260800,10 +261876,10 @@ module \ls180 parameter \Y_WIDTH 13 connect \A \main_sdram_bankmachine2_auto_precharge connect \B 4'1010 - connect \Y $sshl$ls180.v:3567$194_Y + connect \Y $sshl$ls180.v:3596$258_Y end - attribute \src "ls180.v:3724.46-3724.94" - cell $sshl $sshl$ls180.v:3724$224 + attribute \src "ls180.v:3753.46-3753.94" + cell $sshl $sshl$ls180.v:3753$288 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260811,10 +261887,10 @@ module \ls180 parameter \Y_WIDTH 13 connect \A \main_sdram_bankmachine3_auto_precharge connect \B 4'1010 - connect \Y $sshl$ls180.v:3724$224_Y + connect \Y $sshl$ls180.v:3753$288_Y end - attribute \src "ls180.v:3284.63-3284.122" - cell $sub $sub$ls180.v:3284$147 + attribute \src "ls180.v:3313.63-3313.122" + cell $sub $sub$ls180.v:3313$211 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -260822,10 +261898,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_produce connect \B 1'1 - connect \Y $sub$ls180.v:3284$147_Y + connect \Y $sub$ls180.v:3313$211_Y end - attribute \src "ls180.v:3441.63-3441.122" - cell $sub $sub$ls180.v:3441$177 + attribute \src "ls180.v:3470.63-3470.122" + cell $sub $sub$ls180.v:3470$241 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -260833,10 +261909,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_produce connect \B 1'1 - connect \Y $sub$ls180.v:3441$177_Y + connect \Y $sub$ls180.v:3470$241_Y end - attribute \src "ls180.v:3598.63-3598.122" - cell $sub $sub$ls180.v:3598$207 + attribute \src "ls180.v:3627.63-3627.122" + cell $sub $sub$ls180.v:3627$271 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -260844,10 +261920,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_produce connect \B 1'1 - connect \Y $sub$ls180.v:3598$207_Y + connect \Y $sub$ls180.v:3627$271_Y end - attribute \src "ls180.v:3755.63-3755.122" - cell $sub $sub$ls180.v:3755$237 + attribute \src "ls180.v:3784.63-3784.122" + cell $sub $sub$ls180.v:3784$301 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -260855,10 +261931,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_produce connect \B 1'1 - connect \Y $sub$ls180.v:3755$237_Y + connect \Y $sub$ls180.v:3784$301_Y end - attribute \src "ls180.v:4161.38-4161.75" - cell $sub $sub$ls180.v:4161$591 + attribute \src "ls180.v:4190.38-4190.75" + cell $sub $sub$ls180.v:4190$655 parameter \A_SIGNED 0 parameter \A_WIDTH 30 parameter \B_SIGNED 0 @@ -260866,10 +261942,10 @@ module \ls180 parameter \Y_WIDTH 31 connect \A \main_litedram_wb_adr connect \B 31'1001000000000000000000000000000 - connect \Y $sub$ls180.v:4161$591_Y + connect \Y $sub$ls180.v:4190$655_Y end - attribute \src "ls180.v:4247.36-4247.68" - cell $sub $sub$ls180.v:4247$636 + attribute \src "ls180.v:4276.36-4276.68" + cell $sub $sub$ls180.v:4276$700 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -260877,10 +261953,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_uart_tx_fifo_produce connect \B 1'1 - connect \Y $sub$ls180.v:4247$636_Y + connect \Y $sub$ls180.v:4276$700_Y end - attribute \src "ls180.v:4277.36-4277.68" - cell $sub $sub$ls180.v:4277$647 + attribute \src "ls180.v:4306.36-4306.68" + cell $sub $sub$ls180.v:4306$711 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -260888,10 +261964,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_uart_rx_fifo_produce connect \B 1'1 - connect \Y $sub$ls180.v:4277$647_Y + connect \Y $sub$ls180.v:4306$711_Y end - attribute \src "ls180.v:4302.70-4302.110" - cell $sub $sub$ls180.v:4302$653 + attribute \src "ls180.v:4342.70-4342.110" + cell $sub $sub$ls180.v:4342$719 parameter \A_SIGNED 0 parameter \A_WIDTH 15 parameter \B_SIGNED 0 @@ -260899,10 +261975,10 @@ module \ls180 parameter \Y_WIDTH 16 connect \A \main_spimaster8_clk_divider [15:1] connect \B 1'1 - connect \Y $sub$ls180.v:4302$653_Y + connect \Y $sub$ls180.v:4342$719_Y end - attribute \src "ls180.v:4303.70-4303.104" - cell $sub $sub$ls180.v:4303$655 + attribute \src "ls180.v:4343.70-4343.104" + cell $sub $sub$ls180.v:4343$721 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -260910,10 +261986,10 @@ module \ls180 parameter \Y_WIDTH 16 connect \A \main_spimaster8_clk_divider connect \B 1'1 - connect \Y $sub$ls180.v:4303$655_Y + connect \Y $sub$ls180.v:4343$721_Y end - attribute \src "ls180.v:4330.37-4330.66" - cell $sub $sub$ls180.v:4330$659 + attribute \src "ls180.v:4370.37-4370.66" + cell $sub $sub$ls180.v:4370$725 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -260921,10 +261997,10 @@ module \ls180 parameter \Y_WIDTH 8 connect \A \main_spimaster1_length connect \B 1'1 - connect \Y $sub$ls180.v:4330$659_Y + connect \Y $sub$ls180.v:4370$725_Y end - attribute \src "ls180.v:4360.67-4360.107" - cell $sub $sub$ls180.v:4360$661 + attribute \src "ls180.v:4400.67-4400.107" + cell $sub $sub$ls180.v:4400$727 parameter \A_SIGNED 0 parameter \A_WIDTH 15 parameter \B_SIGNED 0 @@ -260932,10 +262008,10 @@ module \ls180 parameter \Y_WIDTH 16 connect \A \main_spisdcard_clk_divider0 [15:1] connect \B 1'1 - connect \Y $sub$ls180.v:4360$661_Y + connect \Y $sub$ls180.v:4400$727_Y end - attribute \src "ls180.v:4361.67-4361.101" - cell $sub $sub$ls180.v:4361$663 + attribute \src "ls180.v:4401.67-4401.101" + cell $sub $sub$ls180.v:4401$729 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -260943,10 +262019,10 @@ module \ls180 parameter \Y_WIDTH 16 connect \A \main_spisdcard_clk_divider0 connect \B 1'1 - connect \Y $sub$ls180.v:4361$663_Y + connect \Y $sub$ls180.v:4401$729_Y end - attribute \src "ls180.v:4389.35-4389.64" - cell $sub $sub$ls180.v:4389$667 + attribute \src "ls180.v:4429.35-4429.64" + cell $sub $sub$ls180.v:4429$733 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -260954,10 +262030,10 @@ module \ls180 parameter \Y_WIDTH 8 connect \A \main_spisdcard_length0 connect \B 1'1 - connect \Y $sub$ls180.v:4389$667_Y + connect \Y $sub$ls180.v:4429$733_Y end - attribute \src "ls180.v:4643.60-4643.90" - cell $sub $sub$ls180.v:4643$711 + attribute \src "ls180.v:4683.60-4683.90" + cell $sub $sub$ls180.v:4683$777 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -260965,10 +262041,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdphy_cmdr_timeout connect \B 1'1 - connect \Y $sub$ls180.v:4643$711_Y + connect \Y $sub$ls180.v:4683$777_Y end - attribute \src "ls180.v:4654.62-4654.104" - cell $sub $sub$ls180.v:4654$713 + attribute \src "ls180.v:4694.62-4694.104" + cell $sub $sub$ls180.v:4694$779 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -260976,10 +262052,10 @@ module \ls180 parameter \Y_WIDTH 8 connect \A \main_sdphy_cmdr_sink_payload_length connect \B 1'1 - connect \Y $sub$ls180.v:4654$713_Y + connect \Y $sub$ls180.v:4694$779_Y end - attribute \src "ls180.v:4671.60-4671.90" - cell $sub $sub$ls180.v:4671$717 + attribute \src "ls180.v:4711.60-4711.90" + cell $sub $sub$ls180.v:4711$783 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -260987,10 +262063,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdphy_cmdr_timeout connect \B 1'1 - connect \Y $sub$ls180.v:4671$717_Y + connect \Y $sub$ls180.v:4711$783_Y end - attribute \src "ls180.v:4900.62-4900.93" - cell $sub $sub$ls180.v:4900$747 + attribute \src "ls180.v:4940.62-4940.93" + cell $sub $sub$ls180.v:4940$813 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -260998,10 +262074,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdphy_datar_timeout connect \B 1'1 - connect \Y $sub$ls180.v:4900$747_Y + connect \Y $sub$ls180.v:4940$813_Y end - attribute \src "ls180.v:4905.62-4905.93" - cell $sub $sub$ls180.v:4905$748 + attribute \src "ls180.v:4945.62-4945.93" + cell $sub $sub$ls180.v:4945$814 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -261009,21 +262085,21 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdphy_datar_timeout connect \B 1'1 - connect \Y $sub$ls180.v:4905$748_Y + connect \Y $sub$ls180.v:4945$814_Y end - attribute \src "ls180.v:4916.64-4916.122" - cell $sub $sub$ls180.v:4916$751 + attribute \src "ls180.v:4956.64-4956.122" + cell $sub $sub$ls180.v:4956$817 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 10 - connect \A $add$ls180.v:4916$750_Y + connect \A $add$ls180.v:4956$816_Y connect \B 1'1 - connect \Y $sub$ls180.v:4916$751_Y + connect \Y $sub$ls180.v:4956$817_Y end - attribute \src "ls180.v:4937.62-4937.93" - cell $sub $sub$ls180.v:4937$754 + attribute \src "ls180.v:4977.62-4977.93" + cell $sub $sub$ls180.v:4977$820 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -261031,10 +262107,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdphy_datar_timeout connect \B 1'1 - connect \Y $sub$ls180.v:4937$754_Y + connect \Y $sub$ls180.v:4977$820_Y end - attribute \src "ls180.v:5399.37-5399.75" - cell $sub $sub$ls180.v:5399$1027 + attribute \src "ls180.v:5439.37-5439.75" + cell $sub $sub$ls180.v:5439$1093 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -261042,10 +262118,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdcore_block_count_storage connect \B 1'1 - connect \Y $sub$ls180.v:5399$1027_Y + connect \Y $sub$ls180.v:5439$1093_Y end - attribute \src "ls180.v:5414.62-5414.100" - cell $sub $sub$ls180.v:5414$1030 + attribute \src "ls180.v:5454.62-5454.100" + cell $sub $sub$ls180.v:5454$1096 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -261053,10 +262129,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdcore_block_count_storage connect \B 1'1 - connect \Y $sub$ls180.v:5414$1030_Y + connect \Y $sub$ls180.v:5454$1096_Y end - attribute \src "ls180.v:5425.39-5425.77" - cell $sub $sub$ls180.v:5425$1035 + attribute \src "ls180.v:5465.39-5465.77" + cell $sub $sub$ls180.v:5465$1101 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -261064,10 +262140,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdcore_block_count_storage connect \B 1'1 - connect \Y $sub$ls180.v:5425$1035_Y + connect \Y $sub$ls180.v:5465$1101_Y end - attribute \src "ls180.v:5500.40-5500.76" - cell $sub $sub$ls180.v:5500$1039 + attribute \src "ls180.v:5540.40-5540.76" + cell $sub $sub$ls180.v:5540$1105 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -261075,10 +262151,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_sdblock2mem_fifo_produce connect \B 1'1 - connect \Y $sub$ls180.v:5500$1039_Y + connect \Y $sub$ls180.v:5540$1105_Y end - attribute \src "ls180.v:5549.56-5549.104" - cell $sub $sub$ls180.v:5549$1053 + attribute \src "ls180.v:5589.56-5589.104" + cell $sub $sub$ls180.v:5589$1119 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -261086,10 +262162,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdblock2mem_wishbonedmawriter_length connect \B 1'1 - connect \Y $sub$ls180.v:5549$1053_Y + connect \Y $sub$ls180.v:5589$1119_Y end - attribute \src "ls180.v:5639.71-5639.105" - cell $sub $sub$ls180.v:5639$1059 + attribute \src "ls180.v:5679.71-5679.105" + cell $sub $sub$ls180.v:5679$1125 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -261097,10 +262173,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdmem2block_dma_length connect \B 1'1 - connect \Y $sub$ls180.v:5639$1059_Y + connect \Y $sub$ls180.v:5679$1125_Y end - attribute \src "ls180.v:5708.40-5708.76" - cell $sub $sub$ls180.v:5708$1070 + attribute \src "ls180.v:5760.40-5760.76" + cell $sub $sub$ls180.v:5760$1136 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -261108,10 +262184,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_sdmem2block_fifo_produce connect \B 1'1 - connect \Y $sub$ls180.v:5708$1070_Y + connect \Y $sub$ls180.v:5760$1136_Y end - attribute \src "ls180.v:7600.31-7600.60" - cell $sub $sub$ls180.v:7600$2477 + attribute \src "ls180.v:7655.31-7655.60" + cell $sub $sub$ls180.v:7655$2544 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -261119,10 +262195,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_libresocsim_value connect \B 1'1 - connect \Y $sub$ls180.v:7600$2477_Y + connect \Y $sub$ls180.v:7655$2544_Y end - attribute \src "ls180.v:7633.31-7633.61" - cell $sub $sub$ls180.v:7633$2491 + attribute \src "ls180.v:7688.31-7688.61" + cell $sub $sub$ls180.v:7688$2558 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -261130,10 +262206,10 @@ module \ls180 parameter \Y_WIDTH 10 connect \A \main_sdram_timer_count1 connect \B 1'1 - connect \Y $sub$ls180.v:7633$2491_Y + connect \Y $sub$ls180.v:7688$2558_Y end - attribute \src "ls180.v:7639.34-7639.67" - cell $sub $sub$ls180.v:7639$2492 + attribute \src "ls180.v:7694.34-7694.67" + cell $sub $sub$ls180.v:7694$2559 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261141,10 +262217,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_postponer_count connect \B 1'1 - connect \Y $sub$ls180.v:7639$2492_Y + connect \Y $sub$ls180.v:7694$2559_Y end - attribute \src "ls180.v:7650.36-7650.69" - cell $sub $sub$ls180.v:7650$2495 + attribute \src "ls180.v:7705.36-7705.69" + cell $sub $sub$ls180.v:7705$2562 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261152,10 +262228,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_count connect \B 1'1 - connect \Y $sub$ls180.v:7650$2495_Y + connect \Y $sub$ls180.v:7705$2562_Y end - attribute \src "ls180.v:7714.59-7714.116" - cell $sub $sub$ls180.v:7714$2513 + attribute \src "ls180.v:7769.59-7769.116" + cell $sub $sub$ls180.v:7769$2580 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -261163,10 +262239,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $sub$ls180.v:7714$2513_Y + connect \Y $sub$ls180.v:7769$2580_Y end - attribute \src "ls180.v:7733.46-7733.90" - cell $sub $sub$ls180.v:7733$2517 + attribute \src "ls180.v:7788.46-7788.90" + cell $sub $sub$ls180.v:7788$2584 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -261174,10 +262250,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine0_twtpcon_count connect \B 1'1 - connect \Y $sub$ls180.v:7733$2517_Y + connect \Y $sub$ls180.v:7788$2584_Y end - attribute \src "ls180.v:7760.59-7760.116" - cell $sub $sub$ls180.v:7760$2529 + attribute \src "ls180.v:7815.59-7815.116" + cell $sub $sub$ls180.v:7815$2596 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -261185,10 +262261,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $sub$ls180.v:7760$2529_Y + connect \Y $sub$ls180.v:7815$2596_Y end - attribute \src "ls180.v:7779.46-7779.90" - cell $sub $sub$ls180.v:7779$2533 + attribute \src "ls180.v:7834.46-7834.90" + cell $sub $sub$ls180.v:7834$2600 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -261196,10 +262272,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine1_twtpcon_count connect \B 1'1 - connect \Y $sub$ls180.v:7779$2533_Y + connect \Y $sub$ls180.v:7834$2600_Y end - attribute \src "ls180.v:7806.59-7806.116" - cell $sub $sub$ls180.v:7806$2545 + attribute \src "ls180.v:7861.59-7861.116" + cell $sub $sub$ls180.v:7861$2612 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -261207,10 +262283,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $sub$ls180.v:7806$2545_Y + connect \Y $sub$ls180.v:7861$2612_Y end - attribute \src "ls180.v:7825.46-7825.90" - cell $sub $sub$ls180.v:7825$2549 + attribute \src "ls180.v:7880.46-7880.90" + cell $sub $sub$ls180.v:7880$2616 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -261218,10 +262294,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine2_twtpcon_count connect \B 1'1 - connect \Y $sub$ls180.v:7825$2549_Y + connect \Y $sub$ls180.v:7880$2616_Y end - attribute \src "ls180.v:7852.59-7852.116" - cell $sub $sub$ls180.v:7852$2561 + attribute \src "ls180.v:7907.59-7907.116" + cell $sub $sub$ls180.v:7907$2628 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -261229,10 +262305,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $sub$ls180.v:7852$2561_Y + connect \Y $sub$ls180.v:7907$2628_Y end - attribute \src "ls180.v:7871.46-7871.90" - cell $sub $sub$ls180.v:7871$2565 + attribute \src "ls180.v:7926.46-7926.90" + cell $sub $sub$ls180.v:7926$2632 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -261240,10 +262316,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine3_twtpcon_count connect \B 1'1 - connect \Y $sub$ls180.v:7871$2565_Y + connect \Y $sub$ls180.v:7926$2632_Y end - attribute \src "ls180.v:7882.25-7882.48" - cell $sub $sub$ls180.v:7882$2569 + attribute \src "ls180.v:7937.25-7937.48" + cell $sub $sub$ls180.v:7937$2636 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -261251,10 +262327,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_sdram_time0 connect \B 1'1 - connect \Y $sub$ls180.v:7882$2569_Y + connect \Y $sub$ls180.v:7937$2636_Y end - attribute \src "ls180.v:7889.25-7889.48" - cell $sub $sub$ls180.v:7889$2572 + attribute \src "ls180.v:7944.25-7944.48" + cell $sub $sub$ls180.v:7944$2639 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -261262,10 +262338,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_time1 connect \B 1'1 - connect \Y $sub$ls180.v:7889$2572_Y + connect \Y $sub$ls180.v:7944$2639_Y end - attribute \src "ls180.v:8021.33-8021.64" - cell $sub $sub$ls180.v:8021$2577 + attribute \src "ls180.v:8076.33-8076.64" + cell $sub $sub$ls180.v:8076$2644 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261273,10 +262349,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_tccdcon_count connect \B 1'1 - connect \Y $sub$ls180.v:8021$2577_Y + connect \Y $sub$ls180.v:8076$2644_Y end - attribute \src "ls180.v:8036.33-8036.64" - cell $sub $sub$ls180.v:8036$2580 + attribute \src "ls180.v:8091.33-8091.64" + cell $sub $sub$ls180.v:8091$2647 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -261284,10 +262360,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_twtrcon_count connect \B 1'1 - connect \Y $sub$ls180.v:8036$2580_Y + connect \Y $sub$ls180.v:8091$2647_Y end - attribute \src "ls180.v:8163.33-8163.64" - cell $sub $sub$ls180.v:8163$2639 + attribute \src "ls180.v:8218.33-8218.64" + cell $sub $sub$ls180.v:8218$2706 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -261295,10 +262371,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_uart_tx_fifo_level0 connect \B 1'1 - connect \Y $sub$ls180.v:8163$2639_Y + connect \Y $sub$ls180.v:8218$2706_Y end - attribute \src "ls180.v:8185.33-8185.64" - cell $sub $sub$ls180.v:8185$2650 + attribute \src "ls180.v:8240.33-8240.64" + cell $sub $sub$ls180.v:8240$2717 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -261306,10 +262382,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_uart_rx_fifo_level0 connect \B 1'1 - connect \Y $sub$ls180.v:8185$2650_Y + connect \Y $sub$ls180.v:8240$2717_Y end - attribute \src "ls180.v:8220.34-8220.66" - cell $sub $sub$ls180.v:8220$2655 + attribute \src "ls180.v:8275.34-8275.66" + cell $sub $sub$ls180.v:8275$2722 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -261317,10 +262393,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_spimaster34_mosi_sel connect \B 1'1 - connect \Y $sub$ls180.v:8220$2655_Y + connect \Y $sub$ls180.v:8275$2722_Y end - attribute \src "ls180.v:8255.32-8255.62" - cell $sub $sub$ls180.v:8255$2660 + attribute \src "ls180.v:8310.32-8310.62" + cell $sub $sub$ls180.v:8310$2727 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -261328,10 +262404,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_spisdcard_mosi_sel connect \B 1'1 - connect \Y $sub$ls180.v:8255$2660_Y + connect \Y $sub$ls180.v:8310$2727_Y end - attribute \src "ls180.v:8279.30-8279.53" - cell $sub $sub$ls180.v:8279$2663 + attribute \src "ls180.v:8334.30-8334.53" + cell $sub $sub$ls180.v:8334$2730 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -261339,10 +262415,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_pwm0_period connect \B 1'1 - connect \Y $sub$ls180.v:8279$2663_Y + connect \Y $sub$ls180.v:8334$2730_Y end - attribute \src "ls180.v:8293.30-8293.53" - cell $sub $sub$ls180.v:8293$2667 + attribute \src "ls180.v:8348.30-8348.53" + cell $sub $sub$ls180.v:8348$2734 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -261350,10 +262426,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_pwm1_period connect \B 1'1 - connect \Y $sub$ls180.v:8293$2667_Y + connect \Y $sub$ls180.v:8348$2734_Y end - attribute \src "ls180.v:8696.36-8696.70" - cell $sub $sub$ls180.v:8696$2728 + attribute \src "ls180.v:8751.36-8751.70" + cell $sub $sub$ls180.v:8751$2795 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -261361,10 +262437,10 @@ module \ls180 parameter \Y_WIDTH 6 connect \A \main_sdblock2mem_fifo_level connect \B 1'1 - connect \Y $sub$ls180.v:8696$2728_Y + connect \Y $sub$ls180.v:8751$2795_Y end - attribute \src "ls180.v:8782.36-8782.70" - cell $sub $sub$ls180.v:8782$2750 + attribute \src "ls180.v:8849.36-8849.70" + cell $sub $sub$ls180.v:8849$2817 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -261372,10 +262448,10 @@ module \ls180 parameter \Y_WIDTH 6 connect \A \main_sdmem2block_fifo_level connect \B 1'1 - connect \Y $sub$ls180.v:8782$2750_Y + connect \Y $sub$ls180.v:8849$2817_Y end - attribute \src "ls180.v:8895.22-8895.42" - cell $sub $sub$ls180.v:8895$2757 + attribute \src "ls180.v:8962.22-8962.42" + cell $sub $sub$ls180.v:8962$2824 parameter \A_SIGNED 0 parameter \A_WIDTH 20 parameter \B_SIGNED 0 @@ -261383,10 +262459,10 @@ module \ls180 parameter \Y_WIDTH 20 connect \A \builder_count connect \B 1'1 - connect \Y $sub$ls180.v:8895$2757_Y + connect \Y $sub$ls180.v:8962$2824_Y end - attribute \src "ls180.v:4997.353-4997.425" - cell $xor $xor$ls180.v:4997$761 + attribute \src "ls180.v:5037.353-5037.425" + cell $xor $xor$ls180.v:5037$827 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261394,10 +262470,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [39] connect \B \main_sdcore_crc7_inserter_crcreg0 [6] - connect \Y $xor$ls180.v:4997$761_Y + connect \Y $xor$ls180.v:5037$827_Y end - attribute \src "ls180.v:4997.200-4997.272" - cell $xor $xor$ls180.v:4997$762 + attribute \src "ls180.v:5037.200-5037.272" + cell $xor $xor$ls180.v:5037$828 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261405,21 +262481,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [39] connect \B \main_sdcore_crc7_inserter_crcreg0 [6] - connect \Y $xor$ls180.v:4997$762_Y + connect \Y $xor$ls180.v:5037$828_Y end - attribute \src "ls180.v:4997.160-4997.273" - cell $xor $xor$ls180.v:4997$763 + attribute \src "ls180.v:5037.160-5037.273" + cell $xor $xor$ls180.v:5037$829 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg0 [2] - connect \B $xor$ls180.v:4997$762_Y - connect \Y $xor$ls180.v:4997$763_Y + connect \B $xor$ls180.v:5037$828_Y + connect \Y $xor$ls180.v:5037$829_Y end - attribute \src "ls180.v:4998.353-4998.425" - cell $xor $xor$ls180.v:4998$764 + attribute \src "ls180.v:5038.353-5038.425" + cell $xor $xor$ls180.v:5038$830 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261427,10 +262503,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [38] connect \B \main_sdcore_crc7_inserter_crcreg1 [6] - connect \Y $xor$ls180.v:4998$764_Y + connect \Y $xor$ls180.v:5038$830_Y end - attribute \src "ls180.v:4998.200-4998.272" - cell $xor $xor$ls180.v:4998$765 + attribute \src "ls180.v:5038.200-5038.272" + cell $xor $xor$ls180.v:5038$831 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261438,21 +262514,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [38] connect \B \main_sdcore_crc7_inserter_crcreg1 [6] - connect \Y $xor$ls180.v:4998$765_Y + connect \Y $xor$ls180.v:5038$831_Y end - attribute \src "ls180.v:4998.160-4998.273" - cell $xor $xor$ls180.v:4998$766 + attribute \src "ls180.v:5038.160-5038.273" + cell $xor $xor$ls180.v:5038$832 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg1 [2] - connect \B $xor$ls180.v:4998$765_Y - connect \Y $xor$ls180.v:4998$766_Y + connect \B $xor$ls180.v:5038$831_Y + connect \Y $xor$ls180.v:5038$832_Y end - attribute \src "ls180.v:4999.353-4999.425" - cell $xor $xor$ls180.v:4999$767 + attribute \src "ls180.v:5039.353-5039.425" + cell $xor $xor$ls180.v:5039$833 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261460,10 +262536,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [37] connect \B \main_sdcore_crc7_inserter_crcreg2 [6] - connect \Y $xor$ls180.v:4999$767_Y + connect \Y $xor$ls180.v:5039$833_Y end - attribute \src "ls180.v:4999.200-4999.272" - cell $xor $xor$ls180.v:4999$768 + attribute \src "ls180.v:5039.200-5039.272" + cell $xor $xor$ls180.v:5039$834 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261471,21 +262547,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [37] connect \B \main_sdcore_crc7_inserter_crcreg2 [6] - connect \Y $xor$ls180.v:4999$768_Y + connect \Y $xor$ls180.v:5039$834_Y end - attribute \src "ls180.v:4999.160-4999.273" - cell $xor $xor$ls180.v:4999$769 + attribute \src "ls180.v:5039.160-5039.273" + cell $xor $xor$ls180.v:5039$835 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg2 [2] - connect \B $xor$ls180.v:4999$768_Y - connect \Y $xor$ls180.v:4999$769_Y + connect \B $xor$ls180.v:5039$834_Y + connect \Y $xor$ls180.v:5039$835_Y end - attribute \src "ls180.v:5000.353-5000.425" - cell $xor $xor$ls180.v:5000$770 + attribute \src "ls180.v:5040.353-5040.425" + cell $xor $xor$ls180.v:5040$836 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261493,10 +262569,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [36] connect \B \main_sdcore_crc7_inserter_crcreg3 [6] - connect \Y $xor$ls180.v:5000$770_Y + connect \Y $xor$ls180.v:5040$836_Y end - attribute \src "ls180.v:5000.200-5000.272" - cell $xor $xor$ls180.v:5000$771 + attribute \src "ls180.v:5040.200-5040.272" + cell $xor $xor$ls180.v:5040$837 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261504,21 +262580,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [36] connect \B \main_sdcore_crc7_inserter_crcreg3 [6] - connect \Y $xor$ls180.v:5000$771_Y + connect \Y $xor$ls180.v:5040$837_Y end - attribute \src "ls180.v:5000.160-5000.273" - cell $xor $xor$ls180.v:5000$772 + attribute \src "ls180.v:5040.160-5040.273" + cell $xor $xor$ls180.v:5040$838 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg3 [2] - connect \B $xor$ls180.v:5000$771_Y - connect \Y $xor$ls180.v:5000$772_Y + connect \B $xor$ls180.v:5040$837_Y + connect \Y $xor$ls180.v:5040$838_Y end - attribute \src "ls180.v:5001.353-5001.425" - cell $xor $xor$ls180.v:5001$773 + attribute \src "ls180.v:5041.353-5041.425" + cell $xor $xor$ls180.v:5041$839 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261526,10 +262602,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [35] connect \B \main_sdcore_crc7_inserter_crcreg4 [6] - connect \Y $xor$ls180.v:5001$773_Y + connect \Y $xor$ls180.v:5041$839_Y end - attribute \src "ls180.v:5001.200-5001.272" - cell $xor $xor$ls180.v:5001$774 + attribute \src "ls180.v:5041.200-5041.272" + cell $xor $xor$ls180.v:5041$840 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261537,21 +262613,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [35] connect \B \main_sdcore_crc7_inserter_crcreg4 [6] - connect \Y $xor$ls180.v:5001$774_Y + connect \Y $xor$ls180.v:5041$840_Y end - attribute \src "ls180.v:5001.160-5001.273" - cell $xor $xor$ls180.v:5001$775 + attribute \src "ls180.v:5041.160-5041.273" + cell $xor $xor$ls180.v:5041$841 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg4 [2] - connect \B $xor$ls180.v:5001$774_Y - connect \Y $xor$ls180.v:5001$775_Y + connect \B $xor$ls180.v:5041$840_Y + connect \Y $xor$ls180.v:5041$841_Y end - attribute \src "ls180.v:5002.353-5002.425" - cell $xor $xor$ls180.v:5002$776 + attribute \src "ls180.v:5042.353-5042.425" + cell $xor $xor$ls180.v:5042$842 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261559,10 +262635,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [34] connect \B \main_sdcore_crc7_inserter_crcreg5 [6] - connect \Y $xor$ls180.v:5002$776_Y + connect \Y $xor$ls180.v:5042$842_Y end - attribute \src "ls180.v:5002.200-5002.272" - cell $xor $xor$ls180.v:5002$777 + attribute \src "ls180.v:5042.200-5042.272" + cell $xor $xor$ls180.v:5042$843 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261570,21 +262646,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [34] connect \B \main_sdcore_crc7_inserter_crcreg5 [6] - connect \Y $xor$ls180.v:5002$777_Y + connect \Y $xor$ls180.v:5042$843_Y end - attribute \src "ls180.v:5002.160-5002.273" - cell $xor $xor$ls180.v:5002$778 + attribute \src "ls180.v:5042.160-5042.273" + cell $xor $xor$ls180.v:5042$844 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg5 [2] - connect \B $xor$ls180.v:5002$777_Y - connect \Y $xor$ls180.v:5002$778_Y + connect \B $xor$ls180.v:5042$843_Y + connect \Y $xor$ls180.v:5042$844_Y end - attribute \src "ls180.v:5003.353-5003.425" - cell $xor $xor$ls180.v:5003$779 + attribute \src "ls180.v:5043.353-5043.425" + cell $xor $xor$ls180.v:5043$845 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261592,10 +262668,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [33] connect \B \main_sdcore_crc7_inserter_crcreg6 [6] - connect \Y $xor$ls180.v:5003$779_Y + connect \Y $xor$ls180.v:5043$845_Y end - attribute \src "ls180.v:5003.200-5003.272" - cell $xor $xor$ls180.v:5003$780 + attribute \src "ls180.v:5043.200-5043.272" + cell $xor $xor$ls180.v:5043$846 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261603,21 +262679,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [33] connect \B \main_sdcore_crc7_inserter_crcreg6 [6] - connect \Y $xor$ls180.v:5003$780_Y + connect \Y $xor$ls180.v:5043$846_Y end - attribute \src "ls180.v:5003.160-5003.273" - cell $xor $xor$ls180.v:5003$781 + attribute \src "ls180.v:5043.160-5043.273" + cell $xor $xor$ls180.v:5043$847 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg6 [2] - connect \B $xor$ls180.v:5003$780_Y - connect \Y $xor$ls180.v:5003$781_Y + connect \B $xor$ls180.v:5043$846_Y + connect \Y $xor$ls180.v:5043$847_Y end - attribute \src "ls180.v:5004.353-5004.425" - cell $xor $xor$ls180.v:5004$782 + attribute \src "ls180.v:5044.353-5044.425" + cell $xor $xor$ls180.v:5044$848 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261625,10 +262701,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [32] connect \B \main_sdcore_crc7_inserter_crcreg7 [6] - connect \Y $xor$ls180.v:5004$782_Y + connect \Y $xor$ls180.v:5044$848_Y end - attribute \src "ls180.v:5004.200-5004.272" - cell $xor $xor$ls180.v:5004$783 + attribute \src "ls180.v:5044.200-5044.272" + cell $xor $xor$ls180.v:5044$849 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261636,21 +262712,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [32] connect \B \main_sdcore_crc7_inserter_crcreg7 [6] - connect \Y $xor$ls180.v:5004$783_Y + connect \Y $xor$ls180.v:5044$849_Y end - attribute \src "ls180.v:5004.160-5004.273" - cell $xor $xor$ls180.v:5004$784 + attribute \src "ls180.v:5044.160-5044.273" + cell $xor $xor$ls180.v:5044$850 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg7 [2] - connect \B $xor$ls180.v:5004$783_Y - connect \Y $xor$ls180.v:5004$784_Y + connect \B $xor$ls180.v:5044$849_Y + connect \Y $xor$ls180.v:5044$850_Y end - attribute \src "ls180.v:5005.353-5005.425" - cell $xor $xor$ls180.v:5005$785 + attribute \src "ls180.v:5045.353-5045.425" + cell $xor $xor$ls180.v:5045$851 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261658,10 +262734,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [31] connect \B \main_sdcore_crc7_inserter_crcreg8 [6] - connect \Y $xor$ls180.v:5005$785_Y + connect \Y $xor$ls180.v:5045$851_Y end - attribute \src "ls180.v:5005.200-5005.272" - cell $xor $xor$ls180.v:5005$786 + attribute \src "ls180.v:5045.200-5045.272" + cell $xor $xor$ls180.v:5045$852 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261669,21 +262745,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [31] connect \B \main_sdcore_crc7_inserter_crcreg8 [6] - connect \Y $xor$ls180.v:5005$786_Y + connect \Y $xor$ls180.v:5045$852_Y end - attribute \src "ls180.v:5005.160-5005.273" - cell $xor $xor$ls180.v:5005$787 + attribute \src "ls180.v:5045.160-5045.273" + cell $xor $xor$ls180.v:5045$853 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg8 [2] - connect \B $xor$ls180.v:5005$786_Y - connect \Y $xor$ls180.v:5005$787_Y + connect \B $xor$ls180.v:5045$852_Y + connect \Y $xor$ls180.v:5045$853_Y end - attribute \src "ls180.v:5006.354-5006.426" - cell $xor $xor$ls180.v:5006$788 + attribute \src "ls180.v:5046.354-5046.426" + cell $xor $xor$ls180.v:5046$854 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261691,10 +262767,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [30] connect \B \main_sdcore_crc7_inserter_crcreg9 [6] - connect \Y $xor$ls180.v:5006$788_Y + connect \Y $xor$ls180.v:5046$854_Y end - attribute \src "ls180.v:5006.201-5006.273" - cell $xor $xor$ls180.v:5006$789 + attribute \src "ls180.v:5046.201-5046.273" + cell $xor $xor$ls180.v:5046$855 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261702,21 +262778,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [30] connect \B \main_sdcore_crc7_inserter_crcreg9 [6] - connect \Y $xor$ls180.v:5006$789_Y + connect \Y $xor$ls180.v:5046$855_Y end - attribute \src "ls180.v:5006.161-5006.274" - cell $xor $xor$ls180.v:5006$790 + attribute \src "ls180.v:5046.161-5046.274" + cell $xor $xor$ls180.v:5046$856 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg9 [2] - connect \B $xor$ls180.v:5006$789_Y - connect \Y $xor$ls180.v:5006$790_Y + connect \B $xor$ls180.v:5046$855_Y + connect \Y $xor$ls180.v:5046$856_Y end - attribute \src "ls180.v:5007.361-5007.434" - cell $xor $xor$ls180.v:5007$791 + attribute \src "ls180.v:5047.361-5047.434" + cell $xor $xor$ls180.v:5047$857 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261724,10 +262800,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [29] connect \B \main_sdcore_crc7_inserter_crcreg10 [6] - connect \Y $xor$ls180.v:5007$791_Y + connect \Y $xor$ls180.v:5047$857_Y end - attribute \src "ls180.v:5007.205-5007.278" - cell $xor $xor$ls180.v:5007$792 + attribute \src "ls180.v:5047.205-5047.278" + cell $xor $xor$ls180.v:5047$858 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261735,21 +262811,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [29] connect \B \main_sdcore_crc7_inserter_crcreg10 [6] - connect \Y $xor$ls180.v:5007$792_Y + connect \Y $xor$ls180.v:5047$858_Y end - attribute \src "ls180.v:5007.164-5007.279" - cell $xor $xor$ls180.v:5007$793 + attribute \src "ls180.v:5047.164-5047.279" + cell $xor $xor$ls180.v:5047$859 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg10 [2] - connect \B $xor$ls180.v:5007$792_Y - connect \Y $xor$ls180.v:5007$793_Y + connect \B $xor$ls180.v:5047$858_Y + connect \Y $xor$ls180.v:5047$859_Y end - attribute \src "ls180.v:5008.361-5008.434" - cell $xor $xor$ls180.v:5008$794 + attribute \src "ls180.v:5048.361-5048.434" + cell $xor $xor$ls180.v:5048$860 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261757,10 +262833,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [28] connect \B \main_sdcore_crc7_inserter_crcreg11 [6] - connect \Y $xor$ls180.v:5008$794_Y + connect \Y $xor$ls180.v:5048$860_Y end - attribute \src "ls180.v:5008.205-5008.278" - cell $xor $xor$ls180.v:5008$795 + attribute \src "ls180.v:5048.205-5048.278" + cell $xor $xor$ls180.v:5048$861 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261768,21 +262844,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [28] connect \B \main_sdcore_crc7_inserter_crcreg11 [6] - connect \Y $xor$ls180.v:5008$795_Y + connect \Y $xor$ls180.v:5048$861_Y end - attribute \src "ls180.v:5008.164-5008.279" - cell $xor $xor$ls180.v:5008$796 + attribute \src "ls180.v:5048.164-5048.279" + cell $xor $xor$ls180.v:5048$862 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg11 [2] - connect \B $xor$ls180.v:5008$795_Y - connect \Y $xor$ls180.v:5008$796_Y + connect \B $xor$ls180.v:5048$861_Y + connect \Y $xor$ls180.v:5048$862_Y end - attribute \src "ls180.v:5009.361-5009.434" - cell $xor $xor$ls180.v:5009$797 + attribute \src "ls180.v:5049.361-5049.434" + cell $xor $xor$ls180.v:5049$863 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261790,10 +262866,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [27] connect \B \main_sdcore_crc7_inserter_crcreg12 [6] - connect \Y $xor$ls180.v:5009$797_Y + connect \Y $xor$ls180.v:5049$863_Y end - attribute \src "ls180.v:5009.205-5009.278" - cell $xor $xor$ls180.v:5009$798 + attribute \src "ls180.v:5049.205-5049.278" + cell $xor $xor$ls180.v:5049$864 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261801,21 +262877,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [27] connect \B \main_sdcore_crc7_inserter_crcreg12 [6] - connect \Y $xor$ls180.v:5009$798_Y + connect \Y $xor$ls180.v:5049$864_Y end - attribute \src "ls180.v:5009.164-5009.279" - cell $xor $xor$ls180.v:5009$799 + attribute \src "ls180.v:5049.164-5049.279" + cell $xor $xor$ls180.v:5049$865 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg12 [2] - connect \B $xor$ls180.v:5009$798_Y - connect \Y $xor$ls180.v:5009$799_Y + connect \B $xor$ls180.v:5049$864_Y + connect \Y $xor$ls180.v:5049$865_Y end - attribute \src "ls180.v:5010.361-5010.434" - cell $xor $xor$ls180.v:5010$800 + attribute \src "ls180.v:5050.361-5050.434" + cell $xor $xor$ls180.v:5050$866 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261823,10 +262899,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [26] connect \B \main_sdcore_crc7_inserter_crcreg13 [6] - connect \Y $xor$ls180.v:5010$800_Y + connect \Y $xor$ls180.v:5050$866_Y end - attribute \src "ls180.v:5010.205-5010.278" - cell $xor $xor$ls180.v:5010$801 + attribute \src "ls180.v:5050.205-5050.278" + cell $xor $xor$ls180.v:5050$867 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261834,21 +262910,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [26] connect \B \main_sdcore_crc7_inserter_crcreg13 [6] - connect \Y $xor$ls180.v:5010$801_Y + connect \Y $xor$ls180.v:5050$867_Y end - attribute \src "ls180.v:5010.164-5010.279" - cell $xor $xor$ls180.v:5010$802 + attribute \src "ls180.v:5050.164-5050.279" + cell $xor $xor$ls180.v:5050$868 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg13 [2] - connect \B $xor$ls180.v:5010$801_Y - connect \Y $xor$ls180.v:5010$802_Y + connect \B $xor$ls180.v:5050$867_Y + connect \Y $xor$ls180.v:5050$868_Y end - attribute \src "ls180.v:5011.361-5011.434" - cell $xor $xor$ls180.v:5011$803 + attribute \src "ls180.v:5051.361-5051.434" + cell $xor $xor$ls180.v:5051$869 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261856,10 +262932,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [25] connect \B \main_sdcore_crc7_inserter_crcreg14 [6] - connect \Y $xor$ls180.v:5011$803_Y + connect \Y $xor$ls180.v:5051$869_Y end - attribute \src "ls180.v:5011.205-5011.278" - cell $xor $xor$ls180.v:5011$804 + attribute \src "ls180.v:5051.205-5051.278" + cell $xor $xor$ls180.v:5051$870 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261867,21 +262943,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [25] connect \B \main_sdcore_crc7_inserter_crcreg14 [6] - connect \Y $xor$ls180.v:5011$804_Y + connect \Y $xor$ls180.v:5051$870_Y end - attribute \src "ls180.v:5011.164-5011.279" - cell $xor $xor$ls180.v:5011$805 + attribute \src "ls180.v:5051.164-5051.279" + cell $xor $xor$ls180.v:5051$871 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg14 [2] - connect \B $xor$ls180.v:5011$804_Y - connect \Y $xor$ls180.v:5011$805_Y + connect \B $xor$ls180.v:5051$870_Y + connect \Y $xor$ls180.v:5051$871_Y end - attribute \src "ls180.v:5012.361-5012.434" - cell $xor $xor$ls180.v:5012$806 + attribute \src "ls180.v:5052.361-5052.434" + cell $xor $xor$ls180.v:5052$872 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261889,10 +262965,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [24] connect \B \main_sdcore_crc7_inserter_crcreg15 [6] - connect \Y $xor$ls180.v:5012$806_Y + connect \Y $xor$ls180.v:5052$872_Y end - attribute \src "ls180.v:5012.205-5012.278" - cell $xor $xor$ls180.v:5012$807 + attribute \src "ls180.v:5052.205-5052.278" + cell $xor $xor$ls180.v:5052$873 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261900,21 +262976,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [24] connect \B \main_sdcore_crc7_inserter_crcreg15 [6] - connect \Y $xor$ls180.v:5012$807_Y + connect \Y $xor$ls180.v:5052$873_Y end - attribute \src "ls180.v:5012.164-5012.279" - cell $xor $xor$ls180.v:5012$808 + attribute \src "ls180.v:5052.164-5052.279" + cell $xor $xor$ls180.v:5052$874 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg15 [2] - connect \B $xor$ls180.v:5012$807_Y - connect \Y $xor$ls180.v:5012$808_Y + connect \B $xor$ls180.v:5052$873_Y + connect \Y $xor$ls180.v:5052$874_Y end - attribute \src "ls180.v:5013.361-5013.434" - cell $xor $xor$ls180.v:5013$809 + attribute \src "ls180.v:5053.361-5053.434" + cell $xor $xor$ls180.v:5053$875 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261922,10 +262998,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [23] connect \B \main_sdcore_crc7_inserter_crcreg16 [6] - connect \Y $xor$ls180.v:5013$809_Y + connect \Y $xor$ls180.v:5053$875_Y end - attribute \src "ls180.v:5013.205-5013.278" - cell $xor $xor$ls180.v:5013$810 + attribute \src "ls180.v:5053.205-5053.278" + cell $xor $xor$ls180.v:5053$876 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261933,21 +263009,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [23] connect \B \main_sdcore_crc7_inserter_crcreg16 [6] - connect \Y $xor$ls180.v:5013$810_Y + connect \Y $xor$ls180.v:5053$876_Y end - attribute \src "ls180.v:5013.164-5013.279" - cell $xor $xor$ls180.v:5013$811 + attribute \src "ls180.v:5053.164-5053.279" + cell $xor $xor$ls180.v:5053$877 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg16 [2] - connect \B $xor$ls180.v:5013$810_Y - connect \Y $xor$ls180.v:5013$811_Y + connect \B $xor$ls180.v:5053$876_Y + connect \Y $xor$ls180.v:5053$877_Y end - attribute \src "ls180.v:5014.361-5014.434" - cell $xor $xor$ls180.v:5014$812 + attribute \src "ls180.v:5054.361-5054.434" + cell $xor $xor$ls180.v:5054$878 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261955,10 +263031,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [22] connect \B \main_sdcore_crc7_inserter_crcreg17 [6] - connect \Y $xor$ls180.v:5014$812_Y + connect \Y $xor$ls180.v:5054$878_Y end - attribute \src "ls180.v:5014.205-5014.278" - cell $xor $xor$ls180.v:5014$813 + attribute \src "ls180.v:5054.205-5054.278" + cell $xor $xor$ls180.v:5054$879 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261966,21 +263042,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [22] connect \B \main_sdcore_crc7_inserter_crcreg17 [6] - connect \Y $xor$ls180.v:5014$813_Y + connect \Y $xor$ls180.v:5054$879_Y end - attribute \src "ls180.v:5014.164-5014.279" - cell $xor $xor$ls180.v:5014$814 + attribute \src "ls180.v:5054.164-5054.279" + cell $xor $xor$ls180.v:5054$880 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg17 [2] - connect \B $xor$ls180.v:5014$813_Y - connect \Y $xor$ls180.v:5014$814_Y + connect \B $xor$ls180.v:5054$879_Y + connect \Y $xor$ls180.v:5054$880_Y end - attribute \src "ls180.v:5015.361-5015.434" - cell $xor $xor$ls180.v:5015$815 + attribute \src "ls180.v:5055.361-5055.434" + cell $xor $xor$ls180.v:5055$881 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261988,10 +263064,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [21] connect \B \main_sdcore_crc7_inserter_crcreg18 [6] - connect \Y $xor$ls180.v:5015$815_Y + connect \Y $xor$ls180.v:5055$881_Y end - attribute \src "ls180.v:5015.205-5015.278" - cell $xor $xor$ls180.v:5015$816 + attribute \src "ls180.v:5055.205-5055.278" + cell $xor $xor$ls180.v:5055$882 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261999,21 +263075,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [21] connect \B \main_sdcore_crc7_inserter_crcreg18 [6] - connect \Y $xor$ls180.v:5015$816_Y + connect \Y $xor$ls180.v:5055$882_Y end - attribute \src "ls180.v:5015.164-5015.279" - cell $xor $xor$ls180.v:5015$817 + attribute \src "ls180.v:5055.164-5055.279" + cell $xor $xor$ls180.v:5055$883 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg18 [2] - connect \B $xor$ls180.v:5015$816_Y - connect \Y $xor$ls180.v:5015$817_Y + connect \B $xor$ls180.v:5055$882_Y + connect \Y $xor$ls180.v:5055$883_Y end - attribute \src "ls180.v:5016.361-5016.434" - cell $xor $xor$ls180.v:5016$818 + attribute \src "ls180.v:5056.361-5056.434" + cell $xor $xor$ls180.v:5056$884 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262021,10 +263097,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [20] connect \B \main_sdcore_crc7_inserter_crcreg19 [6] - connect \Y $xor$ls180.v:5016$818_Y + connect \Y $xor$ls180.v:5056$884_Y end - attribute \src "ls180.v:5016.205-5016.278" - cell $xor $xor$ls180.v:5016$819 + attribute \src "ls180.v:5056.205-5056.278" + cell $xor $xor$ls180.v:5056$885 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262032,21 +263108,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [20] connect \B \main_sdcore_crc7_inserter_crcreg19 [6] - connect \Y $xor$ls180.v:5016$819_Y + connect \Y $xor$ls180.v:5056$885_Y end - attribute \src "ls180.v:5016.164-5016.279" - cell $xor $xor$ls180.v:5016$820 + attribute \src "ls180.v:5056.164-5056.279" + cell $xor $xor$ls180.v:5056$886 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg19 [2] - connect \B $xor$ls180.v:5016$819_Y - connect \Y $xor$ls180.v:5016$820_Y + connect \B $xor$ls180.v:5056$885_Y + connect \Y $xor$ls180.v:5056$886_Y end - attribute \src "ls180.v:5017.361-5017.434" - cell $xor $xor$ls180.v:5017$821 + attribute \src "ls180.v:5057.361-5057.434" + cell $xor $xor$ls180.v:5057$887 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262054,10 +263130,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [19] connect \B \main_sdcore_crc7_inserter_crcreg20 [6] - connect \Y $xor$ls180.v:5017$821_Y + connect \Y $xor$ls180.v:5057$887_Y end - attribute \src "ls180.v:5017.205-5017.278" - cell $xor $xor$ls180.v:5017$822 + attribute \src "ls180.v:5057.205-5057.278" + cell $xor $xor$ls180.v:5057$888 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262065,21 +263141,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [19] connect \B \main_sdcore_crc7_inserter_crcreg20 [6] - connect \Y $xor$ls180.v:5017$822_Y + connect \Y $xor$ls180.v:5057$888_Y end - attribute \src "ls180.v:5017.164-5017.279" - cell $xor $xor$ls180.v:5017$823 + attribute \src "ls180.v:5057.164-5057.279" + cell $xor $xor$ls180.v:5057$889 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg20 [2] - connect \B $xor$ls180.v:5017$822_Y - connect \Y $xor$ls180.v:5017$823_Y + connect \B $xor$ls180.v:5057$888_Y + connect \Y $xor$ls180.v:5057$889_Y end - attribute \src "ls180.v:5018.361-5018.434" - cell $xor $xor$ls180.v:5018$824 + attribute \src "ls180.v:5058.361-5058.434" + cell $xor $xor$ls180.v:5058$890 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262087,10 +263163,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [18] connect \B \main_sdcore_crc7_inserter_crcreg21 [6] - connect \Y $xor$ls180.v:5018$824_Y + connect \Y $xor$ls180.v:5058$890_Y end - attribute \src "ls180.v:5018.205-5018.278" - cell $xor $xor$ls180.v:5018$825 + attribute \src "ls180.v:5058.205-5058.278" + cell $xor $xor$ls180.v:5058$891 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262098,21 +263174,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [18] connect \B \main_sdcore_crc7_inserter_crcreg21 [6] - connect \Y $xor$ls180.v:5018$825_Y + connect \Y $xor$ls180.v:5058$891_Y end - attribute \src "ls180.v:5018.164-5018.279" - cell $xor $xor$ls180.v:5018$826 + attribute \src "ls180.v:5058.164-5058.279" + cell $xor $xor$ls180.v:5058$892 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg21 [2] - connect \B $xor$ls180.v:5018$825_Y - connect \Y $xor$ls180.v:5018$826_Y + connect \B $xor$ls180.v:5058$891_Y + connect \Y $xor$ls180.v:5058$892_Y end - attribute \src "ls180.v:5019.361-5019.434" - cell $xor $xor$ls180.v:5019$827 + attribute \src "ls180.v:5059.361-5059.434" + cell $xor $xor$ls180.v:5059$893 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262120,10 +263196,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [17] connect \B \main_sdcore_crc7_inserter_crcreg22 [6] - connect \Y $xor$ls180.v:5019$827_Y + connect \Y $xor$ls180.v:5059$893_Y end - attribute \src "ls180.v:5019.205-5019.278" - cell $xor $xor$ls180.v:5019$828 + attribute \src "ls180.v:5059.205-5059.278" + cell $xor $xor$ls180.v:5059$894 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262131,21 +263207,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [17] connect \B \main_sdcore_crc7_inserter_crcreg22 [6] - connect \Y $xor$ls180.v:5019$828_Y + connect \Y $xor$ls180.v:5059$894_Y end - attribute \src "ls180.v:5019.164-5019.279" - cell $xor $xor$ls180.v:5019$829 + attribute \src "ls180.v:5059.164-5059.279" + cell $xor $xor$ls180.v:5059$895 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg22 [2] - connect \B $xor$ls180.v:5019$828_Y - connect \Y $xor$ls180.v:5019$829_Y + connect \B $xor$ls180.v:5059$894_Y + connect \Y $xor$ls180.v:5059$895_Y end - attribute \src "ls180.v:5020.361-5020.434" - cell $xor $xor$ls180.v:5020$830 + attribute \src "ls180.v:5060.361-5060.434" + cell $xor $xor$ls180.v:5060$896 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262153,10 +263229,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [16] connect \B \main_sdcore_crc7_inserter_crcreg23 [6] - connect \Y $xor$ls180.v:5020$830_Y + connect \Y $xor$ls180.v:5060$896_Y end - attribute \src "ls180.v:5020.205-5020.278" - cell $xor $xor$ls180.v:5020$831 + attribute \src "ls180.v:5060.205-5060.278" + cell $xor $xor$ls180.v:5060$897 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262164,21 +263240,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [16] connect \B \main_sdcore_crc7_inserter_crcreg23 [6] - connect \Y $xor$ls180.v:5020$831_Y + connect \Y $xor$ls180.v:5060$897_Y end - attribute \src "ls180.v:5020.164-5020.279" - cell $xor $xor$ls180.v:5020$832 + attribute \src "ls180.v:5060.164-5060.279" + cell $xor $xor$ls180.v:5060$898 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg23 [2] - connect \B $xor$ls180.v:5020$831_Y - connect \Y $xor$ls180.v:5020$832_Y + connect \B $xor$ls180.v:5060$897_Y + connect \Y $xor$ls180.v:5060$898_Y end - attribute \src "ls180.v:5021.361-5021.434" - cell $xor $xor$ls180.v:5021$833 + attribute \src "ls180.v:5061.361-5061.434" + cell $xor $xor$ls180.v:5061$899 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262186,10 +263262,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [15] connect \B \main_sdcore_crc7_inserter_crcreg24 [6] - connect \Y $xor$ls180.v:5021$833_Y + connect \Y $xor$ls180.v:5061$899_Y end - attribute \src "ls180.v:5021.205-5021.278" - cell $xor $xor$ls180.v:5021$834 + attribute \src "ls180.v:5061.205-5061.278" + cell $xor $xor$ls180.v:5061$900 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262197,21 +263273,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [15] connect \B \main_sdcore_crc7_inserter_crcreg24 [6] - connect \Y $xor$ls180.v:5021$834_Y + connect \Y $xor$ls180.v:5061$900_Y end - attribute \src "ls180.v:5021.164-5021.279" - cell $xor $xor$ls180.v:5021$835 + attribute \src "ls180.v:5061.164-5061.279" + cell $xor $xor$ls180.v:5061$901 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg24 [2] - connect \B $xor$ls180.v:5021$834_Y - connect \Y $xor$ls180.v:5021$835_Y + connect \B $xor$ls180.v:5061$900_Y + connect \Y $xor$ls180.v:5061$901_Y end - attribute \src "ls180.v:5022.361-5022.434" - cell $xor $xor$ls180.v:5022$836 + attribute \src "ls180.v:5062.361-5062.434" + cell $xor $xor$ls180.v:5062$902 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262219,10 +263295,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [14] connect \B \main_sdcore_crc7_inserter_crcreg25 [6] - connect \Y $xor$ls180.v:5022$836_Y + connect \Y $xor$ls180.v:5062$902_Y end - attribute \src "ls180.v:5022.205-5022.278" - cell $xor $xor$ls180.v:5022$837 + attribute \src "ls180.v:5062.205-5062.278" + cell $xor $xor$ls180.v:5062$903 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262230,21 +263306,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [14] connect \B \main_sdcore_crc7_inserter_crcreg25 [6] - connect \Y $xor$ls180.v:5022$837_Y + connect \Y $xor$ls180.v:5062$903_Y end - attribute \src "ls180.v:5022.164-5022.279" - cell $xor $xor$ls180.v:5022$838 + attribute \src "ls180.v:5062.164-5062.279" + cell $xor $xor$ls180.v:5062$904 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg25 [2] - connect \B $xor$ls180.v:5022$837_Y - connect \Y $xor$ls180.v:5022$838_Y + connect \B $xor$ls180.v:5062$903_Y + connect \Y $xor$ls180.v:5062$904_Y end - attribute \src "ls180.v:5023.361-5023.434" - cell $xor $xor$ls180.v:5023$839 + attribute \src "ls180.v:5063.361-5063.434" + cell $xor $xor$ls180.v:5063$905 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262252,10 +263328,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [13] connect \B \main_sdcore_crc7_inserter_crcreg26 [6] - connect \Y $xor$ls180.v:5023$839_Y + connect \Y $xor$ls180.v:5063$905_Y end - attribute \src "ls180.v:5023.205-5023.278" - cell $xor $xor$ls180.v:5023$840 + attribute \src "ls180.v:5063.205-5063.278" + cell $xor $xor$ls180.v:5063$906 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262263,21 +263339,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [13] connect \B \main_sdcore_crc7_inserter_crcreg26 [6] - connect \Y $xor$ls180.v:5023$840_Y + connect \Y $xor$ls180.v:5063$906_Y end - attribute \src "ls180.v:5023.164-5023.279" - cell $xor $xor$ls180.v:5023$841 + attribute \src "ls180.v:5063.164-5063.279" + cell $xor $xor$ls180.v:5063$907 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg26 [2] - connect \B $xor$ls180.v:5023$840_Y - connect \Y $xor$ls180.v:5023$841_Y + connect \B $xor$ls180.v:5063$906_Y + connect \Y $xor$ls180.v:5063$907_Y end - attribute \src "ls180.v:5024.361-5024.434" - cell $xor $xor$ls180.v:5024$842 + attribute \src "ls180.v:5064.361-5064.434" + cell $xor $xor$ls180.v:5064$908 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262285,10 +263361,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [12] connect \B \main_sdcore_crc7_inserter_crcreg27 [6] - connect \Y $xor$ls180.v:5024$842_Y + connect \Y $xor$ls180.v:5064$908_Y end - attribute \src "ls180.v:5024.205-5024.278" - cell $xor $xor$ls180.v:5024$843 + attribute \src "ls180.v:5064.205-5064.278" + cell $xor $xor$ls180.v:5064$909 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262296,21 +263372,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [12] connect \B \main_sdcore_crc7_inserter_crcreg27 [6] - connect \Y $xor$ls180.v:5024$843_Y + connect \Y $xor$ls180.v:5064$909_Y end - attribute \src "ls180.v:5024.164-5024.279" - cell $xor $xor$ls180.v:5024$844 + attribute \src "ls180.v:5064.164-5064.279" + cell $xor $xor$ls180.v:5064$910 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg27 [2] - connect \B $xor$ls180.v:5024$843_Y - connect \Y $xor$ls180.v:5024$844_Y + connect \B $xor$ls180.v:5064$909_Y + connect \Y $xor$ls180.v:5064$910_Y end - attribute \src "ls180.v:5025.361-5025.434" - cell $xor $xor$ls180.v:5025$845 + attribute \src "ls180.v:5065.361-5065.434" + cell $xor $xor$ls180.v:5065$911 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262318,10 +263394,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [11] connect \B \main_sdcore_crc7_inserter_crcreg28 [6] - connect \Y $xor$ls180.v:5025$845_Y + connect \Y $xor$ls180.v:5065$911_Y end - attribute \src "ls180.v:5025.205-5025.278" - cell $xor $xor$ls180.v:5025$846 + attribute \src "ls180.v:5065.205-5065.278" + cell $xor $xor$ls180.v:5065$912 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262329,21 +263405,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [11] connect \B \main_sdcore_crc7_inserter_crcreg28 [6] - connect \Y $xor$ls180.v:5025$846_Y + connect \Y $xor$ls180.v:5065$912_Y end - attribute \src "ls180.v:5025.164-5025.279" - cell $xor $xor$ls180.v:5025$847 + attribute \src "ls180.v:5065.164-5065.279" + cell $xor $xor$ls180.v:5065$913 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg28 [2] - connect \B $xor$ls180.v:5025$846_Y - connect \Y $xor$ls180.v:5025$847_Y + connect \B $xor$ls180.v:5065$912_Y + connect \Y $xor$ls180.v:5065$913_Y end - attribute \src "ls180.v:5026.361-5026.434" - cell $xor $xor$ls180.v:5026$848 + attribute \src "ls180.v:5066.361-5066.434" + cell $xor $xor$ls180.v:5066$914 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262351,10 +263427,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [10] connect \B \main_sdcore_crc7_inserter_crcreg29 [6] - connect \Y $xor$ls180.v:5026$848_Y + connect \Y $xor$ls180.v:5066$914_Y end - attribute \src "ls180.v:5026.205-5026.278" - cell $xor $xor$ls180.v:5026$849 + attribute \src "ls180.v:5066.205-5066.278" + cell $xor $xor$ls180.v:5066$915 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262362,21 +263438,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [10] connect \B \main_sdcore_crc7_inserter_crcreg29 [6] - connect \Y $xor$ls180.v:5026$849_Y + connect \Y $xor$ls180.v:5066$915_Y end - attribute \src "ls180.v:5026.164-5026.279" - cell $xor $xor$ls180.v:5026$850 + attribute \src "ls180.v:5066.164-5066.279" + cell $xor $xor$ls180.v:5066$916 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg29 [2] - connect \B $xor$ls180.v:5026$849_Y - connect \Y $xor$ls180.v:5026$850_Y + connect \B $xor$ls180.v:5066$915_Y + connect \Y $xor$ls180.v:5066$916_Y end - attribute \src "ls180.v:5027.360-5027.432" - cell $xor $xor$ls180.v:5027$851 + attribute \src "ls180.v:5067.360-5067.432" + cell $xor $xor$ls180.v:5067$917 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262384,10 +263460,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [9] connect \B \main_sdcore_crc7_inserter_crcreg30 [6] - connect \Y $xor$ls180.v:5027$851_Y + connect \Y $xor$ls180.v:5067$917_Y end - attribute \src "ls180.v:5027.205-5027.277" - cell $xor $xor$ls180.v:5027$852 + attribute \src "ls180.v:5067.205-5067.277" + cell $xor $xor$ls180.v:5067$918 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262395,21 +263471,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [9] connect \B \main_sdcore_crc7_inserter_crcreg30 [6] - connect \Y $xor$ls180.v:5027$852_Y + connect \Y $xor$ls180.v:5067$918_Y end - attribute \src "ls180.v:5027.164-5027.278" - cell $xor $xor$ls180.v:5027$853 + attribute \src "ls180.v:5067.164-5067.278" + cell $xor $xor$ls180.v:5067$919 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg30 [2] - connect \B $xor$ls180.v:5027$852_Y - connect \Y $xor$ls180.v:5027$853_Y + connect \B $xor$ls180.v:5067$918_Y + connect \Y $xor$ls180.v:5067$919_Y end - attribute \src "ls180.v:5028.360-5028.432" - cell $xor $xor$ls180.v:5028$854 + attribute \src "ls180.v:5068.360-5068.432" + cell $xor $xor$ls180.v:5068$920 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262417,10 +263493,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [8] connect \B \main_sdcore_crc7_inserter_crcreg31 [6] - connect \Y $xor$ls180.v:5028$854_Y + connect \Y $xor$ls180.v:5068$920_Y end - attribute \src "ls180.v:5028.205-5028.277" - cell $xor $xor$ls180.v:5028$855 + attribute \src "ls180.v:5068.205-5068.277" + cell $xor $xor$ls180.v:5068$921 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262428,21 +263504,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [8] connect \B \main_sdcore_crc7_inserter_crcreg31 [6] - connect \Y $xor$ls180.v:5028$855_Y + connect \Y $xor$ls180.v:5068$921_Y end - attribute \src "ls180.v:5028.164-5028.278" - cell $xor $xor$ls180.v:5028$856 + attribute \src "ls180.v:5068.164-5068.278" + cell $xor $xor$ls180.v:5068$922 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg31 [2] - connect \B $xor$ls180.v:5028$855_Y - connect \Y $xor$ls180.v:5028$856_Y + connect \B $xor$ls180.v:5068$921_Y + connect \Y $xor$ls180.v:5068$922_Y end - attribute \src "ls180.v:5029.360-5029.432" - cell $xor $xor$ls180.v:5029$857 + attribute \src "ls180.v:5069.360-5069.432" + cell $xor $xor$ls180.v:5069$923 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262450,10 +263526,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [7] connect \B \main_sdcore_crc7_inserter_crcreg32 [6] - connect \Y $xor$ls180.v:5029$857_Y + connect \Y $xor$ls180.v:5069$923_Y end - attribute \src "ls180.v:5029.205-5029.277" - cell $xor $xor$ls180.v:5029$858 + attribute \src "ls180.v:5069.205-5069.277" + cell $xor $xor$ls180.v:5069$924 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262461,21 +263537,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [7] connect \B \main_sdcore_crc7_inserter_crcreg32 [6] - connect \Y $xor$ls180.v:5029$858_Y + connect \Y $xor$ls180.v:5069$924_Y end - attribute \src "ls180.v:5029.164-5029.278" - cell $xor $xor$ls180.v:5029$859 + attribute \src "ls180.v:5069.164-5069.278" + cell $xor $xor$ls180.v:5069$925 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg32 [2] - connect \B $xor$ls180.v:5029$858_Y - connect \Y $xor$ls180.v:5029$859_Y + connect \B $xor$ls180.v:5069$924_Y + connect \Y $xor$ls180.v:5069$925_Y end - attribute \src "ls180.v:5030.360-5030.432" - cell $xor $xor$ls180.v:5030$860 + attribute \src "ls180.v:5070.360-5070.432" + cell $xor $xor$ls180.v:5070$926 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262483,10 +263559,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [6] connect \B \main_sdcore_crc7_inserter_crcreg33 [6] - connect \Y $xor$ls180.v:5030$860_Y + connect \Y $xor$ls180.v:5070$926_Y end - attribute \src "ls180.v:5030.205-5030.277" - cell $xor $xor$ls180.v:5030$861 + attribute \src "ls180.v:5070.205-5070.277" + cell $xor $xor$ls180.v:5070$927 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262494,21 +263570,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [6] connect \B \main_sdcore_crc7_inserter_crcreg33 [6] - connect \Y $xor$ls180.v:5030$861_Y + connect \Y $xor$ls180.v:5070$927_Y end - attribute \src "ls180.v:5030.164-5030.278" - cell $xor $xor$ls180.v:5030$862 + attribute \src "ls180.v:5070.164-5070.278" + cell $xor $xor$ls180.v:5070$928 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg33 [2] - connect \B $xor$ls180.v:5030$861_Y - connect \Y $xor$ls180.v:5030$862_Y + connect \B $xor$ls180.v:5070$927_Y + connect \Y $xor$ls180.v:5070$928_Y end - attribute \src "ls180.v:5031.360-5031.432" - cell $xor $xor$ls180.v:5031$863 + attribute \src "ls180.v:5071.360-5071.432" + cell $xor $xor$ls180.v:5071$929 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262516,10 +263592,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [5] connect \B \main_sdcore_crc7_inserter_crcreg34 [6] - connect \Y $xor$ls180.v:5031$863_Y + connect \Y $xor$ls180.v:5071$929_Y end - attribute \src "ls180.v:5031.205-5031.277" - cell $xor $xor$ls180.v:5031$864 + attribute \src "ls180.v:5071.205-5071.277" + cell $xor $xor$ls180.v:5071$930 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262527,21 +263603,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [5] connect \B \main_sdcore_crc7_inserter_crcreg34 [6] - connect \Y $xor$ls180.v:5031$864_Y + connect \Y $xor$ls180.v:5071$930_Y end - attribute \src "ls180.v:5031.164-5031.278" - cell $xor $xor$ls180.v:5031$865 + attribute \src "ls180.v:5071.164-5071.278" + cell $xor $xor$ls180.v:5071$931 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg34 [2] - connect \B $xor$ls180.v:5031$864_Y - connect \Y $xor$ls180.v:5031$865_Y + connect \B $xor$ls180.v:5071$930_Y + connect \Y $xor$ls180.v:5071$931_Y end - attribute \src "ls180.v:5032.360-5032.432" - cell $xor $xor$ls180.v:5032$866 + attribute \src "ls180.v:5072.360-5072.432" + cell $xor $xor$ls180.v:5072$932 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262549,10 +263625,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [4] connect \B \main_sdcore_crc7_inserter_crcreg35 [6] - connect \Y $xor$ls180.v:5032$866_Y + connect \Y $xor$ls180.v:5072$932_Y end - attribute \src "ls180.v:5032.205-5032.277" - cell $xor $xor$ls180.v:5032$867 + attribute \src "ls180.v:5072.205-5072.277" + cell $xor $xor$ls180.v:5072$933 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262560,21 +263636,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [4] connect \B \main_sdcore_crc7_inserter_crcreg35 [6] - connect \Y $xor$ls180.v:5032$867_Y + connect \Y $xor$ls180.v:5072$933_Y end - attribute \src "ls180.v:5032.164-5032.278" - cell $xor $xor$ls180.v:5032$868 + attribute \src "ls180.v:5072.164-5072.278" + cell $xor $xor$ls180.v:5072$934 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg35 [2] - connect \B $xor$ls180.v:5032$867_Y - connect \Y $xor$ls180.v:5032$868_Y + connect \B $xor$ls180.v:5072$933_Y + connect \Y $xor$ls180.v:5072$934_Y end - attribute \src "ls180.v:5033.360-5033.432" - cell $xor $xor$ls180.v:5033$869 + attribute \src "ls180.v:5073.360-5073.432" + cell $xor $xor$ls180.v:5073$935 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262582,10 +263658,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [3] connect \B \main_sdcore_crc7_inserter_crcreg36 [6] - connect \Y $xor$ls180.v:5033$869_Y + connect \Y $xor$ls180.v:5073$935_Y end - attribute \src "ls180.v:5033.205-5033.277" - cell $xor $xor$ls180.v:5033$870 + attribute \src "ls180.v:5073.205-5073.277" + cell $xor $xor$ls180.v:5073$936 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262593,21 +263669,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [3] connect \B \main_sdcore_crc7_inserter_crcreg36 [6] - connect \Y $xor$ls180.v:5033$870_Y + connect \Y $xor$ls180.v:5073$936_Y end - attribute \src "ls180.v:5033.164-5033.278" - cell $xor $xor$ls180.v:5033$871 + attribute \src "ls180.v:5073.164-5073.278" + cell $xor $xor$ls180.v:5073$937 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg36 [2] - connect \B $xor$ls180.v:5033$870_Y - connect \Y $xor$ls180.v:5033$871_Y + connect \B $xor$ls180.v:5073$936_Y + connect \Y $xor$ls180.v:5073$937_Y end - attribute \src "ls180.v:5034.360-5034.432" - cell $xor $xor$ls180.v:5034$872 + attribute \src "ls180.v:5074.360-5074.432" + cell $xor $xor$ls180.v:5074$938 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262615,10 +263691,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [2] connect \B \main_sdcore_crc7_inserter_crcreg37 [6] - connect \Y $xor$ls180.v:5034$872_Y + connect \Y $xor$ls180.v:5074$938_Y end - attribute \src "ls180.v:5034.205-5034.277" - cell $xor $xor$ls180.v:5034$873 + attribute \src "ls180.v:5074.205-5074.277" + cell $xor $xor$ls180.v:5074$939 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262626,21 +263702,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [2] connect \B \main_sdcore_crc7_inserter_crcreg37 [6] - connect \Y $xor$ls180.v:5034$873_Y + connect \Y $xor$ls180.v:5074$939_Y end - attribute \src "ls180.v:5034.164-5034.278" - cell $xor $xor$ls180.v:5034$874 + attribute \src "ls180.v:5074.164-5074.278" + cell $xor $xor$ls180.v:5074$940 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg37 [2] - connect \B $xor$ls180.v:5034$873_Y - connect \Y $xor$ls180.v:5034$874_Y + connect \B $xor$ls180.v:5074$939_Y + connect \Y $xor$ls180.v:5074$940_Y end - attribute \src "ls180.v:5035.360-5035.432" - cell $xor $xor$ls180.v:5035$875 + attribute \src "ls180.v:5075.360-5075.432" + cell $xor $xor$ls180.v:5075$941 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262648,10 +263724,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [1] connect \B \main_sdcore_crc7_inserter_crcreg38 [6] - connect \Y $xor$ls180.v:5035$875_Y + connect \Y $xor$ls180.v:5075$941_Y end - attribute \src "ls180.v:5035.205-5035.277" - cell $xor $xor$ls180.v:5035$876 + attribute \src "ls180.v:5075.205-5075.277" + cell $xor $xor$ls180.v:5075$942 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262659,21 +263735,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [1] connect \B \main_sdcore_crc7_inserter_crcreg38 [6] - connect \Y $xor$ls180.v:5035$876_Y + connect \Y $xor$ls180.v:5075$942_Y end - attribute \src "ls180.v:5035.164-5035.278" - cell $xor $xor$ls180.v:5035$877 + attribute \src "ls180.v:5075.164-5075.278" + cell $xor $xor$ls180.v:5075$943 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg38 [2] - connect \B $xor$ls180.v:5035$876_Y - connect \Y $xor$ls180.v:5035$877_Y + connect \B $xor$ls180.v:5075$942_Y + connect \Y $xor$ls180.v:5075$943_Y end - attribute \src "ls180.v:5036.360-5036.432" - cell $xor $xor$ls180.v:5036$878 + attribute \src "ls180.v:5076.360-5076.432" + cell $xor $xor$ls180.v:5076$944 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262681,10 +263757,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [0] connect \B \main_sdcore_crc7_inserter_crcreg39 [6] - connect \Y $xor$ls180.v:5036$878_Y + connect \Y $xor$ls180.v:5076$944_Y end - attribute \src "ls180.v:5036.205-5036.277" - cell $xor $xor$ls180.v:5036$879 + attribute \src "ls180.v:5076.205-5076.277" + cell $xor $xor$ls180.v:5076$945 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262692,21 +263768,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [0] connect \B \main_sdcore_crc7_inserter_crcreg39 [6] - connect \Y $xor$ls180.v:5036$879_Y + connect \Y $xor$ls180.v:5076$945_Y end - attribute \src "ls180.v:5036.164-5036.278" - cell $xor $xor$ls180.v:5036$880 + attribute \src "ls180.v:5076.164-5076.278" + cell $xor $xor$ls180.v:5076$946 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg39 [2] - connect \B $xor$ls180.v:5036$879_Y - connect \Y $xor$ls180.v:5036$880_Y + connect \B $xor$ls180.v:5076$945_Y + connect \Y $xor$ls180.v:5076$946_Y end - attribute \src "ls180.v:5057.899-5057.983" - cell $xor $xor$ls180.v:5057$894 + attribute \src "ls180.v:5097.899-5097.983" + cell $xor $xor$ls180.v:5097$960 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262714,10 +263790,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc0_val [1] connect \B \main_sdcore_crc16_inserter_crc0_crcreg0 [15] - connect \Y $xor$ls180.v:5057$894_Y + connect \Y $xor$ls180.v:5097$960_Y end - attribute \src "ls180.v:5057.634-5057.718" - cell $xor $xor$ls180.v:5057$895 + attribute \src "ls180.v:5097.634-5097.718" + cell $xor $xor$ls180.v:5097$961 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262725,21 +263801,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc0_val [1] connect \B \main_sdcore_crc16_inserter_crc0_crcreg0 [15] - connect \Y $xor$ls180.v:5057$895_Y + connect \Y $xor$ls180.v:5097$961_Y end - attribute \src "ls180.v:5057.588-5057.719" - cell $xor $xor$ls180.v:5057$896 + attribute \src "ls180.v:5097.588-5097.719" + cell $xor $xor$ls180.v:5097$962 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc0_crcreg0 [4] - connect \B $xor$ls180.v:5057$895_Y - connect \Y $xor$ls180.v:5057$896_Y + connect \B $xor$ls180.v:5097$961_Y + connect \Y $xor$ls180.v:5097$962_Y end - attribute \src "ls180.v:5057.234-5057.318" - cell $xor $xor$ls180.v:5057$897 + attribute \src "ls180.v:5097.234-5097.318" + cell $xor $xor$ls180.v:5097$963 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262747,21 +263823,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc0_val [1] connect \B \main_sdcore_crc16_inserter_crc0_crcreg0 [15] - connect \Y $xor$ls180.v:5057$897_Y + connect \Y $xor$ls180.v:5097$963_Y end - attribute \src "ls180.v:5057.187-5057.319" - cell $xor $xor$ls180.v:5057$898 + attribute \src "ls180.v:5097.187-5097.319" + cell $xor $xor$ls180.v:5097$964 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc0_crcreg0 [11] - connect \B $xor$ls180.v:5057$897_Y - connect \Y $xor$ls180.v:5057$898_Y + connect \B $xor$ls180.v:5097$963_Y + connect \Y $xor$ls180.v:5097$964_Y end - attribute \src "ls180.v:5058.899-5058.983" - cell $xor $xor$ls180.v:5058$899 + attribute \src "ls180.v:5098.899-5098.983" + cell $xor $xor$ls180.v:5098$965 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262769,10 +263845,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc0_val [0] connect \B \main_sdcore_crc16_inserter_crc0_crcreg1 [15] - connect \Y $xor$ls180.v:5058$899_Y + connect \Y $xor$ls180.v:5098$965_Y end - attribute \src "ls180.v:5058.634-5058.718" - cell $xor $xor$ls180.v:5058$900 + attribute \src "ls180.v:5098.634-5098.718" + cell $xor $xor$ls180.v:5098$966 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262780,21 +263856,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc0_val [0] connect \B \main_sdcore_crc16_inserter_crc0_crcreg1 [15] - connect \Y $xor$ls180.v:5058$900_Y + connect \Y $xor$ls180.v:5098$966_Y end - attribute \src "ls180.v:5058.588-5058.719" - cell $xor $xor$ls180.v:5058$901 + attribute \src "ls180.v:5098.588-5098.719" + cell $xor $xor$ls180.v:5098$967 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc0_crcreg1 [4] - connect \B $xor$ls180.v:5058$900_Y - connect \Y $xor$ls180.v:5058$901_Y + connect \B $xor$ls180.v:5098$966_Y + connect \Y $xor$ls180.v:5098$967_Y end - attribute \src "ls180.v:5058.234-5058.318" - cell $xor $xor$ls180.v:5058$902 + attribute \src "ls180.v:5098.234-5098.318" + cell $xor $xor$ls180.v:5098$968 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262802,21 +263878,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc0_val [0] connect \B \main_sdcore_crc16_inserter_crc0_crcreg1 [15] - connect \Y $xor$ls180.v:5058$902_Y + connect \Y $xor$ls180.v:5098$968_Y end - attribute \src "ls180.v:5058.187-5058.319" - cell $xor $xor$ls180.v:5058$903 + attribute \src "ls180.v:5098.187-5098.319" + cell $xor $xor$ls180.v:5098$969 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc0_crcreg1 [11] - connect \B $xor$ls180.v:5058$902_Y - connect \Y $xor$ls180.v:5058$903_Y + connect \B $xor$ls180.v:5098$968_Y + connect \Y $xor$ls180.v:5098$969_Y end - attribute \src "ls180.v:5067.899-5067.983" - cell $xor $xor$ls180.v:5067$905 + attribute \src "ls180.v:5107.899-5107.983" + cell $xor $xor$ls180.v:5107$971 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262824,10 +263900,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc1_val [1] connect \B \main_sdcore_crc16_inserter_crc1_crcreg0 [15] - connect \Y $xor$ls180.v:5067$905_Y + connect \Y $xor$ls180.v:5107$971_Y end - attribute \src "ls180.v:5067.634-5067.718" - cell $xor $xor$ls180.v:5067$906 + attribute \src "ls180.v:5107.634-5107.718" + cell $xor $xor$ls180.v:5107$972 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262835,21 +263911,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc1_val [1] connect \B \main_sdcore_crc16_inserter_crc1_crcreg0 [15] - connect \Y $xor$ls180.v:5067$906_Y + connect \Y $xor$ls180.v:5107$972_Y end - attribute \src "ls180.v:5067.588-5067.719" - cell $xor $xor$ls180.v:5067$907 + attribute \src "ls180.v:5107.588-5107.719" + cell $xor $xor$ls180.v:5107$973 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc1_crcreg0 [4] - connect \B $xor$ls180.v:5067$906_Y - connect \Y $xor$ls180.v:5067$907_Y + connect \B $xor$ls180.v:5107$972_Y + connect \Y $xor$ls180.v:5107$973_Y end - attribute \src "ls180.v:5067.234-5067.318" - cell $xor $xor$ls180.v:5067$908 + attribute \src "ls180.v:5107.234-5107.318" + cell $xor $xor$ls180.v:5107$974 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262857,21 +263933,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc1_val [1] connect \B \main_sdcore_crc16_inserter_crc1_crcreg0 [15] - connect \Y $xor$ls180.v:5067$908_Y + connect \Y $xor$ls180.v:5107$974_Y end - attribute \src "ls180.v:5067.187-5067.319" - cell $xor $xor$ls180.v:5067$909 + attribute \src "ls180.v:5107.187-5107.319" + cell $xor $xor$ls180.v:5107$975 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc1_crcreg0 [11] - connect \B $xor$ls180.v:5067$908_Y - connect \Y $xor$ls180.v:5067$909_Y + connect \B $xor$ls180.v:5107$974_Y + connect \Y $xor$ls180.v:5107$975_Y end - attribute \src "ls180.v:5068.899-5068.983" - cell $xor $xor$ls180.v:5068$910 + attribute \src "ls180.v:5108.899-5108.983" + cell $xor $xor$ls180.v:5108$976 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262879,10 +263955,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc1_val [0] connect \B \main_sdcore_crc16_inserter_crc1_crcreg1 [15] - connect \Y $xor$ls180.v:5068$910_Y + connect \Y $xor$ls180.v:5108$976_Y end - attribute \src "ls180.v:5068.634-5068.718" - cell $xor $xor$ls180.v:5068$911 + attribute \src "ls180.v:5108.634-5108.718" + cell $xor $xor$ls180.v:5108$977 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262890,21 +263966,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc1_val [0] connect \B \main_sdcore_crc16_inserter_crc1_crcreg1 [15] - connect \Y $xor$ls180.v:5068$911_Y + connect \Y $xor$ls180.v:5108$977_Y end - attribute \src "ls180.v:5068.588-5068.719" - cell $xor $xor$ls180.v:5068$912 + attribute \src "ls180.v:5108.588-5108.719" + cell $xor $xor$ls180.v:5108$978 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc1_crcreg1 [4] - connect \B $xor$ls180.v:5068$911_Y - connect \Y $xor$ls180.v:5068$912_Y + connect \B $xor$ls180.v:5108$977_Y + connect \Y $xor$ls180.v:5108$978_Y end - attribute \src "ls180.v:5068.234-5068.318" - cell $xor $xor$ls180.v:5068$913 + attribute \src "ls180.v:5108.234-5108.318" + cell $xor $xor$ls180.v:5108$979 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262912,21 +263988,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc1_val [0] connect \B \main_sdcore_crc16_inserter_crc1_crcreg1 [15] - connect \Y $xor$ls180.v:5068$913_Y + connect \Y $xor$ls180.v:5108$979_Y end - attribute \src "ls180.v:5068.187-5068.319" - cell $xor $xor$ls180.v:5068$914 + attribute \src "ls180.v:5108.187-5108.319" + cell $xor $xor$ls180.v:5108$980 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc1_crcreg1 [11] - connect \B $xor$ls180.v:5068$913_Y - connect \Y $xor$ls180.v:5068$914_Y + connect \B $xor$ls180.v:5108$979_Y + connect \Y $xor$ls180.v:5108$980_Y end - attribute \src "ls180.v:5077.899-5077.983" - cell $xor $xor$ls180.v:5077$916 + attribute \src "ls180.v:5117.899-5117.983" + cell $xor $xor$ls180.v:5117$982 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262934,10 +264010,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc2_val [1] connect \B \main_sdcore_crc16_inserter_crc2_crcreg0 [15] - connect \Y $xor$ls180.v:5077$916_Y + connect \Y $xor$ls180.v:5117$982_Y end - attribute \src "ls180.v:5077.634-5077.718" - cell $xor $xor$ls180.v:5077$917 + attribute \src "ls180.v:5117.634-5117.718" + cell $xor $xor$ls180.v:5117$983 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262945,21 +264021,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc2_val [1] connect \B \main_sdcore_crc16_inserter_crc2_crcreg0 [15] - connect \Y $xor$ls180.v:5077$917_Y + connect \Y $xor$ls180.v:5117$983_Y end - attribute \src "ls180.v:5077.588-5077.719" - cell $xor $xor$ls180.v:5077$918 + attribute \src "ls180.v:5117.588-5117.719" + cell $xor $xor$ls180.v:5117$984 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc2_crcreg0 [4] - connect \B $xor$ls180.v:5077$917_Y - connect \Y $xor$ls180.v:5077$918_Y + connect \B $xor$ls180.v:5117$983_Y + connect \Y $xor$ls180.v:5117$984_Y end - attribute \src "ls180.v:5077.234-5077.318" - cell $xor $xor$ls180.v:5077$919 + attribute \src "ls180.v:5117.234-5117.318" + cell $xor $xor$ls180.v:5117$985 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262967,21 +264043,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc2_val [1] connect \B \main_sdcore_crc16_inserter_crc2_crcreg0 [15] - connect \Y $xor$ls180.v:5077$919_Y + connect \Y $xor$ls180.v:5117$985_Y end - attribute \src "ls180.v:5077.187-5077.319" - cell $xor $xor$ls180.v:5077$920 + attribute \src "ls180.v:5117.187-5117.319" + cell $xor $xor$ls180.v:5117$986 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc2_crcreg0 [11] - connect \B $xor$ls180.v:5077$919_Y - connect \Y $xor$ls180.v:5077$920_Y + connect \B $xor$ls180.v:5117$985_Y + connect \Y $xor$ls180.v:5117$986_Y end - attribute \src "ls180.v:5078.899-5078.983" - cell $xor $xor$ls180.v:5078$921 + attribute \src "ls180.v:5118.899-5118.983" + cell $xor $xor$ls180.v:5118$987 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262989,10 +264065,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc2_val [0] connect \B \main_sdcore_crc16_inserter_crc2_crcreg1 [15] - connect \Y $xor$ls180.v:5078$921_Y + connect \Y $xor$ls180.v:5118$987_Y end - attribute \src "ls180.v:5078.634-5078.718" - cell $xor $xor$ls180.v:5078$922 + attribute \src "ls180.v:5118.634-5118.718" + cell $xor $xor$ls180.v:5118$988 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263000,21 +264076,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc2_val [0] connect \B \main_sdcore_crc16_inserter_crc2_crcreg1 [15] - connect \Y $xor$ls180.v:5078$922_Y + connect \Y $xor$ls180.v:5118$988_Y end - attribute \src "ls180.v:5078.588-5078.719" - cell $xor $xor$ls180.v:5078$923 + attribute \src "ls180.v:5118.588-5118.719" + cell $xor $xor$ls180.v:5118$989 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc2_crcreg1 [4] - connect \B $xor$ls180.v:5078$922_Y - connect \Y $xor$ls180.v:5078$923_Y + connect \B $xor$ls180.v:5118$988_Y + connect \Y $xor$ls180.v:5118$989_Y end - attribute \src "ls180.v:5078.234-5078.318" - cell $xor $xor$ls180.v:5078$924 + attribute \src "ls180.v:5118.234-5118.318" + cell $xor $xor$ls180.v:5118$990 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263022,21 +264098,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc2_val [0] connect \B \main_sdcore_crc16_inserter_crc2_crcreg1 [15] - connect \Y $xor$ls180.v:5078$924_Y + connect \Y $xor$ls180.v:5118$990_Y end - attribute \src "ls180.v:5078.187-5078.319" - cell $xor $xor$ls180.v:5078$925 + attribute \src "ls180.v:5118.187-5118.319" + cell $xor $xor$ls180.v:5118$991 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc2_crcreg1 [11] - connect \B $xor$ls180.v:5078$924_Y - connect \Y $xor$ls180.v:5078$925_Y + connect \B $xor$ls180.v:5118$990_Y + connect \Y $xor$ls180.v:5118$991_Y end - attribute \src "ls180.v:5087.899-5087.983" - cell $xor $xor$ls180.v:5087$927 + attribute \src "ls180.v:5127.899-5127.983" + cell $xor $xor$ls180.v:5127$993 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263044,10 +264120,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc3_val [1] connect \B \main_sdcore_crc16_inserter_crc3_crcreg0 [15] - connect \Y $xor$ls180.v:5087$927_Y + connect \Y $xor$ls180.v:5127$993_Y end - attribute \src "ls180.v:5087.634-5087.718" - cell $xor $xor$ls180.v:5087$928 + attribute \src "ls180.v:5127.634-5127.718" + cell $xor $xor$ls180.v:5127$994 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263055,21 +264131,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc3_val [1] connect \B \main_sdcore_crc16_inserter_crc3_crcreg0 [15] - connect \Y $xor$ls180.v:5087$928_Y + connect \Y $xor$ls180.v:5127$994_Y end - attribute \src "ls180.v:5087.588-5087.719" - cell $xor $xor$ls180.v:5087$929 + attribute \src "ls180.v:5127.588-5127.719" + cell $xor $xor$ls180.v:5127$995 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc3_crcreg0 [4] - connect \B $xor$ls180.v:5087$928_Y - connect \Y $xor$ls180.v:5087$929_Y + connect \B $xor$ls180.v:5127$994_Y + connect \Y $xor$ls180.v:5127$995_Y end - attribute \src "ls180.v:5087.234-5087.318" - cell $xor $xor$ls180.v:5087$930 + attribute \src "ls180.v:5127.234-5127.318" + cell $xor $xor$ls180.v:5127$996 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263077,32 +264153,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc3_val [1] connect \B \main_sdcore_crc16_inserter_crc3_crcreg0 [15] - connect \Y $xor$ls180.v:5087$930_Y + connect \Y $xor$ls180.v:5127$996_Y end - attribute \src "ls180.v:5087.187-5087.319" - cell $xor $xor$ls180.v:5087$931 + attribute \src "ls180.v:5127.187-5127.319" + cell $xor $xor$ls180.v:5127$997 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc3_crcreg0 [11] - connect \B $xor$ls180.v:5087$930_Y - connect \Y $xor$ls180.v:5087$931_Y + connect \B $xor$ls180.v:5127$996_Y + connect \Y $xor$ls180.v:5127$997_Y end - attribute \src "ls180.v:5088.899-5088.983" - cell $xor $xor$ls180.v:5088$932 + attribute \src "ls180.v:5128.588-5128.719" + cell $xor $xor$ls180.v:5128$1000 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc3_val [0] - connect \B \main_sdcore_crc16_inserter_crc3_crcreg1 [15] - connect \Y $xor$ls180.v:5088$932_Y + connect \A \main_sdcore_crc16_inserter_crc3_crcreg1 [4] + connect \B $xor$ls180.v:5128$999_Y + connect \Y $xor$ls180.v:5128$1000_Y end - attribute \src "ls180.v:5088.634-5088.718" - cell $xor $xor$ls180.v:5088$933 + attribute \src "ls180.v:5128.234-5128.318" + cell $xor $xor$ls180.v:5128$1001 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263110,21 +264186,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc3_val [0] connect \B \main_sdcore_crc16_inserter_crc3_crcreg1 [15] - connect \Y $xor$ls180.v:5088$933_Y + connect \Y $xor$ls180.v:5128$1001_Y end - attribute \src "ls180.v:5088.588-5088.719" - cell $xor $xor$ls180.v:5088$934 + attribute \src "ls180.v:5128.187-5128.319" + cell $xor $xor$ls180.v:5128$1002 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc3_crcreg1 [4] - connect \B $xor$ls180.v:5088$933_Y - connect \Y $xor$ls180.v:5088$934_Y + connect \A \main_sdcore_crc16_inserter_crc3_crcreg1 [11] + connect \B $xor$ls180.v:5128$1001_Y + connect \Y $xor$ls180.v:5128$1002_Y end - attribute \src "ls180.v:5088.234-5088.318" - cell $xor $xor$ls180.v:5088$935 + attribute \src "ls180.v:5128.899-5128.983" + cell $xor $xor$ls180.v:5128$998 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263132,21 +264208,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc3_val [0] connect \B \main_sdcore_crc16_inserter_crc3_crcreg1 [15] - connect \Y $xor$ls180.v:5088$935_Y + connect \Y $xor$ls180.v:5128$998_Y end - attribute \src "ls180.v:5088.187-5088.319" - cell $xor $xor$ls180.v:5088$936 + attribute \src "ls180.v:5128.634-5128.718" + cell $xor $xor$ls180.v:5128$999 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc3_crcreg1 [11] - connect \B $xor$ls180.v:5088$935_Y - connect \Y $xor$ls180.v:5088$936_Y + connect \A \main_sdcore_crc16_inserter_crc3_val [0] + connect \B \main_sdcore_crc16_inserter_crc3_crcreg1 [15] + connect \Y $xor$ls180.v:5128$999_Y end - attribute \src "ls180.v:5239.879-5239.961" - cell $xor $xor$ls180.v:5239$969 + attribute \src "ls180.v:5279.879-5279.961" + cell $xor $xor$ls180.v:5279$1035 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263154,10 +264230,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc0_val [1] connect \B \main_sdcore_crc16_checker_crc0_crcreg0 [15] - connect \Y $xor$ls180.v:5239$969_Y + connect \Y $xor$ls180.v:5279$1035_Y end - attribute \src "ls180.v:5239.620-5239.702" - cell $xor $xor$ls180.v:5239$970 + attribute \src "ls180.v:5279.620-5279.702" + cell $xor $xor$ls180.v:5279$1036 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263165,21 +264241,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc0_val [1] connect \B \main_sdcore_crc16_checker_crc0_crcreg0 [15] - connect \Y $xor$ls180.v:5239$970_Y + connect \Y $xor$ls180.v:5279$1036_Y end - attribute \src "ls180.v:5239.575-5239.703" - cell $xor $xor$ls180.v:5239$971 + attribute \src "ls180.v:5279.575-5279.703" + cell $xor $xor$ls180.v:5279$1037 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc0_crcreg0 [4] - connect \B $xor$ls180.v:5239$970_Y - connect \Y $xor$ls180.v:5239$971_Y + connect \B $xor$ls180.v:5279$1036_Y + connect \Y $xor$ls180.v:5279$1037_Y end - attribute \src "ls180.v:5239.229-5239.311" - cell $xor $xor$ls180.v:5239$972 + attribute \src "ls180.v:5279.229-5279.311" + cell $xor $xor$ls180.v:5279$1038 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263187,21 +264263,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc0_val [1] connect \B \main_sdcore_crc16_checker_crc0_crcreg0 [15] - connect \Y $xor$ls180.v:5239$972_Y + connect \Y $xor$ls180.v:5279$1038_Y end - attribute \src "ls180.v:5239.183-5239.312" - cell $xor $xor$ls180.v:5239$973 + attribute \src "ls180.v:5279.183-5279.312" + cell $xor $xor$ls180.v:5279$1039 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc0_crcreg0 [11] - connect \B $xor$ls180.v:5239$972_Y - connect \Y $xor$ls180.v:5239$973_Y + connect \B $xor$ls180.v:5279$1038_Y + connect \Y $xor$ls180.v:5279$1039_Y end - attribute \src "ls180.v:5240.879-5240.961" - cell $xor $xor$ls180.v:5240$974 + attribute \src "ls180.v:5280.879-5280.961" + cell $xor $xor$ls180.v:5280$1040 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263209,10 +264285,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc0_val [0] connect \B \main_sdcore_crc16_checker_crc0_crcreg1 [15] - connect \Y $xor$ls180.v:5240$974_Y + connect \Y $xor$ls180.v:5280$1040_Y end - attribute \src "ls180.v:5240.620-5240.702" - cell $xor $xor$ls180.v:5240$975 + attribute \src "ls180.v:5280.620-5280.702" + cell $xor $xor$ls180.v:5280$1041 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263220,21 +264296,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc0_val [0] connect \B \main_sdcore_crc16_checker_crc0_crcreg1 [15] - connect \Y $xor$ls180.v:5240$975_Y + connect \Y $xor$ls180.v:5280$1041_Y end - attribute \src "ls180.v:5240.575-5240.703" - cell $xor $xor$ls180.v:5240$976 + attribute \src "ls180.v:5280.575-5280.703" + cell $xor $xor$ls180.v:5280$1042 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc0_crcreg1 [4] - connect \B $xor$ls180.v:5240$975_Y - connect \Y $xor$ls180.v:5240$976_Y + connect \B $xor$ls180.v:5280$1041_Y + connect \Y $xor$ls180.v:5280$1042_Y end - attribute \src "ls180.v:5240.229-5240.311" - cell $xor $xor$ls180.v:5240$977 + attribute \src "ls180.v:5280.229-5280.311" + cell $xor $xor$ls180.v:5280$1043 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263242,21 +264318,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc0_val [0] connect \B \main_sdcore_crc16_checker_crc0_crcreg1 [15] - connect \Y $xor$ls180.v:5240$977_Y + connect \Y $xor$ls180.v:5280$1043_Y end - attribute \src "ls180.v:5240.183-5240.312" - cell $xor $xor$ls180.v:5240$978 + attribute \src "ls180.v:5280.183-5280.312" + cell $xor $xor$ls180.v:5280$1044 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc0_crcreg1 [11] - connect \B $xor$ls180.v:5240$977_Y - connect \Y $xor$ls180.v:5240$978_Y + connect \B $xor$ls180.v:5280$1043_Y + connect \Y $xor$ls180.v:5280$1044_Y end - attribute \src "ls180.v:5249.879-5249.961" - cell $xor $xor$ls180.v:5249$980 + attribute \src "ls180.v:5289.879-5289.961" + cell $xor $xor$ls180.v:5289$1046 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263264,10 +264340,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc1_val [1] connect \B \main_sdcore_crc16_checker_crc1_crcreg0 [15] - connect \Y $xor$ls180.v:5249$980_Y + connect \Y $xor$ls180.v:5289$1046_Y end - attribute \src "ls180.v:5249.620-5249.702" - cell $xor $xor$ls180.v:5249$981 + attribute \src "ls180.v:5289.620-5289.702" + cell $xor $xor$ls180.v:5289$1047 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263275,21 +264351,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc1_val [1] connect \B \main_sdcore_crc16_checker_crc1_crcreg0 [15] - connect \Y $xor$ls180.v:5249$981_Y + connect \Y $xor$ls180.v:5289$1047_Y end - attribute \src "ls180.v:5249.575-5249.703" - cell $xor $xor$ls180.v:5249$982 + attribute \src "ls180.v:5289.575-5289.703" + cell $xor $xor$ls180.v:5289$1048 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc1_crcreg0 [4] - connect \B $xor$ls180.v:5249$981_Y - connect \Y $xor$ls180.v:5249$982_Y + connect \B $xor$ls180.v:5289$1047_Y + connect \Y $xor$ls180.v:5289$1048_Y end - attribute \src "ls180.v:5249.229-5249.311" - cell $xor $xor$ls180.v:5249$983 + attribute \src "ls180.v:5289.229-5289.311" + cell $xor $xor$ls180.v:5289$1049 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263297,21 +264373,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc1_val [1] connect \B \main_sdcore_crc16_checker_crc1_crcreg0 [15] - connect \Y $xor$ls180.v:5249$983_Y + connect \Y $xor$ls180.v:5289$1049_Y end - attribute \src "ls180.v:5249.183-5249.312" - cell $xor $xor$ls180.v:5249$984 + attribute \src "ls180.v:5289.183-5289.312" + cell $xor $xor$ls180.v:5289$1050 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc1_crcreg0 [11] - connect \B $xor$ls180.v:5249$983_Y - connect \Y $xor$ls180.v:5249$984_Y + connect \B $xor$ls180.v:5289$1049_Y + connect \Y $xor$ls180.v:5289$1050_Y end - attribute \src "ls180.v:5250.879-5250.961" - cell $xor $xor$ls180.v:5250$985 + attribute \src "ls180.v:5290.879-5290.961" + cell $xor $xor$ls180.v:5290$1051 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263319,10 +264395,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc1_val [0] connect \B \main_sdcore_crc16_checker_crc1_crcreg1 [15] - connect \Y $xor$ls180.v:5250$985_Y + connect \Y $xor$ls180.v:5290$1051_Y end - attribute \src "ls180.v:5250.620-5250.702" - cell $xor $xor$ls180.v:5250$986 + attribute \src "ls180.v:5290.620-5290.702" + cell $xor $xor$ls180.v:5290$1052 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263330,21 +264406,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc1_val [0] connect \B \main_sdcore_crc16_checker_crc1_crcreg1 [15] - connect \Y $xor$ls180.v:5250$986_Y + connect \Y $xor$ls180.v:5290$1052_Y end - attribute \src "ls180.v:5250.575-5250.703" - cell $xor $xor$ls180.v:5250$987 + attribute \src "ls180.v:5290.575-5290.703" + cell $xor $xor$ls180.v:5290$1053 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc1_crcreg1 [4] - connect \B $xor$ls180.v:5250$986_Y - connect \Y $xor$ls180.v:5250$987_Y + connect \B $xor$ls180.v:5290$1052_Y + connect \Y $xor$ls180.v:5290$1053_Y end - attribute \src "ls180.v:5250.229-5250.311" - cell $xor $xor$ls180.v:5250$988 + attribute \src "ls180.v:5290.229-5290.311" + cell $xor $xor$ls180.v:5290$1054 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263352,21 +264428,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc1_val [0] connect \B \main_sdcore_crc16_checker_crc1_crcreg1 [15] - connect \Y $xor$ls180.v:5250$988_Y + connect \Y $xor$ls180.v:5290$1054_Y end - attribute \src "ls180.v:5250.183-5250.312" - cell $xor $xor$ls180.v:5250$989 + attribute \src "ls180.v:5290.183-5290.312" + cell $xor $xor$ls180.v:5290$1055 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc1_crcreg1 [11] - connect \B $xor$ls180.v:5250$988_Y - connect \Y $xor$ls180.v:5250$989_Y + connect \B $xor$ls180.v:5290$1054_Y + connect \Y $xor$ls180.v:5290$1055_Y end - attribute \src "ls180.v:5259.879-5259.961" - cell $xor $xor$ls180.v:5259$991 + attribute \src "ls180.v:5299.879-5299.961" + cell $xor $xor$ls180.v:5299$1057 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263374,10 +264450,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc2_val [1] connect \B \main_sdcore_crc16_checker_crc2_crcreg0 [15] - connect \Y $xor$ls180.v:5259$991_Y + connect \Y $xor$ls180.v:5299$1057_Y end - attribute \src "ls180.v:5259.620-5259.702" - cell $xor $xor$ls180.v:5259$992 + attribute \src "ls180.v:5299.620-5299.702" + cell $xor $xor$ls180.v:5299$1058 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263385,21 +264461,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc2_val [1] connect \B \main_sdcore_crc16_checker_crc2_crcreg0 [15] - connect \Y $xor$ls180.v:5259$992_Y + connect \Y $xor$ls180.v:5299$1058_Y end - attribute \src "ls180.v:5259.575-5259.703" - cell $xor $xor$ls180.v:5259$993 + attribute \src "ls180.v:5299.575-5299.703" + cell $xor $xor$ls180.v:5299$1059 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc2_crcreg0 [4] - connect \B $xor$ls180.v:5259$992_Y - connect \Y $xor$ls180.v:5259$993_Y + connect \B $xor$ls180.v:5299$1058_Y + connect \Y $xor$ls180.v:5299$1059_Y end - attribute \src "ls180.v:5259.229-5259.311" - cell $xor $xor$ls180.v:5259$994 + attribute \src "ls180.v:5299.229-5299.311" + cell $xor $xor$ls180.v:5299$1060 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263407,32 +264483,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc2_val [1] connect \B \main_sdcore_crc16_checker_crc2_crcreg0 [15] - connect \Y $xor$ls180.v:5259$994_Y + connect \Y $xor$ls180.v:5299$1060_Y end - attribute \src "ls180.v:5259.183-5259.312" - cell $xor $xor$ls180.v:5259$995 + attribute \src "ls180.v:5299.183-5299.312" + cell $xor $xor$ls180.v:5299$1061 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc2_crcreg0 [11] - connect \B $xor$ls180.v:5259$994_Y - connect \Y $xor$ls180.v:5259$995_Y + connect \B $xor$ls180.v:5299$1060_Y + connect \Y $xor$ls180.v:5299$1061_Y end - attribute \src "ls180.v:5260.183-5260.312" - cell $xor $xor$ls180.v:5260$1000 + attribute \src "ls180.v:5300.879-5300.961" + cell $xor $xor$ls180.v:5300$1062 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc2_crcreg1 [11] - connect \B $xor$ls180.v:5260$999_Y - connect \Y $xor$ls180.v:5260$1000_Y + connect \A \main_sdcore_crc16_checker_crc2_val [0] + connect \B \main_sdcore_crc16_checker_crc2_crcreg1 [15] + connect \Y $xor$ls180.v:5300$1062_Y end - attribute \src "ls180.v:5260.879-5260.961" - cell $xor $xor$ls180.v:5260$996 + attribute \src "ls180.v:5300.620-5300.702" + cell $xor $xor$ls180.v:5300$1063 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263440,43 +264516,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc2_val [0] connect \B \main_sdcore_crc16_checker_crc2_crcreg1 [15] - connect \Y $xor$ls180.v:5260$996_Y + connect \Y $xor$ls180.v:5300$1063_Y end - attribute \src "ls180.v:5260.620-5260.702" - cell $xor $xor$ls180.v:5260$997 + attribute \src "ls180.v:5300.575-5300.703" + cell $xor $xor$ls180.v:5300$1064 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc2_val [0] - connect \B \main_sdcore_crc16_checker_crc2_crcreg1 [15] - connect \Y $xor$ls180.v:5260$997_Y + connect \A \main_sdcore_crc16_checker_crc2_crcreg1 [4] + connect \B $xor$ls180.v:5300$1063_Y + connect \Y $xor$ls180.v:5300$1064_Y end - attribute \src "ls180.v:5260.575-5260.703" - cell $xor $xor$ls180.v:5260$998 + attribute \src "ls180.v:5300.229-5300.311" + cell $xor $xor$ls180.v:5300$1065 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc2_crcreg1 [4] - connect \B $xor$ls180.v:5260$997_Y - connect \Y $xor$ls180.v:5260$998_Y + connect \A \main_sdcore_crc16_checker_crc2_val [0] + connect \B \main_sdcore_crc16_checker_crc2_crcreg1 [15] + connect \Y $xor$ls180.v:5300$1065_Y end - attribute \src "ls180.v:5260.229-5260.311" - cell $xor $xor$ls180.v:5260$999 + attribute \src "ls180.v:5300.183-5300.312" + cell $xor $xor$ls180.v:5300$1066 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc2_val [0] - connect \B \main_sdcore_crc16_checker_crc2_crcreg1 [15] - connect \Y $xor$ls180.v:5260$999_Y + connect \A \main_sdcore_crc16_checker_crc2_crcreg1 [11] + connect \B $xor$ls180.v:5300$1065_Y + connect \Y $xor$ls180.v:5300$1066_Y end - attribute \src "ls180.v:5269.879-5269.961" - cell $xor $xor$ls180.v:5269$1002 + attribute \src "ls180.v:5309.879-5309.961" + cell $xor $xor$ls180.v:5309$1068 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263484,10 +264560,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc3_val [1] connect \B \main_sdcore_crc16_checker_crc3_crcreg0 [15] - connect \Y $xor$ls180.v:5269$1002_Y + connect \Y $xor$ls180.v:5309$1068_Y end - attribute \src "ls180.v:5269.620-5269.702" - cell $xor $xor$ls180.v:5269$1003 + attribute \src "ls180.v:5309.620-5309.702" + cell $xor $xor$ls180.v:5309$1069 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263495,21 +264571,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc3_val [1] connect \B \main_sdcore_crc16_checker_crc3_crcreg0 [15] - connect \Y $xor$ls180.v:5269$1003_Y + connect \Y $xor$ls180.v:5309$1069_Y end - attribute \src "ls180.v:5269.575-5269.703" - cell $xor $xor$ls180.v:5269$1004 + attribute \src "ls180.v:5309.575-5309.703" + cell $xor $xor$ls180.v:5309$1070 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc3_crcreg0 [4] - connect \B $xor$ls180.v:5269$1003_Y - connect \Y $xor$ls180.v:5269$1004_Y + connect \B $xor$ls180.v:5309$1069_Y + connect \Y $xor$ls180.v:5309$1070_Y end - attribute \src "ls180.v:5269.229-5269.311" - cell $xor $xor$ls180.v:5269$1005 + attribute \src "ls180.v:5309.229-5309.311" + cell $xor $xor$ls180.v:5309$1071 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263517,21 +264593,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc3_val [1] connect \B \main_sdcore_crc16_checker_crc3_crcreg0 [15] - connect \Y $xor$ls180.v:5269$1005_Y + connect \Y $xor$ls180.v:5309$1071_Y end - attribute \src "ls180.v:5269.183-5269.312" - cell $xor $xor$ls180.v:5269$1006 + attribute \src "ls180.v:5309.183-5309.312" + cell $xor $xor$ls180.v:5309$1072 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc3_crcreg0 [11] - connect \B $xor$ls180.v:5269$1005_Y - connect \Y $xor$ls180.v:5269$1006_Y + connect \B $xor$ls180.v:5309$1071_Y + connect \Y $xor$ls180.v:5309$1072_Y end - attribute \src "ls180.v:5270.879-5270.961" - cell $xor $xor$ls180.v:5270$1007 + attribute \src "ls180.v:5310.879-5310.961" + cell $xor $xor$ls180.v:5310$1073 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263539,10 +264615,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc3_val [0] connect \B \main_sdcore_crc16_checker_crc3_crcreg1 [15] - connect \Y $xor$ls180.v:5270$1007_Y + connect \Y $xor$ls180.v:5310$1073_Y end - attribute \src "ls180.v:5270.620-5270.702" - cell $xor $xor$ls180.v:5270$1008 + attribute \src "ls180.v:5310.620-5310.702" + cell $xor $xor$ls180.v:5310$1074 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263550,21 +264626,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc3_val [0] connect \B \main_sdcore_crc16_checker_crc3_crcreg1 [15] - connect \Y $xor$ls180.v:5270$1008_Y + connect \Y $xor$ls180.v:5310$1074_Y end - attribute \src "ls180.v:5270.575-5270.703" - cell $xor $xor$ls180.v:5270$1009 + attribute \src "ls180.v:5310.575-5310.703" + cell $xor $xor$ls180.v:5310$1075 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc3_crcreg1 [4] - connect \B $xor$ls180.v:5270$1008_Y - connect \Y $xor$ls180.v:5270$1009_Y + connect \B $xor$ls180.v:5310$1074_Y + connect \Y $xor$ls180.v:5310$1075_Y end - attribute \src "ls180.v:5270.229-5270.311" - cell $xor $xor$ls180.v:5270$1010 + attribute \src "ls180.v:5310.229-5310.311" + cell $xor $xor$ls180.v:5310$1076 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263572,21 +264648,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc3_val [0] connect \B \main_sdcore_crc16_checker_crc3_crcreg1 [15] - connect \Y $xor$ls180.v:5270$1010_Y + connect \Y $xor$ls180.v:5310$1076_Y end - attribute \src "ls180.v:5270.183-5270.312" - cell $xor $xor$ls180.v:5270$1011 + attribute \src "ls180.v:5310.183-5310.312" + cell $xor $xor$ls180.v:5310$1077 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc3_crcreg1 [11] - connect \B $xor$ls180.v:5270$1010_Y - connect \Y $xor$ls180.v:5270$1011_Y + connect \B $xor$ls180.v:5310$1076_Y + connect \Y $xor$ls180.v:5310$1077_Y end attribute \module_not_derived 1 - attribute \src "ls180.v:10356.13-10730.2" + attribute \src "ls180.v:10455.13-10829.2" cell \test_issuer \test_issuer connect \TAP_bus__tck \main_libresocsim_libresoc_jtag_tck connect \TAP_bus__tdi \main_libresocsim_libresoc_jtag_tdi @@ -263782,7 +264858,7 @@ module \ls180 connect \pwm_0__pad__o \pwm_1 [0] connect \pwm_1__core__o \pwm [1] connect \pwm_1__pad__o \pwm_1 [1] - connect \rst $or$ls180.v:10456$2870_Y + connect \rst $or$ls180.v:10555$2985_Y connect \sd0_clk__core__o \sdcard_clk connect \sd0_clk__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_clk connect \sd0_cmd__core__i \sdcard_cmd_i @@ -263963,67 +265039,101 @@ module \ls180 connect \sdr_we_n__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_we_n end attribute \src "ls180.v:0.0-0.0" - process $proc$ls180.v:0$3842 + process $proc$ls180.v:0$3983 sync always sync init end attribute \src "ls180.v:0.0-0.0" - process $proc$ls180.v:0$3843 + process $proc$ls180.v:0$3984 sync always sync init end attribute \src "ls180.v:0.0-0.0" - process $proc$ls180.v:0$3844 + process $proc$ls180.v:0$3985 sync always sync init end attribute \src "ls180.v:0.0-0.0" - process $proc$ls180.v:0$3845 + process $proc$ls180.v:0$3986 + sync always + sync init + end + attribute \src "ls180.v:100.11-100.56" + process $proc$ls180.v:100$3044 + assign { } { } + assign $1\main_libresocsim_libresoc_xics_ics_sel[3:0] 4'0000 sync always sync init + update \main_libresocsim_libresoc_xics_ics_sel $1\main_libresocsim_libresoc_xics_ics_sel[3:0] end - attribute \src "ls180.v:1004.11-1004.42" - process $proc$ls180.v:1004$3254 + attribute \src "ls180.v:1003.11-1003.42" + process $proc$ls180.v:1003$3384 assign { } { } assign $1\main_uart_rx_fifo_level0[4:0] 5'00000 sync always sync init update \main_uart_rx_fifo_level0 $1\main_uart_rx_fifo_level0[4:0] end - attribute \src "ls180.v:1005.5-1005.37" - process $proc$ls180.v:1005$3255 + attribute \src "ls180.v:1004.5-1004.37" + process $proc$ls180.v:1004$3385 assign { } { } assign $0\main_uart_rx_fifo_replace[0:0] 1'0 sync always update \main_uart_rx_fifo_replace $0\main_uart_rx_fifo_replace[0:0] sync init end - attribute \src "ls180.v:1006.11-1006.43" - process $proc$ls180.v:1006$3256 + attribute \src "ls180.v:1005.11-1005.43" + process $proc$ls180.v:1005$3386 assign { } { } assign $1\main_uart_rx_fifo_produce[3:0] 4'0000 sync always sync init update \main_uart_rx_fifo_produce $1\main_uart_rx_fifo_produce[3:0] end - attribute \src "ls180.v:1007.11-1007.43" - process $proc$ls180.v:1007$3257 + attribute \src "ls180.v:1006.11-1006.43" + process $proc$ls180.v:1006$3387 assign { } { } assign $1\main_uart_rx_fifo_consume[3:0] 4'0000 sync always sync init update \main_uart_rx_fifo_consume $1\main_uart_rx_fifo_consume[3:0] end - attribute \src "ls180.v:1008.11-1008.46" - process $proc$ls180.v:1008$3258 + attribute \src "ls180.v:1007.11-1007.46" + process $proc$ls180.v:1007$3388 assign { } { } assign $1\main_uart_rx_fifo_wrport_adr[3:0] 4'0000 sync always sync init update \main_uart_rx_fifo_wrport_adr $1\main_uart_rx_fifo_wrport_adr[3:0] end - attribute \src "ls180.v:10160.1-10170.4" - process $proc$ls180.v:10160$2758 + attribute \src "ls180.v:101.5-101.50" + process $proc$ls180.v:101$3045 + assign { } { } + assign $1\main_libresocsim_libresoc_xics_ics_cyc[0:0] 1'0 + sync always + sync init + update \main_libresocsim_libresoc_xics_ics_cyc $1\main_libresocsim_libresoc_xics_ics_cyc[0:0] + end + attribute \src "ls180.v:102.5-102.50" + process $proc$ls180.v:102$3046 + assign { } { } + assign $1\main_libresocsim_libresoc_xics_ics_stb[0:0] 1'0 + sync always + sync init + update \main_libresocsim_libresoc_xics_ics_stb $1\main_libresocsim_libresoc_xics_ics_stb[0:0] + end + attribute \src "ls180.v:1022.5-1022.27" + process $proc$ls180.v:1022$3389 + assign { } { } + assign $0\main_uart_reset[0:0] 1'0 + sync always + update \main_uart_reset $0\main_uart_reset[0:0] + sync init + end + attribute \src "ls180.v:10227.1-10245.4" + process $proc$ls180.v:10227$2825 + assign { } { } + assign { } { } assign { } { } assign { } { } assign { } { } @@ -264037,72 +265147,167 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0$memwr$\mem$ls180.v:10168$4_ADDR[6:0]$2768 7'xxxxxxx - assign $0$memwr$\mem$ls180.v:10168$4_DATA[31:0]$2769 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:10168$4_EN[31:0]$2770 0 - assign $0$memwr$\mem$ls180.v:10166$3_ADDR[6:0]$2765 7'xxxxxxx - assign $0$memwr$\mem$ls180.v:10166$3_DATA[31:0]$2766 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:10166$3_EN[31:0]$2767 0 - assign $0$memwr$\mem$ls180.v:10164$2_ADDR[6:0]$2762 7'xxxxxxx - assign $0$memwr$\mem$ls180.v:10164$2_DATA[31:0]$2763 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:10164$2_EN[31:0]$2764 0 - assign $0$memwr$\mem$ls180.v:10162$1_ADDR[6:0]$2759 7'xxxxxxx - assign $0$memwr$\mem$ls180.v:10162$1_DATA[31:0]$2760 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:10162$1_EN[31:0]$2761 0 - assign $0\memadr[6:0] \main_libresocsim_adr - attribute \src "ls180.v:10161.2-10162.65" + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\mem$ls180.v:10243$8_ADDR[5:0]$2847 6'xxxxxx + assign $0$memwr$\mem$ls180.v:10243$8_DATA[63:0]$2848 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10243$8_EN[63:0]$2849 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10241$7_ADDR[5:0]$2844 6'xxxxxx + assign $0$memwr$\mem$ls180.v:10241$7_DATA[63:0]$2845 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10241$7_EN[63:0]$2846 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10239$6_ADDR[5:0]$2841 6'xxxxxx + assign $0$memwr$\mem$ls180.v:10239$6_DATA[63:0]$2842 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10239$6_EN[63:0]$2843 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10237$5_ADDR[5:0]$2838 6'xxxxxx + assign $0$memwr$\mem$ls180.v:10237$5_DATA[63:0]$2839 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10237$5_EN[63:0]$2840 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10235$4_ADDR[5:0]$2835 6'xxxxxx + assign $0$memwr$\mem$ls180.v:10235$4_DATA[63:0]$2836 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10235$4_EN[63:0]$2837 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10233$3_ADDR[5:0]$2832 6'xxxxxx + assign $0$memwr$\mem$ls180.v:10233$3_DATA[63:0]$2833 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10233$3_EN[63:0]$2834 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10231$2_ADDR[5:0]$2829 6'xxxxxx + assign $0$memwr$\mem$ls180.v:10231$2_DATA[63:0]$2830 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10231$2_EN[63:0]$2831 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10229$1_ADDR[5:0]$2826 6'xxxxxx + assign $0$memwr$\mem$ls180.v:10229$1_DATA[63:0]$2827 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10229$1_EN[63:0]$2828 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\memadr[5:0] \main_libresocsim_adr + attribute \src "ls180.v:10228.2-10229.65" switch \main_libresocsim_we [0] - attribute \src "ls180.v:10161.6-10161.28" + attribute \src "ls180.v:10228.6-10228.28" case 1'1 - assign $0$memwr$\mem$ls180.v:10162$1_ADDR[6:0]$2759 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:10162$1_DATA[31:0]$2760 { 24'000000000000000000000000 \main_libresocsim_dat_w [7:0] } - assign $0$memwr$\mem$ls180.v:10162$1_EN[31:0]$2761 255 + assign $0$memwr$\mem$ls180.v:10229$1_ADDR[5:0]$2826 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10229$1_DATA[63:0]$2827 { 56'00000000000000000000000000000000000000000000000000000000 \main_libresocsim_dat_w [7:0] } + assign $0$memwr$\mem$ls180.v:10229$1_EN[63:0]$2828 64'0000000000000000000000000000000000000000000000000000000011111111 case end - attribute \src "ls180.v:10163.2-10164.67" + attribute \src "ls180.v:10230.2-10231.67" switch \main_libresocsim_we [1] - attribute \src "ls180.v:10163.6-10163.28" + attribute \src "ls180.v:10230.6-10230.28" case 1'1 - assign $0$memwr$\mem$ls180.v:10164$2_ADDR[6:0]$2762 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:10164$2_DATA[31:0]$2763 { 16'0000000000000000 \main_libresocsim_dat_w [15:8] 8'xxxxxxxx } - assign $0$memwr$\mem$ls180.v:10164$2_EN[31:0]$2764 65280 + assign $0$memwr$\mem$ls180.v:10231$2_ADDR[5:0]$2829 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10231$2_DATA[63:0]$2830 { 48'000000000000000000000000000000000000000000000000 \main_libresocsim_dat_w [15:8] 8'xxxxxxxx } + assign $0$memwr$\mem$ls180.v:10231$2_EN[63:0]$2831 64'0000000000000000000000000000000000000000000000001111111100000000 case end - attribute \src "ls180.v:10165.2-10166.69" + attribute \src "ls180.v:10232.2-10233.69" switch \main_libresocsim_we [2] - attribute \src "ls180.v:10165.6-10165.28" + attribute \src "ls180.v:10232.6-10232.28" case 1'1 - assign $0$memwr$\mem$ls180.v:10166$3_ADDR[6:0]$2765 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:10166$3_DATA[31:0]$2766 { 8'00000000 \main_libresocsim_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } - assign $0$memwr$\mem$ls180.v:10166$3_EN[31:0]$2767 16711680 + assign $0$memwr$\mem$ls180.v:10233$3_ADDR[5:0]$2832 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10233$3_DATA[63:0]$2833 { 40'0000000000000000000000000000000000000000 \main_libresocsim_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } + assign $0$memwr$\mem$ls180.v:10233$3_EN[63:0]$2834 64'0000000000000000000000000000000000000000111111110000000000000000 case end - attribute \src "ls180.v:10167.2-10168.69" + attribute \src "ls180.v:10234.2-10235.69" switch \main_libresocsim_we [3] - attribute \src "ls180.v:10167.6-10167.28" + attribute \src "ls180.v:10234.6-10234.28" + case 1'1 + assign $0$memwr$\mem$ls180.v:10235$4_ADDR[5:0]$2835 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10235$4_DATA[63:0]$2836 { 32'00000000000000000000000000000000 \main_libresocsim_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem$ls180.v:10235$4_EN[63:0]$2837 64'0000000000000000000000000000000011111111000000000000000000000000 + case + end + attribute \src "ls180.v:10236.2-10237.69" + switch \main_libresocsim_we [4] + attribute \src "ls180.v:10236.6-10236.28" + case 1'1 + assign $0$memwr$\mem$ls180.v:10237$5_ADDR[5:0]$2838 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10237$5_DATA[63:0]$2839 { 24'000000000000000000000000 \main_libresocsim_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem$ls180.v:10237$5_EN[63:0]$2840 64'0000000000000000000000001111111100000000000000000000000000000000 + case + end + attribute \src "ls180.v:10238.2-10239.69" + switch \main_libresocsim_we [5] + attribute \src "ls180.v:10238.6-10238.28" + case 1'1 + assign $0$memwr$\mem$ls180.v:10239$6_ADDR[5:0]$2841 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10239$6_DATA[63:0]$2842 { 16'0000000000000000 \main_libresocsim_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem$ls180.v:10239$6_EN[63:0]$2843 64'0000000000000000111111110000000000000000000000000000000000000000 + case + end + attribute \src "ls180.v:10240.2-10241.69" + switch \main_libresocsim_we [6] + attribute \src "ls180.v:10240.6-10240.28" + case 1'1 + assign $0$memwr$\mem$ls180.v:10241$7_ADDR[5:0]$2844 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10241$7_DATA[63:0]$2845 { 8'00000000 \main_libresocsim_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem$ls180.v:10241$7_EN[63:0]$2846 64'0000000011111111000000000000000000000000000000000000000000000000 + case + end + attribute \src "ls180.v:10242.2-10243.69" + switch \main_libresocsim_we [7] + attribute \src "ls180.v:10242.6-10242.28" case 1'1 - assign $0$memwr$\mem$ls180.v:10168$4_ADDR[6:0]$2768 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:10168$4_DATA[31:0]$2769 { \main_libresocsim_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem$ls180.v:10168$4_EN[31:0]$2770 32'11111111000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10243$8_ADDR[5:0]$2847 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10243$8_DATA[63:0]$2848 { \main_libresocsim_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem$ls180.v:10243$8_EN[63:0]$2849 64'1111111100000000000000000000000000000000000000000000000000000000 case end sync posedge \sys_clk_1 - update \memadr $0\memadr[6:0] - update $memwr$\mem$ls180.v:10162$1_ADDR $0$memwr$\mem$ls180.v:10162$1_ADDR[6:0]$2759 - update $memwr$\mem$ls180.v:10162$1_DATA $0$memwr$\mem$ls180.v:10162$1_DATA[31:0]$2760 - update $memwr$\mem$ls180.v:10162$1_EN $0$memwr$\mem$ls180.v:10162$1_EN[31:0]$2761 - update $memwr$\mem$ls180.v:10164$2_ADDR $0$memwr$\mem$ls180.v:10164$2_ADDR[6:0]$2762 - update $memwr$\mem$ls180.v:10164$2_DATA $0$memwr$\mem$ls180.v:10164$2_DATA[31:0]$2763 - update $memwr$\mem$ls180.v:10164$2_EN $0$memwr$\mem$ls180.v:10164$2_EN[31:0]$2764 - update $memwr$\mem$ls180.v:10166$3_ADDR $0$memwr$\mem$ls180.v:10166$3_ADDR[6:0]$2765 - update $memwr$\mem$ls180.v:10166$3_DATA $0$memwr$\mem$ls180.v:10166$3_DATA[31:0]$2766 - update $memwr$\mem$ls180.v:10166$3_EN $0$memwr$\mem$ls180.v:10166$3_EN[31:0]$2767 - update $memwr$\mem$ls180.v:10168$4_ADDR $0$memwr$\mem$ls180.v:10168$4_ADDR[6:0]$2768 - update $memwr$\mem$ls180.v:10168$4_DATA $0$memwr$\mem$ls180.v:10168$4_DATA[31:0]$2769 - update $memwr$\mem$ls180.v:10168$4_EN $0$memwr$\mem$ls180.v:10168$4_EN[31:0]$2770 + update \memadr $0\memadr[5:0] + update $memwr$\mem$ls180.v:10229$1_ADDR $0$memwr$\mem$ls180.v:10229$1_ADDR[5:0]$2826 + update $memwr$\mem$ls180.v:10229$1_DATA $0$memwr$\mem$ls180.v:10229$1_DATA[63:0]$2827 + update $memwr$\mem$ls180.v:10229$1_EN $0$memwr$\mem$ls180.v:10229$1_EN[63:0]$2828 + update $memwr$\mem$ls180.v:10231$2_ADDR $0$memwr$\mem$ls180.v:10231$2_ADDR[5:0]$2829 + update $memwr$\mem$ls180.v:10231$2_DATA $0$memwr$\mem$ls180.v:10231$2_DATA[63:0]$2830 + update $memwr$\mem$ls180.v:10231$2_EN $0$memwr$\mem$ls180.v:10231$2_EN[63:0]$2831 + update $memwr$\mem$ls180.v:10233$3_ADDR $0$memwr$\mem$ls180.v:10233$3_ADDR[5:0]$2832 + update $memwr$\mem$ls180.v:10233$3_DATA $0$memwr$\mem$ls180.v:10233$3_DATA[63:0]$2833 + update $memwr$\mem$ls180.v:10233$3_EN $0$memwr$\mem$ls180.v:10233$3_EN[63:0]$2834 + update $memwr$\mem$ls180.v:10235$4_ADDR $0$memwr$\mem$ls180.v:10235$4_ADDR[5:0]$2835 + update $memwr$\mem$ls180.v:10235$4_DATA $0$memwr$\mem$ls180.v:10235$4_DATA[63:0]$2836 + update $memwr$\mem$ls180.v:10235$4_EN $0$memwr$\mem$ls180.v:10235$4_EN[63:0]$2837 + update $memwr$\mem$ls180.v:10237$5_ADDR $0$memwr$\mem$ls180.v:10237$5_ADDR[5:0]$2838 + update $memwr$\mem$ls180.v:10237$5_DATA $0$memwr$\mem$ls180.v:10237$5_DATA[63:0]$2839 + update $memwr$\mem$ls180.v:10237$5_EN $0$memwr$\mem$ls180.v:10237$5_EN[63:0]$2840 + update $memwr$\mem$ls180.v:10239$6_ADDR $0$memwr$\mem$ls180.v:10239$6_ADDR[5:0]$2841 + update $memwr$\mem$ls180.v:10239$6_DATA $0$memwr$\mem$ls180.v:10239$6_DATA[63:0]$2842 + update $memwr$\mem$ls180.v:10239$6_EN $0$memwr$\mem$ls180.v:10239$6_EN[63:0]$2843 + update $memwr$\mem$ls180.v:10241$7_ADDR $0$memwr$\mem$ls180.v:10241$7_ADDR[5:0]$2844 + update $memwr$\mem$ls180.v:10241$7_DATA $0$memwr$\mem$ls180.v:10241$7_DATA[63:0]$2845 + update $memwr$\mem$ls180.v:10241$7_EN $0$memwr$\mem$ls180.v:10241$7_EN[63:0]$2846 + update $memwr$\mem$ls180.v:10243$8_ADDR $0$memwr$\mem$ls180.v:10243$8_ADDR[5:0]$2847 + update $memwr$\mem$ls180.v:10243$8_DATA $0$memwr$\mem$ls180.v:10243$8_DATA[63:0]$2848 + update $memwr$\mem$ls180.v:10243$8_EN $0$memwr$\mem$ls180.v:10243$8_EN[63:0]$2849 + end + attribute \src "ls180.v:1023.12-1023.53" + process $proc$ls180.v:1023$3390 + assign { } { } + assign $0\main_gpiotristateasic0_oe_storage[15:0] 16'0000000000000000 + sync always + update \main_gpiotristateasic0_oe_storage $0\main_gpiotristateasic0_oe_storage[15:0] + sync init end - attribute \src "ls180.v:10180.1-10190.4" - process $proc$ls180.v:10180$2772 + attribute \src "ls180.v:1024.12-1024.49" + process $proc$ls180.v:1024$3391 + assign { } { } + assign $1\main_gpiotristateasic0_status[15:0] 16'0000000000000000 + sync always + sync init + update \main_gpiotristateasic0_status $1\main_gpiotristateasic0_status[15:0] + end + attribute \src "ls180.v:1025.12-1025.54" + process $proc$ls180.v:1025$3392 + assign { } { } + assign $0\main_gpiotristateasic0_out_storage[15:0] 16'0000000000000000 + sync always + update \main_gpiotristateasic0_out_storage $0\main_gpiotristateasic0_out_storage[15:0] + sync init + end + attribute \src "ls180.v:10255.1-10273.4" + process $proc$ls180.v:10255$2851 + assign { } { } assign { } { } assign { } { } assign { } { } @@ -264116,72 +265321,155 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0$memwr$\mem_1$ls180.v:10188$8_ADDR[6:0]$2782 7'xxxxxxx - assign $0$memwr$\mem_1$ls180.v:10188$8_DATA[31:0]$2783 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_1$ls180.v:10188$8_EN[31:0]$2784 0 - assign $0$memwr$\mem_1$ls180.v:10186$7_ADDR[6:0]$2779 7'xxxxxxx - assign $0$memwr$\mem_1$ls180.v:10186$7_DATA[31:0]$2780 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_1$ls180.v:10186$7_EN[31:0]$2781 0 - assign $0$memwr$\mem_1$ls180.v:10184$6_ADDR[6:0]$2776 7'xxxxxxx - assign $0$memwr$\mem_1$ls180.v:10184$6_DATA[31:0]$2777 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_1$ls180.v:10184$6_EN[31:0]$2778 0 - assign $0$memwr$\mem_1$ls180.v:10182$5_ADDR[6:0]$2773 7'xxxxxxx - assign $0$memwr$\mem_1$ls180.v:10182$5_DATA[31:0]$2774 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_1$ls180.v:10182$5_EN[31:0]$2775 0 - assign $0\memadr_1[6:0] \main_sram0_adr - attribute \src "ls180.v:10181.2-10182.55" + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\mem_1$ls180.v:10271$16_ADDR[5:0]$2873 6'xxxxxx + assign $0$memwr$\mem_1$ls180.v:10271$16_DATA[63:0]$2874 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10271$16_EN[63:0]$2875 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10269$15_ADDR[5:0]$2870 6'xxxxxx + assign $0$memwr$\mem_1$ls180.v:10269$15_DATA[63:0]$2871 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10269$15_EN[63:0]$2872 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10267$14_ADDR[5:0]$2867 6'xxxxxx + assign $0$memwr$\mem_1$ls180.v:10267$14_DATA[63:0]$2868 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10267$14_EN[63:0]$2869 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10265$13_ADDR[5:0]$2864 6'xxxxxx + assign $0$memwr$\mem_1$ls180.v:10265$13_DATA[63:0]$2865 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10265$13_EN[63:0]$2866 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10263$12_ADDR[5:0]$2861 6'xxxxxx + assign $0$memwr$\mem_1$ls180.v:10263$12_DATA[63:0]$2862 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10263$12_EN[63:0]$2863 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10261$11_ADDR[5:0]$2858 6'xxxxxx + assign $0$memwr$\mem_1$ls180.v:10261$11_DATA[63:0]$2859 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10261$11_EN[63:0]$2860 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10259$10_ADDR[5:0]$2855 6'xxxxxx + assign $0$memwr$\mem_1$ls180.v:10259$10_DATA[63:0]$2856 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10259$10_EN[63:0]$2857 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10257$9_ADDR[5:0]$2852 6'xxxxxx + assign $0$memwr$\mem_1$ls180.v:10257$9_DATA[63:0]$2853 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10257$9_EN[63:0]$2854 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\memadr_1[5:0] \main_sram0_adr + attribute \src "ls180.v:10256.2-10257.55" switch \main_sram0_we [0] - attribute \src "ls180.v:10181.6-10181.22" + attribute \src "ls180.v:10256.6-10256.22" case 1'1 - assign $0$memwr$\mem_1$ls180.v:10182$5_ADDR[6:0]$2773 \main_sram0_adr - assign $0$memwr$\mem_1$ls180.v:10182$5_DATA[31:0]$2774 { 24'000000000000000000000000 \main_sram0_dat_w [7:0] } - assign $0$memwr$\mem_1$ls180.v:10182$5_EN[31:0]$2775 255 + assign $0$memwr$\mem_1$ls180.v:10257$9_ADDR[5:0]$2852 \main_sram0_adr + assign $0$memwr$\mem_1$ls180.v:10257$9_DATA[63:0]$2853 { 56'00000000000000000000000000000000000000000000000000000000 \main_sram0_dat_w [7:0] } + assign $0$memwr$\mem_1$ls180.v:10257$9_EN[63:0]$2854 64'0000000000000000000000000000000000000000000000000000000011111111 case end - attribute \src "ls180.v:10183.2-10184.57" + attribute \src "ls180.v:10258.2-10259.57" switch \main_sram0_we [1] - attribute \src "ls180.v:10183.6-10183.22" + attribute \src "ls180.v:10258.6-10258.22" case 1'1 - assign $0$memwr$\mem_1$ls180.v:10184$6_ADDR[6:0]$2776 \main_sram0_adr - assign $0$memwr$\mem_1$ls180.v:10184$6_DATA[31:0]$2777 { 16'0000000000000000 \main_sram0_dat_w [15:8] 8'xxxxxxxx } - assign $0$memwr$\mem_1$ls180.v:10184$6_EN[31:0]$2778 65280 + assign $0$memwr$\mem_1$ls180.v:10259$10_ADDR[5:0]$2855 \main_sram0_adr + assign $0$memwr$\mem_1$ls180.v:10259$10_DATA[63:0]$2856 { 48'000000000000000000000000000000000000000000000000 \main_sram0_dat_w [15:8] 8'xxxxxxxx } + assign $0$memwr$\mem_1$ls180.v:10259$10_EN[63:0]$2857 64'0000000000000000000000000000000000000000000000001111111100000000 case end - attribute \src "ls180.v:10185.2-10186.59" + attribute \src "ls180.v:10260.2-10261.59" switch \main_sram0_we [2] - attribute \src "ls180.v:10185.6-10185.22" + attribute \src "ls180.v:10260.6-10260.22" case 1'1 - assign $0$memwr$\mem_1$ls180.v:10186$7_ADDR[6:0]$2779 \main_sram0_adr - assign $0$memwr$\mem_1$ls180.v:10186$7_DATA[31:0]$2780 { 8'00000000 \main_sram0_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_1$ls180.v:10186$7_EN[31:0]$2781 16711680 + assign $0$memwr$\mem_1$ls180.v:10261$11_ADDR[5:0]$2858 \main_sram0_adr + assign $0$memwr$\mem_1$ls180.v:10261$11_DATA[63:0]$2859 { 40'0000000000000000000000000000000000000000 \main_sram0_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_1$ls180.v:10261$11_EN[63:0]$2860 64'0000000000000000000000000000000000000000111111110000000000000000 case end - attribute \src "ls180.v:10187.2-10188.59" + attribute \src "ls180.v:10262.2-10263.59" switch \main_sram0_we [3] - attribute \src "ls180.v:10187.6-10187.22" + attribute \src "ls180.v:10262.6-10262.22" + case 1'1 + assign $0$memwr$\mem_1$ls180.v:10263$12_ADDR[5:0]$2861 \main_sram0_adr + assign $0$memwr$\mem_1$ls180.v:10263$12_DATA[63:0]$2862 { 32'00000000000000000000000000000000 \main_sram0_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_1$ls180.v:10263$12_EN[63:0]$2863 64'0000000000000000000000000000000011111111000000000000000000000000 + case + end + attribute \src "ls180.v:10264.2-10265.59" + switch \main_sram0_we [4] + attribute \src "ls180.v:10264.6-10264.22" + case 1'1 + assign $0$memwr$\mem_1$ls180.v:10265$13_ADDR[5:0]$2864 \main_sram0_adr + assign $0$memwr$\mem_1$ls180.v:10265$13_DATA[63:0]$2865 { 24'000000000000000000000000 \main_sram0_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_1$ls180.v:10265$13_EN[63:0]$2866 64'0000000000000000000000001111111100000000000000000000000000000000 + case + end + attribute \src "ls180.v:10266.2-10267.59" + switch \main_sram0_we [5] + attribute \src "ls180.v:10266.6-10266.22" case 1'1 - assign $0$memwr$\mem_1$ls180.v:10188$8_ADDR[6:0]$2782 \main_sram0_adr - assign $0$memwr$\mem_1$ls180.v:10188$8_DATA[31:0]$2783 { \main_sram0_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_1$ls180.v:10188$8_EN[31:0]$2784 32'11111111000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10267$14_ADDR[5:0]$2867 \main_sram0_adr + assign $0$memwr$\mem_1$ls180.v:10267$14_DATA[63:0]$2868 { 16'0000000000000000 \main_sram0_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_1$ls180.v:10267$14_EN[63:0]$2869 64'0000000000000000111111110000000000000000000000000000000000000000 + case + end + attribute \src "ls180.v:10268.2-10269.59" + switch \main_sram0_we [6] + attribute \src "ls180.v:10268.6-10268.22" + case 1'1 + assign $0$memwr$\mem_1$ls180.v:10269$15_ADDR[5:0]$2870 \main_sram0_adr + assign $0$memwr$\mem_1$ls180.v:10269$15_DATA[63:0]$2871 { 8'00000000 \main_sram0_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_1$ls180.v:10269$15_EN[63:0]$2872 64'0000000011111111000000000000000000000000000000000000000000000000 + case + end + attribute \src "ls180.v:10270.2-10271.59" + switch \main_sram0_we [7] + attribute \src "ls180.v:10270.6-10270.22" + case 1'1 + assign $0$memwr$\mem_1$ls180.v:10271$16_ADDR[5:0]$2873 \main_sram0_adr + assign $0$memwr$\mem_1$ls180.v:10271$16_DATA[63:0]$2874 { \main_sram0_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_1$ls180.v:10271$16_EN[63:0]$2875 64'1111111100000000000000000000000000000000000000000000000000000000 case end sync posedge \sys_clk_1 - update \memadr_1 $0\memadr_1[6:0] - update $memwr$\mem_1$ls180.v:10182$5_ADDR $0$memwr$\mem_1$ls180.v:10182$5_ADDR[6:0]$2773 - update $memwr$\mem_1$ls180.v:10182$5_DATA $0$memwr$\mem_1$ls180.v:10182$5_DATA[31:0]$2774 - update $memwr$\mem_1$ls180.v:10182$5_EN $0$memwr$\mem_1$ls180.v:10182$5_EN[31:0]$2775 - update $memwr$\mem_1$ls180.v:10184$6_ADDR $0$memwr$\mem_1$ls180.v:10184$6_ADDR[6:0]$2776 - update $memwr$\mem_1$ls180.v:10184$6_DATA $0$memwr$\mem_1$ls180.v:10184$6_DATA[31:0]$2777 - update $memwr$\mem_1$ls180.v:10184$6_EN $0$memwr$\mem_1$ls180.v:10184$6_EN[31:0]$2778 - update $memwr$\mem_1$ls180.v:10186$7_ADDR $0$memwr$\mem_1$ls180.v:10186$7_ADDR[6:0]$2779 - update $memwr$\mem_1$ls180.v:10186$7_DATA $0$memwr$\mem_1$ls180.v:10186$7_DATA[31:0]$2780 - update $memwr$\mem_1$ls180.v:10186$7_EN $0$memwr$\mem_1$ls180.v:10186$7_EN[31:0]$2781 - update $memwr$\mem_1$ls180.v:10188$8_ADDR $0$memwr$\mem_1$ls180.v:10188$8_ADDR[6:0]$2782 - update $memwr$\mem_1$ls180.v:10188$8_DATA $0$memwr$\mem_1$ls180.v:10188$8_DATA[31:0]$2783 - update $memwr$\mem_1$ls180.v:10188$8_EN $0$memwr$\mem_1$ls180.v:10188$8_EN[31:0]$2784 + update \memadr_1 $0\memadr_1[5:0] + update $memwr$\mem_1$ls180.v:10257$9_ADDR $0$memwr$\mem_1$ls180.v:10257$9_ADDR[5:0]$2852 + update $memwr$\mem_1$ls180.v:10257$9_DATA $0$memwr$\mem_1$ls180.v:10257$9_DATA[63:0]$2853 + update $memwr$\mem_1$ls180.v:10257$9_EN $0$memwr$\mem_1$ls180.v:10257$9_EN[63:0]$2854 + update $memwr$\mem_1$ls180.v:10259$10_ADDR $0$memwr$\mem_1$ls180.v:10259$10_ADDR[5:0]$2855 + update $memwr$\mem_1$ls180.v:10259$10_DATA $0$memwr$\mem_1$ls180.v:10259$10_DATA[63:0]$2856 + update $memwr$\mem_1$ls180.v:10259$10_EN $0$memwr$\mem_1$ls180.v:10259$10_EN[63:0]$2857 + update $memwr$\mem_1$ls180.v:10261$11_ADDR $0$memwr$\mem_1$ls180.v:10261$11_ADDR[5:0]$2858 + update $memwr$\mem_1$ls180.v:10261$11_DATA $0$memwr$\mem_1$ls180.v:10261$11_DATA[63:0]$2859 + update $memwr$\mem_1$ls180.v:10261$11_EN $0$memwr$\mem_1$ls180.v:10261$11_EN[63:0]$2860 + update $memwr$\mem_1$ls180.v:10263$12_ADDR $0$memwr$\mem_1$ls180.v:10263$12_ADDR[5:0]$2861 + update $memwr$\mem_1$ls180.v:10263$12_DATA $0$memwr$\mem_1$ls180.v:10263$12_DATA[63:0]$2862 + update $memwr$\mem_1$ls180.v:10263$12_EN $0$memwr$\mem_1$ls180.v:10263$12_EN[63:0]$2863 + update $memwr$\mem_1$ls180.v:10265$13_ADDR $0$memwr$\mem_1$ls180.v:10265$13_ADDR[5:0]$2864 + update $memwr$\mem_1$ls180.v:10265$13_DATA $0$memwr$\mem_1$ls180.v:10265$13_DATA[63:0]$2865 + update $memwr$\mem_1$ls180.v:10265$13_EN $0$memwr$\mem_1$ls180.v:10265$13_EN[63:0]$2866 + update $memwr$\mem_1$ls180.v:10267$14_ADDR $0$memwr$\mem_1$ls180.v:10267$14_ADDR[5:0]$2867 + update $memwr$\mem_1$ls180.v:10267$14_DATA $0$memwr$\mem_1$ls180.v:10267$14_DATA[63:0]$2868 + update $memwr$\mem_1$ls180.v:10267$14_EN $0$memwr$\mem_1$ls180.v:10267$14_EN[63:0]$2869 + update $memwr$\mem_1$ls180.v:10269$15_ADDR $0$memwr$\mem_1$ls180.v:10269$15_ADDR[5:0]$2870 + update $memwr$\mem_1$ls180.v:10269$15_DATA $0$memwr$\mem_1$ls180.v:10269$15_DATA[63:0]$2871 + update $memwr$\mem_1$ls180.v:10269$15_EN $0$memwr$\mem_1$ls180.v:10269$15_EN[63:0]$2872 + update $memwr$\mem_1$ls180.v:10271$16_ADDR $0$memwr$\mem_1$ls180.v:10271$16_ADDR[5:0]$2873 + update $memwr$\mem_1$ls180.v:10271$16_DATA $0$memwr$\mem_1$ls180.v:10271$16_DATA[63:0]$2874 + update $memwr$\mem_1$ls180.v:10271$16_EN $0$memwr$\mem_1$ls180.v:10271$16_EN[63:0]$2875 end - attribute \src "ls180.v:10200.1-10210.4" - process $proc$ls180.v:10200$2786 + attribute \src "ls180.v:10283.1-10301.4" + process $proc$ls180.v:10283$2877 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } assign { } { } assign { } { } assign { } { } @@ -264195,72 +265483,167 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0$memwr$\mem_2$ls180.v:10208$12_ADDR[6:0]$2796 7'xxxxxxx - assign $0$memwr$\mem_2$ls180.v:10208$12_DATA[31:0]$2797 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_2$ls180.v:10208$12_EN[31:0]$2798 0 - assign $0$memwr$\mem_2$ls180.v:10206$11_ADDR[6:0]$2793 7'xxxxxxx - assign $0$memwr$\mem_2$ls180.v:10206$11_DATA[31:0]$2794 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_2$ls180.v:10206$11_EN[31:0]$2795 0 - assign $0$memwr$\mem_2$ls180.v:10204$10_ADDR[6:0]$2790 7'xxxxxxx - assign $0$memwr$\mem_2$ls180.v:10204$10_DATA[31:0]$2791 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_2$ls180.v:10204$10_EN[31:0]$2792 0 - assign $0$memwr$\mem_2$ls180.v:10202$9_ADDR[6:0]$2787 7'xxxxxxx - assign $0$memwr$\mem_2$ls180.v:10202$9_DATA[31:0]$2788 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_2$ls180.v:10202$9_EN[31:0]$2789 0 - assign $0\memadr_2[6:0] \main_sram1_adr - attribute \src "ls180.v:10201.2-10202.55" + assign $0$memwr$\mem_2$ls180.v:10299$24_ADDR[5:0]$2899 6'xxxxxx + assign $0$memwr$\mem_2$ls180.v:10299$24_DATA[63:0]$2900 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_2$ls180.v:10299$24_EN[63:0]$2901 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_2$ls180.v:10297$23_ADDR[5:0]$2896 6'xxxxxx + assign $0$memwr$\mem_2$ls180.v:10297$23_DATA[63:0]$2897 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_2$ls180.v:10297$23_EN[63:0]$2898 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_2$ls180.v:10295$22_ADDR[5:0]$2893 6'xxxxxx + assign $0$memwr$\mem_2$ls180.v:10295$22_DATA[63:0]$2894 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_2$ls180.v:10295$22_EN[63:0]$2895 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_2$ls180.v:10293$21_ADDR[5:0]$2890 6'xxxxxx + assign $0$memwr$\mem_2$ls180.v:10293$21_DATA[63:0]$2891 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_2$ls180.v:10293$21_EN[63:0]$2892 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_2$ls180.v:10291$20_ADDR[5:0]$2887 6'xxxxxx + assign $0$memwr$\mem_2$ls180.v:10291$20_DATA[63:0]$2888 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_2$ls180.v:10291$20_EN[63:0]$2889 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_2$ls180.v:10289$19_ADDR[5:0]$2884 6'xxxxxx + assign $0$memwr$\mem_2$ls180.v:10289$19_DATA[63:0]$2885 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_2$ls180.v:10289$19_EN[63:0]$2886 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_2$ls180.v:10287$18_ADDR[5:0]$2881 6'xxxxxx + assign $0$memwr$\mem_2$ls180.v:10287$18_DATA[63:0]$2882 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_2$ls180.v:10287$18_EN[63:0]$2883 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_2$ls180.v:10285$17_ADDR[5:0]$2878 6'xxxxxx + assign $0$memwr$\mem_2$ls180.v:10285$17_DATA[63:0]$2879 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_2$ls180.v:10285$17_EN[63:0]$2880 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\memadr_2[5:0] \main_sram1_adr + attribute \src "ls180.v:10284.2-10285.55" switch \main_sram1_we [0] - attribute \src "ls180.v:10201.6-10201.22" + attribute \src "ls180.v:10284.6-10284.22" case 1'1 - assign $0$memwr$\mem_2$ls180.v:10202$9_ADDR[6:0]$2787 \main_sram1_adr - assign $0$memwr$\mem_2$ls180.v:10202$9_DATA[31:0]$2788 { 24'000000000000000000000000 \main_sram1_dat_w [7:0] } - assign $0$memwr$\mem_2$ls180.v:10202$9_EN[31:0]$2789 255 + assign $0$memwr$\mem_2$ls180.v:10285$17_ADDR[5:0]$2878 \main_sram1_adr + assign $0$memwr$\mem_2$ls180.v:10285$17_DATA[63:0]$2879 { 56'00000000000000000000000000000000000000000000000000000000 \main_sram1_dat_w [7:0] } + assign $0$memwr$\mem_2$ls180.v:10285$17_EN[63:0]$2880 64'0000000000000000000000000000000000000000000000000000000011111111 case end - attribute \src "ls180.v:10203.2-10204.57" + attribute \src "ls180.v:10286.2-10287.57" switch \main_sram1_we [1] - attribute \src "ls180.v:10203.6-10203.22" + attribute \src "ls180.v:10286.6-10286.22" case 1'1 - assign $0$memwr$\mem_2$ls180.v:10204$10_ADDR[6:0]$2790 \main_sram1_adr - assign $0$memwr$\mem_2$ls180.v:10204$10_DATA[31:0]$2791 { 16'0000000000000000 \main_sram1_dat_w [15:8] 8'xxxxxxxx } - assign $0$memwr$\mem_2$ls180.v:10204$10_EN[31:0]$2792 65280 + assign $0$memwr$\mem_2$ls180.v:10287$18_ADDR[5:0]$2881 \main_sram1_adr + assign $0$memwr$\mem_2$ls180.v:10287$18_DATA[63:0]$2882 { 48'000000000000000000000000000000000000000000000000 \main_sram1_dat_w [15:8] 8'xxxxxxxx } + assign $0$memwr$\mem_2$ls180.v:10287$18_EN[63:0]$2883 64'0000000000000000000000000000000000000000000000001111111100000000 case end - attribute \src "ls180.v:10205.2-10206.59" + attribute \src "ls180.v:10288.2-10289.59" switch \main_sram1_we [2] - attribute \src "ls180.v:10205.6-10205.22" + attribute \src "ls180.v:10288.6-10288.22" case 1'1 - assign $0$memwr$\mem_2$ls180.v:10206$11_ADDR[6:0]$2793 \main_sram1_adr - assign $0$memwr$\mem_2$ls180.v:10206$11_DATA[31:0]$2794 { 8'00000000 \main_sram1_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_2$ls180.v:10206$11_EN[31:0]$2795 16711680 + assign $0$memwr$\mem_2$ls180.v:10289$19_ADDR[5:0]$2884 \main_sram1_adr + assign $0$memwr$\mem_2$ls180.v:10289$19_DATA[63:0]$2885 { 40'0000000000000000000000000000000000000000 \main_sram1_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_2$ls180.v:10289$19_EN[63:0]$2886 64'0000000000000000000000000000000000000000111111110000000000000000 case end - attribute \src "ls180.v:10207.2-10208.59" + attribute \src "ls180.v:10290.2-10291.59" switch \main_sram1_we [3] - attribute \src "ls180.v:10207.6-10207.22" + attribute \src "ls180.v:10290.6-10290.22" case 1'1 - assign $0$memwr$\mem_2$ls180.v:10208$12_ADDR[6:0]$2796 \main_sram1_adr - assign $0$memwr$\mem_2$ls180.v:10208$12_DATA[31:0]$2797 { \main_sram1_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_2$ls180.v:10208$12_EN[31:0]$2798 32'11111111000000000000000000000000 + assign $0$memwr$\mem_2$ls180.v:10291$20_ADDR[5:0]$2887 \main_sram1_adr + assign $0$memwr$\mem_2$ls180.v:10291$20_DATA[63:0]$2888 { 32'00000000000000000000000000000000 \main_sram1_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_2$ls180.v:10291$20_EN[63:0]$2889 64'0000000000000000000000000000000011111111000000000000000000000000 + case + end + attribute \src "ls180.v:10292.2-10293.59" + switch \main_sram1_we [4] + attribute \src "ls180.v:10292.6-10292.22" + case 1'1 + assign $0$memwr$\mem_2$ls180.v:10293$21_ADDR[5:0]$2890 \main_sram1_adr + assign $0$memwr$\mem_2$ls180.v:10293$21_DATA[63:0]$2891 { 24'000000000000000000000000 \main_sram1_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_2$ls180.v:10293$21_EN[63:0]$2892 64'0000000000000000000000001111111100000000000000000000000000000000 + case + end + attribute \src "ls180.v:10294.2-10295.59" + switch \main_sram1_we [5] + attribute \src "ls180.v:10294.6-10294.22" + case 1'1 + assign $0$memwr$\mem_2$ls180.v:10295$22_ADDR[5:0]$2893 \main_sram1_adr + assign $0$memwr$\mem_2$ls180.v:10295$22_DATA[63:0]$2894 { 16'0000000000000000 \main_sram1_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_2$ls180.v:10295$22_EN[63:0]$2895 64'0000000000000000111111110000000000000000000000000000000000000000 + case + end + attribute \src "ls180.v:10296.2-10297.59" + switch \main_sram1_we [6] + attribute \src "ls180.v:10296.6-10296.22" + case 1'1 + assign $0$memwr$\mem_2$ls180.v:10297$23_ADDR[5:0]$2896 \main_sram1_adr + assign $0$memwr$\mem_2$ls180.v:10297$23_DATA[63:0]$2897 { 8'00000000 \main_sram1_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_2$ls180.v:10297$23_EN[63:0]$2898 64'0000000011111111000000000000000000000000000000000000000000000000 + case + end + attribute \src "ls180.v:10298.2-10299.59" + switch \main_sram1_we [7] + attribute \src "ls180.v:10298.6-10298.22" + case 1'1 + assign $0$memwr$\mem_2$ls180.v:10299$24_ADDR[5:0]$2899 \main_sram1_adr + assign $0$memwr$\mem_2$ls180.v:10299$24_DATA[63:0]$2900 { \main_sram1_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_2$ls180.v:10299$24_EN[63:0]$2901 64'1111111100000000000000000000000000000000000000000000000000000000 case end sync posedge \sys_clk_1 - update \memadr_2 $0\memadr_2[6:0] - update $memwr$\mem_2$ls180.v:10202$9_ADDR $0$memwr$\mem_2$ls180.v:10202$9_ADDR[6:0]$2787 - update $memwr$\mem_2$ls180.v:10202$9_DATA $0$memwr$\mem_2$ls180.v:10202$9_DATA[31:0]$2788 - update $memwr$\mem_2$ls180.v:10202$9_EN $0$memwr$\mem_2$ls180.v:10202$9_EN[31:0]$2789 - update $memwr$\mem_2$ls180.v:10204$10_ADDR $0$memwr$\mem_2$ls180.v:10204$10_ADDR[6:0]$2790 - update $memwr$\mem_2$ls180.v:10204$10_DATA $0$memwr$\mem_2$ls180.v:10204$10_DATA[31:0]$2791 - update $memwr$\mem_2$ls180.v:10204$10_EN $0$memwr$\mem_2$ls180.v:10204$10_EN[31:0]$2792 - update $memwr$\mem_2$ls180.v:10206$11_ADDR $0$memwr$\mem_2$ls180.v:10206$11_ADDR[6:0]$2793 - update $memwr$\mem_2$ls180.v:10206$11_DATA $0$memwr$\mem_2$ls180.v:10206$11_DATA[31:0]$2794 - update $memwr$\mem_2$ls180.v:10206$11_EN $0$memwr$\mem_2$ls180.v:10206$11_EN[31:0]$2795 - update $memwr$\mem_2$ls180.v:10208$12_ADDR $0$memwr$\mem_2$ls180.v:10208$12_ADDR[6:0]$2796 - update $memwr$\mem_2$ls180.v:10208$12_DATA $0$memwr$\mem_2$ls180.v:10208$12_DATA[31:0]$2797 - update $memwr$\mem_2$ls180.v:10208$12_EN $0$memwr$\mem_2$ls180.v:10208$12_EN[31:0]$2798 + update \memadr_2 $0\memadr_2[5:0] + update $memwr$\mem_2$ls180.v:10285$17_ADDR $0$memwr$\mem_2$ls180.v:10285$17_ADDR[5:0]$2878 + update $memwr$\mem_2$ls180.v:10285$17_DATA $0$memwr$\mem_2$ls180.v:10285$17_DATA[63:0]$2879 + update $memwr$\mem_2$ls180.v:10285$17_EN $0$memwr$\mem_2$ls180.v:10285$17_EN[63:0]$2880 + update $memwr$\mem_2$ls180.v:10287$18_ADDR $0$memwr$\mem_2$ls180.v:10287$18_ADDR[5:0]$2881 + update $memwr$\mem_2$ls180.v:10287$18_DATA $0$memwr$\mem_2$ls180.v:10287$18_DATA[63:0]$2882 + update $memwr$\mem_2$ls180.v:10287$18_EN $0$memwr$\mem_2$ls180.v:10287$18_EN[63:0]$2883 + update $memwr$\mem_2$ls180.v:10289$19_ADDR $0$memwr$\mem_2$ls180.v:10289$19_ADDR[5:0]$2884 + update $memwr$\mem_2$ls180.v:10289$19_DATA $0$memwr$\mem_2$ls180.v:10289$19_DATA[63:0]$2885 + update $memwr$\mem_2$ls180.v:10289$19_EN $0$memwr$\mem_2$ls180.v:10289$19_EN[63:0]$2886 + update $memwr$\mem_2$ls180.v:10291$20_ADDR $0$memwr$\mem_2$ls180.v:10291$20_ADDR[5:0]$2887 + update $memwr$\mem_2$ls180.v:10291$20_DATA $0$memwr$\mem_2$ls180.v:10291$20_DATA[63:0]$2888 + update $memwr$\mem_2$ls180.v:10291$20_EN $0$memwr$\mem_2$ls180.v:10291$20_EN[63:0]$2889 + update $memwr$\mem_2$ls180.v:10293$21_ADDR $0$memwr$\mem_2$ls180.v:10293$21_ADDR[5:0]$2890 + update $memwr$\mem_2$ls180.v:10293$21_DATA $0$memwr$\mem_2$ls180.v:10293$21_DATA[63:0]$2891 + update $memwr$\mem_2$ls180.v:10293$21_EN $0$memwr$\mem_2$ls180.v:10293$21_EN[63:0]$2892 + update $memwr$\mem_2$ls180.v:10295$22_ADDR $0$memwr$\mem_2$ls180.v:10295$22_ADDR[5:0]$2893 + update $memwr$\mem_2$ls180.v:10295$22_DATA $0$memwr$\mem_2$ls180.v:10295$22_DATA[63:0]$2894 + update $memwr$\mem_2$ls180.v:10295$22_EN $0$memwr$\mem_2$ls180.v:10295$22_EN[63:0]$2895 + update $memwr$\mem_2$ls180.v:10297$23_ADDR $0$memwr$\mem_2$ls180.v:10297$23_ADDR[5:0]$2896 + update $memwr$\mem_2$ls180.v:10297$23_DATA $0$memwr$\mem_2$ls180.v:10297$23_DATA[63:0]$2897 + update $memwr$\mem_2$ls180.v:10297$23_EN $0$memwr$\mem_2$ls180.v:10297$23_EN[63:0]$2898 + update $memwr$\mem_2$ls180.v:10299$24_ADDR $0$memwr$\mem_2$ls180.v:10299$24_ADDR[5:0]$2899 + update $memwr$\mem_2$ls180.v:10299$24_DATA $0$memwr$\mem_2$ls180.v:10299$24_DATA[63:0]$2900 + update $memwr$\mem_2$ls180.v:10299$24_EN $0$memwr$\mem_2$ls180.v:10299$24_EN[63:0]$2901 + end + attribute \src "ls180.v:1029.12-1029.53" + process $proc$ls180.v:1029$3393 + assign { } { } + assign $1\main_gpiotristateasic1_oe_storage[15:0] 16'0000000000000000 + sync always + sync init + update \main_gpiotristateasic1_oe_storage $1\main_gpiotristateasic1_oe_storage[15:0] + end + attribute \src "ls180.v:1030.5-1030.40" + process $proc$ls180.v:1030$3394 + assign { } { } + assign $1\main_gpiotristateasic1_oe_re[0:0] 1'0 + sync always + sync init + update \main_gpiotristateasic1_oe_re $1\main_gpiotristateasic1_oe_re[0:0] end - attribute \src "ls180.v:10220.1-10230.4" - process $proc$ls180.v:10220$2800 + attribute \src "ls180.v:1031.12-1031.49" + process $proc$ls180.v:1031$3395 + assign { } { } + assign $1\main_gpiotristateasic1_status[15:0] 16'0000000000000000 + sync always + sync init + update \main_gpiotristateasic1_status $1\main_gpiotristateasic1_status[15:0] + end + attribute \src "ls180.v:10311.1-10329.4" + process $proc$ls180.v:10311$2903 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } assign { } { } assign { } { } assign { } { } @@ -264274,5466 +265657,5407 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0$memwr$\mem_3$ls180.v:10228$16_ADDR[6:0]$2810 7'xxxxxxx - assign $0$memwr$\mem_3$ls180.v:10228$16_DATA[31:0]$2811 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_3$ls180.v:10228$16_EN[31:0]$2812 0 - assign $0$memwr$\mem_3$ls180.v:10226$15_ADDR[6:0]$2807 7'xxxxxxx - assign $0$memwr$\mem_3$ls180.v:10226$15_DATA[31:0]$2808 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_3$ls180.v:10226$15_EN[31:0]$2809 0 - assign $0$memwr$\mem_3$ls180.v:10224$14_ADDR[6:0]$2804 7'xxxxxxx - assign $0$memwr$\mem_3$ls180.v:10224$14_DATA[31:0]$2805 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_3$ls180.v:10224$14_EN[31:0]$2806 0 - assign $0$memwr$\mem_3$ls180.v:10222$13_ADDR[6:0]$2801 7'xxxxxxx - assign $0$memwr$\mem_3$ls180.v:10222$13_DATA[31:0]$2802 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_3$ls180.v:10222$13_EN[31:0]$2803 0 - assign $0\memadr_3[6:0] \main_sram2_adr - attribute \src "ls180.v:10221.2-10222.55" + assign { } { } + assign $0$memwr$\mem_3$ls180.v:10327$32_ADDR[5:0]$2925 6'xxxxxx + assign $0$memwr$\mem_3$ls180.v:10327$32_DATA[63:0]$2926 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_3$ls180.v:10327$32_EN[63:0]$2927 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_3$ls180.v:10325$31_ADDR[5:0]$2922 6'xxxxxx + assign $0$memwr$\mem_3$ls180.v:10325$31_DATA[63:0]$2923 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_3$ls180.v:10325$31_EN[63:0]$2924 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_3$ls180.v:10323$30_ADDR[5:0]$2919 6'xxxxxx + assign $0$memwr$\mem_3$ls180.v:10323$30_DATA[63:0]$2920 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_3$ls180.v:10323$30_EN[63:0]$2921 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_3$ls180.v:10321$29_ADDR[5:0]$2916 6'xxxxxx + assign $0$memwr$\mem_3$ls180.v:10321$29_DATA[63:0]$2917 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_3$ls180.v:10321$29_EN[63:0]$2918 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_3$ls180.v:10319$28_ADDR[5:0]$2913 6'xxxxxx + assign $0$memwr$\mem_3$ls180.v:10319$28_DATA[63:0]$2914 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_3$ls180.v:10319$28_EN[63:0]$2915 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_3$ls180.v:10317$27_ADDR[5:0]$2910 6'xxxxxx + assign $0$memwr$\mem_3$ls180.v:10317$27_DATA[63:0]$2911 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_3$ls180.v:10317$27_EN[63:0]$2912 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_3$ls180.v:10315$26_ADDR[5:0]$2907 6'xxxxxx + assign $0$memwr$\mem_3$ls180.v:10315$26_DATA[63:0]$2908 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_3$ls180.v:10315$26_EN[63:0]$2909 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_3$ls180.v:10313$25_ADDR[5:0]$2904 6'xxxxxx + assign $0$memwr$\mem_3$ls180.v:10313$25_DATA[63:0]$2905 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_3$ls180.v:10313$25_EN[63:0]$2906 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\memadr_3[5:0] \main_sram2_adr + attribute \src "ls180.v:10312.2-10313.55" switch \main_sram2_we [0] - attribute \src "ls180.v:10221.6-10221.22" + attribute \src "ls180.v:10312.6-10312.22" case 1'1 - assign $0$memwr$\mem_3$ls180.v:10222$13_ADDR[6:0]$2801 \main_sram2_adr - assign $0$memwr$\mem_3$ls180.v:10222$13_DATA[31:0]$2802 { 24'000000000000000000000000 \main_sram2_dat_w [7:0] } - assign $0$memwr$\mem_3$ls180.v:10222$13_EN[31:0]$2803 255 + assign $0$memwr$\mem_3$ls180.v:10313$25_ADDR[5:0]$2904 \main_sram2_adr + assign $0$memwr$\mem_3$ls180.v:10313$25_DATA[63:0]$2905 { 56'00000000000000000000000000000000000000000000000000000000 \main_sram2_dat_w [7:0] } + assign $0$memwr$\mem_3$ls180.v:10313$25_EN[63:0]$2906 64'0000000000000000000000000000000000000000000000000000000011111111 case end - attribute \src "ls180.v:10223.2-10224.57" + attribute \src "ls180.v:10314.2-10315.57" switch \main_sram2_we [1] - attribute \src "ls180.v:10223.6-10223.22" + attribute \src "ls180.v:10314.6-10314.22" case 1'1 - assign $0$memwr$\mem_3$ls180.v:10224$14_ADDR[6:0]$2804 \main_sram2_adr - assign $0$memwr$\mem_3$ls180.v:10224$14_DATA[31:0]$2805 { 16'0000000000000000 \main_sram2_dat_w [15:8] 8'xxxxxxxx } - assign $0$memwr$\mem_3$ls180.v:10224$14_EN[31:0]$2806 65280 + assign $0$memwr$\mem_3$ls180.v:10315$26_ADDR[5:0]$2907 \main_sram2_adr + assign $0$memwr$\mem_3$ls180.v:10315$26_DATA[63:0]$2908 { 48'000000000000000000000000000000000000000000000000 \main_sram2_dat_w [15:8] 8'xxxxxxxx } + assign $0$memwr$\mem_3$ls180.v:10315$26_EN[63:0]$2909 64'0000000000000000000000000000000000000000000000001111111100000000 case end - attribute \src "ls180.v:10225.2-10226.59" + attribute \src "ls180.v:10316.2-10317.59" switch \main_sram2_we [2] - attribute \src "ls180.v:10225.6-10225.22" + attribute \src "ls180.v:10316.6-10316.22" case 1'1 - assign $0$memwr$\mem_3$ls180.v:10226$15_ADDR[6:0]$2807 \main_sram2_adr - assign $0$memwr$\mem_3$ls180.v:10226$15_DATA[31:0]$2808 { 8'00000000 \main_sram2_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_3$ls180.v:10226$15_EN[31:0]$2809 16711680 + assign $0$memwr$\mem_3$ls180.v:10317$27_ADDR[5:0]$2910 \main_sram2_adr + assign $0$memwr$\mem_3$ls180.v:10317$27_DATA[63:0]$2911 { 40'0000000000000000000000000000000000000000 \main_sram2_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_3$ls180.v:10317$27_EN[63:0]$2912 64'0000000000000000000000000000000000000000111111110000000000000000 case end - attribute \src "ls180.v:10227.2-10228.59" + attribute \src "ls180.v:10318.2-10319.59" switch \main_sram2_we [3] - attribute \src "ls180.v:10227.6-10227.22" + attribute \src "ls180.v:10318.6-10318.22" case 1'1 - assign $0$memwr$\mem_3$ls180.v:10228$16_ADDR[6:0]$2810 \main_sram2_adr - assign $0$memwr$\mem_3$ls180.v:10228$16_DATA[31:0]$2811 { \main_sram2_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_3$ls180.v:10228$16_EN[31:0]$2812 32'11111111000000000000000000000000 + assign $0$memwr$\mem_3$ls180.v:10319$28_ADDR[5:0]$2913 \main_sram2_adr + assign $0$memwr$\mem_3$ls180.v:10319$28_DATA[63:0]$2914 { 32'00000000000000000000000000000000 \main_sram2_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_3$ls180.v:10319$28_EN[63:0]$2915 64'0000000000000000000000000000000011111111000000000000000000000000 + case + end + attribute \src "ls180.v:10320.2-10321.59" + switch \main_sram2_we [4] + attribute \src "ls180.v:10320.6-10320.22" + case 1'1 + assign $0$memwr$\mem_3$ls180.v:10321$29_ADDR[5:0]$2916 \main_sram2_adr + assign $0$memwr$\mem_3$ls180.v:10321$29_DATA[63:0]$2917 { 24'000000000000000000000000 \main_sram2_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_3$ls180.v:10321$29_EN[63:0]$2918 64'0000000000000000000000001111111100000000000000000000000000000000 + case + end + attribute \src "ls180.v:10322.2-10323.59" + switch \main_sram2_we [5] + attribute \src "ls180.v:10322.6-10322.22" + case 1'1 + assign $0$memwr$\mem_3$ls180.v:10323$30_ADDR[5:0]$2919 \main_sram2_adr + assign $0$memwr$\mem_3$ls180.v:10323$30_DATA[63:0]$2920 { 16'0000000000000000 \main_sram2_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_3$ls180.v:10323$30_EN[63:0]$2921 64'0000000000000000111111110000000000000000000000000000000000000000 + case + end + attribute \src "ls180.v:10324.2-10325.59" + switch \main_sram2_we [6] + attribute \src "ls180.v:10324.6-10324.22" + case 1'1 + assign $0$memwr$\mem_3$ls180.v:10325$31_ADDR[5:0]$2922 \main_sram2_adr + assign $0$memwr$\mem_3$ls180.v:10325$31_DATA[63:0]$2923 { 8'00000000 \main_sram2_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_3$ls180.v:10325$31_EN[63:0]$2924 64'0000000011111111000000000000000000000000000000000000000000000000 + case + end + attribute \src "ls180.v:10326.2-10327.59" + switch \main_sram2_we [7] + attribute \src "ls180.v:10326.6-10326.22" + case 1'1 + assign $0$memwr$\mem_3$ls180.v:10327$32_ADDR[5:0]$2925 \main_sram2_adr + assign $0$memwr$\mem_3$ls180.v:10327$32_DATA[63:0]$2926 { \main_sram2_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_3$ls180.v:10327$32_EN[63:0]$2927 64'1111111100000000000000000000000000000000000000000000000000000000 case end sync posedge \sys_clk_1 - update \memadr_3 $0\memadr_3[6:0] - update $memwr$\mem_3$ls180.v:10222$13_ADDR $0$memwr$\mem_3$ls180.v:10222$13_ADDR[6:0]$2801 - update $memwr$\mem_3$ls180.v:10222$13_DATA $0$memwr$\mem_3$ls180.v:10222$13_DATA[31:0]$2802 - update $memwr$\mem_3$ls180.v:10222$13_EN $0$memwr$\mem_3$ls180.v:10222$13_EN[31:0]$2803 - update $memwr$\mem_3$ls180.v:10224$14_ADDR $0$memwr$\mem_3$ls180.v:10224$14_ADDR[6:0]$2804 - update $memwr$\mem_3$ls180.v:10224$14_DATA $0$memwr$\mem_3$ls180.v:10224$14_DATA[31:0]$2805 - update $memwr$\mem_3$ls180.v:10224$14_EN $0$memwr$\mem_3$ls180.v:10224$14_EN[31:0]$2806 - update $memwr$\mem_3$ls180.v:10226$15_ADDR $0$memwr$\mem_3$ls180.v:10226$15_ADDR[6:0]$2807 - update $memwr$\mem_3$ls180.v:10226$15_DATA $0$memwr$\mem_3$ls180.v:10226$15_DATA[31:0]$2808 - update $memwr$\mem_3$ls180.v:10226$15_EN $0$memwr$\mem_3$ls180.v:10226$15_EN[31:0]$2809 - update $memwr$\mem_3$ls180.v:10228$16_ADDR $0$memwr$\mem_3$ls180.v:10228$16_ADDR[6:0]$2810 - update $memwr$\mem_3$ls180.v:10228$16_DATA $0$memwr$\mem_3$ls180.v:10228$16_DATA[31:0]$2811 - update $memwr$\mem_3$ls180.v:10228$16_EN $0$memwr$\mem_3$ls180.v:10228$16_EN[31:0]$2812 - end - attribute \src "ls180.v:1023.5-1023.27" - process $proc$ls180.v:1023$3259 - assign { } { } - assign $0\main_uart_reset[0:0] 1'0 - sync always - update \main_uart_reset $0\main_uart_reset[0:0] - sync init - end - attribute \src "ls180.v:1024.12-1024.40" - process $proc$ls180.v:1024$3260 - assign { } { } - assign $1\main_gpio_oe_storage[15:0] 16'0000000000000000 - sync always - sync init - update \main_gpio_oe_storage $1\main_gpio_oe_storage[15:0] - end - attribute \src "ls180.v:10240.1-10244.4" - process $proc$ls180.v:10240$2814 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0$memwr$\storage$ls180.v:10242$17_ADDR[2:0]$2815 3'xxx - assign $0$memwr$\storage$ls180.v:10242$17_DATA[24:0]$2816 25'xxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\storage$ls180.v:10242$17_EN[24:0]$2817 25'0000000000000000000000000 - assign $0\memdat[24:0] $memrd$\storage$ls180.v:10243$2818_DATA - attribute \src "ls180.v:10241.2-10242.129" + update \memadr_3 $0\memadr_3[5:0] + update $memwr$\mem_3$ls180.v:10313$25_ADDR $0$memwr$\mem_3$ls180.v:10313$25_ADDR[5:0]$2904 + update $memwr$\mem_3$ls180.v:10313$25_DATA $0$memwr$\mem_3$ls180.v:10313$25_DATA[63:0]$2905 + update $memwr$\mem_3$ls180.v:10313$25_EN $0$memwr$\mem_3$ls180.v:10313$25_EN[63:0]$2906 + update $memwr$\mem_3$ls180.v:10315$26_ADDR $0$memwr$\mem_3$ls180.v:10315$26_ADDR[5:0]$2907 + update $memwr$\mem_3$ls180.v:10315$26_DATA $0$memwr$\mem_3$ls180.v:10315$26_DATA[63:0]$2908 + update $memwr$\mem_3$ls180.v:10315$26_EN $0$memwr$\mem_3$ls180.v:10315$26_EN[63:0]$2909 + update $memwr$\mem_3$ls180.v:10317$27_ADDR $0$memwr$\mem_3$ls180.v:10317$27_ADDR[5:0]$2910 + update $memwr$\mem_3$ls180.v:10317$27_DATA $0$memwr$\mem_3$ls180.v:10317$27_DATA[63:0]$2911 + update $memwr$\mem_3$ls180.v:10317$27_EN $0$memwr$\mem_3$ls180.v:10317$27_EN[63:0]$2912 + update $memwr$\mem_3$ls180.v:10319$28_ADDR $0$memwr$\mem_3$ls180.v:10319$28_ADDR[5:0]$2913 + update $memwr$\mem_3$ls180.v:10319$28_DATA $0$memwr$\mem_3$ls180.v:10319$28_DATA[63:0]$2914 + update $memwr$\mem_3$ls180.v:10319$28_EN $0$memwr$\mem_3$ls180.v:10319$28_EN[63:0]$2915 + update $memwr$\mem_3$ls180.v:10321$29_ADDR $0$memwr$\mem_3$ls180.v:10321$29_ADDR[5:0]$2916 + update $memwr$\mem_3$ls180.v:10321$29_DATA $0$memwr$\mem_3$ls180.v:10321$29_DATA[63:0]$2917 + update $memwr$\mem_3$ls180.v:10321$29_EN $0$memwr$\mem_3$ls180.v:10321$29_EN[63:0]$2918 + update $memwr$\mem_3$ls180.v:10323$30_ADDR $0$memwr$\mem_3$ls180.v:10323$30_ADDR[5:0]$2919 + update $memwr$\mem_3$ls180.v:10323$30_DATA $0$memwr$\mem_3$ls180.v:10323$30_DATA[63:0]$2920 + update $memwr$\mem_3$ls180.v:10323$30_EN $0$memwr$\mem_3$ls180.v:10323$30_EN[63:0]$2921 + update $memwr$\mem_3$ls180.v:10325$31_ADDR $0$memwr$\mem_3$ls180.v:10325$31_ADDR[5:0]$2922 + update $memwr$\mem_3$ls180.v:10325$31_DATA $0$memwr$\mem_3$ls180.v:10325$31_DATA[63:0]$2923 + update $memwr$\mem_3$ls180.v:10325$31_EN $0$memwr$\mem_3$ls180.v:10325$31_EN[63:0]$2924 + update $memwr$\mem_3$ls180.v:10327$32_ADDR $0$memwr$\mem_3$ls180.v:10327$32_ADDR[5:0]$2925 + update $memwr$\mem_3$ls180.v:10327$32_DATA $0$memwr$\mem_3$ls180.v:10327$32_DATA[63:0]$2926 + update $memwr$\mem_3$ls180.v:10327$32_EN $0$memwr$\mem_3$ls180.v:10327$32_EN[63:0]$2927 + end + attribute \src "ls180.v:1033.12-1033.54" + process $proc$ls180.v:1033$3396 + assign { } { } + assign $1\main_gpiotristateasic1_out_storage[15:0] 16'0000000000000000 + sync always + sync init + update \main_gpiotristateasic1_out_storage $1\main_gpiotristateasic1_out_storage[15:0] + end + attribute \src "ls180.v:10339.1-10343.4" + process $proc$ls180.v:10339$2929 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage$ls180.v:10341$33_ADDR[2:0]$2930 3'xxx + assign $0$memwr$\storage$ls180.v:10341$33_DATA[24:0]$2931 25'xxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\storage$ls180.v:10341$33_EN[24:0]$2932 25'0000000000000000000000000 + assign $0\memdat[24:0] $memrd$\storage$ls180.v:10342$2933_DATA + attribute \src "ls180.v:10340.2-10341.129" switch \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:10241.6-10241.60" + attribute \src "ls180.v:10340.6-10340.60" case 1'1 - assign $0$memwr$\storage$ls180.v:10242$17_ADDR[2:0]$2815 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr - assign $0$memwr$\storage$ls180.v:10242$17_DATA[24:0]$2816 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w - assign $0$memwr$\storage$ls180.v:10242$17_EN[24:0]$2817 25'1111111111111111111111111 + assign $0$memwr$\storage$ls180.v:10341$33_ADDR[2:0]$2930 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr + assign $0$memwr$\storage$ls180.v:10341$33_DATA[24:0]$2931 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w + assign $0$memwr$\storage$ls180.v:10341$33_EN[24:0]$2932 25'1111111111111111111111111 case end sync posedge \sys_clk_1 update \memdat $0\memdat[24:0] - update $memwr$\storage$ls180.v:10242$17_ADDR $0$memwr$\storage$ls180.v:10242$17_ADDR[2:0]$2815 - update $memwr$\storage$ls180.v:10242$17_DATA $0$memwr$\storage$ls180.v:10242$17_DATA[24:0]$2816 - update $memwr$\storage$ls180.v:10242$17_EN $0$memwr$\storage$ls180.v:10242$17_EN[24:0]$2817 - end - attribute \src "ls180.v:10246.1-10247.4" - process $proc$ls180.v:10246$2819 - sync posedge \sys_clk_1 + update $memwr$\storage$ls180.v:10341$33_ADDR $0$memwr$\storage$ls180.v:10341$33_ADDR[2:0]$2930 + update $memwr$\storage$ls180.v:10341$33_DATA $0$memwr$\storage$ls180.v:10341$33_DATA[24:0]$2931 + update $memwr$\storage$ls180.v:10341$33_EN $0$memwr$\storage$ls180.v:10341$33_EN[24:0]$2932 end - attribute \src "ls180.v:1025.5-1025.27" - process $proc$ls180.v:1025$3261 + attribute \src "ls180.v:1034.5-1034.41" + process $proc$ls180.v:1034$3397 assign { } { } - assign $1\main_gpio_oe_re[0:0] 1'0 + assign $1\main_gpiotristateasic1_out_re[0:0] 1'0 sync always sync init - update \main_gpio_oe_re $1\main_gpio_oe_re[0:0] + update \main_gpiotristateasic1_out_re $1\main_gpiotristateasic1_out_re[0:0] + end + attribute \src "ls180.v:10345.1-10346.4" + process $proc$ls180.v:10345$2934 + sync posedge \sys_clk_1 end - attribute \src "ls180.v:10254.1-10258.4" - process $proc$ls180.v:10254$2821 + attribute \src "ls180.v:10353.1-10357.4" + process $proc$ls180.v:10353$2936 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0$memwr$\storage_1$ls180.v:10256$18_ADDR[2:0]$2822 3'xxx - assign $0$memwr$\storage_1$ls180.v:10256$18_DATA[24:0]$2823 25'xxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\storage_1$ls180.v:10256$18_EN[24:0]$2824 25'0000000000000000000000000 - assign $0\memdat_1[24:0] $memrd$\storage_1$ls180.v:10257$2825_DATA - attribute \src "ls180.v:10255.2-10256.131" + assign $0$memwr$\storage_1$ls180.v:10355$34_ADDR[2:0]$2937 3'xxx + assign $0$memwr$\storage_1$ls180.v:10355$34_DATA[24:0]$2938 25'xxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\storage_1$ls180.v:10355$34_EN[24:0]$2939 25'0000000000000000000000000 + assign $0\memdat_1[24:0] $memrd$\storage_1$ls180.v:10356$2940_DATA + attribute \src "ls180.v:10354.2-10355.131" switch \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:10255.6-10255.60" + attribute \src "ls180.v:10354.6-10354.60" case 1'1 - assign $0$memwr$\storage_1$ls180.v:10256$18_ADDR[2:0]$2822 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr - assign $0$memwr$\storage_1$ls180.v:10256$18_DATA[24:0]$2823 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w - assign $0$memwr$\storage_1$ls180.v:10256$18_EN[24:0]$2824 25'1111111111111111111111111 + assign $0$memwr$\storage_1$ls180.v:10355$34_ADDR[2:0]$2937 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr + assign $0$memwr$\storage_1$ls180.v:10355$34_DATA[24:0]$2938 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w + assign $0$memwr$\storage_1$ls180.v:10355$34_EN[24:0]$2939 25'1111111111111111111111111 case end sync posedge \sys_clk_1 update \memdat_1 $0\memdat_1[24:0] - update $memwr$\storage_1$ls180.v:10256$18_ADDR $0$memwr$\storage_1$ls180.v:10256$18_ADDR[2:0]$2822 - update $memwr$\storage_1$ls180.v:10256$18_DATA $0$memwr$\storage_1$ls180.v:10256$18_DATA[24:0]$2823 - update $memwr$\storage_1$ls180.v:10256$18_EN $0$memwr$\storage_1$ls180.v:10256$18_EN[24:0]$2824 - end - attribute \src "ls180.v:1026.12-1026.36" - process $proc$ls180.v:1026$3262 - assign { } { } - assign $1\main_gpio_status[15:0] 16'0000000000000000 - sync always - sync init - update \main_gpio_status $1\main_gpio_status[15:0] + update $memwr$\storage_1$ls180.v:10355$34_ADDR $0$memwr$\storage_1$ls180.v:10355$34_ADDR[2:0]$2937 + update $memwr$\storage_1$ls180.v:10355$34_DATA $0$memwr$\storage_1$ls180.v:10355$34_DATA[24:0]$2938 + update $memwr$\storage_1$ls180.v:10355$34_EN $0$memwr$\storage_1$ls180.v:10355$34_EN[24:0]$2939 end - attribute \src "ls180.v:10260.1-10261.4" - process $proc$ls180.v:10260$2826 + attribute \src "ls180.v:10359.1-10360.4" + process $proc$ls180.v:10359$2941 sync posedge \sys_clk_1 end - attribute \src "ls180.v:10268.1-10272.4" - process $proc$ls180.v:10268$2828 + attribute \src "ls180.v:10367.1-10371.4" + process $proc$ls180.v:10367$2943 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0$memwr$\storage_2$ls180.v:10270$19_ADDR[2:0]$2829 3'xxx - assign $0$memwr$\storage_2$ls180.v:10270$19_DATA[24:0]$2830 25'xxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\storage_2$ls180.v:10270$19_EN[24:0]$2831 25'0000000000000000000000000 - assign $0\memdat_2[24:0] $memrd$\storage_2$ls180.v:10271$2832_DATA - attribute \src "ls180.v:10269.2-10270.131" + assign $0$memwr$\storage_2$ls180.v:10369$35_ADDR[2:0]$2944 3'xxx + assign $0$memwr$\storage_2$ls180.v:10369$35_DATA[24:0]$2945 25'xxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\storage_2$ls180.v:10369$35_EN[24:0]$2946 25'0000000000000000000000000 + assign $0\memdat_2[24:0] $memrd$\storage_2$ls180.v:10370$2947_DATA + attribute \src "ls180.v:10368.2-10369.131" switch \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:10269.6-10269.60" + attribute \src "ls180.v:10368.6-10368.60" case 1'1 - assign $0$memwr$\storage_2$ls180.v:10270$19_ADDR[2:0]$2829 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr - assign $0$memwr$\storage_2$ls180.v:10270$19_DATA[24:0]$2830 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w - assign $0$memwr$\storage_2$ls180.v:10270$19_EN[24:0]$2831 25'1111111111111111111111111 + assign $0$memwr$\storage_2$ls180.v:10369$35_ADDR[2:0]$2944 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr + assign $0$memwr$\storage_2$ls180.v:10369$35_DATA[24:0]$2945 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w + assign $0$memwr$\storage_2$ls180.v:10369$35_EN[24:0]$2946 25'1111111111111111111111111 case end sync posedge \sys_clk_1 update \memdat_2 $0\memdat_2[24:0] - update $memwr$\storage_2$ls180.v:10270$19_ADDR $0$memwr$\storage_2$ls180.v:10270$19_ADDR[2:0]$2829 - update $memwr$\storage_2$ls180.v:10270$19_DATA $0$memwr$\storage_2$ls180.v:10270$19_DATA[24:0]$2830 - update $memwr$\storage_2$ls180.v:10270$19_EN $0$memwr$\storage_2$ls180.v:10270$19_EN[24:0]$2831 + update $memwr$\storage_2$ls180.v:10369$35_ADDR $0$memwr$\storage_2$ls180.v:10369$35_ADDR[2:0]$2944 + update $memwr$\storage_2$ls180.v:10369$35_DATA $0$memwr$\storage_2$ls180.v:10369$35_DATA[24:0]$2945 + update $memwr$\storage_2$ls180.v:10369$35_EN $0$memwr$\storage_2$ls180.v:10369$35_EN[24:0]$2946 end - attribute \src "ls180.v:10274.1-10275.4" - process $proc$ls180.v:10274$2833 + attribute \src "ls180.v:10373.1-10374.4" + process $proc$ls180.v:10373$2948 sync posedge \sys_clk_1 end - attribute \src "ls180.v:1028.12-1028.41" - process $proc$ls180.v:1028$3263 + attribute \src "ls180.v:10381.1-10385.4" + process $proc$ls180.v:10381$2950 assign { } { } - assign $1\main_gpio_out_storage[15:0] 16'0000000000000000 - sync always - sync init - update \main_gpio_out_storage $1\main_gpio_out_storage[15:0] - end - attribute \src "ls180.v:10282.1-10286.4" - process $proc$ls180.v:10282$2835 assign { } { } assign { } { } assign { } { } - assign { } { } - assign $0$memwr$\storage_3$ls180.v:10284$20_ADDR[2:0]$2836 3'xxx - assign $0$memwr$\storage_3$ls180.v:10284$20_DATA[24:0]$2837 25'xxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\storage_3$ls180.v:10284$20_EN[24:0]$2838 25'0000000000000000000000000 - assign $0\memdat_3[24:0] $memrd$\storage_3$ls180.v:10285$2839_DATA - attribute \src "ls180.v:10283.2-10284.131" + assign $0$memwr$\storage_3$ls180.v:10383$36_ADDR[2:0]$2951 3'xxx + assign $0$memwr$\storage_3$ls180.v:10383$36_DATA[24:0]$2952 25'xxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\storage_3$ls180.v:10383$36_EN[24:0]$2953 25'0000000000000000000000000 + assign $0\memdat_3[24:0] $memrd$\storage_3$ls180.v:10384$2954_DATA + attribute \src "ls180.v:10382.2-10383.131" switch \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:10283.6-10283.60" + attribute \src "ls180.v:10382.6-10382.60" case 1'1 - assign $0$memwr$\storage_3$ls180.v:10284$20_ADDR[2:0]$2836 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr - assign $0$memwr$\storage_3$ls180.v:10284$20_DATA[24:0]$2837 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w - assign $0$memwr$\storage_3$ls180.v:10284$20_EN[24:0]$2838 25'1111111111111111111111111 + assign $0$memwr$\storage_3$ls180.v:10383$36_ADDR[2:0]$2951 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr + assign $0$memwr$\storage_3$ls180.v:10383$36_DATA[24:0]$2952 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w + assign $0$memwr$\storage_3$ls180.v:10383$36_EN[24:0]$2953 25'1111111111111111111111111 case end sync posedge \sys_clk_1 update \memdat_3 $0\memdat_3[24:0] - update $memwr$\storage_3$ls180.v:10284$20_ADDR $0$memwr$\storage_3$ls180.v:10284$20_ADDR[2:0]$2836 - update $memwr$\storage_3$ls180.v:10284$20_DATA $0$memwr$\storage_3$ls180.v:10284$20_DATA[24:0]$2837 - update $memwr$\storage_3$ls180.v:10284$20_EN $0$memwr$\storage_3$ls180.v:10284$20_EN[24:0]$2838 + update $memwr$\storage_3$ls180.v:10383$36_ADDR $0$memwr$\storage_3$ls180.v:10383$36_ADDR[2:0]$2951 + update $memwr$\storage_3$ls180.v:10383$36_DATA $0$memwr$\storage_3$ls180.v:10383$36_DATA[24:0]$2952 + update $memwr$\storage_3$ls180.v:10383$36_EN $0$memwr$\storage_3$ls180.v:10383$36_EN[24:0]$2953 end - attribute \src "ls180.v:10288.1-10289.4" - process $proc$ls180.v:10288$2840 + attribute \src "ls180.v:10387.1-10388.4" + process $proc$ls180.v:10387$2955 sync posedge \sys_clk_1 end - attribute \src "ls180.v:1029.5-1029.28" - process $proc$ls180.v:1029$3264 + attribute \src "ls180.v:10396.1-10400.4" + process $proc$ls180.v:10396$2957 assign { } { } - assign $1\main_gpio_out_re[0:0] 1'0 - sync always - sync init - update \main_gpio_out_re $1\main_gpio_out_re[0:0] - end - attribute \src "ls180.v:10297.1-10301.4" - process $proc$ls180.v:10297$2842 assign { } { } assign { } { } assign { } { } - assign { } { } - assign $0$memwr$\storage_4$ls180.v:10299$21_ADDR[3:0]$2843 4'xxxx - assign $0$memwr$\storage_4$ls180.v:10299$21_DATA[9:0]$2844 10'xxxxxxxxxx - assign $0$memwr$\storage_4$ls180.v:10299$21_EN[9:0]$2845 10'0000000000 - assign $0\memdat_4[9:0] $memrd$\storage_4$ls180.v:10300$2846_DATA - attribute \src "ls180.v:10298.2-10299.77" + assign $0$memwr$\storage_4$ls180.v:10398$37_ADDR[3:0]$2958 4'xxxx + assign $0$memwr$\storage_4$ls180.v:10398$37_DATA[9:0]$2959 10'xxxxxxxxxx + assign $0$memwr$\storage_4$ls180.v:10398$37_EN[9:0]$2960 10'0000000000 + assign $0\memdat_4[9:0] $memrd$\storage_4$ls180.v:10399$2961_DATA + attribute \src "ls180.v:10397.2-10398.77" switch \main_uart_tx_fifo_wrport_we - attribute \src "ls180.v:10298.6-10298.33" + attribute \src "ls180.v:10397.6-10397.33" case 1'1 - assign $0$memwr$\storage_4$ls180.v:10299$21_ADDR[3:0]$2843 \main_uart_tx_fifo_wrport_adr - assign $0$memwr$\storage_4$ls180.v:10299$21_DATA[9:0]$2844 \main_uart_tx_fifo_wrport_dat_w - assign $0$memwr$\storage_4$ls180.v:10299$21_EN[9:0]$2845 10'1111111111 + assign $0$memwr$\storage_4$ls180.v:10398$37_ADDR[3:0]$2958 \main_uart_tx_fifo_wrport_adr + assign $0$memwr$\storage_4$ls180.v:10398$37_DATA[9:0]$2959 \main_uart_tx_fifo_wrport_dat_w + assign $0$memwr$\storage_4$ls180.v:10398$37_EN[9:0]$2960 10'1111111111 case end sync posedge \sys_clk_1 update \memdat_4 $0\memdat_4[9:0] - update $memwr$\storage_4$ls180.v:10299$21_ADDR $0$memwr$\storage_4$ls180.v:10299$21_ADDR[3:0]$2843 - update $memwr$\storage_4$ls180.v:10299$21_DATA $0$memwr$\storage_4$ls180.v:10299$21_DATA[9:0]$2844 - update $memwr$\storage_4$ls180.v:10299$21_EN $0$memwr$\storage_4$ls180.v:10299$21_EN[9:0]$2845 + update $memwr$\storage_4$ls180.v:10398$37_ADDR $0$memwr$\storage_4$ls180.v:10398$37_ADDR[3:0]$2958 + update $memwr$\storage_4$ls180.v:10398$37_DATA $0$memwr$\storage_4$ls180.v:10398$37_DATA[9:0]$2959 + update $memwr$\storage_4$ls180.v:10398$37_EN $0$memwr$\storage_4$ls180.v:10398$37_EN[9:0]$2960 + end + attribute \src "ls180.v:104.5-104.49" + process $proc$ls180.v:104$3047 + assign { } { } + assign $1\main_libresocsim_libresoc_xics_ics_we[0:0] 1'0 + sync always + sync init + update \main_libresocsim_libresoc_xics_ics_we $1\main_libresocsim_libresoc_xics_ics_we[0:0] + end + attribute \src "ls180.v:1040.5-1040.32" + process $proc$ls180.v:1040$3398 + assign { } { } + assign $1\main_spimaster2_done[0:0] 1'0 + sync always + sync init + update \main_spimaster2_done $1\main_spimaster2_done[0:0] end - attribute \src "ls180.v:10303.1-10306.4" - process $proc$ls180.v:10303$2847 + attribute \src "ls180.v:10402.1-10405.4" + process $proc$ls180.v:10402$2962 assign $0\memdat_5[9:0] \memdat_5 - attribute \src "ls180.v:10304.2-10305.55" + attribute \src "ls180.v:10403.2-10404.55" switch \main_uart_tx_fifo_rdport_re - attribute \src "ls180.v:10304.6-10304.33" + attribute \src "ls180.v:10403.6-10403.33" case 1'1 - assign $0\memdat_5[9:0] $memrd$\storage_4$ls180.v:10305$2848_DATA + assign $0\memdat_5[9:0] $memrd$\storage_4$ls180.v:10404$2963_DATA case end sync posedge \sys_clk_1 update \memdat_5 $0\memdat_5[9:0] end - attribute \src "ls180.v:10314.1-10318.4" - process $proc$ls180.v:10314$2849 + attribute \src "ls180.v:1041.5-1041.31" + process $proc$ls180.v:1041$3399 + assign { } { } + assign $1\main_spimaster3_irq[0:0] 1'0 + sync always + sync init + update \main_spimaster3_irq $1\main_spimaster3_irq[0:0] + end + attribute \src "ls180.v:10413.1-10417.4" + process $proc$ls180.v:10413$2964 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0$memwr$\storage_5$ls180.v:10316$22_ADDR[3:0]$2850 4'xxxx - assign $0$memwr$\storage_5$ls180.v:10316$22_DATA[9:0]$2851 10'xxxxxxxxxx - assign $0$memwr$\storage_5$ls180.v:10316$22_EN[9:0]$2852 10'0000000000 - assign $0\memdat_6[9:0] $memrd$\storage_5$ls180.v:10317$2853_DATA - attribute \src "ls180.v:10315.2-10316.77" + assign $0$memwr$\storage_5$ls180.v:10415$38_ADDR[3:0]$2965 4'xxxx + assign $0$memwr$\storage_5$ls180.v:10415$38_DATA[9:0]$2966 10'xxxxxxxxxx + assign $0$memwr$\storage_5$ls180.v:10415$38_EN[9:0]$2967 10'0000000000 + assign $0\memdat_6[9:0] $memrd$\storage_5$ls180.v:10416$2968_DATA + attribute \src "ls180.v:10414.2-10415.77" switch \main_uart_rx_fifo_wrport_we - attribute \src "ls180.v:10315.6-10315.33" + attribute \src "ls180.v:10414.6-10414.33" case 1'1 - assign $0$memwr$\storage_5$ls180.v:10316$22_ADDR[3:0]$2850 \main_uart_rx_fifo_wrport_adr - assign $0$memwr$\storage_5$ls180.v:10316$22_DATA[9:0]$2851 \main_uart_rx_fifo_wrport_dat_w - assign $0$memwr$\storage_5$ls180.v:10316$22_EN[9:0]$2852 10'1111111111 + assign $0$memwr$\storage_5$ls180.v:10415$38_ADDR[3:0]$2965 \main_uart_rx_fifo_wrport_adr + assign $0$memwr$\storage_5$ls180.v:10415$38_DATA[9:0]$2966 \main_uart_rx_fifo_wrport_dat_w + assign $0$memwr$\storage_5$ls180.v:10415$38_EN[9:0]$2967 10'1111111111 case end sync posedge \sys_clk_1 update \memdat_6 $0\memdat_6[9:0] - update $memwr$\storage_5$ls180.v:10316$22_ADDR $0$memwr$\storage_5$ls180.v:10316$22_ADDR[3:0]$2850 - update $memwr$\storage_5$ls180.v:10316$22_DATA $0$memwr$\storage_5$ls180.v:10316$22_DATA[9:0]$2851 - update $memwr$\storage_5$ls180.v:10316$22_EN $0$memwr$\storage_5$ls180.v:10316$22_EN[9:0]$2852 + update $memwr$\storage_5$ls180.v:10415$38_ADDR $0$memwr$\storage_5$ls180.v:10415$38_ADDR[3:0]$2965 + update $memwr$\storage_5$ls180.v:10415$38_DATA $0$memwr$\storage_5$ls180.v:10415$38_DATA[9:0]$2966 + update $memwr$\storage_5$ls180.v:10415$38_EN $0$memwr$\storage_5$ls180.v:10415$38_EN[9:0]$2967 end - attribute \src "ls180.v:10320.1-10323.4" - process $proc$ls180.v:10320$2854 + attribute \src "ls180.v:10419.1-10422.4" + process $proc$ls180.v:10419$2969 assign $0\memdat_7[9:0] \memdat_7 - attribute \src "ls180.v:10321.2-10322.55" + attribute \src "ls180.v:10420.2-10421.55" switch \main_uart_rx_fifo_rdport_re - attribute \src "ls180.v:10321.6-10321.33" + attribute \src "ls180.v:10420.6-10420.33" case 1'1 - assign $0\memdat_7[9:0] $memrd$\storage_5$ls180.v:10322$2855_DATA + assign $0\memdat_7[9:0] $memrd$\storage_5$ls180.v:10421$2970_DATA case end sync posedge \sys_clk_1 update \memdat_7 $0\memdat_7[9:0] end - attribute \src "ls180.v:10330.1-10334.4" - process $proc$ls180.v:10330$2856 + attribute \src "ls180.v:10429.1-10433.4" + process $proc$ls180.v:10429$2971 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0$memwr$\storage_6$ls180.v:10332$23_ADDR[4:0]$2857 5'xxxxx - assign $0$memwr$\storage_6$ls180.v:10332$23_DATA[9:0]$2858 10'xxxxxxxxxx - assign $0$memwr$\storage_6$ls180.v:10332$23_EN[9:0]$2859 10'0000000000 - assign $0\memdat_8[9:0] $memrd$\storage_6$ls180.v:10333$2860_DATA - attribute \src "ls180.v:10331.2-10332.85" + assign $0$memwr$\storage_6$ls180.v:10431$39_ADDR[4:0]$2972 5'xxxxx + assign $0$memwr$\storage_6$ls180.v:10431$39_DATA[9:0]$2973 10'xxxxxxxxxx + assign $0$memwr$\storage_6$ls180.v:10431$39_EN[9:0]$2974 10'0000000000 + assign $0\memdat_8[9:0] $memrd$\storage_6$ls180.v:10432$2975_DATA + attribute \src "ls180.v:10430.2-10431.85" switch \main_sdblock2mem_fifo_wrport_we - attribute \src "ls180.v:10331.6-10331.37" + attribute \src "ls180.v:10430.6-10430.37" case 1'1 - assign $0$memwr$\storage_6$ls180.v:10332$23_ADDR[4:0]$2857 \main_sdblock2mem_fifo_wrport_adr - assign $0$memwr$\storage_6$ls180.v:10332$23_DATA[9:0]$2858 \main_sdblock2mem_fifo_wrport_dat_w - assign $0$memwr$\storage_6$ls180.v:10332$23_EN[9:0]$2859 10'1111111111 + assign $0$memwr$\storage_6$ls180.v:10431$39_ADDR[4:0]$2972 \main_sdblock2mem_fifo_wrport_adr + assign $0$memwr$\storage_6$ls180.v:10431$39_DATA[9:0]$2973 \main_sdblock2mem_fifo_wrport_dat_w + assign $0$memwr$\storage_6$ls180.v:10431$39_EN[9:0]$2974 10'1111111111 case end sync posedge \sys_clk_1 update \memdat_8 $0\memdat_8[9:0] - update $memwr$\storage_6$ls180.v:10332$23_ADDR $0$memwr$\storage_6$ls180.v:10332$23_ADDR[4:0]$2857 - update $memwr$\storage_6$ls180.v:10332$23_DATA $0$memwr$\storage_6$ls180.v:10332$23_DATA[9:0]$2858 - update $memwr$\storage_6$ls180.v:10332$23_EN $0$memwr$\storage_6$ls180.v:10332$23_EN[9:0]$2859 + update $memwr$\storage_6$ls180.v:10431$39_ADDR $0$memwr$\storage_6$ls180.v:10431$39_ADDR[4:0]$2972 + update $memwr$\storage_6$ls180.v:10431$39_DATA $0$memwr$\storage_6$ls180.v:10431$39_DATA[9:0]$2973 + update $memwr$\storage_6$ls180.v:10431$39_EN $0$memwr$\storage_6$ls180.v:10431$39_EN[9:0]$2974 + end + attribute \src "ls180.v:1043.11-1043.38" + process $proc$ls180.v:1043$3400 + assign { } { } + assign $1\main_spimaster5_miso[7:0] 8'00000000 + sync always + sync init + update \main_spimaster5_miso $1\main_spimaster5_miso[7:0] end - attribute \src "ls180.v:10336.1-10337.4" - process $proc$ls180.v:10336$2861 + attribute \src "ls180.v:10435.1-10436.4" + process $proc$ls180.v:10435$2976 sync posedge \sys_clk_1 end - attribute \src "ls180.v:10344.1-10348.4" - process $proc$ls180.v:10344$2863 + attribute \src "ls180.v:10443.1-10447.4" + process $proc$ls180.v:10443$2978 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0$memwr$\storage_7$ls180.v:10346$24_ADDR[4:0]$2864 5'xxxxx - assign $0$memwr$\storage_7$ls180.v:10346$24_DATA[9:0]$2865 10'xxxxxxxxxx - assign $0$memwr$\storage_7$ls180.v:10346$24_EN[9:0]$2866 10'0000000000 - assign $0\memdat_9[9:0] $memrd$\storage_7$ls180.v:10347$2867_DATA - attribute \src "ls180.v:10345.2-10346.85" + assign $0$memwr$\storage_7$ls180.v:10445$40_ADDR[4:0]$2979 5'xxxxx + assign $0$memwr$\storage_7$ls180.v:10445$40_DATA[9:0]$2980 10'xxxxxxxxxx + assign $0$memwr$\storage_7$ls180.v:10445$40_EN[9:0]$2981 10'0000000000 + assign $0\memdat_9[9:0] $memrd$\storage_7$ls180.v:10446$2982_DATA + attribute \src "ls180.v:10444.2-10445.85" switch \main_sdmem2block_fifo_wrport_we - attribute \src "ls180.v:10345.6-10345.37" + attribute \src "ls180.v:10444.6-10444.37" case 1'1 - assign $0$memwr$\storage_7$ls180.v:10346$24_ADDR[4:0]$2864 \main_sdmem2block_fifo_wrport_adr - assign $0$memwr$\storage_7$ls180.v:10346$24_DATA[9:0]$2865 \main_sdmem2block_fifo_wrport_dat_w - assign $0$memwr$\storage_7$ls180.v:10346$24_EN[9:0]$2866 10'1111111111 + assign $0$memwr$\storage_7$ls180.v:10445$40_ADDR[4:0]$2979 \main_sdmem2block_fifo_wrport_adr + assign $0$memwr$\storage_7$ls180.v:10445$40_DATA[9:0]$2980 \main_sdmem2block_fifo_wrport_dat_w + assign $0$memwr$\storage_7$ls180.v:10445$40_EN[9:0]$2981 10'1111111111 case end sync posedge \sys_clk_1 update \memdat_9 $0\memdat_9[9:0] - update $memwr$\storage_7$ls180.v:10346$24_ADDR $0$memwr$\storage_7$ls180.v:10346$24_ADDR[4:0]$2864 - update $memwr$\storage_7$ls180.v:10346$24_DATA $0$memwr$\storage_7$ls180.v:10346$24_DATA[9:0]$2865 - update $memwr$\storage_7$ls180.v:10346$24_EN $0$memwr$\storage_7$ls180.v:10346$24_EN[9:0]$2866 + update $memwr$\storage_7$ls180.v:10445$40_ADDR $0$memwr$\storage_7$ls180.v:10445$40_ADDR[4:0]$2979 + update $memwr$\storage_7$ls180.v:10445$40_DATA $0$memwr$\storage_7$ls180.v:10445$40_DATA[9:0]$2980 + update $memwr$\storage_7$ls180.v:10445$40_EN $0$memwr$\storage_7$ls180.v:10445$40_EN[9:0]$2981 end - attribute \src "ls180.v:1035.5-1035.32" - process $proc$ls180.v:1035$3265 - assign { } { } - assign $1\main_spimaster2_done[0:0] 1'0 - sync always - sync init - update \main_spimaster2_done $1\main_spimaster2_done[0:0] - end - attribute \src "ls180.v:10350.1-10351.4" - process $proc$ls180.v:10350$2868 + attribute \src "ls180.v:10449.1-10450.4" + process $proc$ls180.v:10449$2983 sync posedge \sys_clk_1 end - attribute \src "ls180.v:1036.5-1036.31" - process $proc$ls180.v:1036$3266 - assign { } { } - assign $1\main_spimaster3_irq[0:0] 1'0 - sync always - sync init - update \main_spimaster3_irq $1\main_spimaster3_irq[0:0] - end - attribute \src "ls180.v:1038.11-1038.38" - process $proc$ls180.v:1038$3267 - assign { } { } - assign $1\main_spimaster5_miso[7:0] 8'00000000 - sync always - sync init - update \main_spimaster5_miso $1\main_spimaster5_miso[7:0] - end - attribute \src "ls180.v:1041.12-1041.47" - process $proc$ls180.v:1041$3268 + attribute \src "ls180.v:1046.12-1046.47" + process $proc$ls180.v:1046$3401 assign { } { } assign $0\main_spimaster8_clk_divider[15:0] 16'0000000000000111 sync always update \main_spimaster8_clk_divider $0\main_spimaster8_clk_divider[15:0] sync init end - attribute \src "ls180.v:1042.5-1042.33" - process $proc$ls180.v:1042$3269 + attribute \src "ls180.v:1047.5-1047.33" + process $proc$ls180.v:1047$3402 assign { } { } assign $1\main_spimaster9_start[0:0] 1'0 sync always sync init update \main_spimaster9_start $1\main_spimaster9_start[0:0] end - attribute \src "ls180.v:1044.12-1044.44" - process $proc$ls180.v:1044$3270 + attribute \src "ls180.v:1049.12-1049.44" + process $proc$ls180.v:1049$3403 assign { } { } assign $1\main_spimaster11_storage[15:0] 16'0000000000000000 sync always sync init update \main_spimaster11_storage $1\main_spimaster11_storage[15:0] end - attribute \src "ls180.v:1045.5-1045.31" - process $proc$ls180.v:1045$3271 + attribute \src "ls180.v:1050.5-1050.31" + process $proc$ls180.v:1050$3404 assign { } { } assign $1\main_spimaster12_re[0:0] 1'0 sync always sync init update \main_spimaster12_re $1\main_spimaster12_re[0:0] end - attribute \src "ls180.v:1049.11-1049.42" - process $proc$ls180.v:1049$3272 + attribute \src "ls180.v:1054.11-1054.42" + process $proc$ls180.v:1054$3405 assign { } { } assign $1\main_spimaster16_storage[7:0] 8'00000000 sync always sync init update \main_spimaster16_storage $1\main_spimaster16_storage[7:0] end - attribute \src "ls180.v:1050.5-1050.31" - process $proc$ls180.v:1050$3273 + attribute \src "ls180.v:1055.5-1055.31" + process $proc$ls180.v:1055$3406 assign { } { } assign $1\main_spimaster17_re[0:0] 1'0 sync always sync init update \main_spimaster17_re $1\main_spimaster17_re[0:0] end - attribute \src "ls180.v:1054.5-1054.36" - process $proc$ls180.v:1054$3274 + attribute \src "ls180.v:1059.5-1059.36" + process $proc$ls180.v:1059$3407 assign { } { } assign $1\main_spimaster21_storage[0:0] 1'1 sync always sync init update \main_spimaster21_storage $1\main_spimaster21_storage[0:0] end - attribute \src "ls180.v:1055.5-1055.31" - process $proc$ls180.v:1055$3275 + attribute \src "ls180.v:1060.5-1060.31" + process $proc$ls180.v:1060$3408 assign { } { } assign $1\main_spimaster22_re[0:0] 1'0 sync always sync init update \main_spimaster22_re $1\main_spimaster22_re[0:0] end - attribute \src "ls180.v:1056.5-1056.36" - process $proc$ls180.v:1056$3276 + attribute \src "ls180.v:1061.5-1061.36" + process $proc$ls180.v:1061$3409 assign { } { } assign $1\main_spimaster23_storage[0:0] 1'0 sync always sync init update \main_spimaster23_storage $1\main_spimaster23_storage[0:0] end - attribute \src "ls180.v:1057.5-1057.31" - process $proc$ls180.v:1057$3277 + attribute \src "ls180.v:1062.5-1062.31" + process $proc$ls180.v:1062$3410 assign { } { } assign $1\main_spimaster24_re[0:0] 1'0 sync always sync init update \main_spimaster24_re $1\main_spimaster24_re[0:0] end - attribute \src "ls180.v:1058.5-1058.39" - process $proc$ls180.v:1058$3278 + attribute \src "ls180.v:1063.5-1063.39" + process $proc$ls180.v:1063$3411 assign { } { } assign $1\main_spimaster25_clk_enable[0:0] 1'0 sync always sync init update \main_spimaster25_clk_enable $1\main_spimaster25_clk_enable[0:0] end - attribute \src "ls180.v:1059.5-1059.38" - process $proc$ls180.v:1059$3279 + attribute \src "ls180.v:1064.5-1064.38" + process $proc$ls180.v:1064$3412 assign { } { } assign $1\main_spimaster26_cs_enable[0:0] 1'0 sync always sync init update \main_spimaster26_cs_enable $1\main_spimaster26_cs_enable[0:0] end - attribute \src "ls180.v:1060.11-1060.40" - process $proc$ls180.v:1060$3280 + attribute \src "ls180.v:1065.11-1065.40" + process $proc$ls180.v:1065$3413 assign { } { } assign $1\main_spimaster27_count[2:0] 3'000 sync always sync init update \main_spimaster27_count $1\main_spimaster27_count[2:0] end - attribute \src "ls180.v:1061.5-1061.39" - process $proc$ls180.v:1061$3281 + attribute \src "ls180.v:1066.5-1066.39" + process $proc$ls180.v:1066$3414 assign { } { } assign $1\main_spimaster28_mosi_latch[0:0] 1'0 sync always sync init update \main_spimaster28_mosi_latch $1\main_spimaster28_mosi_latch[0:0] end - attribute \src "ls180.v:1062.5-1062.39" - process $proc$ls180.v:1062$3282 + attribute \src "ls180.v:1067.5-1067.39" + process $proc$ls180.v:1067$3415 assign { } { } assign $1\main_spimaster29_miso_latch[0:0] 1'0 sync always sync init update \main_spimaster29_miso_latch $1\main_spimaster29_miso_latch[0:0] end - attribute \src "ls180.v:1063.12-1063.48" - process $proc$ls180.v:1063$3283 + attribute \src "ls180.v:1068.12-1068.48" + process $proc$ls180.v:1068$3416 assign { } { } assign $1\main_spimaster30_clk_divider[15:0] 16'0000000000000000 sync always sync init update \main_spimaster30_clk_divider $1\main_spimaster30_clk_divider[15:0] end - attribute \src "ls180.v:1066.11-1066.44" - process $proc$ls180.v:1066$3284 + attribute \src "ls180.v:1071.11-1071.44" + process $proc$ls180.v:1071$3417 assign { } { } assign $1\main_spimaster33_mosi_data[7:0] 8'00000000 sync always sync init update \main_spimaster33_mosi_data $1\main_spimaster33_mosi_data[7:0] end - attribute \src "ls180.v:1067.11-1067.43" - process $proc$ls180.v:1067$3285 + attribute \src "ls180.v:1072.11-1072.43" + process $proc$ls180.v:1072$3418 assign { } { } assign $1\main_spimaster34_mosi_sel[2:0] 3'000 sync always sync init update \main_spimaster34_mosi_sel $1\main_spimaster34_mosi_sel[2:0] end - attribute \src "ls180.v:1068.11-1068.44" - process $proc$ls180.v:1068$3286 + attribute \src "ls180.v:1073.11-1073.44" + process $proc$ls180.v:1073$3419 assign { } { } assign $1\main_spimaster35_miso_data[7:0] 8'00000000 sync always sync init update \main_spimaster35_miso_data $1\main_spimaster35_miso_data[7:0] end - attribute \src "ls180.v:1071.5-1071.32" - process $proc$ls180.v:1071$3287 + attribute \src "ls180.v:1076.5-1076.32" + process $proc$ls180.v:1076$3420 assign { } { } assign $1\main_spisdcard_done0[0:0] 1'0 sync always sync init update \main_spisdcard_done0 $1\main_spisdcard_done0[0:0] end - attribute \src "ls180.v:1072.5-1072.30" - process $proc$ls180.v:1072$3288 + attribute \src "ls180.v:1077.5-1077.30" + process $proc$ls180.v:1077$3421 assign { } { } assign $1\main_spisdcard_irq[0:0] 1'0 sync always sync init update \main_spisdcard_irq $1\main_spisdcard_irq[0:0] end - attribute \src "ls180.v:1074.11-1074.37" - process $proc$ls180.v:1074$3289 + attribute \src "ls180.v:1079.11-1079.37" + process $proc$ls180.v:1079$3422 assign { } { } assign $1\main_spisdcard_miso[7:0] 8'00000000 sync always sync init update \main_spisdcard_miso $1\main_spisdcard_miso[7:0] end - attribute \src "ls180.v:1078.5-1078.33" - process $proc$ls180.v:1078$3290 + attribute \src "ls180.v:1083.5-1083.33" + process $proc$ls180.v:1083$3423 assign { } { } assign $1\main_spisdcard_start1[0:0] 1'0 sync always sync init update \main_spisdcard_start1 $1\main_spisdcard_start1[0:0] end - attribute \src "ls180.v:1080.12-1080.50" - process $proc$ls180.v:1080$3291 + attribute \src "ls180.v:1085.12-1085.50" + process $proc$ls180.v:1085$3424 assign { } { } assign $1\main_spisdcard_control_storage[15:0] 16'0000000000000000 sync always sync init update \main_spisdcard_control_storage $1\main_spisdcard_control_storage[15:0] end - attribute \src "ls180.v:1081.5-1081.37" - process $proc$ls180.v:1081$3292 + attribute \src "ls180.v:1086.5-1086.37" + process $proc$ls180.v:1086$3425 assign { } { } assign $1\main_spisdcard_control_re[0:0] 1'0 sync always sync init update \main_spisdcard_control_re $1\main_spisdcard_control_re[0:0] end - attribute \src "ls180.v:1085.11-1085.45" - process $proc$ls180.v:1085$3293 + attribute \src "ls180.v:1090.11-1090.45" + process $proc$ls180.v:1090$3426 assign { } { } assign $1\main_spisdcard_mosi_storage[7:0] 8'00000000 sync always sync init update \main_spisdcard_mosi_storage $1\main_spisdcard_mosi_storage[7:0] end - attribute \src "ls180.v:1086.5-1086.34" - process $proc$ls180.v:1086$3294 + attribute \src "ls180.v:1091.5-1091.34" + process $proc$ls180.v:1091$3427 assign { } { } assign $1\main_spisdcard_mosi_re[0:0] 1'0 sync always sync init update \main_spisdcard_mosi_re $1\main_spisdcard_mosi_re[0:0] end - attribute \src "ls180.v:1090.5-1090.37" - process $proc$ls180.v:1090$3295 + attribute \src "ls180.v:1095.5-1095.37" + process $proc$ls180.v:1095$3428 assign { } { } assign $1\main_spisdcard_cs_storage[0:0] 1'1 sync always sync init update \main_spisdcard_cs_storage $1\main_spisdcard_cs_storage[0:0] end - attribute \src "ls180.v:1091.5-1091.32" - process $proc$ls180.v:1091$3296 + attribute \src "ls180.v:1096.5-1096.32" + process $proc$ls180.v:1096$3429 assign { } { } assign $1\main_spisdcard_cs_re[0:0] 1'0 sync always sync init update \main_spisdcard_cs_re $1\main_spisdcard_cs_re[0:0] end - attribute \src "ls180.v:1092.5-1092.43" - process $proc$ls180.v:1092$3297 + attribute \src "ls180.v:1097.5-1097.43" + process $proc$ls180.v:1097$3430 assign { } { } assign $1\main_spisdcard_loopback_storage[0:0] 1'0 sync always sync init update \main_spisdcard_loopback_storage $1\main_spisdcard_loopback_storage[0:0] end - attribute \src "ls180.v:1093.5-1093.38" - process $proc$ls180.v:1093$3298 + attribute \src "ls180.v:1098.5-1098.38" + process $proc$ls180.v:1098$3431 assign { } { } assign $1\main_spisdcard_loopback_re[0:0] 1'0 sync always sync init update \main_spisdcard_loopback_re $1\main_spisdcard_loopback_re[0:0] end - attribute \src "ls180.v:1094.5-1094.37" - process $proc$ls180.v:1094$3299 + attribute \src "ls180.v:1099.5-1099.37" + process $proc$ls180.v:1099$3432 assign { } { } assign $1\main_spisdcard_clk_enable[0:0] 1'0 sync always sync init update \main_spisdcard_clk_enable $1\main_spisdcard_clk_enable[0:0] end - attribute \src "ls180.v:1095.5-1095.36" - process $proc$ls180.v:1095$3300 + attribute \src "ls180.v:1100.5-1100.36" + process $proc$ls180.v:1100$3433 assign { } { } assign $1\main_spisdcard_cs_enable[0:0] 1'0 sync always sync init update \main_spisdcard_cs_enable $1\main_spisdcard_cs_enable[0:0] end - attribute \src "ls180.v:1096.11-1096.38" - process $proc$ls180.v:1096$3301 + attribute \src "ls180.v:1101.11-1101.38" + process $proc$ls180.v:1101$3434 assign { } { } assign $1\main_spisdcard_count[2:0] 3'000 sync always sync init update \main_spisdcard_count $1\main_spisdcard_count[2:0] end - attribute \src "ls180.v:1097.5-1097.37" - process $proc$ls180.v:1097$3302 + attribute \src "ls180.v:1102.5-1102.37" + process $proc$ls180.v:1102$3435 assign { } { } assign $1\main_spisdcard_mosi_latch[0:0] 1'0 sync always sync init update \main_spisdcard_mosi_latch $1\main_spisdcard_mosi_latch[0:0] end - attribute \src "ls180.v:1098.5-1098.37" - process $proc$ls180.v:1098$3303 + attribute \src "ls180.v:1103.5-1103.37" + process $proc$ls180.v:1103$3436 assign { } { } assign $1\main_spisdcard_miso_latch[0:0] 1'0 sync always sync init update \main_spisdcard_miso_latch $1\main_spisdcard_miso_latch[0:0] end - attribute \src "ls180.v:1099.12-1099.47" - process $proc$ls180.v:1099$3304 + attribute \src "ls180.v:1104.12-1104.47" + process $proc$ls180.v:1104$3437 assign { } { } assign $1\main_spisdcard_clk_divider1[15:0] 16'0000000000000000 sync always sync init update \main_spisdcard_clk_divider1 $1\main_spisdcard_clk_divider1[15:0] end - attribute \src "ls180.v:1102.11-1102.42" - process $proc$ls180.v:1102$3305 + attribute \src "ls180.v:1107.11-1107.42" + process $proc$ls180.v:1107$3438 assign { } { } assign $1\main_spisdcard_mosi_data[7:0] 8'00000000 sync always sync init update \main_spisdcard_mosi_data $1\main_spisdcard_mosi_data[7:0] end - attribute \src "ls180.v:1103.11-1103.41" - process $proc$ls180.v:1103$3306 + attribute \src "ls180.v:1108.11-1108.41" + process $proc$ls180.v:1108$3439 assign { } { } assign $1\main_spisdcard_mosi_sel[2:0] 3'000 sync always sync init update \main_spisdcard_mosi_sel $1\main_spisdcard_mosi_sel[2:0] end - attribute \src "ls180.v:1104.11-1104.42" - process $proc$ls180.v:1104$3307 + attribute \src "ls180.v:1109.11-1109.42" + process $proc$ls180.v:1109$3440 assign { } { } assign $1\main_spisdcard_miso_data[7:0] 8'00000000 sync always sync init update \main_spisdcard_miso_data $1\main_spisdcard_miso_data[7:0] end - attribute \src "ls180.v:1105.12-1105.45" - process $proc$ls180.v:1105$3308 + attribute \src "ls180.v:1110.12-1110.45" + process $proc$ls180.v:1110$3441 assign { } { } assign $1\main_spimaster1_storage[15:0] 16'0000000001111101 sync always sync init update \main_spimaster1_storage $1\main_spimaster1_storage[15:0] end - attribute \src "ls180.v:1106.5-1106.30" - process $proc$ls180.v:1106$3309 + attribute \src "ls180.v:1111.5-1111.30" + process $proc$ls180.v:1111$3442 assign { } { } assign $1\main_spimaster1_re[0:0] 1'0 sync always sync init update \main_spimaster1_re $1\main_spimaster1_re[0:0] end - attribute \src "ls180.v:1108.12-1108.30" - process $proc$ls180.v:1108$3310 + attribute \src "ls180.v:1113.12-1113.30" + process $proc$ls180.v:1113$3443 assign { } { } assign $1\main_dummy[23:0] 24'000000000000000000000000 sync always sync init update \main_dummy $1\main_dummy[23:0] end - attribute \src "ls180.v:1112.12-1112.37" - process $proc$ls180.v:1112$3311 + attribute \src "ls180.v:1117.12-1117.37" + process $proc$ls180.v:1117$3444 assign { } { } assign $1\main_pwm0_counter[31:0] 0 sync always sync init update \main_pwm0_counter $1\main_pwm0_counter[31:0] end - attribute \src "ls180.v:1113.5-1113.36" - process $proc$ls180.v:1113$3312 + attribute \src "ls180.v:1118.5-1118.36" + process $proc$ls180.v:1118$3445 assign { } { } assign $1\main_pwm0_enable_storage[0:0] 1'0 sync always sync init update \main_pwm0_enable_storage $1\main_pwm0_enable_storage[0:0] end - attribute \src "ls180.v:1114.5-1114.31" - process $proc$ls180.v:1114$3313 + attribute \src "ls180.v:1119.5-1119.31" + process $proc$ls180.v:1119$3446 assign { } { } assign $1\main_pwm0_enable_re[0:0] 1'0 sync always sync init update \main_pwm0_enable_re $1\main_pwm0_enable_re[0:0] end - attribute \src "ls180.v:1115.12-1115.43" - process $proc$ls180.v:1115$3314 + attribute \src "ls180.v:1120.12-1120.43" + process $proc$ls180.v:1120$3447 assign { } { } assign $1\main_pwm0_width_storage[31:0] 0 sync always sync init update \main_pwm0_width_storage $1\main_pwm0_width_storage[31:0] end - attribute \src "ls180.v:1116.5-1116.30" - process $proc$ls180.v:1116$3315 + attribute \src "ls180.v:1121.5-1121.30" + process $proc$ls180.v:1121$3448 assign { } { } assign $1\main_pwm0_width_re[0:0] 1'0 sync always sync init update \main_pwm0_width_re $1\main_pwm0_width_re[0:0] end - attribute \src "ls180.v:1117.12-1117.44" - process $proc$ls180.v:1117$3316 + attribute \src "ls180.v:1122.12-1122.44" + process $proc$ls180.v:1122$3449 assign { } { } assign $1\main_pwm0_period_storage[31:0] 0 sync always sync init update \main_pwm0_period_storage $1\main_pwm0_period_storage[31:0] end - attribute \src "ls180.v:1118.5-1118.31" - process $proc$ls180.v:1118$3317 + attribute \src "ls180.v:1123.5-1123.31" + process $proc$ls180.v:1123$3450 assign { } { } assign $1\main_pwm0_period_re[0:0] 1'0 sync always sync init update \main_pwm0_period_re $1\main_pwm0_period_re[0:0] end - attribute \src "ls180.v:112.5-112.49" - process $proc$ls180.v:112$2905 - assign { } { } - assign $1\main_libresocsim_libresoc_jtag_wb_ack[0:0] 1'0 - sync always - sync init - update \main_libresocsim_libresoc_jtag_wb_ack $1\main_libresocsim_libresoc_jtag_wb_ack[0:0] - end - attribute \src "ls180.v:1122.12-1122.37" - process $proc$ls180.v:1122$3318 + attribute \src "ls180.v:1127.12-1127.37" + process $proc$ls180.v:1127$3451 assign { } { } assign $1\main_pwm1_counter[31:0] 0 sync always sync init update \main_pwm1_counter $1\main_pwm1_counter[31:0] end - attribute \src "ls180.v:1123.5-1123.36" - process $proc$ls180.v:1123$3319 + attribute \src "ls180.v:1128.5-1128.36" + process $proc$ls180.v:1128$3452 assign { } { } assign $1\main_pwm1_enable_storage[0:0] 1'0 sync always sync init update \main_pwm1_enable_storage $1\main_pwm1_enable_storage[0:0] end - attribute \src "ls180.v:1124.5-1124.31" - process $proc$ls180.v:1124$3320 + attribute \src "ls180.v:1129.5-1129.31" + process $proc$ls180.v:1129$3453 assign { } { } assign $1\main_pwm1_enable_re[0:0] 1'0 sync always sync init update \main_pwm1_enable_re $1\main_pwm1_enable_re[0:0] end - attribute \src "ls180.v:1125.12-1125.43" - process $proc$ls180.v:1125$3321 + attribute \src "ls180.v:1130.12-1130.43" + process $proc$ls180.v:1130$3454 assign { } { } assign $1\main_pwm1_width_storage[31:0] 0 sync always sync init update \main_pwm1_width_storage $1\main_pwm1_width_storage[31:0] end - attribute \src "ls180.v:1126.5-1126.30" - process $proc$ls180.v:1126$3322 + attribute \src "ls180.v:1131.5-1131.30" + process $proc$ls180.v:1131$3455 assign { } { } assign $1\main_pwm1_width_re[0:0] 1'0 sync always sync init update \main_pwm1_width_re $1\main_pwm1_width_re[0:0] end - attribute \src "ls180.v:1127.12-1127.44" - process $proc$ls180.v:1127$3323 + attribute \src "ls180.v:1132.12-1132.44" + process $proc$ls180.v:1132$3456 assign { } { } assign $1\main_pwm1_period_storage[31:0] 0 sync always sync init update \main_pwm1_period_storage $1\main_pwm1_period_storage[31:0] end - attribute \src "ls180.v:1128.5-1128.31" - process $proc$ls180.v:1128$3324 + attribute \src "ls180.v:1133.5-1133.31" + process $proc$ls180.v:1133$3457 assign { } { } assign $1\main_pwm1_period_re[0:0] 1'0 sync always sync init update \main_pwm1_period_re $1\main_pwm1_period_re[0:0] end - attribute \src "ls180.v:1132.11-1132.34" - process $proc$ls180.v:1132$3325 + attribute \src "ls180.v:1137.11-1137.34" + process $proc$ls180.v:1137$3458 assign { } { } assign $1\main_i2c_storage[2:0] 3'000 sync always sync init update \main_i2c_storage $1\main_i2c_storage[2:0] end - attribute \src "ls180.v:1133.5-1133.23" - process $proc$ls180.v:1133$3326 + attribute \src "ls180.v:1138.5-1138.23" + process $proc$ls180.v:1138$3459 assign { } { } assign $1\main_i2c_re[0:0] 1'0 sync always sync init update \main_i2c_re $1\main_i2c_re[0:0] end - attribute \src "ls180.v:1139.11-1139.46" - process $proc$ls180.v:1139$3327 + attribute \src "ls180.v:114.11-114.55" + process $proc$ls180.v:114$3048 assign { } { } - assign $1\main_sdphy_clocker_storage[8:0] 9'100000000 + assign $0\main_libresocsim_libresoc_jtag_wb_cti[2:0] 3'000 sync always + update \main_libresocsim_libresoc_jtag_wb_cti $0\main_libresocsim_libresoc_jtag_wb_cti[2:0] sync init - update \main_sdphy_clocker_storage $1\main_sdphy_clocker_storage[8:0] end - attribute \src "ls180.v:114.5-114.49" - process $proc$ls180.v:114$2906 + attribute \src "ls180.v:1144.11-1144.46" + process $proc$ls180.v:1144$3460 assign { } { } - assign $0\main_libresocsim_libresoc_jtag_wb_err[0:0] 1'0 + assign $1\main_sdphy_clocker_storage[8:0] 9'100000000 sync always - update \main_libresocsim_libresoc_jtag_wb_err $0\main_libresocsim_libresoc_jtag_wb_err[0:0] sync init + update \main_sdphy_clocker_storage $1\main_sdphy_clocker_storage[8:0] end - attribute \src "ls180.v:1140.5-1140.33" - process $proc$ls180.v:1140$3328 + attribute \src "ls180.v:1145.5-1145.33" + process $proc$ls180.v:1145$3461 assign { } { } assign $1\main_sdphy_clocker_re[0:0] 1'0 sync always sync init update \main_sdphy_clocker_re $1\main_sdphy_clocker_re[0:0] end - attribute \src "ls180.v:1142.5-1142.35" - process $proc$ls180.v:1142$3329 + attribute \src "ls180.v:1147.5-1147.35" + process $proc$ls180.v:1147$3462 assign { } { } assign $1\main_sdphy_clocker_clk0[0:0] 1'0 sync always sync init update \main_sdphy_clocker_clk0 $1\main_sdphy_clocker_clk0[0:0] end - attribute \src "ls180.v:1144.11-1144.41" - process $proc$ls180.v:1144$3330 + attribute \src "ls180.v:1149.11-1149.41" + process $proc$ls180.v:1149$3463 assign { } { } assign $1\main_sdphy_clocker_clks[8:0] 9'000000000 sync always sync init update \main_sdphy_clocker_clks $1\main_sdphy_clocker_clks[8:0] end - attribute \src "ls180.v:1145.5-1145.35" - process $proc$ls180.v:1145$3331 + attribute \src "ls180.v:115.11-115.55" + process $proc$ls180.v:115$3049 + assign { } { } + assign $0\main_libresocsim_libresoc_jtag_wb_bte[1:0] 2'00 + sync always + update \main_libresocsim_libresoc_jtag_wb_bte $0\main_libresocsim_libresoc_jtag_wb_bte[1:0] + sync init + end + attribute \src "ls180.v:1150.5-1150.35" + process $proc$ls180.v:1150$3464 assign { } { } assign $1\main_sdphy_clocker_clk1[0:0] 1'0 sync always sync init update \main_sdphy_clocker_clk1 $1\main_sdphy_clocker_clk1[0:0] end - attribute \src "ls180.v:1146.5-1146.36" - process $proc$ls180.v:1146$3332 + attribute \src "ls180.v:1151.5-1151.36" + process $proc$ls180.v:1151$3465 assign { } { } assign $1\main_sdphy_clocker_clk_d[0:0] 1'0 sync always sync init update \main_sdphy_clocker_clk_d $1\main_sdphy_clocker_clk_d[0:0] end - attribute \src "ls180.v:1150.5-1150.40" - process $proc$ls180.v:1150$3333 + attribute \src "ls180.v:1155.5-1155.40" + process $proc$ls180.v:1155$3466 assign { } { } assign $0\main_sdphy_init_initialize_w[0:0] 1'0 sync always update \main_sdphy_init_initialize_w $0\main_sdphy_init_initialize_w[0:0] sync init end - attribute \src "ls180.v:1155.5-1155.48" - process $proc$ls180.v:1155$3334 + attribute \src "ls180.v:1160.5-1160.48" + process $proc$ls180.v:1160$3467 assign { } { } assign $1\main_sdphy_init_pads_out_payload_clk[0:0] 1'0 sync always sync init update \main_sdphy_init_pads_out_payload_clk $1\main_sdphy_init_pads_out_payload_clk[0:0] end - attribute \src "ls180.v:1156.5-1156.50" - process $proc$ls180.v:1156$3335 + attribute \src "ls180.v:1161.5-1161.50" + process $proc$ls180.v:1161$3468 assign { } { } assign $1\main_sdphy_init_pads_out_payload_cmd_o[0:0] 1'0 sync always sync init update \main_sdphy_init_pads_out_payload_cmd_o $1\main_sdphy_init_pads_out_payload_cmd_o[0:0] end - attribute \src "ls180.v:1157.5-1157.51" - process $proc$ls180.v:1157$3336 + attribute \src "ls180.v:1162.5-1162.51" + process $proc$ls180.v:1162$3469 assign { } { } assign $1\main_sdphy_init_pads_out_payload_cmd_oe[0:0] 1'0 sync always sync init update \main_sdphy_init_pads_out_payload_cmd_oe $1\main_sdphy_init_pads_out_payload_cmd_oe[0:0] end - attribute \src "ls180.v:1158.11-1158.57" - process $proc$ls180.v:1158$3337 + attribute \src "ls180.v:1163.11-1163.57" + process $proc$ls180.v:1163$3470 assign { } { } assign $1\main_sdphy_init_pads_out_payload_data_o[3:0] 4'0000 sync always sync init update \main_sdphy_init_pads_out_payload_data_o $1\main_sdphy_init_pads_out_payload_data_o[3:0] end - attribute \src "ls180.v:1159.5-1159.52" - process $proc$ls180.v:1159$3338 + attribute \src "ls180.v:1164.5-1164.52" + process $proc$ls180.v:1164$3471 assign { } { } assign $1\main_sdphy_init_pads_out_payload_data_oe[0:0] 1'0 sync always sync init update \main_sdphy_init_pads_out_payload_data_oe $1\main_sdphy_init_pads_out_payload_data_oe[0:0] end - attribute \src "ls180.v:1160.11-1160.39" - process $proc$ls180.v:1160$3339 + attribute \src "ls180.v:1165.11-1165.39" + process $proc$ls180.v:1165$3472 assign { } { } assign $1\main_sdphy_init_count[7:0] 8'00000000 sync always sync init update \main_sdphy_init_count $1\main_sdphy_init_count[7:0] end - attribute \src "ls180.v:1165.5-1165.48" - process $proc$ls180.v:1165$3340 + attribute \src "ls180.v:1170.5-1170.48" + process $proc$ls180.v:1170$3473 assign { } { } assign $1\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'0 sync always sync init update \main_sdphy_cmdw_pads_out_payload_clk $1\main_sdphy_cmdw_pads_out_payload_clk[0:0] end - attribute \src "ls180.v:1166.5-1166.50" - process $proc$ls180.v:1166$3341 + attribute \src "ls180.v:1171.5-1171.50" + process $proc$ls180.v:1171$3474 assign { } { } assign $1\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] 1'0 sync always sync init update \main_sdphy_cmdw_pads_out_payload_cmd_o $1\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] end - attribute \src "ls180.v:1167.5-1167.51" - process $proc$ls180.v:1167$3342 + attribute \src "ls180.v:1172.5-1172.51" + process $proc$ls180.v:1172$3475 assign { } { } assign $1\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'0 sync always sync init update \main_sdphy_cmdw_pads_out_payload_cmd_oe $1\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] end - attribute \src "ls180.v:1168.11-1168.57" - process $proc$ls180.v:1168$3343 + attribute \src "ls180.v:1173.11-1173.57" + process $proc$ls180.v:1173$3476 assign { } { } assign $0\main_sdphy_cmdw_pads_out_payload_data_o[3:0] 4'0000 sync always update \main_sdphy_cmdw_pads_out_payload_data_o $0\main_sdphy_cmdw_pads_out_payload_data_o[3:0] sync init end - attribute \src "ls180.v:1169.5-1169.52" - process $proc$ls180.v:1169$3344 + attribute \src "ls180.v:1174.5-1174.52" + process $proc$ls180.v:1174$3477 assign { } { } assign $0\main_sdphy_cmdw_pads_out_payload_data_oe[0:0] 1'0 sync always update \main_sdphy_cmdw_pads_out_payload_data_oe $0\main_sdphy_cmdw_pads_out_payload_data_oe[0:0] sync init end - attribute \src "ls180.v:1170.5-1170.38" - process $proc$ls180.v:1170$3345 + attribute \src "ls180.v:1175.5-1175.38" + process $proc$ls180.v:1175$3478 assign { } { } assign $1\main_sdphy_cmdw_sink_valid[0:0] 1'0 sync always sync init update \main_sdphy_cmdw_sink_valid $1\main_sdphy_cmdw_sink_valid[0:0] end - attribute \src "ls180.v:1171.5-1171.38" - process $proc$ls180.v:1171$3346 + attribute \src "ls180.v:1176.5-1176.38" + process $proc$ls180.v:1176$3479 assign { } { } assign $1\main_sdphy_cmdw_sink_ready[0:0] 1'0 sync always sync init update \main_sdphy_cmdw_sink_ready $1\main_sdphy_cmdw_sink_ready[0:0] end - attribute \src "ls180.v:1172.5-1172.37" - process $proc$ls180.v:1172$3347 + attribute \src "ls180.v:1177.5-1177.37" + process $proc$ls180.v:1177$3480 assign { } { } assign $1\main_sdphy_cmdw_sink_last[0:0] 1'0 sync always sync init update \main_sdphy_cmdw_sink_last $1\main_sdphy_cmdw_sink_last[0:0] end - attribute \src "ls180.v:1173.11-1173.51" - process $proc$ls180.v:1173$3348 + attribute \src "ls180.v:1178.11-1178.51" + process $proc$ls180.v:1178$3481 assign { } { } assign $1\main_sdphy_cmdw_sink_payload_data[7:0] 8'00000000 sync always sync init update \main_sdphy_cmdw_sink_payload_data $1\main_sdphy_cmdw_sink_payload_data[7:0] end - attribute \src "ls180.v:1174.5-1174.32" - process $proc$ls180.v:1174$3349 + attribute \src "ls180.v:1179.5-1179.32" + process $proc$ls180.v:1179$3482 assign { } { } assign $1\main_sdphy_cmdw_done[0:0] 1'0 sync always sync init update \main_sdphy_cmdw_done $1\main_sdphy_cmdw_done[0:0] end - attribute \src "ls180.v:1175.11-1175.39" - process $proc$ls180.v:1175$3350 + attribute \src "ls180.v:1180.11-1180.39" + process $proc$ls180.v:1180$3483 assign { } { } assign $1\main_sdphy_cmdw_count[7:0] 8'00000000 sync always sync init update \main_sdphy_cmdw_count $1\main_sdphy_cmdw_count[7:0] end - attribute \src "ls180.v:1178.5-1178.49" - process $proc$ls180.v:1178$3351 + attribute \src "ls180.v:1183.5-1183.49" + process $proc$ls180.v:1183$3484 assign { } { } assign $0\main_sdphy_cmdr_pads_in_pads_in_first[0:0] 1'0 sync always update \main_sdphy_cmdr_pads_in_pads_in_first $0\main_sdphy_cmdr_pads_in_pads_in_first[0:0] sync init end - attribute \src "ls180.v:1179.5-1179.48" - process $proc$ls180.v:1179$3352 + attribute \src "ls180.v:1184.5-1184.48" + process $proc$ls180.v:1184$3485 assign { } { } assign $0\main_sdphy_cmdr_pads_in_pads_in_last[0:0] 1'0 sync always update \main_sdphy_cmdr_pads_in_pads_in_last $0\main_sdphy_cmdr_pads_in_pads_in_last[0:0] sync init end - attribute \src "ls180.v:1180.5-1180.55" - process $proc$ls180.v:1180$3353 + attribute \src "ls180.v:1185.5-1185.55" + process $proc$ls180.v:1185$3486 assign { } { } assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_clk[0:0] 1'0 sync always update \main_sdphy_cmdr_pads_in_pads_in_payload_clk $0\main_sdphy_cmdr_pads_in_pads_in_payload_clk[0:0] sync init end - attribute \src "ls180.v:1182.5-1182.57" - process $proc$ls180.v:1182$3354 + attribute \src "ls180.v:1187.5-1187.57" + process $proc$ls180.v:1187$3487 assign { } { } assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o[0:0] 1'0 sync always update \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o[0:0] sync init end - attribute \src "ls180.v:1183.5-1183.58" - process $proc$ls180.v:1183$3355 + attribute \src "ls180.v:1188.5-1188.58" + process $proc$ls180.v:1188$3488 assign { } { } assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe[0:0] 1'0 sync always update \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe[0:0] sync init end - attribute \src "ls180.v:1185.11-1185.64" - process $proc$ls180.v:1185$3356 + attribute \src "ls180.v:1190.11-1190.64" + process $proc$ls180.v:1190$3489 assign { } { } assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_o[3:0] 4'0000 sync always update \main_sdphy_cmdr_pads_in_pads_in_payload_data_o $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_o[3:0] sync init end - attribute \src "ls180.v:1186.5-1186.59" - process $proc$ls180.v:1186$3357 + attribute \src "ls180.v:1191.5-1191.59" + process $proc$ls180.v:1191$3490 assign { } { } assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_oe[0:0] 1'0 sync always update \main_sdphy_cmdr_pads_in_pads_in_payload_data_oe $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_oe[0:0] sync init end - attribute \src "ls180.v:1188.5-1188.48" - process $proc$ls180.v:1188$3358 + attribute \src "ls180.v:1193.5-1193.48" + process $proc$ls180.v:1193$3491 assign { } { } assign $1\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_pads_out_payload_clk $1\main_sdphy_cmdr_pads_out_payload_clk[0:0] end - attribute \src "ls180.v:1189.5-1189.50" - process $proc$ls180.v:1189$3359 + attribute \src "ls180.v:1194.5-1194.50" + process $proc$ls180.v:1194$3492 assign { } { } assign $1\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_pads_out_payload_cmd_o $1\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] end - attribute \src "ls180.v:1190.5-1190.51" - process $proc$ls180.v:1190$3360 + attribute \src "ls180.v:1195.5-1195.51" + process $proc$ls180.v:1195$3493 assign { } { } assign $1\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_pads_out_payload_cmd_oe $1\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] end - attribute \src "ls180.v:1191.11-1191.57" - process $proc$ls180.v:1191$3361 + attribute \src "ls180.v:1196.11-1196.57" + process $proc$ls180.v:1196$3494 assign { } { } assign $0\main_sdphy_cmdr_pads_out_payload_data_o[3:0] 4'0000 sync always update \main_sdphy_cmdr_pads_out_payload_data_o $0\main_sdphy_cmdr_pads_out_payload_data_o[3:0] sync init end - attribute \src "ls180.v:1192.5-1192.52" - process $proc$ls180.v:1192$3362 + attribute \src "ls180.v:1197.5-1197.52" + process $proc$ls180.v:1197$3495 assign { } { } assign $0\main_sdphy_cmdr_pads_out_payload_data_oe[0:0] 1'0 sync always update \main_sdphy_cmdr_pads_out_payload_data_oe $0\main_sdphy_cmdr_pads_out_payload_data_oe[0:0] sync init end - attribute \src "ls180.v:1193.5-1193.38" - process $proc$ls180.v:1193$3363 + attribute \src "ls180.v:1198.5-1198.38" + process $proc$ls180.v:1198$3496 assign { } { } assign $1\main_sdphy_cmdr_sink_valid[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_sink_valid $1\main_sdphy_cmdr_sink_valid[0:0] end - attribute \src "ls180.v:1194.5-1194.38" - process $proc$ls180.v:1194$3364 + attribute \src "ls180.v:1199.5-1199.38" + process $proc$ls180.v:1199$3497 assign { } { } assign $1\main_sdphy_cmdr_sink_ready[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_sink_ready $1\main_sdphy_cmdr_sink_ready[0:0] end - attribute \src "ls180.v:1195.5-1195.37" - process $proc$ls180.v:1195$3365 + attribute \src "ls180.v:1200.5-1200.37" + process $proc$ls180.v:1200$3498 assign { } { } assign $1\main_sdphy_cmdr_sink_last[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_sink_last $1\main_sdphy_cmdr_sink_last[0:0] end - attribute \src "ls180.v:1196.11-1196.53" - process $proc$ls180.v:1196$3366 + attribute \src "ls180.v:1201.11-1201.53" + process $proc$ls180.v:1201$3499 assign { } { } assign $1\main_sdphy_cmdr_sink_payload_length[7:0] 8'00000000 sync always sync init update \main_sdphy_cmdr_sink_payload_length $1\main_sdphy_cmdr_sink_payload_length[7:0] end - attribute \src "ls180.v:1197.5-1197.40" - process $proc$ls180.v:1197$3367 + attribute \src "ls180.v:1202.5-1202.40" + process $proc$ls180.v:1202$3500 assign { } { } assign $1\main_sdphy_cmdr_source_valid[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_source_valid $1\main_sdphy_cmdr_source_valid[0:0] end - attribute \src "ls180.v:1198.5-1198.40" - process $proc$ls180.v:1198$3368 + attribute \src "ls180.v:1203.5-1203.40" + process $proc$ls180.v:1203$3501 assign { } { } assign $1\main_sdphy_cmdr_source_ready[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_source_ready $1\main_sdphy_cmdr_source_ready[0:0] end - attribute \src "ls180.v:1199.5-1199.39" - process $proc$ls180.v:1199$3369 + attribute \src "ls180.v:1204.5-1204.39" + process $proc$ls180.v:1204$3502 assign { } { } assign $1\main_sdphy_cmdr_source_last[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_source_last $1\main_sdphy_cmdr_source_last[0:0] end - attribute \src "ls180.v:1200.11-1200.53" - process $proc$ls180.v:1200$3370 + attribute \src "ls180.v:1205.11-1205.53" + process $proc$ls180.v:1205$3503 assign { } { } assign $1\main_sdphy_cmdr_source_payload_data[7:0] 8'00000000 sync always sync init update \main_sdphy_cmdr_source_payload_data $1\main_sdphy_cmdr_source_payload_data[7:0] end - attribute \src "ls180.v:1201.11-1201.55" - process $proc$ls180.v:1201$3371 + attribute \src "ls180.v:1206.11-1206.55" + process $proc$ls180.v:1206$3504 assign { } { } assign $1\main_sdphy_cmdr_source_payload_status[2:0] 3'000 sync always sync init update \main_sdphy_cmdr_source_payload_status $1\main_sdphy_cmdr_source_payload_status[2:0] end - attribute \src "ls180.v:1202.12-1202.48" - process $proc$ls180.v:1202$3372 + attribute \src "ls180.v:1207.12-1207.48" + process $proc$ls180.v:1207$3505 assign { } { } assign $1\main_sdphy_cmdr_timeout[31:0] 500000 sync always sync init update \main_sdphy_cmdr_timeout $1\main_sdphy_cmdr_timeout[31:0] end - attribute \src "ls180.v:1203.11-1203.39" - process $proc$ls180.v:1203$3373 + attribute \src "ls180.v:1208.11-1208.39" + process $proc$ls180.v:1208$3506 assign { } { } assign $1\main_sdphy_cmdr_count[7:0] 8'00000000 sync always sync init update \main_sdphy_cmdr_count $1\main_sdphy_cmdr_count[7:0] end - attribute \src "ls180.v:1205.5-1205.46" - process $proc$ls180.v:1205$3374 + attribute \src "ls180.v:1210.5-1210.46" + process $proc$ls180.v:1210$3507 assign { } { } assign $0\main_sdphy_cmdr_cmdr_pads_in_ready[0:0] 1'0 sync always update \main_sdphy_cmdr_cmdr_pads_in_ready $0\main_sdphy_cmdr_cmdr_pads_in_ready[0:0] sync init end - attribute \src "ls180.v:1216.5-1216.53" - process $proc$ls180.v:1216$3375 + attribute \src "ls180.v:1221.5-1221.53" + process $proc$ls180.v:1221$3508 assign { } { } assign $1\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_cmdr_source_source_ready0 $1\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] end - attribute \src "ls180.v:1221.5-1221.36" - process $proc$ls180.v:1221$3376 + attribute \src "ls180.v:1226.5-1226.36" + process $proc$ls180.v:1226$3509 assign { } { } assign $1\main_sdphy_cmdr_cmdr_run[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_cmdr_run $1\main_sdphy_cmdr_cmdr_run[0:0] end - attribute \src "ls180.v:1224.5-1224.53" - process $proc$ls180.v:1224$3377 + attribute \src "ls180.v:1229.5-1229.53" + process $proc$ls180.v:1229$3510 assign { } { } assign $0\main_sdphy_cmdr_cmdr_converter_sink_first[0:0] 1'0 sync always update \main_sdphy_cmdr_cmdr_converter_sink_first $0\main_sdphy_cmdr_cmdr_converter_sink_first[0:0] sync init end - attribute \src "ls180.v:1225.5-1225.52" - process $proc$ls180.v:1225$3378 + attribute \src "ls180.v:1230.5-1230.52" + process $proc$ls180.v:1230$3511 assign { } { } assign $0\main_sdphy_cmdr_cmdr_converter_sink_last[0:0] 1'0 sync always update \main_sdphy_cmdr_cmdr_converter_sink_last $0\main_sdphy_cmdr_cmdr_converter_sink_last[0:0] sync init end - attribute \src "ls180.v:1229.5-1229.55" - process $proc$ls180.v:1229$3379 + attribute \src "ls180.v:1234.5-1234.55" + process $proc$ls180.v:1234$3512 assign { } { } assign $1\main_sdphy_cmdr_cmdr_converter_source_first[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_cmdr_converter_source_first $1\main_sdphy_cmdr_cmdr_converter_source_first[0:0] end - attribute \src "ls180.v:1230.5-1230.54" - process $proc$ls180.v:1230$3380 + attribute \src "ls180.v:1235.5-1235.54" + process $proc$ls180.v:1235$3513 assign { } { } assign $1\main_sdphy_cmdr_cmdr_converter_source_last[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_cmdr_converter_source_last $1\main_sdphy_cmdr_cmdr_converter_source_last[0:0] end - attribute \src "ls180.v:1231.11-1231.68" - process $proc$ls180.v:1231$3381 + attribute \src "ls180.v:1236.11-1236.68" + process $proc$ls180.v:1236$3514 assign { } { } assign $1\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] 8'00000000 sync always sync init update \main_sdphy_cmdr_cmdr_converter_source_payload_data $1\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] end - attribute \src "ls180.v:1232.11-1232.81" - process $proc$ls180.v:1232$3382 + attribute \src "ls180.v:1237.11-1237.81" + process $proc$ls180.v:1237$3515 assign { } { } assign $1\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] 4'0000 sync always sync init update \main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count $1\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] end - attribute \src "ls180.v:1233.11-1233.54" - process $proc$ls180.v:1233$3383 + attribute \src "ls180.v:1238.11-1238.54" + process $proc$ls180.v:1238$3516 assign { } { } assign $1\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000 sync always sync init update \main_sdphy_cmdr_cmdr_converter_demux $1\main_sdphy_cmdr_cmdr_converter_demux[2:0] end - attribute \src "ls180.v:1235.5-1235.53" - process $proc$ls180.v:1235$3384 + attribute \src "ls180.v:1240.5-1240.53" + process $proc$ls180.v:1240$3517 assign { } { } assign $1\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_cmdr_converter_strobe_all $1\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] end - attribute \src "ls180.v:1246.5-1246.49" - process $proc$ls180.v:1246$3385 + attribute \src "ls180.v:1251.5-1251.49" + process $proc$ls180.v:1251$3518 assign { } { } assign $1\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_cmdr_buf_source_valid $1\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] end - attribute \src "ls180.v:1248.5-1248.49" - process $proc$ls180.v:1248$3386 + attribute \src "ls180.v:1253.5-1253.49" + process $proc$ls180.v:1253$3519 assign { } { } assign $1\main_sdphy_cmdr_cmdr_buf_source_first[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_cmdr_buf_source_first $1\main_sdphy_cmdr_cmdr_buf_source_first[0:0] end - attribute \src "ls180.v:1249.5-1249.48" - process $proc$ls180.v:1249$3387 + attribute \src "ls180.v:1254.5-1254.48" + process $proc$ls180.v:1254$3520 assign { } { } assign $1\main_sdphy_cmdr_cmdr_buf_source_last[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_cmdr_buf_source_last $1\main_sdphy_cmdr_cmdr_buf_source_last[0:0] end - attribute \src "ls180.v:1250.11-1250.62" - process $proc$ls180.v:1250$3388 + attribute \src "ls180.v:1255.11-1255.62" + process $proc$ls180.v:1255$3521 assign { } { } assign $1\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] 8'00000000 sync always sync init update \main_sdphy_cmdr_cmdr_buf_source_payload_data $1\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] end - attribute \src "ls180.v:1251.5-1251.38" - process $proc$ls180.v:1251$3389 + attribute \src "ls180.v:1256.5-1256.38" + process $proc$ls180.v:1256$3522 assign { } { } assign $1\main_sdphy_cmdr_cmdr_reset[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_cmdr_reset $1\main_sdphy_cmdr_cmdr_reset[0:0] end - attribute \src "ls180.v:1256.5-1256.49" - process $proc$ls180.v:1256$3390 + attribute \src "ls180.v:1261.5-1261.49" + process $proc$ls180.v:1261$3523 assign { } { } assign $1\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'0 sync always sync init update \main_sdphy_dataw_pads_out_payload_clk $1\main_sdphy_dataw_pads_out_payload_clk[0:0] end - attribute \src "ls180.v:1257.5-1257.51" - process $proc$ls180.v:1257$3391 + attribute \src "ls180.v:1262.5-1262.51" + process $proc$ls180.v:1262$3524 assign { } { } assign $0\main_sdphy_dataw_pads_out_payload_cmd_o[0:0] 1'0 sync always update \main_sdphy_dataw_pads_out_payload_cmd_o $0\main_sdphy_dataw_pads_out_payload_cmd_o[0:0] sync init end - attribute \src "ls180.v:1258.5-1258.52" - process $proc$ls180.v:1258$3392 + attribute \src "ls180.v:1263.5-1263.52" + process $proc$ls180.v:1263$3525 assign { } { } assign $0\main_sdphy_dataw_pads_out_payload_cmd_oe[0:0] 1'0 sync always update \main_sdphy_dataw_pads_out_payload_cmd_oe $0\main_sdphy_dataw_pads_out_payload_cmd_oe[0:0] sync init end - attribute \src "ls180.v:1259.11-1259.58" - process $proc$ls180.v:1259$3393 + attribute \src "ls180.v:1264.11-1264.58" + process $proc$ls180.v:1264$3526 assign { } { } assign $1\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'0000 sync always sync init update \main_sdphy_dataw_pads_out_payload_data_o $1\main_sdphy_dataw_pads_out_payload_data_o[3:0] end - attribute \src "ls180.v:1260.5-1260.53" - process $proc$ls180.v:1260$3394 + attribute \src "ls180.v:1265.5-1265.53" + process $proc$ls180.v:1265$3527 assign { } { } assign $1\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'0 sync always sync init update \main_sdphy_dataw_pads_out_payload_data_oe $1\main_sdphy_dataw_pads_out_payload_data_oe[0:0] end - attribute \src "ls180.v:1261.5-1261.39" - process $proc$ls180.v:1261$3395 + attribute \src "ls180.v:1266.5-1266.39" + process $proc$ls180.v:1266$3528 assign { } { } assign $1\main_sdphy_dataw_sink_valid[0:0] 1'0 sync always sync init update \main_sdphy_dataw_sink_valid $1\main_sdphy_dataw_sink_valid[0:0] end - attribute \src "ls180.v:1262.5-1262.39" - process $proc$ls180.v:1262$3396 + attribute \src "ls180.v:1267.5-1267.39" + process $proc$ls180.v:1267$3529 assign { } { } assign $1\main_sdphy_dataw_sink_ready[0:0] 1'0 sync always sync init update \main_sdphy_dataw_sink_ready $1\main_sdphy_dataw_sink_ready[0:0] end - attribute \src "ls180.v:1263.5-1263.39" - process $proc$ls180.v:1263$3397 + attribute \src "ls180.v:1268.5-1268.39" + process $proc$ls180.v:1268$3530 assign { } { } assign $1\main_sdphy_dataw_sink_first[0:0] 1'0 sync always sync init update \main_sdphy_dataw_sink_first $1\main_sdphy_dataw_sink_first[0:0] end - attribute \src "ls180.v:1264.5-1264.38" - process $proc$ls180.v:1264$3398 + attribute \src "ls180.v:1269.5-1269.38" + process $proc$ls180.v:1269$3531 assign { } { } assign $1\main_sdphy_dataw_sink_last[0:0] 1'0 sync always sync init update \main_sdphy_dataw_sink_last $1\main_sdphy_dataw_sink_last[0:0] end - attribute \src "ls180.v:1265.11-1265.52" - process $proc$ls180.v:1265$3399 + attribute \src "ls180.v:1270.11-1270.52" + process $proc$ls180.v:1270$3532 assign { } { } assign $1\main_sdphy_dataw_sink_payload_data[7:0] 8'00000000 sync always sync init update \main_sdphy_dataw_sink_payload_data $1\main_sdphy_dataw_sink_payload_data[7:0] end - attribute \src "ls180.v:1266.5-1266.33" - process $proc$ls180.v:1266$3400 + attribute \src "ls180.v:1271.5-1271.33" + process $proc$ls180.v:1271$3533 assign { } { } assign $1\main_sdphy_dataw_stop[0:0] 1'0 sync always sync init update \main_sdphy_dataw_stop $1\main_sdphy_dataw_stop[0:0] end - attribute \src "ls180.v:1267.11-1267.40" - process $proc$ls180.v:1267$3401 + attribute \src "ls180.v:1272.11-1272.40" + process $proc$ls180.v:1272$3534 assign { } { } assign $1\main_sdphy_dataw_count[7:0] 8'00000000 sync always sync init update \main_sdphy_dataw_count $1\main_sdphy_dataw_count[7:0] end - attribute \src "ls180.v:1268.5-1268.50" - process $proc$ls180.v:1268$3402 + attribute \src "ls180.v:1273.5-1273.50" + process $proc$ls180.v:1273$3535 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_valid[0:0] 1'0 sync always update \main_sdphy_dataw_pads_in_pads_in_valid $0\main_sdphy_dataw_pads_in_pads_in_valid[0:0] sync init end - attribute \src "ls180.v:1270.5-1270.50" - process $proc$ls180.v:1270$3403 + attribute \src "ls180.v:1275.5-1275.50" + process $proc$ls180.v:1275$3536 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_first[0:0] 1'0 sync always update \main_sdphy_dataw_pads_in_pads_in_first $0\main_sdphy_dataw_pads_in_pads_in_first[0:0] sync init end - attribute \src "ls180.v:1271.5-1271.49" - process $proc$ls180.v:1271$3404 + attribute \src "ls180.v:1276.5-1276.49" + process $proc$ls180.v:1276$3537 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_last[0:0] 1'0 sync always update \main_sdphy_dataw_pads_in_pads_in_last $0\main_sdphy_dataw_pads_in_pads_in_last[0:0] sync init end - attribute \src "ls180.v:1272.5-1272.56" - process $proc$ls180.v:1272$3405 + attribute \src "ls180.v:1277.5-1277.56" + process $proc$ls180.v:1277$3538 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_payload_clk[0:0] 1'0 sync always update \main_sdphy_dataw_pads_in_pads_in_payload_clk $0\main_sdphy_dataw_pads_in_pads_in_payload_clk[0:0] sync init end - attribute \src "ls180.v:1273.5-1273.58" - process $proc$ls180.v:1273$3406 + attribute \src "ls180.v:1278.5-1278.58" + process $proc$ls180.v:1278$3539 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_i[0:0] 1'0 sync always update \main_sdphy_dataw_pads_in_pads_in_payload_cmd_i $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_i[0:0] sync init end - attribute \src "ls180.v:1274.5-1274.58" - process $proc$ls180.v:1274$3407 + attribute \src "ls180.v:1279.5-1279.58" + process $proc$ls180.v:1279$3540 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_o[0:0] 1'0 sync always update \main_sdphy_dataw_pads_in_pads_in_payload_cmd_o $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_o[0:0] sync init end - attribute \src "ls180.v:1275.5-1275.59" - process $proc$ls180.v:1275$3408 + attribute \src "ls180.v:1280.5-1280.59" + process $proc$ls180.v:1280$3541 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe[0:0] 1'0 sync always update \main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe[0:0] sync init end - attribute \src "ls180.v:1276.11-1276.65" - process $proc$ls180.v:1276$3409 + attribute \src "ls180.v:1281.11-1281.65" + process $proc$ls180.v:1281$3542 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_i[3:0] 4'0000 sync always update \main_sdphy_dataw_pads_in_pads_in_payload_data_i $0\main_sdphy_dataw_pads_in_pads_in_payload_data_i[3:0] sync init end - attribute \src "ls180.v:1277.11-1277.65" - process $proc$ls180.v:1277$3410 + attribute \src "ls180.v:1282.11-1282.65" + process $proc$ls180.v:1282$3543 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_o[3:0] 4'0000 sync always update \main_sdphy_dataw_pads_in_pads_in_payload_data_o $0\main_sdphy_dataw_pads_in_pads_in_payload_data_o[3:0] sync init end - attribute \src "ls180.v:1278.5-1278.60" - process $proc$ls180.v:1278$3411 + attribute \src "ls180.v:1283.5-1283.60" + process $proc$ls180.v:1283$3544 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_oe[0:0] 1'0 sync always update \main_sdphy_dataw_pads_in_pads_in_payload_data_oe $0\main_sdphy_dataw_pads_in_pads_in_payload_data_oe[0:0] sync init end - attribute \src "ls180.v:1279.5-1279.34" - process $proc$ls180.v:1279$3412 + attribute \src "ls180.v:1284.5-1284.34" + process $proc$ls180.v:1284$3545 assign { } { } assign $1\main_sdphy_dataw_start[0:0] 1'0 sync always sync init update \main_sdphy_dataw_start $1\main_sdphy_dataw_start[0:0] end - attribute \src "ls180.v:1280.5-1280.34" - process $proc$ls180.v:1280$3413 + attribute \src "ls180.v:1285.5-1285.34" + process $proc$ls180.v:1285$3546 assign { } { } assign $1\main_sdphy_dataw_valid[0:0] 1'0 sync always sync init update \main_sdphy_dataw_valid $1\main_sdphy_dataw_valid[0:0] end - attribute \src "ls180.v:1281.5-1281.34" - process $proc$ls180.v:1281$3414 + attribute \src "ls180.v:1286.5-1286.34" + process $proc$ls180.v:1286$3547 assign { } { } assign $1\main_sdphy_dataw_error[0:0] 1'0 sync always sync init update \main_sdphy_dataw_error $1\main_sdphy_dataw_error[0:0] end - attribute \src "ls180.v:1283.5-1283.47" - process $proc$ls180.v:1283$3415 + attribute \src "ls180.v:1288.5-1288.47" + process $proc$ls180.v:1288$3548 assign { } { } assign $0\main_sdphy_dataw_crcr_pads_in_ready[0:0] 1'0 sync always update \main_sdphy_dataw_crcr_pads_in_ready $0\main_sdphy_dataw_crcr_pads_in_ready[0:0] sync init end - attribute \src "ls180.v:1294.5-1294.54" - process $proc$ls180.v:1294$3416 + attribute \src "ls180.v:1299.5-1299.54" + process $proc$ls180.v:1299$3549 assign { } { } assign $1\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'0 sync always sync init update \main_sdphy_dataw_crcr_source_source_ready0 $1\main_sdphy_dataw_crcr_source_source_ready0[0:0] end - attribute \src "ls180.v:1299.5-1299.37" - process $proc$ls180.v:1299$3417 + attribute \src "ls180.v:1304.5-1304.37" + process $proc$ls180.v:1304$3550 assign { } { } assign $1\main_sdphy_dataw_crcr_run[0:0] 1'0 sync always sync init update \main_sdphy_dataw_crcr_run $1\main_sdphy_dataw_crcr_run[0:0] end - attribute \src "ls180.v:1302.5-1302.54" - process $proc$ls180.v:1302$3418 + attribute \src "ls180.v:1307.5-1307.54" + process $proc$ls180.v:1307$3551 assign { } { } assign $0\main_sdphy_dataw_crcr_converter_sink_first[0:0] 1'0 sync always update \main_sdphy_dataw_crcr_converter_sink_first $0\main_sdphy_dataw_crcr_converter_sink_first[0:0] sync init end - attribute \src "ls180.v:1303.5-1303.53" - process $proc$ls180.v:1303$3419 + attribute \src "ls180.v:1308.5-1308.53" + process $proc$ls180.v:1308$3552 assign { } { } assign $0\main_sdphy_dataw_crcr_converter_sink_last[0:0] 1'0 sync always update \main_sdphy_dataw_crcr_converter_sink_last $0\main_sdphy_dataw_crcr_converter_sink_last[0:0] sync init end - attribute \src "ls180.v:1307.5-1307.56" - process $proc$ls180.v:1307$3420 + attribute \src "ls180.v:1312.5-1312.56" + process $proc$ls180.v:1312$3553 assign { } { } assign $1\main_sdphy_dataw_crcr_converter_source_first[0:0] 1'0 sync always sync init update \main_sdphy_dataw_crcr_converter_source_first $1\main_sdphy_dataw_crcr_converter_source_first[0:0] end - attribute \src "ls180.v:1308.5-1308.55" - process $proc$ls180.v:1308$3421 + attribute \src "ls180.v:1313.5-1313.55" + process $proc$ls180.v:1313$3554 assign { } { } assign $1\main_sdphy_dataw_crcr_converter_source_last[0:0] 1'0 sync always sync init update \main_sdphy_dataw_crcr_converter_source_last $1\main_sdphy_dataw_crcr_converter_source_last[0:0] end - attribute \src "ls180.v:1309.11-1309.69" - process $proc$ls180.v:1309$3422 + attribute \src "ls180.v:1314.11-1314.69" + process $proc$ls180.v:1314$3555 assign { } { } assign $1\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] 8'00000000 sync always sync init update \main_sdphy_dataw_crcr_converter_source_payload_data $1\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] end - attribute \src "ls180.v:1310.11-1310.82" - process $proc$ls180.v:1310$3423 + attribute \src "ls180.v:1315.11-1315.82" + process $proc$ls180.v:1315$3556 assign { } { } assign $1\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] 4'0000 sync always sync init update \main_sdphy_dataw_crcr_converter_source_payload_valid_token_count $1\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] end - attribute \src "ls180.v:1311.11-1311.55" - process $proc$ls180.v:1311$3424 + attribute \src "ls180.v:1316.11-1316.55" + process $proc$ls180.v:1316$3557 assign { } { } assign $1\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000 sync always sync init update \main_sdphy_dataw_crcr_converter_demux $1\main_sdphy_dataw_crcr_converter_demux[2:0] end - attribute \src "ls180.v:1313.5-1313.54" - process $proc$ls180.v:1313$3425 + attribute \src "ls180.v:1318.5-1318.54" + process $proc$ls180.v:1318$3558 assign { } { } assign $1\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'0 sync always sync init update \main_sdphy_dataw_crcr_converter_strobe_all $1\main_sdphy_dataw_crcr_converter_strobe_all[0:0] end - attribute \src "ls180.v:1324.5-1324.50" - process $proc$ls180.v:1324$3426 + attribute \src "ls180.v:1329.5-1329.50" + process $proc$ls180.v:1329$3559 assign { } { } assign $1\main_sdphy_dataw_crcr_buf_source_valid[0:0] 1'0 sync always sync init update \main_sdphy_dataw_crcr_buf_source_valid $1\main_sdphy_dataw_crcr_buf_source_valid[0:0] end - attribute \src "ls180.v:1326.5-1326.50" - process $proc$ls180.v:1326$3427 + attribute \src "ls180.v:1331.5-1331.50" + process $proc$ls180.v:1331$3560 assign { } { } assign $1\main_sdphy_dataw_crcr_buf_source_first[0:0] 1'0 sync always sync init update \main_sdphy_dataw_crcr_buf_source_first $1\main_sdphy_dataw_crcr_buf_source_first[0:0] end - attribute \src "ls180.v:1327.5-1327.49" - process $proc$ls180.v:1327$3428 + attribute \src "ls180.v:1332.5-1332.49" + process $proc$ls180.v:1332$3561 assign { } { } assign $1\main_sdphy_dataw_crcr_buf_source_last[0:0] 1'0 sync always sync init update \main_sdphy_dataw_crcr_buf_source_last $1\main_sdphy_dataw_crcr_buf_source_last[0:0] end - attribute \src "ls180.v:1328.11-1328.63" - process $proc$ls180.v:1328$3429 + attribute \src "ls180.v:1333.11-1333.63" + process $proc$ls180.v:1333$3562 assign { } { } assign $1\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] 8'00000000 sync always sync init update \main_sdphy_dataw_crcr_buf_source_payload_data $1\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] end - attribute \src "ls180.v:1329.5-1329.39" - process $proc$ls180.v:1329$3430 + attribute \src "ls180.v:1334.5-1334.39" + process $proc$ls180.v:1334$3563 assign { } { } assign $1\main_sdphy_dataw_crcr_reset[0:0] 1'0 sync always sync init update \main_sdphy_dataw_crcr_reset $1\main_sdphy_dataw_crcr_reset[0:0] end - attribute \src "ls180.v:1332.5-1332.50" - process $proc$ls180.v:1332$3431 + attribute \src "ls180.v:1337.5-1337.50" + process $proc$ls180.v:1337$3564 assign { } { } assign $0\main_sdphy_datar_pads_in_pads_in_first[0:0] 1'0 sync always update \main_sdphy_datar_pads_in_pads_in_first $0\main_sdphy_datar_pads_in_pads_in_first[0:0] sync init end - attribute \src "ls180.v:1333.5-1333.49" - process $proc$ls180.v:1333$3432 + attribute \src "ls180.v:1338.5-1338.49" + process $proc$ls180.v:1338$3565 assign { } { } assign $0\main_sdphy_datar_pads_in_pads_in_last[0:0] 1'0 sync always update \main_sdphy_datar_pads_in_pads_in_last $0\main_sdphy_datar_pads_in_pads_in_last[0:0] sync init end - attribute \src "ls180.v:1334.5-1334.56" - process $proc$ls180.v:1334$3433 + attribute \src "ls180.v:1339.5-1339.56" + process $proc$ls180.v:1339$3566 assign { } { } assign $0\main_sdphy_datar_pads_in_pads_in_payload_clk[0:0] 1'0 sync always update \main_sdphy_datar_pads_in_pads_in_payload_clk $0\main_sdphy_datar_pads_in_pads_in_payload_clk[0:0] sync init end - attribute \src "ls180.v:1336.5-1336.58" - process $proc$ls180.v:1336$3434 + attribute \src "ls180.v:1341.5-1341.58" + process $proc$ls180.v:1341$3567 assign { } { } assign $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_o[0:0] 1'0 sync always update \main_sdphy_datar_pads_in_pads_in_payload_cmd_o $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_o[0:0] sync init end - attribute \src "ls180.v:1337.5-1337.59" - process $proc$ls180.v:1337$3435 + attribute \src "ls180.v:1342.5-1342.59" + process $proc$ls180.v:1342$3568 assign { } { } assign $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_oe[0:0] 1'0 sync always update \main_sdphy_datar_pads_in_pads_in_payload_cmd_oe $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_oe[0:0] sync init end - attribute \src "ls180.v:1339.11-1339.65" - process $proc$ls180.v:1339$3436 + attribute \src "ls180.v:1344.11-1344.65" + process $proc$ls180.v:1344$3569 assign { } { } assign $0\main_sdphy_datar_pads_in_pads_in_payload_data_o[3:0] 4'0000 sync always update \main_sdphy_datar_pads_in_pads_in_payload_data_o $0\main_sdphy_datar_pads_in_pads_in_payload_data_o[3:0] sync init end - attribute \src "ls180.v:1340.5-1340.60" - process $proc$ls180.v:1340$3437 + attribute \src "ls180.v:1345.5-1345.60" + process $proc$ls180.v:1345$3570 assign { } { } assign $0\main_sdphy_datar_pads_in_pads_in_payload_data_oe[0:0] 1'0 sync always update \main_sdphy_datar_pads_in_pads_in_payload_data_oe $0\main_sdphy_datar_pads_in_pads_in_payload_data_oe[0:0] sync init end - attribute \src "ls180.v:1342.5-1342.49" - process $proc$ls180.v:1342$3438 + attribute \src "ls180.v:1347.5-1347.49" + process $proc$ls180.v:1347$3571 assign { } { } assign $1\main_sdphy_datar_pads_out_payload_clk[0:0] 1'0 sync always sync init update \main_sdphy_datar_pads_out_payload_clk $1\main_sdphy_datar_pads_out_payload_clk[0:0] end - attribute \src "ls180.v:1343.5-1343.51" - process $proc$ls180.v:1343$3439 + attribute \src "ls180.v:1348.5-1348.51" + process $proc$ls180.v:1348$3572 assign { } { } assign $0\main_sdphy_datar_pads_out_payload_cmd_o[0:0] 1'0 sync always update \main_sdphy_datar_pads_out_payload_cmd_o $0\main_sdphy_datar_pads_out_payload_cmd_o[0:0] sync init end - attribute \src "ls180.v:1344.5-1344.52" - process $proc$ls180.v:1344$3440 + attribute \src "ls180.v:1349.5-1349.52" + process $proc$ls180.v:1349$3573 assign { } { } assign $0\main_sdphy_datar_pads_out_payload_cmd_oe[0:0] 1'0 sync always update \main_sdphy_datar_pads_out_payload_cmd_oe $0\main_sdphy_datar_pads_out_payload_cmd_oe[0:0] sync init end - attribute \src "ls180.v:1345.11-1345.58" - process $proc$ls180.v:1345$3441 + attribute \src "ls180.v:1350.11-1350.58" + process $proc$ls180.v:1350$3574 assign { } { } assign $0\main_sdphy_datar_pads_out_payload_data_o[3:0] 4'0000 sync always update \main_sdphy_datar_pads_out_payload_data_o $0\main_sdphy_datar_pads_out_payload_data_o[3:0] sync init end - attribute \src "ls180.v:1346.5-1346.53" - process $proc$ls180.v:1346$3442 + attribute \src "ls180.v:1351.5-1351.53" + process $proc$ls180.v:1351$3575 assign { } { } assign $0\main_sdphy_datar_pads_out_payload_data_oe[0:0] 1'0 sync always update \main_sdphy_datar_pads_out_payload_data_oe $0\main_sdphy_datar_pads_out_payload_data_oe[0:0] sync init end - attribute \src "ls180.v:1347.5-1347.39" - process $proc$ls180.v:1347$3443 + attribute \src "ls180.v:1352.5-1352.39" + process $proc$ls180.v:1352$3576 assign { } { } assign $1\main_sdphy_datar_sink_valid[0:0] 1'0 sync always sync init update \main_sdphy_datar_sink_valid $1\main_sdphy_datar_sink_valid[0:0] end - attribute \src "ls180.v:1348.5-1348.39" - process $proc$ls180.v:1348$3444 + attribute \src "ls180.v:1353.5-1353.39" + process $proc$ls180.v:1353$3577 assign { } { } assign $1\main_sdphy_datar_sink_ready[0:0] 1'0 sync always sync init update \main_sdphy_datar_sink_ready $1\main_sdphy_datar_sink_ready[0:0] end - attribute \src "ls180.v:1349.5-1349.38" - process $proc$ls180.v:1349$3445 + attribute \src "ls180.v:1354.5-1354.38" + process $proc$ls180.v:1354$3578 assign { } { } assign $1\main_sdphy_datar_sink_last[0:0] 1'0 sync always sync init update \main_sdphy_datar_sink_last $1\main_sdphy_datar_sink_last[0:0] end - attribute \src "ls180.v:1350.11-1350.61" - process $proc$ls180.v:1350$3446 + attribute \src "ls180.v:1355.11-1355.61" + process $proc$ls180.v:1355$3579 assign { } { } assign $1\main_sdphy_datar_sink_payload_block_length[9:0] 10'0000000000 sync always sync init update \main_sdphy_datar_sink_payload_block_length $1\main_sdphy_datar_sink_payload_block_length[9:0] end - attribute \src "ls180.v:1351.5-1351.41" - process $proc$ls180.v:1351$3447 + attribute \src "ls180.v:1356.5-1356.41" + process $proc$ls180.v:1356$3580 assign { } { } assign $1\main_sdphy_datar_source_valid[0:0] 1'0 sync always sync init update \main_sdphy_datar_source_valid $1\main_sdphy_datar_source_valid[0:0] end - attribute \src "ls180.v:1352.5-1352.41" - process $proc$ls180.v:1352$3448 + attribute \src "ls180.v:1357.5-1357.41" + process $proc$ls180.v:1357$3581 assign { } { } assign $1\main_sdphy_datar_source_ready[0:0] 1'0 sync always sync init update \main_sdphy_datar_source_ready $1\main_sdphy_datar_source_ready[0:0] end - attribute \src "ls180.v:1353.5-1353.41" - process $proc$ls180.v:1353$3449 + attribute \src "ls180.v:1358.5-1358.41" + process $proc$ls180.v:1358$3582 assign { } { } assign $0\main_sdphy_datar_source_first[0:0] 1'0 sync always update \main_sdphy_datar_source_first $0\main_sdphy_datar_source_first[0:0] sync init end - attribute \src "ls180.v:1354.5-1354.40" - process $proc$ls180.v:1354$3450 + attribute \src "ls180.v:1359.5-1359.40" + process $proc$ls180.v:1359$3583 assign { } { } assign $1\main_sdphy_datar_source_last[0:0] 1'0 sync always sync init update \main_sdphy_datar_source_last $1\main_sdphy_datar_source_last[0:0] end - attribute \src "ls180.v:1355.11-1355.54" - process $proc$ls180.v:1355$3451 + attribute \src "ls180.v:1360.11-1360.54" + process $proc$ls180.v:1360$3584 assign { } { } assign $1\main_sdphy_datar_source_payload_data[7:0] 8'00000000 sync always sync init update \main_sdphy_datar_source_payload_data $1\main_sdphy_datar_source_payload_data[7:0] end - attribute \src "ls180.v:1356.11-1356.56" - process $proc$ls180.v:1356$3452 + attribute \src "ls180.v:1361.11-1361.56" + process $proc$ls180.v:1361$3585 assign { } { } assign $1\main_sdphy_datar_source_payload_status[2:0] 3'000 sync always sync init update \main_sdphy_datar_source_payload_status $1\main_sdphy_datar_source_payload_status[2:0] end - attribute \src "ls180.v:1357.5-1357.33" - process $proc$ls180.v:1357$3453 + attribute \src "ls180.v:1362.5-1362.33" + process $proc$ls180.v:1362$3586 assign { } { } assign $1\main_sdphy_datar_stop[0:0] 1'0 sync always sync init update \main_sdphy_datar_stop $1\main_sdphy_datar_stop[0:0] end - attribute \src "ls180.v:1358.12-1358.49" - process $proc$ls180.v:1358$3454 + attribute \src "ls180.v:1363.12-1363.49" + process $proc$ls180.v:1363$3587 assign { } { } assign $1\main_sdphy_datar_timeout[31:0] 500000 sync always sync init update \main_sdphy_datar_timeout $1\main_sdphy_datar_timeout[31:0] end - attribute \src "ls180.v:1359.11-1359.41" - process $proc$ls180.v:1359$3455 + attribute \src "ls180.v:1364.11-1364.41" + process $proc$ls180.v:1364$3588 assign { } { } assign $1\main_sdphy_datar_count[9:0] 10'0000000000 sync always sync init update \main_sdphy_datar_count $1\main_sdphy_datar_count[9:0] end - attribute \src "ls180.v:1361.5-1361.48" - process $proc$ls180.v:1361$3456 + attribute \src "ls180.v:1366.5-1366.48" + process $proc$ls180.v:1366$3589 assign { } { } assign $0\main_sdphy_datar_datar_pads_in_ready[0:0] 1'0 sync always update \main_sdphy_datar_datar_pads_in_ready $0\main_sdphy_datar_datar_pads_in_ready[0:0] sync init end - attribute \src "ls180.v:1372.5-1372.55" - process $proc$ls180.v:1372$3457 + attribute \src "ls180.v:1377.5-1377.55" + process $proc$ls180.v:1377$3590 assign { } { } assign $1\main_sdphy_datar_datar_source_source_ready0[0:0] 1'0 sync always sync init update \main_sdphy_datar_datar_source_source_ready0 $1\main_sdphy_datar_datar_source_source_ready0[0:0] end - attribute \src "ls180.v:1377.5-1377.38" - process $proc$ls180.v:1377$3458 + attribute \src "ls180.v:1382.5-1382.38" + process $proc$ls180.v:1382$3591 assign { } { } assign $1\main_sdphy_datar_datar_run[0:0] 1'0 sync always sync init update \main_sdphy_datar_datar_run $1\main_sdphy_datar_datar_run[0:0] end - attribute \src "ls180.v:1380.5-1380.55" - process $proc$ls180.v:1380$3459 + attribute \src "ls180.v:1385.5-1385.55" + process $proc$ls180.v:1385$3592 assign { } { } assign $0\main_sdphy_datar_datar_converter_sink_first[0:0] 1'0 sync always update \main_sdphy_datar_datar_converter_sink_first $0\main_sdphy_datar_datar_converter_sink_first[0:0] sync init end - attribute \src "ls180.v:1381.5-1381.54" - process $proc$ls180.v:1381$3460 + attribute \src "ls180.v:1386.5-1386.54" + process $proc$ls180.v:1386$3593 assign { } { } assign $0\main_sdphy_datar_datar_converter_sink_last[0:0] 1'0 sync always update \main_sdphy_datar_datar_converter_sink_last $0\main_sdphy_datar_datar_converter_sink_last[0:0] sync init end - attribute \src "ls180.v:1385.5-1385.57" - process $proc$ls180.v:1385$3461 + attribute \src "ls180.v:1390.5-1390.57" + process $proc$ls180.v:1390$3594 assign { } { } assign $1\main_sdphy_datar_datar_converter_source_first[0:0] 1'0 sync always sync init update \main_sdphy_datar_datar_converter_source_first $1\main_sdphy_datar_datar_converter_source_first[0:0] end - attribute \src "ls180.v:1386.5-1386.56" - process $proc$ls180.v:1386$3462 + attribute \src "ls180.v:1391.5-1391.56" + process $proc$ls180.v:1391$3595 assign { } { } assign $1\main_sdphy_datar_datar_converter_source_last[0:0] 1'0 sync always sync init update \main_sdphy_datar_datar_converter_source_last $1\main_sdphy_datar_datar_converter_source_last[0:0] end - attribute \src "ls180.v:1387.11-1387.70" - process $proc$ls180.v:1387$3463 + attribute \src "ls180.v:1392.11-1392.70" + process $proc$ls180.v:1392$3596 assign { } { } assign $1\main_sdphy_datar_datar_converter_source_payload_data[7:0] 8'00000000 sync always sync init update \main_sdphy_datar_datar_converter_source_payload_data $1\main_sdphy_datar_datar_converter_source_payload_data[7:0] end - attribute \src "ls180.v:1388.11-1388.83" - process $proc$ls180.v:1388$3464 + attribute \src "ls180.v:1393.11-1393.83" + process $proc$ls180.v:1393$3597 assign { } { } assign $1\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] 2'00 sync always sync init update \main_sdphy_datar_datar_converter_source_payload_valid_token_count $1\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] end - attribute \src "ls180.v:1389.5-1389.50" - process $proc$ls180.v:1389$3465 + attribute \src "ls180.v:1394.5-1394.50" + process $proc$ls180.v:1394$3598 assign { } { } assign $1\main_sdphy_datar_datar_converter_demux[0:0] 1'0 sync always sync init update \main_sdphy_datar_datar_converter_demux $1\main_sdphy_datar_datar_converter_demux[0:0] end - attribute \src "ls180.v:1391.5-1391.55" - process $proc$ls180.v:1391$3466 + attribute \src "ls180.v:1396.5-1396.55" + process $proc$ls180.v:1396$3599 assign { } { } assign $1\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'0 sync always sync init update \main_sdphy_datar_datar_converter_strobe_all $1\main_sdphy_datar_datar_converter_strobe_all[0:0] end - attribute \src "ls180.v:1402.5-1402.51" - process $proc$ls180.v:1402$3467 + attribute \src "ls180.v:1407.5-1407.51" + process $proc$ls180.v:1407$3600 assign { } { } assign $1\main_sdphy_datar_datar_buf_source_valid[0:0] 1'0 sync always sync init update \main_sdphy_datar_datar_buf_source_valid $1\main_sdphy_datar_datar_buf_source_valid[0:0] end - attribute \src "ls180.v:1404.5-1404.51" - process $proc$ls180.v:1404$3468 + attribute \src "ls180.v:1409.5-1409.51" + process $proc$ls180.v:1409$3601 assign { } { } assign $1\main_sdphy_datar_datar_buf_source_first[0:0] 1'0 sync always sync init update \main_sdphy_datar_datar_buf_source_first $1\main_sdphy_datar_datar_buf_source_first[0:0] end - attribute \src "ls180.v:1405.5-1405.50" - process $proc$ls180.v:1405$3469 + attribute \src "ls180.v:1410.5-1410.50" + process $proc$ls180.v:1410$3602 assign { } { } assign $1\main_sdphy_datar_datar_buf_source_last[0:0] 1'0 sync always sync init update \main_sdphy_datar_datar_buf_source_last $1\main_sdphy_datar_datar_buf_source_last[0:0] end - attribute \src "ls180.v:1406.11-1406.64" - process $proc$ls180.v:1406$3470 + attribute \src "ls180.v:1411.11-1411.64" + process $proc$ls180.v:1411$3603 assign { } { } assign $1\main_sdphy_datar_datar_buf_source_payload_data[7:0] 8'00000000 sync always sync init update \main_sdphy_datar_datar_buf_source_payload_data $1\main_sdphy_datar_datar_buf_source_payload_data[7:0] end - attribute \src "ls180.v:1407.5-1407.40" - process $proc$ls180.v:1407$3471 + attribute \src "ls180.v:1412.5-1412.40" + process $proc$ls180.v:1412$3604 assign { } { } assign $1\main_sdphy_datar_datar_reset[0:0] 1'0 sync always sync init update \main_sdphy_datar_datar_reset $1\main_sdphy_datar_datar_reset[0:0] end - attribute \src "ls180.v:1409.5-1409.35" - process $proc$ls180.v:1409$3472 + attribute \src "ls180.v:1414.5-1414.35" + process $proc$ls180.v:1414$3605 assign { } { } assign $1\main_sdphy_sdpads_cmd_i[0:0] 1'0 sync always sync init update \main_sdphy_sdpads_cmd_i $1\main_sdphy_sdpads_cmd_i[0:0] end - attribute \src "ls180.v:1412.11-1412.42" - process $proc$ls180.v:1412$3473 + attribute \src "ls180.v:1417.11-1417.42" + process $proc$ls180.v:1417$3606 assign { } { } assign $1\main_sdphy_sdpads_data_i[3:0] 4'0000 sync always sync init update \main_sdphy_sdpads_data_i $1\main_sdphy_sdpads_data_i[3:0] end - attribute \src "ls180.v:1425.12-1425.52" - process $proc$ls180.v:1425$3474 + attribute \src "ls180.v:1430.12-1430.52" + process $proc$ls180.v:1430$3607 assign { } { } assign $1\main_sdcore_cmd_argument_storage[31:0] 0 sync always sync init update \main_sdcore_cmd_argument_storage $1\main_sdcore_cmd_argument_storage[31:0] end - attribute \src "ls180.v:1426.5-1426.39" - process $proc$ls180.v:1426$3475 + attribute \src "ls180.v:1431.5-1431.39" + process $proc$ls180.v:1431$3608 assign { } { } assign $1\main_sdcore_cmd_argument_re[0:0] 1'0 sync always sync init update \main_sdcore_cmd_argument_re $1\main_sdcore_cmd_argument_re[0:0] end - attribute \src "ls180.v:1427.12-1427.51" - process $proc$ls180.v:1427$3476 + attribute \src "ls180.v:1432.12-1432.51" + process $proc$ls180.v:1432$3609 assign { } { } assign $1\main_sdcore_cmd_command_storage[31:0] 0 sync always sync init update \main_sdcore_cmd_command_storage $1\main_sdcore_cmd_command_storage[31:0] end - attribute \src "ls180.v:1428.5-1428.38" - process $proc$ls180.v:1428$3477 + attribute \src "ls180.v:1433.5-1433.38" + process $proc$ls180.v:1433$3610 assign { } { } assign $1\main_sdcore_cmd_command_re[0:0] 1'0 sync always sync init update \main_sdcore_cmd_command_re $1\main_sdcore_cmd_command_re[0:0] end - attribute \src "ls180.v:1432.5-1432.34" - process $proc$ls180.v:1432$3478 + attribute \src "ls180.v:1437.5-1437.34" + process $proc$ls180.v:1437$3611 assign { } { } assign $0\main_sdcore_cmd_send_w[0:0] 1'0 sync always update \main_sdcore_cmd_send_w $0\main_sdcore_cmd_send_w[0:0] sync init end - attribute \src "ls180.v:1433.13-1433.53" - process $proc$ls180.v:1433$3479 + attribute \src "ls180.v:1438.13-1438.53" + process $proc$ls180.v:1438$3612 assign { } { } assign $1\main_sdcore_cmd_response_status[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \main_sdcore_cmd_response_status $1\main_sdcore_cmd_response_status[127:0] end - attribute \src "ls180.v:1439.11-1439.51" - process $proc$ls180.v:1439$3480 + attribute \src "ls180.v:1444.11-1444.51" + process $proc$ls180.v:1444$3613 assign { } { } assign $1\main_sdcore_block_length_storage[9:0] 10'0000000000 sync always sync init update \main_sdcore_block_length_storage $1\main_sdcore_block_length_storage[9:0] end - attribute \src "ls180.v:1440.5-1440.39" - process $proc$ls180.v:1440$3481 + attribute \src "ls180.v:1445.5-1445.39" + process $proc$ls180.v:1445$3614 assign { } { } assign $1\main_sdcore_block_length_re[0:0] 1'0 sync always sync init update \main_sdcore_block_length_re $1\main_sdcore_block_length_re[0:0] end - attribute \src "ls180.v:1441.12-1441.51" - process $proc$ls180.v:1441$3482 + attribute \src "ls180.v:1446.12-1446.51" + process $proc$ls180.v:1446$3615 assign { } { } assign $1\main_sdcore_block_count_storage[31:0] 0 sync always sync init update \main_sdcore_block_count_storage $1\main_sdcore_block_count_storage[31:0] end - attribute \src "ls180.v:1442.5-1442.38" - process $proc$ls180.v:1442$3483 + attribute \src "ls180.v:1447.5-1447.38" + process $proc$ls180.v:1447$3616 assign { } { } assign $1\main_sdcore_block_count_re[0:0] 1'0 sync always sync init update \main_sdcore_block_count_re $1\main_sdcore_block_count_re[0:0] end - attribute \src "ls180.v:1443.11-1443.51" - process $proc$ls180.v:1443$3484 + attribute \src "ls180.v:1448.11-1448.51" + process $proc$ls180.v:1448$3617 assign { } { } assign $1\main_sdcore_crc7_inserter_crcreg0[6:0] 7'0000000 sync always sync init update \main_sdcore_crc7_inserter_crcreg0 $1\main_sdcore_crc7_inserter_crcreg0[6:0] end - attribute \src "ls180.v:1485.11-1485.47" - process $proc$ls180.v:1485$3485 + attribute \src "ls180.v:1490.11-1490.47" + process $proc$ls180.v:1490$3618 assign { } { } assign $1\main_sdcore_crc7_inserter_crc[6:0] 7'0000000 sync always sync init update \main_sdcore_crc7_inserter_crc $1\main_sdcore_crc7_inserter_crc[6:0] end - attribute \src "ls180.v:1489.5-1489.49" - process $proc$ls180.v:1489$3486 + attribute \src "ls180.v:1494.5-1494.49" + process $proc$ls180.v:1494$3619 assign { } { } assign $1\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0 sync always sync init update \main_sdcore_crc16_inserter_sink_ready $1\main_sdcore_crc16_inserter_sink_ready[0:0] end - attribute \src "ls180.v:1493.5-1493.51" - process $proc$ls180.v:1493$3487 + attribute \src "ls180.v:1498.5-1498.51" + process $proc$ls180.v:1498$3620 assign { } { } assign $1\main_sdcore_crc16_inserter_source_valid[0:0] 1'0 sync always sync init update \main_sdcore_crc16_inserter_source_valid $1\main_sdcore_crc16_inserter_source_valid[0:0] end - attribute \src "ls180.v:1494.5-1494.51" - process $proc$ls180.v:1494$3488 + attribute \src "ls180.v:1499.5-1499.51" + process $proc$ls180.v:1499$3621 assign { } { } assign $1\main_sdcore_crc16_inserter_source_ready[0:0] 1'0 sync always sync init update \main_sdcore_crc16_inserter_source_ready $1\main_sdcore_crc16_inserter_source_ready[0:0] end - attribute \src "ls180.v:1495.5-1495.51" - process $proc$ls180.v:1495$3489 + attribute \src "ls180.v:1500.5-1500.51" + process $proc$ls180.v:1500$3622 assign { } { } assign $0\main_sdcore_crc16_inserter_source_first[0:0] 1'0 sync always update \main_sdcore_crc16_inserter_source_first $0\main_sdcore_crc16_inserter_source_first[0:0] sync init end - attribute \src "ls180.v:1496.5-1496.50" - process $proc$ls180.v:1496$3490 + attribute \src "ls180.v:1501.5-1501.50" + process $proc$ls180.v:1501$3623 assign { } { } assign $1\main_sdcore_crc16_inserter_source_last[0:0] 1'0 sync always sync init update \main_sdcore_crc16_inserter_source_last $1\main_sdcore_crc16_inserter_source_last[0:0] end - attribute \src "ls180.v:1497.11-1497.64" - process $proc$ls180.v:1497$3491 + attribute \src "ls180.v:1502.11-1502.64" + process $proc$ls180.v:1502$3624 assign { } { } assign $1\main_sdcore_crc16_inserter_source_payload_data[7:0] 8'00000000 sync always sync init update \main_sdcore_crc16_inserter_source_payload_data $1\main_sdcore_crc16_inserter_source_payload_data[7:0] end - attribute \src "ls180.v:1498.11-1498.48" - process $proc$ls180.v:1498$3492 + attribute \src "ls180.v:1503.11-1503.48" + process $proc$ls180.v:1503$3625 assign { } { } assign $1\main_sdcore_crc16_inserter_cnt[2:0] 3'000 sync always sync init update \main_sdcore_crc16_inserter_cnt $1\main_sdcore_crc16_inserter_cnt[2:0] end - attribute \src "ls180.v:1499.12-1499.59" - process $proc$ls180.v:1499$3493 + attribute \src "ls180.v:1504.12-1504.59" + process $proc$ls180.v:1504$3626 assign { } { } assign $1\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crc0_crcreg0 $1\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] end - attribute \src "ls180.v:1503.12-1503.55" - process $proc$ls180.v:1503$3494 + attribute \src "ls180.v:1508.12-1508.55" + process $proc$ls180.v:1508$3627 assign { } { } assign $1\main_sdcore_crc16_inserter_crc0_crc[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crc0_crc $1\main_sdcore_crc16_inserter_crc0_crc[15:0] end - attribute \src "ls180.v:1506.12-1506.59" - process $proc$ls180.v:1506$3495 + attribute \src "ls180.v:1511.12-1511.59" + process $proc$ls180.v:1511$3628 assign { } { } assign $1\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crc1_crcreg0 $1\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] end - attribute \src "ls180.v:1510.12-1510.55" - process $proc$ls180.v:1510$3496 + attribute \src "ls180.v:1515.12-1515.55" + process $proc$ls180.v:1515$3629 assign { } { } assign $1\main_sdcore_crc16_inserter_crc1_crc[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crc1_crc $1\main_sdcore_crc16_inserter_crc1_crc[15:0] end - attribute \src "ls180.v:1513.12-1513.59" - process $proc$ls180.v:1513$3497 + attribute \src "ls180.v:1518.12-1518.59" + process $proc$ls180.v:1518$3630 assign { } { } assign $1\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crc2_crcreg0 $1\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] end - attribute \src "ls180.v:1517.12-1517.55" - process $proc$ls180.v:1517$3498 + attribute \src "ls180.v:1522.12-1522.55" + process $proc$ls180.v:1522$3631 assign { } { } assign $1\main_sdcore_crc16_inserter_crc2_crc[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crc2_crc $1\main_sdcore_crc16_inserter_crc2_crc[15:0] end - attribute \src "ls180.v:1520.12-1520.59" - process $proc$ls180.v:1520$3499 + attribute \src "ls180.v:1525.12-1525.59" + process $proc$ls180.v:1525$3632 assign { } { } assign $1\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crc3_crcreg0 $1\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] end - attribute \src "ls180.v:1524.12-1524.55" - process $proc$ls180.v:1524$3500 + attribute \src "ls180.v:1529.12-1529.55" + process $proc$ls180.v:1529$3633 assign { } { } assign $1\main_sdcore_crc16_inserter_crc3_crc[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crc3_crc $1\main_sdcore_crc16_inserter_crc3_crc[15:0] end - attribute \src "ls180.v:1527.12-1527.54" - process $proc$ls180.v:1527$3501 + attribute \src "ls180.v:1532.12-1532.54" + process $proc$ls180.v:1532$3634 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp0[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crctmp0 $1\main_sdcore_crc16_inserter_crctmp0[15:0] end - attribute \src "ls180.v:1528.12-1528.54" - process $proc$ls180.v:1528$3502 + attribute \src "ls180.v:1533.12-1533.54" + process $proc$ls180.v:1533$3635 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp1[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crctmp1 $1\main_sdcore_crc16_inserter_crctmp1[15:0] end - attribute \src "ls180.v:1529.12-1529.54" - process $proc$ls180.v:1529$3503 + attribute \src "ls180.v:1534.12-1534.54" + process $proc$ls180.v:1534$3636 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp2[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crctmp2 $1\main_sdcore_crc16_inserter_crctmp2[15:0] end - attribute \src "ls180.v:1530.12-1530.54" - process $proc$ls180.v:1530$3504 + attribute \src "ls180.v:1535.12-1535.54" + process $proc$ls180.v:1535$3637 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp3[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crctmp3 $1\main_sdcore_crc16_inserter_crctmp3[15:0] end - attribute \src "ls180.v:1531.5-1531.48" - process $proc$ls180.v:1531$3505 + attribute \src "ls180.v:1536.5-1536.48" + process $proc$ls180.v:1536$3638 assign { } { } assign $1\main_sdcore_crc16_checker_sink_valid[0:0] 1'0 sync always sync init update \main_sdcore_crc16_checker_sink_valid $1\main_sdcore_crc16_checker_sink_valid[0:0] end - attribute \src "ls180.v:1532.5-1532.48" - process $proc$ls180.v:1532$3506 + attribute \src "ls180.v:1537.5-1537.48" + process $proc$ls180.v:1537$3639 assign { } { } assign $1\main_sdcore_crc16_checker_sink_ready[0:0] 1'0 sync always sync init update \main_sdcore_crc16_checker_sink_ready $1\main_sdcore_crc16_checker_sink_ready[0:0] end - attribute \src "ls180.v:1533.5-1533.48" - process $proc$ls180.v:1533$3507 + attribute \src "ls180.v:1538.5-1538.48" + process $proc$ls180.v:1538$3640 assign { } { } assign $1\main_sdcore_crc16_checker_sink_first[0:0] 1'0 sync always sync init update \main_sdcore_crc16_checker_sink_first $1\main_sdcore_crc16_checker_sink_first[0:0] end - attribute \src "ls180.v:1534.5-1534.47" - process $proc$ls180.v:1534$3508 + attribute \src "ls180.v:1539.5-1539.47" + process $proc$ls180.v:1539$3641 assign { } { } assign $1\main_sdcore_crc16_checker_sink_last[0:0] 1'0 sync always sync init update \main_sdcore_crc16_checker_sink_last $1\main_sdcore_crc16_checker_sink_last[0:0] end - attribute \src "ls180.v:1535.11-1535.61" - process $proc$ls180.v:1535$3509 + attribute \src "ls180.v:1540.11-1540.61" + process $proc$ls180.v:1540$3642 assign { } { } assign $1\main_sdcore_crc16_checker_sink_payload_data[7:0] 8'00000000 sync always sync init update \main_sdcore_crc16_checker_sink_payload_data $1\main_sdcore_crc16_checker_sink_payload_data[7:0] end - attribute \src "ls180.v:1536.5-1536.50" - process $proc$ls180.v:1536$3510 + attribute \src "ls180.v:1541.5-1541.50" + process $proc$ls180.v:1541$3643 assign { } { } assign $1\main_sdcore_crc16_checker_source_valid[0:0] 1'0 sync always sync init update \main_sdcore_crc16_checker_source_valid $1\main_sdcore_crc16_checker_source_valid[0:0] end - attribute \src "ls180.v:1538.5-1538.50" - process $proc$ls180.v:1538$3511 + attribute \src "ls180.v:1543.5-1543.50" + process $proc$ls180.v:1543$3644 assign { } { } assign $0\main_sdcore_crc16_checker_source_first[0:0] 1'0 sync always update \main_sdcore_crc16_checker_source_first $0\main_sdcore_crc16_checker_source_first[0:0] sync init end - attribute \src "ls180.v:1541.11-1541.47" - process $proc$ls180.v:1541$3512 + attribute \src "ls180.v:1546.11-1546.47" + process $proc$ls180.v:1546$3645 assign { } { } assign $1\main_sdcore_crc16_checker_val[7:0] 8'00000000 sync always sync init update \main_sdcore_crc16_checker_val $1\main_sdcore_crc16_checker_val[7:0] end - attribute \src "ls180.v:1542.11-1542.47" - process $proc$ls180.v:1542$3513 + attribute \src "ls180.v:1547.11-1547.47" + process $proc$ls180.v:1547$3646 assign { } { } assign $1\main_sdcore_crc16_checker_cnt[3:0] 4'0000 sync always sync init update \main_sdcore_crc16_checker_cnt $1\main_sdcore_crc16_checker_cnt[3:0] end - attribute \src "ls180.v:1543.12-1543.58" - process $proc$ls180.v:1543$3514 + attribute \src "ls180.v:1548.12-1548.58" + process $proc$ls180.v:1548$3647 assign { } { } assign $1\main_sdcore_crc16_checker_crc0_crcreg0[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_crc0_crcreg0 $1\main_sdcore_crc16_checker_crc0_crcreg0[15:0] end - attribute \src "ls180.v:1547.12-1547.54" - process $proc$ls180.v:1547$3515 + attribute \src "ls180.v:1552.12-1552.54" + process $proc$ls180.v:1552$3648 assign { } { } assign $1\main_sdcore_crc16_checker_crc0_crc[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_crc0_crc $1\main_sdcore_crc16_checker_crc0_crc[15:0] end - attribute \src "ls180.v:1548.5-1548.46" - process $proc$ls180.v:1548$3516 + attribute \src "ls180.v:1553.5-1553.46" + process $proc$ls180.v:1553$3649 assign { } { } assign $1\main_sdcore_crc16_checker_crc0_clr[0:0] 1'0 sync always sync init update \main_sdcore_crc16_checker_crc0_clr $1\main_sdcore_crc16_checker_crc0_clr[0:0] end - attribute \src "ls180.v:1550.12-1550.58" - process $proc$ls180.v:1550$3517 + attribute \src "ls180.v:1555.12-1555.58" + process $proc$ls180.v:1555$3650 assign { } { } assign $1\main_sdcore_crc16_checker_crc1_crcreg0[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_crc1_crcreg0 $1\main_sdcore_crc16_checker_crc1_crcreg0[15:0] end - attribute \src "ls180.v:1554.12-1554.54" - process $proc$ls180.v:1554$3518 + attribute \src "ls180.v:1559.12-1559.54" + process $proc$ls180.v:1559$3651 assign { } { } assign $1\main_sdcore_crc16_checker_crc1_crc[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_crc1_crc $1\main_sdcore_crc16_checker_crc1_crc[15:0] end - attribute \src "ls180.v:1555.5-1555.46" - process $proc$ls180.v:1555$3519 + attribute \src "ls180.v:1560.5-1560.46" + process $proc$ls180.v:1560$3652 assign { } { } assign $1\main_sdcore_crc16_checker_crc1_clr[0:0] 1'0 sync always sync init update \main_sdcore_crc16_checker_crc1_clr $1\main_sdcore_crc16_checker_crc1_clr[0:0] end - attribute \src "ls180.v:1557.12-1557.58" - process $proc$ls180.v:1557$3520 + attribute \src "ls180.v:1562.12-1562.58" + process $proc$ls180.v:1562$3653 assign { } { } assign $1\main_sdcore_crc16_checker_crc2_crcreg0[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_crc2_crcreg0 $1\main_sdcore_crc16_checker_crc2_crcreg0[15:0] end - attribute \src "ls180.v:1561.12-1561.54" - process $proc$ls180.v:1561$3521 + attribute \src "ls180.v:1566.12-1566.54" + process $proc$ls180.v:1566$3654 assign { } { } assign $1\main_sdcore_crc16_checker_crc2_crc[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_crc2_crc $1\main_sdcore_crc16_checker_crc2_crc[15:0] end - attribute \src "ls180.v:1562.5-1562.46" - process $proc$ls180.v:1562$3522 + attribute \src "ls180.v:1567.5-1567.46" + process $proc$ls180.v:1567$3655 assign { } { } assign $1\main_sdcore_crc16_checker_crc2_clr[0:0] 1'0 sync always sync init update \main_sdcore_crc16_checker_crc2_clr $1\main_sdcore_crc16_checker_crc2_clr[0:0] end - attribute \src "ls180.v:1564.12-1564.58" - process $proc$ls180.v:1564$3523 + attribute \src "ls180.v:1569.12-1569.58" + process $proc$ls180.v:1569$3656 assign { } { } assign $1\main_sdcore_crc16_checker_crc3_crcreg0[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_crc3_crcreg0 $1\main_sdcore_crc16_checker_crc3_crcreg0[15:0] end - attribute \src "ls180.v:1568.12-1568.54" - process $proc$ls180.v:1568$3524 + attribute \src "ls180.v:1573.12-1573.54" + process $proc$ls180.v:1573$3657 assign { } { } assign $1\main_sdcore_crc16_checker_crc3_crc[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_crc3_crc $1\main_sdcore_crc16_checker_crc3_crc[15:0] end - attribute \src "ls180.v:1569.5-1569.46" - process $proc$ls180.v:1569$3525 + attribute \src "ls180.v:1574.5-1574.46" + process $proc$ls180.v:1574$3658 assign { } { } assign $1\main_sdcore_crc16_checker_crc3_clr[0:0] 1'0 sync always sync init update \main_sdcore_crc16_checker_crc3_clr $1\main_sdcore_crc16_checker_crc3_clr[0:0] end - attribute \src "ls180.v:1571.12-1571.53" - process $proc$ls180.v:1571$3526 + attribute \src "ls180.v:1576.12-1576.53" + process $proc$ls180.v:1576$3659 assign { } { } assign $1\main_sdcore_crc16_checker_crctmp0[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_crctmp0 $1\main_sdcore_crc16_checker_crctmp0[15:0] end - attribute \src "ls180.v:1572.12-1572.53" - process $proc$ls180.v:1572$3527 + attribute \src "ls180.v:1577.12-1577.53" + process $proc$ls180.v:1577$3660 assign { } { } assign $1\main_sdcore_crc16_checker_crctmp1[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_crctmp1 $1\main_sdcore_crc16_checker_crctmp1[15:0] end - attribute \src "ls180.v:1573.12-1573.53" - process $proc$ls180.v:1573$3528 + attribute \src "ls180.v:1578.12-1578.53" + process $proc$ls180.v:1578$3661 assign { } { } assign $1\main_sdcore_crc16_checker_crctmp2[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_crctmp2 $1\main_sdcore_crc16_checker_crctmp2[15:0] end - attribute \src "ls180.v:1574.12-1574.53" - process $proc$ls180.v:1574$3529 + attribute \src "ls180.v:1579.12-1579.53" + process $proc$ls180.v:1579$3662 assign { } { } assign $1\main_sdcore_crc16_checker_crctmp3[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_crctmp3 $1\main_sdcore_crc16_checker_crctmp3[15:0] end - attribute \src "ls180.v:1575.5-1575.43" - process $proc$ls180.v:1575$3530 + attribute \src "ls180.v:1580.5-1580.43" + process $proc$ls180.v:1580$3663 assign { } { } assign $1\main_sdcore_crc16_checker_valid[0:0] 1'0 sync always sync init update \main_sdcore_crc16_checker_valid $1\main_sdcore_crc16_checker_valid[0:0] end - attribute \src "ls180.v:1576.12-1576.51" - process $proc$ls180.v:1576$3531 + attribute \src "ls180.v:1581.12-1581.51" + process $proc$ls180.v:1581$3664 assign { } { } assign $1\main_sdcore_crc16_checker_fifo0[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_fifo0 $1\main_sdcore_crc16_checker_fifo0[15:0] end - attribute \src "ls180.v:1577.12-1577.51" - process $proc$ls180.v:1577$3532 + attribute \src "ls180.v:1582.12-1582.51" + process $proc$ls180.v:1582$3665 assign { } { } assign $1\main_sdcore_crc16_checker_fifo1[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_fifo1 $1\main_sdcore_crc16_checker_fifo1[15:0] end - attribute \src "ls180.v:1578.12-1578.51" - process $proc$ls180.v:1578$3533 + attribute \src "ls180.v:1583.12-1583.51" + process $proc$ls180.v:1583$3666 assign { } { } assign $1\main_sdcore_crc16_checker_fifo2[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_fifo2 $1\main_sdcore_crc16_checker_fifo2[15:0] end - attribute \src "ls180.v:1579.12-1579.51" - process $proc$ls180.v:1579$3534 + attribute \src "ls180.v:1584.12-1584.51" + process $proc$ls180.v:1584$3667 assign { } { } assign $1\main_sdcore_crc16_checker_fifo3[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_fifo3 $1\main_sdcore_crc16_checker_fifo3[15:0] end - attribute \src "ls180.v:158.12-158.71" - process $proc$ls180.v:158$2907 - assign { } { } - assign $1\main_libresocsim_interface0_converted_interface_adr[29:0] 30'000000000000000000000000000000 - sync always - sync init - update \main_libresocsim_interface0_converted_interface_adr $1\main_libresocsim_interface0_converted_interface_adr[29:0] - end - attribute \src "ls180.v:1581.11-1581.39" - process $proc$ls180.v:1581$3535 + attribute \src "ls180.v:1586.11-1586.39" + process $proc$ls180.v:1586$3668 assign { } { } assign $1\main_sdcore_cmd_count[2:0] 3'000 sync always sync init update \main_sdcore_cmd_count $1\main_sdcore_cmd_count[2:0] end - attribute \src "ls180.v:1582.5-1582.32" - process $proc$ls180.v:1582$3536 + attribute \src "ls180.v:1587.5-1587.32" + process $proc$ls180.v:1587$3669 assign { } { } assign $1\main_sdcore_cmd_done[0:0] 1'0 sync always sync init update \main_sdcore_cmd_done $1\main_sdcore_cmd_done[0:0] end - attribute \src "ls180.v:1583.5-1583.33" - process $proc$ls180.v:1583$3537 + attribute \src "ls180.v:1588.5-1588.33" + process $proc$ls180.v:1588$3670 assign { } { } assign $1\main_sdcore_cmd_error[0:0] 1'0 sync always sync init update \main_sdcore_cmd_error $1\main_sdcore_cmd_error[0:0] end - attribute \src "ls180.v:1584.5-1584.35" - process $proc$ls180.v:1584$3538 + attribute \src "ls180.v:1589.5-1589.35" + process $proc$ls180.v:1589$3671 assign { } { } assign $1\main_sdcore_cmd_timeout[0:0] 1'0 sync always sync init update \main_sdcore_cmd_timeout $1\main_sdcore_cmd_timeout[0:0] end - attribute \src "ls180.v:1586.12-1586.42" - process $proc$ls180.v:1586$3539 + attribute \src "ls180.v:1591.12-1591.42" + process $proc$ls180.v:1591$3672 assign { } { } assign $1\main_sdcore_data_count[31:0] 0 sync always sync init update \main_sdcore_data_count $1\main_sdcore_data_count[31:0] end - attribute \src "ls180.v:1587.5-1587.33" - process $proc$ls180.v:1587$3540 + attribute \src "ls180.v:1592.5-1592.33" + process $proc$ls180.v:1592$3673 assign { } { } assign $1\main_sdcore_data_done[0:0] 1'0 sync always sync init update \main_sdcore_data_done $1\main_sdcore_data_done[0:0] end - attribute \src "ls180.v:1588.5-1588.34" - process $proc$ls180.v:1588$3541 + attribute \src "ls180.v:1593.5-1593.34" + process $proc$ls180.v:1593$3674 assign { } { } assign $1\main_sdcore_data_error[0:0] 1'0 sync always sync init update \main_sdcore_data_error $1\main_sdcore_data_error[0:0] end - attribute \src "ls180.v:1589.5-1589.36" - process $proc$ls180.v:1589$3542 + attribute \src "ls180.v:1594.5-1594.36" + process $proc$ls180.v:1594$3675 assign { } { } assign $1\main_sdcore_data_timeout[0:0] 1'0 sync always sync init update \main_sdcore_data_timeout $1\main_sdcore_data_timeout[0:0] end - attribute \src "ls180.v:159.12-159.73" - process $proc$ls180.v:159$2908 - assign { } { } - assign $1\main_libresocsim_interface0_converted_interface_dat_w[31:0] 0 - sync always - sync init - update \main_libresocsim_interface0_converted_interface_dat_w $1\main_libresocsim_interface0_converted_interface_dat_w[31:0] - end - attribute \src "ls180.v:1598.11-1598.41" - process $proc$ls180.v:1598$3543 + attribute \src "ls180.v:1603.11-1603.41" + process $proc$ls180.v:1603$3676 assign { } { } assign $0\main_interface0_bus_cti[2:0] 3'000 sync always update \main_interface0_bus_cti $0\main_interface0_bus_cti[2:0] sync init end - attribute \src "ls180.v:1599.11-1599.41" - process $proc$ls180.v:1599$3544 + attribute \src "ls180.v:1604.11-1604.41" + process $proc$ls180.v:1604$3677 assign { } { } assign $0\main_interface0_bus_bte[1:0] 2'00 sync always update \main_interface0_bus_bte $0\main_interface0_bus_bte[1:0] sync init end - attribute \src "ls180.v:161.11-161.69" - process $proc$ls180.v:161$2909 - assign { } { } - assign $1\main_libresocsim_interface0_converted_interface_sel[3:0] 4'0000 - sync always - sync init - update \main_libresocsim_interface0_converted_interface_sel $1\main_libresocsim_interface0_converted_interface_sel[3:0] - end - attribute \src "ls180.v:162.5-162.63" - process $proc$ls180.v:162$2910 - assign { } { } - assign $1\main_libresocsim_interface0_converted_interface_cyc[0:0] 1'0 - sync always - sync init - update \main_libresocsim_interface0_converted_interface_cyc $1\main_libresocsim_interface0_converted_interface_cyc[0:0] - end - attribute \src "ls180.v:1622.11-1622.45" - process $proc$ls180.v:1622$3545 + attribute \src "ls180.v:1627.11-1627.45" + process $proc$ls180.v:1627$3678 assign { } { } assign $1\main_sdblock2mem_fifo_level[5:0] 6'000000 sync always sync init update \main_sdblock2mem_fifo_level $1\main_sdblock2mem_fifo_level[5:0] end - attribute \src "ls180.v:1623.5-1623.41" - process $proc$ls180.v:1623$3546 + attribute \src "ls180.v:1628.5-1628.41" + process $proc$ls180.v:1628$3679 assign { } { } assign $0\main_sdblock2mem_fifo_replace[0:0] 1'0 sync always update \main_sdblock2mem_fifo_replace $0\main_sdblock2mem_fifo_replace[0:0] sync init end - attribute \src "ls180.v:1624.11-1624.47" - process $proc$ls180.v:1624$3547 + attribute \src "ls180.v:1629.11-1629.47" + process $proc$ls180.v:1629$3680 assign { } { } assign $1\main_sdblock2mem_fifo_produce[4:0] 5'00000 sync always sync init update \main_sdblock2mem_fifo_produce $1\main_sdblock2mem_fifo_produce[4:0] end - attribute \src "ls180.v:1625.11-1625.47" - process $proc$ls180.v:1625$3548 + attribute \src "ls180.v:1630.11-1630.47" + process $proc$ls180.v:1630$3681 assign { } { } assign $1\main_sdblock2mem_fifo_consume[4:0] 5'00000 sync always sync init update \main_sdblock2mem_fifo_consume $1\main_sdblock2mem_fifo_consume[4:0] end - attribute \src "ls180.v:1626.11-1626.50" - process $proc$ls180.v:1626$3549 + attribute \src "ls180.v:1631.11-1631.50" + process $proc$ls180.v:1631$3682 assign { } { } assign $1\main_sdblock2mem_fifo_wrport_adr[4:0] 5'00000 sync always sync init update \main_sdblock2mem_fifo_wrport_adr $1\main_sdblock2mem_fifo_wrport_adr[4:0] end - attribute \src "ls180.v:163.5-163.63" - process $proc$ls180.v:163$2911 - assign { } { } - assign $1\main_libresocsim_interface0_converted_interface_stb[0:0] 1'0 - sync always - sync init - update \main_libresocsim_interface0_converted_interface_stb $1\main_libresocsim_interface0_converted_interface_stb[0:0] - end - attribute \src "ls180.v:1646.5-1646.51" - process $proc$ls180.v:1646$3550 + attribute \src "ls180.v:1651.5-1651.51" + process $proc$ls180.v:1651$3683 assign { } { } assign $1\main_sdblock2mem_converter_source_first[0:0] 1'0 sync always sync init update \main_sdblock2mem_converter_source_first $1\main_sdblock2mem_converter_source_first[0:0] end - attribute \src "ls180.v:1647.5-1647.50" - process $proc$ls180.v:1647$3551 + attribute \src "ls180.v:1652.5-1652.50" + process $proc$ls180.v:1652$3684 assign { } { } assign $1\main_sdblock2mem_converter_source_last[0:0] 1'0 sync always sync init update \main_sdblock2mem_converter_source_last $1\main_sdblock2mem_converter_source_last[0:0] end - attribute \src "ls180.v:1648.12-1648.66" - process $proc$ls180.v:1648$3552 + attribute \src "ls180.v:1653.12-1653.66" + process $proc$ls180.v:1653$3685 assign { } { } - assign $1\main_sdblock2mem_converter_source_payload_data[31:0] 0 + assign $1\main_sdblock2mem_converter_source_payload_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \main_sdblock2mem_converter_source_payload_data $1\main_sdblock2mem_converter_source_payload_data[31:0] + update \main_sdblock2mem_converter_source_payload_data $1\main_sdblock2mem_converter_source_payload_data[63:0] end - attribute \src "ls180.v:1649.11-1649.77" - process $proc$ls180.v:1649$3553 + attribute \src "ls180.v:1654.11-1654.77" + process $proc$ls180.v:1654$3686 assign { } { } - assign $1\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] 3'000 + assign $1\main_sdblock2mem_converter_source_payload_valid_token_count[3:0] 4'0000 sync always sync init - update \main_sdblock2mem_converter_source_payload_valid_token_count $1\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] + update \main_sdblock2mem_converter_source_payload_valid_token_count $1\main_sdblock2mem_converter_source_payload_valid_token_count[3:0] end - attribute \src "ls180.v:165.5-165.62" - process $proc$ls180.v:165$2912 + attribute \src "ls180.v:1655.11-1655.50" + process $proc$ls180.v:1655$3687 assign { } { } - assign $1\main_libresocsim_interface0_converted_interface_we[0:0] 1'0 + assign $1\main_sdblock2mem_converter_demux[2:0] 3'000 sync always sync init - update \main_libresocsim_interface0_converted_interface_we $1\main_libresocsim_interface0_converted_interface_we[0:0] + update \main_sdblock2mem_converter_demux $1\main_sdblock2mem_converter_demux[2:0] end - attribute \src "ls180.v:1650.11-1650.50" - process $proc$ls180.v:1650$3554 - assign { } { } - assign $1\main_sdblock2mem_converter_demux[1:0] 2'00 - sync always - sync init - update \main_sdblock2mem_converter_demux $1\main_sdblock2mem_converter_demux[1:0] - end - attribute \src "ls180.v:1652.5-1652.49" - process $proc$ls180.v:1652$3555 + attribute \src "ls180.v:1657.5-1657.49" + process $proc$ls180.v:1657$3688 assign { } { } assign $1\main_sdblock2mem_converter_strobe_all[0:0] 1'0 sync always sync init update \main_sdblock2mem_converter_strobe_all $1\main_sdblock2mem_converter_strobe_all[0:0] end - attribute \src "ls180.v:1658.5-1658.45" - process $proc$ls180.v:1658$3556 + attribute \src "ls180.v:166.5-166.40" + process $proc$ls180.v:166$3050 assign { } { } - assign $1\main_sdblock2mem_sink_sink_valid1[0:0] 1'0 + assign $1\main_libresocsim_ram_bus_ack[0:0] 1'0 sync always sync init - update \main_sdblock2mem_sink_sink_valid1 $1\main_sdblock2mem_sink_sink_valid1[0:0] + update \main_libresocsim_ram_bus_ack $1\main_libresocsim_ram_bus_ack[0:0] end - attribute \src "ls180.v:166.11-166.69" - process $proc$ls180.v:166$2913 + attribute \src "ls180.v:1663.5-1663.45" + process $proc$ls180.v:1663$3689 assign { } { } - assign $0\main_libresocsim_interface0_converted_interface_cti[2:0] 3'000 + assign $1\main_sdblock2mem_sink_sink_valid1[0:0] 1'0 sync always - update \main_libresocsim_interface0_converted_interface_cti $0\main_libresocsim_interface0_converted_interface_cti[2:0] sync init + update \main_sdblock2mem_sink_sink_valid1 $1\main_sdblock2mem_sink_sink_valid1[0:0] end - attribute \src "ls180.v:1660.12-1660.62" - process $proc$ls180.v:1660$3557 + attribute \src "ls180.v:1665.12-1665.62" + process $proc$ls180.v:1665$3690 assign { } { } assign $1\main_sdblock2mem_sink_sink_payload_address[31:0] 0 sync always sync init update \main_sdblock2mem_sink_sink_payload_address $1\main_sdblock2mem_sink_sink_payload_address[31:0] end - attribute \src "ls180.v:1661.12-1661.60" - process $proc$ls180.v:1661$3558 + attribute \src "ls180.v:1666.12-1666.60" + process $proc$ls180.v:1666$3691 assign { } { } - assign $1\main_sdblock2mem_sink_sink_payload_data1[31:0] 0 + assign $1\main_sdblock2mem_sink_sink_payload_data1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \main_sdblock2mem_sink_sink_payload_data1 $1\main_sdblock2mem_sink_sink_payload_data1[31:0] + update \main_sdblock2mem_sink_sink_payload_data1 $1\main_sdblock2mem_sink_sink_payload_data1[63:0] end - attribute \src "ls180.v:1663.5-1663.57" - process $proc$ls180.v:1663$3559 + attribute \src "ls180.v:1668.5-1668.57" + process $proc$ls180.v:1668$3692 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] 1'0 sync always sync init update \main_sdblock2mem_wishbonedmawriter_sink_ready $1\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] end - attribute \src "ls180.v:1667.12-1667.67" - process $proc$ls180.v:1667$3560 + attribute \src "ls180.v:1672.12-1672.67" + process $proc$ls180.v:1672$3693 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \main_sdblock2mem_wishbonedmawriter_base_storage $1\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] end - attribute \src "ls180.v:1668.5-1668.54" - process $proc$ls180.v:1668$3561 + attribute \src "ls180.v:1673.5-1673.54" + process $proc$ls180.v:1673$3694 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_base_re[0:0] 1'0 sync always sync init update \main_sdblock2mem_wishbonedmawriter_base_re $1\main_sdblock2mem_wishbonedmawriter_base_re[0:0] end - attribute \src "ls180.v:1669.12-1669.69" - process $proc$ls180.v:1669$3562 + attribute \src "ls180.v:1674.12-1674.69" + process $proc$ls180.v:1674$3695 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] 0 sync always sync init update \main_sdblock2mem_wishbonedmawriter_length_storage $1\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] end - attribute \src "ls180.v:167.11-167.69" - process $proc$ls180.v:167$2914 - assign { } { } - assign $0\main_libresocsim_interface0_converted_interface_bte[1:0] 2'00 - sync always - update \main_libresocsim_interface0_converted_interface_bte $0\main_libresocsim_interface0_converted_interface_bte[1:0] - sync init - end - attribute \src "ls180.v:1670.5-1670.56" - process $proc$ls180.v:1670$3563 + attribute \src "ls180.v:1675.5-1675.56" + process $proc$ls180.v:1675$3696 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_length_re[0:0] 1'0 sync always sync init update \main_sdblock2mem_wishbonedmawriter_length_re $1\main_sdblock2mem_wishbonedmawriter_length_re[0:0] end - attribute \src "ls180.v:1671.5-1671.61" - process $proc$ls180.v:1671$3564 + attribute \src "ls180.v:1676.5-1676.61" + process $proc$ls180.v:1676$3697 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] 1'0 sync always sync init update \main_sdblock2mem_wishbonedmawriter_enable_storage $1\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] end - attribute \src "ls180.v:1672.5-1672.56" - process $proc$ls180.v:1672$3565 + attribute \src "ls180.v:1677.5-1677.56" + process $proc$ls180.v:1677$3698 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] 1'0 sync always sync init update \main_sdblock2mem_wishbonedmawriter_enable_re $1\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] end - attribute \src "ls180.v:1673.5-1673.53" - process $proc$ls180.v:1673$3566 + attribute \src "ls180.v:1678.5-1678.53" + process $proc$ls180.v:1678$3699 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_status[0:0] 1'0 sync always sync init update \main_sdblock2mem_wishbonedmawriter_status $1\main_sdblock2mem_wishbonedmawriter_status[0:0] end - attribute \src "ls180.v:1675.5-1675.59" - process $proc$ls180.v:1675$3567 + attribute \src "ls180.v:1680.5-1680.59" + process $proc$ls180.v:1680$3700 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] 1'0 sync always sync init update \main_sdblock2mem_wishbonedmawriter_loop_storage $1\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] end - attribute \src "ls180.v:1676.5-1676.54" - process $proc$ls180.v:1676$3568 + attribute \src "ls180.v:1681.5-1681.54" + process $proc$ls180.v:1681$3701 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] 1'0 sync always sync init update \main_sdblock2mem_wishbonedmawriter_loop_re $1\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] end - attribute \src "ls180.v:1678.12-1678.61" - process $proc$ls180.v:1678$3569 + attribute \src "ls180.v:1683.12-1683.61" + process $proc$ls180.v:1683$3702 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_offset[31:0] 0 sync always sync init update \main_sdblock2mem_wishbonedmawriter_offset $1\main_sdblock2mem_wishbonedmawriter_offset[31:0] end - attribute \src "ls180.v:1681.12-1681.43" - process $proc$ls180.v:1681$3570 + attribute \src "ls180.v:1686.12-1686.43" + process $proc$ls180.v:1686$3703 assign { } { } assign $1\main_interface1_bus_adr[31:0] 0 sync always sync init update \main_interface1_bus_adr $1\main_interface1_bus_adr[31:0] end - attribute \src "ls180.v:1682.12-1682.45" - process $proc$ls180.v:1682$3571 + attribute \src "ls180.v:1687.12-1687.45" + process $proc$ls180.v:1687$3704 assign { } { } - assign $0\main_interface1_bus_dat_w[31:0] 0 + assign $0\main_interface1_bus_dat_w[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always - update \main_interface1_bus_dat_w $0\main_interface1_bus_dat_w[31:0] + update \main_interface1_bus_dat_w $0\main_interface1_bus_dat_w[63:0] sync init end - attribute \src "ls180.v:1684.11-1684.41" - process $proc$ls180.v:1684$3572 + attribute \src "ls180.v:1689.11-1689.41" + process $proc$ls180.v:1689$3705 assign { } { } - assign $1\main_interface1_bus_sel[3:0] 4'0000 + assign $1\main_interface1_bus_sel[7:0] 8'00000000 sync always sync init - update \main_interface1_bus_sel $1\main_interface1_bus_sel[3:0] + update \main_interface1_bus_sel $1\main_interface1_bus_sel[7:0] end - attribute \src "ls180.v:1685.5-1685.35" - process $proc$ls180.v:1685$3573 + attribute \src "ls180.v:1690.5-1690.35" + process $proc$ls180.v:1690$3706 assign { } { } assign $1\main_interface1_bus_cyc[0:0] 1'0 sync always sync init update \main_interface1_bus_cyc $1\main_interface1_bus_cyc[0:0] end - attribute \src "ls180.v:1686.5-1686.35" - process $proc$ls180.v:1686$3574 + attribute \src "ls180.v:1691.5-1691.35" + process $proc$ls180.v:1691$3707 assign { } { } assign $1\main_interface1_bus_stb[0:0] 1'0 sync always sync init update \main_interface1_bus_stb $1\main_interface1_bus_stb[0:0] end - attribute \src "ls180.v:1688.5-1688.34" - process $proc$ls180.v:1688$3575 + attribute \src "ls180.v:1693.5-1693.34" + process $proc$ls180.v:1693$3708 assign { } { } assign $1\main_interface1_bus_we[0:0] 1'0 sync always sync init update \main_interface1_bus_we $1\main_interface1_bus_we[0:0] end - attribute \src "ls180.v:1689.11-1689.41" - process $proc$ls180.v:1689$3576 + attribute \src "ls180.v:1694.11-1694.41" + process $proc$ls180.v:1694$3709 assign { } { } assign $0\main_interface1_bus_cti[2:0] 3'000 sync always update \main_interface1_bus_cti $0\main_interface1_bus_cti[2:0] sync init end - attribute \src "ls180.v:169.5-169.44" - process $proc$ls180.v:169$2915 + attribute \src "ls180.v:1695.11-1695.41" + process $proc$ls180.v:1695$3710 assign { } { } - assign $1\main_libresocsim_converter0_skip[0:0] 1'0 + assign $0\main_interface1_bus_bte[1:0] 2'00 sync always + update \main_interface1_bus_bte $0\main_interface1_bus_bte[1:0] sync init - update \main_libresocsim_converter0_skip $1\main_libresocsim_converter0_skip[0:0] end - attribute \src "ls180.v:1690.11-1690.41" - process $proc$ls180.v:1690$3577 + attribute \src "ls180.v:170.5-170.40" + process $proc$ls180.v:170$3051 assign { } { } - assign $0\main_interface1_bus_bte[1:0] 2'00 + assign $0\main_libresocsim_ram_bus_err[0:0] 1'0 sync always - update \main_interface1_bus_bte $0\main_interface1_bus_bte[1:0] + update \main_libresocsim_ram_bus_err $0\main_libresocsim_ram_bus_err[0:0] sync init end - attribute \src "ls180.v:1697.5-1697.43" - process $proc$ls180.v:1697$3578 + attribute \src "ls180.v:1702.5-1702.43" + process $proc$ls180.v:1702$3711 assign { } { } assign $1\main_sdmem2block_dma_sink_valid[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_sink_valid $1\main_sdmem2block_dma_sink_valid[0:0] end - attribute \src "ls180.v:1698.5-1698.43" - process $proc$ls180.v:1698$3579 + attribute \src "ls180.v:1703.5-1703.43" + process $proc$ls180.v:1703$3712 assign { } { } assign $1\main_sdmem2block_dma_sink_ready[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_sink_ready $1\main_sdmem2block_dma_sink_ready[0:0] end - attribute \src "ls180.v:1699.5-1699.42" - process $proc$ls180.v:1699$3580 + attribute \src "ls180.v:1704.5-1704.42" + process $proc$ls180.v:1704$3713 assign { } { } assign $1\main_sdmem2block_dma_sink_last[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_sink_last $1\main_sdmem2block_dma_sink_last[0:0] end - attribute \src "ls180.v:170.5-170.47" - process $proc$ls180.v:170$2916 - assign { } { } - assign $1\main_libresocsim_converter0_counter[0:0] 1'0 - sync always - sync init - update \main_libresocsim_converter0_counter $1\main_libresocsim_converter0_counter[0:0] - end - attribute \src "ls180.v:1700.12-1700.61" - process $proc$ls180.v:1700$3581 + attribute \src "ls180.v:1705.12-1705.61" + process $proc$ls180.v:1705$3714 assign { } { } assign $1\main_sdmem2block_dma_sink_payload_address[31:0] 0 sync always sync init update \main_sdmem2block_dma_sink_payload_address $1\main_sdmem2block_dma_sink_payload_address[31:0] end - attribute \src "ls180.v:1701.5-1701.45" - process $proc$ls180.v:1701$3582 + attribute \src "ls180.v:1706.5-1706.45" + process $proc$ls180.v:1706$3715 assign { } { } assign $1\main_sdmem2block_dma_source_valid[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_source_valid $1\main_sdmem2block_dma_source_valid[0:0] end - attribute \src "ls180.v:1703.5-1703.45" - process $proc$ls180.v:1703$3583 + attribute \src "ls180.v:1708.5-1708.45" + process $proc$ls180.v:1708$3716 assign { } { } assign $0\main_sdmem2block_dma_source_first[0:0] 1'0 sync always update \main_sdmem2block_dma_source_first $0\main_sdmem2block_dma_source_first[0:0] sync init end - attribute \src "ls180.v:1704.5-1704.44" - process $proc$ls180.v:1704$3584 + attribute \src "ls180.v:1709.5-1709.44" + process $proc$ls180.v:1709$3717 assign { } { } assign $1\main_sdmem2block_dma_source_last[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_source_last $1\main_sdmem2block_dma_source_last[0:0] end - attribute \src "ls180.v:1705.12-1705.60" - process $proc$ls180.v:1705$3585 + attribute \src "ls180.v:1710.12-1710.60" + process $proc$ls180.v:1710$3718 assign { } { } - assign $1\main_sdmem2block_dma_source_payload_data[31:0] 0 + assign $1\main_sdmem2block_dma_source_payload_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \main_sdmem2block_dma_source_payload_data $1\main_sdmem2block_dma_source_payload_data[31:0] + update \main_sdmem2block_dma_source_payload_data $1\main_sdmem2block_dma_source_payload_data[63:0] end - attribute \src "ls180.v:1706.12-1706.45" - process $proc$ls180.v:1706$3586 + attribute \src "ls180.v:1711.12-1711.45" + process $proc$ls180.v:1711$3719 assign { } { } - assign $1\main_sdmem2block_dma_data[31:0] 0 + assign $1\main_sdmem2block_dma_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \main_sdmem2block_dma_data $1\main_sdmem2block_dma_data[31:0] + update \main_sdmem2block_dma_data $1\main_sdmem2block_dma_data[63:0] end - attribute \src "ls180.v:1707.12-1707.53" - process $proc$ls180.v:1707$3587 + attribute \src "ls180.v:1712.12-1712.53" + process $proc$ls180.v:1712$3720 assign { } { } assign $1\main_sdmem2block_dma_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \main_sdmem2block_dma_base_storage $1\main_sdmem2block_dma_base_storage[63:0] end - attribute \src "ls180.v:1708.5-1708.40" - process $proc$ls180.v:1708$3588 + attribute \src "ls180.v:1713.5-1713.40" + process $proc$ls180.v:1713$3721 assign { } { } assign $1\main_sdmem2block_dma_base_re[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_base_re $1\main_sdmem2block_dma_base_re[0:0] end - attribute \src "ls180.v:1709.12-1709.55" - process $proc$ls180.v:1709$3589 + attribute \src "ls180.v:1714.12-1714.55" + process $proc$ls180.v:1714$3722 assign { } { } assign $1\main_sdmem2block_dma_length_storage[31:0] 0 sync always sync init update \main_sdmem2block_dma_length_storage $1\main_sdmem2block_dma_length_storage[31:0] end - attribute \src "ls180.v:1710.5-1710.42" - process $proc$ls180.v:1710$3590 + attribute \src "ls180.v:1715.5-1715.42" + process $proc$ls180.v:1715$3723 assign { } { } assign $1\main_sdmem2block_dma_length_re[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_length_re $1\main_sdmem2block_dma_length_re[0:0] end - attribute \src "ls180.v:1711.5-1711.47" - process $proc$ls180.v:1711$3591 + attribute \src "ls180.v:1716.5-1716.47" + process $proc$ls180.v:1716$3724 assign { } { } assign $1\main_sdmem2block_dma_enable_storage[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_enable_storage $1\main_sdmem2block_dma_enable_storage[0:0] end - attribute \src "ls180.v:1712.5-1712.42" - process $proc$ls180.v:1712$3592 + attribute \src "ls180.v:1717.5-1717.42" + process $proc$ls180.v:1717$3725 assign { } { } assign $1\main_sdmem2block_dma_enable_re[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_enable_re $1\main_sdmem2block_dma_enable_re[0:0] end - attribute \src "ls180.v:1713.5-1713.44" - process $proc$ls180.v:1713$3593 + attribute \src "ls180.v:1718.5-1718.44" + process $proc$ls180.v:1718$3726 assign { } { } assign $1\main_sdmem2block_dma_done_status[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_done_status $1\main_sdmem2block_dma_done_status[0:0] end - attribute \src "ls180.v:1715.5-1715.45" - process $proc$ls180.v:1715$3594 + attribute \src "ls180.v:1720.5-1720.45" + process $proc$ls180.v:1720$3727 assign { } { } assign $1\main_sdmem2block_dma_loop_storage[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_loop_storage $1\main_sdmem2block_dma_loop_storage[0:0] end - attribute \src "ls180.v:1716.5-1716.40" - process $proc$ls180.v:1716$3595 + attribute \src "ls180.v:1721.5-1721.40" + process $proc$ls180.v:1721$3728 assign { } { } assign $1\main_sdmem2block_dma_loop_re[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_loop_re $1\main_sdmem2block_dma_loop_re[0:0] end - attribute \src "ls180.v:172.12-172.53" - process $proc$ls180.v:172$2917 - assign { } { } - assign $1\main_libresocsim_converter0_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \main_libresocsim_converter0_dat_r $1\main_libresocsim_converter0_dat_r[63:0] - end - attribute \src "ls180.v:1720.12-1720.47" - process $proc$ls180.v:1720$3596 + attribute \src "ls180.v:1725.12-1725.47" + process $proc$ls180.v:1725$3729 assign { } { } assign $1\main_sdmem2block_dma_offset[31:0] 0 sync always sync init update \main_sdmem2block_dma_offset $1\main_sdmem2block_dma_offset[31:0] end - attribute \src "ls180.v:173.12-173.71" - process $proc$ls180.v:173$2918 + attribute \src "ls180.v:173.11-173.37" + process $proc$ls180.v:173$3052 assign { } { } - assign $1\main_libresocsim_interface1_converted_interface_adr[29:0] 30'000000000000000000000000000000 + assign $1\main_libresocsim_we[7:0] 8'00000000 sync always sync init - update \main_libresocsim_interface1_converted_interface_adr $1\main_libresocsim_interface1_converted_interface_adr[29:0] + update \main_libresocsim_we $1\main_libresocsim_we[7:0] end - attribute \src "ls180.v:1732.11-1732.64" - process $proc$ls180.v:1732$3597 + attribute \src "ls180.v:1737.11-1737.64" + process $proc$ls180.v:1737$3730 assign { } { } assign $1\main_sdmem2block_converter_source_payload_data[7:0] 8'00000000 sync always sync init update \main_sdmem2block_converter_source_payload_data $1\main_sdmem2block_converter_source_payload_data[7:0] end - attribute \src "ls180.v:1734.11-1734.48" - process $proc$ls180.v:1734$3598 + attribute \src "ls180.v:1739.11-1739.48" + process $proc$ls180.v:1739$3731 assign { } { } - assign $1\main_sdmem2block_converter_mux[1:0] 2'00 + assign $1\main_sdmem2block_converter_mux[2:0] 3'000 sync always sync init - update \main_sdmem2block_converter_mux $1\main_sdmem2block_converter_mux[1:0] + update \main_sdmem2block_converter_mux $1\main_sdmem2block_converter_mux[2:0] end - attribute \src "ls180.v:174.12-174.73" - process $proc$ls180.v:174$2919 + attribute \src "ls180.v:175.12-175.49" + process $proc$ls180.v:175$3053 assign { } { } - assign $1\main_libresocsim_interface1_converted_interface_dat_w[31:0] 0 + assign $1\main_libresocsim_load_storage[31:0] 0 sync always sync init - update \main_libresocsim_interface1_converted_interface_dat_w $1\main_libresocsim_interface1_converted_interface_dat_w[31:0] + update \main_libresocsim_load_storage $1\main_libresocsim_load_storage[31:0] end - attribute \src "ls180.v:1758.11-1758.45" - process $proc$ls180.v:1758$3599 + attribute \src "ls180.v:176.5-176.36" + process $proc$ls180.v:176$3054 assign { } { } - assign $1\main_sdmem2block_fifo_level[5:0] 6'000000 + assign $1\main_libresocsim_load_re[0:0] 1'0 sync always sync init - update \main_sdmem2block_fifo_level $1\main_sdmem2block_fifo_level[5:0] + update \main_libresocsim_load_re $1\main_libresocsim_load_re[0:0] end - attribute \src "ls180.v:1759.5-1759.41" - process $proc$ls180.v:1759$3600 + attribute \src "ls180.v:1763.11-1763.45" + process $proc$ls180.v:1763$3732 assign { } { } - assign $0\main_sdmem2block_fifo_replace[0:0] 1'0 + assign $1\main_sdmem2block_fifo_level[5:0] 6'000000 sync always - update \main_sdmem2block_fifo_replace $0\main_sdmem2block_fifo_replace[0:0] sync init + update \main_sdmem2block_fifo_level $1\main_sdmem2block_fifo_level[5:0] end - attribute \src "ls180.v:176.11-176.69" - process $proc$ls180.v:176$2920 + attribute \src "ls180.v:1764.5-1764.41" + process $proc$ls180.v:1764$3733 assign { } { } - assign $1\main_libresocsim_interface1_converted_interface_sel[3:0] 4'0000 + assign $0\main_sdmem2block_fifo_replace[0:0] 1'0 sync always + update \main_sdmem2block_fifo_replace $0\main_sdmem2block_fifo_replace[0:0] sync init - update \main_libresocsim_interface1_converted_interface_sel $1\main_libresocsim_interface1_converted_interface_sel[3:0] end - attribute \src "ls180.v:1760.11-1760.47" - process $proc$ls180.v:1760$3601 + attribute \src "ls180.v:1765.11-1765.47" + process $proc$ls180.v:1765$3734 assign { } { } assign $1\main_sdmem2block_fifo_produce[4:0] 5'00000 sync always sync init update \main_sdmem2block_fifo_produce $1\main_sdmem2block_fifo_produce[4:0] end - attribute \src "ls180.v:1761.11-1761.47" - process $proc$ls180.v:1761$3602 + attribute \src "ls180.v:1766.11-1766.47" + process $proc$ls180.v:1766$3735 assign { } { } assign $1\main_sdmem2block_fifo_consume[4:0] 5'00000 sync always sync init update \main_sdmem2block_fifo_consume $1\main_sdmem2block_fifo_consume[4:0] end - attribute \src "ls180.v:1762.11-1762.50" - process $proc$ls180.v:1762$3603 + attribute \src "ls180.v:1767.11-1767.50" + process $proc$ls180.v:1767$3736 assign { } { } assign $1\main_sdmem2block_fifo_wrport_adr[4:0] 5'00000 sync always sync init update \main_sdmem2block_fifo_wrport_adr $1\main_sdmem2block_fifo_wrport_adr[4:0] end - attribute \src "ls180.v:177.5-177.63" - process $proc$ls180.v:177$2921 + attribute \src "ls180.v:177.12-177.51" + process $proc$ls180.v:177$3055 + assign { } { } + assign $1\main_libresocsim_reload_storage[31:0] 0 + sync always + sync init + update \main_libresocsim_reload_storage $1\main_libresocsim_reload_storage[31:0] + end + attribute \src "ls180.v:178.5-178.38" + process $proc$ls180.v:178$3056 assign { } { } - assign $1\main_libresocsim_interface1_converted_interface_cyc[0:0] 1'0 + assign $1\main_libresocsim_reload_re[0:0] 1'0 sync always sync init - update \main_libresocsim_interface1_converted_interface_cyc $1\main_libresocsim_interface1_converted_interface_cyc[0:0] + update \main_libresocsim_reload_re $1\main_libresocsim_reload_re[0:0] end - attribute \src "ls180.v:1775.5-1775.36" - process $proc$ls180.v:1775$3604 + attribute \src "ls180.v:1780.5-1780.36" + process $proc$ls180.v:1780$3737 assign { } { } assign $1\builder_converter0_state[0:0] 1'0 sync always sync init update \builder_converter0_state $1\builder_converter0_state[0:0] end - attribute \src "ls180.v:1776.5-1776.41" - process $proc$ls180.v:1776$3605 + attribute \src "ls180.v:1781.5-1781.41" + process $proc$ls180.v:1781$3738 assign { } { } assign $1\builder_converter0_next_state[0:0] 1'0 sync always sync init update \builder_converter0_next_state $1\builder_converter0_next_state[0:0] end - attribute \src "ls180.v:1777.5-1777.69" - process $proc$ls180.v:1777$3606 + attribute \src "ls180.v:1782.5-1782.57" + process $proc$ls180.v:1782$3739 assign { } { } - assign $1\main_libresocsim_converter0_counter_converter0_next_value[0:0] 1'0 + assign $1\main_converter0_counter_converter0_next_value[0:0] 1'0 sync always sync init - update \main_libresocsim_converter0_counter_converter0_next_value $1\main_libresocsim_converter0_counter_converter0_next_value[0:0] + update \main_converter0_counter_converter0_next_value $1\main_converter0_counter_converter0_next_value[0:0] end - attribute \src "ls180.v:1778.5-1778.72" - process $proc$ls180.v:1778$3607 + attribute \src "ls180.v:1783.5-1783.60" + process $proc$ls180.v:1783$3740 assign { } { } - assign $1\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] 1'0 + assign $1\main_converter0_counter_converter0_next_value_ce[0:0] 1'0 sync always sync init - update \main_libresocsim_converter0_counter_converter0_next_value_ce $1\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] + update \main_converter0_counter_converter0_next_value_ce $1\main_converter0_counter_converter0_next_value_ce[0:0] end - attribute \src "ls180.v:1779.5-1779.36" - process $proc$ls180.v:1779$3608 + attribute \src "ls180.v:1784.5-1784.36" + process $proc$ls180.v:1784$3741 assign { } { } assign $1\builder_converter1_state[0:0] 1'0 sync always sync init update \builder_converter1_state $1\builder_converter1_state[0:0] end - attribute \src "ls180.v:178.5-178.63" - process $proc$ls180.v:178$2922 - assign { } { } - assign $1\main_libresocsim_interface1_converted_interface_stb[0:0] 1'0 - sync always - sync init - update \main_libresocsim_interface1_converted_interface_stb $1\main_libresocsim_interface1_converted_interface_stb[0:0] - end - attribute \src "ls180.v:1780.5-1780.41" - process $proc$ls180.v:1780$3609 + attribute \src "ls180.v:1785.5-1785.41" + process $proc$ls180.v:1785$3742 assign { } { } assign $1\builder_converter1_next_state[0:0] 1'0 sync always sync init update \builder_converter1_next_state $1\builder_converter1_next_state[0:0] end - attribute \src "ls180.v:1781.5-1781.69" - process $proc$ls180.v:1781$3610 + attribute \src "ls180.v:1786.5-1786.57" + process $proc$ls180.v:1786$3743 assign { } { } - assign $1\main_libresocsim_converter1_counter_converter1_next_value[0:0] 1'0 + assign $1\main_converter1_counter_converter1_next_value[0:0] 1'0 sync always sync init - update \main_libresocsim_converter1_counter_converter1_next_value $1\main_libresocsim_converter1_counter_converter1_next_value[0:0] + update \main_converter1_counter_converter1_next_value $1\main_converter1_counter_converter1_next_value[0:0] end - attribute \src "ls180.v:1782.5-1782.72" - process $proc$ls180.v:1782$3611 + attribute \src "ls180.v:1787.5-1787.60" + process $proc$ls180.v:1787$3744 assign { } { } - assign $1\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] 1'0 + assign $1\main_converter1_counter_converter1_next_value_ce[0:0] 1'0 sync always sync init - update \main_libresocsim_converter1_counter_converter1_next_value_ce $1\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] + update \main_converter1_counter_converter1_next_value_ce $1\main_converter1_counter_converter1_next_value_ce[0:0] end - attribute \src "ls180.v:1783.5-1783.36" - process $proc$ls180.v:1783$3612 + attribute \src "ls180.v:1788.5-1788.36" + process $proc$ls180.v:1788$3745 assign { } { } assign $1\builder_converter2_state[0:0] 1'0 sync always sync init update \builder_converter2_state $1\builder_converter2_state[0:0] end - attribute \src "ls180.v:1784.5-1784.41" - process $proc$ls180.v:1784$3613 + attribute \src "ls180.v:1789.5-1789.41" + process $proc$ls180.v:1789$3746 assign { } { } assign $1\builder_converter2_next_state[0:0] 1'0 sync always sync init update \builder_converter2_next_state $1\builder_converter2_next_state[0:0] end - attribute \src "ls180.v:1785.5-1785.69" - process $proc$ls180.v:1785$3614 + attribute \src "ls180.v:179.5-179.39" + process $proc$ls180.v:179$3057 assign { } { } - assign $1\main_libresocsim_converter2_counter_converter2_next_value[0:0] 1'0 + assign $1\main_libresocsim_en_storage[0:0] 1'0 + sync always + sync init + update \main_libresocsim_en_storage $1\main_libresocsim_en_storage[0:0] + end + attribute \src "ls180.v:1790.5-1790.60" + process $proc$ls180.v:1790$3747 + assign { } { } + assign $1\main_socbushandler_counter_converter2_next_value[0:0] 1'0 sync always sync init - update \main_libresocsim_converter2_counter_converter2_next_value $1\main_libresocsim_converter2_counter_converter2_next_value[0:0] + update \main_socbushandler_counter_converter2_next_value $1\main_socbushandler_counter_converter2_next_value[0:0] end - attribute \src "ls180.v:1786.5-1786.72" - process $proc$ls180.v:1786$3615 + attribute \src "ls180.v:1791.5-1791.63" + process $proc$ls180.v:1791$3748 assign { } { } - assign $1\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] 1'0 + assign $1\main_socbushandler_counter_converter2_next_value_ce[0:0] 1'0 sync always sync init - update \main_libresocsim_converter2_counter_converter2_next_value_ce $1\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] + update \main_socbushandler_counter_converter2_next_value_ce $1\main_socbushandler_counter_converter2_next_value_ce[0:0] end - attribute \src "ls180.v:1787.11-1787.41" - process $proc$ls180.v:1787$3616 + attribute \src "ls180.v:1792.11-1792.41" + process $proc$ls180.v:1792$3749 assign { } { } assign $1\builder_refresher_state[1:0] 2'00 sync always sync init update \builder_refresher_state $1\builder_refresher_state[1:0] end - attribute \src "ls180.v:1788.11-1788.46" - process $proc$ls180.v:1788$3617 + attribute \src "ls180.v:1793.11-1793.46" + process $proc$ls180.v:1793$3750 assign { } { } assign $1\builder_refresher_next_state[1:0] 2'00 sync always sync init update \builder_refresher_next_state $1\builder_refresher_next_state[1:0] end - attribute \src "ls180.v:1789.11-1789.44" - process $proc$ls180.v:1789$3618 + attribute \src "ls180.v:1794.11-1794.44" + process $proc$ls180.v:1794$3751 assign { } { } assign $1\builder_bankmachine0_state[2:0] 3'000 sync always sync init update \builder_bankmachine0_state $1\builder_bankmachine0_state[2:0] end - attribute \src "ls180.v:1790.11-1790.49" - process $proc$ls180.v:1790$3619 + attribute \src "ls180.v:1795.11-1795.49" + process $proc$ls180.v:1795$3752 assign { } { } assign $1\builder_bankmachine0_next_state[2:0] 3'000 sync always sync init update \builder_bankmachine0_next_state $1\builder_bankmachine0_next_state[2:0] end - attribute \src "ls180.v:1791.11-1791.44" - process $proc$ls180.v:1791$3620 + attribute \src "ls180.v:1796.11-1796.44" + process $proc$ls180.v:1796$3753 assign { } { } assign $1\builder_bankmachine1_state[2:0] 3'000 sync always sync init update \builder_bankmachine1_state $1\builder_bankmachine1_state[2:0] end - attribute \src "ls180.v:1792.11-1792.49" - process $proc$ls180.v:1792$3621 + attribute \src "ls180.v:1797.11-1797.49" + process $proc$ls180.v:1797$3754 assign { } { } assign $1\builder_bankmachine1_next_state[2:0] 3'000 sync always sync init update \builder_bankmachine1_next_state $1\builder_bankmachine1_next_state[2:0] end - attribute \src "ls180.v:1793.11-1793.44" - process $proc$ls180.v:1793$3622 + attribute \src "ls180.v:1798.11-1798.44" + process $proc$ls180.v:1798$3755 assign { } { } assign $1\builder_bankmachine2_state[2:0] 3'000 sync always sync init update \builder_bankmachine2_state $1\builder_bankmachine2_state[2:0] end - attribute \src "ls180.v:1794.11-1794.49" - process $proc$ls180.v:1794$3623 + attribute \src "ls180.v:1799.11-1799.49" + process $proc$ls180.v:1799$3756 assign { } { } assign $1\builder_bankmachine2_next_state[2:0] 3'000 sync always sync init update \builder_bankmachine2_next_state $1\builder_bankmachine2_next_state[2:0] end - attribute \src "ls180.v:1795.11-1795.44" - process $proc$ls180.v:1795$3624 + attribute \src "ls180.v:180.5-180.34" + process $proc$ls180.v:180$3058 + assign { } { } + assign $1\main_libresocsim_en_re[0:0] 1'0 + sync always + sync init + update \main_libresocsim_en_re $1\main_libresocsim_en_re[0:0] + end + attribute \src "ls180.v:1800.11-1800.44" + process $proc$ls180.v:1800$3757 assign { } { } assign $1\builder_bankmachine3_state[2:0] 3'000 sync always sync init update \builder_bankmachine3_state $1\builder_bankmachine3_state[2:0] end - attribute \src "ls180.v:1796.11-1796.49" - process $proc$ls180.v:1796$3625 + attribute \src "ls180.v:1801.11-1801.49" + process $proc$ls180.v:1801$3758 assign { } { } assign $1\builder_bankmachine3_next_state[2:0] 3'000 sync always sync init update \builder_bankmachine3_next_state $1\builder_bankmachine3_next_state[2:0] end - attribute \src "ls180.v:1797.11-1797.43" - process $proc$ls180.v:1797$3626 + attribute \src "ls180.v:1802.11-1802.43" + process $proc$ls180.v:1802$3759 assign { } { } assign $1\builder_multiplexer_state[2:0] 3'000 sync always sync init update \builder_multiplexer_state $1\builder_multiplexer_state[2:0] end - attribute \src "ls180.v:1798.11-1798.48" - process $proc$ls180.v:1798$3627 + attribute \src "ls180.v:1803.11-1803.48" + process $proc$ls180.v:1803$3760 assign { } { } assign $1\builder_multiplexer_next_state[2:0] 3'000 sync always sync init update \builder_multiplexer_next_state $1\builder_multiplexer_next_state[2:0] end - attribute \src "ls180.v:180.5-180.62" - process $proc$ls180.v:180$2923 - assign { } { } - assign $1\main_libresocsim_interface1_converted_interface_we[0:0] 1'0 - sync always - sync init - update \main_libresocsim_interface1_converted_interface_we $1\main_libresocsim_interface1_converted_interface_we[0:0] - end - attribute \src "ls180.v:181.11-181.69" - process $proc$ls180.v:181$2924 + attribute \src "ls180.v:181.5-181.49" + process $proc$ls180.v:181$3059 assign { } { } - assign $0\main_libresocsim_interface1_converted_interface_cti[2:0] 3'000 + assign $1\main_libresocsim_update_value_storage[0:0] 1'0 sync always - update \main_libresocsim_interface1_converted_interface_cti $0\main_libresocsim_interface1_converted_interface_cti[2:0] sync init + update \main_libresocsim_update_value_storage $1\main_libresocsim_update_value_storage[0:0] end - attribute \src "ls180.v:1811.5-1811.27" - process $proc$ls180.v:1811$3628 + attribute \src "ls180.v:1816.5-1816.27" + process $proc$ls180.v:1816$3761 assign { } { } assign $0\builder_locked0[0:0] 1'0 sync always update \builder_locked0 $0\builder_locked0[0:0] sync init end - attribute \src "ls180.v:1812.5-1812.27" - process $proc$ls180.v:1812$3629 + attribute \src "ls180.v:1817.5-1817.27" + process $proc$ls180.v:1817$3762 assign { } { } assign $0\builder_locked1[0:0] 1'0 sync always update \builder_locked1 $0\builder_locked1[0:0] sync init end - attribute \src "ls180.v:1813.5-1813.27" - process $proc$ls180.v:1813$3630 + attribute \src "ls180.v:1818.5-1818.27" + process $proc$ls180.v:1818$3763 assign { } { } assign $0\builder_locked2[0:0] 1'0 sync always update \builder_locked2 $0\builder_locked2[0:0] sync init end - attribute \src "ls180.v:1814.5-1814.27" - process $proc$ls180.v:1814$3631 + attribute \src "ls180.v:1819.5-1819.27" + process $proc$ls180.v:1819$3764 assign { } { } assign $0\builder_locked3[0:0] 1'0 sync always update \builder_locked3 $0\builder_locked3[0:0] sync init end - attribute \src "ls180.v:1815.5-1815.42" - process $proc$ls180.v:1815$3632 + attribute \src "ls180.v:182.5-182.44" + process $proc$ls180.v:182$3060 + assign { } { } + assign $1\main_libresocsim_update_value_re[0:0] 1'0 + sync always + sync init + update \main_libresocsim_update_value_re $1\main_libresocsim_update_value_re[0:0] + end + attribute \src "ls180.v:1820.5-1820.42" + process $proc$ls180.v:1820$3765 assign { } { } assign $1\builder_new_master_wdata_ready[0:0] 1'0 sync always sync init update \builder_new_master_wdata_ready $1\builder_new_master_wdata_ready[0:0] end - attribute \src "ls180.v:1816.5-1816.43" - process $proc$ls180.v:1816$3633 + attribute \src "ls180.v:1821.5-1821.43" + process $proc$ls180.v:1821$3766 assign { } { } assign $1\builder_new_master_rdata_valid0[0:0] 1'0 sync always sync init update \builder_new_master_rdata_valid0 $1\builder_new_master_rdata_valid0[0:0] end - attribute \src "ls180.v:1817.5-1817.43" - process $proc$ls180.v:1817$3634 + attribute \src "ls180.v:1822.5-1822.43" + process $proc$ls180.v:1822$3767 assign { } { } assign $1\builder_new_master_rdata_valid1[0:0] 1'0 sync always sync init update \builder_new_master_rdata_valid1 $1\builder_new_master_rdata_valid1[0:0] end - attribute \src "ls180.v:1818.5-1818.43" - process $proc$ls180.v:1818$3635 + attribute \src "ls180.v:1823.5-1823.43" + process $proc$ls180.v:1823$3768 assign { } { } assign $1\builder_new_master_rdata_valid2[0:0] 1'0 sync always sync init update \builder_new_master_rdata_valid2 $1\builder_new_master_rdata_valid2[0:0] end - attribute \src "ls180.v:1819.5-1819.43" - process $proc$ls180.v:1819$3636 + attribute \src "ls180.v:1824.5-1824.43" + process $proc$ls180.v:1824$3769 assign { } { } assign $1\builder_new_master_rdata_valid3[0:0] 1'0 sync always sync init update \builder_new_master_rdata_valid3 $1\builder_new_master_rdata_valid3[0:0] end - attribute \src "ls180.v:182.11-182.69" - process $proc$ls180.v:182$2925 - assign { } { } - assign $0\main_libresocsim_interface1_converted_interface_bte[1:0] 2'00 - sync always - update \main_libresocsim_interface1_converted_interface_bte $0\main_libresocsim_interface1_converted_interface_bte[1:0] - sync init - end - attribute \src "ls180.v:1820.5-1820.35" - process $proc$ls180.v:1820$3637 + attribute \src "ls180.v:1825.5-1825.35" + process $proc$ls180.v:1825$3770 assign { } { } assign $1\builder_converter_state[0:0] 1'0 sync always sync init update \builder_converter_state $1\builder_converter_state[0:0] end - attribute \src "ls180.v:1821.5-1821.40" - process $proc$ls180.v:1821$3638 + attribute \src "ls180.v:1826.5-1826.40" + process $proc$ls180.v:1826$3771 assign { } { } assign $1\builder_converter_next_state[0:0] 1'0 sync always sync init update \builder_converter_next_state $1\builder_converter_next_state[0:0] end - attribute \src "ls180.v:1822.5-1822.55" - process $proc$ls180.v:1822$3639 + attribute \src "ls180.v:1827.5-1827.55" + process $proc$ls180.v:1827$3772 assign { } { } assign $1\main_converter_counter_converter_next_value[0:0] 1'0 sync always sync init update \main_converter_counter_converter_next_value $1\main_converter_counter_converter_next_value[0:0] end - attribute \src "ls180.v:1823.5-1823.58" - process $proc$ls180.v:1823$3640 + attribute \src "ls180.v:1828.5-1828.58" + process $proc$ls180.v:1828$3773 assign { } { } assign $1\main_converter_counter_converter_next_value_ce[0:0] 1'0 sync always sync init update \main_converter_counter_converter_next_value_ce $1\main_converter_counter_converter_next_value_ce[0:0] end - attribute \src "ls180.v:1824.11-1824.42" - process $proc$ls180.v:1824$3641 + attribute \src "ls180.v:1829.11-1829.42" + process $proc$ls180.v:1829$3774 assign { } { } assign $1\builder_spimaster0_state[1:0] 2'00 sync always sync init update \builder_spimaster0_state $1\builder_spimaster0_state[1:0] end - attribute \src "ls180.v:1825.11-1825.47" - process $proc$ls180.v:1825$3642 + attribute \src "ls180.v:183.12-183.49" + process $proc$ls180.v:183$3061 + assign { } { } + assign $1\main_libresocsim_value_status[31:0] 0 + sync always + sync init + update \main_libresocsim_value_status $1\main_libresocsim_value_status[31:0] + end + attribute \src "ls180.v:1830.11-1830.47" + process $proc$ls180.v:1830$3775 assign { } { } assign $1\builder_spimaster0_next_state[1:0] 2'00 sync always sync init update \builder_spimaster0_next_state $1\builder_spimaster0_next_state[1:0] end - attribute \src "ls180.v:1826.11-1826.62" - process $proc$ls180.v:1826$3643 + attribute \src "ls180.v:1831.11-1831.62" + process $proc$ls180.v:1831$3776 assign { } { } assign $1\main_spimaster27_count_spimaster0_next_value[2:0] 3'000 sync always sync init update \main_spimaster27_count_spimaster0_next_value $1\main_spimaster27_count_spimaster0_next_value[2:0] end - attribute \src "ls180.v:1827.5-1827.59" - process $proc$ls180.v:1827$3644 + attribute \src "ls180.v:1832.5-1832.59" + process $proc$ls180.v:1832$3777 assign { } { } assign $1\main_spimaster27_count_spimaster0_next_value_ce[0:0] 1'0 sync always sync init update \main_spimaster27_count_spimaster0_next_value_ce $1\main_spimaster27_count_spimaster0_next_value_ce[0:0] end - attribute \src "ls180.v:1828.11-1828.42" - process $proc$ls180.v:1828$3645 + attribute \src "ls180.v:1833.11-1833.42" + process $proc$ls180.v:1833$3778 assign { } { } assign $1\builder_spimaster1_state[1:0] 2'00 sync always sync init update \builder_spimaster1_state $1\builder_spimaster1_state[1:0] end - attribute \src "ls180.v:1829.11-1829.47" - process $proc$ls180.v:1829$3646 + attribute \src "ls180.v:1834.11-1834.47" + process $proc$ls180.v:1834$3779 assign { } { } assign $1\builder_spimaster1_next_state[1:0] 2'00 sync always sync init update \builder_spimaster1_next_state $1\builder_spimaster1_next_state[1:0] end - attribute \src "ls180.v:1830.11-1830.60" - process $proc$ls180.v:1830$3647 + attribute \src "ls180.v:1835.11-1835.60" + process $proc$ls180.v:1835$3780 assign { } { } assign $1\main_spisdcard_count_spimaster1_next_value[2:0] 3'000 sync always sync init update \main_spisdcard_count_spimaster1_next_value $1\main_spisdcard_count_spimaster1_next_value[2:0] end - attribute \src "ls180.v:1831.5-1831.57" - process $proc$ls180.v:1831$3648 + attribute \src "ls180.v:1836.5-1836.57" + process $proc$ls180.v:1836$3781 assign { } { } assign $1\main_spisdcard_count_spimaster1_next_value_ce[0:0] 1'0 sync always sync init update \main_spisdcard_count_spimaster1_next_value_ce $1\main_spisdcard_count_spimaster1_next_value_ce[0:0] end - attribute \src "ls180.v:1832.5-1832.41" - process $proc$ls180.v:1832$3649 + attribute \src "ls180.v:1837.5-1837.41" + process $proc$ls180.v:1837$3782 assign { } { } assign $1\builder_sdphy_sdphyinit_state[0:0] 1'0 sync always sync init update \builder_sdphy_sdphyinit_state $1\builder_sdphy_sdphyinit_state[0:0] end - attribute \src "ls180.v:1833.5-1833.46" - process $proc$ls180.v:1833$3650 + attribute \src "ls180.v:1838.5-1838.46" + process $proc$ls180.v:1838$3783 assign { } { } assign $1\builder_sdphy_sdphyinit_next_state[0:0] 1'0 sync always sync init update \builder_sdphy_sdphyinit_next_state $1\builder_sdphy_sdphyinit_next_state[0:0] end - attribute \src "ls180.v:1834.11-1834.66" - process $proc$ls180.v:1834$3651 + attribute \src "ls180.v:1839.11-1839.66" + process $proc$ls180.v:1839$3784 assign { } { } assign $1\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000 sync always sync init update \main_sdphy_init_count_sdphy_sdphyinit_next_value $1\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] end - attribute \src "ls180.v:1835.5-1835.63" - process $proc$ls180.v:1835$3652 + attribute \src "ls180.v:1840.5-1840.63" + process $proc$ls180.v:1840$3785 assign { } { } assign $1\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'0 sync always sync init update \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce $1\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] end - attribute \src "ls180.v:1836.11-1836.47" - process $proc$ls180.v:1836$3653 + attribute \src "ls180.v:1841.11-1841.47" + process $proc$ls180.v:1841$3786 assign { } { } assign $1\builder_sdphy_sdphycmdw_state[1:0] 2'00 sync always sync init update \builder_sdphy_sdphycmdw_state $1\builder_sdphy_sdphycmdw_state[1:0] end - attribute \src "ls180.v:1837.11-1837.52" - process $proc$ls180.v:1837$3654 + attribute \src "ls180.v:1842.11-1842.52" + process $proc$ls180.v:1842$3787 assign { } { } assign $1\builder_sdphy_sdphycmdw_next_state[1:0] 2'00 sync always sync init update \builder_sdphy_sdphycmdw_next_state $1\builder_sdphy_sdphycmdw_next_state[1:0] end - attribute \src "ls180.v:1838.11-1838.66" - process $proc$ls180.v:1838$3655 + attribute \src "ls180.v:1843.11-1843.66" + process $proc$ls180.v:1843$3788 assign { } { } assign $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] 8'00000000 sync always sync init update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] end - attribute \src "ls180.v:1839.5-1839.63" - process $proc$ls180.v:1839$3656 + attribute \src "ls180.v:1844.5-1844.63" + process $proc$ls180.v:1844$3789 assign { } { } assign $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'0 sync always sync init update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] end - attribute \src "ls180.v:184.5-184.44" - process $proc$ls180.v:184$2926 - assign { } { } - assign $1\main_libresocsim_converter1_skip[0:0] 1'0 - sync always - sync init - update \main_libresocsim_converter1_skip $1\main_libresocsim_converter1_skip[0:0] - end - attribute \src "ls180.v:1840.11-1840.47" - process $proc$ls180.v:1840$3657 + attribute \src "ls180.v:1845.11-1845.47" + process $proc$ls180.v:1845$3790 assign { } { } assign $1\builder_sdphy_sdphycmdr_state[2:0] 3'000 sync always sync init update \builder_sdphy_sdphycmdr_state $1\builder_sdphy_sdphycmdr_state[2:0] end - attribute \src "ls180.v:1841.11-1841.52" - process $proc$ls180.v:1841$3658 + attribute \src "ls180.v:1846.11-1846.52" + process $proc$ls180.v:1846$3791 assign { } { } assign $1\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 sync always sync init update \builder_sdphy_sdphycmdr_next_state $1\builder_sdphy_sdphycmdr_next_state[2:0] end - attribute \src "ls180.v:1842.11-1842.67" - process $proc$ls180.v:1842$3659 + attribute \src "ls180.v:1847.11-1847.67" + process $proc$ls180.v:1847$3792 assign { } { } assign $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000 sync always sync init update \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0 $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] end - attribute \src "ls180.v:1843.5-1843.64" - process $proc$ls180.v:1843$3660 + attribute \src "ls180.v:1848.5-1848.64" + process $proc$ls180.v:1848$3793 assign { } { } assign $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0 $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] end - attribute \src "ls180.v:1844.12-1844.71" - process $proc$ls180.v:1844$3661 + attribute \src "ls180.v:1849.12-1849.71" + process $proc$ls180.v:1849$3794 assign { } { } assign $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] 0 sync always sync init update \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1 $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] end - attribute \src "ls180.v:1845.5-1845.66" - process $proc$ls180.v:1845$3662 + attribute \src "ls180.v:1850.5-1850.66" + process $proc$ls180.v:1850$3795 assign { } { } assign $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] end - attribute \src "ls180.v:1846.5-1846.66" - process $proc$ls180.v:1846$3663 + attribute \src "ls180.v:1851.5-1851.66" + process $proc$ls180.v:1851$3796 assign { } { } assign $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] end - attribute \src "ls180.v:1847.5-1847.69" - process $proc$ls180.v:1847$3664 + attribute \src "ls180.v:1852.5-1852.69" + process $proc$ls180.v:1852$3797 assign { } { } assign $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] end - attribute \src "ls180.v:1848.5-1848.41" - process $proc$ls180.v:1848$3665 + attribute \src "ls180.v:1853.5-1853.41" + process $proc$ls180.v:1853$3798 assign { } { } assign $1\builder_sdphy_sdphycrcr_state[0:0] 1'0 sync always sync init update \builder_sdphy_sdphycrcr_state $1\builder_sdphy_sdphycrcr_state[0:0] end - attribute \src "ls180.v:1849.5-1849.46" - process $proc$ls180.v:1849$3666 + attribute \src "ls180.v:1854.5-1854.46" + process $proc$ls180.v:1854$3799 assign { } { } assign $1\builder_sdphy_sdphycrcr_next_state[0:0] 1'0 sync always sync init update \builder_sdphy_sdphycrcr_next_state $1\builder_sdphy_sdphycrcr_next_state[0:0] end - attribute \src "ls180.v:185.5-185.47" - process $proc$ls180.v:185$2927 - assign { } { } - assign $1\main_libresocsim_converter1_counter[0:0] 1'0 - sync always - sync init - update \main_libresocsim_converter1_counter $1\main_libresocsim_converter1_counter[0:0] - end - attribute \src "ls180.v:1850.5-1850.66" - process $proc$ls180.v:1850$3667 + attribute \src "ls180.v:1855.5-1855.66" + process $proc$ls180.v:1855$3800 assign { } { } assign $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0 sync always sync init update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] end - attribute \src "ls180.v:1851.5-1851.69" - process $proc$ls180.v:1851$3668 + attribute \src "ls180.v:1856.5-1856.69" + process $proc$ls180.v:1856$3801 assign { } { } assign $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'0 sync always sync init update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] end - attribute \src "ls180.v:1852.11-1852.41" - process $proc$ls180.v:1852$3669 + attribute \src "ls180.v:1857.11-1857.41" + process $proc$ls180.v:1857$3802 assign { } { } assign $1\builder_sdphy_fsm_state[2:0] 3'000 sync always sync init update \builder_sdphy_fsm_state $1\builder_sdphy_fsm_state[2:0] end - attribute \src "ls180.v:1853.11-1853.46" - process $proc$ls180.v:1853$3670 + attribute \src "ls180.v:1858.11-1858.46" + process $proc$ls180.v:1858$3803 assign { } { } assign $1\builder_sdphy_fsm_next_state[2:0] 3'000 sync always sync init update \builder_sdphy_fsm_next_state $1\builder_sdphy_fsm_next_state[2:0] end - attribute \src "ls180.v:1854.11-1854.61" - process $proc$ls180.v:1854$3671 + attribute \src "ls180.v:1859.11-1859.61" + process $proc$ls180.v:1859$3804 assign { } { } assign $1\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 sync always sync init update \main_sdphy_dataw_count_sdphy_fsm_next_value $1\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] end - attribute \src "ls180.v:1855.5-1855.58" - process $proc$ls180.v:1855$3672 + attribute \src "ls180.v:1860.5-1860.58" + process $proc$ls180.v:1860$3805 assign { } { } assign $1\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'0 sync always sync init update \main_sdphy_dataw_count_sdphy_fsm_next_value_ce $1\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] end - attribute \src "ls180.v:1856.11-1856.48" - process $proc$ls180.v:1856$3673 + attribute \src "ls180.v:1861.11-1861.48" + process $proc$ls180.v:1861$3806 assign { } { } assign $1\builder_sdphy_sdphydatar_state[2:0] 3'000 sync always sync init update \builder_sdphy_sdphydatar_state $1\builder_sdphy_sdphydatar_state[2:0] end - attribute \src "ls180.v:1857.11-1857.53" - process $proc$ls180.v:1857$3674 + attribute \src "ls180.v:1862.11-1862.53" + process $proc$ls180.v:1862$3807 assign { } { } assign $1\builder_sdphy_sdphydatar_next_state[2:0] 3'000 sync always sync init update \builder_sdphy_sdphydatar_next_state $1\builder_sdphy_sdphydatar_next_state[2:0] end - attribute \src "ls180.v:1858.11-1858.70" - process $proc$ls180.v:1858$3675 + attribute \src "ls180.v:1863.11-1863.70" + process $proc$ls180.v:1863$3808 assign { } { } assign $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 sync always sync init update \main_sdphy_datar_count_sdphy_sdphydatar_next_value0 $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] end - attribute \src "ls180.v:1859.5-1859.66" - process $proc$ls180.v:1859$3676 + attribute \src "ls180.v:1864.5-1864.66" + process $proc$ls180.v:1864$3809 assign { } { } assign $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'0 sync always sync init update \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0 $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] end - attribute \src "ls180.v:1860.12-1860.73" - process $proc$ls180.v:1860$3677 + attribute \src "ls180.v:1865.12-1865.73" + process $proc$ls180.v:1865$3810 assign { } { } assign $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 0 sync always sync init update \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1 $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] end - attribute \src "ls180.v:1861.5-1861.68" - process $proc$ls180.v:1861$3678 + attribute \src "ls180.v:1866.5-1866.68" + process $proc$ls180.v:1866$3811 assign { } { } assign $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'0 sync always sync init update \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1 $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] end - attribute \src "ls180.v:1862.5-1862.69" - process $proc$ls180.v:1862$3679 + attribute \src "ls180.v:1867.5-1867.69" + process $proc$ls180.v:1867$3812 assign { } { } assign $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'0 sync always sync init update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] end - attribute \src "ls180.v:1863.5-1863.72" - process $proc$ls180.v:1863$3680 + attribute \src "ls180.v:1868.5-1868.72" + process $proc$ls180.v:1868$3813 assign { } { } assign $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'0 sync always sync init update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] end - attribute \src "ls180.v:1864.5-1864.52" - process $proc$ls180.v:1864$3681 + attribute \src "ls180.v:1869.5-1869.52" + process $proc$ls180.v:1869$3814 assign { } { } assign $1\builder_sdcore_crcupstreaminserter_state[0:0] 1'0 sync always sync init update \builder_sdcore_crcupstreaminserter_state $1\builder_sdcore_crcupstreaminserter_state[0:0] end - attribute \src "ls180.v:1865.5-1865.57" - process $proc$ls180.v:1865$3682 + attribute \src "ls180.v:187.5-187.41" + process $proc$ls180.v:187$3062 + assign { } { } + assign $1\main_libresocsim_zero_pending[0:0] 1'0 + sync always + sync init + update \main_libresocsim_zero_pending $1\main_libresocsim_zero_pending[0:0] + end + attribute \src "ls180.v:1870.5-1870.57" + process $proc$ls180.v:1870$3815 assign { } { } assign $1\builder_sdcore_crcupstreaminserter_next_state[0:0] 1'0 sync always sync init update \builder_sdcore_crcupstreaminserter_next_state $1\builder_sdcore_crcupstreaminserter_next_state[0:0] end - attribute \src "ls180.v:1866.12-1866.93" - process $proc$ls180.v:1866$3683 + attribute \src "ls180.v:1871.12-1871.93" + process $proc$ls180.v:1871$3816 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] end - attribute \src "ls180.v:1867.5-1867.88" - process $proc$ls180.v:1867$3684 + attribute \src "ls180.v:1872.5-1872.88" + process $proc$ls180.v:1872$3817 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] 1'0 sync always sync init update \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] end - attribute \src "ls180.v:1868.12-1868.93" - process $proc$ls180.v:1868$3685 + attribute \src "ls180.v:1873.12-1873.93" + process $proc$ls180.v:1873$3818 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] end - attribute \src "ls180.v:1869.5-1869.88" - process $proc$ls180.v:1869$3686 + attribute \src "ls180.v:1874.5-1874.88" + process $proc$ls180.v:1874$3819 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] 1'0 sync always sync init update \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] end - attribute \src "ls180.v:187.12-187.53" - process $proc$ls180.v:187$2928 - assign { } { } - assign $1\main_libresocsim_converter1_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \main_libresocsim_converter1_dat_r $1\main_libresocsim_converter1_dat_r[63:0] - end - attribute \src "ls180.v:1870.12-1870.93" - process $proc$ls180.v:1870$3687 + attribute \src "ls180.v:1875.12-1875.93" + process $proc$ls180.v:1875$3820 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] end - attribute \src "ls180.v:1871.5-1871.88" - process $proc$ls180.v:1871$3688 + attribute \src "ls180.v:1876.5-1876.88" + process $proc$ls180.v:1876$3821 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'0 sync always sync init update \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] end - attribute \src "ls180.v:1872.12-1872.93" - process $proc$ls180.v:1872$3689 + attribute \src "ls180.v:1877.12-1877.93" + process $proc$ls180.v:1877$3822 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] end - attribute \src "ls180.v:1873.5-1873.88" - process $proc$ls180.v:1873$3690 + attribute \src "ls180.v:1878.5-1878.88" + process $proc$ls180.v:1878$3823 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'0 sync always sync init update \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] end - attribute \src "ls180.v:1874.11-1874.87" - process $proc$ls180.v:1874$3691 + attribute \src "ls180.v:1879.11-1879.87" + process $proc$ls180.v:1879$3824 assign { } { } assign $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000 sync always sync init update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] end - attribute \src "ls180.v:1875.5-1875.84" - process $proc$ls180.v:1875$3692 + attribute \src "ls180.v:1880.5-1880.84" + process $proc$ls180.v:1880$3825 assign { } { } assign $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'0 sync always sync init update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] end - attribute \src "ls180.v:1876.11-1876.42" - process $proc$ls180.v:1876$3693 + attribute \src "ls180.v:1881.11-1881.42" + process $proc$ls180.v:1881$3826 assign { } { } assign $1\builder_sdcore_fsm_state[2:0] 3'000 sync always sync init update \builder_sdcore_fsm_state $1\builder_sdcore_fsm_state[2:0] end - attribute \src "ls180.v:1877.11-1877.47" - process $proc$ls180.v:1877$3694 + attribute \src "ls180.v:1882.11-1882.47" + process $proc$ls180.v:1882$3827 assign { } { } assign $1\builder_sdcore_fsm_next_state[2:0] 3'000 sync always sync init update \builder_sdcore_fsm_next_state $1\builder_sdcore_fsm_next_state[2:0] end - attribute \src "ls180.v:1878.5-1878.55" - process $proc$ls180.v:1878$3695 + attribute \src "ls180.v:1883.5-1883.55" + process $proc$ls180.v:1883$3828 assign { } { } assign $1\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0 sync always sync init update \main_sdcore_cmd_done_sdcore_fsm_next_value0 $1\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] end - attribute \src "ls180.v:1879.5-1879.58" - process $proc$ls180.v:1879$3696 + attribute \src "ls180.v:1884.5-1884.58" + process $proc$ls180.v:1884$3829 assign { } { } assign $1\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'0 sync always sync init update \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0 $1\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] end - attribute \src "ls180.v:188.12-188.71" - process $proc$ls180.v:188$2929 - assign { } { } - assign $1\main_libresocsim_interface2_converted_interface_adr[29:0] 30'000000000000000000000000000000 - sync always - sync init - update \main_libresocsim_interface2_converted_interface_adr $1\main_libresocsim_interface2_converted_interface_adr[29:0] - end - attribute \src "ls180.v:1880.5-1880.56" - process $proc$ls180.v:1880$3697 + attribute \src "ls180.v:1885.5-1885.56" + process $proc$ls180.v:1885$3830 assign { } { } assign $1\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'0 sync always sync init update \main_sdcore_data_done_sdcore_fsm_next_value1 $1\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] end - attribute \src "ls180.v:1881.5-1881.59" - process $proc$ls180.v:1881$3698 + attribute \src "ls180.v:1886.5-1886.59" + process $proc$ls180.v:1886$3831 assign { } { } assign $1\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'0 sync always sync init update \main_sdcore_data_done_sdcore_fsm_next_value_ce1 $1\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] end - attribute \src "ls180.v:1882.11-1882.62" - process $proc$ls180.v:1882$3699 + attribute \src "ls180.v:1887.11-1887.62" + process $proc$ls180.v:1887$3832 assign { } { } assign $1\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] 3'000 sync always sync init update \main_sdcore_cmd_count_sdcore_fsm_next_value2 $1\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] end - attribute \src "ls180.v:1883.5-1883.59" - process $proc$ls180.v:1883$3700 + attribute \src "ls180.v:1888.5-1888.59" + process $proc$ls180.v:1888$3833 assign { } { } assign $1\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'0 sync always sync init update \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2 $1\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] end - attribute \src "ls180.v:1884.12-1884.65" - process $proc$ls180.v:1884$3701 + attribute \src "ls180.v:1889.12-1889.65" + process $proc$ls180.v:1889$3834 assign { } { } assign $1\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0 sync always sync init update \main_sdcore_data_count_sdcore_fsm_next_value3 $1\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] end - attribute \src "ls180.v:1885.5-1885.60" - process $proc$ls180.v:1885$3702 + attribute \src "ls180.v:189.5-189.39" + process $proc$ls180.v:189$3063 + assign { } { } + assign $1\main_libresocsim_zero_clear[0:0] 1'0 + sync always + sync init + update \main_libresocsim_zero_clear $1\main_libresocsim_zero_clear[0:0] + end + attribute \src "ls180.v:1890.5-1890.60" + process $proc$ls180.v:1890$3835 assign { } { } assign $1\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'0 sync always sync init update \main_sdcore_data_count_sdcore_fsm_next_value_ce3 $1\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] end - attribute \src "ls180.v:1886.5-1886.56" - process $proc$ls180.v:1886$3703 + attribute \src "ls180.v:1891.5-1891.56" + process $proc$ls180.v:1891$3836 assign { } { } assign $1\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] 1'0 sync always sync init update \main_sdcore_cmd_error_sdcore_fsm_next_value4 $1\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] end - attribute \src "ls180.v:1887.5-1887.59" - process $proc$ls180.v:1887$3704 + attribute \src "ls180.v:1892.5-1892.59" + process $proc$ls180.v:1892$3837 assign { } { } assign $1\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] 1'0 sync always sync init update \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4 $1\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] end - attribute \src "ls180.v:1888.5-1888.58" - process $proc$ls180.v:1888$3705 + attribute \src "ls180.v:1893.5-1893.58" + process $proc$ls180.v:1893$3838 assign { } { } assign $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'0 sync always sync init update \main_sdcore_cmd_timeout_sdcore_fsm_next_value5 $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] end - attribute \src "ls180.v:1889.5-1889.61" - process $proc$ls180.v:1889$3706 + attribute \src "ls180.v:1894.5-1894.61" + process $proc$ls180.v:1894$3839 assign { } { } assign $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'0 sync always sync init update \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] end - attribute \src "ls180.v:189.12-189.73" - process $proc$ls180.v:189$2930 - assign { } { } - assign $1\main_libresocsim_interface2_converted_interface_dat_w[31:0] 0 - sync always - sync init - update \main_libresocsim_interface2_converted_interface_dat_w $1\main_libresocsim_interface2_converted_interface_dat_w[31:0] - end - attribute \src "ls180.v:1890.5-1890.57" - process $proc$ls180.v:1890$3707 + attribute \src "ls180.v:1895.5-1895.57" + process $proc$ls180.v:1895$3840 assign { } { } assign $1\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'0 sync always sync init update \main_sdcore_data_error_sdcore_fsm_next_value6 $1\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] end - attribute \src "ls180.v:1891.5-1891.60" - process $proc$ls180.v:1891$3708 + attribute \src "ls180.v:1896.5-1896.60" + process $proc$ls180.v:1896$3841 assign { } { } assign $1\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'0 sync always sync init update \main_sdcore_data_error_sdcore_fsm_next_value_ce6 $1\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] end - attribute \src "ls180.v:1892.5-1892.59" - process $proc$ls180.v:1892$3709 + attribute \src "ls180.v:1897.5-1897.59" + process $proc$ls180.v:1897$3842 assign { } { } assign $1\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'0 sync always sync init update \main_sdcore_data_timeout_sdcore_fsm_next_value7 $1\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] end - attribute \src "ls180.v:1893.5-1893.62" - process $proc$ls180.v:1893$3710 + attribute \src "ls180.v:1898.5-1898.62" + process $proc$ls180.v:1898$3843 assign { } { } assign $1\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'0 sync always sync init update \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7 $1\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] end - attribute \src "ls180.v:1894.13-1894.76" - process $proc$ls180.v:1894$3711 + attribute \src "ls180.v:1899.13-1899.76" + process $proc$ls180.v:1899$3844 assign { } { } assign $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] end - attribute \src "ls180.v:1895.5-1895.69" - process $proc$ls180.v:1895$3712 + attribute \src "ls180.v:190.5-190.45" + process $proc$ls180.v:190$3064 + assign { } { } + assign $1\main_libresocsim_zero_old_trigger[0:0] 1'0 + sync always + sync init + update \main_libresocsim_zero_old_trigger $1\main_libresocsim_zero_old_trigger[0:0] + end + attribute \src "ls180.v:1900.5-1900.69" + process $proc$ls180.v:1900$3845 assign { } { } assign $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'0 sync always sync init update \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] end - attribute \src "ls180.v:1896.11-1896.46" - process $proc$ls180.v:1896$3713 + attribute \src "ls180.v:1901.11-1901.46" + process $proc$ls180.v:1901$3846 assign { } { } assign $1\builder_sdblock2memdma_state[1:0] 2'00 sync always sync init update \builder_sdblock2memdma_state $1\builder_sdblock2memdma_state[1:0] end - attribute \src "ls180.v:1897.11-1897.51" - process $proc$ls180.v:1897$3714 + attribute \src "ls180.v:1902.11-1902.51" + process $proc$ls180.v:1902$3847 assign { } { } assign $1\builder_sdblock2memdma_next_state[1:0] 2'00 sync always sync init update \builder_sdblock2memdma_next_state $1\builder_sdblock2memdma_next_state[1:0] end - attribute \src "ls180.v:1898.12-1898.87" - process $proc$ls180.v:1898$3715 + attribute \src "ls180.v:1903.12-1903.87" + process $proc$ls180.v:1903$3848 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0 sync always sync init update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] end - attribute \src "ls180.v:1899.5-1899.82" - process $proc$ls180.v:1899$3716 + attribute \src "ls180.v:1904.5-1904.82" + process $proc$ls180.v:1904$3849 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'0 sync always sync init update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] end - attribute \src "ls180.v:1900.5-1900.44" - process $proc$ls180.v:1900$3717 + attribute \src "ls180.v:1905.5-1905.44" + process $proc$ls180.v:1905$3850 assign { } { } assign $1\builder_sdmem2blockdma_fsm_state[0:0] 1'0 sync always sync init update \builder_sdmem2blockdma_fsm_state $1\builder_sdmem2blockdma_fsm_state[0:0] end - attribute \src "ls180.v:1901.5-1901.49" - process $proc$ls180.v:1901$3718 + attribute \src "ls180.v:1906.5-1906.49" + process $proc$ls180.v:1906$3851 assign { } { } assign $1\builder_sdmem2blockdma_fsm_next_state[0:0] 1'0 sync always sync init update \builder_sdmem2blockdma_fsm_next_state $1\builder_sdmem2blockdma_fsm_next_state[0:0] end - attribute \src "ls180.v:1902.12-1902.75" - process $proc$ls180.v:1902$3719 + attribute \src "ls180.v:1907.12-1907.75" + process $proc$ls180.v:1907$3852 assign { } { } - assign $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] 0 + assign $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] + update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[63:0] end - attribute \src "ls180.v:1903.5-1903.70" - process $proc$ls180.v:1903$3720 + attribute \src "ls180.v:1908.5-1908.70" + process $proc$ls180.v:1908$3853 assign { } { } assign $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] end - attribute \src "ls180.v:1904.11-1904.60" - process $proc$ls180.v:1904$3721 + attribute \src "ls180.v:1909.11-1909.60" + process $proc$ls180.v:1909$3854 assign { } { } assign $1\builder_sdmem2blockdma_resetinserter_state[1:0] 2'00 sync always sync init update \builder_sdmem2blockdma_resetinserter_state $1\builder_sdmem2blockdma_resetinserter_state[1:0] end - attribute \src "ls180.v:1905.11-1905.65" - process $proc$ls180.v:1905$3722 + attribute \src "ls180.v:1910.11-1910.65" + process $proc$ls180.v:1910$3855 assign { } { } assign $1\builder_sdmem2blockdma_resetinserter_next_state[1:0] 2'00 sync always sync init update \builder_sdmem2blockdma_resetinserter_next_state $1\builder_sdmem2blockdma_resetinserter_next_state[1:0] end - attribute \src "ls180.v:1906.12-1906.87" - process $proc$ls180.v:1906$3723 + attribute \src "ls180.v:1911.12-1911.87" + process $proc$ls180.v:1911$3856 assign { } { } assign $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 sync always sync init update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] end - attribute \src "ls180.v:1907.5-1907.82" - process $proc$ls180.v:1907$3724 + attribute \src "ls180.v:1912.5-1912.82" + process $proc$ls180.v:1912$3857 assign { } { } assign $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] end - attribute \src "ls180.v:1908.12-1908.43" - process $proc$ls180.v:1908$3725 + attribute \src "ls180.v:1913.12-1913.43" + process $proc$ls180.v:1913$3858 assign { } { } assign $1\builder_libresocsim_adr[13:0] 14'00000000000000 sync always sync init update \builder_libresocsim_adr $1\builder_libresocsim_adr[13:0] end - attribute \src "ls180.v:1909.5-1909.34" - process $proc$ls180.v:1909$3726 + attribute \src "ls180.v:1914.5-1914.34" + process $proc$ls180.v:1914$3859 assign { } { } assign $1\builder_libresocsim_we[0:0] 1'0 sync always sync init update \builder_libresocsim_we $1\builder_libresocsim_we[0:0] end - attribute \src "ls180.v:191.11-191.69" - process $proc$ls180.v:191$2931 + attribute \src "ls180.v:1915.11-1915.43" + process $proc$ls180.v:1915$3860 assign { } { } - assign $1\main_libresocsim_interface2_converted_interface_sel[3:0] 4'0000 + assign $1\builder_libresocsim_dat_w[7:0] 8'00000000 sync always sync init - update \main_libresocsim_interface2_converted_interface_sel $1\main_libresocsim_interface2_converted_interface_sel[3:0] + update \builder_libresocsim_dat_w $1\builder_libresocsim_dat_w[7:0] end - attribute \src "ls180.v:1910.11-1910.43" - process $proc$ls180.v:1910$3727 + attribute \src "ls180.v:1917.12-1917.52" + process $proc$ls180.v:1917$3861 assign { } { } - assign $1\builder_libresocsim_dat_w[7:0] 8'00000000 + assign $0\builder_libresocsim_wishbone_adr[29:0] 30'000000000000000000000000000000 sync always + update \builder_libresocsim_wishbone_adr $0\builder_libresocsim_wishbone_adr[29:0] + sync init + end + attribute \src "ls180.v:1918.12-1918.54" + process $proc$ls180.v:1918$3862 + assign { } { } + assign $0\builder_libresocsim_wishbone_dat_w[31:0] 0 + sync always + update \builder_libresocsim_wishbone_dat_w $0\builder_libresocsim_wishbone_dat_w[31:0] sync init - update \builder_libresocsim_dat_w $1\builder_libresocsim_dat_w[7:0] end - attribute \src "ls180.v:1914.12-1914.54" - process $proc$ls180.v:1914$3728 + attribute \src "ls180.v:1919.12-1919.54" + process $proc$ls180.v:1919$3863 assign { } { } assign $1\builder_libresocsim_wishbone_dat_r[31:0] 0 sync always sync init update \builder_libresocsim_wishbone_dat_r $1\builder_libresocsim_wishbone_dat_r[31:0] end - attribute \src "ls180.v:1918.5-1918.44" - process $proc$ls180.v:1918$3729 + attribute \src "ls180.v:1920.11-1920.50" + process $proc$ls180.v:1920$3864 + assign { } { } + assign $0\builder_libresocsim_wishbone_sel[3:0] 4'0000 + sync always + update \builder_libresocsim_wishbone_sel $0\builder_libresocsim_wishbone_sel[3:0] + sync init + end + attribute \src "ls180.v:1921.5-1921.44" + process $proc$ls180.v:1921$3865 + assign { } { } + assign $0\builder_libresocsim_wishbone_cyc[0:0] 1'0 + sync always + update \builder_libresocsim_wishbone_cyc $0\builder_libresocsim_wishbone_cyc[0:0] + sync init + end + attribute \src "ls180.v:1922.5-1922.44" + process $proc$ls180.v:1922$3866 + assign { } { } + assign $0\builder_libresocsim_wishbone_stb[0:0] 1'0 + sync always + update \builder_libresocsim_wishbone_stb $0\builder_libresocsim_wishbone_stb[0:0] + sync init + end + attribute \src "ls180.v:1923.5-1923.44" + process $proc$ls180.v:1923$3867 assign { } { } assign $1\builder_libresocsim_wishbone_ack[0:0] 1'0 sync always sync init update \builder_libresocsim_wishbone_ack $1\builder_libresocsim_wishbone_ack[0:0] end - attribute \src "ls180.v:192.5-192.63" - process $proc$ls180.v:192$2932 + attribute \src "ls180.v:1924.5-1924.43" + process $proc$ls180.v:1924$3868 assign { } { } - assign $1\main_libresocsim_interface2_converted_interface_cyc[0:0] 1'0 + assign $0\builder_libresocsim_wishbone_we[0:0] 1'0 sync always + update \builder_libresocsim_wishbone_we $0\builder_libresocsim_wishbone_we[0:0] sync init - update \main_libresocsim_interface2_converted_interface_cyc $1\main_libresocsim_interface2_converted_interface_cyc[0:0] end - attribute \src "ls180.v:1922.5-1922.44" - process $proc$ls180.v:1922$3730 + attribute \src "ls180.v:1927.12-1927.65" + process $proc$ls180.v:1927$3869 assign { } { } - assign $0\builder_libresocsim_wishbone_err[0:0] 1'0 + assign $0\builder_libresocsim_converted_interface_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always - update \builder_libresocsim_wishbone_err $0\builder_libresocsim_wishbone_err[0:0] + update \builder_libresocsim_converted_interface_dat_r $0\builder_libresocsim_converted_interface_dat_r[63:0] sync init end - attribute \src "ls180.v:1925.12-1925.40" - process $proc$ls180.v:1925$3731 + attribute \src "ls180.v:1931.5-1931.55" + process $proc$ls180.v:1931$3870 assign { } { } - assign $1\builder_shared_dat_r[31:0] 0 + assign $0\builder_libresocsim_converted_interface_ack[0:0] 1'0 sync always + update \builder_libresocsim_converted_interface_ack $0\builder_libresocsim_converted_interface_ack[0:0] sync init - update \builder_shared_dat_r $1\builder_shared_dat_r[31:0] end - attribute \src "ls180.v:1929.5-1929.30" - process $proc$ls180.v:1929$3732 + attribute \src "ls180.v:1935.5-1935.55" + process $proc$ls180.v:1935$3871 assign { } { } - assign $1\builder_shared_ack[0:0] 1'0 + assign $0\builder_libresocsim_converted_interface_err[0:0] 1'0 sync always + update \builder_libresocsim_converted_interface_err $0\builder_libresocsim_converted_interface_err[0:0] sync init - update \builder_shared_ack $1\builder_shared_ack[0:0] end - attribute \src "ls180.v:193.5-193.63" - process $proc$ls180.v:193$2933 + attribute \src "ls180.v:1938.12-1938.40" + process $proc$ls180.v:1938$3872 + assign { } { } + assign $1\builder_shared_dat_r[31:0] 0 + sync always + sync init + update \builder_shared_dat_r $1\builder_shared_dat_r[31:0] + end + attribute \src "ls180.v:1942.5-1942.30" + process $proc$ls180.v:1942$3873 assign { } { } - assign $1\main_libresocsim_interface2_converted_interface_stb[0:0] 1'0 + assign $1\builder_shared_ack[0:0] 1'0 sync always sync init - update \main_libresocsim_interface2_converted_interface_stb $1\main_libresocsim_interface2_converted_interface_stb[0:0] + update \builder_shared_ack $1\builder_shared_ack[0:0] end - attribute \src "ls180.v:1935.11-1935.31" - process $proc$ls180.v:1935$3733 + attribute \src "ls180.v:1948.11-1948.31" + process $proc$ls180.v:1948$3874 assign { } { } assign $1\builder_grant[2:0] 3'000 sync always sync init update \builder_grant $1\builder_grant[2:0] end - attribute \src "ls180.v:1936.11-1936.35" - process $proc$ls180.v:1936$3734 + attribute \src "ls180.v:1949.11-1949.35" + process $proc$ls180.v:1949$3875 assign { } { } assign $1\builder_slave_sel[7:0] 8'00000000 sync always sync init update \builder_slave_sel $1\builder_slave_sel[7:0] end - attribute \src "ls180.v:1937.11-1937.37" - process $proc$ls180.v:1937$3735 + attribute \src "ls180.v:1950.11-1950.37" + process $proc$ls180.v:1950$3876 assign { } { } assign $1\builder_slave_sel_r[7:0] 8'00000000 sync always sync init update \builder_slave_sel_r $1\builder_slave_sel_r[7:0] end - attribute \src "ls180.v:1938.5-1938.25" - process $proc$ls180.v:1938$3736 + attribute \src "ls180.v:1951.5-1951.25" + process $proc$ls180.v:1951$3877 assign { } { } assign $1\builder_error[0:0] 1'0 sync always sync init update \builder_error $1\builder_error[0:0] end - attribute \src "ls180.v:1941.12-1941.39" - process $proc$ls180.v:1941$3737 + attribute \src "ls180.v:1954.12-1954.39" + process $proc$ls180.v:1954$3878 assign { } { } assign $1\builder_count[19:0] 20'11110100001001000000 sync always sync init update \builder_count $1\builder_count[19:0] end - attribute \src "ls180.v:1945.11-1945.51" - process $proc$ls180.v:1945$3738 + attribute \src "ls180.v:1958.11-1958.51" + process $proc$ls180.v:1958$3879 assign { } { } assign $1\builder_interface0_bank_bus_dat_r[7:0] 8'00000000 sync always sync init update \builder_interface0_bank_bus_dat_r $1\builder_interface0_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:195.5-195.62" - process $proc$ls180.v:195$2934 - assign { } { } - assign $1\main_libresocsim_interface2_converted_interface_we[0:0] 1'0 - sync always - sync init - update \main_libresocsim_interface2_converted_interface_we $1\main_libresocsim_interface2_converted_interface_we[0:0] - end - attribute \src "ls180.v:196.11-196.69" - process $proc$ls180.v:196$2935 - assign { } { } - assign $0\main_libresocsim_interface2_converted_interface_cti[2:0] 3'000 - sync always - update \main_libresocsim_interface2_converted_interface_cti $0\main_libresocsim_interface2_converted_interface_cti[2:0] - sync init - end - attribute \src "ls180.v:197.11-197.69" - process $proc$ls180.v:197$2936 + attribute \src "ls180.v:199.5-199.49" + process $proc$ls180.v:199$3065 assign { } { } - assign $0\main_libresocsim_interface2_converted_interface_bte[1:0] 2'00 + assign $1\main_libresocsim_eventmanager_storage[0:0] 1'0 sync always - update \main_libresocsim_interface2_converted_interface_bte $0\main_libresocsim_interface2_converted_interface_bte[1:0] sync init + update \main_libresocsim_eventmanager_storage $1\main_libresocsim_eventmanager_storage[0:0] end - attribute \src "ls180.v:1986.11-1986.51" - process $proc$ls180.v:1986$3739 + attribute \src "ls180.v:1999.11-1999.51" + process $proc$ls180.v:1999$3880 assign { } { } assign $1\builder_interface1_bank_bus_dat_r[7:0] 8'00000000 sync always sync init update \builder_interface1_bank_bus_dat_r $1\builder_interface1_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:199.5-199.44" - process $proc$ls180.v:199$2937 + attribute \src "ls180.v:200.5-200.44" + process $proc$ls180.v:200$3066 assign { } { } - assign $1\main_libresocsim_converter2_skip[0:0] 1'0 + assign $1\main_libresocsim_eventmanager_re[0:0] 1'0 sync always sync init - update \main_libresocsim_converter2_skip $1\main_libresocsim_converter2_skip[0:0] + update \main_libresocsim_eventmanager_re $1\main_libresocsim_eventmanager_re[0:0] end - attribute \src "ls180.v:200.5-200.47" - process $proc$ls180.v:200$2938 + attribute \src "ls180.v:201.12-201.42" + process $proc$ls180.v:201$3067 assign { } { } - assign $1\main_libresocsim_converter2_counter[0:0] 1'0 + assign $1\main_libresocsim_value[31:0] 0 sync always sync init - update \main_libresocsim_converter2_counter $1\main_libresocsim_converter2_counter[0:0] + update \main_libresocsim_value $1\main_libresocsim_value[31:0] end - attribute \src "ls180.v:2015.11-2015.51" - process $proc$ls180.v:2015$3740 + attribute \src "ls180.v:2028.11-2028.51" + process $proc$ls180.v:2028$3881 assign { } { } assign $1\builder_interface2_bank_bus_dat_r[7:0] 8'00000000 sync always sync init update \builder_interface2_bank_bus_dat_r $1\builder_interface2_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:202.12-202.53" - process $proc$ls180.v:202$2939 + attribute \src "ls180.v:2041.11-2041.51" + process $proc$ls180.v:2041$3882 assign { } { } - assign $1\main_libresocsim_converter2_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\builder_interface3_bank_bus_dat_r[7:0] 8'00000000 sync always sync init - update \main_libresocsim_converter2_dat_r $1\main_libresocsim_converter2_dat_r[63:0] + update \builder_interface3_bank_bus_dat_r $1\builder_interface3_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:2028.11-2028.51" - process $proc$ls180.v:2028$3741 + attribute \src "ls180.v:208.5-208.39" + process $proc$ls180.v:208$3068 assign { } { } - assign $1\builder_interface3_bank_bus_dat_r[7:0] 8'00000000 + assign $1\main_interface0_ram_bus_ack[0:0] 1'0 sync always sync init - update \builder_interface3_bank_bus_dat_r $1\builder_interface3_bank_bus_dat_r[7:0] + update \main_interface0_ram_bus_ack $1\main_interface0_ram_bus_ack[0:0] end - attribute \src "ls180.v:2069.11-2069.51" - process $proc$ls180.v:2069$3742 + attribute \src "ls180.v:2082.11-2082.51" + process $proc$ls180.v:2082$3883 assign { } { } assign $1\builder_interface4_bank_bus_dat_r[7:0] 8'00000000 sync always sync init update \builder_interface4_bank_bus_dat_r $1\builder_interface4_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:209.5-209.40" - process $proc$ls180.v:209$2940 + attribute \src "ls180.v:212.5-212.39" + process $proc$ls180.v:212$3069 assign { } { } - assign $1\main_libresocsim_ram_bus_ack[0:0] 1'0 + assign $0\main_interface0_ram_bus_err[0:0] 1'0 sync always + update \main_interface0_ram_bus_err $0\main_interface0_ram_bus_err[0:0] sync init - update \main_libresocsim_ram_bus_ack $1\main_libresocsim_ram_bus_ack[0:0] end - attribute \src "ls180.v:2110.11-2110.51" - process $proc$ls180.v:2110$3743 + attribute \src "ls180.v:2123.11-2123.51" + process $proc$ls180.v:2123$3884 assign { } { } assign $1\builder_interface5_bank_bus_dat_r[7:0] 8'00000000 sync always sync init update \builder_interface5_bank_bus_dat_r $1\builder_interface5_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:213.5-213.40" - process $proc$ls180.v:213$2941 - assign { } { } - assign $0\main_libresocsim_ram_bus_err[0:0] 1'0 - sync always - update \main_libresocsim_ram_bus_err $0\main_libresocsim_ram_bus_err[0:0] - sync init - end - attribute \src "ls180.v:216.11-216.37" - process $proc$ls180.v:216$2942 + attribute \src "ls180.v:215.11-215.31" + process $proc$ls180.v:215$3070 assign { } { } - assign $1\main_libresocsim_we[3:0] 4'0000 + assign $1\main_sram0_we[7:0] 8'00000000 sync always sync init - update \main_libresocsim_we $1\main_libresocsim_we[3:0] + update \main_sram0_we $1\main_sram0_we[7:0] end - attribute \src "ls180.v:2175.11-2175.51" - process $proc$ls180.v:2175$3744 + attribute \src "ls180.v:2188.11-2188.51" + process $proc$ls180.v:2188$3885 assign { } { } assign $1\builder_interface6_bank_bus_dat_r[7:0] 8'00000000 sync always sync init update \builder_interface6_bank_bus_dat_r $1\builder_interface6_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:218.12-218.49" - process $proc$ls180.v:218$2943 - assign { } { } - assign $1\main_libresocsim_load_storage[31:0] 0 - sync always - sync init - update \main_libresocsim_load_storage $1\main_libresocsim_load_storage[31:0] - end - attribute \src "ls180.v:219.5-219.36" - process $proc$ls180.v:219$2944 - assign { } { } - assign $1\main_libresocsim_load_re[0:0] 1'0 - sync always - sync init - update \main_libresocsim_load_re $1\main_libresocsim_load_re[0:0] - end - attribute \src "ls180.v:220.12-220.51" - process $proc$ls180.v:220$2945 - assign { } { } - assign $1\main_libresocsim_reload_storage[31:0] 0 - sync always - sync init - update \main_libresocsim_reload_storage $1\main_libresocsim_reload_storage[31:0] - end - attribute \src "ls180.v:221.5-221.38" - process $proc$ls180.v:221$2946 - assign { } { } - assign $1\main_libresocsim_reload_re[0:0] 1'0 - sync always - sync init - update \main_libresocsim_reload_re $1\main_libresocsim_reload_re[0:0] - end - attribute \src "ls180.v:222.5-222.39" - process $proc$ls180.v:222$2947 + attribute \src "ls180.v:223.5-223.39" + process $proc$ls180.v:223$3071 assign { } { } - assign $1\main_libresocsim_en_storage[0:0] 1'0 - sync always - sync init - update \main_libresocsim_en_storage $1\main_libresocsim_en_storage[0:0] - end - attribute \src "ls180.v:223.5-223.34" - process $proc$ls180.v:223$2948 - assign { } { } - assign $1\main_libresocsim_en_re[0:0] 1'0 - sync always - sync init - update \main_libresocsim_en_re $1\main_libresocsim_en_re[0:0] - end - attribute \src "ls180.v:224.5-224.49" - process $proc$ls180.v:224$2949 - assign { } { } - assign $1\main_libresocsim_update_value_storage[0:0] 1'0 - sync always - sync init - update \main_libresocsim_update_value_storage $1\main_libresocsim_update_value_storage[0:0] - end - attribute \src "ls180.v:225.5-225.44" - process $proc$ls180.v:225$2950 - assign { } { } - assign $1\main_libresocsim_update_value_re[0:0] 1'0 + assign $1\main_interface1_ram_bus_ack[0:0] 1'0 sync always sync init - update \main_libresocsim_update_value_re $1\main_libresocsim_update_value_re[0:0] + update \main_interface1_ram_bus_ack $1\main_interface1_ram_bus_ack[0:0] end - attribute \src "ls180.v:226.12-226.49" - process $proc$ls180.v:226$2951 + attribute \src "ls180.v:227.5-227.39" + process $proc$ls180.v:227$3072 assign { } { } - assign $1\main_libresocsim_value_status[31:0] 0 + assign $0\main_interface1_ram_bus_err[0:0] 1'0 sync always + update \main_interface1_ram_bus_err $0\main_interface1_ram_bus_err[0:0] sync init - update \main_libresocsim_value_status $1\main_libresocsim_value_status[31:0] end - attribute \src "ls180.v:230.5-230.41" - process $proc$ls180.v:230$2952 + attribute \src "ls180.v:230.11-230.31" + process $proc$ls180.v:230$3073 assign { } { } - assign $1\main_libresocsim_zero_pending[0:0] 1'0 + assign $1\main_sram1_we[7:0] 8'00000000 sync always sync init - update \main_libresocsim_zero_pending $1\main_libresocsim_zero_pending[0:0] + update \main_sram1_we $1\main_sram1_we[7:0] end - attribute \src "ls180.v:2308.11-2308.51" - process $proc$ls180.v:2308$3745 + attribute \src "ls180.v:2321.11-2321.51" + process $proc$ls180.v:2321$3886 assign { } { } assign $1\builder_interface7_bank_bus_dat_r[7:0] 8'00000000 sync always sync init update \builder_interface7_bank_bus_dat_r $1\builder_interface7_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:232.5-232.39" - process $proc$ls180.v:232$2953 - assign { } { } - assign $1\main_libresocsim_zero_clear[0:0] 1'0 - sync always - sync init - update \main_libresocsim_zero_clear $1\main_libresocsim_zero_clear[0:0] - end - attribute \src "ls180.v:233.5-233.45" - process $proc$ls180.v:233$2954 + attribute \src "ls180.v:238.5-238.39" + process $proc$ls180.v:238$3074 assign { } { } - assign $1\main_libresocsim_zero_old_trigger[0:0] 1'0 + assign $1\main_interface2_ram_bus_ack[0:0] 1'0 sync always sync init - update \main_libresocsim_zero_old_trigger $1\main_libresocsim_zero_old_trigger[0:0] + update \main_interface2_ram_bus_ack $1\main_interface2_ram_bus_ack[0:0] end - attribute \src "ls180.v:2389.11-2389.51" - process $proc$ls180.v:2389$3746 + attribute \src "ls180.v:2402.11-2402.51" + process $proc$ls180.v:2402$3887 assign { } { } assign $1\builder_interface8_bank_bus_dat_r[7:0] 8'00000000 sync always sync init update \builder_interface8_bank_bus_dat_r $1\builder_interface8_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:2406.11-2406.51" - process $proc$ls180.v:2406$3747 + attribute \src "ls180.v:2419.11-2419.51" + process $proc$ls180.v:2419$3888 assign { } { } assign $1\builder_interface9_bank_bus_dat_r[7:0] 8'00000000 sync always sync init update \builder_interface9_bank_bus_dat_r $1\builder_interface9_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:242.5-242.49" - process $proc$ls180.v:242$2955 - assign { } { } - assign $1\main_libresocsim_eventmanager_storage[0:0] 1'0 - sync always - sync init - update \main_libresocsim_eventmanager_storage $1\main_libresocsim_eventmanager_storage[0:0] - end - attribute \src "ls180.v:243.5-243.44" - process $proc$ls180.v:243$2956 + attribute \src "ls180.v:242.5-242.39" + process $proc$ls180.v:242$3075 assign { } { } - assign $1\main_libresocsim_eventmanager_re[0:0] 1'0 + assign $0\main_interface2_ram_bus_err[0:0] 1'0 sync always + update \main_interface2_ram_bus_err $0\main_interface2_ram_bus_err[0:0] sync init - update \main_libresocsim_eventmanager_re $1\main_libresocsim_eventmanager_re[0:0] end - attribute \src "ls180.v:244.12-244.42" - process $proc$ls180.v:244$2957 + attribute \src "ls180.v:245.11-245.31" + process $proc$ls180.v:245$3076 assign { } { } - assign $1\main_libresocsim_value[31:0] 0 + assign $1\main_sram2_we[7:0] 8'00000000 sync always sync init - update \main_libresocsim_value $1\main_libresocsim_value[31:0] + update \main_sram2_we $1\main_sram2_we[7:0] end - attribute \src "ls180.v:2447.11-2447.52" - process $proc$ls180.v:2447$3748 + attribute \src "ls180.v:2460.11-2460.52" + process $proc$ls180.v:2460$3889 assign { } { } assign $1\builder_interface10_bank_bus_dat_r[7:0] 8'00000000 sync always sync init update \builder_interface10_bank_bus_dat_r $1\builder_interface10_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:2480.11-2480.52" - process $proc$ls180.v:2480$3749 + attribute \src "ls180.v:2493.11-2493.52" + process $proc$ls180.v:2493$3890 assign { } { } assign $1\builder_interface11_bank_bus_dat_r[7:0] 8'00000000 sync always sync init update \builder_interface11_bank_bus_dat_r $1\builder_interface11_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:251.5-251.39" - process $proc$ls180.v:251$2958 + attribute \src "ls180.v:253.5-253.51" + process $proc$ls180.v:253$3077 assign { } { } - assign $1\main_interface0_ram_bus_ack[0:0] 1'0 + assign $1\main_interface0_converted_interface_ack[0:0] 1'0 sync always sync init - update \main_interface0_ram_bus_ack $1\main_interface0_ram_bus_ack[0:0] + update \main_interface0_converted_interface_ack $1\main_interface0_converted_interface_ack[0:0] end - attribute \src "ls180.v:2521.11-2521.52" - process $proc$ls180.v:2521$3750 + attribute \src "ls180.v:2534.11-2534.52" + process $proc$ls180.v:2534$3891 assign { } { } assign $1\builder_interface12_bank_bus_dat_r[7:0] 8'00000000 sync always sync init update \builder_interface12_bank_bus_dat_r $1\builder_interface12_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:255.5-255.39" - process $proc$ls180.v:255$2959 + attribute \src "ls180.v:257.5-257.51" + process $proc$ls180.v:257$3078 assign { } { } - assign $0\main_interface0_ram_bus_err[0:0] 1'0 + assign $0\main_interface0_converted_interface_err[0:0] 1'0 + sync always + update \main_interface0_converted_interface_err $0\main_interface0_converted_interface_err[0:0] + sync init + end + attribute \src "ls180.v:258.5-258.32" + process $proc$ls180.v:258$3079 + assign { } { } + assign $1\main_converter0_skip[0:0] 1'0 sync always - update \main_interface0_ram_bus_err $0\main_interface0_ram_bus_err[0:0] sync init + update \main_converter0_skip $1\main_converter0_skip[0:0] end - attribute \src "ls180.v:258.11-258.31" - process $proc$ls180.v:258$2960 + attribute \src "ls180.v:259.5-259.35" + process $proc$ls180.v:259$3080 assign { } { } - assign $1\main_sram0_we[3:0] 4'0000 + assign $1\main_converter0_counter[0:0] 1'0 sync always sync init - update \main_sram0_we $1\main_sram0_we[3:0] + update \main_converter0_counter $1\main_converter0_counter[0:0] end - attribute \src "ls180.v:2586.11-2586.52" - process $proc$ls180.v:2586$3751 + attribute \src "ls180.v:2599.11-2599.52" + process $proc$ls180.v:2599$3892 assign { } { } assign $1\builder_interface13_bank_bus_dat_r[7:0] 8'00000000 sync always sync init update \builder_interface13_bank_bus_dat_r $1\builder_interface13_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:2611.11-2611.52" - process $proc$ls180.v:2611$3752 + attribute \src "ls180.v:261.12-261.41" + process $proc$ls180.v:261$3081 + assign { } { } + assign $1\main_converter0_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \main_converter0_dat_r $1\main_converter0_dat_r[63:0] + end + attribute \src "ls180.v:2624.11-2624.52" + process $proc$ls180.v:2624$3893 assign { } { } assign $1\builder_interface14_bank_bus_dat_r[7:0] 8'00000000 sync always sync init update \builder_interface14_bank_bus_dat_r $1\builder_interface14_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:2633.11-2633.31" - process $proc$ls180.v:2633$3753 + attribute \src "ls180.v:2646.11-2646.31" + process $proc$ls180.v:2646$3894 assign { } { } assign $1\builder_state[1:0] 2'00 sync always sync init update \builder_state $1\builder_state[1:0] end - attribute \src "ls180.v:2634.11-2634.36" - process $proc$ls180.v:2634$3754 + attribute \src "ls180.v:2647.11-2647.36" + process $proc$ls180.v:2647$3895 assign { } { } assign $1\builder_next_state[1:0] 2'00 sync always sync init update \builder_next_state $1\builder_next_state[1:0] end - attribute \src "ls180.v:2635.11-2635.55" - process $proc$ls180.v:2635$3755 + attribute \src "ls180.v:2648.11-2648.55" + process $proc$ls180.v:2648$3896 assign { } { } assign $1\builder_libresocsim_dat_w_next_value0[7:0] 8'00000000 sync always sync init update \builder_libresocsim_dat_w_next_value0 $1\builder_libresocsim_dat_w_next_value0[7:0] end - attribute \src "ls180.v:2636.5-2636.52" - process $proc$ls180.v:2636$3756 + attribute \src "ls180.v:2649.5-2649.52" + process $proc$ls180.v:2649$3897 assign { } { } assign $1\builder_libresocsim_dat_w_next_value_ce0[0:0] 1'0 sync always sync init update \builder_libresocsim_dat_w_next_value_ce0 $1\builder_libresocsim_dat_w_next_value_ce0[0:0] end - attribute \src "ls180.v:2637.12-2637.55" - process $proc$ls180.v:2637$3757 + attribute \src "ls180.v:2650.12-2650.55" + process $proc$ls180.v:2650$3898 assign { } { } assign $1\builder_libresocsim_adr_next_value1[13:0] 14'00000000000000 sync always sync init update \builder_libresocsim_adr_next_value1 $1\builder_libresocsim_adr_next_value1[13:0] end - attribute \src "ls180.v:2638.5-2638.50" - process $proc$ls180.v:2638$3758 + attribute \src "ls180.v:2651.5-2651.50" + process $proc$ls180.v:2651$3899 assign { } { } assign $1\builder_libresocsim_adr_next_value_ce1[0:0] 1'0 sync always sync init update \builder_libresocsim_adr_next_value_ce1 $1\builder_libresocsim_adr_next_value_ce1[0:0] end - attribute \src "ls180.v:2639.5-2639.46" - process $proc$ls180.v:2639$3759 + attribute \src "ls180.v:2652.5-2652.46" + process $proc$ls180.v:2652$3900 assign { } { } assign $1\builder_libresocsim_we_next_value2[0:0] 1'0 sync always sync init update \builder_libresocsim_we_next_value2 $1\builder_libresocsim_we_next_value2[0:0] end - attribute \src "ls180.v:2640.5-2640.49" - process $proc$ls180.v:2640$3760 + attribute \src "ls180.v:2653.5-2653.49" + process $proc$ls180.v:2653$3901 assign { } { } assign $1\builder_libresocsim_we_next_value_ce2[0:0] 1'0 sync always sync init update \builder_libresocsim_we_next_value_ce2 $1\builder_libresocsim_we_next_value_ce2[0:0] end - attribute \src "ls180.v:2641.5-2641.41" - process $proc$ls180.v:2641$3761 + attribute \src "ls180.v:2654.5-2654.41" + process $proc$ls180.v:2654$3902 assign { } { } assign $1\builder_comb_rhs_array_muxed0[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed0 $1\builder_comb_rhs_array_muxed0[0:0] end - attribute \src "ls180.v:2642.12-2642.49" - process $proc$ls180.v:2642$3762 + attribute \src "ls180.v:2655.12-2655.49" + process $proc$ls180.v:2655$3903 assign { } { } assign $1\builder_comb_rhs_array_muxed1[12:0] 13'0000000000000 sync always sync init update \builder_comb_rhs_array_muxed1 $1\builder_comb_rhs_array_muxed1[12:0] end - attribute \src "ls180.v:2643.11-2643.47" - process $proc$ls180.v:2643$3763 + attribute \src "ls180.v:2656.11-2656.47" + process $proc$ls180.v:2656$3904 assign { } { } assign $1\builder_comb_rhs_array_muxed2[1:0] 2'00 sync always sync init update \builder_comb_rhs_array_muxed2 $1\builder_comb_rhs_array_muxed2[1:0] end - attribute \src "ls180.v:2644.5-2644.41" - process $proc$ls180.v:2644$3764 + attribute \src "ls180.v:2657.5-2657.41" + process $proc$ls180.v:2657$3905 assign { } { } assign $1\builder_comb_rhs_array_muxed3[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed3 $1\builder_comb_rhs_array_muxed3[0:0] end - attribute \src "ls180.v:2645.5-2645.41" - process $proc$ls180.v:2645$3765 + attribute \src "ls180.v:2658.5-2658.41" + process $proc$ls180.v:2658$3906 assign { } { } assign $1\builder_comb_rhs_array_muxed4[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed4 $1\builder_comb_rhs_array_muxed4[0:0] end - attribute \src "ls180.v:2646.5-2646.41" - process $proc$ls180.v:2646$3766 + attribute \src "ls180.v:2659.5-2659.41" + process $proc$ls180.v:2659$3907 assign { } { } assign $1\builder_comb_rhs_array_muxed5[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed5 $1\builder_comb_rhs_array_muxed5[0:0] end - attribute \src "ls180.v:2647.5-2647.39" - process $proc$ls180.v:2647$3767 + attribute \src "ls180.v:2660.5-2660.39" + process $proc$ls180.v:2660$3908 assign { } { } assign $1\builder_comb_t_array_muxed0[0:0] 1'0 sync always sync init update \builder_comb_t_array_muxed0 $1\builder_comb_t_array_muxed0[0:0] end - attribute \src "ls180.v:2648.5-2648.39" - process $proc$ls180.v:2648$3768 + attribute \src "ls180.v:2661.5-2661.39" + process $proc$ls180.v:2661$3909 assign { } { } assign $1\builder_comb_t_array_muxed1[0:0] 1'0 sync always sync init update \builder_comb_t_array_muxed1 $1\builder_comb_t_array_muxed1[0:0] end - attribute \src "ls180.v:2649.5-2649.39" - process $proc$ls180.v:2649$3769 + attribute \src "ls180.v:2662.5-2662.39" + process $proc$ls180.v:2662$3910 assign { } { } assign $1\builder_comb_t_array_muxed2[0:0] 1'0 sync always sync init update \builder_comb_t_array_muxed2 $1\builder_comb_t_array_muxed2[0:0] end - attribute \src "ls180.v:2650.5-2650.41" - process $proc$ls180.v:2650$3770 + attribute \src "ls180.v:2663.5-2663.41" + process $proc$ls180.v:2663$3911 assign { } { } assign $1\builder_comb_rhs_array_muxed6[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed6 $1\builder_comb_rhs_array_muxed6[0:0] end - attribute \src "ls180.v:2651.12-2651.49" - process $proc$ls180.v:2651$3771 + attribute \src "ls180.v:2664.12-2664.49" + process $proc$ls180.v:2664$3912 assign { } { } assign $1\builder_comb_rhs_array_muxed7[12:0] 13'0000000000000 sync always sync init update \builder_comb_rhs_array_muxed7 $1\builder_comb_rhs_array_muxed7[12:0] end - attribute \src "ls180.v:2652.11-2652.47" - process $proc$ls180.v:2652$3772 + attribute \src "ls180.v:2665.11-2665.47" + process $proc$ls180.v:2665$3913 assign { } { } assign $1\builder_comb_rhs_array_muxed8[1:0] 2'00 sync always sync init update \builder_comb_rhs_array_muxed8 $1\builder_comb_rhs_array_muxed8[1:0] end - attribute \src "ls180.v:2653.5-2653.41" - process $proc$ls180.v:2653$3773 + attribute \src "ls180.v:2666.5-2666.41" + process $proc$ls180.v:2666$3914 assign { } { } assign $1\builder_comb_rhs_array_muxed9[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed9 $1\builder_comb_rhs_array_muxed9[0:0] end - attribute \src "ls180.v:2654.5-2654.42" - process $proc$ls180.v:2654$3774 + attribute \src "ls180.v:2667.5-2667.42" + process $proc$ls180.v:2667$3915 assign { } { } assign $1\builder_comb_rhs_array_muxed10[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed10 $1\builder_comb_rhs_array_muxed10[0:0] end - attribute \src "ls180.v:2655.5-2655.42" - process $proc$ls180.v:2655$3775 + attribute \src "ls180.v:2668.5-2668.42" + process $proc$ls180.v:2668$3916 assign { } { } assign $1\builder_comb_rhs_array_muxed11[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed11 $1\builder_comb_rhs_array_muxed11[0:0] end - attribute \src "ls180.v:2656.5-2656.39" - process $proc$ls180.v:2656$3776 + attribute \src "ls180.v:2669.5-2669.39" + process $proc$ls180.v:2669$3917 assign { } { } assign $1\builder_comb_t_array_muxed3[0:0] 1'0 sync always sync init update \builder_comb_t_array_muxed3 $1\builder_comb_t_array_muxed3[0:0] end - attribute \src "ls180.v:2657.5-2657.39" - process $proc$ls180.v:2657$3777 + attribute \src "ls180.v:2670.5-2670.39" + process $proc$ls180.v:2670$3918 assign { } { } assign $1\builder_comb_t_array_muxed4[0:0] 1'0 sync always sync init update \builder_comb_t_array_muxed4 $1\builder_comb_t_array_muxed4[0:0] end - attribute \src "ls180.v:2658.5-2658.39" - process $proc$ls180.v:2658$3778 + attribute \src "ls180.v:2671.5-2671.39" + process $proc$ls180.v:2671$3919 assign { } { } assign $1\builder_comb_t_array_muxed5[0:0] 1'0 sync always sync init update \builder_comb_t_array_muxed5 $1\builder_comb_t_array_muxed5[0:0] end - attribute \src "ls180.v:2659.12-2659.50" - process $proc$ls180.v:2659$3779 + attribute \src "ls180.v:2672.12-2672.50" + process $proc$ls180.v:2672$3920 assign { } { } assign $1\builder_comb_rhs_array_muxed12[21:0] 22'0000000000000000000000 sync always sync init update \builder_comb_rhs_array_muxed12 $1\builder_comb_rhs_array_muxed12[21:0] end - attribute \src "ls180.v:266.5-266.39" - process $proc$ls180.v:266$2961 - assign { } { } - assign $1\main_interface1_ram_bus_ack[0:0] 1'0 - sync always - sync init - update \main_interface1_ram_bus_ack $1\main_interface1_ram_bus_ack[0:0] - end - attribute \src "ls180.v:2660.5-2660.42" - process $proc$ls180.v:2660$3780 + attribute \src "ls180.v:2673.5-2673.42" + process $proc$ls180.v:2673$3921 assign { } { } assign $1\builder_comb_rhs_array_muxed13[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed13 $1\builder_comb_rhs_array_muxed13[0:0] end - attribute \src "ls180.v:2661.5-2661.42" - process $proc$ls180.v:2661$3781 + attribute \src "ls180.v:2674.5-2674.42" + process $proc$ls180.v:2674$3922 assign { } { } assign $1\builder_comb_rhs_array_muxed14[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed14 $1\builder_comb_rhs_array_muxed14[0:0] end - attribute \src "ls180.v:2662.12-2662.50" - process $proc$ls180.v:2662$3782 + attribute \src "ls180.v:2675.12-2675.50" + process $proc$ls180.v:2675$3923 assign { } { } assign $1\builder_comb_rhs_array_muxed15[21:0] 22'0000000000000000000000 sync always sync init update \builder_comb_rhs_array_muxed15 $1\builder_comb_rhs_array_muxed15[21:0] end - attribute \src "ls180.v:2663.5-2663.42" - process $proc$ls180.v:2663$3783 + attribute \src "ls180.v:2676.5-2676.42" + process $proc$ls180.v:2676$3924 assign { } { } assign $1\builder_comb_rhs_array_muxed16[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed16 $1\builder_comb_rhs_array_muxed16[0:0] end - attribute \src "ls180.v:2664.5-2664.42" - process $proc$ls180.v:2664$3784 + attribute \src "ls180.v:2677.5-2677.42" + process $proc$ls180.v:2677$3925 assign { } { } assign $1\builder_comb_rhs_array_muxed17[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed17 $1\builder_comb_rhs_array_muxed17[0:0] end - attribute \src "ls180.v:2665.12-2665.50" - process $proc$ls180.v:2665$3785 + attribute \src "ls180.v:2678.12-2678.50" + process $proc$ls180.v:2678$3926 assign { } { } assign $1\builder_comb_rhs_array_muxed18[21:0] 22'0000000000000000000000 sync always sync init update \builder_comb_rhs_array_muxed18 $1\builder_comb_rhs_array_muxed18[21:0] end - attribute \src "ls180.v:2666.5-2666.42" - process $proc$ls180.v:2666$3786 + attribute \src "ls180.v:2679.5-2679.42" + process $proc$ls180.v:2679$3927 assign { } { } assign $1\builder_comb_rhs_array_muxed19[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed19 $1\builder_comb_rhs_array_muxed19[0:0] end - attribute \src "ls180.v:2667.5-2667.42" - process $proc$ls180.v:2667$3787 + attribute \src "ls180.v:268.5-268.51" + process $proc$ls180.v:268$3082 + assign { } { } + assign $1\main_interface1_converted_interface_ack[0:0] 1'0 + sync always + sync init + update \main_interface1_converted_interface_ack $1\main_interface1_converted_interface_ack[0:0] + end + attribute \src "ls180.v:2680.5-2680.42" + process $proc$ls180.v:2680$3928 assign { } { } assign $1\builder_comb_rhs_array_muxed20[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed20 $1\builder_comb_rhs_array_muxed20[0:0] end - attribute \src "ls180.v:2668.12-2668.50" - process $proc$ls180.v:2668$3788 + attribute \src "ls180.v:2681.12-2681.50" + process $proc$ls180.v:2681$3929 assign { } { } assign $1\builder_comb_rhs_array_muxed21[21:0] 22'0000000000000000000000 sync always sync init update \builder_comb_rhs_array_muxed21 $1\builder_comb_rhs_array_muxed21[21:0] end - attribute \src "ls180.v:2669.5-2669.42" - process $proc$ls180.v:2669$3789 + attribute \src "ls180.v:2682.5-2682.42" + process $proc$ls180.v:2682$3930 assign { } { } assign $1\builder_comb_rhs_array_muxed22[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed22 $1\builder_comb_rhs_array_muxed22[0:0] end - attribute \src "ls180.v:2670.5-2670.42" - process $proc$ls180.v:2670$3790 + attribute \src "ls180.v:2683.5-2683.42" + process $proc$ls180.v:2683$3931 assign { } { } assign $1\builder_comb_rhs_array_muxed23[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed23 $1\builder_comb_rhs_array_muxed23[0:0] end - attribute \src "ls180.v:2671.12-2671.50" - process $proc$ls180.v:2671$3791 + attribute \src "ls180.v:2684.12-2684.50" + process $proc$ls180.v:2684$3932 assign { } { } assign $1\builder_comb_rhs_array_muxed24[31:0] 0 sync always sync init update \builder_comb_rhs_array_muxed24 $1\builder_comb_rhs_array_muxed24[31:0] end - attribute \src "ls180.v:2672.12-2672.50" - process $proc$ls180.v:2672$3792 + attribute \src "ls180.v:2685.12-2685.50" + process $proc$ls180.v:2685$3933 assign { } { } - assign $1\builder_comb_rhs_array_muxed25[31:0] 0 + assign $1\builder_comb_rhs_array_muxed25[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \builder_comb_rhs_array_muxed25 $1\builder_comb_rhs_array_muxed25[31:0] + update \builder_comb_rhs_array_muxed25 $1\builder_comb_rhs_array_muxed25[63:0] end - attribute \src "ls180.v:2673.11-2673.48" - process $proc$ls180.v:2673$3793 + attribute \src "ls180.v:2686.11-2686.48" + process $proc$ls180.v:2686$3934 assign { } { } - assign $1\builder_comb_rhs_array_muxed26[3:0] 4'0000 + assign $1\builder_comb_rhs_array_muxed26[7:0] 8'00000000 sync always sync init - update \builder_comb_rhs_array_muxed26 $1\builder_comb_rhs_array_muxed26[3:0] + update \builder_comb_rhs_array_muxed26 $1\builder_comb_rhs_array_muxed26[7:0] end - attribute \src "ls180.v:2674.5-2674.42" - process $proc$ls180.v:2674$3794 + attribute \src "ls180.v:2687.5-2687.42" + process $proc$ls180.v:2687$3935 assign { } { } assign $1\builder_comb_rhs_array_muxed27[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed27 $1\builder_comb_rhs_array_muxed27[0:0] end - attribute \src "ls180.v:2675.5-2675.42" - process $proc$ls180.v:2675$3795 + attribute \src "ls180.v:2688.5-2688.42" + process $proc$ls180.v:2688$3936 assign { } { } assign $1\builder_comb_rhs_array_muxed28[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed28 $1\builder_comb_rhs_array_muxed28[0:0] end - attribute \src "ls180.v:2676.5-2676.42" - process $proc$ls180.v:2676$3796 + attribute \src "ls180.v:2689.5-2689.42" + process $proc$ls180.v:2689$3937 assign { } { } assign $1\builder_comb_rhs_array_muxed29[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed29 $1\builder_comb_rhs_array_muxed29[0:0] end - attribute \src "ls180.v:2677.11-2677.48" - process $proc$ls180.v:2677$3797 + attribute \src "ls180.v:2690.11-2690.48" + process $proc$ls180.v:2690$3938 assign { } { } assign $1\builder_comb_rhs_array_muxed30[2:0] 3'000 sync always sync init update \builder_comb_rhs_array_muxed30 $1\builder_comb_rhs_array_muxed30[2:0] end - attribute \src "ls180.v:2678.11-2678.48" - process $proc$ls180.v:2678$3798 + attribute \src "ls180.v:2691.11-2691.48" + process $proc$ls180.v:2691$3939 assign { } { } assign $1\builder_comb_rhs_array_muxed31[1:0] 2'00 sync always sync init update \builder_comb_rhs_array_muxed31 $1\builder_comb_rhs_array_muxed31[1:0] end - attribute \src "ls180.v:2679.11-2679.47" - process $proc$ls180.v:2679$3799 + attribute \src "ls180.v:2692.11-2692.47" + process $proc$ls180.v:2692$3940 assign { } { } assign $1\builder_sync_rhs_array_muxed0[1:0] 2'00 sync always sync init update \builder_sync_rhs_array_muxed0 $1\builder_sync_rhs_array_muxed0[1:0] end - attribute \src "ls180.v:2680.12-2680.49" - process $proc$ls180.v:2680$3800 + attribute \src "ls180.v:2693.12-2693.49" + process $proc$ls180.v:2693$3941 assign { } { } assign $1\builder_sync_rhs_array_muxed1[12:0] 13'0000000000000 sync always sync init update \builder_sync_rhs_array_muxed1 $1\builder_sync_rhs_array_muxed1[12:0] end - attribute \src "ls180.v:2681.5-2681.41" - process $proc$ls180.v:2681$3801 + attribute \src "ls180.v:2694.5-2694.41" + process $proc$ls180.v:2694$3942 assign { } { } assign $1\builder_sync_rhs_array_muxed2[0:0] 1'0 sync always sync init update \builder_sync_rhs_array_muxed2 $1\builder_sync_rhs_array_muxed2[0:0] end - attribute \src "ls180.v:2682.5-2682.41" - process $proc$ls180.v:2682$3802 + attribute \src "ls180.v:2695.5-2695.41" + process $proc$ls180.v:2695$3943 assign { } { } assign $1\builder_sync_rhs_array_muxed3[0:0] 1'0 sync always sync init update \builder_sync_rhs_array_muxed3 $1\builder_sync_rhs_array_muxed3[0:0] end - attribute \src "ls180.v:2683.5-2683.41" - process $proc$ls180.v:2683$3803 + attribute \src "ls180.v:2696.5-2696.41" + process $proc$ls180.v:2696$3944 assign { } { } assign $1\builder_sync_rhs_array_muxed4[0:0] 1'0 sync always sync init update \builder_sync_rhs_array_muxed4 $1\builder_sync_rhs_array_muxed4[0:0] end - attribute \src "ls180.v:2684.5-2684.41" - process $proc$ls180.v:2684$3804 + attribute \src "ls180.v:2697.5-2697.41" + process $proc$ls180.v:2697$3945 assign { } { } assign $1\builder_sync_rhs_array_muxed5[0:0] 1'0 sync always sync init update \builder_sync_rhs_array_muxed5 $1\builder_sync_rhs_array_muxed5[0:0] end - attribute \src "ls180.v:2685.5-2685.41" - process $proc$ls180.v:2685$3805 + attribute \src "ls180.v:2698.5-2698.41" + process $proc$ls180.v:2698$3946 assign { } { } assign $1\builder_sync_rhs_array_muxed6[0:0] 1'0 sync always sync init update \builder_sync_rhs_array_muxed6 $1\builder_sync_rhs_array_muxed6[0:0] end - attribute \src "ls180.v:2686.5-2686.39" - process $proc$ls180.v:2686$3806 + attribute \src "ls180.v:2699.5-2699.39" + process $proc$ls180.v:2699$3947 assign { } { } assign $1\builder_sync_f_array_muxed0[0:0] 1'0 sync always sync init update \builder_sync_f_array_muxed0 $1\builder_sync_f_array_muxed0[0:0] end - attribute \src "ls180.v:2687.5-2687.39" - process $proc$ls180.v:2687$3807 + attribute \src "ls180.v:2700.5-2700.39" + process $proc$ls180.v:2700$3948 assign { } { } assign $1\builder_sync_f_array_muxed1[0:0] 1'0 sync always sync init update \builder_sync_f_array_muxed1 $1\builder_sync_f_array_muxed1[0:0] end - attribute \src "ls180.v:270.5-270.39" - process $proc$ls180.v:270$2962 + attribute \src "ls180.v:272.5-272.51" + process $proc$ls180.v:272$3083 assign { } { } - assign $0\main_interface1_ram_bus_err[0:0] 1'0 + assign $0\main_interface1_converted_interface_err[0:0] 1'0 + sync always + update \main_interface1_converted_interface_err $0\main_interface1_converted_interface_err[0:0] + sync init + end + attribute \src "ls180.v:273.5-273.32" + process $proc$ls180.v:273$3084 + assign { } { } + assign $1\main_converter1_skip[0:0] 1'0 sync always - update \main_interface1_ram_bus_err $0\main_interface1_ram_bus_err[0:0] sync init + update \main_converter1_skip $1\main_converter1_skip[0:0] end - attribute \src "ls180.v:273.11-273.31" - process $proc$ls180.v:273$2963 + attribute \src "ls180.v:274.5-274.35" + process $proc$ls180.v:274$3085 assign { } { } - assign $1\main_sram1_we[3:0] 4'0000 + assign $1\main_converter1_counter[0:0] 1'0 sync always sync init - update \main_sram1_we $1\main_sram1_we[3:0] + update \main_converter1_counter $1\main_converter1_counter[0:0] end - attribute \src "ls180.v:2744.32-2744.66" - process $proc$ls180.v:2744$3808 + attribute \src "ls180.v:2757.32-2757.66" + process $proc$ls180.v:2757$3949 assign { } { } assign $1\builder_multiregimpl0_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl0_regs0 $1\builder_multiregimpl0_regs0[0:0] end - attribute \src "ls180.v:2745.32-2745.66" - process $proc$ls180.v:2745$3809 + attribute \src "ls180.v:2758.32-2758.66" + process $proc$ls180.v:2758$3950 assign { } { } assign $1\builder_multiregimpl0_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl0_regs1 $1\builder_multiregimpl0_regs1[0:0] end - attribute \src "ls180.v:2746.32-2746.66" - process $proc$ls180.v:2746$3810 + attribute \src "ls180.v:2759.32-2759.66" + process $proc$ls180.v:2759$3951 assign { } { } assign $1\builder_multiregimpl1_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl1_regs0 $1\builder_multiregimpl1_regs0[0:0] end - attribute \src "ls180.v:2747.32-2747.66" - process $proc$ls180.v:2747$3811 + attribute \src "ls180.v:276.12-276.41" + process $proc$ls180.v:276$3086 + assign { } { } + assign $1\main_converter1_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \main_converter1_dat_r $1\main_converter1_dat_r[63:0] + end + attribute \src "ls180.v:2760.32-2760.66" + process $proc$ls180.v:2760$3952 assign { } { } assign $1\builder_multiregimpl1_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl1_regs1 $1\builder_multiregimpl1_regs1[0:0] end - attribute \src "ls180.v:2748.32-2748.66" - process $proc$ls180.v:2748$3812 + attribute \src "ls180.v:2761.32-2761.66" + process $proc$ls180.v:2761$3953 assign { } { } assign $1\builder_multiregimpl2_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl2_regs0 $1\builder_multiregimpl2_regs0[0:0] end - attribute \src "ls180.v:2749.32-2749.66" - process $proc$ls180.v:2749$3813 + attribute \src "ls180.v:2762.32-2762.66" + process $proc$ls180.v:2762$3954 assign { } { } assign $1\builder_multiregimpl2_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl2_regs1 $1\builder_multiregimpl2_regs1[0:0] end - attribute \src "ls180.v:2750.32-2750.66" - process $proc$ls180.v:2750$3814 + attribute \src "ls180.v:2763.32-2763.66" + process $proc$ls180.v:2763$3955 assign { } { } assign $1\builder_multiregimpl3_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl3_regs0 $1\builder_multiregimpl3_regs0[0:0] end - attribute \src "ls180.v:2751.32-2751.66" - process $proc$ls180.v:2751$3815 + attribute \src "ls180.v:2764.32-2764.66" + process $proc$ls180.v:2764$3956 assign { } { } assign $1\builder_multiregimpl3_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl3_regs1 $1\builder_multiregimpl3_regs1[0:0] end - attribute \src "ls180.v:2752.32-2752.66" - process $proc$ls180.v:2752$3816 + attribute \src "ls180.v:2765.32-2765.66" + process $proc$ls180.v:2765$3957 assign { } { } assign $1\builder_multiregimpl4_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl4_regs0 $1\builder_multiregimpl4_regs0[0:0] end - attribute \src "ls180.v:2753.32-2753.66" - process $proc$ls180.v:2753$3817 + attribute \src "ls180.v:2766.32-2766.66" + process $proc$ls180.v:2766$3958 assign { } { } assign $1\builder_multiregimpl4_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl4_regs1 $1\builder_multiregimpl4_regs1[0:0] end - attribute \src "ls180.v:2754.32-2754.66" - process $proc$ls180.v:2754$3818 + attribute \src "ls180.v:2767.32-2767.66" + process $proc$ls180.v:2767$3959 assign { } { } assign $1\builder_multiregimpl5_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl5_regs0 $1\builder_multiregimpl5_regs0[0:0] end - attribute \src "ls180.v:2755.32-2755.66" - process $proc$ls180.v:2755$3819 + attribute \src "ls180.v:2768.32-2768.66" + process $proc$ls180.v:2768$3960 assign { } { } assign $1\builder_multiregimpl5_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl5_regs1 $1\builder_multiregimpl5_regs1[0:0] end - attribute \src "ls180.v:2756.32-2756.66" - process $proc$ls180.v:2756$3820 + attribute \src "ls180.v:2769.32-2769.66" + process $proc$ls180.v:2769$3961 assign { } { } assign $1\builder_multiregimpl6_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl6_regs0 $1\builder_multiregimpl6_regs0[0:0] end - attribute \src "ls180.v:2757.32-2757.66" - process $proc$ls180.v:2757$3821 + attribute \src "ls180.v:2770.32-2770.66" + process $proc$ls180.v:2770$3962 assign { } { } assign $1\builder_multiregimpl6_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl6_regs1 $1\builder_multiregimpl6_regs1[0:0] end - attribute \src "ls180.v:2758.32-2758.66" - process $proc$ls180.v:2758$3822 + attribute \src "ls180.v:2771.32-2771.66" + process $proc$ls180.v:2771$3963 assign { } { } assign $1\builder_multiregimpl7_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl7_regs0 $1\builder_multiregimpl7_regs0[0:0] end - attribute \src "ls180.v:2759.32-2759.66" - process $proc$ls180.v:2759$3823 + attribute \src "ls180.v:2772.32-2772.66" + process $proc$ls180.v:2772$3964 assign { } { } assign $1\builder_multiregimpl7_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl7_regs1 $1\builder_multiregimpl7_regs1[0:0] end - attribute \src "ls180.v:2760.32-2760.66" - process $proc$ls180.v:2760$3824 + attribute \src "ls180.v:2773.32-2773.66" + process $proc$ls180.v:2773$3965 assign { } { } assign $1\builder_multiregimpl8_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl8_regs0 $1\builder_multiregimpl8_regs0[0:0] end - attribute \src "ls180.v:2761.32-2761.66" - process $proc$ls180.v:2761$3825 + attribute \src "ls180.v:2774.32-2774.66" + process $proc$ls180.v:2774$3966 assign { } { } assign $1\builder_multiregimpl8_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl8_regs1 $1\builder_multiregimpl8_regs1[0:0] end - attribute \src "ls180.v:2762.32-2762.66" - process $proc$ls180.v:2762$3826 + attribute \src "ls180.v:2775.32-2775.66" + process $proc$ls180.v:2775$3967 assign { } { } assign $1\builder_multiregimpl9_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl9_regs0 $1\builder_multiregimpl9_regs0[0:0] end - attribute \src "ls180.v:2763.32-2763.66" - process $proc$ls180.v:2763$3827 + attribute \src "ls180.v:2776.32-2776.66" + process $proc$ls180.v:2776$3968 assign { } { } assign $1\builder_multiregimpl9_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl9_regs1 $1\builder_multiregimpl9_regs1[0:0] end - attribute \src "ls180.v:2764.32-2764.67" - process $proc$ls180.v:2764$3828 + attribute \src "ls180.v:2777.32-2777.67" + process $proc$ls180.v:2777$3969 assign { } { } assign $1\builder_multiregimpl10_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl10_regs0 $1\builder_multiregimpl10_regs0[0:0] end - attribute \src "ls180.v:2765.32-2765.67" - process $proc$ls180.v:2765$3829 + attribute \src "ls180.v:2778.32-2778.67" + process $proc$ls180.v:2778$3970 assign { } { } assign $1\builder_multiregimpl10_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl10_regs1 $1\builder_multiregimpl10_regs1[0:0] end - attribute \src "ls180.v:2766.32-2766.67" - process $proc$ls180.v:2766$3830 + attribute \src "ls180.v:2779.32-2779.67" + process $proc$ls180.v:2779$3971 assign { } { } assign $1\builder_multiregimpl11_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl11_regs0 $1\builder_multiregimpl11_regs0[0:0] end - attribute \src "ls180.v:2767.32-2767.67" - process $proc$ls180.v:2767$3831 + attribute \src "ls180.v:2780.32-2780.67" + process $proc$ls180.v:2780$3972 assign { } { } assign $1\builder_multiregimpl11_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl11_regs1 $1\builder_multiregimpl11_regs1[0:0] end - attribute \src "ls180.v:2768.32-2768.67" - process $proc$ls180.v:2768$3832 + attribute \src "ls180.v:2781.32-2781.67" + process $proc$ls180.v:2781$3973 assign { } { } assign $1\builder_multiregimpl12_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl12_regs0 $1\builder_multiregimpl12_regs0[0:0] end - attribute \src "ls180.v:2769.32-2769.67" - process $proc$ls180.v:2769$3833 + attribute \src "ls180.v:2782.32-2782.67" + process $proc$ls180.v:2782$3974 assign { } { } assign $1\builder_multiregimpl12_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl12_regs1 $1\builder_multiregimpl12_regs1[0:0] end - attribute \src "ls180.v:2770.32-2770.67" - process $proc$ls180.v:2770$3834 + attribute \src "ls180.v:2783.32-2783.67" + process $proc$ls180.v:2783$3975 assign { } { } assign $1\builder_multiregimpl13_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl13_regs0 $1\builder_multiregimpl13_regs0[0:0] end - attribute \src "ls180.v:2771.32-2771.67" - process $proc$ls180.v:2771$3835 + attribute \src "ls180.v:2784.32-2784.67" + process $proc$ls180.v:2784$3976 assign { } { } assign $1\builder_multiregimpl13_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl13_regs1 $1\builder_multiregimpl13_regs1[0:0] end - attribute \src "ls180.v:2772.32-2772.67" - process $proc$ls180.v:2772$3836 + attribute \src "ls180.v:2785.32-2785.67" + process $proc$ls180.v:2785$3977 assign { } { } assign $1\builder_multiregimpl14_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl14_regs0 $1\builder_multiregimpl14_regs0[0:0] end - attribute \src "ls180.v:2773.32-2773.67" - process $proc$ls180.v:2773$3837 + attribute \src "ls180.v:2786.32-2786.67" + process $proc$ls180.v:2786$3978 assign { } { } assign $1\builder_multiregimpl14_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl14_regs1 $1\builder_multiregimpl14_regs1[0:0] end - attribute \src "ls180.v:2774.32-2774.67" - process $proc$ls180.v:2774$3838 + attribute \src "ls180.v:2787.32-2787.67" + process $proc$ls180.v:2787$3979 assign { } { } assign $1\builder_multiregimpl15_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl15_regs0 $1\builder_multiregimpl15_regs0[0:0] end - attribute \src "ls180.v:2775.32-2775.67" - process $proc$ls180.v:2775$3839 + attribute \src "ls180.v:2788.32-2788.67" + process $proc$ls180.v:2788$3980 assign { } { } assign $1\builder_multiregimpl15_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl15_regs1 $1\builder_multiregimpl15_regs1[0:0] end - attribute \src "ls180.v:2776.32-2776.67" - process $proc$ls180.v:2776$3840 + attribute \src "ls180.v:2789.32-2789.67" + process $proc$ls180.v:2789$3981 assign { } { } assign $1\builder_multiregimpl16_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl16_regs0 $1\builder_multiregimpl16_regs0[0:0] end - attribute \src "ls180.v:2777.32-2777.67" - process $proc$ls180.v:2777$3841 + attribute \src "ls180.v:2790.32-2790.67" + process $proc$ls180.v:2790$3982 assign { } { } assign $1\builder_multiregimpl16_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl16_regs1 $1\builder_multiregimpl16_regs1[0:0] end - attribute \src "ls180.v:281.5-281.39" - process $proc$ls180.v:281$2964 + attribute \src "ls180.v:280.5-280.24" + process $proc$ls180.v:280$3087 assign { } { } - assign $1\main_interface2_ram_bus_ack[0:0] 1'0 + assign $1\main_int_rst[0:0] 1'1 sync always sync init - update \main_interface2_ram_bus_ack $1\main_interface2_ram_bus_ack[0:0] + update \main_int_rst $1\main_int_rst[0:0] end - attribute \src "ls180.v:2812.1-2817.4" - process $proc$ls180.v:2812$25 + attribute \src "ls180.v:2825.1-2830.4" + process $proc$ls180.v:2825$41 assign { } { } assign $0\main_libresocsim_libresoc_interrupt[15:0] [11:2] 10'0000000000 assign $0\main_libresocsim_libresoc_interrupt[15:0] [15:12] { 1'0 \eint } @@ -269742,25 +271066,25 @@ module \ls180 sync always update \main_libresocsim_libresoc_interrupt $0\main_libresocsim_libresoc_interrupt[15:0] end - attribute \src "ls180.v:2819.1-2829.4" - process $proc$ls180.v:2819$27 + attribute \src "ls180.v:2832.1-2842.4" + process $proc$ls180.v:2832$43 assign { } { } - assign $0\main_libresocsim_interface0_converted_interface_dat_w[31:0] 0 - attribute \src "ls180.v:2821.2-2828.9" - switch \main_libresocsim_converter0_counter + assign $0\main_libresocsim_libresoc_xics_icp_dat_w[31:0] 0 + attribute \src "ls180.v:2834.2-2841.9" + switch \main_converter0_counter attribute \src "ls180.v:0.0-0.0" case 1'0 - assign $0\main_libresocsim_interface0_converted_interface_dat_w[31:0] \main_libresocsim_libresoc_ibus_dat_w [31:0] + assign $0\main_libresocsim_libresoc_xics_icp_dat_w[31:0] \main_interface0_converted_interface_dat_w [31:0] attribute \src "ls180.v:0.0-0.0" case 1'1 - assign $0\main_libresocsim_interface0_converted_interface_dat_w[31:0] \main_libresocsim_libresoc_ibus_dat_w [63:32] + assign $0\main_libresocsim_libresoc_xics_icp_dat_w[31:0] \main_interface0_converted_interface_dat_w [63:32] case end sync always - update \main_libresocsim_interface0_converted_interface_dat_w $0\main_libresocsim_interface0_converted_interface_dat_w[31:0] + update \main_libresocsim_libresoc_xics_icp_dat_w $0\main_libresocsim_libresoc_xics_icp_dat_w[31:0] end - attribute \src "ls180.v:2831.1-2877.4" - process $proc$ls180.v:2831$28 + attribute \src "ls180.v:2844.1-2890.4" + process $proc$ls180.v:2844$44 assign { } { } assign { } { } assign { } { } @@ -269771,51 +271095,51 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\main_converter0_counter_converter0_next_value[0:0] 1'0 + assign $0\main_converter0_counter_converter0_next_value_ce[0:0] 1'0 + assign $0\main_interface0_converted_interface_ack[0:0] 1'0 + assign $0\main_libresocsim_libresoc_xics_icp_adr[29:0] 30'000000000000000000000000000000 + assign $0\main_libresocsim_libresoc_xics_icp_sel[3:0] 4'0000 + assign $0\main_converter0_skip[0:0] 1'0 + assign $0\main_libresocsim_libresoc_xics_icp_cyc[0:0] 1'0 + assign $0\main_libresocsim_libresoc_xics_icp_stb[0:0] 1'0 + assign $0\main_libresocsim_libresoc_xics_icp_we[0:0] 1'0 assign { } { } - assign $0\main_libresocsim_interface0_converted_interface_we[0:0] 1'0 - assign $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] 1'0 - assign $0\main_libresocsim_libresoc_ibus_ack[0:0] 1'0 - assign $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] 1'0 - assign $0\main_libresocsim_converter0_skip[0:0] 1'0 - assign $0\main_libresocsim_interface0_converted_interface_adr[29:0] 30'000000000000000000000000000000 - assign $0\main_libresocsim_interface0_converted_interface_sel[3:0] 4'0000 - assign $0\main_libresocsim_interface0_converted_interface_cyc[0:0] 1'0 - assign $0\main_libresocsim_interface0_converted_interface_stb[0:0] 1'0 assign $0\builder_converter0_next_state[0:0] \builder_converter0_state - attribute \src "ls180.v:2843.2-2876.9" + attribute \src "ls180.v:2856.2-2889.9" switch \builder_converter0_state attribute \src "ls180.v:0.0-0.0" case 1'1 - assign $0\main_libresocsim_interface0_converted_interface_adr[29:0] { \main_libresocsim_libresoc_ibus_adr \main_libresocsim_converter0_counter } - attribute \src "ls180.v:2846.4-2853.11" - switch \main_libresocsim_converter0_counter + assign $0\main_libresocsim_libresoc_xics_icp_adr[29:0] { \main_interface0_converted_interface_adr [28:0] \main_converter0_counter } + attribute \src "ls180.v:2859.4-2866.11" + switch \main_converter0_counter attribute \src "ls180.v:0.0-0.0" case 1'0 - assign $0\main_libresocsim_interface0_converted_interface_sel[3:0] \main_libresocsim_libresoc_ibus_sel [3:0] + assign $0\main_libresocsim_libresoc_xics_icp_sel[3:0] \main_interface0_converted_interface_sel [3:0] attribute \src "ls180.v:0.0-0.0" case 1'1 - assign $0\main_libresocsim_interface0_converted_interface_sel[3:0] \main_libresocsim_libresoc_ibus_sel [7:4] + assign $0\main_libresocsim_libresoc_xics_icp_sel[3:0] \main_interface0_converted_interface_sel [7:4] case end - attribute \src "ls180.v:2854.4-2867.7" - switch $and$ls180.v:2854$29_Y - attribute \src "ls180.v:2854.8-2854.81" + attribute \src "ls180.v:2867.4-2880.7" + switch $and$ls180.v:2867$45_Y + attribute \src "ls180.v:2867.8-2867.91" case 1'1 - assign $0\main_libresocsim_converter0_skip[0:0] $eq$ls180.v:2855$30_Y - assign $0\main_libresocsim_interface0_converted_interface_we[0:0] \main_libresocsim_libresoc_ibus_we - assign $0\main_libresocsim_interface0_converted_interface_cyc[0:0] $not$ls180.v:2857$31_Y - assign $0\main_libresocsim_interface0_converted_interface_stb[0:0] $not$ls180.v:2858$32_Y - attribute \src "ls180.v:2859.5-2866.8" - switch $or$ls180.v:2859$33_Y - attribute \src "ls180.v:2859.9-2859.97" + assign $0\main_converter0_skip[0:0] $eq$ls180.v:2868$46_Y + assign $0\main_libresocsim_libresoc_xics_icp_we[0:0] \main_interface0_converted_interface_we + assign $0\main_libresocsim_libresoc_xics_icp_cyc[0:0] $not$ls180.v:2870$47_Y + assign $0\main_libresocsim_libresoc_xics_icp_stb[0:0] $not$ls180.v:2871$48_Y + attribute \src "ls180.v:2872.5-2879.8" + switch $or$ls180.v:2872$49_Y + attribute \src "ls180.v:2872.9-2872.72" case 1'1 - assign $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] $add$ls180.v:2860$34_Y - assign $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:2862.6-2865.9" - switch $eq$ls180.v:2862$35_Y - attribute \src "ls180.v:2862.10-2862.55" + assign $0\main_converter0_counter_converter0_next_value[0:0] $add$ls180.v:2873$50_Y + assign $0\main_converter0_counter_converter0_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:2875.6-2878.9" + switch $eq$ls180.v:2875$51_Y + attribute \src "ls180.v:2875.10-2875.43" case 1'1 - assign $0\main_libresocsim_libresoc_ibus_ack[0:0] 1'1 + assign $0\main_interface0_converted_interface_ack[0:0] 1'1 assign $0\builder_converter0_next_state[0:0] 1'0 case end @@ -269825,63 +271149,47 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case - assign $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] 1'0 - assign $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:2872.4-2874.7" - switch $and$ls180.v:2872$36_Y - attribute \src "ls180.v:2872.8-2872.81" + assign $0\main_converter0_counter_converter0_next_value[0:0] 1'0 + assign $0\main_converter0_counter_converter0_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:2885.4-2887.7" + switch $and$ls180.v:2885$52_Y + attribute \src "ls180.v:2885.8-2885.91" case 1'1 assign $0\builder_converter0_next_state[0:0] 1'1 case end end sync always - update \main_libresocsim_libresoc_ibus_ack $0\main_libresocsim_libresoc_ibus_ack[0:0] - update \main_libresocsim_interface0_converted_interface_adr $0\main_libresocsim_interface0_converted_interface_adr[29:0] - update \main_libresocsim_interface0_converted_interface_sel $0\main_libresocsim_interface0_converted_interface_sel[3:0] - update \main_libresocsim_interface0_converted_interface_cyc $0\main_libresocsim_interface0_converted_interface_cyc[0:0] - update \main_libresocsim_interface0_converted_interface_stb $0\main_libresocsim_interface0_converted_interface_stb[0:0] - update \main_libresocsim_interface0_converted_interface_we $0\main_libresocsim_interface0_converted_interface_we[0:0] - update \main_libresocsim_converter0_skip $0\main_libresocsim_converter0_skip[0:0] + update \main_libresocsim_libresoc_xics_icp_adr $0\main_libresocsim_libresoc_xics_icp_adr[29:0] + update \main_libresocsim_libresoc_xics_icp_sel $0\main_libresocsim_libresoc_xics_icp_sel[3:0] + update \main_libresocsim_libresoc_xics_icp_cyc $0\main_libresocsim_libresoc_xics_icp_cyc[0:0] + update \main_libresocsim_libresoc_xics_icp_stb $0\main_libresocsim_libresoc_xics_icp_stb[0:0] + update \main_libresocsim_libresoc_xics_icp_we $0\main_libresocsim_libresoc_xics_icp_we[0:0] + update \main_interface0_converted_interface_ack $0\main_interface0_converted_interface_ack[0:0] + update \main_converter0_skip $0\main_converter0_skip[0:0] update \builder_converter0_next_state $0\builder_converter0_next_state[0:0] - update \main_libresocsim_converter0_counter_converter0_next_value $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] - update \main_libresocsim_converter0_counter_converter0_next_value_ce $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] - end - attribute \src "ls180.v:285.5-285.39" - process $proc$ls180.v:285$2965 - assign { } { } - assign $0\main_interface2_ram_bus_err[0:0] 1'0 - sync always - update \main_interface2_ram_bus_err $0\main_interface2_ram_bus_err[0:0] - sync init + update \main_converter0_counter_converter0_next_value $0\main_converter0_counter_converter0_next_value[0:0] + update \main_converter0_counter_converter0_next_value_ce $0\main_converter0_counter_converter0_next_value_ce[0:0] end - attribute \src "ls180.v:2879.1-2889.4" - process $proc$ls180.v:2879$38 + attribute \src "ls180.v:2892.1-2902.4" + process $proc$ls180.v:2892$54 assign { } { } - assign $0\main_libresocsim_interface1_converted_interface_dat_w[31:0] 0 - attribute \src "ls180.v:2881.2-2888.9" - switch \main_libresocsim_converter1_counter + assign $0\main_libresocsim_libresoc_xics_ics_dat_w[31:0] 0 + attribute \src "ls180.v:2894.2-2901.9" + switch \main_converter1_counter attribute \src "ls180.v:0.0-0.0" case 1'0 - assign $0\main_libresocsim_interface1_converted_interface_dat_w[31:0] \main_libresocsim_libresoc_dbus_dat_w [31:0] + assign $0\main_libresocsim_libresoc_xics_ics_dat_w[31:0] \main_interface1_converted_interface_dat_w [31:0] attribute \src "ls180.v:0.0-0.0" case 1'1 - assign $0\main_libresocsim_interface1_converted_interface_dat_w[31:0] \main_libresocsim_libresoc_dbus_dat_w [63:32] + assign $0\main_libresocsim_libresoc_xics_ics_dat_w[31:0] \main_interface1_converted_interface_dat_w [63:32] case end sync always - update \main_libresocsim_interface1_converted_interface_dat_w $0\main_libresocsim_interface1_converted_interface_dat_w[31:0] - end - attribute \src "ls180.v:288.11-288.31" - process $proc$ls180.v:288$2966 - assign { } { } - assign $1\main_sram2_we[3:0] 4'0000 - sync always - sync init - update \main_sram2_we $1\main_sram2_we[3:0] + update \main_libresocsim_libresoc_xics_ics_dat_w $0\main_libresocsim_libresoc_xics_ics_dat_w[31:0] end - attribute \src "ls180.v:2891.1-2937.4" - process $proc$ls180.v:2891$39 + attribute \src "ls180.v:2904.1-2950.4" + process $proc$ls180.v:2904$55 assign { } { } assign { } { } assign { } { } @@ -269892,51 +271200,51 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_libresocsim_converter1_skip[0:0] 1'0 - assign $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] 1'0 - assign $0\main_libresocsim_interface1_converted_interface_adr[29:0] 30'000000000000000000000000000000 - assign $0\main_libresocsim_libresoc_dbus_ack[0:0] 1'0 - assign $0\main_libresocsim_interface1_converted_interface_sel[3:0] 4'0000 - assign $0\main_libresocsim_interface1_converted_interface_cyc[0:0] 1'0 - assign $0\main_libresocsim_interface1_converted_interface_stb[0:0] 1'0 - assign $0\main_libresocsim_interface1_converted_interface_we[0:0] 1'0 + assign $0\main_interface1_converted_interface_ack[0:0] 1'0 + assign $0\main_libresocsim_libresoc_xics_ics_adr[29:0] 30'000000000000000000000000000000 + assign $0\main_libresocsim_libresoc_xics_ics_sel[3:0] 4'0000 + assign $0\main_libresocsim_libresoc_xics_ics_cyc[0:0] 1'0 + assign $0\main_converter1_skip[0:0] 1'0 + assign $0\main_libresocsim_libresoc_xics_ics_stb[0:0] 1'0 + assign $0\main_libresocsim_libresoc_xics_ics_we[0:0] 1'0 assign { } { } - assign $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] 1'0 + assign $0\main_converter1_counter_converter1_next_value[0:0] 1'0 + assign $0\main_converter1_counter_converter1_next_value_ce[0:0] 1'0 assign $0\builder_converter1_next_state[0:0] \builder_converter1_state - attribute \src "ls180.v:2903.2-2936.9" + attribute \src "ls180.v:2916.2-2949.9" switch \builder_converter1_state attribute \src "ls180.v:0.0-0.0" case 1'1 - assign $0\main_libresocsim_interface1_converted_interface_adr[29:0] { \main_libresocsim_libresoc_dbus_adr \main_libresocsim_converter1_counter } - attribute \src "ls180.v:2906.4-2913.11" - switch \main_libresocsim_converter1_counter + assign $0\main_libresocsim_libresoc_xics_ics_adr[29:0] { \main_interface1_converted_interface_adr [28:0] \main_converter1_counter } + attribute \src "ls180.v:2919.4-2926.11" + switch \main_converter1_counter attribute \src "ls180.v:0.0-0.0" case 1'0 - assign $0\main_libresocsim_interface1_converted_interface_sel[3:0] \main_libresocsim_libresoc_dbus_sel [3:0] + assign $0\main_libresocsim_libresoc_xics_ics_sel[3:0] \main_interface1_converted_interface_sel [3:0] attribute \src "ls180.v:0.0-0.0" case 1'1 - assign $0\main_libresocsim_interface1_converted_interface_sel[3:0] \main_libresocsim_libresoc_dbus_sel [7:4] + assign $0\main_libresocsim_libresoc_xics_ics_sel[3:0] \main_interface1_converted_interface_sel [7:4] case end - attribute \src "ls180.v:2914.4-2927.7" - switch $and$ls180.v:2914$40_Y - attribute \src "ls180.v:2914.8-2914.81" + attribute \src "ls180.v:2927.4-2940.7" + switch $and$ls180.v:2927$56_Y + attribute \src "ls180.v:2927.8-2927.91" case 1'1 - assign $0\main_libresocsim_converter1_skip[0:0] $eq$ls180.v:2915$41_Y - assign $0\main_libresocsim_interface1_converted_interface_we[0:0] \main_libresocsim_libresoc_dbus_we - assign $0\main_libresocsim_interface1_converted_interface_cyc[0:0] $not$ls180.v:2917$42_Y - assign $0\main_libresocsim_interface1_converted_interface_stb[0:0] $not$ls180.v:2918$43_Y - attribute \src "ls180.v:2919.5-2926.8" - switch $or$ls180.v:2919$44_Y - attribute \src "ls180.v:2919.9-2919.97" + assign $0\main_converter1_skip[0:0] $eq$ls180.v:2928$57_Y + assign $0\main_libresocsim_libresoc_xics_ics_we[0:0] \main_interface1_converted_interface_we + assign $0\main_libresocsim_libresoc_xics_ics_cyc[0:0] $not$ls180.v:2930$58_Y + assign $0\main_libresocsim_libresoc_xics_ics_stb[0:0] $not$ls180.v:2931$59_Y + attribute \src "ls180.v:2932.5-2939.8" + switch $or$ls180.v:2932$60_Y + attribute \src "ls180.v:2932.9-2932.72" case 1'1 - assign $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] $add$ls180.v:2920$45_Y - assign $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:2922.6-2925.9" - switch $eq$ls180.v:2922$46_Y - attribute \src "ls180.v:2922.10-2922.55" + assign $0\main_converter1_counter_converter1_next_value[0:0] $add$ls180.v:2933$61_Y + assign $0\main_converter1_counter_converter1_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:2935.6-2938.9" + switch $eq$ls180.v:2935$62_Y + attribute \src "ls180.v:2935.10-2935.43" case 1'1 - assign $0\main_libresocsim_libresoc_dbus_ack[0:0] 1'1 + assign $0\main_interface1_converted_interface_ack[0:0] 1'1 assign $0\builder_converter1_next_state[0:0] 1'0 case end @@ -269946,55 +271254,63 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case - assign $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] 1'0 - assign $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:2932.4-2934.7" - switch $and$ls180.v:2932$47_Y - attribute \src "ls180.v:2932.8-2932.81" + assign $0\main_converter1_counter_converter1_next_value[0:0] 1'0 + assign $0\main_converter1_counter_converter1_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:2945.4-2947.7" + switch $and$ls180.v:2945$63_Y + attribute \src "ls180.v:2945.8-2945.91" case 1'1 assign $0\builder_converter1_next_state[0:0] 1'1 case end end sync always - update \main_libresocsim_libresoc_dbus_ack $0\main_libresocsim_libresoc_dbus_ack[0:0] - update \main_libresocsim_interface1_converted_interface_adr $0\main_libresocsim_interface1_converted_interface_adr[29:0] - update \main_libresocsim_interface1_converted_interface_sel $0\main_libresocsim_interface1_converted_interface_sel[3:0] - update \main_libresocsim_interface1_converted_interface_cyc $0\main_libresocsim_interface1_converted_interface_cyc[0:0] - update \main_libresocsim_interface1_converted_interface_stb $0\main_libresocsim_interface1_converted_interface_stb[0:0] - update \main_libresocsim_interface1_converted_interface_we $0\main_libresocsim_interface1_converted_interface_we[0:0] - update \main_libresocsim_converter1_skip $0\main_libresocsim_converter1_skip[0:0] + update \main_libresocsim_libresoc_xics_ics_adr $0\main_libresocsim_libresoc_xics_ics_adr[29:0] + update \main_libresocsim_libresoc_xics_ics_sel $0\main_libresocsim_libresoc_xics_ics_sel[3:0] + update \main_libresocsim_libresoc_xics_ics_cyc $0\main_libresocsim_libresoc_xics_ics_cyc[0:0] + update \main_libresocsim_libresoc_xics_ics_stb $0\main_libresocsim_libresoc_xics_ics_stb[0:0] + update \main_libresocsim_libresoc_xics_ics_we $0\main_libresocsim_libresoc_xics_ics_we[0:0] + update \main_interface1_converted_interface_ack $0\main_interface1_converted_interface_ack[0:0] + update \main_converter1_skip $0\main_converter1_skip[0:0] update \builder_converter1_next_state $0\builder_converter1_next_state[0:0] - update \main_libresocsim_converter1_counter_converter1_next_value $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] - update \main_libresocsim_converter1_counter_converter1_next_value_ce $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] + update \main_converter1_counter_converter1_next_value $0\main_converter1_counter_converter1_next_value[0:0] + update \main_converter1_counter_converter1_next_value_ce $0\main_converter1_counter_converter1_next_value_ce[0:0] end - attribute \src "ls180.v:293.5-293.24" - process $proc$ls180.v:293$2967 + attribute \src "ls180.v:295.12-295.38" + process $proc$ls180.v:295$3088 assign { } { } - assign $1\main_int_rst[0:0] 1'1 + assign $1\main_dfi_p0_rddata[15:0] 16'0000000000000000 sync always sync init - update \main_int_rst $1\main_int_rst[0:0] + update \main_dfi_p0_rddata $1\main_dfi_p0_rddata[15:0] end - attribute \src "ls180.v:2939.1-2949.4" - process $proc$ls180.v:2939$49 + attribute \src "ls180.v:2952.1-2962.4" + process $proc$ls180.v:2952$65 assign { } { } - assign $0\main_libresocsim_interface2_converted_interface_dat_w[31:0] 0 - attribute \src "ls180.v:2941.2-2948.9" - switch \main_libresocsim_converter2_counter + assign $0\main_wb_sdram_dat_w[31:0] 0 + attribute \src "ls180.v:2954.2-2961.9" + switch \main_socbushandler_counter attribute \src "ls180.v:0.0-0.0" case 1'0 - assign $0\main_libresocsim_interface2_converted_interface_dat_w[31:0] \main_libresocsim_libresoc_jtag_wb_dat_w [31:0] + assign $0\main_wb_sdram_dat_w[31:0] \main_socbushandler_converted_interface_dat_w [31:0] attribute \src "ls180.v:0.0-0.0" case 1'1 - assign $0\main_libresocsim_interface2_converted_interface_dat_w[31:0] \main_libresocsim_libresoc_jtag_wb_dat_w [63:32] + assign $0\main_wb_sdram_dat_w[31:0] \main_socbushandler_converted_interface_dat_w [63:32] case end sync always - update \main_libresocsim_interface2_converted_interface_dat_w $0\main_libresocsim_interface2_converted_interface_dat_w[31:0] + update \main_wb_sdram_dat_w $0\main_wb_sdram_dat_w[31:0] + end + attribute \src "ls180.v:296.5-296.36" + process $proc$ls180.v:296$3089 + assign { } { } + assign $1\main_dfi_p0_rddata_valid[0:0] 1'0 + sync always + sync init + update \main_dfi_p0_rddata_valid $1\main_dfi_p0_rddata_valid[0:0] end - attribute \src "ls180.v:2951.1-2997.4" - process $proc$ls180.v:2951$50 + attribute \src "ls180.v:2964.1-3010.4" + process $proc$ls180.v:2964$66 assign { } { } assign { } { } assign { } { } @@ -270005,51 +271321,51 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_libresocsim_interface2_converted_interface_adr[29:0] 30'000000000000000000000000000000 - assign $0\main_libresocsim_libresoc_jtag_wb_ack[0:0] 1'0 - assign $0\main_libresocsim_interface2_converted_interface_sel[3:0] 4'0000 - assign $0\main_libresocsim_interface2_converted_interface_cyc[0:0] 1'0 - assign $0\main_libresocsim_interface2_converted_interface_stb[0:0] 1'0 - assign $0\main_libresocsim_interface2_converted_interface_we[0:0] 1'0 - assign $0\main_libresocsim_converter2_skip[0:0] 1'0 + assign $0\main_wb_sdram_adr[29:0] 30'000000000000000000000000000000 + assign $0\main_socbushandler_converted_interface_ack[0:0] 1'0 + assign $0\main_wb_sdram_sel[3:0] 4'0000 + assign $0\main_wb_sdram_cyc[0:0] 1'0 + assign $0\main_wb_sdram_stb[0:0] 1'0 + assign $0\main_socbushandler_skip[0:0] 1'0 assign { } { } - assign $0\main_libresocsim_converter2_counter_converter2_next_value[0:0] 1'0 - assign $0\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] 1'0 + assign $0\main_wb_sdram_we[0:0] 1'0 + assign $0\main_socbushandler_counter_converter2_next_value[0:0] 1'0 + assign $0\main_socbushandler_counter_converter2_next_value_ce[0:0] 1'0 assign $0\builder_converter2_next_state[0:0] \builder_converter2_state - attribute \src "ls180.v:2963.2-2996.9" + attribute \src "ls180.v:2976.2-3009.9" switch \builder_converter2_state attribute \src "ls180.v:0.0-0.0" case 1'1 - assign $0\main_libresocsim_interface2_converted_interface_adr[29:0] { \main_libresocsim_libresoc_jtag_wb_adr \main_libresocsim_converter2_counter } - attribute \src "ls180.v:2966.4-2973.11" - switch \main_libresocsim_converter2_counter + assign $0\main_wb_sdram_adr[29:0] { \main_socbushandler_converted_interface_adr [28:0] \main_socbushandler_counter } + attribute \src "ls180.v:2979.4-2986.11" + switch \main_socbushandler_counter attribute \src "ls180.v:0.0-0.0" case 1'0 - assign $0\main_libresocsim_interface2_converted_interface_sel[3:0] \main_libresocsim_libresoc_jtag_wb_sel [3:0] + assign $0\main_wb_sdram_sel[3:0] \main_socbushandler_converted_interface_sel [3:0] attribute \src "ls180.v:0.0-0.0" case 1'1 - assign $0\main_libresocsim_interface2_converted_interface_sel[3:0] \main_libresocsim_libresoc_jtag_wb_sel [7:4] + assign $0\main_wb_sdram_sel[3:0] \main_socbushandler_converted_interface_sel [7:4] case end - attribute \src "ls180.v:2974.4-2987.7" - switch $and$ls180.v:2974$51_Y - attribute \src "ls180.v:2974.8-2974.87" + attribute \src "ls180.v:2987.4-3000.7" + switch $and$ls180.v:2987$67_Y + attribute \src "ls180.v:2987.8-2987.97" case 1'1 - assign $0\main_libresocsim_converter2_skip[0:0] $eq$ls180.v:2975$52_Y - assign $0\main_libresocsim_interface2_converted_interface_we[0:0] \main_libresocsim_libresoc_jtag_wb_we - assign $0\main_libresocsim_interface2_converted_interface_cyc[0:0] $not$ls180.v:2977$53_Y - assign $0\main_libresocsim_interface2_converted_interface_stb[0:0] $not$ls180.v:2978$54_Y - attribute \src "ls180.v:2979.5-2986.8" - switch $or$ls180.v:2979$55_Y - attribute \src "ls180.v:2979.9-2979.97" + assign $0\main_socbushandler_skip[0:0] $eq$ls180.v:2988$68_Y + assign $0\main_wb_sdram_we[0:0] \main_socbushandler_converted_interface_we + assign $0\main_wb_sdram_cyc[0:0] $not$ls180.v:2990$69_Y + assign $0\main_wb_sdram_stb[0:0] $not$ls180.v:2991$70_Y + attribute \src "ls180.v:2992.5-2999.8" + switch $or$ls180.v:2992$71_Y + attribute \src "ls180.v:2992.9-2992.54" case 1'1 - assign $0\main_libresocsim_converter2_counter_converter2_next_value[0:0] $add$ls180.v:2980$56_Y - assign $0\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:2982.6-2985.9" - switch $eq$ls180.v:2982$57_Y - attribute \src "ls180.v:2982.10-2982.55" + assign $0\main_socbushandler_counter_converter2_next_value[0:0] $add$ls180.v:2993$72_Y + assign $0\main_socbushandler_counter_converter2_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:2995.6-2998.9" + switch $eq$ls180.v:2995$73_Y + attribute \src "ls180.v:2995.10-2995.46" case 1'1 - assign $0\main_libresocsim_libresoc_jtag_wb_ack[0:0] 1'1 + assign $0\main_socbushandler_converted_interface_ack[0:0] 1'1 assign $0\builder_converter2_next_state[0:0] 1'0 case end @@ -270059,46 +271375,82 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case - assign $0\main_libresocsim_converter2_counter_converter2_next_value[0:0] 1'0 - assign $0\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:2992.4-2994.7" - switch $and$ls180.v:2992$58_Y - attribute \src "ls180.v:2992.8-2992.87" + assign $0\main_socbushandler_counter_converter2_next_value[0:0] 1'0 + assign $0\main_socbushandler_counter_converter2_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:3005.4-3007.7" + switch $and$ls180.v:3005$74_Y + attribute \src "ls180.v:3005.8-3005.97" case 1'1 assign $0\builder_converter2_next_state[0:0] 1'1 case end end sync always - update \main_libresocsim_libresoc_jtag_wb_ack $0\main_libresocsim_libresoc_jtag_wb_ack[0:0] - update \main_libresocsim_interface2_converted_interface_adr $0\main_libresocsim_interface2_converted_interface_adr[29:0] - update \main_libresocsim_interface2_converted_interface_sel $0\main_libresocsim_interface2_converted_interface_sel[3:0] - update \main_libresocsim_interface2_converted_interface_cyc $0\main_libresocsim_interface2_converted_interface_cyc[0:0] - update \main_libresocsim_interface2_converted_interface_stb $0\main_libresocsim_interface2_converted_interface_stb[0:0] - update \main_libresocsim_interface2_converted_interface_we $0\main_libresocsim_interface2_converted_interface_we[0:0] - update \main_libresocsim_converter2_skip $0\main_libresocsim_converter2_skip[0:0] + update \main_wb_sdram_adr $0\main_wb_sdram_adr[29:0] + update \main_wb_sdram_sel $0\main_wb_sdram_sel[3:0] + update \main_wb_sdram_cyc $0\main_wb_sdram_cyc[0:0] + update \main_wb_sdram_stb $0\main_wb_sdram_stb[0:0] + update \main_wb_sdram_we $0\main_wb_sdram_we[0:0] + update \main_socbushandler_converted_interface_ack $0\main_socbushandler_converted_interface_ack[0:0] + update \main_socbushandler_skip $0\main_socbushandler_skip[0:0] update \builder_converter2_next_state $0\builder_converter2_next_state[0:0] - update \main_libresocsim_converter2_counter_converter2_next_value $0\main_libresocsim_converter2_counter_converter2_next_value[0:0] - update \main_libresocsim_converter2_counter_converter2_next_value_ce $0\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] + update \main_socbushandler_counter_converter2_next_value $0\main_socbushandler_counter_converter2_next_value[0:0] + update \main_socbushandler_counter_converter2_next_value_ce $0\main_socbushandler_counter_converter2_next_value_ce[0:0] + end + attribute \src "ls180.v:297.11-297.32" + process $proc$ls180.v:297$3090 + assign { } { } + assign $1\main_rddata_en[2:0] 3'000 + sync always + sync init + update \main_rddata_en $1\main_rddata_en[2:0] + end + attribute \src "ls180.v:300.5-300.36" + process $proc$ls180.v:300$3091 + assign { } { } + assign $1\main_sdram_inti_p0_cas_n[0:0] 1'1 + sync always + sync init + update \main_sdram_inti_p0_cas_n $1\main_sdram_inti_p0_cas_n[0:0] + end + attribute \src "ls180.v:301.5-301.35" + process $proc$ls180.v:301$3092 + assign { } { } + assign $1\main_sdram_inti_p0_cs_n[0:0] 1'1 + sync always + sync init + update \main_sdram_inti_p0_cs_n $1\main_sdram_inti_p0_cs_n[0:0] end - attribute \src "ls180.v:3000.1-3006.4" - process $proc$ls180.v:3000$59 + attribute \src "ls180.v:3013.1-3023.4" + process $proc$ls180.v:3013$75 + assign { } { } assign { } { } + assign $0\main_libresocsim_we[7:0] [0] $and$ls180.v:3015$78_Y + assign $0\main_libresocsim_we[7:0] [1] $and$ls180.v:3016$81_Y + assign $0\main_libresocsim_we[7:0] [2] $and$ls180.v:3017$84_Y + assign $0\main_libresocsim_we[7:0] [3] $and$ls180.v:3018$87_Y + assign $0\main_libresocsim_we[7:0] [4] $and$ls180.v:3019$90_Y + assign $0\main_libresocsim_we[7:0] [5] $and$ls180.v:3020$93_Y + assign $0\main_libresocsim_we[7:0] [6] $and$ls180.v:3021$96_Y + assign $0\main_libresocsim_we[7:0] [7] $and$ls180.v:3022$99_Y + sync always + update \main_libresocsim_we $0\main_libresocsim_we[7:0] + end + attribute \src "ls180.v:302.5-302.36" + process $proc$ls180.v:302$3093 assign { } { } - assign $0\main_libresocsim_we[3:0] [0] $and$ls180.v:3002$62_Y - assign $0\main_libresocsim_we[3:0] [1] $and$ls180.v:3003$65_Y - assign $0\main_libresocsim_we[3:0] [2] $and$ls180.v:3004$68_Y - assign $0\main_libresocsim_we[3:0] [3] $and$ls180.v:3005$71_Y + assign $1\main_sdram_inti_p0_ras_n[0:0] 1'1 sync always - update \main_libresocsim_we $0\main_libresocsim_we[3:0] + sync init + update \main_sdram_inti_p0_ras_n $1\main_sdram_inti_p0_ras_n[0:0] end - attribute \src "ls180.v:3012.1-3017.4" - process $proc$ls180.v:3012$73 + attribute \src "ls180.v:3029.1-3034.4" + process $proc$ls180.v:3029$101 assign { } { } assign $0\main_libresocsim_zero_clear[0:0] 1'0 - attribute \src "ls180.v:3014.2-3016.5" - switch $and$ls180.v:3014$74_Y - attribute \src "ls180.v:3014.6-3014.90" + attribute \src "ls180.v:3031.2-3033.5" + switch $and$ls180.v:3031$102_Y + attribute \src "ls180.v:3031.6-3031.90" case 1'1 assign $0\main_libresocsim_zero_clear[0:0] 1'1 case @@ -270106,49 +271458,69 @@ module \ls180 sync always update \main_libresocsim_zero_clear $0\main_libresocsim_zero_clear[0:0] end - attribute \src "ls180.v:3021.1-3027.4" - process $proc$ls180.v:3021$76 + attribute \src "ls180.v:303.5-303.35" + process $proc$ls180.v:303$3094 + assign { } { } + assign $1\main_sdram_inti_p0_we_n[0:0] 1'1 + sync always + sync init + update \main_sdram_inti_p0_we_n $1\main_sdram_inti_p0_we_n[0:0] + end + attribute \src "ls180.v:3038.1-3048.4" + process $proc$ls180.v:3038$104 assign { } { } assign { } { } - assign $0\main_sram0_we[3:0] [0] $and$ls180.v:3023$79_Y - assign $0\main_sram0_we[3:0] [1] $and$ls180.v:3024$82_Y - assign $0\main_sram0_we[3:0] [2] $and$ls180.v:3025$85_Y - assign $0\main_sram0_we[3:0] [3] $and$ls180.v:3026$88_Y + assign $0\main_sram0_we[7:0] [0] $and$ls180.v:3040$107_Y + assign $0\main_sram0_we[7:0] [1] $and$ls180.v:3041$110_Y + assign $0\main_sram0_we[7:0] [2] $and$ls180.v:3042$113_Y + assign $0\main_sram0_we[7:0] [3] $and$ls180.v:3043$116_Y + assign $0\main_sram0_we[7:0] [4] $and$ls180.v:3044$119_Y + assign $0\main_sram0_we[7:0] [5] $and$ls180.v:3045$122_Y + assign $0\main_sram0_we[7:0] [6] $and$ls180.v:3046$125_Y + assign $0\main_sram0_we[7:0] [7] $and$ls180.v:3047$128_Y sync always - update \main_sram0_we $0\main_sram0_we[3:0] + update \main_sram0_we $0\main_sram0_we[7:0] end - attribute \src "ls180.v:3031.1-3037.4" - process $proc$ls180.v:3031$89 + attribute \src "ls180.v:3052.1-3062.4" + process $proc$ls180.v:3052$129 assign { } { } assign { } { } - assign $0\main_sram1_we[3:0] [0] $and$ls180.v:3033$92_Y - assign $0\main_sram1_we[3:0] [1] $and$ls180.v:3034$95_Y - assign $0\main_sram1_we[3:0] [2] $and$ls180.v:3035$98_Y - assign $0\main_sram1_we[3:0] [3] $and$ls180.v:3036$101_Y + assign $0\main_sram1_we[7:0] [0] $and$ls180.v:3054$132_Y + assign $0\main_sram1_we[7:0] [1] $and$ls180.v:3055$135_Y + assign $0\main_sram1_we[7:0] [2] $and$ls180.v:3056$138_Y + assign $0\main_sram1_we[7:0] [3] $and$ls180.v:3057$141_Y + assign $0\main_sram1_we[7:0] [4] $and$ls180.v:3058$144_Y + assign $0\main_sram1_we[7:0] [5] $and$ls180.v:3059$147_Y + assign $0\main_sram1_we[7:0] [6] $and$ls180.v:3060$150_Y + assign $0\main_sram1_we[7:0] [7] $and$ls180.v:3061$153_Y sync always - update \main_sram1_we $0\main_sram1_we[3:0] + update \main_sram1_we $0\main_sram1_we[7:0] end - attribute \src "ls180.v:3041.1-3047.4" - process $proc$ls180.v:3041$102 + attribute \src "ls180.v:3066.1-3076.4" + process $proc$ls180.v:3066$154 assign { } { } assign { } { } - assign $0\main_sram2_we[3:0] [0] $and$ls180.v:3043$105_Y - assign $0\main_sram2_we[3:0] [1] $and$ls180.v:3044$108_Y - assign $0\main_sram2_we[3:0] [2] $and$ls180.v:3045$111_Y - assign $0\main_sram2_we[3:0] [3] $and$ls180.v:3046$114_Y + assign $0\main_sram2_we[7:0] [0] $and$ls180.v:3068$157_Y + assign $0\main_sram2_we[7:0] [1] $and$ls180.v:3069$160_Y + assign $0\main_sram2_we[7:0] [2] $and$ls180.v:3070$163_Y + assign $0\main_sram2_we[7:0] [3] $and$ls180.v:3071$166_Y + assign $0\main_sram2_we[7:0] [4] $and$ls180.v:3072$169_Y + assign $0\main_sram2_we[7:0] [5] $and$ls180.v:3073$172_Y + assign $0\main_sram2_we[7:0] [6] $and$ls180.v:3074$175_Y + assign $0\main_sram2_we[7:0] [7] $and$ls180.v:3075$178_Y sync always - update \main_sram2_we $0\main_sram2_we[3:0] + update \main_sram2_we $0\main_sram2_we[7:0] end - attribute \src "ls180.v:308.12-308.38" - process $proc$ls180.v:308$2968 + attribute \src "ls180.v:307.5-307.36" + process $proc$ls180.v:307$3095 assign { } { } - assign $1\main_dfi_p0_rddata[15:0] 16'0000000000000000 + assign $0\main_sdram_inti_p0_act_n[0:0] 1'1 sync always + update \main_sdram_inti_p0_act_n $0\main_sdram_inti_p0_act_n[0:0] sync init - update \main_dfi_p0_rddata $1\main_dfi_p0_rddata[15:0] end - attribute \src "ls180.v:3086.1-3140.4" - process $proc$ls180.v:3086$115 + attribute \src "ls180.v:3115.1-3169.4" + process $proc$ls180.v:3115$179 assign { } { } assign { } { } assign { } { } @@ -270167,13 +271539,6 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_sdram_slave_p0_rddata[15:0] 16'0000000000000000 - assign $0\main_sdram_slave_p0_rddata_valid[0:0] 1'0 - assign $0\main_sdram_master_p0_address[12:0] 13'0000000000000 - assign $0\main_sdram_master_p0_bank[1:0] 2'00 - assign $0\main_sdram_master_p0_cas_n[0:0] 1'1 - assign $0\main_sdram_master_p0_cs_n[0:0] 1'1 - assign $0\main_sdram_master_p0_ras_n[0:0] 1'1 assign $0\main_sdram_master_p0_we_n[0:0] 1'1 assign $0\main_sdram_master_p0_cke[0:0] 1'0 assign $0\main_sdram_master_p0_odt[0:0] 1'0 @@ -270185,9 +271550,16 @@ module \ls180 assign $0\main_sdram_master_p0_wrdata_en[0:0] 1'0 assign $0\main_sdram_master_p0_wrdata_mask[1:0] 2'00 assign $0\main_sdram_master_p0_rddata_en[0:0] 1'0 - attribute \src "ls180.v:3105.2-3139.5" + assign $0\main_sdram_slave_p0_rddata[15:0] 16'0000000000000000 + assign $0\main_sdram_slave_p0_rddata_valid[0:0] 1'0 + assign $0\main_sdram_master_p0_address[12:0] 13'0000000000000 + assign $0\main_sdram_master_p0_bank[1:0] 2'00 + assign $0\main_sdram_master_p0_cas_n[0:0] 1'1 + assign $0\main_sdram_master_p0_cs_n[0:0] 1'1 + assign $0\main_sdram_master_p0_ras_n[0:0] 1'1 + attribute \src "ls180.v:3134.2-3168.5" switch \main_sdram_sel - attribute \src "ls180.v:3105.6-3105.20" + attribute \src "ls180.v:3134.6-3134.20" case 1'1 assign $0\main_sdram_master_p0_address[12:0] \main_sdram_slave_p0_address assign $0\main_sdram_master_p0_bank[1:0] \main_sdram_slave_p0_bank @@ -270205,7 +271577,7 @@ module \ls180 assign $0\main_sdram_master_p0_rddata_en[0:0] \main_sdram_slave_p0_rddata_en assign $0\main_sdram_slave_p0_rddata[15:0] \main_sdram_master_p0_rddata assign $0\main_sdram_slave_p0_rddata_valid[0:0] \main_sdram_master_p0_rddata_valid - attribute \src "ls180.v:3122.6-3122.10" + attribute \src "ls180.v:3151.6-3151.10" case assign $0\main_sdram_master_p0_address[12:0] \main_sdram_inti_p0_address assign $0\main_sdram_master_p0_bank[1:0] \main_sdram_inti_p0_bank @@ -270244,40 +271616,24 @@ module \ls180 update \main_sdram_master_p0_wrdata_mask $0\main_sdram_master_p0_wrdata_mask[1:0] update \main_sdram_master_p0_rddata_en $0\main_sdram_master_p0_rddata_en[0:0] end - attribute \src "ls180.v:309.5-309.36" - process $proc$ls180.v:309$2969 - assign { } { } - assign $1\main_dfi_p0_rddata_valid[0:0] 1'0 - sync always - sync init - update \main_dfi_p0_rddata_valid $1\main_dfi_p0_rddata_valid[0:0] - end - attribute \src "ls180.v:310.11-310.32" - process $proc$ls180.v:310$2970 - assign { } { } - assign $1\main_rddata_en[2:0] 3'000 - sync always - sync init - update \main_rddata_en $1\main_rddata_en[2:0] - end - attribute \src "ls180.v:313.5-313.36" - process $proc$ls180.v:313$2971 + attribute \src "ls180.v:312.12-312.45" + process $proc$ls180.v:312$3096 assign { } { } - assign $1\main_sdram_inti_p0_cas_n[0:0] 1'1 + assign $1\main_sdram_inti_p0_rddata[15:0] 16'0000000000000000 sync always sync init - update \main_sdram_inti_p0_cas_n $1\main_sdram_inti_p0_cas_n[0:0] + update \main_sdram_inti_p0_rddata $1\main_sdram_inti_p0_rddata[15:0] end - attribute \src "ls180.v:314.5-314.35" - process $proc$ls180.v:314$2972 + attribute \src "ls180.v:313.5-313.43" + process $proc$ls180.v:313$3097 assign { } { } - assign $1\main_sdram_inti_p0_cs_n[0:0] 1'1 + assign $1\main_sdram_inti_p0_rddata_valid[0:0] 1'0 sync always sync init - update \main_sdram_inti_p0_cs_n $1\main_sdram_inti_p0_cs_n[0:0] + update \main_sdram_inti_p0_rddata_valid $1\main_sdram_inti_p0_rddata_valid[0:0] end - attribute \src "ls180.v:3144.1-3160.4" - process $proc$ls180.v:3144$116 + attribute \src "ls180.v:3173.1-3189.4" + process $proc$ls180.v:3173$180 assign { } { } assign { } { } assign { } { } @@ -270286,15 +271642,15 @@ module \ls180 assign $0\main_sdram_inti_p0_cs_n[0:0] 1'1 assign $0\main_sdram_inti_p0_ras_n[0:0] 1'1 assign $0\main_sdram_inti_p0_we_n[0:0] 1'1 - attribute \src "ls180.v:3149.2-3159.5" + attribute \src "ls180.v:3178.2-3188.5" switch \main_sdram_command_issue_re - attribute \src "ls180.v:3149.6-3149.33" + attribute \src "ls180.v:3178.6-3178.33" case 1'1 - assign $0\main_sdram_inti_p0_cs_n[0:0] $not$ls180.v:3150$117_Y - assign $0\main_sdram_inti_p0_we_n[0:0] $not$ls180.v:3151$118_Y - assign $0\main_sdram_inti_p0_cas_n[0:0] $not$ls180.v:3152$119_Y - assign $0\main_sdram_inti_p0_ras_n[0:0] $not$ls180.v:3153$120_Y - attribute \src "ls180.v:3154.6-3154.10" + assign $0\main_sdram_inti_p0_cs_n[0:0] $not$ls180.v:3179$181_Y + assign $0\main_sdram_inti_p0_we_n[0:0] $not$ls180.v:3180$182_Y + assign $0\main_sdram_inti_p0_cas_n[0:0] $not$ls180.v:3181$183_Y + assign $0\main_sdram_inti_p0_ras_n[0:0] $not$ls180.v:3182$184_Y + attribute \src "ls180.v:3183.6-3183.10" case assign $0\main_sdram_inti_p0_cs_n[0:0] 1'1 assign $0\main_sdram_inti_p0_we_n[0:0] 1'1 @@ -270307,49 +271663,25 @@ module \ls180 update \main_sdram_inti_p0_ras_n $0\main_sdram_inti_p0_ras_n[0:0] update \main_sdram_inti_p0_we_n $0\main_sdram_inti_p0_we_n[0:0] end - attribute \src "ls180.v:315.5-315.36" - process $proc$ls180.v:315$2973 - assign { } { } - assign $1\main_sdram_inti_p0_ras_n[0:0] 1'1 - sync always - sync init - update \main_sdram_inti_p0_ras_n $1\main_sdram_inti_p0_ras_n[0:0] - end - attribute \src "ls180.v:316.5-316.35" - process $proc$ls180.v:316$2974 - assign { } { } - assign $1\main_sdram_inti_p0_we_n[0:0] 1'1 - sync always - sync init - update \main_sdram_inti_p0_we_n $1\main_sdram_inti_p0_we_n[0:0] - end - attribute \src "ls180.v:320.5-320.36" - process $proc$ls180.v:320$2975 - assign { } { } - assign $0\main_sdram_inti_p0_act_n[0:0] 1'1 - sync always - update \main_sdram_inti_p0_act_n $0\main_sdram_inti_p0_act_n[0:0] - sync init - end - attribute \src "ls180.v:3203.1-3233.4" - process $proc$ls180.v:3203$129 + attribute \src "ls180.v:3232.1-3262.4" + process $proc$ls180.v:3232$193 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\main_sdram_cmd_last[0:0] 1'0 assign $0\main_sdram_sequencer_start0[0:0] 1'0 - assign { } { } assign $0\main_sdram_cmd_valid[0:0] 1'0 + assign { } { } + assign $0\main_sdram_cmd_last[0:0] 1'0 assign $0\builder_refresher_next_state[1:0] \builder_refresher_state - attribute \src "ls180.v:3209.2-3232.9" + attribute \src "ls180.v:3238.2-3261.9" switch \builder_refresher_state attribute \src "ls180.v:0.0-0.0" case 2'01 assign $0\main_sdram_cmd_valid[0:0] 1'1 - attribute \src "ls180.v:3212.4-3215.7" + attribute \src "ls180.v:3241.4-3244.7" switch \main_sdram_cmd_ready - attribute \src "ls180.v:3212.8-3212.28" + attribute \src "ls180.v:3241.8-3241.28" case 1'1 assign $0\main_sdram_sequencer_start0[0:0] 1'1 assign $0\builder_refresher_next_state[1:0] 2'10 @@ -270358,9 +271690,9 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 2'10 assign $0\main_sdram_cmd_valid[0:0] 1'1 - attribute \src "ls180.v:3219.4-3223.7" + attribute \src "ls180.v:3248.4-3252.7" switch \main_sdram_sequencer_done0 - attribute \src "ls180.v:3219.8-3219.34" + attribute \src "ls180.v:3248.8-3248.34" case 1'1 assign $0\main_sdram_cmd_valid[0:0] 1'0 assign $0\main_sdram_cmd_last[0:0] 1'1 @@ -270369,13 +271701,13 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case - attribute \src "ls180.v:3226.4-3230.7" + attribute \src "ls180.v:3255.4-3259.7" switch 1'1 - attribute \src "ls180.v:3226.8-3226.12" + attribute \src "ls180.v:3255.8-3255.12" case 1'1 - attribute \src "ls180.v:3227.5-3229.8" + attribute \src "ls180.v:3256.5-3258.8" switch \main_sdram_wants_refresh - attribute \src "ls180.v:3227.9-3227.33" + attribute \src "ls180.v:3256.9-3256.33" case 1'1 assign $0\builder_refresher_next_state[1:0] 2'01 case @@ -270389,43 +271721,43 @@ module \ls180 update \main_sdram_sequencer_start0 $0\main_sdram_sequencer_start0[0:0] update \builder_refresher_next_state $0\builder_refresher_next_state[1:0] end - attribute \src "ls180.v:3248.1-3255.4" - process $proc$ls180.v:3248$133 + attribute \src "ls180.v:3277.1-3284.4" + process $proc$ls180.v:3277$197 assign { } { } assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] 13'0000000000000 - attribute \src "ls180.v:3250.2-3254.5" + attribute \src "ls180.v:3279.2-3283.5" switch \main_sdram_bankmachine0_row_col_n_addr_sel - attribute \src "ls180.v:3250.6-3250.48" + attribute \src "ls180.v:3279.6-3279.48" case 1'1 assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] - attribute \src "ls180.v:3252.6-3252.10" + attribute \src "ls180.v:3281.6-3281.10" case - assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] $or$ls180.v:3253$135_Y + assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] $or$ls180.v:3282$199_Y end sync always update \main_sdram_bankmachine0_cmd_payload_a $0\main_sdram_bankmachine0_cmd_payload_a[12:0] end - attribute \src "ls180.v:325.12-325.45" - process $proc$ls180.v:325$2976 + attribute \src "ls180.v:328.12-328.46" + process $proc$ls180.v:328$3098 assign { } { } - assign $1\main_sdram_inti_p0_rddata[15:0] 16'0000000000000000 + assign $1\main_sdram_slave_p0_rddata[15:0] 16'0000000000000000 sync always sync init - update \main_sdram_inti_p0_rddata $1\main_sdram_inti_p0_rddata[15:0] + update \main_sdram_slave_p0_rddata $1\main_sdram_slave_p0_rddata[15:0] end - attribute \src "ls180.v:3259.1-3266.4" - process $proc$ls180.v:3259$142 + attribute \src "ls180.v:3288.1-3295.4" + process $proc$ls180.v:3288$206 assign { } { } assign $0\main_sdram_bankmachine0_auto_precharge[0:0] 1'0 - attribute \src "ls180.v:3261.2-3265.5" - switch $and$ls180.v:3261$143_Y - attribute \src "ls180.v:3261.6-3261.115" + attribute \src "ls180.v:3290.2-3294.5" + switch $and$ls180.v:3290$207_Y + attribute \src "ls180.v:3290.6-3290.115" case 1'1 - attribute \src "ls180.v:3262.3-3264.6" - switch $ne$ls180.v:3262$144_Y - attribute \src "ls180.v:3262.7-3262.143" + attribute \src "ls180.v:3291.3-3293.6" + switch $ne$ls180.v:3291$208_Y + attribute \src "ls180.v:3291.7-3291.143" case 1'1 - assign $0\main_sdram_bankmachine0_auto_precharge[0:0] $eq$ls180.v:3263$145_Y + assign $0\main_sdram_bankmachine0_auto_precharge[0:0] $eq$ls180.v:3292$209_Y case end case @@ -270433,32 +271765,56 @@ module \ls180 sync always update \main_sdram_bankmachine0_auto_precharge $0\main_sdram_bankmachine0_auto_precharge[0:0] end - attribute \src "ls180.v:326.5-326.43" - process $proc$ls180.v:326$2977 + attribute \src "ls180.v:329.5-329.44" + process $proc$ls180.v:329$3099 assign { } { } - assign $1\main_sdram_inti_p0_rddata_valid[0:0] 1'0 + assign $1\main_sdram_slave_p0_rddata_valid[0:0] 1'0 sync always sync init - update \main_sdram_inti_p0_rddata_valid $1\main_sdram_inti_p0_rddata_valid[0:0] + update \main_sdram_slave_p0_rddata_valid $1\main_sdram_slave_p0_rddata_valid[0:0] + end + attribute \src "ls180.v:330.12-330.48" + process $proc$ls180.v:330$3100 + assign { } { } + assign $1\main_sdram_master_p0_address[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_master_p0_address $1\main_sdram_master_p0_address[12:0] + end + attribute \src "ls180.v:331.11-331.43" + process $proc$ls180.v:331$3101 + assign { } { } + assign $1\main_sdram_master_p0_bank[1:0] 2'00 + sync always + sync init + update \main_sdram_master_p0_bank $1\main_sdram_master_p0_bank[1:0] end - attribute \src "ls180.v:3281.1-3288.4" - process $proc$ls180.v:3281$146 + attribute \src "ls180.v:3310.1-3317.4" + process $proc$ls180.v:3310$210 assign { } { } assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 - attribute \src "ls180.v:3283.2-3287.5" + attribute \src "ls180.v:3312.2-3316.5" switch \main_sdram_bankmachine0_cmd_buffer_lookahead_replace - attribute \src "ls180.v:3283.6-3283.58" + attribute \src "ls180.v:3312.6-3312.58" case 1'1 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3284$147_Y - attribute \src "ls180.v:3285.6-3285.10" + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3313$211_Y + attribute \src "ls180.v:3314.6-3314.10" case assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine0_cmd_buffer_lookahead_produce end sync always update \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] end - attribute \src "ls180.v:3297.1-3390.4" - process $proc$ls180.v:3297$155 + attribute \src "ls180.v:332.5-332.38" + process $proc$ls180.v:332$3102 + assign { } { } + assign $1\main_sdram_master_p0_cas_n[0:0] 1'1 + sync always + sync init + update \main_sdram_master_p0_cas_n $1\main_sdram_master_p0_cas_n[0:0] + end + attribute \src "ls180.v:3326.1-3419.4" + process $proc$ls180.v:3326$219 assign { } { } assign { } { } assign { } { } @@ -270473,37 +271829,37 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_sdram_bankmachine0_row_open[0:0] 1'0 - assign $0\main_sdram_bankmachine0_row_close[0:0] 1'0 - assign $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'0 assign $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'0 assign $0\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'0 - assign { } { } - assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'0 assign $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'0 + assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'0 + assign { } { } assign $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'0 assign $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'0 assign $0\main_sdram_bankmachine0_req_wdata_ready[0:0] 1'0 assign $0\main_sdram_bankmachine0_req_rdata_valid[0:0] 1'0 assign $0\main_sdram_bankmachine0_refresh_gnt[0:0] 1'0 assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine0_row_open[0:0] 1'0 + assign $0\main_sdram_bankmachine0_row_close[0:0] 1'0 + assign $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'0 assign $0\builder_bankmachine0_next_state[2:0] \builder_bankmachine0_state - attribute \src "ls180.v:3313.2-3389.9" + attribute \src "ls180.v:3342.2-3418.9" switch \builder_bankmachine0_state attribute \src "ls180.v:0.0-0.0" case 3'001 assign $0\main_sdram_bankmachine0_row_close[0:0] 1'1 - attribute \src "ls180.v:3315.4-3323.7" - switch $and$ls180.v:3315$156_Y - attribute \src "ls180.v:3315.8-3315.87" + attribute \src "ls180.v:3344.4-3352.7" + switch $and$ls180.v:3344$220_Y + attribute \src "ls180.v:3344.8-3344.87" case 1'1 assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'1 assign $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'1 assign $0\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'1 assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3317.5-3319.8" + attribute \src "ls180.v:3346.5-3348.8" switch \main_sdram_bankmachine0_cmd_ready - attribute \src "ls180.v:3317.9-3317.42" + attribute \src "ls180.v:3346.9-3346.42" case 1'1 assign $0\builder_bankmachine0_next_state[2:0] 3'101 case @@ -270513,27 +271869,27 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 3'010 assign $0\main_sdram_bankmachine0_row_close[0:0] 1'1 - attribute \src "ls180.v:3327.4-3329.7" - switch $and$ls180.v:3327$157_Y - attribute \src "ls180.v:3327.8-3327.87" + attribute \src "ls180.v:3356.4-3358.7" + switch $and$ls180.v:3356$221_Y + attribute \src "ls180.v:3356.8-3356.87" case 1'1 assign $0\builder_bankmachine0_next_state[2:0] 3'101 case end attribute \src "ls180.v:0.0-0.0" case 3'011 - attribute \src "ls180.v:3333.4-3342.7" + attribute \src "ls180.v:3362.4-3371.7" switch \main_sdram_bankmachine0_trccon_ready - attribute \src "ls180.v:3333.8-3333.44" + attribute \src "ls180.v:3362.8-3362.44" case 1'1 assign $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'1 assign $0\main_sdram_bankmachine0_row_open[0:0] 1'1 assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'1 assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1 assign $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'1 - attribute \src "ls180.v:3338.5-3340.8" + attribute \src "ls180.v:3367.5-3369.8" switch \main_sdram_bankmachine0_cmd_ready - attribute \src "ls180.v:3338.9-3338.42" + attribute \src "ls180.v:3367.9-3367.42" case 1'1 assign $0\builder_bankmachine0_next_state[2:0] 3'110 case @@ -270544,16 +271900,16 @@ module \ls180 case 3'100 assign $0\main_sdram_bankmachine0_row_close[0:0] 1'1 assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3345.4-3347.7" + attribute \src "ls180.v:3374.4-3376.7" switch \main_sdram_bankmachine0_twtpcon_ready - attribute \src "ls180.v:3345.8-3345.45" + attribute \src "ls180.v:3374.8-3374.45" case 1'1 assign $0\main_sdram_bankmachine0_refresh_gnt[0:0] 1'1 case end - attribute \src "ls180.v:3350.4-3352.7" - switch $not$ls180.v:3350$158_Y - attribute \src "ls180.v:3350.8-3350.46" + attribute \src "ls180.v:3379.4-3381.7" + switch $not$ls180.v:3379$222_Y + attribute \src "ls180.v:3379.8-3379.46" case 1'1 assign $0\builder_bankmachine0_next_state[2:0] 3'000 case @@ -270566,51 +271922,51 @@ module \ls180 assign $0\builder_bankmachine0_next_state[2:0] 3'000 attribute \src "ls180.v:0.0-0.0" case - attribute \src "ls180.v:3361.4-3387.7" + attribute \src "ls180.v:3390.4-3416.7" switch \main_sdram_bankmachine0_refresh_req - attribute \src "ls180.v:3361.8-3361.43" + attribute \src "ls180.v:3390.8-3390.43" case 1'1 assign $0\builder_bankmachine0_next_state[2:0] 3'100 - attribute \src "ls180.v:3363.8-3363.12" + attribute \src "ls180.v:3392.8-3392.12" case - attribute \src "ls180.v:3364.5-3386.8" + attribute \src "ls180.v:3393.5-3415.8" switch \main_sdram_bankmachine0_cmd_buffer_source_valid - attribute \src "ls180.v:3364.9-3364.56" + attribute \src "ls180.v:3393.9-3393.56" case 1'1 - attribute \src "ls180.v:3365.6-3385.9" + attribute \src "ls180.v:3394.6-3414.9" switch \main_sdram_bankmachine0_row_opened - attribute \src "ls180.v:3365.10-3365.44" + attribute \src "ls180.v:3394.10-3394.44" case 1'1 - attribute \src "ls180.v:3366.7-3382.10" + attribute \src "ls180.v:3395.7-3411.10" switch \main_sdram_bankmachine0_row_hit - attribute \src "ls180.v:3366.11-3366.42" + attribute \src "ls180.v:3395.11-3395.42" case 1'1 assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'1 assign $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'1 - attribute \src "ls180.v:3368.8-3375.11" + attribute \src "ls180.v:3397.8-3404.11" switch \main_sdram_bankmachine0_cmd_buffer_source_payload_we - attribute \src "ls180.v:3368.12-3368.64" + attribute \src "ls180.v:3397.12-3397.64" case 1'1 assign $0\main_sdram_bankmachine0_req_wdata_ready[0:0] \main_sdram_bankmachine0_cmd_ready assign $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'1 assign $0\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'1 - attribute \src "ls180.v:3372.12-3372.16" + attribute \src "ls180.v:3401.12-3401.16" case assign $0\main_sdram_bankmachine0_req_rdata_valid[0:0] \main_sdram_bankmachine0_cmd_ready assign $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'1 end - attribute \src "ls180.v:3377.8-3379.11" - switch $and$ls180.v:3377$159_Y - attribute \src "ls180.v:3377.12-3377.88" + attribute \src "ls180.v:3406.8-3408.11" + switch $and$ls180.v:3406$223_Y + attribute \src "ls180.v:3406.12-3406.88" case 1'1 assign $0\builder_bankmachine0_next_state[2:0] 3'010 case end - attribute \src "ls180.v:3380.11-3380.15" + attribute \src "ls180.v:3409.11-3409.15" case assign $0\builder_bankmachine0_next_state[2:0] 3'001 end - attribute \src "ls180.v:3383.10-3383.14" + attribute \src "ls180.v:3412.10-3412.14" case assign $0\builder_bankmachine0_next_state[2:0] 3'011 end @@ -270634,43 +271990,123 @@ module \ls180 update \main_sdram_bankmachine0_row_col_n_addr_sel $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] update \builder_bankmachine0_next_state $0\builder_bankmachine0_next_state[2:0] end - attribute \src "ls180.v:3405.1-3412.4" - process $proc$ls180.v:3405$163 + attribute \src "ls180.v:333.5-333.37" + process $proc$ls180.v:333$3103 + assign { } { } + assign $1\main_sdram_master_p0_cs_n[0:0] 1'1 + sync always + sync init + update \main_sdram_master_p0_cs_n $1\main_sdram_master_p0_cs_n[0:0] + end + attribute \src "ls180.v:334.5-334.38" + process $proc$ls180.v:334$3104 + assign { } { } + assign $1\main_sdram_master_p0_ras_n[0:0] 1'1 + sync always + sync init + update \main_sdram_master_p0_ras_n $1\main_sdram_master_p0_ras_n[0:0] + end + attribute \src "ls180.v:335.5-335.37" + process $proc$ls180.v:335$3105 + assign { } { } + assign $1\main_sdram_master_p0_we_n[0:0] 1'1 + sync always + sync init + update \main_sdram_master_p0_we_n $1\main_sdram_master_p0_we_n[0:0] + end + attribute \src "ls180.v:336.5-336.36" + process $proc$ls180.v:336$3106 + assign { } { } + assign $1\main_sdram_master_p0_cke[0:0] 1'0 + sync always + sync init + update \main_sdram_master_p0_cke $1\main_sdram_master_p0_cke[0:0] + end + attribute \src "ls180.v:337.5-337.36" + process $proc$ls180.v:337$3107 + assign { } { } + assign $1\main_sdram_master_p0_odt[0:0] 1'0 + sync always + sync init + update \main_sdram_master_p0_odt $1\main_sdram_master_p0_odt[0:0] + end + attribute \src "ls180.v:338.5-338.40" + process $proc$ls180.v:338$3108 + assign { } { } + assign $1\main_sdram_master_p0_reset_n[0:0] 1'0 + sync always + sync init + update \main_sdram_master_p0_reset_n $1\main_sdram_master_p0_reset_n[0:0] + end + attribute \src "ls180.v:339.5-339.38" + process $proc$ls180.v:339$3109 + assign { } { } + assign $1\main_sdram_master_p0_act_n[0:0] 1'1 + sync always + sync init + update \main_sdram_master_p0_act_n $1\main_sdram_master_p0_act_n[0:0] + end + attribute \src "ls180.v:340.12-340.47" + process $proc$ls180.v:340$3110 + assign { } { } + assign $1\main_sdram_master_p0_wrdata[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdram_master_p0_wrdata $1\main_sdram_master_p0_wrdata[15:0] + end + attribute \src "ls180.v:341.5-341.42" + process $proc$ls180.v:341$3111 + assign { } { } + assign $1\main_sdram_master_p0_wrdata_en[0:0] 1'0 + sync always + sync init + update \main_sdram_master_p0_wrdata_en $1\main_sdram_master_p0_wrdata_en[0:0] + end + attribute \src "ls180.v:342.11-342.50" + process $proc$ls180.v:342$3112 + assign { } { } + assign $1\main_sdram_master_p0_wrdata_mask[1:0] 2'00 + sync always + sync init + update \main_sdram_master_p0_wrdata_mask $1\main_sdram_master_p0_wrdata_mask[1:0] + end + attribute \src "ls180.v:343.5-343.42" + process $proc$ls180.v:343$3113 + assign { } { } + assign $1\main_sdram_master_p0_rddata_en[0:0] 1'0 + sync always + sync init + update \main_sdram_master_p0_rddata_en $1\main_sdram_master_p0_rddata_en[0:0] + end + attribute \src "ls180.v:3434.1-3441.4" + process $proc$ls180.v:3434$227 assign { } { } assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] 13'0000000000000 - attribute \src "ls180.v:3407.2-3411.5" + attribute \src "ls180.v:3436.2-3440.5" switch \main_sdram_bankmachine1_row_col_n_addr_sel - attribute \src "ls180.v:3407.6-3407.48" + attribute \src "ls180.v:3436.6-3436.48" case 1'1 assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] - attribute \src "ls180.v:3409.6-3409.10" + attribute \src "ls180.v:3438.6-3438.10" case - assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] $or$ls180.v:3410$165_Y + assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] $or$ls180.v:3439$229_Y end sync always update \main_sdram_bankmachine1_cmd_payload_a $0\main_sdram_bankmachine1_cmd_payload_a[12:0] end - attribute \src "ls180.v:341.12-341.46" - process $proc$ls180.v:341$2978 - assign { } { } - assign $1\main_sdram_slave_p0_rddata[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdram_slave_p0_rddata $1\main_sdram_slave_p0_rddata[15:0] - end - attribute \src "ls180.v:3416.1-3423.4" - process $proc$ls180.v:3416$172 + attribute \src "ls180.v:3445.1-3452.4" + process $proc$ls180.v:3445$236 assign { } { } assign $0\main_sdram_bankmachine1_auto_precharge[0:0] 1'0 - attribute \src "ls180.v:3418.2-3422.5" - switch $and$ls180.v:3418$173_Y - attribute \src "ls180.v:3418.6-3418.115" + attribute \src "ls180.v:3447.2-3451.5" + switch $and$ls180.v:3447$237_Y + attribute \src "ls180.v:3447.6-3447.115" case 1'1 - attribute \src "ls180.v:3419.3-3421.6" - switch $ne$ls180.v:3419$174_Y - attribute \src "ls180.v:3419.7-3419.143" + attribute \src "ls180.v:3448.3-3450.6" + switch $ne$ls180.v:3448$238_Y + attribute \src "ls180.v:3448.7-3448.143" case 1'1 - assign $0\main_sdram_bankmachine1_auto_precharge[0:0] $eq$ls180.v:3420$175_Y + assign $0\main_sdram_bankmachine1_auto_precharge[0:0] $eq$ls180.v:3449$239_Y case end case @@ -270678,56 +272114,24 @@ module \ls180 sync always update \main_sdram_bankmachine1_auto_precharge $0\main_sdram_bankmachine1_auto_precharge[0:0] end - attribute \src "ls180.v:342.5-342.44" - process $proc$ls180.v:342$2979 - assign { } { } - assign $1\main_sdram_slave_p0_rddata_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_slave_p0_rddata_valid $1\main_sdram_slave_p0_rddata_valid[0:0] - end - attribute \src "ls180.v:343.12-343.48" - process $proc$ls180.v:343$2980 - assign { } { } - assign $1\main_sdram_master_p0_address[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_master_p0_address $1\main_sdram_master_p0_address[12:0] - end - attribute \src "ls180.v:3438.1-3445.4" - process $proc$ls180.v:3438$176 + attribute \src "ls180.v:3467.1-3474.4" + process $proc$ls180.v:3467$240 assign { } { } assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 - attribute \src "ls180.v:3440.2-3444.5" + attribute \src "ls180.v:3469.2-3473.5" switch \main_sdram_bankmachine1_cmd_buffer_lookahead_replace - attribute \src "ls180.v:3440.6-3440.58" + attribute \src "ls180.v:3469.6-3469.58" case 1'1 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3441$177_Y - attribute \src "ls180.v:3442.6-3442.10" + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3470$241_Y + attribute \src "ls180.v:3471.6-3471.10" case assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine1_cmd_buffer_lookahead_produce end sync always update \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] end - attribute \src "ls180.v:344.11-344.43" - process $proc$ls180.v:344$2981 - assign { } { } - assign $1\main_sdram_master_p0_bank[1:0] 2'00 - sync always - sync init - update \main_sdram_master_p0_bank $1\main_sdram_master_p0_bank[1:0] - end - attribute \src "ls180.v:345.5-345.38" - process $proc$ls180.v:345$2982 - assign { } { } - assign $1\main_sdram_master_p0_cas_n[0:0] 1'1 - sync always - sync init - update \main_sdram_master_p0_cas_n $1\main_sdram_master_p0_cas_n[0:0] - end - attribute \src "ls180.v:3454.1-3547.4" - process $proc$ls180.v:3454$185 + attribute \src "ls180.v:3483.1-3576.4" + process $proc$ls180.v:3483$249 assign { } { } assign { } { } assign { } { } @@ -270742,10 +272146,8 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_sdram_bankmachine1_refresh_gnt[0:0] 1'0 - assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'0 - assign { } { } assign $0\main_sdram_bankmachine1_row_open[0:0] 1'0 + assign { } { } assign $0\main_sdram_bankmachine1_row_close[0:0] 1'0 assign $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'0 assign $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'0 @@ -270756,23 +272158,25 @@ module \ls180 assign $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'0 assign $0\main_sdram_bankmachine1_req_wdata_ready[0:0] 1'0 assign $0\main_sdram_bankmachine1_req_rdata_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine1_refresh_gnt[0:0] 1'0 + assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'0 assign $0\builder_bankmachine1_next_state[2:0] \builder_bankmachine1_state - attribute \src "ls180.v:3470.2-3546.9" + attribute \src "ls180.v:3499.2-3575.9" switch \builder_bankmachine1_state attribute \src "ls180.v:0.0-0.0" case 3'001 assign $0\main_sdram_bankmachine1_row_close[0:0] 1'1 - attribute \src "ls180.v:3472.4-3480.7" - switch $and$ls180.v:3472$186_Y - attribute \src "ls180.v:3472.8-3472.87" + attribute \src "ls180.v:3501.4-3509.7" + switch $and$ls180.v:3501$250_Y + attribute \src "ls180.v:3501.8-3501.87" case 1'1 assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'1 assign $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'1 assign $0\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'1 assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3474.5-3476.8" + attribute \src "ls180.v:3503.5-3505.8" switch \main_sdram_bankmachine1_cmd_ready - attribute \src "ls180.v:3474.9-3474.42" + attribute \src "ls180.v:3503.9-3503.42" case 1'1 assign $0\builder_bankmachine1_next_state[2:0] 3'101 case @@ -270782,27 +272186,27 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 3'010 assign $0\main_sdram_bankmachine1_row_close[0:0] 1'1 - attribute \src "ls180.v:3484.4-3486.7" - switch $and$ls180.v:3484$187_Y - attribute \src "ls180.v:3484.8-3484.87" + attribute \src "ls180.v:3513.4-3515.7" + switch $and$ls180.v:3513$251_Y + attribute \src "ls180.v:3513.8-3513.87" case 1'1 assign $0\builder_bankmachine1_next_state[2:0] 3'101 case end attribute \src "ls180.v:0.0-0.0" case 3'011 - attribute \src "ls180.v:3490.4-3499.7" + attribute \src "ls180.v:3519.4-3528.7" switch \main_sdram_bankmachine1_trccon_ready - attribute \src "ls180.v:3490.8-3490.44" + attribute \src "ls180.v:3519.8-3519.44" case 1'1 assign $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'1 assign $0\main_sdram_bankmachine1_row_open[0:0] 1'1 assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'1 assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1 assign $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'1 - attribute \src "ls180.v:3495.5-3497.8" + attribute \src "ls180.v:3524.5-3526.8" switch \main_sdram_bankmachine1_cmd_ready - attribute \src "ls180.v:3495.9-3495.42" + attribute \src "ls180.v:3524.9-3524.42" case 1'1 assign $0\builder_bankmachine1_next_state[2:0] 3'110 case @@ -270813,16 +272217,16 @@ module \ls180 case 3'100 assign $0\main_sdram_bankmachine1_row_close[0:0] 1'1 assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3502.4-3504.7" + attribute \src "ls180.v:3531.4-3533.7" switch \main_sdram_bankmachine1_twtpcon_ready - attribute \src "ls180.v:3502.8-3502.45" + attribute \src "ls180.v:3531.8-3531.45" case 1'1 assign $0\main_sdram_bankmachine1_refresh_gnt[0:0] 1'1 case end - attribute \src "ls180.v:3507.4-3509.7" - switch $not$ls180.v:3507$188_Y - attribute \src "ls180.v:3507.8-3507.46" + attribute \src "ls180.v:3536.4-3538.7" + switch $not$ls180.v:3536$252_Y + attribute \src "ls180.v:3536.8-3536.46" case 1'1 assign $0\builder_bankmachine1_next_state[2:0] 3'000 case @@ -270835,51 +272239,51 @@ module \ls180 assign $0\builder_bankmachine1_next_state[2:0] 3'000 attribute \src "ls180.v:0.0-0.0" case - attribute \src "ls180.v:3518.4-3544.7" + attribute \src "ls180.v:3547.4-3573.7" switch \main_sdram_bankmachine1_refresh_req - attribute \src "ls180.v:3518.8-3518.43" + attribute \src "ls180.v:3547.8-3547.43" case 1'1 assign $0\builder_bankmachine1_next_state[2:0] 3'100 - attribute \src "ls180.v:3520.8-3520.12" + attribute \src "ls180.v:3549.8-3549.12" case - attribute \src "ls180.v:3521.5-3543.8" + attribute \src "ls180.v:3550.5-3572.8" switch \main_sdram_bankmachine1_cmd_buffer_source_valid - attribute \src "ls180.v:3521.9-3521.56" + attribute \src "ls180.v:3550.9-3550.56" case 1'1 - attribute \src "ls180.v:3522.6-3542.9" + attribute \src "ls180.v:3551.6-3571.9" switch \main_sdram_bankmachine1_row_opened - attribute \src "ls180.v:3522.10-3522.44" + attribute \src "ls180.v:3551.10-3551.44" case 1'1 - attribute \src "ls180.v:3523.7-3539.10" + attribute \src "ls180.v:3552.7-3568.10" switch \main_sdram_bankmachine1_row_hit - attribute \src "ls180.v:3523.11-3523.42" + attribute \src "ls180.v:3552.11-3552.42" case 1'1 assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'1 assign $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'1 - attribute \src "ls180.v:3525.8-3532.11" + attribute \src "ls180.v:3554.8-3561.11" switch \main_sdram_bankmachine1_cmd_buffer_source_payload_we - attribute \src "ls180.v:3525.12-3525.64" + attribute \src "ls180.v:3554.12-3554.64" case 1'1 assign $0\main_sdram_bankmachine1_req_wdata_ready[0:0] \main_sdram_bankmachine1_cmd_ready assign $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'1 assign $0\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'1 - attribute \src "ls180.v:3529.12-3529.16" + attribute \src "ls180.v:3558.12-3558.16" case assign $0\main_sdram_bankmachine1_req_rdata_valid[0:0] \main_sdram_bankmachine1_cmd_ready assign $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'1 end - attribute \src "ls180.v:3534.8-3536.11" - switch $and$ls180.v:3534$189_Y - attribute \src "ls180.v:3534.12-3534.88" + attribute \src "ls180.v:3563.8-3565.11" + switch $and$ls180.v:3563$253_Y + attribute \src "ls180.v:3563.12-3563.88" case 1'1 assign $0\builder_bankmachine1_next_state[2:0] 3'010 case end - attribute \src "ls180.v:3537.11-3537.15" + attribute \src "ls180.v:3566.11-3566.15" case assign $0\builder_bankmachine1_next_state[2:0] 3'001 end - attribute \src "ls180.v:3540.10-3540.14" + attribute \src "ls180.v:3569.10-3569.14" case assign $0\builder_bankmachine1_next_state[2:0] 3'011 end @@ -270903,123 +272307,99 @@ module \ls180 update \main_sdram_bankmachine1_row_col_n_addr_sel $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] update \builder_bankmachine1_next_state $0\builder_bankmachine1_next_state[2:0] end - attribute \src "ls180.v:346.5-346.37" - process $proc$ls180.v:346$2983 + attribute \src "ls180.v:350.11-350.36" + process $proc$ls180.v:350$3114 assign { } { } - assign $1\main_sdram_master_p0_cs_n[0:0] 1'1 - sync always - sync init - update \main_sdram_master_p0_cs_n $1\main_sdram_master_p0_cs_n[0:0] - end - attribute \src "ls180.v:347.5-347.38" - process $proc$ls180.v:347$2984 - assign { } { } - assign $1\main_sdram_master_p0_ras_n[0:0] 1'1 - sync always - sync init - update \main_sdram_master_p0_ras_n $1\main_sdram_master_p0_ras_n[0:0] - end - attribute \src "ls180.v:348.5-348.37" - process $proc$ls180.v:348$2985 - assign { } { } - assign $1\main_sdram_master_p0_we_n[0:0] 1'1 - sync always - sync init - update \main_sdram_master_p0_we_n $1\main_sdram_master_p0_we_n[0:0] - end - attribute \src "ls180.v:349.5-349.36" - process $proc$ls180.v:349$2986 - assign { } { } - assign $1\main_sdram_master_p0_cke[0:0] 1'0 - sync always - sync init - update \main_sdram_master_p0_cke $1\main_sdram_master_p0_cke[0:0] - end - attribute \src "ls180.v:350.5-350.36" - process $proc$ls180.v:350$2987 - assign { } { } - assign $1\main_sdram_master_p0_odt[0:0] 1'0 + assign $1\main_sdram_storage[3:0] 4'0001 sync always sync init - update \main_sdram_master_p0_odt $1\main_sdram_master_p0_odt[0:0] + update \main_sdram_storage $1\main_sdram_storage[3:0] end - attribute \src "ls180.v:351.5-351.40" - process $proc$ls180.v:351$2988 + attribute \src "ls180.v:351.5-351.25" + process $proc$ls180.v:351$3115 assign { } { } - assign $1\main_sdram_master_p0_reset_n[0:0] 1'0 + assign $1\main_sdram_re[0:0] 1'0 sync always sync init - update \main_sdram_master_p0_reset_n $1\main_sdram_master_p0_reset_n[0:0] + update \main_sdram_re $1\main_sdram_re[0:0] end - attribute \src "ls180.v:352.5-352.38" - process $proc$ls180.v:352$2989 + attribute \src "ls180.v:352.11-352.44" + process $proc$ls180.v:352$3116 assign { } { } - assign $1\main_sdram_master_p0_act_n[0:0] 1'1 + assign $1\main_sdram_command_storage[5:0] 6'000000 sync always sync init - update \main_sdram_master_p0_act_n $1\main_sdram_master_p0_act_n[0:0] + update \main_sdram_command_storage $1\main_sdram_command_storage[5:0] end - attribute \src "ls180.v:353.12-353.47" - process $proc$ls180.v:353$2990 + attribute \src "ls180.v:353.5-353.33" + process $proc$ls180.v:353$3117 assign { } { } - assign $1\main_sdram_master_p0_wrdata[15:0] 16'0000000000000000 + assign $1\main_sdram_command_re[0:0] 1'0 sync always sync init - update \main_sdram_master_p0_wrdata $1\main_sdram_master_p0_wrdata[15:0] + update \main_sdram_command_re $1\main_sdram_command_re[0:0] end - attribute \src "ls180.v:354.5-354.42" - process $proc$ls180.v:354$2991 + attribute \src "ls180.v:357.5-357.38" + process $proc$ls180.v:357$3118 assign { } { } - assign $1\main_sdram_master_p0_wrdata_en[0:0] 1'0 + assign $0\main_sdram_command_issue_w[0:0] 1'0 sync always + update \main_sdram_command_issue_w $0\main_sdram_command_issue_w[0:0] sync init - update \main_sdram_master_p0_wrdata_en $1\main_sdram_master_p0_wrdata_en[0:0] end - attribute \src "ls180.v:355.11-355.50" - process $proc$ls180.v:355$2992 + attribute \src "ls180.v:358.12-358.46" + process $proc$ls180.v:358$3119 assign { } { } - assign $1\main_sdram_master_p0_wrdata_mask[1:0] 2'00 + assign $1\main_sdram_address_storage[12:0] 13'0000000000000 sync always sync init - update \main_sdram_master_p0_wrdata_mask $1\main_sdram_master_p0_wrdata_mask[1:0] + update \main_sdram_address_storage $1\main_sdram_address_storage[12:0] end - attribute \src "ls180.v:356.5-356.42" - process $proc$ls180.v:356$2993 + attribute \src "ls180.v:359.5-359.33" + process $proc$ls180.v:359$3120 assign { } { } - assign $1\main_sdram_master_p0_rddata_en[0:0] 1'0 + assign $1\main_sdram_address_re[0:0] 1'0 sync always sync init - update \main_sdram_master_p0_rddata_en $1\main_sdram_master_p0_rddata_en[0:0] + update \main_sdram_address_re $1\main_sdram_address_re[0:0] end - attribute \src "ls180.v:3562.1-3569.4" - process $proc$ls180.v:3562$193 + attribute \src "ls180.v:3591.1-3598.4" + process $proc$ls180.v:3591$257 assign { } { } assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] 13'0000000000000 - attribute \src "ls180.v:3564.2-3568.5" + attribute \src "ls180.v:3593.2-3597.5" switch \main_sdram_bankmachine2_row_col_n_addr_sel - attribute \src "ls180.v:3564.6-3564.48" + attribute \src "ls180.v:3593.6-3593.48" case 1'1 assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] - attribute \src "ls180.v:3566.6-3566.10" + attribute \src "ls180.v:3595.6-3595.10" case - assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] $or$ls180.v:3567$195_Y + assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] $or$ls180.v:3596$259_Y end sync always update \main_sdram_bankmachine2_cmd_payload_a $0\main_sdram_bankmachine2_cmd_payload_a[12:0] end - attribute \src "ls180.v:3573.1-3580.4" - process $proc$ls180.v:3573$202 + attribute \src "ls180.v:360.11-360.45" + process $proc$ls180.v:360$3121 + assign { } { } + assign $1\main_sdram_baddress_storage[1:0] 2'00 + sync always + sync init + update \main_sdram_baddress_storage $1\main_sdram_baddress_storage[1:0] + end + attribute \src "ls180.v:3602.1-3609.4" + process $proc$ls180.v:3602$266 assign { } { } assign $0\main_sdram_bankmachine2_auto_precharge[0:0] 1'0 - attribute \src "ls180.v:3575.2-3579.5" - switch $and$ls180.v:3575$203_Y - attribute \src "ls180.v:3575.6-3575.115" + attribute \src "ls180.v:3604.2-3608.5" + switch $and$ls180.v:3604$267_Y + attribute \src "ls180.v:3604.6-3604.115" case 1'1 - attribute \src "ls180.v:3576.3-3578.6" - switch $ne$ls180.v:3576$204_Y - attribute \src "ls180.v:3576.7-3576.143" + attribute \src "ls180.v:3605.3-3607.6" + switch $ne$ls180.v:3605$268_Y + attribute \src "ls180.v:3605.7-3605.143" case 1'1 - assign $0\main_sdram_bankmachine2_auto_precharge[0:0] $eq$ls180.v:3577$205_Y + assign $0\main_sdram_bankmachine2_auto_precharge[0:0] $eq$ls180.v:3606$269_Y case end case @@ -271027,25 +272407,56 @@ module \ls180 sync always update \main_sdram_bankmachine2_auto_precharge $0\main_sdram_bankmachine2_auto_precharge[0:0] end - attribute \src "ls180.v:3595.1-3602.4" - process $proc$ls180.v:3595$206 + attribute \src "ls180.v:361.5-361.34" + process $proc$ls180.v:361$3122 + assign { } { } + assign $1\main_sdram_baddress_re[0:0] 1'0 + sync always + sync init + update \main_sdram_baddress_re $1\main_sdram_baddress_re[0:0] + end + attribute \src "ls180.v:362.12-362.45" + process $proc$ls180.v:362$3123 + assign { } { } + assign $1\main_sdram_wrdata_storage[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdram_wrdata_storage $1\main_sdram_wrdata_storage[15:0] + end + attribute \src "ls180.v:3624.1-3631.4" + process $proc$ls180.v:3624$270 assign { } { } assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 - attribute \src "ls180.v:3597.2-3601.5" + attribute \src "ls180.v:3626.2-3630.5" switch \main_sdram_bankmachine2_cmd_buffer_lookahead_replace - attribute \src "ls180.v:3597.6-3597.58" + attribute \src "ls180.v:3626.6-3626.58" case 1'1 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3598$207_Y - attribute \src "ls180.v:3599.6-3599.10" + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3627$271_Y + attribute \src "ls180.v:3628.6-3628.10" case assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine2_cmd_buffer_lookahead_produce end sync always update \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] end - attribute \src "ls180.v:3611.1-3704.4" - process $proc$ls180.v:3611$215 + attribute \src "ls180.v:363.5-363.32" + process $proc$ls180.v:363$3124 assign { } { } + assign $1\main_sdram_wrdata_re[0:0] 1'0 + sync always + sync init + update \main_sdram_wrdata_re $1\main_sdram_wrdata_re[0:0] + end + attribute \src "ls180.v:364.12-364.37" + process $proc$ls180.v:364$3125 + assign { } { } + assign $1\main_sdram_status[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdram_status $1\main_sdram_status[15:0] + end + attribute \src "ls180.v:3640.1-3733.4" + process $proc$ls180.v:3640$279 assign { } { } assign { } { } assign { } { } @@ -271059,37 +272470,38 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'0 - assign $0\main_sdram_bankmachine2_req_wdata_ready[0:0] 1'0 assign { } { } - assign $0\main_sdram_bankmachine2_req_rdata_valid[0:0] 1'0 assign $0\main_sdram_bankmachine2_refresh_gnt[0:0] 1'0 assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'0 - assign $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0 assign $0\main_sdram_bankmachine2_row_open[0:0] 1'0 assign $0\main_sdram_bankmachine2_row_close[0:0] 1'0 assign $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'0 assign $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'0 assign $0\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'0 + assign $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0 assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'0 assign $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0 + assign $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'0 + assign $0\main_sdram_bankmachine2_req_wdata_ready[0:0] 1'0 + assign $0\main_sdram_bankmachine2_req_rdata_valid[0:0] 1'0 + assign { } { } assign $0\builder_bankmachine2_next_state[2:0] \builder_bankmachine2_state - attribute \src "ls180.v:3627.2-3703.9" + attribute \src "ls180.v:3656.2-3732.9" switch \builder_bankmachine2_state attribute \src "ls180.v:0.0-0.0" case 3'001 assign $0\main_sdram_bankmachine2_row_close[0:0] 1'1 - attribute \src "ls180.v:3629.4-3637.7" - switch $and$ls180.v:3629$216_Y - attribute \src "ls180.v:3629.8-3629.87" + attribute \src "ls180.v:3658.4-3666.7" + switch $and$ls180.v:3658$280_Y + attribute \src "ls180.v:3658.8-3658.87" case 1'1 assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'1 assign $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'1 assign $0\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'1 assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3631.5-3633.8" + attribute \src "ls180.v:3660.5-3662.8" switch \main_sdram_bankmachine2_cmd_ready - attribute \src "ls180.v:3631.9-3631.42" + attribute \src "ls180.v:3660.9-3660.42" case 1'1 assign $0\builder_bankmachine2_next_state[2:0] 3'101 case @@ -271099,27 +272511,27 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 3'010 assign $0\main_sdram_bankmachine2_row_close[0:0] 1'1 - attribute \src "ls180.v:3641.4-3643.7" - switch $and$ls180.v:3641$217_Y - attribute \src "ls180.v:3641.8-3641.87" + attribute \src "ls180.v:3670.4-3672.7" + switch $and$ls180.v:3670$281_Y + attribute \src "ls180.v:3670.8-3670.87" case 1'1 assign $0\builder_bankmachine2_next_state[2:0] 3'101 case end attribute \src "ls180.v:0.0-0.0" case 3'011 - attribute \src "ls180.v:3647.4-3656.7" + attribute \src "ls180.v:3676.4-3685.7" switch \main_sdram_bankmachine2_trccon_ready - attribute \src "ls180.v:3647.8-3647.44" + attribute \src "ls180.v:3676.8-3676.44" case 1'1 assign $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'1 assign $0\main_sdram_bankmachine2_row_open[0:0] 1'1 assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'1 assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1 assign $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'1 - attribute \src "ls180.v:3652.5-3654.8" + attribute \src "ls180.v:3681.5-3683.8" switch \main_sdram_bankmachine2_cmd_ready - attribute \src "ls180.v:3652.9-3652.42" + attribute \src "ls180.v:3681.9-3681.42" case 1'1 assign $0\builder_bankmachine2_next_state[2:0] 3'110 case @@ -271130,16 +272542,16 @@ module \ls180 case 3'100 assign $0\main_sdram_bankmachine2_row_close[0:0] 1'1 assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3659.4-3661.7" + attribute \src "ls180.v:3688.4-3690.7" switch \main_sdram_bankmachine2_twtpcon_ready - attribute \src "ls180.v:3659.8-3659.45" + attribute \src "ls180.v:3688.8-3688.45" case 1'1 assign $0\main_sdram_bankmachine2_refresh_gnt[0:0] 1'1 case end - attribute \src "ls180.v:3664.4-3666.7" - switch $not$ls180.v:3664$218_Y - attribute \src "ls180.v:3664.8-3664.46" + attribute \src "ls180.v:3693.4-3695.7" + switch $not$ls180.v:3693$282_Y + attribute \src "ls180.v:3693.8-3693.46" case 1'1 assign $0\builder_bankmachine2_next_state[2:0] 3'000 case @@ -271152,51 +272564,51 @@ module \ls180 assign $0\builder_bankmachine2_next_state[2:0] 3'000 attribute \src "ls180.v:0.0-0.0" case - attribute \src "ls180.v:3675.4-3701.7" + attribute \src "ls180.v:3704.4-3730.7" switch \main_sdram_bankmachine2_refresh_req - attribute \src "ls180.v:3675.8-3675.43" + attribute \src "ls180.v:3704.8-3704.43" case 1'1 assign $0\builder_bankmachine2_next_state[2:0] 3'100 - attribute \src "ls180.v:3677.8-3677.12" + attribute \src "ls180.v:3706.8-3706.12" case - attribute \src "ls180.v:3678.5-3700.8" + attribute \src "ls180.v:3707.5-3729.8" switch \main_sdram_bankmachine2_cmd_buffer_source_valid - attribute \src "ls180.v:3678.9-3678.56" + attribute \src "ls180.v:3707.9-3707.56" case 1'1 - attribute \src "ls180.v:3679.6-3699.9" + attribute \src "ls180.v:3708.6-3728.9" switch \main_sdram_bankmachine2_row_opened - attribute \src "ls180.v:3679.10-3679.44" + attribute \src "ls180.v:3708.10-3708.44" case 1'1 - attribute \src "ls180.v:3680.7-3696.10" + attribute \src "ls180.v:3709.7-3725.10" switch \main_sdram_bankmachine2_row_hit - attribute \src "ls180.v:3680.11-3680.42" + attribute \src "ls180.v:3709.11-3709.42" case 1'1 assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'1 assign $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'1 - attribute \src "ls180.v:3682.8-3689.11" + attribute \src "ls180.v:3711.8-3718.11" switch \main_sdram_bankmachine2_cmd_buffer_source_payload_we - attribute \src "ls180.v:3682.12-3682.64" + attribute \src "ls180.v:3711.12-3711.64" case 1'1 assign $0\main_sdram_bankmachine2_req_wdata_ready[0:0] \main_sdram_bankmachine2_cmd_ready assign $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'1 assign $0\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'1 - attribute \src "ls180.v:3686.12-3686.16" + attribute \src "ls180.v:3715.12-3715.16" case assign $0\main_sdram_bankmachine2_req_rdata_valid[0:0] \main_sdram_bankmachine2_cmd_ready assign $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'1 end - attribute \src "ls180.v:3691.8-3693.11" - switch $and$ls180.v:3691$219_Y - attribute \src "ls180.v:3691.12-3691.88" + attribute \src "ls180.v:3720.8-3722.11" + switch $and$ls180.v:3720$283_Y + attribute \src "ls180.v:3720.12-3720.88" case 1'1 assign $0\builder_bankmachine2_next_state[2:0] 3'010 case end - attribute \src "ls180.v:3694.11-3694.15" + attribute \src "ls180.v:3723.11-3723.15" case assign $0\builder_bankmachine2_next_state[2:0] 3'001 end - attribute \src "ls180.v:3697.10-3697.14" + attribute \src "ls180.v:3726.10-3726.14" case assign $0\builder_bankmachine2_next_state[2:0] 3'011 end @@ -271220,99 +272632,35 @@ module \ls180 update \main_sdram_bankmachine2_row_col_n_addr_sel $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] update \builder_bankmachine2_next_state $0\builder_bankmachine2_next_state[2:0] end - attribute \src "ls180.v:363.11-363.36" - process $proc$ls180.v:363$2994 - assign { } { } - assign $1\main_sdram_storage[3:0] 4'0001 - sync always - sync init - update \main_sdram_storage $1\main_sdram_storage[3:0] - end - attribute \src "ls180.v:364.5-364.25" - process $proc$ls180.v:364$2995 - assign { } { } - assign $1\main_sdram_re[0:0] 1'0 - sync always - sync init - update \main_sdram_re $1\main_sdram_re[0:0] - end - attribute \src "ls180.v:365.11-365.44" - process $proc$ls180.v:365$2996 - assign { } { } - assign $1\main_sdram_command_storage[5:0] 6'000000 - sync always - sync init - update \main_sdram_command_storage $1\main_sdram_command_storage[5:0] - end - attribute \src "ls180.v:366.5-366.33" - process $proc$ls180.v:366$2997 - assign { } { } - assign $1\main_sdram_command_re[0:0] 1'0 - sync always - sync init - update \main_sdram_command_re $1\main_sdram_command_re[0:0] - end - attribute \src "ls180.v:370.5-370.38" - process $proc$ls180.v:370$2998 - assign { } { } - assign $0\main_sdram_command_issue_w[0:0] 1'0 - sync always - update \main_sdram_command_issue_w $0\main_sdram_command_issue_w[0:0] - sync init - end - attribute \src "ls180.v:371.12-371.46" - process $proc$ls180.v:371$2999 - assign { } { } - assign $1\main_sdram_address_storage[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_address_storage $1\main_sdram_address_storage[12:0] - end - attribute \src "ls180.v:3719.1-3726.4" - process $proc$ls180.v:3719$223 + attribute \src "ls180.v:3748.1-3755.4" + process $proc$ls180.v:3748$287 assign { } { } assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] 13'0000000000000 - attribute \src "ls180.v:3721.2-3725.5" + attribute \src "ls180.v:3750.2-3754.5" switch \main_sdram_bankmachine3_row_col_n_addr_sel - attribute \src "ls180.v:3721.6-3721.48" + attribute \src "ls180.v:3750.6-3750.48" case 1'1 assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] - attribute \src "ls180.v:3723.6-3723.10" + attribute \src "ls180.v:3752.6-3752.10" case - assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] $or$ls180.v:3724$225_Y + assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] $or$ls180.v:3753$289_Y end sync always update \main_sdram_bankmachine3_cmd_payload_a $0\main_sdram_bankmachine3_cmd_payload_a[12:0] end - attribute \src "ls180.v:372.5-372.33" - process $proc$ls180.v:372$3000 - assign { } { } - assign $1\main_sdram_address_re[0:0] 1'0 - sync always - sync init - update \main_sdram_address_re $1\main_sdram_address_re[0:0] - end - attribute \src "ls180.v:373.11-373.45" - process $proc$ls180.v:373$3001 - assign { } { } - assign $1\main_sdram_baddress_storage[1:0] 2'00 - sync always - sync init - update \main_sdram_baddress_storage $1\main_sdram_baddress_storage[1:0] - end - attribute \src "ls180.v:3730.1-3737.4" - process $proc$ls180.v:3730$232 + attribute \src "ls180.v:3759.1-3766.4" + process $proc$ls180.v:3759$296 assign { } { } assign $0\main_sdram_bankmachine3_auto_precharge[0:0] 1'0 - attribute \src "ls180.v:3732.2-3736.5" - switch $and$ls180.v:3732$233_Y - attribute \src "ls180.v:3732.6-3732.115" + attribute \src "ls180.v:3761.2-3765.5" + switch $and$ls180.v:3761$297_Y + attribute \src "ls180.v:3761.6-3761.115" case 1'1 - attribute \src "ls180.v:3733.3-3735.6" - switch $ne$ls180.v:3733$234_Y - attribute \src "ls180.v:3733.7-3733.143" + attribute \src "ls180.v:3762.3-3764.6" + switch $ne$ls180.v:3762$298_Y + attribute \src "ls180.v:3762.7-3762.143" case 1'1 - assign $0\main_sdram_bankmachine3_auto_precharge[0:0] $eq$ls180.v:3734$235_Y + assign $0\main_sdram_bankmachine3_auto_precharge[0:0] $eq$ls180.v:3763$299_Y case end case @@ -271320,48 +272668,24 @@ module \ls180 sync always update \main_sdram_bankmachine3_auto_precharge $0\main_sdram_bankmachine3_auto_precharge[0:0] end - attribute \src "ls180.v:374.5-374.34" - process $proc$ls180.v:374$3002 - assign { } { } - assign $1\main_sdram_baddress_re[0:0] 1'0 - sync always - sync init - update \main_sdram_baddress_re $1\main_sdram_baddress_re[0:0] - end - attribute \src "ls180.v:375.12-375.45" - process $proc$ls180.v:375$3003 - assign { } { } - assign $1\main_sdram_wrdata_storage[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdram_wrdata_storage $1\main_sdram_wrdata_storage[15:0] - end - attribute \src "ls180.v:3752.1-3759.4" - process $proc$ls180.v:3752$236 + attribute \src "ls180.v:3781.1-3788.4" + process $proc$ls180.v:3781$300 assign { } { } assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 - attribute \src "ls180.v:3754.2-3758.5" + attribute \src "ls180.v:3783.2-3787.5" switch \main_sdram_bankmachine3_cmd_buffer_lookahead_replace - attribute \src "ls180.v:3754.6-3754.58" + attribute \src "ls180.v:3783.6-3783.58" case 1'1 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3755$237_Y - attribute \src "ls180.v:3756.6-3756.10" + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3784$301_Y + attribute \src "ls180.v:3785.6-3785.10" case assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine3_cmd_buffer_lookahead_produce end sync always update \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] end - attribute \src "ls180.v:376.5-376.32" - process $proc$ls180.v:376$3004 - assign { } { } - assign $1\main_sdram_wrdata_re[0:0] 1'0 - sync always - sync init - update \main_sdram_wrdata_re $1\main_sdram_wrdata_re[0:0] - end - attribute \src "ls180.v:3768.1-3861.4" - process $proc$ls180.v:3768$245 + attribute \src "ls180.v:3797.1-3890.4" + process $proc$ls180.v:3797$309 assign { } { } assign { } { } assign { } { } @@ -271376,37 +272700,37 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'0 - assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'0 - assign $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'0 - assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'0 - assign $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'0 - assign $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'0 assign $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'0 assign $0\main_sdram_bankmachine3_req_wdata_ready[0:0] 1'0 + assign $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'0 assign $0\main_sdram_bankmachine3_req_rdata_valid[0:0] 1'0 assign $0\main_sdram_bankmachine3_refresh_gnt[0:0] 1'0 assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'0 assign $0\main_sdram_bankmachine3_row_open[0:0] 1'0 assign $0\main_sdram_bankmachine3_row_close[0:0] 1'0 + assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'0 + assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'0 assign { } { } + assign $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'0 + assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'0 + assign $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'0 assign $0\builder_bankmachine3_next_state[2:0] \builder_bankmachine3_state - attribute \src "ls180.v:3784.2-3860.9" + attribute \src "ls180.v:3813.2-3889.9" switch \builder_bankmachine3_state attribute \src "ls180.v:0.0-0.0" case 3'001 assign $0\main_sdram_bankmachine3_row_close[0:0] 1'1 - attribute \src "ls180.v:3786.4-3794.7" - switch $and$ls180.v:3786$246_Y - attribute \src "ls180.v:3786.8-3786.87" + attribute \src "ls180.v:3815.4-3823.7" + switch $and$ls180.v:3815$310_Y + attribute \src "ls180.v:3815.8-3815.87" case 1'1 assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'1 assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'1 assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'1 assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3788.5-3790.8" + attribute \src "ls180.v:3817.5-3819.8" switch \main_sdram_bankmachine3_cmd_ready - attribute \src "ls180.v:3788.9-3788.42" + attribute \src "ls180.v:3817.9-3817.42" case 1'1 assign $0\builder_bankmachine3_next_state[2:0] 3'101 case @@ -271416,27 +272740,27 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 3'010 assign $0\main_sdram_bankmachine3_row_close[0:0] 1'1 - attribute \src "ls180.v:3798.4-3800.7" - switch $and$ls180.v:3798$247_Y - attribute \src "ls180.v:3798.8-3798.87" + attribute \src "ls180.v:3827.4-3829.7" + switch $and$ls180.v:3827$311_Y + attribute \src "ls180.v:3827.8-3827.87" case 1'1 assign $0\builder_bankmachine3_next_state[2:0] 3'101 case end attribute \src "ls180.v:0.0-0.0" case 3'011 - attribute \src "ls180.v:3804.4-3813.7" + attribute \src "ls180.v:3833.4-3842.7" switch \main_sdram_bankmachine3_trccon_ready - attribute \src "ls180.v:3804.8-3804.44" + attribute \src "ls180.v:3833.8-3833.44" case 1'1 assign $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'1 assign $0\main_sdram_bankmachine3_row_open[0:0] 1'1 assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'1 assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1 assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'1 - attribute \src "ls180.v:3809.5-3811.8" + attribute \src "ls180.v:3838.5-3840.8" switch \main_sdram_bankmachine3_cmd_ready - attribute \src "ls180.v:3809.9-3809.42" + attribute \src "ls180.v:3838.9-3838.42" case 1'1 assign $0\builder_bankmachine3_next_state[2:0] 3'110 case @@ -271447,16 +272771,16 @@ module \ls180 case 3'100 assign $0\main_sdram_bankmachine3_row_close[0:0] 1'1 assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3816.4-3818.7" + attribute \src "ls180.v:3845.4-3847.7" switch \main_sdram_bankmachine3_twtpcon_ready - attribute \src "ls180.v:3816.8-3816.45" + attribute \src "ls180.v:3845.8-3845.45" case 1'1 assign $0\main_sdram_bankmachine3_refresh_gnt[0:0] 1'1 case end - attribute \src "ls180.v:3821.4-3823.7" - switch $not$ls180.v:3821$248_Y - attribute \src "ls180.v:3821.8-3821.46" + attribute \src "ls180.v:3850.4-3852.7" + switch $not$ls180.v:3850$312_Y + attribute \src "ls180.v:3850.8-3850.46" case 1'1 assign $0\builder_bankmachine3_next_state[2:0] 3'000 case @@ -271469,51 +272793,51 @@ module \ls180 assign $0\builder_bankmachine3_next_state[2:0] 3'000 attribute \src "ls180.v:0.0-0.0" case - attribute \src "ls180.v:3832.4-3858.7" + attribute \src "ls180.v:3861.4-3887.7" switch \main_sdram_bankmachine3_refresh_req - attribute \src "ls180.v:3832.8-3832.43" + attribute \src "ls180.v:3861.8-3861.43" case 1'1 assign $0\builder_bankmachine3_next_state[2:0] 3'100 - attribute \src "ls180.v:3834.8-3834.12" + attribute \src "ls180.v:3863.8-3863.12" case - attribute \src "ls180.v:3835.5-3857.8" + attribute \src "ls180.v:3864.5-3886.8" switch \main_sdram_bankmachine3_cmd_buffer_source_valid - attribute \src "ls180.v:3835.9-3835.56" + attribute \src "ls180.v:3864.9-3864.56" case 1'1 - attribute \src "ls180.v:3836.6-3856.9" + attribute \src "ls180.v:3865.6-3885.9" switch \main_sdram_bankmachine3_row_opened - attribute \src "ls180.v:3836.10-3836.44" + attribute \src "ls180.v:3865.10-3865.44" case 1'1 - attribute \src "ls180.v:3837.7-3853.10" + attribute \src "ls180.v:3866.7-3882.10" switch \main_sdram_bankmachine3_row_hit - attribute \src "ls180.v:3837.11-3837.42" + attribute \src "ls180.v:3866.11-3866.42" case 1'1 assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'1 assign $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'1 - attribute \src "ls180.v:3839.8-3846.11" + attribute \src "ls180.v:3868.8-3875.11" switch \main_sdram_bankmachine3_cmd_buffer_source_payload_we - attribute \src "ls180.v:3839.12-3839.64" + attribute \src "ls180.v:3868.12-3868.64" case 1'1 assign $0\main_sdram_bankmachine3_req_wdata_ready[0:0] \main_sdram_bankmachine3_cmd_ready assign $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'1 assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'1 - attribute \src "ls180.v:3843.12-3843.16" + attribute \src "ls180.v:3872.12-3872.16" case assign $0\main_sdram_bankmachine3_req_rdata_valid[0:0] \main_sdram_bankmachine3_cmd_ready assign $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'1 end - attribute \src "ls180.v:3848.8-3850.11" - switch $and$ls180.v:3848$249_Y - attribute \src "ls180.v:3848.12-3848.88" + attribute \src "ls180.v:3877.8-3879.11" + switch $and$ls180.v:3877$313_Y + attribute \src "ls180.v:3877.12-3877.88" case 1'1 assign $0\builder_bankmachine3_next_state[2:0] 3'010 case end - attribute \src "ls180.v:3851.11-3851.15" + attribute \src "ls180.v:3880.11-3880.15" case assign $0\builder_bankmachine3_next_state[2:0] 3'001 end - attribute \src "ls180.v:3854.10-3854.14" + attribute \src "ls180.v:3883.10-3883.14" case assign $0\builder_bankmachine3_next_state[2:0] 3'011 end @@ -271537,32 +272861,24 @@ module \ls180 update \main_sdram_bankmachine3_row_col_n_addr_sel $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] update \builder_bankmachine3_next_state $0\builder_bankmachine3_next_state[2:0] end - attribute \src "ls180.v:377.12-377.37" - process $proc$ls180.v:377$3005 + attribute \src "ls180.v:3910.1-3916.4" + process $proc$ls180.v:3910$352 assign { } { } - assign $1\main_sdram_status[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdram_status $1\main_sdram_status[15:0] - end - attribute \src "ls180.v:3881.1-3887.4" - process $proc$ls180.v:3881$288 assign { } { } - assign { } { } - assign $0\main_sdram_choose_cmd_valids[3:0] [0] $and$ls180.v:3883$301_Y - assign $0\main_sdram_choose_cmd_valids[3:0] [1] $and$ls180.v:3884$314_Y - assign $0\main_sdram_choose_cmd_valids[3:0] [2] $and$ls180.v:3885$327_Y - assign $0\main_sdram_choose_cmd_valids[3:0] [3] $and$ls180.v:3886$340_Y + assign $0\main_sdram_choose_cmd_valids[3:0] [0] $and$ls180.v:3912$365_Y + assign $0\main_sdram_choose_cmd_valids[3:0] [1] $and$ls180.v:3913$378_Y + assign $0\main_sdram_choose_cmd_valids[3:0] [2] $and$ls180.v:3914$391_Y + assign $0\main_sdram_choose_cmd_valids[3:0] [3] $and$ls180.v:3915$404_Y sync always update \main_sdram_choose_cmd_valids $0\main_sdram_choose_cmd_valids[3:0] end - attribute \src "ls180.v:3895.1-3900.4" - process $proc$ls180.v:3895$341 + attribute \src "ls180.v:3924.1-3929.4" + process $proc$ls180.v:3924$405 assign { } { } assign $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] 1'0 - attribute \src "ls180.v:3897.2-3899.5" + attribute \src "ls180.v:3926.2-3928.5" switch \main_sdram_choose_cmd_cmd_valid - attribute \src "ls180.v:3897.6-3897.37" + attribute \src "ls180.v:3926.6-3926.37" case 1'1 assign $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] \builder_comb_t_array_muxed0 case @@ -271570,13 +272886,13 @@ module \ls180 sync always update \main_sdram_choose_cmd_cmd_payload_cas $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] end - attribute \src "ls180.v:3901.1-3906.4" - process $proc$ls180.v:3901$342 + attribute \src "ls180.v:3930.1-3935.4" + process $proc$ls180.v:3930$406 assign { } { } assign $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] 1'0 - attribute \src "ls180.v:3903.2-3905.5" + attribute \src "ls180.v:3932.2-3934.5" switch \main_sdram_choose_cmd_cmd_valid - attribute \src "ls180.v:3903.6-3903.37" + attribute \src "ls180.v:3932.6-3932.37" case 1'1 assign $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] \builder_comb_t_array_muxed1 case @@ -271584,13 +272900,13 @@ module \ls180 sync always update \main_sdram_choose_cmd_cmd_payload_ras $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] end - attribute \src "ls180.v:3907.1-3912.4" - process $proc$ls180.v:3907$343 + attribute \src "ls180.v:3936.1-3941.4" + process $proc$ls180.v:3936$407 assign { } { } assign $0\main_sdram_choose_cmd_cmd_payload_we[0:0] 1'0 - attribute \src "ls180.v:3909.2-3911.5" + attribute \src "ls180.v:3938.2-3940.5" switch \main_sdram_choose_cmd_cmd_valid - attribute \src "ls180.v:3909.6-3909.37" + attribute \src "ls180.v:3938.6-3938.37" case 1'1 assign $0\main_sdram_choose_cmd_cmd_payload_we[0:0] \builder_comb_t_array_muxed2 case @@ -271598,24 +272914,40 @@ module \ls180 sync always update \main_sdram_choose_cmd_cmd_payload_we $0\main_sdram_choose_cmd_cmd_payload_we[0:0] end - attribute \src "ls180.v:3914.1-3920.4" - process $proc$ls180.v:3914$346 + attribute \src "ls180.v:394.12-394.46" + process $proc$ls180.v:394$3126 assign { } { } + assign $1\main_sdram_interface_wdata[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdram_interface_wdata $1\main_sdram_interface_wdata[15:0] + end + attribute \src "ls180.v:3943.1-3949.4" + process $proc$ls180.v:3943$410 assign { } { } - assign $0\main_sdram_choose_req_valids[3:0] [0] $and$ls180.v:3916$359_Y - assign $0\main_sdram_choose_req_valids[3:0] [1] $and$ls180.v:3917$372_Y - assign $0\main_sdram_choose_req_valids[3:0] [2] $and$ls180.v:3918$385_Y - assign $0\main_sdram_choose_req_valids[3:0] [3] $and$ls180.v:3919$398_Y + assign { } { } + assign $0\main_sdram_choose_req_valids[3:0] [0] $and$ls180.v:3945$423_Y + assign $0\main_sdram_choose_req_valids[3:0] [1] $and$ls180.v:3946$436_Y + assign $0\main_sdram_choose_req_valids[3:0] [2] $and$ls180.v:3947$449_Y + assign $0\main_sdram_choose_req_valids[3:0] [3] $and$ls180.v:3948$462_Y sync always update \main_sdram_choose_req_valids $0\main_sdram_choose_req_valids[3:0] end - attribute \src "ls180.v:3928.1-3933.4" - process $proc$ls180.v:3928$399 + attribute \src "ls180.v:395.11-395.47" + process $proc$ls180.v:395$3127 + assign { } { } + assign $1\main_sdram_interface_wdata_we[1:0] 2'00 + sync always + sync init + update \main_sdram_interface_wdata_we $1\main_sdram_interface_wdata_we[1:0] + end + attribute \src "ls180.v:3957.1-3962.4" + process $proc$ls180.v:3957$463 assign { } { } assign $0\main_sdram_choose_req_cmd_payload_cas[0:0] 1'0 - attribute \src "ls180.v:3930.2-3932.5" + attribute \src "ls180.v:3959.2-3961.5" switch \main_sdram_choose_req_cmd_valid - attribute \src "ls180.v:3930.6-3930.37" + attribute \src "ls180.v:3959.6-3959.37" case 1'1 assign $0\main_sdram_choose_req_cmd_payload_cas[0:0] \builder_comb_t_array_muxed3 case @@ -271623,13 +272955,13 @@ module \ls180 sync always update \main_sdram_choose_req_cmd_payload_cas $0\main_sdram_choose_req_cmd_payload_cas[0:0] end - attribute \src "ls180.v:3934.1-3939.4" - process $proc$ls180.v:3934$400 + attribute \src "ls180.v:3963.1-3968.4" + process $proc$ls180.v:3963$464 assign { } { } assign $0\main_sdram_choose_req_cmd_payload_ras[0:0] 1'0 - attribute \src "ls180.v:3936.2-3938.5" + attribute \src "ls180.v:3965.2-3967.5" switch \main_sdram_choose_req_cmd_valid - attribute \src "ls180.v:3936.6-3936.37" + attribute \src "ls180.v:3965.6-3965.37" case 1'1 assign $0\main_sdram_choose_req_cmd_payload_ras[0:0] \builder_comb_t_array_muxed4 case @@ -271637,13 +272969,13 @@ module \ls180 sync always update \main_sdram_choose_req_cmd_payload_ras $0\main_sdram_choose_req_cmd_payload_ras[0:0] end - attribute \src "ls180.v:3940.1-3945.4" - process $proc$ls180.v:3940$401 + attribute \src "ls180.v:3969.1-3974.4" + process $proc$ls180.v:3969$465 assign { } { } assign $0\main_sdram_choose_req_cmd_payload_we[0:0] 1'0 - attribute \src "ls180.v:3942.2-3944.5" + attribute \src "ls180.v:3971.2-3973.5" switch \main_sdram_choose_req_cmd_valid - attribute \src "ls180.v:3942.6-3942.37" + attribute \src "ls180.v:3971.6-3971.37" case 1'1 assign $0\main_sdram_choose_req_cmd_payload_we[0:0] \builder_comb_t_array_muxed5 case @@ -271651,20 +272983,28 @@ module \ls180 sync always update \main_sdram_choose_req_cmd_payload_we $0\main_sdram_choose_req_cmd_payload_we[0:0] end - attribute \src "ls180.v:3946.1-3954.4" - process $proc$ls180.v:3946$402 + attribute \src "ls180.v:397.12-397.45" + process $proc$ls180.v:397$3128 + assign { } { } + assign $1\main_sdram_dfi_p0_address[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_dfi_p0_address $1\main_sdram_dfi_p0_address[12:0] + end + attribute \src "ls180.v:3975.1-3983.4" + process $proc$ls180.v:3975$466 assign { } { } assign $0\main_sdram_bankmachine0_cmd_ready[0:0] 1'0 - attribute \src "ls180.v:3948.2-3950.5" - switch $and$ls180.v:3948$405_Y - attribute \src "ls180.v:3948.6-3948.115" + attribute \src "ls180.v:3977.2-3979.5" + switch $and$ls180.v:3977$469_Y + attribute \src "ls180.v:3977.6-3977.115" case 1'1 assign $0\main_sdram_bankmachine0_cmd_ready[0:0] 1'1 case end - attribute \src "ls180.v:3951.2-3953.5" - switch $and$ls180.v:3951$408_Y - attribute \src "ls180.v:3951.6-3951.115" + attribute \src "ls180.v:3980.2-3982.5" + switch $and$ls180.v:3980$472_Y + attribute \src "ls180.v:3980.6-3980.115" case 1'1 assign $0\main_sdram_bankmachine0_cmd_ready[0:0] 1'1 case @@ -271672,20 +273012,28 @@ module \ls180 sync always update \main_sdram_bankmachine0_cmd_ready $0\main_sdram_bankmachine0_cmd_ready[0:0] end - attribute \src "ls180.v:3955.1-3963.4" - process $proc$ls180.v:3955$409 + attribute \src "ls180.v:398.11-398.40" + process $proc$ls180.v:398$3129 + assign { } { } + assign $1\main_sdram_dfi_p0_bank[1:0] 2'00 + sync always + sync init + update \main_sdram_dfi_p0_bank $1\main_sdram_dfi_p0_bank[1:0] + end + attribute \src "ls180.v:3984.1-3992.4" + process $proc$ls180.v:3984$473 assign { } { } assign $0\main_sdram_bankmachine1_cmd_ready[0:0] 1'0 - attribute \src "ls180.v:3957.2-3959.5" - switch $and$ls180.v:3957$412_Y - attribute \src "ls180.v:3957.6-3957.115" + attribute \src "ls180.v:3986.2-3988.5" + switch $and$ls180.v:3986$476_Y + attribute \src "ls180.v:3986.6-3986.115" case 1'1 assign $0\main_sdram_bankmachine1_cmd_ready[0:0] 1'1 case end - attribute \src "ls180.v:3960.2-3962.5" - switch $and$ls180.v:3960$415_Y - attribute \src "ls180.v:3960.6-3960.115" + attribute \src "ls180.v:3989.2-3991.5" + switch $and$ls180.v:3989$479_Y + attribute \src "ls180.v:3989.6-3989.115" case 1'1 assign $0\main_sdram_bankmachine1_cmd_ready[0:0] 1'1 case @@ -271693,20 +273041,28 @@ module \ls180 sync always update \main_sdram_bankmachine1_cmd_ready $0\main_sdram_bankmachine1_cmd_ready[0:0] end - attribute \src "ls180.v:3964.1-3972.4" - process $proc$ls180.v:3964$416 + attribute \src "ls180.v:399.5-399.35" + process $proc$ls180.v:399$3130 + assign { } { } + assign $1\main_sdram_dfi_p0_cas_n[0:0] 1'1 + sync always + sync init + update \main_sdram_dfi_p0_cas_n $1\main_sdram_dfi_p0_cas_n[0:0] + end + attribute \src "ls180.v:3993.1-4001.4" + process $proc$ls180.v:3993$480 assign { } { } assign $0\main_sdram_bankmachine2_cmd_ready[0:0] 1'0 - attribute \src "ls180.v:3966.2-3968.5" - switch $and$ls180.v:3966$419_Y - attribute \src "ls180.v:3966.6-3966.115" + attribute \src "ls180.v:3995.2-3997.5" + switch $and$ls180.v:3995$483_Y + attribute \src "ls180.v:3995.6-3995.115" case 1'1 assign $0\main_sdram_bankmachine2_cmd_ready[0:0] 1'1 case end - attribute \src "ls180.v:3969.2-3971.5" - switch $and$ls180.v:3969$422_Y - attribute \src "ls180.v:3969.6-3969.115" + attribute \src "ls180.v:3998.2-4000.5" + switch $and$ls180.v:3998$486_Y + attribute \src "ls180.v:3998.6-3998.115" case 1'1 assign $0\main_sdram_bankmachine2_cmd_ready[0:0] 1'1 case @@ -271714,20 +273070,28 @@ module \ls180 sync always update \main_sdram_bankmachine2_cmd_ready $0\main_sdram_bankmachine2_cmd_ready[0:0] end - attribute \src "ls180.v:3973.1-3981.4" - process $proc$ls180.v:3973$423 + attribute \src "ls180.v:400.5-400.34" + process $proc$ls180.v:400$3131 + assign { } { } + assign $1\main_sdram_dfi_p0_cs_n[0:0] 1'1 + sync always + sync init + update \main_sdram_dfi_p0_cs_n $1\main_sdram_dfi_p0_cs_n[0:0] + end + attribute \src "ls180.v:4002.1-4010.4" + process $proc$ls180.v:4002$487 assign { } { } assign $0\main_sdram_bankmachine3_cmd_ready[0:0] 1'0 - attribute \src "ls180.v:3975.2-3977.5" - switch $and$ls180.v:3975$426_Y - attribute \src "ls180.v:3975.6-3975.115" + attribute \src "ls180.v:4004.2-4006.5" + switch $and$ls180.v:4004$490_Y + attribute \src "ls180.v:4004.6-4004.115" case 1'1 assign $0\main_sdram_bankmachine3_cmd_ready[0:0] 1'1 case end - attribute \src "ls180.v:3978.2-3980.5" - switch $and$ls180.v:3978$429_Y - attribute \src "ls180.v:3978.6-3978.115" + attribute \src "ls180.v:4007.2-4009.5" + switch $and$ls180.v:4007$493_Y + attribute \src "ls180.v:4007.6-4007.115" case 1'1 assign $0\main_sdram_bankmachine3_cmd_ready[0:0] 1'1 case @@ -271735,8 +273099,16 @@ module \ls180 sync always update \main_sdram_bankmachine3_cmd_ready $0\main_sdram_bankmachine3_cmd_ready[0:0] end - attribute \src "ls180.v:3986.1-4058.4" - process $proc$ls180.v:3986$432 + attribute \src "ls180.v:401.5-401.35" + process $proc$ls180.v:401$3132 + assign { } { } + assign $1\main_sdram_dfi_p0_ras_n[0:0] 1'1 + sync always + sync init + update \main_sdram_dfi_p0_ras_n $1\main_sdram_dfi_p0_ras_n[0:0] + end + attribute \src "ls180.v:4015.1-4087.4" + process $proc$ls180.v:4015$496 assign { } { } assign { } { } assign { } { } @@ -271753,40 +273125,40 @@ module \ls180 assign { } { } assign $0\main_sdram_steerer_sel[1:0] 2'00 assign $0\main_sdram_choose_req_cmd_ready[0:0] 1'0 - assign { } { } assign $0\main_sdram_en0[0:0] 1'0 + assign { } { } assign $0\main_sdram_choose_req_want_activates[0:0] \main_sdram_ras_allowed assign $0\builder_multiplexer_next_state[2:0] \builder_multiplexer_state - attribute \src "ls180.v:3998.2-4057.9" + attribute \src "ls180.v:4027.2-4086.9" switch \builder_multiplexer_state attribute \src "ls180.v:0.0-0.0" case 3'001 assign $0\main_sdram_en1[0:0] 1'1 assign $0\main_sdram_choose_req_want_writes[0:0] 1'1 assign $0\main_sdram_steerer_sel[1:0] 2'10 - attribute \src "ls180.v:4002.4-4008.7" + attribute \src "ls180.v:4031.4-4037.7" switch 1'1 - attribute \src "ls180.v:4002.8-4002.12" + attribute \src "ls180.v:4031.8-4031.12" case 1'1 - assign $0\main_sdram_choose_req_cmd_ready[0:0] $and$ls180.v:4003$439_Y + assign $0\main_sdram_choose_req_cmd_ready[0:0] $and$ls180.v:4032$503_Y case end - attribute \src "ls180.v:4010.4-4014.7" + attribute \src "ls180.v:4039.4-4043.7" switch \main_sdram_read_available - attribute \src "ls180.v:4010.8-4010.33" + attribute \src "ls180.v:4039.8-4039.33" case 1'1 - attribute \src "ls180.v:4011.5-4013.8" - switch $or$ls180.v:4011$441_Y - attribute \src "ls180.v:4011.9-4011.63" + attribute \src "ls180.v:4040.5-4042.8" + switch $or$ls180.v:4040$505_Y + attribute \src "ls180.v:4040.9-4040.63" case 1'1 assign $0\builder_multiplexer_next_state[2:0] 3'011 case end case end - attribute \src "ls180.v:4015.4-4017.7" + attribute \src "ls180.v:4044.4-4046.7" switch \main_sdram_go_to_refresh - attribute \src "ls180.v:4015.8-4015.32" + attribute \src "ls180.v:4044.8-4044.32" case 1'1 assign $0\builder_multiplexer_next_state[2:0] 3'010 case @@ -271795,18 +273167,18 @@ module \ls180 case 3'010 assign $0\main_sdram_steerer_sel[1:0] 2'11 assign $0\main_sdram_cmd_ready[0:0] 1'1 - attribute \src "ls180.v:4022.4-4024.7" + attribute \src "ls180.v:4051.4-4053.7" switch \main_sdram_cmd_last - attribute \src "ls180.v:4022.8-4022.27" + attribute \src "ls180.v:4051.8-4051.27" case 1'1 assign $0\builder_multiplexer_next_state[2:0] 3'000 case end attribute \src "ls180.v:0.0-0.0" case 3'011 - attribute \src "ls180.v:4027.4-4029.7" + attribute \src "ls180.v:4056.4-4058.7" switch \main_sdram_twtrcon_ready - attribute \src "ls180.v:4027.8-4027.32" + attribute \src "ls180.v:4056.8-4056.32" case 1'1 assign $0\builder_multiplexer_next_state[2:0] 3'000 case @@ -271822,29 +273194,29 @@ module \ls180 assign $0\main_sdram_en0[0:0] 1'1 assign $0\main_sdram_choose_req_want_reads[0:0] 1'1 assign $0\main_sdram_steerer_sel[1:0] 2'10 - attribute \src "ls180.v:4040.4-4046.7" + attribute \src "ls180.v:4069.4-4075.7" switch 1'1 - attribute \src "ls180.v:4040.8-4040.12" + attribute \src "ls180.v:4069.8-4069.12" case 1'1 - assign $0\main_sdram_choose_req_cmd_ready[0:0] $and$ls180.v:4041$448_Y + assign $0\main_sdram_choose_req_cmd_ready[0:0] $and$ls180.v:4070$512_Y case end - attribute \src "ls180.v:4048.4-4052.7" + attribute \src "ls180.v:4077.4-4081.7" switch \main_sdram_write_available - attribute \src "ls180.v:4048.8-4048.34" + attribute \src "ls180.v:4077.8-4077.34" case 1'1 - attribute \src "ls180.v:4049.5-4051.8" - switch $or$ls180.v:4049$450_Y - attribute \src "ls180.v:4049.9-4049.62" + attribute \src "ls180.v:4078.5-4080.8" + switch $or$ls180.v:4078$514_Y + attribute \src "ls180.v:4078.9-4078.62" case 1'1 assign $0\builder_multiplexer_next_state[2:0] 3'100 case end case end - attribute \src "ls180.v:4053.4-4055.7" + attribute \src "ls180.v:4082.4-4084.7" switch \main_sdram_go_to_refresh - attribute \src "ls180.v:4053.8-4053.32" + attribute \src "ls180.v:4082.8-4082.32" case 1'1 assign $0\builder_multiplexer_next_state[2:0] 3'010 case @@ -271861,29 +273233,45 @@ module \ls180 update \main_sdram_en1 $0\main_sdram_en1[0:0] update \builder_multiplexer_next_state $0\builder_multiplexer_next_state[2:0] end - attribute \src "ls180.v:407.12-407.46" - process $proc$ls180.v:407$3006 + attribute \src "ls180.v:402.5-402.34" + process $proc$ls180.v:402$3133 assign { } { } - assign $1\main_sdram_interface_wdata[15:0] 16'0000000000000000 + assign $1\main_sdram_dfi_p0_we_n[0:0] 1'1 sync always sync init - update \main_sdram_interface_wdata $1\main_sdram_interface_wdata[15:0] + update \main_sdram_dfi_p0_we_n $1\main_sdram_dfi_p0_we_n[0:0] end - attribute \src "ls180.v:408.11-408.47" - process $proc$ls180.v:408$3007 + attribute \src "ls180.v:406.5-406.35" + process $proc$ls180.v:406$3134 assign { } { } - assign $1\main_sdram_interface_wdata_we[1:0] 2'00 + assign $0\main_sdram_dfi_p0_act_n[0:0] 1'1 sync always + update \main_sdram_dfi_p0_act_n $0\main_sdram_dfi_p0_act_n[0:0] sync init - update \main_sdram_interface_wdata_we $1\main_sdram_interface_wdata_we[1:0] end - attribute \src "ls180.v:4082.1-4095.4" - process $proc$ls180.v:4082$579 + attribute \src "ls180.v:408.5-408.39" + process $proc$ls180.v:408$3135 + assign { } { } + assign $1\main_sdram_dfi_p0_wrdata_en[0:0] 1'0 + sync always + sync init + update \main_sdram_dfi_p0_wrdata_en $1\main_sdram_dfi_p0_wrdata_en[0:0] + end + attribute \src "ls180.v:410.5-410.39" + process $proc$ls180.v:410$3136 + assign { } { } + assign $1\main_sdram_dfi_p0_rddata_en[0:0] 1'0 + sync always + sync init + update \main_sdram_dfi_p0_rddata_en $1\main_sdram_dfi_p0_rddata_en[0:0] + end + attribute \src "ls180.v:4111.1-4124.4" + process $proc$ls180.v:4111$643 assign { } { } assign { } { } assign $0\main_sdram_interface_wdata[15:0] 16'0000000000000000 assign $0\main_sdram_interface_wdata_we[1:0] 2'00 - attribute \src "ls180.v:4085.2-4094.9" + attribute \src "ls180.v:4114.2-4123.9" switch \builder_new_master_wdata_ready attribute \src "ls180.v:0.0-0.0" case 1'1 @@ -271898,19 +273286,19 @@ module \ls180 update \main_sdram_interface_wdata $0\main_sdram_interface_wdata[15:0] update \main_sdram_interface_wdata_we $0\main_sdram_interface_wdata_we[1:0] end - attribute \src "ls180.v:410.12-410.45" - process $proc$ls180.v:410$3008 + attribute \src "ls180.v:413.5-413.32" + process $proc$ls180.v:413$3137 assign { } { } - assign $1\main_sdram_dfi_p0_address[12:0] 13'0000000000000 + assign $1\main_sdram_cmd_valid[0:0] 1'0 sync always sync init - update \main_sdram_dfi_p0_address $1\main_sdram_dfi_p0_address[12:0] + update \main_sdram_cmd_valid $1\main_sdram_cmd_valid[0:0] end - attribute \src "ls180.v:4102.1-4112.4" - process $proc$ls180.v:4102$581 + attribute \src "ls180.v:4131.1-4141.4" + process $proc$ls180.v:4131$645 assign { } { } assign $0\main_litedram_wb_dat_w[15:0] 16'0000000000000000 - attribute \src "ls180.v:4104.2-4111.9" + attribute \src "ls180.v:4133.2-4140.9" switch \main_converter_counter attribute \src "ls180.v:0.0-0.0" case 1'0 @@ -271923,17 +273311,16 @@ module \ls180 sync always update \main_litedram_wb_dat_w $0\main_litedram_wb_dat_w[15:0] end - attribute \src "ls180.v:411.11-411.40" - process $proc$ls180.v:411$3009 + attribute \src "ls180.v:414.5-414.32" + process $proc$ls180.v:414$3138 assign { } { } - assign $1\main_sdram_dfi_p0_bank[1:0] 2'00 + assign $1\main_sdram_cmd_ready[0:0] 1'0 sync always sync init - update \main_sdram_dfi_p0_bank $1\main_sdram_dfi_p0_bank[1:0] + update \main_sdram_cmd_ready $1\main_sdram_cmd_ready[0:0] end - attribute \src "ls180.v:4114.1-4160.4" - process $proc$ls180.v:4114$582 - assign { } { } + attribute \src "ls180.v:4143.1-4189.4" + process $proc$ls180.v:4143$646 assign { } { } assign { } { } assign { } { } @@ -271945,21 +273332,22 @@ module \ls180 assign { } { } assign { } { } assign $0\main_converter_counter_converter_next_value[0:0] 1'0 - assign $0\main_litedram_wb_adr[29:0] 30'000000000000000000000000000000 assign $0\main_converter_counter_converter_next_value_ce[0:0] 1'0 - assign $0\main_litedram_wb_sel[1:0] 2'00 - assign $0\main_litedram_wb_cyc[0:0] 1'0 - assign $0\main_litedram_wb_stb[0:0] 1'0 - assign $0\main_wb_sdram_ack[0:0] 1'0 assign $0\main_litedram_wb_we[0:0] 1'0 + assign $0\main_litedram_wb_stb[0:0] 1'0 assign $0\main_converter_skip[0:0] 1'0 + assign $0\main_wb_sdram_ack[0:0] 1'0 + assign $0\main_litedram_wb_adr[29:0] 30'000000000000000000000000000000 + assign $0\main_litedram_wb_sel[1:0] 2'00 + assign $0\main_litedram_wb_cyc[0:0] 1'0 + assign { } { } assign $0\builder_converter_next_state[0:0] \builder_converter_state - attribute \src "ls180.v:4126.2-4159.9" + attribute \src "ls180.v:4155.2-4188.9" switch \builder_converter_state attribute \src "ls180.v:0.0-0.0" case 1'1 assign $0\main_litedram_wb_adr[29:0] { \main_wb_sdram_adr [28:0] \main_converter_counter } - attribute \src "ls180.v:4129.4-4136.11" + attribute \src "ls180.v:4158.4-4165.11" switch \main_converter_counter attribute \src "ls180.v:0.0-0.0" case 1'0 @@ -271969,23 +273357,23 @@ module \ls180 assign $0\main_litedram_wb_sel[1:0] \main_wb_sdram_sel [3:2] case end - attribute \src "ls180.v:4137.4-4150.7" - switch $and$ls180.v:4137$583_Y - attribute \src "ls180.v:4137.8-4137.47" + attribute \src "ls180.v:4166.4-4179.7" + switch $and$ls180.v:4166$647_Y + attribute \src "ls180.v:4166.8-4166.47" case 1'1 - assign $0\main_converter_skip[0:0] $eq$ls180.v:4138$584_Y + assign $0\main_converter_skip[0:0] $eq$ls180.v:4167$648_Y assign $0\main_litedram_wb_we[0:0] \main_wb_sdram_we - assign $0\main_litedram_wb_cyc[0:0] $not$ls180.v:4140$585_Y - assign $0\main_litedram_wb_stb[0:0] $not$ls180.v:4141$586_Y - attribute \src "ls180.v:4142.5-4149.8" - switch $or$ls180.v:4142$587_Y - attribute \src "ls180.v:4142.9-4142.53" + assign $0\main_litedram_wb_cyc[0:0] $not$ls180.v:4169$649_Y + assign $0\main_litedram_wb_stb[0:0] $not$ls180.v:4170$650_Y + attribute \src "ls180.v:4171.5-4178.8" + switch $or$ls180.v:4171$651_Y + attribute \src "ls180.v:4171.9-4171.53" case 1'1 - assign $0\main_converter_counter_converter_next_value[0:0] $add$ls180.v:4143$588_Y + assign $0\main_converter_counter_converter_next_value[0:0] $add$ls180.v:4172$652_Y assign $0\main_converter_counter_converter_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4145.6-4148.9" - switch $eq$ls180.v:4145$589_Y - attribute \src "ls180.v:4145.10-4145.42" + attribute \src "ls180.v:4174.6-4177.9" + switch $eq$ls180.v:4174$653_Y + attribute \src "ls180.v:4174.10-4174.42" case 1'1 assign $0\main_wb_sdram_ack[0:0] 1'1 assign $0\builder_converter_next_state[0:0] 1'0 @@ -271999,9 +273387,9 @@ module \ls180 case assign $0\main_converter_counter_converter_next_value[0:0] 1'0 assign $0\main_converter_counter_converter_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4155.4-4157.7" - switch $and$ls180.v:4155$590_Y - attribute \src "ls180.v:4155.8-4155.47" + attribute \src "ls180.v:4184.4-4186.7" + switch $and$ls180.v:4184$654_Y + attribute \src "ls180.v:4184.8-4184.47" case 1'1 assign $0\builder_converter_next_state[0:0] 1'1 case @@ -272019,53 +273407,77 @@ module \ls180 update \main_converter_counter_converter_next_value $0\main_converter_counter_converter_next_value[0:0] update \main_converter_counter_converter_next_value_ce $0\main_converter_counter_converter_next_value_ce[0:0] end - attribute \src "ls180.v:412.5-412.35" - process $proc$ls180.v:412$3010 + attribute \src "ls180.v:415.5-415.31" + process $proc$ls180.v:415$3139 assign { } { } - assign $1\main_sdram_dfi_p0_cas_n[0:0] 1'1 + assign $1\main_sdram_cmd_last[0:0] 1'0 sync always sync init - update \main_sdram_dfi_p0_cas_n $1\main_sdram_dfi_p0_cas_n[0:0] + update \main_sdram_cmd_last $1\main_sdram_cmd_last[0:0] end - attribute \src "ls180.v:413.5-413.34" - process $proc$ls180.v:413$3011 + attribute \src "ls180.v:416.12-416.44" + process $proc$ls180.v:416$3140 assign { } { } - assign $1\main_sdram_dfi_p0_cs_n[0:0] 1'1 + assign $1\main_sdram_cmd_payload_a[12:0] 13'0000000000000 sync always sync init - update \main_sdram_dfi_p0_cs_n $1\main_sdram_dfi_p0_cs_n[0:0] + update \main_sdram_cmd_payload_a $1\main_sdram_cmd_payload_a[12:0] end - attribute \src "ls180.v:414.5-414.35" - process $proc$ls180.v:414$3012 + attribute \src "ls180.v:417.11-417.43" + process $proc$ls180.v:417$3141 assign { } { } - assign $1\main_sdram_dfi_p0_ras_n[0:0] 1'1 + assign $1\main_sdram_cmd_payload_ba[1:0] 2'00 sync always sync init - update \main_sdram_dfi_p0_ras_n $1\main_sdram_dfi_p0_ras_n[0:0] + update \main_sdram_cmd_payload_ba $1\main_sdram_cmd_payload_ba[1:0] end - attribute \src "ls180.v:415.5-415.34" - process $proc$ls180.v:415$3013 + attribute \src "ls180.v:418.5-418.38" + process $proc$ls180.v:418$3142 assign { } { } - assign $1\main_sdram_dfi_p0_we_n[0:0] 1'1 + assign $1\main_sdram_cmd_payload_cas[0:0] 1'0 sync always sync init - update \main_sdram_dfi_p0_we_n $1\main_sdram_dfi_p0_we_n[0:0] + update \main_sdram_cmd_payload_cas $1\main_sdram_cmd_payload_cas[0:0] end - attribute \src "ls180.v:419.5-419.35" - process $proc$ls180.v:419$3014 + attribute \src "ls180.v:419.5-419.38" + process $proc$ls180.v:419$3143 assign { } { } - assign $0\main_sdram_dfi_p0_act_n[0:0] 1'1 + assign $1\main_sdram_cmd_payload_ras[0:0] 1'0 + sync always + sync init + update \main_sdram_cmd_payload_ras $1\main_sdram_cmd_payload_ras[0:0] + end + attribute \src "ls180.v:420.5-420.37" + process $proc$ls180.v:420$3144 + assign { } { } + assign $1\main_sdram_cmd_payload_we[0:0] 1'0 sync always - update \main_sdram_dfi_p0_act_n $0\main_sdram_dfi_p0_act_n[0:0] + sync init + update \main_sdram_cmd_payload_we $1\main_sdram_cmd_payload_we[0:0] + end + attribute \src "ls180.v:421.5-421.42" + process $proc$ls180.v:421$3145 + assign { } { } + assign $0\main_sdram_cmd_payload_is_read[0:0] 1'0 + sync always + update \main_sdram_cmd_payload_is_read $0\main_sdram_cmd_payload_is_read[0:0] + sync init + end + attribute \src "ls180.v:422.5-422.43" + process $proc$ls180.v:422$3146 + assign { } { } + assign $0\main_sdram_cmd_payload_is_write[0:0] 1'0 + sync always + update \main_sdram_cmd_payload_is_write $0\main_sdram_cmd_payload_is_write[0:0] sync init end - attribute \src "ls180.v:4205.1-4210.4" - process $proc$ls180.v:4205$622 + attribute \src "ls180.v:4234.1-4239.4" + process $proc$ls180.v:4234$686 assign { } { } assign $0\main_uart_tx_clear[0:0] 1'0 - attribute \src "ls180.v:4207.2-4209.5" - switch $and$ls180.v:4207$623_Y - attribute \src "ls180.v:4207.6-4207.79" + attribute \src "ls180.v:4236.2-4238.5" + switch $and$ls180.v:4236$687_Y + attribute \src "ls180.v:4236.6-4236.79" case 1'1 assign $0\main_uart_tx_clear[0:0] 1'1 case @@ -272073,16 +273485,8 @@ module \ls180 sync always update \main_uart_tx_clear $0\main_uart_tx_clear[0:0] end - attribute \src "ls180.v:421.5-421.39" - process $proc$ls180.v:421$3015 - assign { } { } - assign $1\main_sdram_dfi_p0_wrdata_en[0:0] 1'0 - sync always - sync init - update \main_sdram_dfi_p0_wrdata_en $1\main_sdram_dfi_p0_wrdata_en[0:0] - end - attribute \src "ls180.v:4211.1-4215.4" - process $proc$ls180.v:4211$624 + attribute \src "ls180.v:4240.1-4244.4" + process $proc$ls180.v:4240$688 assign { } { } assign { } { } assign $0\main_uart_eventmanager_status_w[1:0] [0] \main_uart_tx_status @@ -272090,13 +273494,13 @@ module \ls180 sync always update \main_uart_eventmanager_status_w $0\main_uart_eventmanager_status_w[1:0] end - attribute \src "ls180.v:4216.1-4221.4" - process $proc$ls180.v:4216$625 + attribute \src "ls180.v:4245.1-4250.4" + process $proc$ls180.v:4245$689 assign { } { } assign $0\main_uart_rx_clear[0:0] 1'0 - attribute \src "ls180.v:4218.2-4220.5" - switch $and$ls180.v:4218$626_Y - attribute \src "ls180.v:4218.6-4218.79" + attribute \src "ls180.v:4247.2-4249.5" + switch $and$ls180.v:4247$690_Y + attribute \src "ls180.v:4247.6-4247.79" case 1'1 assign $0\main_uart_rx_clear[0:0] 1'1 case @@ -272104,8 +273508,8 @@ module \ls180 sync always update \main_uart_rx_clear $0\main_uart_rx_clear[0:0] end - attribute \src "ls180.v:4222.1-4226.4" - process $proc$ls180.v:4222$627 + attribute \src "ls180.v:4251.1-4255.4" + process $proc$ls180.v:4251$691 assign { } { } assign { } { } assign $0\main_uart_eventmanager_pending_w[1:0] [0] \main_uart_tx_pending @@ -272113,116 +273517,118 @@ module \ls180 sync always update \main_uart_eventmanager_pending_w $0\main_uart_eventmanager_pending_w[1:0] end - attribute \src "ls180.v:423.5-423.39" - process $proc$ls180.v:423$3016 - assign { } { } - assign $1\main_sdram_dfi_p0_rddata_en[0:0] 1'0 - sync always - sync init - update \main_sdram_dfi_p0_rddata_en $1\main_sdram_dfi_p0_rddata_en[0:0] - end - attribute \src "ls180.v:4244.1-4251.4" - process $proc$ls180.v:4244$635 + attribute \src "ls180.v:4273.1-4280.4" + process $proc$ls180.v:4273$699 assign { } { } assign $0\main_uart_tx_fifo_wrport_adr[3:0] 4'0000 - attribute \src "ls180.v:4246.2-4250.5" + attribute \src "ls180.v:4275.2-4279.5" switch \main_uart_tx_fifo_replace - attribute \src "ls180.v:4246.6-4246.31" + attribute \src "ls180.v:4275.6-4275.31" case 1'1 - assign $0\main_uart_tx_fifo_wrport_adr[3:0] $sub$ls180.v:4247$636_Y - attribute \src "ls180.v:4248.6-4248.10" + assign $0\main_uart_tx_fifo_wrport_adr[3:0] $sub$ls180.v:4276$700_Y + attribute \src "ls180.v:4277.6-4277.10" case assign $0\main_uart_tx_fifo_wrport_adr[3:0] \main_uart_tx_fifo_produce end sync always update \main_uart_tx_fifo_wrport_adr $0\main_uart_tx_fifo_wrport_adr[3:0] end - attribute \src "ls180.v:426.5-426.32" - process $proc$ls180.v:426$3017 + attribute \src "ls180.v:428.11-428.44" + process $proc$ls180.v:428$3147 assign { } { } - assign $1\main_sdram_cmd_valid[0:0] 1'0 + assign $1\main_sdram_timer_count1[9:0] 10'1100001101 sync always sync init - update \main_sdram_cmd_valid $1\main_sdram_cmd_valid[0:0] + update \main_sdram_timer_count1 $1\main_sdram_timer_count1[9:0] end - attribute \src "ls180.v:427.5-427.32" - process $proc$ls180.v:427$3018 + attribute \src "ls180.v:430.5-430.38" + process $proc$ls180.v:430$3148 assign { } { } - assign $1\main_sdram_cmd_ready[0:0] 1'0 + assign $1\main_sdram_postponer_req_o[0:0] 1'0 sync always sync init - update \main_sdram_cmd_ready $1\main_sdram_cmd_ready[0:0] + update \main_sdram_postponer_req_o $1\main_sdram_postponer_req_o[0:0] end - attribute \src "ls180.v:4274.1-4281.4" - process $proc$ls180.v:4274$646 + attribute \src "ls180.v:4303.1-4310.4" + process $proc$ls180.v:4303$710 assign { } { } assign $0\main_uart_rx_fifo_wrport_adr[3:0] 4'0000 - attribute \src "ls180.v:4276.2-4280.5" + attribute \src "ls180.v:4305.2-4309.5" switch \main_uart_rx_fifo_replace - attribute \src "ls180.v:4276.6-4276.31" + attribute \src "ls180.v:4305.6-4305.31" case 1'1 - assign $0\main_uart_rx_fifo_wrport_adr[3:0] $sub$ls180.v:4277$647_Y - attribute \src "ls180.v:4278.6-4278.10" + assign $0\main_uart_rx_fifo_wrport_adr[3:0] $sub$ls180.v:4306$711_Y + attribute \src "ls180.v:4307.6-4307.10" case assign $0\main_uart_rx_fifo_wrport_adr[3:0] \main_uart_rx_fifo_produce end sync always update \main_uart_rx_fifo_wrport_adr $0\main_uart_rx_fifo_wrport_adr[3:0] end - attribute \src "ls180.v:428.5-428.31" - process $proc$ls180.v:428$3019 + attribute \src "ls180.v:431.5-431.38" + process $proc$ls180.v:431$3149 assign { } { } - assign $1\main_sdram_cmd_last[0:0] 1'0 + assign $1\main_sdram_postponer_count[0:0] 1'0 sync always sync init - update \main_sdram_cmd_last $1\main_sdram_cmd_last[0:0] + update \main_sdram_postponer_count $1\main_sdram_postponer_count[0:0] end - attribute \src "ls180.v:429.12-429.44" - process $proc$ls180.v:429$3020 + attribute \src "ls180.v:432.5-432.39" + process $proc$ls180.v:432$3150 assign { } { } - assign $1\main_sdram_cmd_payload_a[12:0] 13'0000000000000 + assign $1\main_sdram_sequencer_start0[0:0] 1'0 sync always sync init - update \main_sdram_cmd_payload_a $1\main_sdram_cmd_payload_a[12:0] + update \main_sdram_sequencer_start0 $1\main_sdram_sequencer_start0[0:0] end - attribute \src "ls180.v:430.11-430.43" - process $proc$ls180.v:430$3021 + attribute \src "ls180.v:4323.1-4327.4" + process $proc$ls180.v:4323$717 assign { } { } - assign $1\main_sdram_cmd_payload_ba[1:0] 2'00 + assign { } { } + assign { } { } + assign $0\gpio_o[15:0] \main_gpiotristateasic1_pads_o sync always - sync init - update \main_sdram_cmd_payload_ba $1\main_sdram_cmd_payload_ba[1:0] + update \gpio_o $0\gpio_o[15:0] end - attribute \src "ls180.v:4304.1-4352.4" - process $proc$ls180.v:4304$657 + attribute \src "ls180.v:4328.1-4332.4" + process $proc$ls180.v:4328$718 assign { } { } assign { } { } assign { } { } + assign $0\gpio_oe[15:0] \main_gpiotristateasic1_pads_oe + sync always + update \gpio_oe $0\gpio_oe[15:0] + end + attribute \src "ls180.v:4344.1-4392.4" + process $proc$ls180.v:4344$723 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] 1'0 + assign $0\main_spimaster25_clk_enable[0:0] 1'0 + assign $0\main_spimaster26_cs_enable[0:0] 1'0 assign $0\main_spimaster28_mosi_latch[0:0] 1'0 - assign $0\main_spimaster27_count_spimaster0_next_value[2:0] 3'000 assign $0\main_spimaster2_done[0:0] 1'0 - assign $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] 1'0 assign $0\main_spimaster29_miso_latch[0:0] 1'0 assign $0\main_spimaster3_irq[0:0] 1'0 - assign $0\main_spimaster25_clk_enable[0:0] 1'0 - assign $0\main_spimaster26_cs_enable[0:0] 1'0 assign { } { } + assign $0\main_spimaster27_count_spimaster0_next_value[2:0] 3'000 assign $0\builder_spimaster0_next_state[1:0] \builder_spimaster0_state - attribute \src "ls180.v:4315.2-4351.9" + attribute \src "ls180.v:4355.2-4391.9" switch \builder_spimaster0_state attribute \src "ls180.v:0.0-0.0" case 2'01 assign $0\main_spimaster27_count_spimaster0_next_value[2:0] 3'000 assign $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4319.4-4322.7" + attribute \src "ls180.v:4359.4-4362.7" switch \main_spimaster32_clk_fall - attribute \src "ls180.v:4319.8-4319.33" + attribute \src "ls180.v:4359.8-4359.33" case 1'1 assign $0\main_spimaster26_cs_enable[0:0] 1'1 assign $0\builder_spimaster0_next_state[1:0] 2'10 @@ -272232,15 +273638,15 @@ module \ls180 case 2'10 assign $0\main_spimaster25_clk_enable[0:0] 1'1 assign $0\main_spimaster26_cs_enable[0:0] 1'1 - attribute \src "ls180.v:4327.4-4333.7" + attribute \src "ls180.v:4367.4-4373.7" switch \main_spimaster32_clk_fall - attribute \src "ls180.v:4327.8-4327.33" + attribute \src "ls180.v:4367.8-4367.33" case 1'1 - assign $0\main_spimaster27_count_spimaster0_next_value[2:0] $add$ls180.v:4328$658_Y + assign $0\main_spimaster27_count_spimaster0_next_value[2:0] $add$ls180.v:4368$724_Y assign $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4330.5-4332.8" - switch $eq$ls180.v:4330$660_Y - attribute \src "ls180.v:4330.9-4330.68" + attribute \src "ls180.v:4370.5-4372.8" + switch $eq$ls180.v:4370$726_Y + attribute \src "ls180.v:4370.9-4370.68" case 1'1 assign $0\builder_spimaster0_next_state[1:0] 2'11 case @@ -272250,9 +273656,9 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 2'11 assign $0\main_spimaster26_cs_enable[0:0] 1'1 - attribute \src "ls180.v:4337.4-4341.7" + attribute \src "ls180.v:4377.4-4381.7" switch \main_spimaster31_clk_rise - attribute \src "ls180.v:4337.8-4337.33" + attribute \src "ls180.v:4377.8-4377.33" case 1'1 assign $0\main_spimaster29_miso_latch[0:0] 1'1 assign $0\main_spimaster3_irq[0:0] 1'1 @@ -272262,9 +273668,9 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case assign $0\main_spimaster2_done[0:0] 1'1 - attribute \src "ls180.v:4345.4-4349.7" + attribute \src "ls180.v:4385.4-4389.7" switch \main_spimaster0_start - attribute \src "ls180.v:4345.8-4345.29" + attribute \src "ls180.v:4385.8-4385.29" case 1'1 assign $0\main_spimaster2_done[0:0] 1'0 assign $0\main_spimaster28_mosi_latch[0:0] 1'1 @@ -272283,48 +273689,32 @@ module \ls180 update \main_spimaster27_count_spimaster0_next_value $0\main_spimaster27_count_spimaster0_next_value[2:0] update \main_spimaster27_count_spimaster0_next_value_ce $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] end - attribute \src "ls180.v:431.5-431.38" - process $proc$ls180.v:431$3022 - assign { } { } - assign $1\main_sdram_cmd_payload_cas[0:0] 1'0 - sync always - sync init - update \main_sdram_cmd_payload_cas $1\main_sdram_cmd_payload_cas[0:0] - end - attribute \src "ls180.v:432.5-432.38" - process $proc$ls180.v:432$3023 - assign { } { } - assign $1\main_sdram_cmd_payload_ras[0:0] 1'0 - sync always - sync init - update \main_sdram_cmd_payload_ras $1\main_sdram_cmd_payload_ras[0:0] - end - attribute \src "ls180.v:433.5-433.37" - process $proc$ls180.v:433$3024 + attribute \src "ls180.v:435.5-435.38" + process $proc$ls180.v:435$3151 assign { } { } - assign $1\main_sdram_cmd_payload_we[0:0] 1'0 + assign $1\main_sdram_sequencer_done1[0:0] 1'0 sync always sync init - update \main_sdram_cmd_payload_we $1\main_sdram_cmd_payload_we[0:0] + update \main_sdram_sequencer_done1 $1\main_sdram_sequencer_done1[0:0] end - attribute \src "ls180.v:434.5-434.42" - process $proc$ls180.v:434$3025 + attribute \src "ls180.v:436.11-436.46" + process $proc$ls180.v:436$3152 assign { } { } - assign $0\main_sdram_cmd_payload_is_read[0:0] 1'0 + assign $1\main_sdram_sequencer_counter[3:0] 4'0000 sync always - update \main_sdram_cmd_payload_is_read $0\main_sdram_cmd_payload_is_read[0:0] sync init + update \main_sdram_sequencer_counter $1\main_sdram_sequencer_counter[3:0] end - attribute \src "ls180.v:435.5-435.43" - process $proc$ls180.v:435$3026 + attribute \src "ls180.v:437.5-437.38" + process $proc$ls180.v:437$3153 assign { } { } - assign $0\main_sdram_cmd_payload_is_write[0:0] 1'0 + assign $1\main_sdram_sequencer_count[0:0] 1'0 sync always - update \main_sdram_cmd_payload_is_write $0\main_sdram_cmd_payload_is_write[0:0] sync init + update \main_sdram_sequencer_count $1\main_sdram_sequencer_count[0:0] end - attribute \src "ls180.v:4363.1-4411.4" - process $proc$ls180.v:4363$665 + attribute \src "ls180.v:4403.1-4451.4" + process $proc$ls180.v:4403$731 assign { } { } assign { } { } assign { } { } @@ -272334,25 +273724,25 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\main_spisdcard_clk_enable[0:0] 1'0 + assign $0\main_spisdcard_cs_enable[0:0] 1'0 assign $0\main_spisdcard_mosi_latch[0:0] 1'0 assign $0\main_spisdcard_done0[0:0] 1'0 assign $0\main_spisdcard_miso_latch[0:0] 1'0 assign $0\main_spisdcard_irq[0:0] 1'0 - assign $0\main_spisdcard_clk_enable[0:0] 1'0 assign { } { } assign $0\main_spisdcard_count_spimaster1_next_value[2:0] 3'000 assign $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] 1'0 - assign $0\main_spisdcard_cs_enable[0:0] 1'0 assign $0\builder_spimaster1_next_state[1:0] \builder_spimaster1_state - attribute \src "ls180.v:4374.2-4410.9" + attribute \src "ls180.v:4414.2-4450.9" switch \builder_spimaster1_state attribute \src "ls180.v:0.0-0.0" case 2'01 assign $0\main_spisdcard_count_spimaster1_next_value[2:0] 3'000 assign $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4378.4-4381.7" + attribute \src "ls180.v:4418.4-4421.7" switch \main_spisdcard_clk_fall - attribute \src "ls180.v:4378.8-4378.31" + attribute \src "ls180.v:4418.8-4418.31" case 1'1 assign $0\main_spisdcard_cs_enable[0:0] 1'1 assign $0\builder_spimaster1_next_state[1:0] 2'10 @@ -272362,15 +273752,15 @@ module \ls180 case 2'10 assign $0\main_spisdcard_clk_enable[0:0] 1'1 assign $0\main_spisdcard_cs_enable[0:0] 1'1 - attribute \src "ls180.v:4386.4-4392.7" + attribute \src "ls180.v:4426.4-4432.7" switch \main_spisdcard_clk_fall - attribute \src "ls180.v:4386.8-4386.31" + attribute \src "ls180.v:4426.8-4426.31" case 1'1 - assign $0\main_spisdcard_count_spimaster1_next_value[2:0] $add$ls180.v:4387$666_Y + assign $0\main_spisdcard_count_spimaster1_next_value[2:0] $add$ls180.v:4427$732_Y assign $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4389.5-4391.8" - switch $eq$ls180.v:4389$668_Y - attribute \src "ls180.v:4389.9-4389.66" + attribute \src "ls180.v:4429.5-4431.8" + switch $eq$ls180.v:4429$734_Y + attribute \src "ls180.v:4429.9-4429.66" case 1'1 assign $0\builder_spimaster1_next_state[1:0] 2'11 case @@ -272380,9 +273770,9 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 2'11 assign $0\main_spisdcard_cs_enable[0:0] 1'1 - attribute \src "ls180.v:4396.4-4400.7" + attribute \src "ls180.v:4436.4-4440.7" switch \main_spisdcard_clk_rise - attribute \src "ls180.v:4396.8-4396.31" + attribute \src "ls180.v:4436.8-4436.31" case 1'1 assign $0\main_spisdcard_miso_latch[0:0] 1'1 assign $0\main_spisdcard_irq[0:0] 1'1 @@ -272392,9 +273782,9 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case assign $0\main_spisdcard_done0[0:0] 1'1 - attribute \src "ls180.v:4404.4-4408.7" + attribute \src "ls180.v:4444.4-4448.7" switch \main_spisdcard_start0 - attribute \src "ls180.v:4404.8-4404.29" + attribute \src "ls180.v:4444.8-4444.29" case 1'1 assign $0\main_spisdcard_done0[0:0] 1'0 assign $0\main_spisdcard_mosi_latch[0:0] 1'1 @@ -272413,35 +273803,51 @@ module \ls180 update \main_spisdcard_count_spimaster1_next_value $0\main_spisdcard_count_spimaster1_next_value[2:0] update \main_spisdcard_count_spimaster1_next_value_ce $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] end - attribute \src "ls180.v:441.11-441.44" - process $proc$ls180.v:441$3027 + attribute \src "ls180.v:443.5-443.51" + process $proc$ls180.v:443$3154 assign { } { } - assign $1\main_sdram_timer_count1[9:0] 10'1100001101 + assign $1\main_sdram_bankmachine0_req_wdata_ready[0:0] 1'0 sync always sync init - update \main_sdram_timer_count1 $1\main_sdram_timer_count1[9:0] + update \main_sdram_bankmachine0_req_wdata_ready $1\main_sdram_bankmachine0_req_wdata_ready[0:0] end - attribute \src "ls180.v:443.5-443.38" - process $proc$ls180.v:443$3028 + attribute \src "ls180.v:444.5-444.51" + process $proc$ls180.v:444$3155 assign { } { } - assign $1\main_sdram_postponer_req_o[0:0] 1'0 + assign $1\main_sdram_bankmachine0_req_rdata_valid[0:0] 1'0 sync always sync init - update \main_sdram_postponer_req_o $1\main_sdram_postponer_req_o[0:0] + update \main_sdram_bankmachine0_req_rdata_valid $1\main_sdram_bankmachine0_req_rdata_valid[0:0] end - attribute \src "ls180.v:444.5-444.38" - process $proc$ls180.v:444$3029 + attribute \src "ls180.v:446.5-446.47" + process $proc$ls180.v:446$3156 assign { } { } - assign $1\main_sdram_postponer_count[0:0] 1'0 + assign $1\main_sdram_bankmachine0_refresh_gnt[0:0] 1'0 sync always sync init - update \main_sdram_postponer_count $1\main_sdram_postponer_count[0:0] + update \main_sdram_bankmachine0_refresh_gnt $1\main_sdram_bankmachine0_refresh_gnt[0:0] + end + attribute \src "ls180.v:447.5-447.45" + process $proc$ls180.v:447$3157 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_valid $1\main_sdram_bankmachine0_cmd_valid[0:0] + end + attribute \src "ls180.v:448.5-448.45" + process $proc$ls180.v:448$3158 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_ready $1\main_sdram_bankmachine0_cmd_ready[0:0] end - attribute \src "ls180.v:4443.1-4471.4" - process $proc$ls180.v:4443$690 + attribute \src "ls180.v:4483.1-4511.4" + process $proc$ls180.v:4483$756 assign { } { } assign $0\main_sdphy_clocker_clk1[0:0] 1'0 - attribute \src "ls180.v:4445.2-4470.9" + attribute \src "ls180.v:4485.2-4510.9" switch \main_sdphy_clocker_storage attribute \src "ls180.v:0.0-0.0" case 9'000000100 @@ -272471,16 +273877,24 @@ module \ls180 sync always update \main_sdphy_clocker_clk1 $0\main_sdphy_clocker_clk1[0:0] end - attribute \src "ls180.v:445.5-445.39" - process $proc$ls180.v:445$3030 + attribute \src "ls180.v:449.12-449.57" + process $proc$ls180.v:449$3159 assign { } { } - assign $1\main_sdram_sequencer_start0[0:0] 1'0 + assign $1\main_sdram_bankmachine0_cmd_payload_a[12:0] 13'0000000000000 sync always sync init - update \main_sdram_sequencer_start0 $1\main_sdram_sequencer_start0[0:0] + update \main_sdram_bankmachine0_cmd_payload_a $1\main_sdram_bankmachine0_cmd_payload_a[12:0] + end + attribute \src "ls180.v:451.5-451.51" + process $proc$ls180.v:451$3160 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_payload_cas $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] end - attribute \src "ls180.v:4473.1-4506.4" - process $proc$ls180.v:4473$693 + attribute \src "ls180.v:4513.1-4546.4" + process $proc$ls180.v:4513$759 assign { } { } assign { } { } assign { } { } @@ -272489,16 +273903,16 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_sdphy_init_pads_out_payload_clk[0:0] 1'0 assign { } { } assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000 + assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'0 + assign $0\main_sdphy_init_pads_out_payload_clk[0:0] 1'0 assign $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] 1'0 assign $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0] 1'0 - assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'0 assign $0\main_sdphy_init_pads_out_payload_data_o[3:0] 4'0000 assign $0\main_sdphy_init_pads_out_payload_data_oe[0:0] 1'0 assign $0\builder_sdphy_sdphyinit_next_state[0:0] \builder_sdphy_sdphyinit_state - attribute \src "ls180.v:4483.2-4505.9" + attribute \src "ls180.v:4523.2-4545.9" switch \builder_sdphy_sdphyinit_state attribute \src "ls180.v:0.0-0.0" case 1'1 @@ -272507,15 +273921,15 @@ module \ls180 assign $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] 1'1 assign $0\main_sdphy_init_pads_out_payload_data_oe[0:0] 1'1 assign $0\main_sdphy_init_pads_out_payload_data_o[3:0] 4'1111 - attribute \src "ls180.v:4490.4-4496.7" + attribute \src "ls180.v:4530.4-4536.7" switch \main_sdphy_init_pads_out_ready - attribute \src "ls180.v:4490.8-4490.38" + attribute \src "ls180.v:4530.8-4530.38" case 1'1 - assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] $add$ls180.v:4491$694_Y + assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] $add$ls180.v:4531$760_Y assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4493.5-4495.8" - switch $eq$ls180.v:4493$695_Y - attribute \src "ls180.v:4493.9-4493.41" + attribute \src "ls180.v:4533.5-4535.8" + switch $eq$ls180.v:4533$761_Y + attribute \src "ls180.v:4533.9-4533.41" case 1'1 assign $0\builder_sdphy_sdphyinit_next_state[0:0] 1'0 case @@ -272526,9 +273940,9 @@ module \ls180 case assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000 assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4501.4-4503.7" + attribute \src "ls180.v:4541.4-4543.7" switch \main_sdphy_init_initialize_re - attribute \src "ls180.v:4501.8-4501.37" + attribute \src "ls180.v:4541.8-4541.37" case 1'1 assign $0\builder_sdphy_sdphyinit_next_state[0:0] 1'1 case @@ -272544,32 +273958,32 @@ module \ls180 update \main_sdphy_init_count_sdphy_sdphyinit_next_value $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] update \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] end - attribute \src "ls180.v:448.5-448.38" - process $proc$ls180.v:448$3031 + attribute \src "ls180.v:452.5-452.51" + process $proc$ls180.v:452$3161 assign { } { } - assign $1\main_sdram_sequencer_done1[0:0] 1'0 + assign $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'0 sync always sync init - update \main_sdram_sequencer_done1 $1\main_sdram_sequencer_done1[0:0] + update \main_sdram_bankmachine0_cmd_payload_ras $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] end - attribute \src "ls180.v:449.11-449.46" - process $proc$ls180.v:449$3032 + attribute \src "ls180.v:453.5-453.50" + process $proc$ls180.v:453$3162 assign { } { } - assign $1\main_sdram_sequencer_counter[3:0] 4'0000 + assign $1\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'0 sync always sync init - update \main_sdram_sequencer_counter $1\main_sdram_sequencer_counter[3:0] + update \main_sdram_bankmachine0_cmd_payload_we $1\main_sdram_bankmachine0_cmd_payload_we[0:0] end - attribute \src "ls180.v:450.5-450.38" - process $proc$ls180.v:450$3033 + attribute \src "ls180.v:454.5-454.54" + process $proc$ls180.v:454$3163 assign { } { } - assign $1\main_sdram_sequencer_count[0:0] 1'0 + assign $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'0 sync always sync init - update \main_sdram_sequencer_count $1\main_sdram_sequencer_count[0:0] + update \main_sdram_bankmachine0_cmd_payload_is_cmd $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] end - attribute \src "ls180.v:4507.1-4583.4" - process $proc$ls180.v:4507$696 + attribute \src "ls180.v:4547.1-4623.4" + process $proc$ls180.v:4547$762 assign { } { } assign { } { } assign { } { } @@ -272578,22 +273992,22 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign { } { } - assign $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'0 assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] 8'00000000 + assign $0\main_sdphy_cmdw_done[0:0] 1'0 assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'0 + assign $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'0 assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] 1'0 assign $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'0 assign $0\main_sdphy_cmdw_sink_ready[0:0] 1'0 - assign $0\main_sdphy_cmdw_done[0:0] 1'0 + assign { } { } assign $0\builder_sdphy_sdphycmdw_next_state[1:0] \builder_sdphy_sdphycmdw_state - attribute \src "ls180.v:4517.2-4582.9" + attribute \src "ls180.v:4557.2-4622.9" switch \builder_sdphy_sdphycmdw_state attribute \src "ls180.v:0.0-0.0" case 2'01 assign $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'1 assign $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'1 - attribute \src "ls180.v:4521.4-4546.11" + attribute \src "ls180.v:4561.4-4586.11" switch \main_sdphy_cmdw_count attribute \src "ls180.v:0.0-0.0" case 8'00000000 @@ -272621,22 +274035,22 @@ module \ls180 assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [0] case end - attribute \src "ls180.v:4547.4-4558.7" + attribute \src "ls180.v:4587.4-4598.7" switch \main_sdphy_cmdw_pads_out_ready - attribute \src "ls180.v:4547.8-4547.38" + attribute \src "ls180.v:4587.8-4587.38" case 1'1 - assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] $add$ls180.v:4548$697_Y + assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] $add$ls180.v:4588$763_Y assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4550.5-4557.8" - switch $eq$ls180.v:4550$698_Y - attribute \src "ls180.v:4550.9-4550.40" + attribute \src "ls180.v:4590.5-4597.8" + switch $eq$ls180.v:4590$764_Y + attribute \src "ls180.v:4590.9-4590.40" case 1'1 - attribute \src "ls180.v:4551.6-4556.9" + attribute \src "ls180.v:4591.6-4596.9" switch \main_sdphy_cmdw_sink_last - attribute \src "ls180.v:4551.10-4551.35" + attribute \src "ls180.v:4591.10-4591.35" case 1'1 assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'10 - attribute \src "ls180.v:4553.10-4553.14" + attribute \src "ls180.v:4593.10-4593.14" case assign $0\main_sdphy_cmdw_sink_ready[0:0] 1'1 assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'00 @@ -272650,15 +274064,15 @@ module \ls180 assign $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'1 assign $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'1 assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] 1'1 - attribute \src "ls180.v:4564.4-4571.7" + attribute \src "ls180.v:4604.4-4611.7" switch \main_sdphy_cmdw_pads_out_ready - attribute \src "ls180.v:4564.8-4564.38" + attribute \src "ls180.v:4604.8-4604.38" case 1'1 - assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] $add$ls180.v:4565$699_Y + assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] $add$ls180.v:4605$765_Y assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4567.5-4570.8" - switch $eq$ls180.v:4567$700_Y - attribute \src "ls180.v:4567.9-4567.40" + attribute \src "ls180.v:4607.5-4610.8" + switch $eq$ls180.v:4607$766_Y + attribute \src "ls180.v:4607.9-4607.40" case 1'1 assign $0\main_sdphy_cmdw_sink_ready[0:0] 1'1 assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'00 @@ -272670,12 +274084,12 @@ module \ls180 case assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] 8'00000000 assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4576.4-4580.7" - switch $and$ls180.v:4576$701_Y - attribute \src "ls180.v:4576.8-4576.69" + attribute \src "ls180.v:4616.4-4620.7" + switch $and$ls180.v:4616$767_Y + attribute \src "ls180.v:4616.8-4616.69" case 1'1 assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'01 - attribute \src "ls180.v:4578.8-4578.12" + attribute \src "ls180.v:4618.8-4618.12" case assign $0\main_sdphy_cmdw_done[0:0] 1'1 end @@ -272690,48 +274104,48 @@ module \ls180 update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] end - attribute \src "ls180.v:456.5-456.51" - process $proc$ls180.v:456$3034 + attribute \src "ls180.v:455.5-455.55" + process $proc$ls180.v:455$3164 assign { } { } - assign $1\main_sdram_bankmachine0_req_wdata_ready[0:0] 1'0 + assign $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine0_req_wdata_ready $1\main_sdram_bankmachine0_req_wdata_ready[0:0] + update \main_sdram_bankmachine0_cmd_payload_is_read $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] end - attribute \src "ls180.v:457.5-457.51" - process $proc$ls180.v:457$3035 + attribute \src "ls180.v:456.5-456.56" + process $proc$ls180.v:456$3165 assign { } { } - assign $1\main_sdram_bankmachine0_req_rdata_valid[0:0] 1'0 + assign $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine0_req_rdata_valid $1\main_sdram_bankmachine0_req_rdata_valid[0:0] + update \main_sdram_bankmachine0_cmd_payload_is_write $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] end - attribute \src "ls180.v:459.5-459.47" - process $proc$ls180.v:459$3036 + attribute \src "ls180.v:457.5-457.50" + process $proc$ls180.v:457$3166 assign { } { } - assign $1\main_sdram_bankmachine0_refresh_gnt[0:0] 1'0 + assign $1\main_sdram_bankmachine0_auto_precharge[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine0_refresh_gnt $1\main_sdram_bankmachine0_refresh_gnt[0:0] + update \main_sdram_bankmachine0_auto_precharge $1\main_sdram_bankmachine0_auto_precharge[0:0] end - attribute \src "ls180.v:460.5-460.45" - process $proc$ls180.v:460$3037 + attribute \src "ls180.v:460.5-460.67" + process $proc$ls180.v:460$3167 assign { } { } - assign $1\main_sdram_bankmachine0_cmd_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] 1'0 sync always + update \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] sync init - update \main_sdram_bankmachine0_cmd_valid $1\main_sdram_bankmachine0_cmd_valid[0:0] end - attribute \src "ls180.v:461.5-461.45" - process $proc$ls180.v:461$3038 + attribute \src "ls180.v:461.5-461.66" + process $proc$ls180.v:461$3168 assign { } { } - assign $1\main_sdram_bankmachine0_cmd_ready[0:0] 1'0 + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] 1'0 sync always + update \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] sync init - update \main_sdram_bankmachine0_cmd_ready $1\main_sdram_bankmachine0_cmd_ready[0:0] end - attribute \src "ls180.v:4617.1-4710.4" - process $proc$ls180.v:4617$710 + attribute \src "ls180.v:4657.1-4750.4" + process $proc$ls180.v:4657$776 assign { } { } assign { } { } assign { } { } @@ -272748,42 +274162,42 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_sdphy_cmdr_source_payload_status[2:0] 3'000 - assign { } { } assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000 assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'0 + assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'0 + assign $0\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] 1'0 assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] 0 + assign $0\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] 1'0 assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'0 + assign $0\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] 1'0 assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0 assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'0 - assign $0\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] 1'0 - assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'0 - assign $0\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] 1'0 - assign $0\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] 1'0 assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'0 assign $0\main_sdphy_cmdr_source_valid[0:0] 1'0 assign $0\main_sdphy_cmdr_source_last[0:0] 1'0 assign $0\main_sdphy_cmdr_source_payload_data[7:0] 8'00000000 + assign $0\main_sdphy_cmdr_source_payload_status[2:0] 3'000 + assign { } { } assign $0\builder_sdphy_sdphycmdr_next_state[2:0] \builder_sdphy_sdphycmdr_state - attribute \src "ls180.v:4635.2-4709.9" + attribute \src "ls180.v:4675.2-4749.9" switch \builder_sdphy_sdphycmdr_state attribute \src "ls180.v:0.0-0.0" case 3'001 assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'1 assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0 assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'1 - assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] $sub$ls180.v:4643$711_Y + assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] $sub$ls180.v:4683$777_Y assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'1 - attribute \src "ls180.v:4640.4-4642.7" + attribute \src "ls180.v:4680.4-4682.7" switch \main_sdphy_cmdr_cmdr_source_source_valid0 - attribute \src "ls180.v:4640.8-4640.49" + attribute \src "ls180.v:4680.8-4680.49" case 1'1 assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'010 case end - attribute \src "ls180.v:4645.4-4648.7" - switch $eq$ls180.v:4645$712_Y - attribute \src "ls180.v:4645.8-4645.41" + attribute \src "ls180.v:4685.4-4688.7" + switch $eq$ls180.v:4685$778_Y + attribute \src "ls180.v:4685.8-4685.41" case 1'1 assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'1 assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'100 @@ -272794,30 +274208,30 @@ module \ls180 assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'1 assign $0\main_sdphy_cmdr_source_valid[0:0] \main_sdphy_cmdr_cmdr_source_source_valid0 assign $0\main_sdphy_cmdr_source_payload_status[2:0] 3'000 - assign $0\main_sdphy_cmdr_source_last[0:0] $eq$ls180.v:4654$714_Y + assign $0\main_sdphy_cmdr_source_last[0:0] $eq$ls180.v:4694$780_Y assign $0\main_sdphy_cmdr_source_payload_data[7:0] \main_sdphy_cmdr_cmdr_source_source_payload_data0 - assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] $sub$ls180.v:4671$717_Y + assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] $sub$ls180.v:4711$783_Y assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'1 - attribute \src "ls180.v:4656.4-4670.7" - switch $and$ls180.v:4656$715_Y - attribute \src "ls180.v:4656.8-4656.69" + attribute \src "ls180.v:4696.4-4710.7" + switch $and$ls180.v:4696$781_Y + attribute \src "ls180.v:4696.8-4696.69" case 1'1 assign $0\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] 1'1 - assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] $add$ls180.v:4658$716_Y + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] $add$ls180.v:4698$782_Y assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 - attribute \src "ls180.v:4660.5-4669.8" + attribute \src "ls180.v:4700.5-4709.8" switch \main_sdphy_cmdr_source_last - attribute \src "ls180.v:4660.9-4660.36" + attribute \src "ls180.v:4700.9-4700.36" case 1'1 assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'1 - attribute \src "ls180.v:4662.6-4668.9" + attribute \src "ls180.v:4702.6-4708.9" switch \main_sdphy_cmdr_sink_last - attribute \src "ls180.v:4662.10-4662.35" + attribute \src "ls180.v:4702.10-4702.35" case 1'1 assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000 assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'011 - attribute \src "ls180.v:4666.10-4666.14" + attribute \src "ls180.v:4706.10-4706.14" case assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 end @@ -272825,9 +274239,9 @@ module \ls180 end case end - attribute \src "ls180.v:4673.4-4676.7" - switch $eq$ls180.v:4673$718_Y - attribute \src "ls180.v:4673.8-4673.41" + attribute \src "ls180.v:4713.4-4716.7" + switch $eq$ls180.v:4713$784_Y + attribute \src "ls180.v:4713.8-4713.41" case 1'1 assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'1 assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'100 @@ -272838,15 +274252,15 @@ module \ls180 assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'1 assign $0\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] 1'1 assign $0\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] 1'1 - attribute \src "ls180.v:4682.4-4688.7" + attribute \src "ls180.v:4722.4-4728.7" switch \main_sdphy_cmdr_pads_out_ready - attribute \src "ls180.v:4682.8-4682.38" + attribute \src "ls180.v:4722.8-4722.38" case 1'1 - assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] $add$ls180.v:4683$719_Y + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] $add$ls180.v:4723$785_Y assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 - attribute \src "ls180.v:4685.5-4687.8" - switch $eq$ls180.v:4685$720_Y - attribute \src "ls180.v:4685.9-4685.40" + attribute \src "ls180.v:4725.5-4727.8" + switch $eq$ls180.v:4725$786_Y + attribute \src "ls180.v:4725.9-4725.40" case 1'1 assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 case @@ -272858,9 +274272,9 @@ module \ls180 assign $0\main_sdphy_cmdr_source_valid[0:0] 1'1 assign $0\main_sdphy_cmdr_source_payload_status[2:0] 3'001 assign $0\main_sdphy_cmdr_source_last[0:0] 1'1 - attribute \src "ls180.v:4694.4-4696.7" - switch $and$ls180.v:4694$721_Y - attribute \src "ls180.v:4694.8-4694.69" + attribute \src "ls180.v:4734.4-4736.7" + switch $and$ls180.v:4734$787_Y + attribute \src "ls180.v:4734.8-4734.69" case 1'1 assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 case @@ -272871,9 +274285,9 @@ module \ls180 assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] 500000 assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'1 - attribute \src "ls180.v:4703.4-4707.7" - switch $and$ls180.v:4703$723_Y - attribute \src "ls180.v:4703.8-4703.94" + attribute \src "ls180.v:4743.4-4747.7" + switch $and$ls180.v:4743$789_Y + attribute \src "ls180.v:4743.8-4743.94" case 1'1 assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'1 assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'1 @@ -272899,122 +274313,66 @@ module \ls180 update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] end - attribute \src "ls180.v:462.12-462.57" - process $proc$ls180.v:462$3039 + attribute \src "ls180.v:476.11-476.68" + process $proc$ls180.v:476$3169 assign { } { } - assign $1\main_sdram_bankmachine0_cmd_payload_a[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_bankmachine0_cmd_payload_a $1\main_sdram_bankmachine0_cmd_payload_a[12:0] - end - attribute \src "ls180.v:464.5-464.51" - process $proc$ls180.v:464$3040 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_payload_cas $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] - end - attribute \src "ls180.v:465.5-465.51" - process $proc$ls180.v:465$3041 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_payload_ras $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] - end - attribute \src "ls180.v:466.5-466.50" - process $proc$ls180.v:466$3042 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_payload_we $1\main_sdram_bankmachine0_cmd_payload_we[0:0] - end - attribute \src "ls180.v:467.5-467.54" - process $proc$ls180.v:467$3043 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_payload_is_cmd $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] - end - attribute \src "ls180.v:468.5-468.55" - process $proc$ls180.v:468$3044 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_payload_is_read $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] - end - attribute \src "ls180.v:469.5-469.56" - process $proc$ls180.v:469$3045 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'0 + assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] 4'0000 sync always sync init - update \main_sdram_bankmachine0_cmd_payload_is_write $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] + update \main_sdram_bankmachine0_cmd_buffer_lookahead_level $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] end - attribute \src "ls180.v:470.5-470.50" - process $proc$ls180.v:470$3046 + attribute \src "ls180.v:477.5-477.64" + process $proc$ls180.v:477$3170 assign { } { } - assign $1\main_sdram_bankmachine0_auto_precharge[0:0] 1'0 + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] 1'0 sync always + update \main_sdram_bankmachine0_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] sync init - update \main_sdram_bankmachine0_auto_precharge $1\main_sdram_bankmachine0_auto_precharge[0:0] end - attribute \src "ls180.v:473.5-473.67" - process $proc$ls180.v:473$3047 + attribute \src "ls180.v:478.11-478.70" + process $proc$ls180.v:478$3171 assign { } { } - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] 1'0 + assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] 3'000 sync always - update \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] sync init + update \main_sdram_bankmachine0_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] end - attribute \src "ls180.v:474.5-474.66" - process $proc$ls180.v:474$3048 + attribute \src "ls180.v:4784.1-4811.4" + process $proc$ls180.v:4784$797 assign { } { } - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] 1'0 - sync always - update \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] - sync init - end - attribute \src "ls180.v:4744.1-4771.4" - process $proc$ls180.v:4744$731 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } + assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'0 assign { } { } assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0 assign $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'0 - assign { } { } assign $0\main_sdphy_dataw_valid[0:0] 1'0 assign $0\main_sdphy_dataw_error[0:0] 1'0 - assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'0 assign $0\builder_sdphy_sdphycrcr_next_state[0:0] \builder_sdphy_sdphycrcr_state - attribute \src "ls180.v:4752.2-4770.9" + attribute \src "ls180.v:4792.2-4810.9" switch \builder_sdphy_sdphycrcr_state attribute \src "ls180.v:0.0-0.0" case 1'1 assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0 assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'1 assign $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'1 - attribute \src "ls180.v:4757.4-4761.7" + attribute \src "ls180.v:4797.4-4801.7" switch \main_sdphy_dataw_crcr_source_source_valid0 - attribute \src "ls180.v:4757.8-4757.50" + attribute \src "ls180.v:4797.8-4797.50" case 1'1 - assign $0\main_sdphy_dataw_valid[0:0] $ne$ls180.v:4758$732_Y - assign $0\main_sdphy_dataw_error[0:0] $eq$ls180.v:4759$733_Y + assign $0\main_sdphy_dataw_valid[0:0] $ne$ls180.v:4798$798_Y + assign $0\main_sdphy_dataw_error[0:0] $eq$ls180.v:4799$799_Y assign $0\builder_sdphy_sdphycrcr_next_state[0:0] 1'0 case end attribute \src "ls180.v:0.0-0.0" case - attribute \src "ls180.v:4764.4-4768.7" + attribute \src "ls180.v:4804.4-4808.7" switch \main_sdphy_dataw_start - attribute \src "ls180.v:4764.8-4764.30" + attribute \src "ls180.v:4804.8-4804.30" case 1'1 assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'1 assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'1 @@ -273030,9 +274388,24 @@ module \ls180 update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] end - attribute \src "ls180.v:4772.1-4844.4" - process $proc$ls180.v:4772$734 + attribute \src "ls180.v:479.11-479.70" + process $proc$ls180.v:479$3172 assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] + end + attribute \src "ls180.v:480.11-480.73" + process $proc$ls180.v:480$3173 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] + end + attribute \src "ls180.v:4812.1-4884.4" + process $proc$ls180.v:4812$800 assign { } { } assign { } { } assign { } { } @@ -273041,36 +274414,37 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign { } { } + assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'0000 assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'0 assign $0\main_sdphy_dataw_sink_ready[0:0] 1'0 - assign $0\main_sdphy_dataw_start[0:0] 1'0 - assign $0\main_sdphy_dataw_stop[0:0] 1'0 assign { } { } + assign $0\main_sdphy_dataw_start[0:0] 1'0 assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'0 + assign $0\main_sdphy_dataw_stop[0:0] 1'0 assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'0 - assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'0000 assign $0\builder_sdphy_fsm_next_state[2:0] \builder_sdphy_fsm_state - attribute \src "ls180.v:4783.2-4843.9" + attribute \src "ls180.v:4823.2-4883.9" switch \builder_sdphy_fsm_state attribute \src "ls180.v:0.0-0.0" case 3'001 assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1 assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'1 assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'0000 - attribute \src "ls180.v:4788.4-4790.7" + attribute \src "ls180.v:4828.4-4830.7" switch \main_sdphy_dataw_pads_out_ready - attribute \src "ls180.v:4788.8-4788.39" + attribute \src "ls180.v:4828.8-4828.39" case 1'1 assign $0\builder_sdphy_fsm_next_state[2:0] 3'010 case end attribute \src "ls180.v:0.0-0.0" case 3'010 - assign $0\main_sdphy_dataw_stop[0:0] $not$ls180.v:4793$735_Y + assign $0\main_sdphy_dataw_stop[0:0] $not$ls180.v:4833$801_Y assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1 assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'1 - attribute \src "ls180.v:4796.4-4803.11" + attribute \src "ls180.v:4836.4-4843.11" switch \main_sdphy_dataw_count attribute \src "ls180.v:0.0-0.0" case 8'00000000 @@ -273080,24 +274454,24 @@ module \ls180 assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] \main_sdphy_dataw_sink_payload_data [3:0] case end - attribute \src "ls180.v:4804.4-4816.7" + attribute \src "ls180.v:4844.4-4856.7" switch \main_sdphy_dataw_pads_out_ready - attribute \src "ls180.v:4804.8-4804.39" + attribute \src "ls180.v:4844.8-4844.39" case 1'1 - assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] $add$ls180.v:4805$736_Y + assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] $add$ls180.v:4845$802_Y assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4807.5-4815.8" - switch $eq$ls180.v:4807$737_Y - attribute \src "ls180.v:4807.9-4807.41" + attribute \src "ls180.v:4847.5-4855.8" + switch $eq$ls180.v:4847$803_Y + attribute \src "ls180.v:4847.9-4847.41" case 1'1 assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4810.6-4814.9" + attribute \src "ls180.v:4850.6-4854.9" switch \main_sdphy_dataw_sink_last - attribute \src "ls180.v:4810.10-4810.36" + attribute \src "ls180.v:4850.10-4850.36" case 1'1 assign $0\builder_sdphy_fsm_next_state[2:0] 3'011 - attribute \src "ls180.v:4812.10-4812.14" + attribute \src "ls180.v:4852.10-4852.14" case assign $0\main_sdphy_dataw_sink_ready[0:0] 1'1 end @@ -273110,9 +274484,9 @@ module \ls180 assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1 assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'1 assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'1111 - attribute \src "ls180.v:4822.4-4825.7" + attribute \src "ls180.v:4862.4-4865.7" switch \main_sdphy_dataw_pads_out_ready - attribute \src "ls180.v:4822.8-4822.39" + attribute \src "ls180.v:4862.8-4862.39" case 1'1 assign $0\main_sdphy_dataw_start[0:0] 1'1 assign $0\builder_sdphy_fsm_next_state[2:0] 3'100 @@ -273121,13 +274495,13 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 3'100 assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1 - attribute \src "ls180.v:4829.4-4834.7" + attribute \src "ls180.v:4869.4-4874.7" switch \main_sdphy_dataw_pads_out_ready - attribute \src "ls180.v:4829.8-4829.39" + attribute \src "ls180.v:4869.8-4869.39" case 1'1 - attribute \src "ls180.v:4830.5-4833.8" + attribute \src "ls180.v:4870.5-4873.8" switch \main_sdphy_dataw_pads_in_payload_data_i [0] - attribute \src "ls180.v:4830.9-4830.51" + attribute \src "ls180.v:4870.9-4870.51" case 1'1 assign $0\main_sdphy_dataw_sink_ready[0:0] 1'1 assign $0\builder_sdphy_fsm_next_state[2:0] 3'000 @@ -273139,9 +274513,9 @@ module \ls180 case assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4839.4-4841.7" - switch $and$ls180.v:4839$738_Y - attribute \src "ls180.v:4839.8-4839.71" + attribute \src "ls180.v:4879.4-4881.7" + switch $and$ls180.v:4879$804_Y + attribute \src "ls180.v:4879.8-4879.71" case 1'1 assign $0\builder_sdphy_fsm_next_state[2:0] 3'001 case @@ -273158,8 +274532,8 @@ module \ls180 update \main_sdphy_dataw_count_sdphy_fsm_next_value $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] update \main_sdphy_dataw_count_sdphy_fsm_next_value_ce $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] end - attribute \src "ls180.v:4878.1-4979.4" - process $proc$ls180.v:4878$746 + attribute \src "ls180.v:4918.1-5019.4" + process $proc$ls180.v:4918$812 assign { } { } assign { } { } assign { } { } @@ -273176,22 +274550,22 @@ module \ls180 assign { } { } assign { } { } assign $0\main_sdphy_datar_sink_ready[0:0] 1'0 - assign $0\main_sdphy_datar_source_valid[0:0] 1'0 + assign $0\main_sdphy_datar_source_payload_status[2:0] 3'000 assign { } { } + assign $0\main_sdphy_datar_datar_source_source_ready0[0:0] 1'0 assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'0 - assign $0\main_sdphy_datar_source_last[0:0] 1'0 - assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'0 - assign $0\main_sdphy_datar_source_payload_data[7:0] 8'00000000 - assign $0\main_sdphy_datar_source_payload_status[2:0] 3'000 + assign $0\main_sdphy_datar_source_valid[0:0] 1'0 assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 0 - assign $0\main_sdphy_datar_datar_source_source_ready0[0:0] 1'0 - assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'0 assign $0\main_sdphy_datar_stop[0:0] 1'0 + assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'0 + assign $0\main_sdphy_datar_source_last[0:0] 1'0 + assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'0 assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'0 assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'0 + assign $0\main_sdphy_datar_source_payload_data[7:0] 8'00000000 assign $0\builder_sdphy_sdphydatar_next_state[2:0] \builder_sdphy_sdphydatar_state - attribute \src "ls180.v:4895.2-4978.9" + attribute \src "ls180.v:4935.2-5018.9" switch \builder_sdphy_sdphydatar_state attribute \src "ls180.v:0.0-0.0" case 3'001 @@ -273200,18 +274574,18 @@ module \ls180 assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'1 assign { } { } assign { } { } - assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] $sub$ls180.v:4905$748_Y + assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] $sub$ls180.v:4945$814_Y assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'1 - attribute \src "ls180.v:4902.4-4904.7" + attribute \src "ls180.v:4942.4-4944.7" switch \main_sdphy_datar_datar_source_source_valid0 - attribute \src "ls180.v:4902.8-4902.51" + attribute \src "ls180.v:4942.8-4942.51" case 1'1 assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'010 case end - attribute \src "ls180.v:4907.4-4910.7" - switch $eq$ls180.v:4907$749_Y - attribute \src "ls180.v:4907.8-4907.42" + attribute \src "ls180.v:4947.4-4950.7" + switch $eq$ls180.v:4947$815_Y + attribute \src "ls180.v:4947.8-4947.42" case 1'1 assign $0\main_sdphy_datar_sink_ready[0:0] 1'1 assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'100 @@ -273222,48 +274596,48 @@ module \ls180 assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'1 assign $0\main_sdphy_datar_source_valid[0:0] \main_sdphy_datar_datar_source_source_valid0 assign $0\main_sdphy_datar_source_payload_status[2:0] 3'000 - assign $0\main_sdphy_datar_source_last[0:0] $eq$ls180.v:4916$752_Y + assign $0\main_sdphy_datar_source_last[0:0] $eq$ls180.v:4956$818_Y assign $0\main_sdphy_datar_source_payload_data[7:0] \main_sdphy_datar_datar_source_source_payload_data0 - assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] $sub$ls180.v:4937$754_Y + assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] $sub$ls180.v:4977$820_Y assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'1 - attribute \src "ls180.v:4918.4-4936.7" + attribute \src "ls180.v:4958.4-4976.7" switch \main_sdphy_datar_source_valid - attribute \src "ls180.v:4918.8-4918.37" + attribute \src "ls180.v:4958.8-4958.37" case 1'1 - attribute \src "ls180.v:4919.5-4935.8" + attribute \src "ls180.v:4959.5-4975.8" switch \main_sdphy_datar_source_ready - attribute \src "ls180.v:4919.9-4919.38" + attribute \src "ls180.v:4959.9-4959.38" case 1'1 assign $0\main_sdphy_datar_datar_source_source_ready0[0:0] 1'1 - assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] $add$ls180.v:4921$753_Y + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] $add$ls180.v:4961$819_Y assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 - attribute \src "ls180.v:4923.6-4932.9" + attribute \src "ls180.v:4963.6-4972.9" switch \main_sdphy_datar_source_last - attribute \src "ls180.v:4923.10-4923.38" + attribute \src "ls180.v:4963.10-4963.38" case 1'1 assign $0\main_sdphy_datar_sink_ready[0:0] 1'1 - attribute \src "ls180.v:4925.7-4931.10" + attribute \src "ls180.v:4965.7-4971.10" switch \main_sdphy_datar_sink_last - attribute \src "ls180.v:4925.11-4925.37" + attribute \src "ls180.v:4965.11-4965.37" case 1'1 assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'011 - attribute \src "ls180.v:4929.11-4929.15" + attribute \src "ls180.v:4969.11-4969.15" case assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'000 end case end - attribute \src "ls180.v:4933.9-4933.13" + attribute \src "ls180.v:4973.9-4973.13" case assign $0\main_sdphy_datar_stop[0:0] 1'1 end case end - attribute \src "ls180.v:4939.4-4942.7" - switch $eq$ls180.v:4939$755_Y - attribute \src "ls180.v:4939.8-4939.42" + attribute \src "ls180.v:4979.4-4982.7" + switch $eq$ls180.v:4979$821_Y + attribute \src "ls180.v:4979.8-4979.42" case 1'1 assign $0\main_sdphy_datar_sink_ready[0:0] 1'1 assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'100 @@ -273272,15 +274646,15 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 3'011 assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'1 - attribute \src "ls180.v:4946.4-4952.7" + attribute \src "ls180.v:4986.4-4992.7" switch \main_sdphy_datar_pads_out_ready - attribute \src "ls180.v:4946.8-4946.39" + attribute \src "ls180.v:4986.8-4986.39" case 1'1 - assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] $add$ls180.v:4947$756_Y + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] $add$ls180.v:4987$822_Y assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 - attribute \src "ls180.v:4949.5-4951.8" - switch $eq$ls180.v:4949$757_Y - attribute \src "ls180.v:4949.9-4949.42" + attribute \src "ls180.v:4989.5-4991.8" + switch $eq$ls180.v:4989$823_Y + attribute \src "ls180.v:4989.9-4989.42" case 1'1 assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'000 case @@ -273292,9 +274666,9 @@ module \ls180 assign $0\main_sdphy_datar_source_valid[0:0] 1'1 assign $0\main_sdphy_datar_source_payload_status[2:0] 3'001 assign $0\main_sdphy_datar_source_last[0:0] 1'1 - attribute \src "ls180.v:4958.4-4960.7" - switch $and$ls180.v:4958$758_Y - attribute \src "ls180.v:4958.8-4958.71" + attribute \src "ls180.v:4998.4-5000.7" + switch $and$ls180.v:4998$824_Y + attribute \src "ls180.v:4998.8-4998.71" case 1'1 assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'000 case @@ -273303,14 +274677,14 @@ module \ls180 case assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 - attribute \src "ls180.v:4965.4-4976.7" - switch $and$ls180.v:4965$759_Y - attribute \src "ls180.v:4965.8-4965.71" + attribute \src "ls180.v:5005.4-5016.7" + switch $and$ls180.v:5005$825_Y + attribute \src "ls180.v:5005.8-5005.71" case 1'1 assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'1 - attribute \src "ls180.v:4967.5-4975.8" + attribute \src "ls180.v:5007.5-5015.8" switch \main_sdphy_datar_pads_out_ready - attribute \src "ls180.v:4967.9-4967.40" + attribute \src "ls180.v:5007.9-5007.40" case 1'1 assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 500000 assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'1 @@ -273341,128 +274715,168 @@ module \ls180 update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] end - attribute \src "ls180.v:489.11-489.68" - process $proc$ls180.v:489$3049 + attribute \src "ls180.v:501.5-501.59" + process $proc$ls180.v:501$3174 assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] 4'0000 + assign $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine0_cmd_buffer_lookahead_level $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] + update \main_sdram_bankmachine0_cmd_buffer_source_valid $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] end - attribute \src "ls180.v:490.5-490.64" - process $proc$ls180.v:490$3050 + attribute \src "ls180.v:503.5-503.59" + process $proc$ls180.v:503$3175 assign { } { } - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] 1'0 + assign $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] 1'0 sync always - update \main_sdram_bankmachine0_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] sync init + update \main_sdram_bankmachine0_cmd_buffer_source_first $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] end - attribute \src "ls180.v:491.11-491.70" - process $proc$ls180.v:491$3051 + attribute \src "ls180.v:504.5-504.58" + process $proc$ls180.v:504$3176 assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] 3'000 + assign $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine0_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] + update \main_sdram_bankmachine0_cmd_buffer_source_last $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] end - attribute \src "ls180.v:492.11-492.70" - process $proc$ls180.v:492$3052 + attribute \src "ls180.v:505.5-505.64" + process $proc$ls180.v:505$3177 assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] 3'000 + assign $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine0_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] + update \main_sdram_bankmachine0_cmd_buffer_source_payload_we $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] end - attribute \src "ls180.v:493.11-493.73" - process $proc$ls180.v:493$3053 + attribute \src "ls180.v:506.12-506.74" + process $proc$ls180.v:506$3178 assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + assign $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 sync always sync init - update \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] + update \main_sdram_bankmachine0_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] + end + attribute \src "ls180.v:507.12-507.47" + process $proc$ls180.v:507$3179 + assign { } { } + assign $1\main_sdram_bankmachine0_row[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_bankmachine0_row $1\main_sdram_bankmachine0_row[12:0] end - attribute \src "ls180.v:5037.1-5044.4" - process $proc$ls180.v:5037$881 + attribute \src "ls180.v:5077.1-5084.4" + process $proc$ls180.v:5077$947 assign { } { } assign $0\main_sdcore_crc7_inserter_crc[6:0] 7'0000000 - attribute \src "ls180.v:5039.2-5043.5" + attribute \src "ls180.v:5079.2-5083.5" switch \main_sdcore_crc7_inserter_enable - attribute \src "ls180.v:5039.6-5039.38" + attribute \src "ls180.v:5079.6-5079.38" case 1'1 assign $0\main_sdcore_crc7_inserter_crc[6:0] \main_sdcore_crc7_inserter_crcreg40 - attribute \src "ls180.v:5041.6-5041.10" + attribute \src "ls180.v:5081.6-5081.10" case assign $0\main_sdcore_crc7_inserter_crc[6:0] \main_sdcore_crc7_inserter_crcreg0 end sync always update \main_sdcore_crc7_inserter_crc $0\main_sdcore_crc7_inserter_crc[6:0] end - attribute \src "ls180.v:5059.1-5066.4" - process $proc$ls180.v:5059$904 + attribute \src "ls180.v:508.5-508.46" + process $proc$ls180.v:508$3180 + assign { } { } + assign $1\main_sdram_bankmachine0_row_opened[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_row_opened $1\main_sdram_bankmachine0_row_opened[0:0] + end + attribute \src "ls180.v:5099.1-5106.4" + process $proc$ls180.v:5099$970 assign { } { } assign $0\main_sdcore_crc16_inserter_crc0_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:5061.2-5065.5" + attribute \src "ls180.v:5101.2-5105.5" switch \main_sdcore_crc16_inserter_crc0_enable - attribute \src "ls180.v:5061.6-5061.44" + attribute \src "ls180.v:5101.6-5101.44" case 1'1 assign $0\main_sdcore_crc16_inserter_crc0_crc[15:0] \main_sdcore_crc16_inserter_crc0_crcreg2 - attribute \src "ls180.v:5063.6-5063.10" + attribute \src "ls180.v:5103.6-5103.10" case assign $0\main_sdcore_crc16_inserter_crc0_crc[15:0] \main_sdcore_crc16_inserter_crc0_crcreg0 end sync always update \main_sdcore_crc16_inserter_crc0_crc $0\main_sdcore_crc16_inserter_crc0_crc[15:0] end - attribute \src "ls180.v:5069.1-5076.4" - process $proc$ls180.v:5069$915 + attribute \src "ls180.v:510.5-510.44" + process $proc$ls180.v:510$3181 + assign { } { } + assign $1\main_sdram_bankmachine0_row_open[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_row_open $1\main_sdram_bankmachine0_row_open[0:0] + end + attribute \src "ls180.v:5109.1-5116.4" + process $proc$ls180.v:5109$981 assign { } { } assign $0\main_sdcore_crc16_inserter_crc1_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:5071.2-5075.5" + attribute \src "ls180.v:5111.2-5115.5" switch \main_sdcore_crc16_inserter_crc1_enable - attribute \src "ls180.v:5071.6-5071.44" + attribute \src "ls180.v:5111.6-5111.44" case 1'1 assign $0\main_sdcore_crc16_inserter_crc1_crc[15:0] \main_sdcore_crc16_inserter_crc1_crcreg2 - attribute \src "ls180.v:5073.6-5073.10" + attribute \src "ls180.v:5113.6-5113.10" case assign $0\main_sdcore_crc16_inserter_crc1_crc[15:0] \main_sdcore_crc16_inserter_crc1_crcreg0 end sync always update \main_sdcore_crc16_inserter_crc1_crc $0\main_sdcore_crc16_inserter_crc1_crc[15:0] end - attribute \src "ls180.v:5079.1-5086.4" - process $proc$ls180.v:5079$926 + attribute \src "ls180.v:511.5-511.45" + process $proc$ls180.v:511$3182 + assign { } { } + assign $1\main_sdram_bankmachine0_row_close[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_row_close $1\main_sdram_bankmachine0_row_close[0:0] + end + attribute \src "ls180.v:5119.1-5126.4" + process $proc$ls180.v:5119$992 assign { } { } assign $0\main_sdcore_crc16_inserter_crc2_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:5081.2-5085.5" + attribute \src "ls180.v:5121.2-5125.5" switch \main_sdcore_crc16_inserter_crc2_enable - attribute \src "ls180.v:5081.6-5081.44" + attribute \src "ls180.v:5121.6-5121.44" case 1'1 assign $0\main_sdcore_crc16_inserter_crc2_crc[15:0] \main_sdcore_crc16_inserter_crc2_crcreg2 - attribute \src "ls180.v:5083.6-5083.10" + attribute \src "ls180.v:5123.6-5123.10" case assign $0\main_sdcore_crc16_inserter_crc2_crc[15:0] \main_sdcore_crc16_inserter_crc2_crcreg0 end sync always update \main_sdcore_crc16_inserter_crc2_crc $0\main_sdcore_crc16_inserter_crc2_crc[15:0] end - attribute \src "ls180.v:5089.1-5096.4" - process $proc$ls180.v:5089$937 + attribute \src "ls180.v:512.5-512.54" + process $proc$ls180.v:512$3183 + assign { } { } + assign $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_row_col_n_addr_sel $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] + end + attribute \src "ls180.v:5129.1-5136.4" + process $proc$ls180.v:5129$1003 assign { } { } assign $0\main_sdcore_crc16_inserter_crc3_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:5091.2-5095.5" + attribute \src "ls180.v:5131.2-5135.5" switch \main_sdcore_crc16_inserter_crc3_enable - attribute \src "ls180.v:5091.6-5091.44" + attribute \src "ls180.v:5131.6-5131.44" case 1'1 assign $0\main_sdcore_crc16_inserter_crc3_crc[15:0] \main_sdcore_crc16_inserter_crc3_crcreg2 - attribute \src "ls180.v:5093.6-5093.10" + attribute \src "ls180.v:5133.6-5133.10" case assign $0\main_sdcore_crc16_inserter_crc3_crc[15:0] \main_sdcore_crc16_inserter_crc3_crcreg0 end sync always update \main_sdcore_crc16_inserter_crc3_crc $0\main_sdcore_crc16_inserter_crc3_crc[15:0] end - attribute \src "ls180.v:5097.1-5176.4" - process $proc$ls180.v:5097$938 + attribute \src "ls180.v:5137.1-5216.4" + process $proc$ls180.v:5137$1004 assign { } { } assign { } { } assign { } { } @@ -273478,36 +274892,36 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0 - assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'0 assign { } { } assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_inserter_source_valid[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0 assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] 1'0 assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_inserter_source_last[0:0] 1'0 assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] 1'0 - assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] 8'00000000 + assign $0\main_sdcore_crc16_inserter_source_valid[0:0] 1'0 assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] 16'0000000000000000 assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_source_last[0:0] 1'0 assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] 8'00000000 assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'0 assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000 + assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'0 assign $0\builder_sdcore_crcupstreaminserter_next_state[0:0] \builder_sdcore_crcupstreaminserter_state - attribute \src "ls180.v:5114.2-5175.9" + attribute \src "ls180.v:5154.2-5215.9" switch \builder_sdcore_crcupstreaminserter_state attribute \src "ls180.v:0.0-0.0" case 1'1 assign $0\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0 assign $0\main_sdcore_crc16_inserter_source_valid[0:0] 1'1 - attribute \src "ls180.v:5118.4-5120.7" - switch $eq$ls180.v:5118$939_Y - attribute \src "ls180.v:5118.8-5118.48" + attribute \src "ls180.v:5158.4-5160.7" + switch $eq$ls180.v:5158$1005_Y + attribute \src "ls180.v:5158.8-5158.48" case 1'1 assign $0\main_sdcore_crc16_inserter_source_last[0:0] 1'1 case end - attribute \src "ls180.v:5121.4-5146.11" + attribute \src "ls180.v:5161.4-5186.11" switch \main_sdcore_crc16_inserter_cnt attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -273535,18 +274949,18 @@ module \ls180 assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [1] \main_sdcore_crc16_inserter_crctmp2 [1] \main_sdcore_crc16_inserter_crctmp1 [1] \main_sdcore_crc16_inserter_crctmp0 [1] \main_sdcore_crc16_inserter_crctmp3 [0] \main_sdcore_crc16_inserter_crctmp2 [0] \main_sdcore_crc16_inserter_crctmp1 [0] \main_sdcore_crc16_inserter_crctmp0 [0] } case end - attribute \src "ls180.v:5147.4-5154.7" + attribute \src "ls180.v:5187.4-5194.7" switch \main_sdcore_crc16_inserter_source_ready - attribute \src "ls180.v:5147.8-5147.47" + attribute \src "ls180.v:5187.8-5187.47" case 1'1 - attribute \src "ls180.v:5148.5-5153.8" - switch $eq$ls180.v:5148$940_Y - attribute \src "ls180.v:5148.9-5148.49" + attribute \src "ls180.v:5188.5-5193.8" + switch $eq$ls180.v:5188$1006_Y + attribute \src "ls180.v:5188.9-5188.49" case 1'1 assign $0\builder_sdcore_crcupstreaminserter_next_state[0:0] 1'0 - attribute \src "ls180.v:5150.9-5150.13" + attribute \src "ls180.v:5190.9-5190.13" case - assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] $add$ls180.v:5151$941_Y + assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] $add$ls180.v:5191$1007_Y assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'1 end case @@ -273565,9 +274979,9 @@ module \ls180 assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'1 assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] \main_sdcore_crc16_inserter_crc3_crc assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'1 - attribute \src "ls180.v:5169.4-5173.7" - switch $and$ls180.v:5169$943_Y - attribute \src "ls180.v:5169.8-5169.128" + attribute \src "ls180.v:5209.4-5213.7" + switch $and$ls180.v:5209$1009_Y + attribute \src "ls180.v:5209.8-5209.128" case 1'1 assign $0\builder_sdcore_crcupstreaminserter_next_state[0:0] 1'1 assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000 @@ -273592,37 +275006,45 @@ module \ls180 update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] end - attribute \src "ls180.v:514.5-514.59" - process $proc$ls180.v:514$3054 + attribute \src "ls180.v:514.32-514.76" + process $proc$ls180.v:514$3184 assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] 1'0 + assign $1\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine0_cmd_buffer_source_valid $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] + update \main_sdram_bankmachine0_twtpcon_ready $1\main_sdram_bankmachine0_twtpcon_ready[0:0] end - attribute \src "ls180.v:516.5-516.59" - process $proc$ls180.v:516$3055 + attribute \src "ls180.v:515.11-515.55" + process $proc$ls180.v:515$3185 assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] 1'0 + assign $1\main_sdram_bankmachine0_twtpcon_count[2:0] 3'000 sync always sync init - update \main_sdram_bankmachine0_cmd_buffer_source_first $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] + update \main_sdram_bankmachine0_twtpcon_count $1\main_sdram_bankmachine0_twtpcon_count[2:0] end - attribute \src "ls180.v:517.5-517.58" - process $proc$ls180.v:517$3056 + attribute \src "ls180.v:517.32-517.75" + process $proc$ls180.v:517$3186 assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] 1'0 + assign $0\main_sdram_bankmachine0_trccon_ready[0:0] 1'1 sync always + update \main_sdram_bankmachine0_trccon_ready $0\main_sdram_bankmachine0_trccon_ready[0:0] + sync init + end + attribute \src "ls180.v:519.32-519.76" + process $proc$ls180.v:519$3187 + assign { } { } + assign $0\main_sdram_bankmachine0_trascon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine0_trascon_ready $0\main_sdram_bankmachine0_trascon_ready[0:0] sync init - update \main_sdram_bankmachine0_cmd_buffer_source_last $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] end - attribute \src "ls180.v:5177.1-5182.4" - process $proc$ls180.v:5177$944 + attribute \src "ls180.v:5217.1-5222.4" + process $proc$ls180.v:5217$1010 assign { } { } assign $0\main_sdcore_crc16_checker_valid[0:0] 1'0 - attribute \src "ls180.v:5179.2-5181.5" - switch $and$ls180.v:5179$951_Y - attribute \src "ls180.v:5179.6-5179.301" + attribute \src "ls180.v:5219.2-5221.5" + switch $and$ls180.v:5219$1017_Y + attribute \src "ls180.v:5219.6-5219.301" case 1'1 assign $0\main_sdcore_crc16_checker_valid[0:0] 1'1 case @@ -273630,109 +275052,93 @@ module \ls180 sync always update \main_sdcore_crc16_checker_valid $0\main_sdcore_crc16_checker_valid[0:0] end - attribute \src "ls180.v:518.5-518.64" - process $proc$ls180.v:518$3057 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_buffer_source_payload_we $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] - end - attribute \src "ls180.v:5185.1-5192.4" - process $proc$ls180.v:5185$953 + attribute \src "ls180.v:5225.1-5232.4" + process $proc$ls180.v:5225$1019 assign { } { } assign $0\main_sdcore_crc16_checker_crc0_clr[0:0] 1'0 - attribute \src "ls180.v:5187.2-5191.5" - switch $eq$ls180.v:5187$954_Y - attribute \src "ls180.v:5187.6-5187.45" + attribute \src "ls180.v:5227.2-5231.5" + switch $eq$ls180.v:5227$1020_Y + attribute \src "ls180.v:5227.6-5227.45" case 1'1 assign $0\main_sdcore_crc16_checker_crc0_clr[0:0] 1'1 - attribute \src "ls180.v:5189.6-5189.10" + attribute \src "ls180.v:5229.6-5229.10" case assign $0\main_sdcore_crc16_checker_crc0_clr[0:0] 1'0 end sync always update \main_sdcore_crc16_checker_crc0_clr $0\main_sdcore_crc16_checker_crc0_clr[0:0] end - attribute \src "ls180.v:519.12-519.74" - process $proc$ls180.v:519$3058 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 - sync always - sync init - update \main_sdram_bankmachine0_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] - end - attribute \src "ls180.v:5195.1-5202.4" - process $proc$ls180.v:5195$956 + attribute \src "ls180.v:5235.1-5242.4" + process $proc$ls180.v:5235$1022 assign { } { } assign $0\main_sdcore_crc16_checker_crc1_clr[0:0] 1'0 - attribute \src "ls180.v:5197.2-5201.5" - switch $eq$ls180.v:5197$957_Y - attribute \src "ls180.v:5197.6-5197.45" + attribute \src "ls180.v:5237.2-5241.5" + switch $eq$ls180.v:5237$1023_Y + attribute \src "ls180.v:5237.6-5237.45" case 1'1 assign $0\main_sdcore_crc16_checker_crc1_clr[0:0] 1'1 - attribute \src "ls180.v:5199.6-5199.10" + attribute \src "ls180.v:5239.6-5239.10" case assign $0\main_sdcore_crc16_checker_crc1_clr[0:0] 1'0 end sync always update \main_sdcore_crc16_checker_crc1_clr $0\main_sdcore_crc16_checker_crc1_clr[0:0] end - attribute \src "ls180.v:520.12-520.47" - process $proc$ls180.v:520$3059 - assign { } { } - assign $1\main_sdram_bankmachine0_row[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_bankmachine0_row $1\main_sdram_bankmachine0_row[12:0] - end - attribute \src "ls180.v:5205.1-5212.4" - process $proc$ls180.v:5205$959 + attribute \src "ls180.v:5245.1-5252.4" + process $proc$ls180.v:5245$1025 assign { } { } assign $0\main_sdcore_crc16_checker_crc2_clr[0:0] 1'0 - attribute \src "ls180.v:5207.2-5211.5" - switch $eq$ls180.v:5207$960_Y - attribute \src "ls180.v:5207.6-5207.45" + attribute \src "ls180.v:5247.2-5251.5" + switch $eq$ls180.v:5247$1026_Y + attribute \src "ls180.v:5247.6-5247.45" case 1'1 assign $0\main_sdcore_crc16_checker_crc2_clr[0:0] 1'1 - attribute \src "ls180.v:5209.6-5209.10" + attribute \src "ls180.v:5249.6-5249.10" case assign $0\main_sdcore_crc16_checker_crc2_clr[0:0] 1'0 end sync always update \main_sdcore_crc16_checker_crc2_clr $0\main_sdcore_crc16_checker_crc2_clr[0:0] end - attribute \src "ls180.v:521.5-521.46" - process $proc$ls180.v:521$3060 + attribute \src "ls180.v:525.5-525.51" + process $proc$ls180.v:525$3188 assign { } { } - assign $1\main_sdram_bankmachine0_row_opened[0:0] 1'0 + assign $1\main_sdram_bankmachine1_req_wdata_ready[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine0_row_opened $1\main_sdram_bankmachine0_row_opened[0:0] + update \main_sdram_bankmachine1_req_wdata_ready $1\main_sdram_bankmachine1_req_wdata_ready[0:0] end - attribute \src "ls180.v:5215.1-5222.4" - process $proc$ls180.v:5215$962 + attribute \src "ls180.v:5255.1-5262.4" + process $proc$ls180.v:5255$1028 assign { } { } assign $0\main_sdcore_crc16_checker_crc3_clr[0:0] 1'0 - attribute \src "ls180.v:5217.2-5221.5" - switch $eq$ls180.v:5217$963_Y - attribute \src "ls180.v:5217.6-5217.45" + attribute \src "ls180.v:5257.2-5261.5" + switch $eq$ls180.v:5257$1029_Y + attribute \src "ls180.v:5257.6-5257.45" case 1'1 assign $0\main_sdcore_crc16_checker_crc3_clr[0:0] 1'1 - attribute \src "ls180.v:5219.6-5219.10" + attribute \src "ls180.v:5259.6-5259.10" case assign $0\main_sdcore_crc16_checker_crc3_clr[0:0] 1'0 end sync always update \main_sdcore_crc16_checker_crc3_clr $0\main_sdcore_crc16_checker_crc3_clr[0:0] end - attribute \src "ls180.v:5224.1-5229.4" - process $proc$ls180.v:5224$964 + attribute \src "ls180.v:526.5-526.51" + process $proc$ls180.v:526$3189 + assign { } { } + assign $1\main_sdram_bankmachine1_req_rdata_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_req_rdata_valid $1\main_sdram_bankmachine1_req_rdata_valid[0:0] + end + attribute \src "ls180.v:5264.1-5269.4" + process $proc$ls180.v:5264$1030 assign { } { } assign $0\main_sdcore_crc16_checker_source_valid[0:0] 1'0 - attribute \src "ls180.v:5226.2-5228.5" - switch $and$ls180.v:5226$966_Y - attribute \src "ls180.v:5226.6-5226.85" + attribute \src "ls180.v:5266.2-5268.5" + switch $and$ls180.v:5266$1032_Y + attribute \src "ls180.v:5266.6-5266.85" case 1'1 assign $0\main_sdcore_crc16_checker_source_valid[0:0] 1'1 case @@ -273740,120 +275146,120 @@ module \ls180 sync always update \main_sdcore_crc16_checker_source_valid $0\main_sdcore_crc16_checker_source_valid[0:0] end - attribute \src "ls180.v:523.5-523.44" - process $proc$ls180.v:523$3061 - assign { } { } - assign $1\main_sdram_bankmachine0_row_open[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_row_open $1\main_sdram_bankmachine0_row_open[0:0] - end - attribute \src "ls180.v:5230.1-5237.4" - process $proc$ls180.v:5230$967 + attribute \src "ls180.v:5270.1-5277.4" + process $proc$ls180.v:5270$1033 assign { } { } assign $0\main_sdcore_crc16_checker_sink_ready[0:0] 1'0 - attribute \src "ls180.v:5232.2-5236.5" - switch $lt$ls180.v:5232$968_Y - attribute \src "ls180.v:5232.6-5232.44" + attribute \src "ls180.v:5272.2-5276.5" + switch $lt$ls180.v:5272$1034_Y + attribute \src "ls180.v:5272.6-5272.44" case 1'1 assign $0\main_sdcore_crc16_checker_sink_ready[0:0] 1'1 - attribute \src "ls180.v:5234.6-5234.10" + attribute \src "ls180.v:5274.6-5274.10" case assign $0\main_sdcore_crc16_checker_sink_ready[0:0] \main_sdcore_crc16_checker_source_ready end sync always update \main_sdcore_crc16_checker_sink_ready $0\main_sdcore_crc16_checker_sink_ready[0:0] end - attribute \src "ls180.v:524.5-524.45" - process $proc$ls180.v:524$3062 + attribute \src "ls180.v:528.5-528.47" + process $proc$ls180.v:528$3190 assign { } { } - assign $1\main_sdram_bankmachine0_row_close[0:0] 1'0 + assign $1\main_sdram_bankmachine1_refresh_gnt[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine0_row_close $1\main_sdram_bankmachine0_row_close[0:0] + update \main_sdram_bankmachine1_refresh_gnt $1\main_sdram_bankmachine1_refresh_gnt[0:0] end - attribute \src "ls180.v:5241.1-5248.4" - process $proc$ls180.v:5241$979 + attribute \src "ls180.v:5281.1-5288.4" + process $proc$ls180.v:5281$1045 assign { } { } assign $0\main_sdcore_crc16_checker_crc0_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:5243.2-5247.5" + attribute \src "ls180.v:5283.2-5287.5" switch \main_sdcore_crc16_checker_crc0_enable - attribute \src "ls180.v:5243.6-5243.43" + attribute \src "ls180.v:5283.6-5283.43" case 1'1 assign $0\main_sdcore_crc16_checker_crc0_crc[15:0] \main_sdcore_crc16_checker_crc0_crcreg2 - attribute \src "ls180.v:5245.6-5245.10" + attribute \src "ls180.v:5285.6-5285.10" case assign $0\main_sdcore_crc16_checker_crc0_crc[15:0] \main_sdcore_crc16_checker_crc0_crcreg0 end sync always update \main_sdcore_crc16_checker_crc0_crc $0\main_sdcore_crc16_checker_crc0_crc[15:0] end - attribute \src "ls180.v:525.5-525.54" - process $proc$ls180.v:525$3063 + attribute \src "ls180.v:529.5-529.45" + process $proc$ls180.v:529$3191 assign { } { } - assign $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'0 + assign $1\main_sdram_bankmachine1_cmd_valid[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine0_row_col_n_addr_sel $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] + update \main_sdram_bankmachine1_cmd_valid $1\main_sdram_bankmachine1_cmd_valid[0:0] end - attribute \src "ls180.v:5251.1-5258.4" - process $proc$ls180.v:5251$990 + attribute \src "ls180.v:5291.1-5298.4" + process $proc$ls180.v:5291$1056 assign { } { } assign $0\main_sdcore_crc16_checker_crc1_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:5253.2-5257.5" + attribute \src "ls180.v:5293.2-5297.5" switch \main_sdcore_crc16_checker_crc1_enable - attribute \src "ls180.v:5253.6-5253.43" + attribute \src "ls180.v:5293.6-5293.43" case 1'1 assign $0\main_sdcore_crc16_checker_crc1_crc[15:0] \main_sdcore_crc16_checker_crc1_crcreg2 - attribute \src "ls180.v:5255.6-5255.10" + attribute \src "ls180.v:5295.6-5295.10" case assign $0\main_sdcore_crc16_checker_crc1_crc[15:0] \main_sdcore_crc16_checker_crc1_crcreg0 end sync always update \main_sdcore_crc16_checker_crc1_crc $0\main_sdcore_crc16_checker_crc1_crc[15:0] end - attribute \src "ls180.v:5261.1-5268.4" - process $proc$ls180.v:5261$1001 + attribute \src "ls180.v:530.5-530.45" + process $proc$ls180.v:530$3192 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_ready $1\main_sdram_bankmachine1_cmd_ready[0:0] + end + attribute \src "ls180.v:5301.1-5308.4" + process $proc$ls180.v:5301$1067 assign { } { } assign $0\main_sdcore_crc16_checker_crc2_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:5263.2-5267.5" + attribute \src "ls180.v:5303.2-5307.5" switch \main_sdcore_crc16_checker_crc2_enable - attribute \src "ls180.v:5263.6-5263.43" + attribute \src "ls180.v:5303.6-5303.43" case 1'1 assign $0\main_sdcore_crc16_checker_crc2_crc[15:0] \main_sdcore_crc16_checker_crc2_crcreg2 - attribute \src "ls180.v:5265.6-5265.10" + attribute \src "ls180.v:5305.6-5305.10" case assign $0\main_sdcore_crc16_checker_crc2_crc[15:0] \main_sdcore_crc16_checker_crc2_crcreg0 end sync always update \main_sdcore_crc16_checker_crc2_crc $0\main_sdcore_crc16_checker_crc2_crc[15:0] end - attribute \src "ls180.v:527.32-527.76" - process $proc$ls180.v:527$3064 + attribute \src "ls180.v:531.12-531.57" + process $proc$ls180.v:531$3193 assign { } { } - assign $1\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'0 + assign $1\main_sdram_bankmachine1_cmd_payload_a[12:0] 13'0000000000000 sync always sync init - update \main_sdram_bankmachine0_twtpcon_ready $1\main_sdram_bankmachine0_twtpcon_ready[0:0] + update \main_sdram_bankmachine1_cmd_payload_a $1\main_sdram_bankmachine1_cmd_payload_a[12:0] end - attribute \src "ls180.v:5271.1-5278.4" - process $proc$ls180.v:5271$1012 + attribute \src "ls180.v:5311.1-5318.4" + process $proc$ls180.v:5311$1078 assign { } { } assign $0\main_sdcore_crc16_checker_crc3_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:5273.2-5277.5" + attribute \src "ls180.v:5313.2-5317.5" switch \main_sdcore_crc16_checker_crc3_enable - attribute \src "ls180.v:5273.6-5273.43" + attribute \src "ls180.v:5313.6-5313.43" case 1'1 assign $0\main_sdcore_crc16_checker_crc3_crc[15:0] \main_sdcore_crc16_checker_crc3_crcreg2 - attribute \src "ls180.v:5275.6-5275.10" + attribute \src "ls180.v:5315.6-5315.10" case assign $0\main_sdcore_crc16_checker_crc3_crc[15:0] \main_sdcore_crc16_checker_crc3_crcreg0 end sync always update \main_sdcore_crc16_checker_crc3_crc $0\main_sdcore_crc16_checker_crc3_crc[15:0] end - attribute \src "ls180.v:5279.1-5469.4" - process $proc$ls180.v:5279$1013 + attribute \src "ls180.v:5319.1-5509.4" + process $proc$ls180.v:5319$1079 assign { } { } assign { } { } assign { } { } @@ -273893,52 +275299,52 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_sdphy_cmdw_sink_valid[0:0] 1'0 assign { } { } - assign $0\main_sdphy_cmdw_sink_last[0:0] 1'0 - assign $0\main_sdphy_cmdw_sink_payload_data[7:0] 8'00000000 assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0 assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'0 + assign $0\main_sdcore_crc16_checker_sink_valid[0:0] 1'0 assign $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'0 assign $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'0 + assign $0\main_sdcore_crc16_checker_sink_first[0:0] 1'0 + assign $0\main_sdcore_crc16_checker_sink_last[0:0] 1'0 assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] 3'000 + assign $0\main_sdcore_crc16_checker_sink_payload_data[7:0] 8'00000000 assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'0 assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0 assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_source_ready[0:0] 1'0 assign $0\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] 1'0 assign $0\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] 1'0 - assign $0\main_sdcore_crc16_checker_sink_valid[0:0] 1'0 assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'0 - assign $0\main_sdcore_crc16_checker_sink_first[0:0] 1'0 assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'0 - assign $0\main_sdcore_crc16_checker_sink_last[0:0] 1'0 - assign $0\main_sdcore_crc16_checker_sink_payload_data[7:0] 8'00000000 assign $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'0 assign $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'0 assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'0 assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'0 - assign $0\main_sdcore_crc16_inserter_source_ready[0:0] 1'0 - assign $0\main_sdphy_datar_sink_valid[0:0] 1'0 assign $0\main_sdphy_dataw_sink_valid[0:0] 1'0 + assign $0\main_sdphy_datar_sink_valid[0:0] 1'0 assign $0\main_sdphy_dataw_sink_first[0:0] 1'0 assign $0\main_sdphy_datar_sink_last[0:0] 1'0 assign $0\main_sdphy_dataw_sink_last[0:0] 1'0 - assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $0\main_sdphy_datar_sink_payload_block_length[9:0] 10'0000000000 assign $0\main_sdphy_dataw_sink_payload_data[7:0] 8'00000000 - assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'0 assign $0\main_sdphy_cmdr_sink_valid[0:0] 1'0 assign $0\main_sdphy_datar_source_ready[0:0] 1'0 - assign $0\main_sdphy_datar_sink_payload_block_length[9:0] 10'0000000000 assign $0\main_sdphy_cmdr_sink_last[0:0] 1'0 assign $0\main_sdphy_cmdr_sink_payload_length[7:0] 8'00000000 assign $0\main_sdphy_cmdr_source_ready[0:0] 1'0 + assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'0 + assign $0\main_sdphy_cmdw_sink_valid[0:0] 1'0 + assign $0\main_sdphy_cmdw_sink_last[0:0] 1'0 + assign $0\main_sdphy_cmdw_sink_payload_data[7:0] 8'00000000 assign $0\builder_sdcore_fsm_next_state[2:0] \builder_sdcore_fsm_state - attribute \src "ls180.v:5320.2-5468.9" + attribute \src "ls180.v:5360.2-5508.9" switch \builder_sdcore_fsm_state attribute \src "ls180.v:0.0-0.0" case 3'001 assign $0\main_sdphy_cmdw_sink_valid[0:0] 1'1 - attribute \src "ls180.v:5323.4-5343.11" + attribute \src "ls180.v:5363.4-5383.11" switch \main_sdcore_cmd_count attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -273958,27 +275364,27 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 3'101 assign $0\main_sdphy_cmdw_sink_payload_data[7:0] { \main_sdcore_crc7_inserter_crc 1'1 } - assign $0\main_sdphy_cmdw_sink_last[0:0] $eq$ls180.v:5341$1014_Y + assign $0\main_sdphy_cmdw_sink_last[0:0] $eq$ls180.v:5381$1080_Y case end - attribute \src "ls180.v:5344.4-5356.7" - switch $and$ls180.v:5344$1015_Y - attribute \src "ls180.v:5344.8-5344.65" + attribute \src "ls180.v:5384.4-5396.7" + switch $and$ls180.v:5384$1081_Y + attribute \src "ls180.v:5384.8-5384.65" case 1'1 - assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] $add$ls180.v:5345$1016_Y + assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] $add$ls180.v:5385$1082_Y assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'1 - attribute \src "ls180.v:5347.5-5355.8" - switch $eq$ls180.v:5347$1017_Y - attribute \src "ls180.v:5347.9-5347.40" + attribute \src "ls180.v:5387.5-5395.8" + switch $eq$ls180.v:5387$1083_Y + attribute \src "ls180.v:5387.9-5387.40" case 1'1 - attribute \src "ls180.v:5348.6-5354.9" - switch $eq$ls180.v:5348$1018_Y - attribute \src "ls180.v:5348.10-5348.40" + attribute \src "ls180.v:5388.6-5394.9" + switch $eq$ls180.v:5388$1084_Y + attribute \src "ls180.v:5388.10-5388.40" case 1'1 assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'1 assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'1 assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 - attribute \src "ls180.v:5352.10-5352.14" + attribute \src "ls180.v:5392.10-5392.14" case assign $0\builder_sdcore_fsm_next_state[2:0] 3'010 end @@ -273989,52 +275395,52 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 3'010 assign $0\main_sdphy_cmdr_sink_valid[0:0] 1'1 - assign $0\main_sdphy_cmdr_sink_last[0:0] $eq$ls180.v:5360$1019_Y + assign $0\main_sdphy_cmdr_sink_last[0:0] $eq$ls180.v:5400$1085_Y assign $0\main_sdphy_cmdr_source_ready[0:0] 1'1 - attribute \src "ls180.v:5361.4-5365.7" - switch $eq$ls180.v:5361$1020_Y - attribute \src "ls180.v:5361.8-5361.38" + attribute \src "ls180.v:5401.4-5405.7" + switch $eq$ls180.v:5401$1086_Y + attribute \src "ls180.v:5401.8-5401.38" case 1'1 assign $0\main_sdphy_cmdr_sink_payload_length[7:0] 8'00010001 - attribute \src "ls180.v:5363.8-5363.12" + attribute \src "ls180.v:5403.8-5403.12" case assign $0\main_sdphy_cmdr_sink_payload_length[7:0] 8'00000110 end - attribute \src "ls180.v:5367.4-5388.7" + attribute \src "ls180.v:5407.4-5428.7" switch \main_sdphy_cmdr_source_valid - attribute \src "ls180.v:5367.8-5367.36" + attribute \src "ls180.v:5407.8-5407.36" case 1'1 - attribute \src "ls180.v:5368.5-5387.8" - switch $eq$ls180.v:5368$1021_Y - attribute \src "ls180.v:5368.9-5368.56" + attribute \src "ls180.v:5408.5-5427.8" + switch $eq$ls180.v:5408$1087_Y + attribute \src "ls180.v:5408.9-5408.56" case 1'1 assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'1 assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'1 assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 - attribute \src "ls180.v:5372.9-5372.13" + attribute \src "ls180.v:5412.9-5412.13" case - attribute \src "ls180.v:5373.6-5386.9" + attribute \src "ls180.v:5413.6-5426.9" switch \main_sdphy_cmdr_source_last - attribute \src "ls180.v:5373.10-5373.37" + attribute \src "ls180.v:5413.10-5413.37" case 1'1 - attribute \src "ls180.v:5374.7-5382.10" - switch $eq$ls180.v:5374$1022_Y - attribute \src "ls180.v:5374.11-5374.42" + attribute \src "ls180.v:5414.7-5422.10" + switch $eq$ls180.v:5414$1088_Y + attribute \src "ls180.v:5414.11-5414.42" case 1'1 assign $0\builder_sdcore_fsm_next_state[2:0] 3'011 - attribute \src "ls180.v:5376.11-5376.15" + attribute \src "ls180.v:5416.11-5416.15" case - attribute \src "ls180.v:5377.8-5381.11" - switch $eq$ls180.v:5377$1023_Y - attribute \src "ls180.v:5377.12-5377.43" + attribute \src "ls180.v:5417.8-5421.11" + switch $eq$ls180.v:5417$1089_Y + attribute \src "ls180.v:5417.12-5417.43" case 1'1 assign $0\builder_sdcore_fsm_next_state[2:0] 3'100 - attribute \src "ls180.v:5379.12-5379.16" + attribute \src "ls180.v:5419.12-5419.16" case assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 end end - attribute \src "ls180.v:5383.10-5383.14" + attribute \src "ls180.v:5423.10-5423.14" case assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] { \main_sdcore_cmd_response_status [119:0] \main_sdphy_cmdr_source_payload_data } assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'1 @@ -274050,28 +275456,28 @@ module \ls180 assign $0\main_sdphy_dataw_sink_last[0:0] \main_sdcore_crc16_inserter_source_last assign $0\main_sdphy_dataw_sink_payload_data[7:0] \main_sdcore_crc16_inserter_source_payload_data assign $0\main_sdphy_datar_source_ready[0:0] 1'1 - attribute \src "ls180.v:5396.4-5402.7" - switch $and$ls180.v:5396$1025_Y - attribute \src "ls180.v:5396.8-5396.98" + attribute \src "ls180.v:5436.4-5442.7" + switch $and$ls180.v:5436$1091_Y + attribute \src "ls180.v:5436.8-5436.98" case 1'1 - assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] $add$ls180.v:5397$1026_Y + assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] $add$ls180.v:5437$1092_Y assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1 - attribute \src "ls180.v:5399.5-5401.8" - switch $eq$ls180.v:5399$1028_Y - attribute \src "ls180.v:5399.9-5399.77" + attribute \src "ls180.v:5439.5-5441.8" + switch $eq$ls180.v:5439$1094_Y + attribute \src "ls180.v:5439.9-5439.77" case 1'1 assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 case end case end - attribute \src "ls180.v:5404.4-5409.7" + attribute \src "ls180.v:5444.4-5449.7" switch \main_sdphy_datar_source_valid - attribute \src "ls180.v:5404.8-5404.37" + attribute \src "ls180.v:5444.8-5444.37" case 1'1 - attribute \src "ls180.v:5405.5-5408.8" - switch $ne$ls180.v:5405$1029_Y - attribute \src "ls180.v:5405.9-5405.57" + attribute \src "ls180.v:5445.5-5448.8" + switch $ne$ls180.v:5445$1095_Y + attribute \src "ls180.v:5445.9-5445.57" case 1'1 assign $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'1 assign $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'1 @@ -274083,42 +275489,42 @@ module \ls180 case 3'100 assign $0\main_sdphy_datar_sink_valid[0:0] 1'1 assign $0\main_sdphy_datar_sink_payload_block_length[9:0] \main_sdcore_block_length_storage - assign $0\main_sdphy_datar_sink_last[0:0] $eq$ls180.v:5414$1031_Y - attribute \src "ls180.v:5415.4-5441.7" + assign $0\main_sdphy_datar_sink_last[0:0] $eq$ls180.v:5454$1097_Y + attribute \src "ls180.v:5455.4-5481.7" switch \main_sdphy_datar_source_valid - attribute \src "ls180.v:5415.8-5415.37" + attribute \src "ls180.v:5455.8-5455.37" case 1'1 - attribute \src "ls180.v:5416.5-5440.8" - switch $eq$ls180.v:5416$1032_Y - attribute \src "ls180.v:5416.9-5416.57" + attribute \src "ls180.v:5456.5-5480.8" + switch $eq$ls180.v:5456$1098_Y + attribute \src "ls180.v:5456.9-5456.57" case 1'1 assign $0\main_sdcore_crc16_checker_sink_valid[0:0] \main_sdphy_datar_source_valid assign $0\main_sdphy_datar_source_ready[0:0] \main_sdcore_crc16_checker_sink_ready assign $0\main_sdcore_crc16_checker_sink_first[0:0] \main_sdphy_datar_source_first assign $0\main_sdcore_crc16_checker_sink_last[0:0] \main_sdphy_datar_source_last assign $0\main_sdcore_crc16_checker_sink_payload_data[7:0] \main_sdphy_datar_source_payload_data - attribute \src "ls180.v:5422.6-5430.9" - switch $and$ls180.v:5422$1033_Y - attribute \src "ls180.v:5422.10-5422.72" + attribute \src "ls180.v:5462.6-5470.9" + switch $and$ls180.v:5462$1099_Y + attribute \src "ls180.v:5462.10-5462.72" case 1'1 - assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] $add$ls180.v:5423$1034_Y + assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] $add$ls180.v:5463$1100_Y assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1 - attribute \src "ls180.v:5425.7-5429.10" - switch $eq$ls180.v:5425$1036_Y - attribute \src "ls180.v:5425.11-5425.79" + attribute \src "ls180.v:5465.7-5469.10" + switch $eq$ls180.v:5465$1102_Y + attribute \src "ls180.v:5465.11-5465.79" case 1'1 assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 - attribute \src "ls180.v:5427.11-5427.15" + attribute \src "ls180.v:5467.11-5467.15" case assign $0\builder_sdcore_fsm_next_state[2:0] 3'100 end case end - attribute \src "ls180.v:5431.9-5431.13" + attribute \src "ls180.v:5471.9-5471.13" case - attribute \src "ls180.v:5432.6-5439.9" - switch $eq$ls180.v:5432$1037_Y - attribute \src "ls180.v:5432.10-5432.58" + attribute \src "ls180.v:5472.6-5479.9" + switch $eq$ls180.v:5472$1103_Y + attribute \src "ls180.v:5472.10-5472.58" case 1'1 assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'1 assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'1 @@ -274141,9 +275547,9 @@ module \ls180 assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'1 assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0 assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1 - attribute \src "ls180.v:5452.4-5466.7" + attribute \src "ls180.v:5492.4-5506.7" switch \main_sdcore_cmd_send_re - attribute \src "ls180.v:5452.8-5452.31" + attribute \src "ls180.v:5492.8-5492.31" case 1'1 assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0 assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'1 @@ -274202,160 +275608,104 @@ module \ls180 update \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] update \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] end - attribute \src "ls180.v:528.11-528.55" - process $proc$ls180.v:528$3065 + attribute \src "ls180.v:533.5-533.51" + process $proc$ls180.v:533$3194 assign { } { } - assign $1\main_sdram_bankmachine0_twtpcon_count[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine0_twtpcon_count $1\main_sdram_bankmachine0_twtpcon_count[2:0] - end - attribute \src "ls180.v:530.32-530.75" - process $proc$ls180.v:530$3066 - assign { } { } - assign $0\main_sdram_bankmachine0_trccon_ready[0:0] 1'1 - sync always - update \main_sdram_bankmachine0_trccon_ready $0\main_sdram_bankmachine0_trccon_ready[0:0] - sync init - end - attribute \src "ls180.v:532.32-532.76" - process $proc$ls180.v:532$3067 - assign { } { } - assign $0\main_sdram_bankmachine0_trascon_ready[0:0] 1'1 - sync always - update \main_sdram_bankmachine0_trascon_ready $0\main_sdram_bankmachine0_trascon_ready[0:0] - sync init - end - attribute \src "ls180.v:538.5-538.51" - process $proc$ls180.v:538$3068 - assign { } { } - assign $1\main_sdram_bankmachine1_req_wdata_ready[0:0] 1'0 + assign $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine1_req_wdata_ready $1\main_sdram_bankmachine1_req_wdata_ready[0:0] + update \main_sdram_bankmachine1_cmd_payload_cas $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] end - attribute \src "ls180.v:539.5-539.51" - process $proc$ls180.v:539$3069 + attribute \src "ls180.v:534.5-534.51" + process $proc$ls180.v:534$3195 assign { } { } - assign $1\main_sdram_bankmachine1_req_rdata_valid[0:0] 1'0 + assign $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine1_req_rdata_valid $1\main_sdram_bankmachine1_req_rdata_valid[0:0] + update \main_sdram_bankmachine1_cmd_payload_ras $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] end - attribute \src "ls180.v:541.5-541.47" - process $proc$ls180.v:541$3070 + attribute \src "ls180.v:535.5-535.50" + process $proc$ls180.v:535$3196 assign { } { } - assign $1\main_sdram_bankmachine1_refresh_gnt[0:0] 1'0 + assign $1\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine1_refresh_gnt $1\main_sdram_bankmachine1_refresh_gnt[0:0] + update \main_sdram_bankmachine1_cmd_payload_we $1\main_sdram_bankmachine1_cmd_payload_we[0:0] end - attribute \src "ls180.v:542.5-542.45" - process $proc$ls180.v:542$3071 + attribute \src "ls180.v:536.5-536.54" + process $proc$ls180.v:536$3197 assign { } { } - assign $1\main_sdram_bankmachine1_cmd_valid[0:0] 1'0 + assign $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine1_cmd_valid $1\main_sdram_bankmachine1_cmd_valid[0:0] + update \main_sdram_bankmachine1_cmd_payload_is_cmd $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] end - attribute \src "ls180.v:543.5-543.45" - process $proc$ls180.v:543$3072 + attribute \src "ls180.v:537.5-537.55" + process $proc$ls180.v:537$3198 assign { } { } - assign $1\main_sdram_bankmachine1_cmd_ready[0:0] 1'0 + assign $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine1_cmd_ready $1\main_sdram_bankmachine1_cmd_ready[0:0] + update \main_sdram_bankmachine1_cmd_payload_is_read $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] end - attribute \src "ls180.v:544.12-544.57" - process $proc$ls180.v:544$3073 + attribute \src "ls180.v:538.5-538.56" + process $proc$ls180.v:538$3199 assign { } { } - assign $1\main_sdram_bankmachine1_cmd_payload_a[12:0] 13'0000000000000 + assign $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine1_cmd_payload_a $1\main_sdram_bankmachine1_cmd_payload_a[12:0] + update \main_sdram_bankmachine1_cmd_payload_is_write $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] end - attribute \src "ls180.v:546.5-546.51" - process $proc$ls180.v:546$3074 + attribute \src "ls180.v:539.5-539.50" + process $proc$ls180.v:539$3200 assign { } { } - assign $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'0 + assign $1\main_sdram_bankmachine1_auto_precharge[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine1_cmd_payload_cas $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] + update \main_sdram_bankmachine1_auto_precharge $1\main_sdram_bankmachine1_auto_precharge[0:0] end - attribute \src "ls180.v:547.5-547.51" - process $proc$ls180.v:547$3075 + attribute \src "ls180.v:542.5-542.67" + process $proc$ls180.v:542$3201 assign { } { } - assign $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'0 + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] 1'0 sync always + update \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] sync init - update \main_sdram_bankmachine1_cmd_payload_ras $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] end - attribute \src "ls180.v:548.5-548.50" - process $proc$ls180.v:548$3076 + attribute \src "ls180.v:543.5-543.66" + process $proc$ls180.v:543$3202 assign { } { } - assign $1\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'0 + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] 1'0 sync always + update \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] sync init - update \main_sdram_bankmachine1_cmd_payload_we $1\main_sdram_bankmachine1_cmd_payload_we[0:0] end - attribute \src "ls180.v:549.5-549.54" - process $proc$ls180.v:549$3077 + attribute \src "ls180.v:55.5-55.42" + process $proc$ls180.v:55$3026 assign { } { } - assign $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'0 + assign $1\main_libresocsim_reset_storage[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine1_cmd_payload_is_cmd $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] + update \main_libresocsim_reset_storage $1\main_libresocsim_reset_storage[0:0] end - attribute \src "ls180.v:5497.1-5504.4" - process $proc$ls180.v:5497$1038 + attribute \src "ls180.v:5537.1-5544.4" + process $proc$ls180.v:5537$1104 assign { } { } assign $0\main_sdblock2mem_fifo_wrport_adr[4:0] 5'00000 - attribute \src "ls180.v:5499.2-5503.5" + attribute \src "ls180.v:5539.2-5543.5" switch \main_sdblock2mem_fifo_replace - attribute \src "ls180.v:5499.6-5499.35" + attribute \src "ls180.v:5539.6-5539.35" case 1'1 - assign $0\main_sdblock2mem_fifo_wrport_adr[4:0] $sub$ls180.v:5500$1039_Y - attribute \src "ls180.v:5501.6-5501.10" + assign $0\main_sdblock2mem_fifo_wrport_adr[4:0] $sub$ls180.v:5540$1105_Y + attribute \src "ls180.v:5541.6-5541.10" case assign $0\main_sdblock2mem_fifo_wrport_adr[4:0] \main_sdblock2mem_fifo_produce end sync always update \main_sdblock2mem_fifo_wrport_adr $0\main_sdblock2mem_fifo_wrport_adr[4:0] end - attribute \src "ls180.v:55.5-55.42" - process $proc$ls180.v:55$2895 - assign { } { } - assign $1\main_libresocsim_reset_storage[0:0] 1'0 - sync always - sync init - update \main_libresocsim_reset_storage $1\main_libresocsim_reset_storage[0:0] - end - attribute \src "ls180.v:550.5-550.55" - process $proc$ls180.v:550$3078 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_cmd_payload_is_read $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] - end - attribute \src "ls180.v:551.5-551.56" - process $proc$ls180.v:551$3079 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_cmd_payload_is_write $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] - end - attribute \src "ls180.v:552.5-552.50" - process $proc$ls180.v:552$3080 - assign { } { } - assign $1\main_sdram_bankmachine1_auto_precharge[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_auto_precharge $1\main_sdram_bankmachine1_auto_precharge[0:0] - end - attribute \src "ls180.v:5530.1-5569.4" - process $proc$ls180.v:5530$1049 + attribute \src "ls180.v:5570.1-5609.4" + process $proc$ls180.v:5570$1115 assign { } { } assign { } { } assign { } { } @@ -274364,40 +275714,40 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_sdblock2mem_sink_sink_valid1[0:0] 1'0 + assign $0\main_sdblock2mem_wishbonedmawriter_status[0:0] 1'0 assign { } { } - assign $0\main_sdblock2mem_sink_sink_payload_address[31:0] 0 assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0 - assign $0\main_sdblock2mem_sink_sink_payload_data1[31:0] 0 - assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'0 - assign $0\main_sdblock2mem_wishbonedmawriter_status[0:0] 1'0 assign $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] 1'0 + assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'0 + assign $0\main_sdblock2mem_sink_sink_valid1[0:0] 1'0 + assign $0\main_sdblock2mem_sink_sink_payload_address[31:0] 0 + assign $0\main_sdblock2mem_sink_sink_payload_data1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 assign $0\builder_sdblock2memdma_next_state[1:0] \builder_sdblock2memdma_state - attribute \src "ls180.v:5540.2-5568.9" + attribute \src "ls180.v:5580.2-5608.9" switch \builder_sdblock2memdma_state attribute \src "ls180.v:0.0-0.0" case 2'01 assign $0\main_sdblock2mem_sink_sink_valid1[0:0] \main_sdblock2mem_wishbonedmawriter_sink_valid - assign $0\main_sdblock2mem_sink_sink_payload_data1[31:0] \main_sdblock2mem_wishbonedmawriter_sink_payload_data - assign $0\main_sdblock2mem_sink_sink_payload_address[31:0] $add$ls180.v:5544$1050_Y + assign $0\main_sdblock2mem_sink_sink_payload_data1[63:0] \main_sdblock2mem_wishbonedmawriter_sink_payload_data + assign $0\main_sdblock2mem_sink_sink_payload_address[31:0] $add$ls180.v:5584$1116_Y assign $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] \main_sdblock2mem_sink_sink_ready1 - attribute \src "ls180.v:5546.4-5557.7" - switch $and$ls180.v:5546$1051_Y - attribute \src "ls180.v:5546.8-5546.103" + attribute \src "ls180.v:5586.4-5597.7" + switch $and$ls180.v:5586$1117_Y + attribute \src "ls180.v:5586.8-5586.103" case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] $add$ls180.v:5547$1052_Y + assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] $add$ls180.v:5587$1118_Y assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:5549.5-5556.8" - switch $eq$ls180.v:5549$1054_Y - attribute \src "ls180.v:5549.9-5549.106" + attribute \src "ls180.v:5589.5-5596.8" + switch $eq$ls180.v:5589$1120_Y + attribute \src "ls180.v:5589.9-5589.106" case 1'1 - attribute \src "ls180.v:5550.6-5555.9" + attribute \src "ls180.v:5590.6-5595.9" switch \main_sdblock2mem_wishbonedmawriter_loop_storage - attribute \src "ls180.v:5550.10-5550.57" + attribute \src "ls180.v:5590.10-5590.57" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0 assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:5553.10-5553.14" + attribute \src "ls180.v:5593.10-5593.14" case assign $0\builder_sdblock2memdma_next_state[1:0] 2'10 end @@ -274418,32 +275768,63 @@ module \ls180 sync always update \main_sdblock2mem_sink_sink_valid1 $0\main_sdblock2mem_sink_sink_valid1[0:0] update \main_sdblock2mem_sink_sink_payload_address $0\main_sdblock2mem_sink_sink_payload_address[31:0] - update \main_sdblock2mem_sink_sink_payload_data1 $0\main_sdblock2mem_sink_sink_payload_data1[31:0] + update \main_sdblock2mem_sink_sink_payload_data1 $0\main_sdblock2mem_sink_sink_payload_data1[63:0] update \main_sdblock2mem_wishbonedmawriter_sink_ready $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] update \main_sdblock2mem_wishbonedmawriter_status $0\main_sdblock2mem_wishbonedmawriter_status[0:0] update \builder_sdblock2memdma_next_state $0\builder_sdblock2memdma_next_state[1:0] update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] end - attribute \src "ls180.v:555.5-555.67" - process $proc$ls180.v:555$3081 + attribute \src "ls180.v:558.11-558.68" + process $proc$ls180.v:558$3203 assign { } { } - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] 1'0 + assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] 4'0000 sync always - update \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] sync init + update \main_sdram_bankmachine1_cmd_buffer_lookahead_level $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] end - attribute \src "ls180.v:556.5-556.66" - process $proc$ls180.v:556$3082 + attribute \src "ls180.v:559.5-559.64" + process $proc$ls180.v:559$3204 assign { } { } - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] 1'0 + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] 1'0 sync always - update \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] + update \main_sdram_bankmachine1_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] sync init end - attribute \src "ls180.v:5589.1-5626.4" - process $proc$ls180.v:5589$1056 + attribute \src "ls180.v:56.5-56.37" + process $proc$ls180.v:56$3027 assign { } { } + assign $1\main_libresocsim_reset_re[0:0] 1'0 + sync always + sync init + update \main_libresocsim_reset_re $1\main_libresocsim_reset_re[0:0] + end + attribute \src "ls180.v:560.11-560.70" + process $proc$ls180.v:560$3205 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] + end + attribute \src "ls180.v:561.11-561.70" + process $proc$ls180.v:561$3206 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] + end + attribute \src "ls180.v:562.11-562.73" + process $proc$ls180.v:562$3207 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] + end + attribute \src "ls180.v:5629.1-5666.4" + process $proc$ls180.v:5629$1122 assign { } { } assign { } { } assign { } { } @@ -274455,29 +275836,30 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_interface1_bus_we[0:0] 1'0 - assign $0\main_sdmem2block_dma_source_last[0:0] 1'0 - assign $0\main_sdmem2block_dma_source_payload_data[31:0] 0 assign { } { } - assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] 0 - assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'0 assign $0\main_interface1_bus_adr[31:0] 0 + assign { } { } assign $0\main_sdmem2block_dma_sink_ready[0:0] 1'0 - assign $0\main_sdmem2block_dma_source_valid[0:0] 1'0 - assign $0\main_interface1_bus_sel[3:0] 4'0000 + assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\main_interface1_bus_sel[7:0] 8'00000000 + assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'0 assign $0\main_interface1_bus_cyc[0:0] 1'0 assign $0\main_interface1_bus_stb[0:0] 1'0 + assign $0\main_sdmem2block_dma_source_valid[0:0] 1'0 + assign $0\main_interface1_bus_we[0:0] 1'0 + assign $0\main_sdmem2block_dma_source_last[0:0] 1'0 + assign $0\main_sdmem2block_dma_source_payload_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 assign $0\builder_sdmem2blockdma_fsm_next_state[0:0] \builder_sdmem2blockdma_fsm_state - attribute \src "ls180.v:5603.2-5625.9" + attribute \src "ls180.v:5643.2-5665.9" switch \builder_sdmem2blockdma_fsm_state attribute \src "ls180.v:0.0-0.0" case 1'1 assign $0\main_sdmem2block_dma_source_valid[0:0] 1'1 assign $0\main_sdmem2block_dma_source_last[0:0] \main_sdmem2block_dma_sink_last - assign $0\main_sdmem2block_dma_source_payload_data[31:0] \main_sdmem2block_dma_data - attribute \src "ls180.v:5608.4-5611.7" + assign $0\main_sdmem2block_dma_source_payload_data[63:0] \main_sdmem2block_dma_data + attribute \src "ls180.v:5648.4-5651.7" switch \main_sdmem2block_dma_source_ready - attribute \src "ls180.v:5608.8-5608.41" + attribute \src "ls180.v:5648.8-5648.41" case 1'1 assign $0\main_sdmem2block_dma_sink_ready[0:0] 1'1 assign $0\builder_sdmem2blockdma_fsm_next_state[0:0] 1'0 @@ -274488,13 +275870,13 @@ module \ls180 assign $0\main_interface1_bus_stb[0:0] \main_sdmem2block_dma_sink_valid assign $0\main_interface1_bus_cyc[0:0] \main_sdmem2block_dma_sink_valid assign $0\main_interface1_bus_we[0:0] 1'0 - assign $0\main_interface1_bus_sel[3:0] 4'1111 + assign $0\main_interface1_bus_sel[7:0] 8'11111111 assign $0\main_interface1_bus_adr[31:0] \main_sdmem2block_dma_sink_payload_address - attribute \src "ls180.v:5619.4-5623.7" - switch $and$ls180.v:5619$1057_Y - attribute \src "ls180.v:5619.8-5619.59" + attribute \src "ls180.v:5659.4-5663.7" + switch $and$ls180.v:5659$1123_Y + attribute \src "ls180.v:5659.8-5659.59" case 1'1 - assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] { \main_interface1_bus_dat_r [7:0] \main_interface1_bus_dat_r [15:8] \main_interface1_bus_dat_r [23:16] \main_interface1_bus_dat_r [31:24] } + assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[63:0] { \main_interface1_bus_dat_r [7:0] \main_interface1_bus_dat_r [15:8] \main_interface1_bus_dat_r [23:16] \main_interface1_bus_dat_r [31:24] \main_interface1_bus_dat_r [39:32] \main_interface1_bus_dat_r [47:40] \main_interface1_bus_dat_r [55:48] \main_interface1_bus_dat_r [63:56] } assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'1 assign $0\builder_sdmem2blockdma_fsm_next_state[0:0] 1'1 case @@ -274502,28 +275884,20 @@ module \ls180 end sync always update \main_interface1_bus_adr $0\main_interface1_bus_adr[31:0] - update \main_interface1_bus_sel $0\main_interface1_bus_sel[3:0] + update \main_interface1_bus_sel $0\main_interface1_bus_sel[7:0] update \main_interface1_bus_cyc $0\main_interface1_bus_cyc[0:0] update \main_interface1_bus_stb $0\main_interface1_bus_stb[0:0] update \main_interface1_bus_we $0\main_interface1_bus_we[0:0] update \main_sdmem2block_dma_sink_ready $0\main_sdmem2block_dma_sink_ready[0:0] update \main_sdmem2block_dma_source_valid $0\main_sdmem2block_dma_source_valid[0:0] update \main_sdmem2block_dma_source_last $0\main_sdmem2block_dma_source_last[0:0] - update \main_sdmem2block_dma_source_payload_data $0\main_sdmem2block_dma_source_payload_data[31:0] + update \main_sdmem2block_dma_source_payload_data $0\main_sdmem2block_dma_source_payload_data[63:0] update \builder_sdmem2blockdma_fsm_next_state $0\builder_sdmem2blockdma_fsm_next_state[0:0] - update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] + update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[63:0] update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] end - attribute \src "ls180.v:56.5-56.37" - process $proc$ls180.v:56$2896 - assign { } { } - assign $1\main_libresocsim_reset_re[0:0] 1'0 - sync always - sync init - update \main_libresocsim_reset_re $1\main_libresocsim_reset_re[0:0] - end - attribute \src "ls180.v:5627.1-5663.4" - process $proc$ls180.v:5627$1058 + attribute \src "ls180.v:5667.1-5703.4" + process $proc$ls180.v:5667$1124 assign { } { } assign { } { } assign { } { } @@ -274531,38 +275905,38 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_sdmem2block_dma_done_status[0:0] 1'0 + assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 assign $0\main_sdmem2block_dma_sink_valid[0:0] 1'0 + assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'0 assign { } { } - assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 + assign $0\main_sdmem2block_dma_done_status[0:0] 1'0 assign $0\main_sdmem2block_dma_sink_last[0:0] 1'0 assign $0\main_sdmem2block_dma_sink_payload_address[31:0] 0 - assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'0 assign $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] \builder_sdmem2blockdma_resetinserter_state - attribute \src "ls180.v:5636.2-5662.9" + attribute \src "ls180.v:5676.2-5702.9" switch \builder_sdmem2blockdma_resetinserter_state attribute \src "ls180.v:0.0-0.0" case 2'01 assign $0\main_sdmem2block_dma_sink_valid[0:0] 1'1 - assign $0\main_sdmem2block_dma_sink_last[0:0] $eq$ls180.v:5639$1060_Y - assign $0\main_sdmem2block_dma_sink_payload_address[31:0] $add$ls180.v:5640$1061_Y - attribute \src "ls180.v:5641.4-5652.7" + assign $0\main_sdmem2block_dma_sink_last[0:0] $eq$ls180.v:5679$1126_Y + assign $0\main_sdmem2block_dma_sink_payload_address[31:0] $add$ls180.v:5680$1127_Y + attribute \src "ls180.v:5681.4-5692.7" switch \main_sdmem2block_dma_sink_ready - attribute \src "ls180.v:5641.8-5641.39" + attribute \src "ls180.v:5681.8-5681.39" case 1'1 - assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] $add$ls180.v:5642$1062_Y + assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] $add$ls180.v:5682$1128_Y assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:5644.5-5651.8" + attribute \src "ls180.v:5684.5-5691.8" switch \main_sdmem2block_dma_sink_last - attribute \src "ls180.v:5644.9-5644.39" + attribute \src "ls180.v:5684.9-5684.39" case 1'1 - attribute \src "ls180.v:5645.6-5650.9" + attribute \src "ls180.v:5685.6-5690.9" switch \main_sdmem2block_dma_loop_storage - attribute \src "ls180.v:5645.10-5645.43" + attribute \src "ls180.v:5685.10-5685.43" case 1'1 assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:5648.10-5648.14" + attribute \src "ls180.v:5688.10-5688.14" case assign $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] 2'10 end @@ -274588,20 +275962,40 @@ module \ls180 update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] end - attribute \src "ls180.v:5675.1-5691.4" - process $proc$ls180.v:5675$1068 + attribute \src "ls180.v:57.12-57.60" + process $proc$ls180.v:57$3028 + assign { } { } + assign $1\main_libresocsim_scratch_storage[31:0] 305419896 + sync always + sync init + update \main_libresocsim_scratch_storage $1\main_libresocsim_scratch_storage[31:0] + end + attribute \src "ls180.v:5715.1-5743.4" + process $proc$ls180.v:5715$1134 assign { } { } assign $0\main_sdmem2block_converter_source_payload_data[7:0] 8'00000000 - attribute \src "ls180.v:5677.2-5690.9" + attribute \src "ls180.v:5717.2-5742.9" switch \main_sdmem2block_converter_mux attribute \src "ls180.v:0.0-0.0" - case 2'00 + case 3'000 + assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [63:56] + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [55:48] + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [47:40] + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [39:32] + attribute \src "ls180.v:0.0-0.0" + case 3'100 assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [31:24] attribute \src "ls180.v:0.0-0.0" - case 2'01 + case 3'101 assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [23:16] attribute \src "ls180.v:0.0-0.0" - case 2'10 + case 3'110 assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [15:8] attribute \src "ls180.v:0.0-0.0" case @@ -274610,48 +276004,25 @@ module \ls180 sync always update \main_sdmem2block_converter_source_payload_data $0\main_sdmem2block_converter_source_payload_data[7:0] end - attribute \src "ls180.v:57.12-57.60" - process $proc$ls180.v:57$2897 - assign { } { } - assign $1\main_libresocsim_scratch_storage[31:0] 305419896 - sync always - sync init - update \main_libresocsim_scratch_storage $1\main_libresocsim_scratch_storage[31:0] - end - attribute \src "ls180.v:5705.1-5712.4" - process $proc$ls180.v:5705$1069 + attribute \src "ls180.v:5757.1-5764.4" + process $proc$ls180.v:5757$1135 assign { } { } assign $0\main_sdmem2block_fifo_wrport_adr[4:0] 5'00000 - attribute \src "ls180.v:5707.2-5711.5" + attribute \src "ls180.v:5759.2-5763.5" switch \main_sdmem2block_fifo_replace - attribute \src "ls180.v:5707.6-5707.35" + attribute \src "ls180.v:5759.6-5759.35" case 1'1 - assign $0\main_sdmem2block_fifo_wrport_adr[4:0] $sub$ls180.v:5708$1070_Y - attribute \src "ls180.v:5709.6-5709.10" + assign $0\main_sdmem2block_fifo_wrport_adr[4:0] $sub$ls180.v:5760$1136_Y + attribute \src "ls180.v:5761.6-5761.10" case assign $0\main_sdmem2block_fifo_wrport_adr[4:0] \main_sdmem2block_fifo_produce end sync always update \main_sdmem2block_fifo_wrport_adr $0\main_sdmem2block_fifo_wrport_adr[4:0] end - attribute \src "ls180.v:571.11-571.68" - process $proc$ls180.v:571$3083 + attribute \src "ls180.v:5772.1-5808.4" + process $proc$ls180.v:5772$1142 assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] 4'0000 - sync always - sync init - update \main_sdram_bankmachine1_cmd_buffer_lookahead_level $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] - end - attribute \src "ls180.v:572.5-572.64" - process $proc$ls180.v:572$3084 - assign { } { } - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] 1'0 - sync always - update \main_sdram_bankmachine1_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] - sync init - end - attribute \src "ls180.v:5720.1-5756.4" - process $proc$ls180.v:5720$1076 assign { } { } assign { } { } assign { } { } @@ -274662,7 +276033,6 @@ module \ls180 assign { } { } assign { } { } assign $0\builder_libresocsim_wishbone_ack[0:0] 1'0 - assign { } { } assign $0\builder_libresocsim_dat_w_next_value0[7:0] 8'00000000 assign $0\builder_libresocsim_dat_w_next_value_ce0[0:0] 1'0 assign $0\builder_libresocsim_adr_next_value1[13:0] 14'00000000000000 @@ -274671,7 +276041,7 @@ module \ls180 assign $0\builder_libresocsim_we_next_value_ce2[0:0] 1'0 assign $0\builder_libresocsim_wishbone_dat_r[31:0] 0 assign $0\builder_next_state[1:0] \builder_state - attribute \src "ls180.v:5731.2-5755.9" + attribute \src "ls180.v:5783.2-5807.9" switch \builder_state attribute \src "ls180.v:0.0-0.0" case 2'01 @@ -274689,13 +276059,13 @@ module \ls180 case assign $0\builder_libresocsim_dat_w_next_value0[7:0] \builder_libresocsim_wishbone_dat_w [7:0] assign $0\builder_libresocsim_dat_w_next_value_ce0[0:0] 1'1 - attribute \src "ls180.v:5747.4-5753.7" - switch $and$ls180.v:5747$1077_Y - attribute \src "ls180.v:5747.8-5747.77" + attribute \src "ls180.v:5799.4-5805.7" + switch $and$ls180.v:5799$1143_Y + attribute \src "ls180.v:5799.8-5799.77" case 1'1 assign $0\builder_libresocsim_adr_next_value1[13:0] \builder_libresocsim_wishbone_adr [13:0] assign $0\builder_libresocsim_adr_next_value_ce1[0:0] 1'1 - assign $0\builder_libresocsim_we_next_value2[0:0] $and$ls180.v:5750$1079_Y + assign $0\builder_libresocsim_we_next_value2[0:0] $and$ls180.v:5802$1145_Y assign $0\builder_libresocsim_we_next_value_ce2[0:0] 1'1 assign $0\builder_next_state[1:0] 2'01 case @@ -274712,398 +276082,390 @@ module \ls180 update \builder_libresocsim_we_next_value2 $0\builder_libresocsim_we_next_value2[0:0] update \builder_libresocsim_we_next_value_ce2 $0\builder_libresocsim_we_next_value_ce2[0:0] end - attribute \src "ls180.v:573.11-573.70" - process $proc$ls180.v:573$3085 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine1_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] - end - attribute \src "ls180.v:574.11-574.70" - process $proc$ls180.v:574$3086 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine1_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] - end - attribute \src "ls180.v:575.11-575.73" - process $proc$ls180.v:575$3087 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] - end - attribute \src "ls180.v:5781.1-5791.4" - process $proc$ls180.v:5781$1100 - assign { } { } - assign { } { } - assign $0\builder_slave_sel[7:0] [0] $eq$ls180.v:5783$1101_Y - assign $0\builder_slave_sel[7:0] [1] $eq$ls180.v:5784$1102_Y - assign $0\builder_slave_sel[7:0] [2] $eq$ls180.v:5785$1103_Y - assign $0\builder_slave_sel[7:0] [3] $eq$ls180.v:5786$1104_Y - assign $0\builder_slave_sel[7:0] [4] $eq$ls180.v:5787$1105_Y - assign $0\builder_slave_sel[7:0] [5] $eq$ls180.v:5788$1106_Y - assign $0\builder_slave_sel[7:0] [6] $eq$ls180.v:5789$1107_Y - assign $0\builder_slave_sel[7:0] [7] $eq$ls180.v:5790$1108_Y - sync always - update \builder_slave_sel $0\builder_slave_sel[7:0] - end attribute \src "ls180.v:58.5-58.39" - process $proc$ls180.v:58$2898 + process $proc$ls180.v:58$3029 assign { } { } assign $1\main_libresocsim_scratch_re[0:0] 1'0 sync always sync init update \main_libresocsim_scratch_re $1\main_libresocsim_scratch_re[0:0] end - attribute \src "ls180.v:5858.1-5869.4" - process $proc$ls180.v:5858$1127 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\builder_error[0:0] 1'0 - assign { } { } - assign $0\builder_shared_ack[0:0] $or$ls180.v:5862$1134_Y - assign $0\builder_shared_dat_r[31:0] $or$ls180.v:5863$1149_Y - attribute \src "ls180.v:5864.2-5868.5" - switch \builder_done - attribute \src "ls180.v:5864.6-5864.18" - case 1'1 - assign $0\builder_shared_dat_r[31:0] 32'11111111111111111111111111111111 - assign $0\builder_shared_ack[0:0] 1'1 - assign $0\builder_error[0:0] 1'1 - case - end - sync always - update \builder_shared_dat_r $0\builder_shared_dat_r[31:0] - update \builder_shared_ack $0\builder_shared_ack[0:0] - update \builder_error $0\builder_error[0:0] - end - attribute \src "ls180.v:596.5-596.59" - process $proc$ls180.v:596$3088 + attribute \src "ls180.v:583.5-583.59" + process $proc$ls180.v:583$3208 assign { } { } assign $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] 1'0 sync always sync init update \main_sdram_bankmachine1_cmd_buffer_source_valid $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] end - attribute \src "ls180.v:598.5-598.59" - process $proc$ls180.v:598$3089 + attribute \src "ls180.v:5833.1-5843.4" + process $proc$ls180.v:5833$1166 + assign { } { } + assign { } { } + assign $0\builder_slave_sel[7:0] [0] $eq$ls180.v:5835$1167_Y + assign $0\builder_slave_sel[7:0] [1] $eq$ls180.v:5836$1168_Y + assign $0\builder_slave_sel[7:0] [2] $eq$ls180.v:5837$1169_Y + assign $0\builder_slave_sel[7:0] [3] $eq$ls180.v:5838$1170_Y + assign $0\builder_slave_sel[7:0] [4] $eq$ls180.v:5839$1171_Y + assign $0\builder_slave_sel[7:0] [5] $eq$ls180.v:5840$1172_Y + assign $0\builder_slave_sel[7:0] [6] $eq$ls180.v:5841$1173_Y + assign $0\builder_slave_sel[7:0] [7] $eq$ls180.v:5842$1174_Y + sync always + update \builder_slave_sel $0\builder_slave_sel[7:0] + end + attribute \src "ls180.v:585.5-585.59" + process $proc$ls180.v:585$3209 assign { } { } assign $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] 1'0 sync always sync init update \main_sdram_bankmachine1_cmd_buffer_source_first $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] end - attribute \src "ls180.v:599.5-599.58" - process $proc$ls180.v:599$3090 + attribute \src "ls180.v:586.5-586.58" + process $proc$ls180.v:586$3210 assign { } { } assign $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] 1'0 sync always sync init update \main_sdram_bankmachine1_cmd_buffer_source_last $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] end - attribute \src "ls180.v:600.5-600.64" - process $proc$ls180.v:600$3091 + attribute \src "ls180.v:587.5-587.64" + process $proc$ls180.v:587$3211 assign { } { } assign $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] 1'0 sync always sync init update \main_sdram_bankmachine1_cmd_buffer_source_payload_we $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] end - attribute \src "ls180.v:601.12-601.74" - process $proc$ls180.v:601$3092 + attribute \src "ls180.v:588.12-588.74" + process $proc$ls180.v:588$3212 assign { } { } assign $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 sync always sync init update \main_sdram_bankmachine1_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] end - attribute \src "ls180.v:602.12-602.47" - process $proc$ls180.v:602$3093 + attribute \src "ls180.v:589.12-589.47" + process $proc$ls180.v:589$3213 assign { } { } assign $1\main_sdram_bankmachine1_row[12:0] 13'0000000000000 sync always sync init update \main_sdram_bankmachine1_row $1\main_sdram_bankmachine1_row[12:0] end - attribute \src "ls180.v:603.5-603.46" - process $proc$ls180.v:603$3094 + attribute \src "ls180.v:590.5-590.46" + process $proc$ls180.v:590$3214 assign { } { } assign $1\main_sdram_bankmachine1_row_opened[0:0] 1'0 sync always sync init update \main_sdram_bankmachine1_row_opened $1\main_sdram_bankmachine1_row_opened[0:0] end - attribute \src "ls180.v:605.5-605.44" - process $proc$ls180.v:605$3095 + attribute \src "ls180.v:5910.1-5921.4" + process $proc$ls180.v:5910$1193 + assign { } { } + assign { } { } + assign { } { } + assign $0\builder_error[0:0] 1'0 + assign { } { } + assign { } { } + assign $0\builder_shared_ack[0:0] $or$ls180.v:5914$1200_Y + assign $0\builder_shared_dat_r[31:0] $or$ls180.v:5915$1215_Y [31:0] + attribute \src "ls180.v:5916.2-5920.5" + switch \builder_done + attribute \src "ls180.v:5916.6-5916.18" + case 1'1 + assign $0\builder_shared_dat_r[31:0] 32'11111111111111111111111111111111 + assign $0\builder_shared_ack[0:0] 1'1 + assign $0\builder_error[0:0] 1'1 + case + end + sync always + update \builder_shared_dat_r $0\builder_shared_dat_r[31:0] + update \builder_shared_ack $0\builder_shared_ack[0:0] + update \builder_error $0\builder_error[0:0] + end + attribute \src "ls180.v:592.5-592.44" + process $proc$ls180.v:592$3215 assign { } { } assign $1\main_sdram_bankmachine1_row_open[0:0] 1'0 sync always sync init update \main_sdram_bankmachine1_row_open $1\main_sdram_bankmachine1_row_open[0:0] end - attribute \src "ls180.v:606.5-606.45" - process $proc$ls180.v:606$3096 + attribute \src "ls180.v:593.5-593.45" + process $proc$ls180.v:593$3216 assign { } { } assign $1\main_sdram_bankmachine1_row_close[0:0] 1'0 sync always sync init update \main_sdram_bankmachine1_row_close $1\main_sdram_bankmachine1_row_close[0:0] end - attribute \src "ls180.v:607.5-607.54" - process $proc$ls180.v:607$3097 + attribute \src "ls180.v:594.5-594.54" + process $proc$ls180.v:594$3217 assign { } { } assign $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'0 sync always sync init update \main_sdram_bankmachine1_row_col_n_addr_sel $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] end - attribute \src "ls180.v:609.32-609.76" - process $proc$ls180.v:609$3098 + attribute \src "ls180.v:596.32-596.76" + process $proc$ls180.v:596$3218 assign { } { } assign $1\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'0 sync always sync init update \main_sdram_bankmachine1_twtpcon_ready $1\main_sdram_bankmachine1_twtpcon_ready[0:0] end - attribute \src "ls180.v:610.11-610.55" - process $proc$ls180.v:610$3099 + attribute \src "ls180.v:597.11-597.55" + process $proc$ls180.v:597$3219 assign { } { } assign $1\main_sdram_bankmachine1_twtpcon_count[2:0] 3'000 sync always sync init update \main_sdram_bankmachine1_twtpcon_count $1\main_sdram_bankmachine1_twtpcon_count[2:0] end - attribute \src "ls180.v:612.32-612.75" - process $proc$ls180.v:612$3100 + attribute \src "ls180.v:599.32-599.75" + process $proc$ls180.v:599$3220 assign { } { } assign $0\main_sdram_bankmachine1_trccon_ready[0:0] 1'1 sync always update \main_sdram_bankmachine1_trccon_ready $0\main_sdram_bankmachine1_trccon_ready[0:0] sync init end - attribute \src "ls180.v:614.32-614.76" - process $proc$ls180.v:614$3101 + attribute \src "ls180.v:601.32-601.76" + process $proc$ls180.v:601$3221 assign { } { } assign $0\main_sdram_bankmachine1_trascon_ready[0:0] 1'1 sync always update \main_sdram_bankmachine1_trascon_ready $0\main_sdram_bankmachine1_trascon_ready[0:0] sync init end - attribute \src "ls180.v:620.5-620.51" - process $proc$ls180.v:620$3102 + attribute \src "ls180.v:607.5-607.51" + process $proc$ls180.v:607$3222 assign { } { } assign $1\main_sdram_bankmachine2_req_wdata_ready[0:0] 1'0 sync always sync init update \main_sdram_bankmachine2_req_wdata_ready $1\main_sdram_bankmachine2_req_wdata_ready[0:0] end - attribute \src "ls180.v:621.5-621.51" - process $proc$ls180.v:621$3103 + attribute \src "ls180.v:608.5-608.51" + process $proc$ls180.v:608$3223 assign { } { } assign $1\main_sdram_bankmachine2_req_rdata_valid[0:0] 1'0 sync always sync init update \main_sdram_bankmachine2_req_rdata_valid $1\main_sdram_bankmachine2_req_rdata_valid[0:0] end - attribute \src "ls180.v:623.5-623.47" - process $proc$ls180.v:623$3104 + attribute \src "ls180.v:610.5-610.47" + process $proc$ls180.v:610$3224 assign { } { } assign $1\main_sdram_bankmachine2_refresh_gnt[0:0] 1'0 sync always sync init update \main_sdram_bankmachine2_refresh_gnt $1\main_sdram_bankmachine2_refresh_gnt[0:0] end - attribute \src "ls180.v:624.5-624.45" - process $proc$ls180.v:624$3105 + attribute \src "ls180.v:611.5-611.45" + process $proc$ls180.v:611$3225 assign { } { } assign $1\main_sdram_bankmachine2_cmd_valid[0:0] 1'0 sync always sync init update \main_sdram_bankmachine2_cmd_valid $1\main_sdram_bankmachine2_cmd_valid[0:0] end - attribute \src "ls180.v:625.5-625.45" - process $proc$ls180.v:625$3106 + attribute \src "ls180.v:612.5-612.45" + process $proc$ls180.v:612$3226 assign { } { } assign $1\main_sdram_bankmachine2_cmd_ready[0:0] 1'0 sync always sync init update \main_sdram_bankmachine2_cmd_ready $1\main_sdram_bankmachine2_cmd_ready[0:0] end - attribute \src "ls180.v:626.12-626.57" - process $proc$ls180.v:626$3107 + attribute \src "ls180.v:613.12-613.57" + process $proc$ls180.v:613$3227 assign { } { } assign $1\main_sdram_bankmachine2_cmd_payload_a[12:0] 13'0000000000000 sync always sync init update \main_sdram_bankmachine2_cmd_payload_a $1\main_sdram_bankmachine2_cmd_payload_a[12:0] end - attribute \src "ls180.v:628.5-628.51" - process $proc$ls180.v:628$3108 + attribute \src "ls180.v:615.5-615.51" + process $proc$ls180.v:615$3228 assign { } { } assign $1\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'0 sync always sync init update \main_sdram_bankmachine2_cmd_payload_cas $1\main_sdram_bankmachine2_cmd_payload_cas[0:0] end - attribute \src "ls180.v:629.5-629.51" - process $proc$ls180.v:629$3109 + attribute \src "ls180.v:616.5-616.51" + process $proc$ls180.v:616$3229 assign { } { } assign $1\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'0 sync always sync init update \main_sdram_bankmachine2_cmd_payload_ras $1\main_sdram_bankmachine2_cmd_payload_ras[0:0] end - attribute \src "ls180.v:63.12-63.47" - process $proc$ls180.v:63$2899 - assign { } { } - assign $1\main_libresocsim_bus_errors[31:0] 0 - sync always - sync init - update \main_libresocsim_bus_errors $1\main_libresocsim_bus_errors[31:0] - end - attribute \src "ls180.v:630.5-630.50" - process $proc$ls180.v:630$3110 + attribute \src "ls180.v:617.5-617.50" + process $proc$ls180.v:617$3230 assign { } { } assign $1\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'0 sync always sync init update \main_sdram_bankmachine2_cmd_payload_we $1\main_sdram_bankmachine2_cmd_payload_we[0:0] end - attribute \src "ls180.v:631.5-631.54" - process $proc$ls180.v:631$3111 + attribute \src "ls180.v:618.5-618.54" + process $proc$ls180.v:618$3231 assign { } { } assign $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'0 sync always sync init update \main_sdram_bankmachine2_cmd_payload_is_cmd $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] end - attribute \src "ls180.v:632.5-632.55" - process $proc$ls180.v:632$3112 + attribute \src "ls180.v:619.5-619.55" + process $proc$ls180.v:619$3232 assign { } { } assign $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0 sync always sync init update \main_sdram_bankmachine2_cmd_payload_is_read $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] end - attribute \src "ls180.v:633.5-633.56" - process $proc$ls180.v:633$3113 + attribute \src "ls180.v:620.5-620.56" + process $proc$ls180.v:620$3233 assign { } { } assign $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'0 sync always sync init update \main_sdram_bankmachine2_cmd_payload_is_write $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0] end - attribute \src "ls180.v:634.5-634.50" - process $proc$ls180.v:634$3114 + attribute \src "ls180.v:621.5-621.50" + process $proc$ls180.v:621$3234 assign { } { } assign $1\main_sdram_bankmachine2_auto_precharge[0:0] 1'0 sync always sync init update \main_sdram_bankmachine2_auto_precharge $1\main_sdram_bankmachine2_auto_precharge[0:0] end - attribute \src "ls180.v:637.5-637.67" - process $proc$ls180.v:637$3115 + attribute \src "ls180.v:624.5-624.67" + process $proc$ls180.v:624$3235 assign { } { } assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] 1'0 sync always update \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] sync init end - attribute \src "ls180.v:638.5-638.66" - process $proc$ls180.v:638$3116 + attribute \src "ls180.v:625.5-625.66" + process $proc$ls180.v:625$3236 assign { } { } assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] 1'0 sync always update \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] sync init end - attribute \src "ls180.v:6383.1-6388.4" - process $proc$ls180.v:6383$2023 - assign { } { } - assign $0\main_spimaster9_start[0:0] 1'0 - attribute \src "ls180.v:6385.2-6387.5" - switch \main_spimaster12_re - attribute \src "ls180.v:6385.6-6385.25" - case 1'1 - assign $0\main_spimaster9_start[0:0] \main_spimaster11_storage [0] - case - end - sync always - update \main_spimaster9_start $0\main_spimaster9_start[0:0] - end - attribute \src "ls180.v:6429.1-6434.4" - process $proc$ls180.v:6429$2088 - assign { } { } - assign $0\main_spisdcard_start1[0:0] 1'0 - attribute \src "ls180.v:6431.2-6433.5" - switch \main_spisdcard_control_re - attribute \src "ls180.v:6431.6-6431.31" - case 1'1 - assign $0\main_spisdcard_start1[0:0] \main_spisdcard_control_storage [0] - case - end - sync always - update \main_spisdcard_start1 $0\main_spisdcard_start1[0:0] - end - attribute \src "ls180.v:65.12-65.55" - process $proc$ls180.v:65$2900 + attribute \src "ls180.v:63.12-63.47" + process $proc$ls180.v:63$3030 assign { } { } - assign $1\main_libresocsim_libresoc_interrupt[15:0] 16'0000000000000000 + assign $1\main_libresocsim_bus_errors[31:0] 0 sync always sync init - update \main_libresocsim_libresoc_interrupt $1\main_libresocsim_libresoc_interrupt[15:0] + update \main_libresocsim_bus_errors $1\main_libresocsim_bus_errors[31:0] end - attribute \src "ls180.v:653.11-653.68" - process $proc$ls180.v:653$3117 + attribute \src "ls180.v:640.11-640.68" + process $proc$ls180.v:640$3237 assign { } { } assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] 4'0000 sync always sync init update \main_sdram_bankmachine2_cmd_buffer_lookahead_level $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] end - attribute \src "ls180.v:654.5-654.64" - process $proc$ls180.v:654$3118 + attribute \src "ls180.v:641.5-641.64" + process $proc$ls180.v:641$3238 assign { } { } assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] 1'0 sync always update \main_sdram_bankmachine2_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] sync init end - attribute \src "ls180.v:655.11-655.70" - process $proc$ls180.v:655$3119 + attribute \src "ls180.v:642.11-642.70" + process $proc$ls180.v:642$3239 assign { } { } assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] 3'000 sync always sync init update \main_sdram_bankmachine2_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] end - attribute \src "ls180.v:656.11-656.70" - process $proc$ls180.v:656$3120 + attribute \src "ls180.v:643.11-643.70" + process $proc$ls180.v:643$3240 assign { } { } assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] 3'000 sync always sync init update \main_sdram_bankmachine2_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] end - attribute \src "ls180.v:657.11-657.73" - process $proc$ls180.v:657$3121 + attribute \src "ls180.v:6435.1-6440.4" + process $proc$ls180.v:6435$2089 + assign { } { } + assign $0\main_spimaster9_start[0:0] 1'0 + attribute \src "ls180.v:6437.2-6439.5" + switch \main_spimaster12_re + attribute \src "ls180.v:6437.6-6437.25" + case 1'1 + assign $0\main_spimaster9_start[0:0] \main_spimaster11_storage [0] + case + end + sync always + update \main_spimaster9_start $0\main_spimaster9_start[0:0] + end + attribute \src "ls180.v:644.11-644.73" + process $proc$ls180.v:644$3241 assign { } { } assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 sync always sync init update \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] end - attribute \src "ls180.v:6618.1-6634.4" - process $proc$ls180.v:6618$2309 + attribute \src "ls180.v:6481.1-6486.4" + process $proc$ls180.v:6481$2154 + assign { } { } + assign $0\main_spisdcard_start1[0:0] 1'0 + attribute \src "ls180.v:6483.2-6485.5" + switch \main_spisdcard_control_re + attribute \src "ls180.v:6483.6-6483.31" + case 1'1 + assign $0\main_spisdcard_start1[0:0] \main_spisdcard_control_storage [0] + case + end + sync always + update \main_spisdcard_start1 $0\main_spisdcard_start1[0:0] + end + attribute \src "ls180.v:65.12-65.55" + process $proc$ls180.v:65$3031 + assign { } { } + assign $1\main_libresocsim_libresoc_interrupt[15:0] 16'0000000000000000 + sync always + sync init + update \main_libresocsim_libresoc_interrupt $1\main_libresocsim_libresoc_interrupt[15:0] + end + attribute \src "ls180.v:665.5-665.59" + process $proc$ls180.v:665$3242 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_source_valid $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] + end + attribute \src "ls180.v:667.5-667.59" + process $proc$ls180.v:667$3243 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_source_first $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] + end + attribute \src "ls180.v:6670.1-6686.4" + process $proc$ls180.v:6670$2375 assign { } { } assign $0\builder_comb_rhs_array_muxed0[0:0] 1'0 - attribute \src "ls180.v:6620.2-6633.9" + attribute \src "ls180.v:6672.2-6685.9" switch \main_sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -275121,11 +276483,19 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed0 $0\builder_comb_rhs_array_muxed0[0:0] end - attribute \src "ls180.v:6635.1-6651.4" - process $proc$ls180.v:6635$2310 + attribute \src "ls180.v:668.5-668.58" + process $proc$ls180.v:668$3244 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_source_last $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] + end + attribute \src "ls180.v:6687.1-6703.4" + process $proc$ls180.v:6687$2376 assign { } { } assign $0\builder_comb_rhs_array_muxed1[12:0] 13'0000000000000 - attribute \src "ls180.v:6637.2-6650.9" + attribute \src "ls180.v:6689.2-6702.9" switch \main_sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -275143,11 +276513,27 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed1 $0\builder_comb_rhs_array_muxed1[12:0] end - attribute \src "ls180.v:6652.1-6668.4" - process $proc$ls180.v:6652$2311 + attribute \src "ls180.v:669.5-669.64" + process $proc$ls180.v:669$3245 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_source_payload_we $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] + end + attribute \src "ls180.v:670.12-670.74" + process $proc$ls180.v:670$3246 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] + end + attribute \src "ls180.v:6704.1-6720.4" + process $proc$ls180.v:6704$2377 assign { } { } assign $0\builder_comb_rhs_array_muxed2[1:0] 2'00 - attribute \src "ls180.v:6654.2-6667.9" + attribute \src "ls180.v:6706.2-6719.9" switch \main_sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -275165,11 +276551,27 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed2 $0\builder_comb_rhs_array_muxed2[1:0] end - attribute \src "ls180.v:6669.1-6685.4" - process $proc$ls180.v:6669$2312 + attribute \src "ls180.v:671.12-671.47" + process $proc$ls180.v:671$3247 + assign { } { } + assign $1\main_sdram_bankmachine2_row[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_bankmachine2_row $1\main_sdram_bankmachine2_row[12:0] + end + attribute \src "ls180.v:672.5-672.46" + process $proc$ls180.v:672$3248 + assign { } { } + assign $1\main_sdram_bankmachine2_row_opened[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_row_opened $1\main_sdram_bankmachine2_row_opened[0:0] + end + attribute \src "ls180.v:6721.1-6737.4" + process $proc$ls180.v:6721$2378 assign { } { } assign $0\builder_comb_rhs_array_muxed3[0:0] 1'0 - attribute \src "ls180.v:6671.2-6684.9" + attribute \src "ls180.v:6723.2-6736.9" switch \main_sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -275187,11 +276589,11 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed3 $0\builder_comb_rhs_array_muxed3[0:0] end - attribute \src "ls180.v:6686.1-6702.4" - process $proc$ls180.v:6686$2313 + attribute \src "ls180.v:6738.1-6754.4" + process $proc$ls180.v:6738$2379 assign { } { } assign $0\builder_comb_rhs_array_muxed4[0:0] 1'0 - attribute \src "ls180.v:6688.2-6701.9" + attribute \src "ls180.v:6740.2-6753.9" switch \main_sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -275209,11 +276611,27 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed4 $0\builder_comb_rhs_array_muxed4[0:0] end - attribute \src "ls180.v:6703.1-6719.4" - process $proc$ls180.v:6703$2314 + attribute \src "ls180.v:674.5-674.44" + process $proc$ls180.v:674$3249 + assign { } { } + assign $1\main_sdram_bankmachine2_row_open[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_row_open $1\main_sdram_bankmachine2_row_open[0:0] + end + attribute \src "ls180.v:675.5-675.45" + process $proc$ls180.v:675$3250 + assign { } { } + assign $1\main_sdram_bankmachine2_row_close[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_row_close $1\main_sdram_bankmachine2_row_close[0:0] + end + attribute \src "ls180.v:6755.1-6771.4" + process $proc$ls180.v:6755$2380 assign { } { } assign $0\builder_comb_rhs_array_muxed5[0:0] 1'0 - attribute \src "ls180.v:6705.2-6718.9" + attribute \src "ls180.v:6757.2-6770.9" switch \main_sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -275231,11 +276649,19 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed5 $0\builder_comb_rhs_array_muxed5[0:0] end - attribute \src "ls180.v:6720.1-6736.4" - process $proc$ls180.v:6720$2315 + attribute \src "ls180.v:676.5-676.54" + process $proc$ls180.v:676$3251 + assign { } { } + assign $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_row_col_n_addr_sel $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] + end + attribute \src "ls180.v:6772.1-6788.4" + process $proc$ls180.v:6772$2381 assign { } { } assign $0\builder_comb_t_array_muxed0[0:0] 1'0 - attribute \src "ls180.v:6722.2-6735.9" + attribute \src "ls180.v:6774.2-6787.9" switch \main_sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -275253,11 +276679,19 @@ module \ls180 sync always update \builder_comb_t_array_muxed0 $0\builder_comb_t_array_muxed0[0:0] end - attribute \src "ls180.v:6737.1-6753.4" - process $proc$ls180.v:6737$2316 + attribute \src "ls180.v:678.32-678.76" + process $proc$ls180.v:678$3252 + assign { } { } + assign $1\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_twtpcon_ready $1\main_sdram_bankmachine2_twtpcon_ready[0:0] + end + attribute \src "ls180.v:6789.1-6805.4" + process $proc$ls180.v:6789$2382 assign { } { } assign $0\builder_comb_t_array_muxed1[0:0] 1'0 - attribute \src "ls180.v:6739.2-6752.9" + attribute \src "ls180.v:6791.2-6804.9" switch \main_sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -275275,11 +276709,19 @@ module \ls180 sync always update \builder_comb_t_array_muxed1 $0\builder_comb_t_array_muxed1[0:0] end - attribute \src "ls180.v:6754.1-6770.4" - process $proc$ls180.v:6754$2317 + attribute \src "ls180.v:679.11-679.55" + process $proc$ls180.v:679$3253 + assign { } { } + assign $1\main_sdram_bankmachine2_twtpcon_count[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine2_twtpcon_count $1\main_sdram_bankmachine2_twtpcon_count[2:0] + end + attribute \src "ls180.v:6806.1-6822.4" + process $proc$ls180.v:6806$2383 assign { } { } assign $0\builder_comb_t_array_muxed2[0:0] 1'0 - attribute \src "ls180.v:6756.2-6769.9" + attribute \src "ls180.v:6808.2-6821.9" switch \main_sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -275297,11 +276739,19 @@ module \ls180 sync always update \builder_comb_t_array_muxed2 $0\builder_comb_t_array_muxed2[0:0] end - attribute \src "ls180.v:6771.1-6787.4" - process $proc$ls180.v:6771$2318 + attribute \src "ls180.v:681.32-681.75" + process $proc$ls180.v:681$3254 + assign { } { } + assign $0\main_sdram_bankmachine2_trccon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine2_trccon_ready $0\main_sdram_bankmachine2_trccon_ready[0:0] + sync init + end + attribute \src "ls180.v:6823.1-6839.4" + process $proc$ls180.v:6823$2384 assign { } { } assign $0\builder_comb_rhs_array_muxed6[0:0] 1'0 - attribute \src "ls180.v:6773.2-6786.9" + attribute \src "ls180.v:6825.2-6838.9" switch \main_sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -275319,19 +276769,19 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed6 $0\builder_comb_rhs_array_muxed6[0:0] end - attribute \src "ls180.v:678.5-678.59" - process $proc$ls180.v:678$3122 + attribute \src "ls180.v:683.32-683.76" + process $proc$ls180.v:683$3255 assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine2_trascon_ready[0:0] 1'1 sync always + update \main_sdram_bankmachine2_trascon_ready $0\main_sdram_bankmachine2_trascon_ready[0:0] sync init - update \main_sdram_bankmachine2_cmd_buffer_source_valid $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] end - attribute \src "ls180.v:6788.1-6804.4" - process $proc$ls180.v:6788$2319 + attribute \src "ls180.v:6840.1-6856.4" + process $proc$ls180.v:6840$2385 assign { } { } assign $0\builder_comb_rhs_array_muxed7[12:0] 13'0000000000000 - attribute \src "ls180.v:6790.2-6803.9" + attribute \src "ls180.v:6842.2-6855.9" switch \main_sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -275349,19 +276799,11 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed7 $0\builder_comb_rhs_array_muxed7[12:0] end - attribute \src "ls180.v:680.5-680.59" - process $proc$ls180.v:680$3123 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_cmd_buffer_source_first $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] - end - attribute \src "ls180.v:6805.1-6821.4" - process $proc$ls180.v:6805$2320 + attribute \src "ls180.v:6857.1-6873.4" + process $proc$ls180.v:6857$2386 assign { } { } assign $0\builder_comb_rhs_array_muxed8[1:0] 2'00 - attribute \src "ls180.v:6807.2-6820.9" + attribute \src "ls180.v:6859.2-6872.9" switch \main_sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -275379,27 +276821,11 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed8 $0\builder_comb_rhs_array_muxed8[1:0] end - attribute \src "ls180.v:681.5-681.58" - process $proc$ls180.v:681$3124 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_cmd_buffer_source_last $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] - end - attribute \src "ls180.v:682.5-682.64" - process $proc$ls180.v:682$3125 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_cmd_buffer_source_payload_we $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] - end - attribute \src "ls180.v:6822.1-6838.4" - process $proc$ls180.v:6822$2321 + attribute \src "ls180.v:6874.1-6890.4" + process $proc$ls180.v:6874$2387 assign { } { } assign $0\builder_comb_rhs_array_muxed9[0:0] 1'0 - attribute \src "ls180.v:6824.2-6837.9" + attribute \src "ls180.v:6876.2-6889.9" switch \main_sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -275417,19 +276843,19 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed9 $0\builder_comb_rhs_array_muxed9[0:0] end - attribute \src "ls180.v:683.12-683.74" - process $proc$ls180.v:683$3126 + attribute \src "ls180.v:689.5-689.51" + process $proc$ls180.v:689$3256 assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 + assign $1\main_sdram_bankmachine3_req_wdata_ready[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine2_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] + update \main_sdram_bankmachine3_req_wdata_ready $1\main_sdram_bankmachine3_req_wdata_ready[0:0] end - attribute \src "ls180.v:6839.1-6855.4" - process $proc$ls180.v:6839$2322 + attribute \src "ls180.v:6891.1-6907.4" + process $proc$ls180.v:6891$2388 assign { } { } assign $0\builder_comb_rhs_array_muxed10[0:0] 1'0 - attribute \src "ls180.v:6841.2-6854.9" + attribute \src "ls180.v:6893.2-6906.9" switch \main_sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -275447,27 +276873,19 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed10 $0\builder_comb_rhs_array_muxed10[0:0] end - attribute \src "ls180.v:684.12-684.47" - process $proc$ls180.v:684$3127 - assign { } { } - assign $1\main_sdram_bankmachine2_row[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_bankmachine2_row $1\main_sdram_bankmachine2_row[12:0] - end - attribute \src "ls180.v:685.5-685.46" - process $proc$ls180.v:685$3128 + attribute \src "ls180.v:690.5-690.51" + process $proc$ls180.v:690$3257 assign { } { } - assign $1\main_sdram_bankmachine2_row_opened[0:0] 1'0 + assign $1\main_sdram_bankmachine3_req_rdata_valid[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine2_row_opened $1\main_sdram_bankmachine2_row_opened[0:0] + update \main_sdram_bankmachine3_req_rdata_valid $1\main_sdram_bankmachine3_req_rdata_valid[0:0] end - attribute \src "ls180.v:6856.1-6872.4" - process $proc$ls180.v:6856$2323 + attribute \src "ls180.v:6908.1-6924.4" + process $proc$ls180.v:6908$2389 assign { } { } assign $0\builder_comb_rhs_array_muxed11[0:0] 1'0 - attribute \src "ls180.v:6858.2-6871.9" + attribute \src "ls180.v:6910.2-6923.9" switch \main_sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -275485,19 +276903,19 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed11 $0\builder_comb_rhs_array_muxed11[0:0] end - attribute \src "ls180.v:687.5-687.44" - process $proc$ls180.v:687$3129 + attribute \src "ls180.v:692.5-692.47" + process $proc$ls180.v:692$3258 assign { } { } - assign $1\main_sdram_bankmachine2_row_open[0:0] 1'0 + assign $1\main_sdram_bankmachine3_refresh_gnt[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine2_row_open $1\main_sdram_bankmachine2_row_open[0:0] + update \main_sdram_bankmachine3_refresh_gnt $1\main_sdram_bankmachine3_refresh_gnt[0:0] end - attribute \src "ls180.v:6873.1-6889.4" - process $proc$ls180.v:6873$2324 + attribute \src "ls180.v:6925.1-6941.4" + process $proc$ls180.v:6925$2390 assign { } { } assign $0\builder_comb_t_array_muxed3[0:0] 1'0 - attribute \src "ls180.v:6875.2-6888.9" + attribute \src "ls180.v:6927.2-6940.9" switch \main_sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -275515,27 +276933,27 @@ module \ls180 sync always update \builder_comb_t_array_muxed3 $0\builder_comb_t_array_muxed3[0:0] end - attribute \src "ls180.v:688.5-688.45" - process $proc$ls180.v:688$3130 + attribute \src "ls180.v:693.5-693.45" + process $proc$ls180.v:693$3259 assign { } { } - assign $1\main_sdram_bankmachine2_row_close[0:0] 1'0 + assign $1\main_sdram_bankmachine3_cmd_valid[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine2_row_close $1\main_sdram_bankmachine2_row_close[0:0] + update \main_sdram_bankmachine3_cmd_valid $1\main_sdram_bankmachine3_cmd_valid[0:0] end - attribute \src "ls180.v:689.5-689.54" - process $proc$ls180.v:689$3131 + attribute \src "ls180.v:694.5-694.45" + process $proc$ls180.v:694$3260 assign { } { } - assign $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0 + assign $1\main_sdram_bankmachine3_cmd_ready[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine2_row_col_n_addr_sel $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] + update \main_sdram_bankmachine3_cmd_ready $1\main_sdram_bankmachine3_cmd_ready[0:0] end - attribute \src "ls180.v:6890.1-6906.4" - process $proc$ls180.v:6890$2325 + attribute \src "ls180.v:6942.1-6958.4" + process $proc$ls180.v:6942$2391 assign { } { } assign $0\builder_comb_t_array_muxed4[0:0] 1'0 - attribute \src "ls180.v:6892.2-6905.9" + attribute \src "ls180.v:6944.2-6957.9" switch \main_sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -275553,11 +276971,19 @@ module \ls180 sync always update \builder_comb_t_array_muxed4 $0\builder_comb_t_array_muxed4[0:0] end - attribute \src "ls180.v:6907.1-6923.4" - process $proc$ls180.v:6907$2326 + attribute \src "ls180.v:695.12-695.57" + process $proc$ls180.v:695$3261 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_a[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_a $1\main_sdram_bankmachine3_cmd_payload_a[12:0] + end + attribute \src "ls180.v:6959.1-6975.4" + process $proc$ls180.v:6959$2392 assign { } { } assign $0\builder_comb_t_array_muxed5[0:0] 1'0 - attribute \src "ls180.v:6909.2-6922.9" + attribute \src "ls180.v:6961.2-6974.9" switch \main_sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -275575,27 +277001,19 @@ module \ls180 sync always update \builder_comb_t_array_muxed5 $0\builder_comb_t_array_muxed5[0:0] end - attribute \src "ls180.v:691.32-691.76" - process $proc$ls180.v:691$3132 + attribute \src "ls180.v:697.5-697.51" + process $proc$ls180.v:697$3262 assign { } { } - assign $1\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_twtpcon_ready $1\main_sdram_bankmachine2_twtpcon_ready[0:0] - end - attribute \src "ls180.v:692.11-692.55" - process $proc$ls180.v:692$3133 - assign { } { } - assign $1\main_sdram_bankmachine2_twtpcon_count[2:0] 3'000 + assign $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine2_twtpcon_count $1\main_sdram_bankmachine2_twtpcon_count[2:0] + update \main_sdram_bankmachine3_cmd_payload_cas $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] end - attribute \src "ls180.v:6924.1-6931.4" - process $proc$ls180.v:6924$2327 + attribute \src "ls180.v:6976.1-6983.4" + process $proc$ls180.v:6976$2393 assign { } { } assign $0\builder_comb_rhs_array_muxed12[21:0] 22'0000000000000000000000 - attribute \src "ls180.v:6926.2-6930.9" + attribute \src "ls180.v:6978.2-6982.9" switch \builder_roundrobin0_grant attribute \src "ls180.v:0.0-0.0" case @@ -275604,11 +277022,19 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed12 $0\builder_comb_rhs_array_muxed12[21:0] end - attribute \src "ls180.v:6932.1-6939.4" - process $proc$ls180.v:6932$2328 + attribute \src "ls180.v:698.5-698.51" + process $proc$ls180.v:698$3263 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_ras $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] + end + attribute \src "ls180.v:6984.1-6991.4" + process $proc$ls180.v:6984$2394 assign { } { } assign $0\builder_comb_rhs_array_muxed13[0:0] 1'0 - attribute \src "ls180.v:6934.2-6938.9" + attribute \src "ls180.v:6986.2-6990.9" switch \builder_roundrobin0_grant attribute \src "ls180.v:0.0-0.0" case @@ -275617,32 +277043,40 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed13 $0\builder_comb_rhs_array_muxed13[0:0] end - attribute \src "ls180.v:694.32-694.75" - process $proc$ls180.v:694$3134 + attribute \src "ls180.v:699.5-699.50" + process $proc$ls180.v:699$3264 assign { } { } - assign $0\main_sdram_bankmachine2_trccon_ready[0:0] 1'1 + assign $1\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'0 sync always - update \main_sdram_bankmachine2_trccon_ready $0\main_sdram_bankmachine2_trccon_ready[0:0] sync init + update \main_sdram_bankmachine3_cmd_payload_we $1\main_sdram_bankmachine3_cmd_payload_we[0:0] end - attribute \src "ls180.v:6940.1-6947.4" - process $proc$ls180.v:6940$2329 + attribute \src "ls180.v:6992.1-6999.4" + process $proc$ls180.v:6992$2395 assign { } { } assign $0\builder_comb_rhs_array_muxed14[0:0] 1'0 - attribute \src "ls180.v:6942.2-6946.9" + attribute \src "ls180.v:6994.2-6998.9" switch \builder_roundrobin0_grant attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed14[0:0] $and$ls180.v:6944$2342_Y + assign $0\builder_comb_rhs_array_muxed14[0:0] $and$ls180.v:6996$2408_Y end sync always update \builder_comb_rhs_array_muxed14 $0\builder_comb_rhs_array_muxed14[0:0] end - attribute \src "ls180.v:6948.1-6955.4" - process $proc$ls180.v:6948$2343 + attribute \src "ls180.v:700.5-700.54" + process $proc$ls180.v:700$3265 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_is_cmd $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] + end + attribute \src "ls180.v:7000.1-7007.4" + process $proc$ls180.v:7000$2409 assign { } { } assign $0\builder_comb_rhs_array_muxed15[21:0] 22'0000000000000000000000 - attribute \src "ls180.v:6950.2-6954.9" + attribute \src "ls180.v:7002.2-7006.9" switch \builder_roundrobin1_grant attribute \src "ls180.v:0.0-0.0" case @@ -275651,11 +277085,11 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed15 $0\builder_comb_rhs_array_muxed15[21:0] end - attribute \src "ls180.v:6956.1-6963.4" - process $proc$ls180.v:6956$2344 + attribute \src "ls180.v:7008.1-7015.4" + process $proc$ls180.v:7008$2410 assign { } { } assign $0\builder_comb_rhs_array_muxed16[0:0] 1'0 - attribute \src "ls180.v:6958.2-6962.9" + attribute \src "ls180.v:7010.2-7014.9" switch \builder_roundrobin1_grant attribute \src "ls180.v:0.0-0.0" case @@ -275664,32 +277098,40 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed16 $0\builder_comb_rhs_array_muxed16[0:0] end - attribute \src "ls180.v:696.32-696.76" - process $proc$ls180.v:696$3135 + attribute \src "ls180.v:701.5-701.55" + process $proc$ls180.v:701$3266 assign { } { } - assign $0\main_sdram_bankmachine2_trascon_ready[0:0] 1'1 + assign $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'0 sync always - update \main_sdram_bankmachine2_trascon_ready $0\main_sdram_bankmachine2_trascon_ready[0:0] sync init + update \main_sdram_bankmachine3_cmd_payload_is_read $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] end - attribute \src "ls180.v:6964.1-6971.4" - process $proc$ls180.v:6964$2345 + attribute \src "ls180.v:7016.1-7023.4" + process $proc$ls180.v:7016$2411 assign { } { } assign $0\builder_comb_rhs_array_muxed17[0:0] 1'0 - attribute \src "ls180.v:6966.2-6970.9" + attribute \src "ls180.v:7018.2-7022.9" switch \builder_roundrobin1_grant attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed17[0:0] $and$ls180.v:6968$2358_Y + assign $0\builder_comb_rhs_array_muxed17[0:0] $and$ls180.v:7020$2424_Y end sync always update \builder_comb_rhs_array_muxed17 $0\builder_comb_rhs_array_muxed17[0:0] end - attribute \src "ls180.v:6972.1-6979.4" - process $proc$ls180.v:6972$2359 + attribute \src "ls180.v:702.5-702.56" + process $proc$ls180.v:702$3267 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_is_write $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] + end + attribute \src "ls180.v:7024.1-7031.4" + process $proc$ls180.v:7024$2425 assign { } { } assign $0\builder_comb_rhs_array_muxed18[21:0] 22'0000000000000000000000 - attribute \src "ls180.v:6974.2-6978.9" + attribute \src "ls180.v:7026.2-7030.9" switch \builder_roundrobin2_grant attribute \src "ls180.v:0.0-0.0" case @@ -275698,11 +277140,19 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed18 $0\builder_comb_rhs_array_muxed18[21:0] end - attribute \src "ls180.v:6980.1-6987.4" - process $proc$ls180.v:6980$2360 + attribute \src "ls180.v:703.5-703.50" + process $proc$ls180.v:703$3268 + assign { } { } + assign $1\main_sdram_bankmachine3_auto_precharge[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_auto_precharge $1\main_sdram_bankmachine3_auto_precharge[0:0] + end + attribute \src "ls180.v:7032.1-7039.4" + process $proc$ls180.v:7032$2426 assign { } { } assign $0\builder_comb_rhs_array_muxed19[0:0] 1'0 - attribute \src "ls180.v:6982.2-6986.9" + attribute \src "ls180.v:7034.2-7038.9" switch \builder_roundrobin2_grant attribute \src "ls180.v:0.0-0.0" case @@ -275711,24 +277161,24 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed19 $0\builder_comb_rhs_array_muxed19[0:0] end - attribute \src "ls180.v:6988.1-6995.4" - process $proc$ls180.v:6988$2361 + attribute \src "ls180.v:7040.1-7047.4" + process $proc$ls180.v:7040$2427 assign { } { } assign $0\builder_comb_rhs_array_muxed20[0:0] 1'0 - attribute \src "ls180.v:6990.2-6994.9" + attribute \src "ls180.v:7042.2-7046.9" switch \builder_roundrobin2_grant attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed20[0:0] $and$ls180.v:6992$2374_Y + assign $0\builder_comb_rhs_array_muxed20[0:0] $and$ls180.v:7044$2440_Y end sync always update \builder_comb_rhs_array_muxed20 $0\builder_comb_rhs_array_muxed20[0:0] end - attribute \src "ls180.v:6996.1-7003.4" - process $proc$ls180.v:6996$2375 + attribute \src "ls180.v:7048.1-7055.4" + process $proc$ls180.v:7048$2441 assign { } { } assign $0\builder_comb_rhs_array_muxed21[21:0] 22'0000000000000000000000 - attribute \src "ls180.v:6998.2-7002.9" + attribute \src "ls180.v:7050.2-7054.9" switch \builder_roundrobin3_grant attribute \src "ls180.v:0.0-0.0" case @@ -275737,11 +277187,11 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed21 $0\builder_comb_rhs_array_muxed21[21:0] end - attribute \src "ls180.v:7004.1-7011.4" - process $proc$ls180.v:7004$2376 + attribute \src "ls180.v:7056.1-7063.4" + process $proc$ls180.v:7056$2442 assign { } { } assign $0\builder_comb_rhs_array_muxed22[0:0] 1'0 - attribute \src "ls180.v:7006.2-7010.9" + attribute \src "ls180.v:7058.2-7062.9" switch \builder_roundrobin3_grant attribute \src "ls180.v:0.0-0.0" case @@ -275750,42 +277200,50 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed22 $0\builder_comb_rhs_array_muxed22[0:0] end - attribute \src "ls180.v:7012.1-7019.4" - process $proc$ls180.v:7012$2377 + attribute \src "ls180.v:706.5-706.67" + process $proc$ls180.v:706$3269 + assign { } { } + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] 1'0 + sync always + update \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] + sync init + end + attribute \src "ls180.v:7064.1-7071.4" + process $proc$ls180.v:7064$2443 assign { } { } assign $0\builder_comb_rhs_array_muxed23[0:0] 1'0 - attribute \src "ls180.v:7014.2-7018.9" + attribute \src "ls180.v:7066.2-7070.9" switch \builder_roundrobin3_grant attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed23[0:0] $and$ls180.v:7016$2390_Y + assign $0\builder_comb_rhs_array_muxed23[0:0] $and$ls180.v:7068$2456_Y end sync always update \builder_comb_rhs_array_muxed23 $0\builder_comb_rhs_array_muxed23[0:0] end - attribute \src "ls180.v:702.5-702.51" - process $proc$ls180.v:702$3136 + attribute \src "ls180.v:707.5-707.66" + process $proc$ls180.v:707$3270 assign { } { } - assign $1\main_sdram_bankmachine3_req_wdata_ready[0:0] 1'0 + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] 1'0 sync always + update \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] sync init - update \main_sdram_bankmachine3_req_wdata_ready $1\main_sdram_bankmachine3_req_wdata_ready[0:0] end - attribute \src "ls180.v:7020.1-7039.4" - process $proc$ls180.v:7020$2391 + attribute \src "ls180.v:7072.1-7091.4" + process $proc$ls180.v:7072$2457 assign { } { } assign $0\builder_comb_rhs_array_muxed24[31:0] 0 - attribute \src "ls180.v:7022.2-7038.9" + attribute \src "ls180.v:7074.2-7090.9" switch \builder_grant attribute \src "ls180.v:0.0-0.0" case 3'000 - assign $0\builder_comb_rhs_array_muxed24[31:0] { 2'00 \main_libresocsim_interface0_converted_interface_adr } + assign $0\builder_comb_rhs_array_muxed24[31:0] { 3'000 \main_libresocsim_libresoc_ibus_adr } attribute \src "ls180.v:0.0-0.0" case 3'001 - assign $0\builder_comb_rhs_array_muxed24[31:0] { 2'00 \main_libresocsim_interface1_converted_interface_adr } + assign $0\builder_comb_rhs_array_muxed24[31:0] { 3'000 \main_libresocsim_libresoc_dbus_adr } attribute \src "ls180.v:0.0-0.0" case 3'010 - assign $0\builder_comb_rhs_array_muxed24[31:0] { 2'00 \main_libresocsim_interface2_converted_interface_adr } + assign $0\builder_comb_rhs_array_muxed24[31:0] { 3'000 \main_libresocsim_libresoc_jtag_wb_adr } attribute \src "ls180.v:0.0-0.0" case 3'011 assign $0\builder_comb_rhs_array_muxed24[31:0] \main_interface0_bus_adr @@ -275796,111 +277254,71 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed24 $0\builder_comb_rhs_array_muxed24[31:0] end - attribute \src "ls180.v:703.5-703.51" - process $proc$ls180.v:703$3137 - assign { } { } - assign $1\main_sdram_bankmachine3_req_rdata_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_req_rdata_valid $1\main_sdram_bankmachine3_req_rdata_valid[0:0] - end - attribute \src "ls180.v:7040.1-7059.4" - process $proc$ls180.v:7040$2392 + attribute \src "ls180.v:7092.1-7111.4" + process $proc$ls180.v:7092$2458 assign { } { } - assign $0\builder_comb_rhs_array_muxed25[31:0] 0 - attribute \src "ls180.v:7042.2-7058.9" + assign $0\builder_comb_rhs_array_muxed25[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "ls180.v:7094.2-7110.9" switch \builder_grant attribute \src "ls180.v:0.0-0.0" case 3'000 - assign $0\builder_comb_rhs_array_muxed25[31:0] \main_libresocsim_interface0_converted_interface_dat_w + assign $0\builder_comb_rhs_array_muxed25[63:0] \main_libresocsim_libresoc_ibus_dat_w attribute \src "ls180.v:0.0-0.0" case 3'001 - assign $0\builder_comb_rhs_array_muxed25[31:0] \main_libresocsim_interface1_converted_interface_dat_w + assign $0\builder_comb_rhs_array_muxed25[63:0] \main_libresocsim_libresoc_dbus_dat_w attribute \src "ls180.v:0.0-0.0" case 3'010 - assign $0\builder_comb_rhs_array_muxed25[31:0] \main_libresocsim_interface2_converted_interface_dat_w + assign $0\builder_comb_rhs_array_muxed25[63:0] \main_libresocsim_libresoc_jtag_wb_dat_w attribute \src "ls180.v:0.0-0.0" case 3'011 - assign $0\builder_comb_rhs_array_muxed25[31:0] \main_interface0_bus_dat_w + assign $0\builder_comb_rhs_array_muxed25[63:0] \main_interface0_bus_dat_w attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed25[31:0] \main_interface1_bus_dat_w + assign $0\builder_comb_rhs_array_muxed25[63:0] \main_interface1_bus_dat_w end sync always - update \builder_comb_rhs_array_muxed25 $0\builder_comb_rhs_array_muxed25[31:0] - end - attribute \src "ls180.v:705.5-705.47" - process $proc$ls180.v:705$3138 - assign { } { } - assign $1\main_sdram_bankmachine3_refresh_gnt[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_refresh_gnt $1\main_sdram_bankmachine3_refresh_gnt[0:0] - end - attribute \src "ls180.v:706.5-706.45" - process $proc$ls180.v:706$3139 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_valid $1\main_sdram_bankmachine3_cmd_valid[0:0] + update \builder_comb_rhs_array_muxed25 $0\builder_comb_rhs_array_muxed25[63:0] end - attribute \src "ls180.v:7060.1-7079.4" - process $proc$ls180.v:7060$2393 + attribute \src "ls180.v:7112.1-7131.4" + process $proc$ls180.v:7112$2459 assign { } { } - assign $0\builder_comb_rhs_array_muxed26[3:0] 4'0000 - attribute \src "ls180.v:7062.2-7078.9" + assign $0\builder_comb_rhs_array_muxed26[7:0] 8'00000000 + attribute \src "ls180.v:7114.2-7130.9" switch \builder_grant attribute \src "ls180.v:0.0-0.0" case 3'000 - assign $0\builder_comb_rhs_array_muxed26[3:0] \main_libresocsim_interface0_converted_interface_sel + assign $0\builder_comb_rhs_array_muxed26[7:0] \main_libresocsim_libresoc_ibus_sel attribute \src "ls180.v:0.0-0.0" case 3'001 - assign $0\builder_comb_rhs_array_muxed26[3:0] \main_libresocsim_interface1_converted_interface_sel + assign $0\builder_comb_rhs_array_muxed26[7:0] \main_libresocsim_libresoc_dbus_sel attribute \src "ls180.v:0.0-0.0" case 3'010 - assign $0\builder_comb_rhs_array_muxed26[3:0] \main_libresocsim_interface2_converted_interface_sel + assign $0\builder_comb_rhs_array_muxed26[7:0] \main_libresocsim_libresoc_jtag_wb_sel attribute \src "ls180.v:0.0-0.0" case 3'011 - assign $0\builder_comb_rhs_array_muxed26[3:0] \main_interface0_bus_sel + assign $0\builder_comb_rhs_array_muxed26[7:0] \main_interface0_bus_sel attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed26[3:0] \main_interface1_bus_sel + assign $0\builder_comb_rhs_array_muxed26[7:0] \main_interface1_bus_sel end sync always - update \builder_comb_rhs_array_muxed26 $0\builder_comb_rhs_array_muxed26[3:0] + update \builder_comb_rhs_array_muxed26 $0\builder_comb_rhs_array_muxed26[7:0] end - attribute \src "ls180.v:707.5-707.45" - process $proc$ls180.v:707$3140 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_ready $1\main_sdram_bankmachine3_cmd_ready[0:0] - end - attribute \src "ls180.v:708.12-708.57" - process $proc$ls180.v:708$3141 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_payload_a[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_bankmachine3_cmd_payload_a $1\main_sdram_bankmachine3_cmd_payload_a[12:0] - end - attribute \src "ls180.v:7080.1-7099.4" - process $proc$ls180.v:7080$2394 + attribute \src "ls180.v:7132.1-7151.4" + process $proc$ls180.v:7132$2460 assign { } { } assign $0\builder_comb_rhs_array_muxed27[0:0] 1'0 - attribute \src "ls180.v:7082.2-7098.9" + attribute \src "ls180.v:7134.2-7150.9" switch \builder_grant attribute \src "ls180.v:0.0-0.0" case 3'000 - assign $0\builder_comb_rhs_array_muxed27[0:0] \main_libresocsim_interface0_converted_interface_cyc + assign $0\builder_comb_rhs_array_muxed27[0:0] \main_libresocsim_libresoc_ibus_cyc attribute \src "ls180.v:0.0-0.0" case 3'001 - assign $0\builder_comb_rhs_array_muxed27[0:0] \main_libresocsim_interface1_converted_interface_cyc + assign $0\builder_comb_rhs_array_muxed27[0:0] \main_libresocsim_libresoc_dbus_cyc attribute \src "ls180.v:0.0-0.0" case 3'010 - assign $0\builder_comb_rhs_array_muxed27[0:0] \main_libresocsim_interface2_converted_interface_cyc + assign $0\builder_comb_rhs_array_muxed27[0:0] \main_libresocsim_libresoc_jtag_wb_cyc attribute \src "ls180.v:0.0-0.0" case 3'011 assign $0\builder_comb_rhs_array_muxed27[0:0] \main_interface0_bus_cyc @@ -275911,29 +277329,21 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed27 $0\builder_comb_rhs_array_muxed27[0:0] end - attribute \src "ls180.v:710.5-710.51" - process $proc$ls180.v:710$3142 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_payload_cas $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] - end - attribute \src "ls180.v:7100.1-7119.4" - process $proc$ls180.v:7100$2395 + attribute \src "ls180.v:7152.1-7171.4" + process $proc$ls180.v:7152$2461 assign { } { } assign $0\builder_comb_rhs_array_muxed28[0:0] 1'0 - attribute \src "ls180.v:7102.2-7118.9" + attribute \src "ls180.v:7154.2-7170.9" switch \builder_grant attribute \src "ls180.v:0.0-0.0" case 3'000 - assign $0\builder_comb_rhs_array_muxed28[0:0] \main_libresocsim_interface0_converted_interface_stb + assign $0\builder_comb_rhs_array_muxed28[0:0] \main_libresocsim_libresoc_ibus_stb attribute \src "ls180.v:0.0-0.0" case 3'001 - assign $0\builder_comb_rhs_array_muxed28[0:0] \main_libresocsim_interface1_converted_interface_stb + assign $0\builder_comb_rhs_array_muxed28[0:0] \main_libresocsim_libresoc_dbus_stb attribute \src "ls180.v:0.0-0.0" case 3'010 - assign $0\builder_comb_rhs_array_muxed28[0:0] \main_libresocsim_interface2_converted_interface_stb + assign $0\builder_comb_rhs_array_muxed28[0:0] \main_libresocsim_libresoc_jtag_wb_stb attribute \src "ls180.v:0.0-0.0" case 3'011 assign $0\builder_comb_rhs_array_muxed28[0:0] \main_interface0_bus_stb @@ -275944,37 +277354,21 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed28 $0\builder_comb_rhs_array_muxed28[0:0] end - attribute \src "ls180.v:711.5-711.51" - process $proc$ls180.v:711$3143 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_payload_ras $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] - end - attribute \src "ls180.v:712.5-712.50" - process $proc$ls180.v:712$3144 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_payload_we $1\main_sdram_bankmachine3_cmd_payload_we[0:0] - end - attribute \src "ls180.v:7120.1-7139.4" - process $proc$ls180.v:7120$2396 + attribute \src "ls180.v:7172.1-7191.4" + process $proc$ls180.v:7172$2462 assign { } { } assign $0\builder_comb_rhs_array_muxed29[0:0] 1'0 - attribute \src "ls180.v:7122.2-7138.9" + attribute \src "ls180.v:7174.2-7190.9" switch \builder_grant attribute \src "ls180.v:0.0-0.0" case 3'000 - assign $0\builder_comb_rhs_array_muxed29[0:0] \main_libresocsim_interface0_converted_interface_we + assign $0\builder_comb_rhs_array_muxed29[0:0] \main_libresocsim_libresoc_ibus_we attribute \src "ls180.v:0.0-0.0" case 3'001 - assign $0\builder_comb_rhs_array_muxed29[0:0] \main_libresocsim_interface1_converted_interface_we + assign $0\builder_comb_rhs_array_muxed29[0:0] \main_libresocsim_libresoc_dbus_we attribute \src "ls180.v:0.0-0.0" case 3'010 - assign $0\builder_comb_rhs_array_muxed29[0:0] \main_libresocsim_interface2_converted_interface_we + assign $0\builder_comb_rhs_array_muxed29[0:0] \main_libresocsim_libresoc_jtag_wb_we attribute \src "ls180.v:0.0-0.0" case 3'011 assign $0\builder_comb_rhs_array_muxed29[0:0] \main_interface0_bus_we @@ -275985,37 +277379,21 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed29 $0\builder_comb_rhs_array_muxed29[0:0] end - attribute \src "ls180.v:713.5-713.54" - process $proc$ls180.v:713$3145 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_payload_is_cmd $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] - end - attribute \src "ls180.v:714.5-714.55" - process $proc$ls180.v:714$3146 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_payload_is_read $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] - end - attribute \src "ls180.v:7140.1-7159.4" - process $proc$ls180.v:7140$2397 + attribute \src "ls180.v:7192.1-7211.4" + process $proc$ls180.v:7192$2463 assign { } { } assign $0\builder_comb_rhs_array_muxed30[2:0] 3'000 - attribute \src "ls180.v:7142.2-7158.9" + attribute \src "ls180.v:7194.2-7210.9" switch \builder_grant attribute \src "ls180.v:0.0-0.0" case 3'000 - assign $0\builder_comb_rhs_array_muxed30[2:0] \main_libresocsim_interface0_converted_interface_cti + assign $0\builder_comb_rhs_array_muxed30[2:0] \main_libresocsim_libresoc_ibus_cti attribute \src "ls180.v:0.0-0.0" case 3'001 - assign $0\builder_comb_rhs_array_muxed30[2:0] \main_libresocsim_interface1_converted_interface_cti + assign $0\builder_comb_rhs_array_muxed30[2:0] \main_libresocsim_libresoc_dbus_cti attribute \src "ls180.v:0.0-0.0" case 3'010 - assign $0\builder_comb_rhs_array_muxed30[2:0] \main_libresocsim_interface2_converted_interface_cti + assign $0\builder_comb_rhs_array_muxed30[2:0] \main_libresocsim_libresoc_jtag_wb_cti attribute \src "ls180.v:0.0-0.0" case 3'011 assign $0\builder_comb_rhs_array_muxed30[2:0] \main_interface0_bus_cti @@ -276026,37 +277404,21 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed30 $0\builder_comb_rhs_array_muxed30[2:0] end - attribute \src "ls180.v:715.5-715.56" - process $proc$ls180.v:715$3147 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_payload_is_write $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] - end - attribute \src "ls180.v:716.5-716.50" - process $proc$ls180.v:716$3148 - assign { } { } - assign $1\main_sdram_bankmachine3_auto_precharge[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_auto_precharge $1\main_sdram_bankmachine3_auto_precharge[0:0] - end - attribute \src "ls180.v:7160.1-7179.4" - process $proc$ls180.v:7160$2398 + attribute \src "ls180.v:7212.1-7231.4" + process $proc$ls180.v:7212$2464 assign { } { } assign $0\builder_comb_rhs_array_muxed31[1:0] 2'00 - attribute \src "ls180.v:7162.2-7178.9" + attribute \src "ls180.v:7214.2-7230.9" switch \builder_grant attribute \src "ls180.v:0.0-0.0" case 3'000 - assign $0\builder_comb_rhs_array_muxed31[1:0] \main_libresocsim_interface0_converted_interface_bte + assign $0\builder_comb_rhs_array_muxed31[1:0] \main_libresocsim_libresoc_ibus_bte attribute \src "ls180.v:0.0-0.0" case 3'001 - assign $0\builder_comb_rhs_array_muxed31[1:0] \main_libresocsim_interface1_converted_interface_bte + assign $0\builder_comb_rhs_array_muxed31[1:0] \main_libresocsim_libresoc_dbus_bte attribute \src "ls180.v:0.0-0.0" case 3'010 - assign $0\builder_comb_rhs_array_muxed31[1:0] \main_libresocsim_interface2_converted_interface_bte + assign $0\builder_comb_rhs_array_muxed31[1:0] \main_libresocsim_libresoc_jtag_wb_bte attribute \src "ls180.v:0.0-0.0" case 3'011 assign $0\builder_comb_rhs_array_muxed31[1:0] \main_interface0_bus_bte @@ -276067,11 +277429,27 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed31 $0\builder_comb_rhs_array_muxed31[1:0] end - attribute \src "ls180.v:7180.1-7196.4" - process $proc$ls180.v:7180$2399 + attribute \src "ls180.v:722.11-722.68" + process $proc$ls180.v:722$3271 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] 4'0000 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_lookahead_level $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] + end + attribute \src "ls180.v:723.5-723.64" + process $proc$ls180.v:723$3272 + assign { } { } + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] 1'0 + sync always + update \main_sdram_bankmachine3_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] + sync init + end + attribute \src "ls180.v:7232.1-7248.4" + process $proc$ls180.v:7232$2465 assign { } { } assign $0\builder_sync_rhs_array_muxed0[1:0] 2'00 - attribute \src "ls180.v:7182.2-7195.9" + attribute \src "ls180.v:7234.2-7247.9" switch \main_sdram_steerer_sel attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -276089,19 +277467,19 @@ module \ls180 sync always update \builder_sync_rhs_array_muxed0 $0\builder_sync_rhs_array_muxed0[1:0] end - attribute \src "ls180.v:719.5-719.67" - process $proc$ls180.v:719$3149 + attribute \src "ls180.v:724.11-724.70" + process $proc$ls180.v:724$3273 assign { } { } - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] 1'0 + assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] 3'000 sync always - update \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] sync init + update \main_sdram_bankmachine3_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] end - attribute \src "ls180.v:7197.1-7213.4" - process $proc$ls180.v:7197$2400 + attribute \src "ls180.v:7249.1-7265.4" + process $proc$ls180.v:7249$2466 assign { } { } assign $0\builder_sync_rhs_array_muxed1[12:0] 13'0000000000000 - attribute \src "ls180.v:7199.2-7212.9" + attribute \src "ls180.v:7251.2-7264.9" switch \main_sdram_steerer_sel attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -276119,137 +277497,137 @@ module \ls180 sync always update \builder_sync_rhs_array_muxed1 $0\builder_sync_rhs_array_muxed1[12:0] end - attribute \src "ls180.v:72.5-72.46" - process $proc$ls180.v:72$2901 + attribute \src "ls180.v:725.11-725.70" + process $proc$ls180.v:725$3274 assign { } { } - assign $1\main_libresocsim_libresoc_dbus_ack[0:0] 1'0 + assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] 3'000 sync always sync init - update \main_libresocsim_libresoc_dbus_ack $1\main_libresocsim_libresoc_dbus_ack[0:0] + update \main_sdram_bankmachine3_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] end - attribute \src "ls180.v:720.5-720.66" - process $proc$ls180.v:720$3150 + attribute \src "ls180.v:726.11-726.73" + process $proc$ls180.v:726$3275 assign { } { } - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] 1'0 + assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 sync always - update \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] sync init + update \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] end - attribute \src "ls180.v:7214.1-7230.4" - process $proc$ls180.v:7214$2401 + attribute \src "ls180.v:7266.1-7282.4" + process $proc$ls180.v:7266$2467 assign { } { } assign $0\builder_sync_rhs_array_muxed2[0:0] 1'0 - attribute \src "ls180.v:7216.2-7229.9" + attribute \src "ls180.v:7268.2-7281.9" switch \main_sdram_steerer_sel attribute \src "ls180.v:0.0-0.0" case 2'00 assign $0\builder_sync_rhs_array_muxed2[0:0] 1'0 attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7221$2403_Y + assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7273$2469_Y attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7224$2405_Y + assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7276$2471_Y attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7227$2407_Y + assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7279$2473_Y end sync always update \builder_sync_rhs_array_muxed2 $0\builder_sync_rhs_array_muxed2[0:0] end - attribute \src "ls180.v:7231.1-7247.4" - process $proc$ls180.v:7231$2408 + attribute \src "ls180.v:7283.1-7299.4" + process $proc$ls180.v:7283$2474 assign { } { } assign $0\builder_sync_rhs_array_muxed3[0:0] 1'0 - attribute \src "ls180.v:7233.2-7246.9" + attribute \src "ls180.v:7285.2-7298.9" switch \main_sdram_steerer_sel attribute \src "ls180.v:0.0-0.0" case 2'00 assign $0\builder_sync_rhs_array_muxed3[0:0] 1'0 attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7238$2410_Y + assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7290$2476_Y attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7241$2412_Y + assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7293$2478_Y attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7244$2414_Y + assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7296$2480_Y end sync always update \builder_sync_rhs_array_muxed3 $0\builder_sync_rhs_array_muxed3[0:0] end - attribute \src "ls180.v:7248.1-7264.4" - process $proc$ls180.v:7248$2415 + attribute \src "ls180.v:7300.1-7316.4" + process $proc$ls180.v:7300$2481 assign { } { } assign $0\builder_sync_rhs_array_muxed4[0:0] 1'0 - attribute \src "ls180.v:7250.2-7263.9" + attribute \src "ls180.v:7302.2-7315.9" switch \main_sdram_steerer_sel attribute \src "ls180.v:0.0-0.0" case 2'00 assign $0\builder_sync_rhs_array_muxed4[0:0] 1'0 attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7255$2417_Y + assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7307$2483_Y attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7258$2419_Y + assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7310$2485_Y attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7261$2421_Y + assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7313$2487_Y end sync always update \builder_sync_rhs_array_muxed4 $0\builder_sync_rhs_array_muxed4[0:0] end - attribute \src "ls180.v:7265.1-7281.4" - process $proc$ls180.v:7265$2422 + attribute \src "ls180.v:7317.1-7333.4" + process $proc$ls180.v:7317$2488 assign { } { } assign $0\builder_sync_rhs_array_muxed5[0:0] 1'0 - attribute \src "ls180.v:7267.2-7280.9" + attribute \src "ls180.v:7319.2-7332.9" switch \main_sdram_steerer_sel attribute \src "ls180.v:0.0-0.0" case 2'00 assign $0\builder_sync_rhs_array_muxed5[0:0] 1'0 attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7272$2424_Y + assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7324$2490_Y attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7275$2426_Y + assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7327$2492_Y attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7278$2428_Y + assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7330$2494_Y end sync always update \builder_sync_rhs_array_muxed5 $0\builder_sync_rhs_array_muxed5[0:0] end - attribute \src "ls180.v:7282.1-7298.4" - process $proc$ls180.v:7282$2429 + attribute \src "ls180.v:7334.1-7350.4" + process $proc$ls180.v:7334$2495 assign { } { } assign $0\builder_sync_rhs_array_muxed6[0:0] 1'0 - attribute \src "ls180.v:7284.2-7297.9" + attribute \src "ls180.v:7336.2-7349.9" switch \main_sdram_steerer_sel attribute \src "ls180.v:0.0-0.0" case 2'00 assign $0\builder_sync_rhs_array_muxed6[0:0] 1'0 attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7289$2431_Y + assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7341$2497_Y attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7292$2433_Y + assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7344$2499_Y attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7295$2435_Y + assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7347$2501_Y end sync always update \builder_sync_rhs_array_muxed6 $0\builder_sync_rhs_array_muxed6[0:0] end - attribute \src "ls180.v:7299.1-7327.4" - process $proc$ls180.v:7299$2436 + attribute \src "ls180.v:7351.1-7379.4" + process $proc$ls180.v:7351$2502 assign { } { } assign $0\builder_sync_f_array_muxed0[0:0] 1'0 - attribute \src "ls180.v:7301.2-7326.9" + attribute \src "ls180.v:7353.2-7378.9" switch \main_spimaster34_mosi_sel attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -276279,11 +277657,11 @@ module \ls180 sync always update \builder_sync_f_array_muxed0 $0\builder_sync_f_array_muxed0[0:0] end - attribute \src "ls180.v:7328.1-7356.4" - process $proc$ls180.v:7328$2437 + attribute \src "ls180.v:7380.1-7408.4" + process $proc$ls180.v:7380$2503 assign { } { } assign $0\builder_sync_f_array_muxed1[0:0] 1'0 - attribute \src "ls180.v:7330.2-7355.9" + attribute \src "ls180.v:7382.2-7407.9" switch \main_spisdcard_mosi_sel attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -276313,86 +277691,93 @@ module \ls180 sync always update \builder_sync_f_array_muxed1 $0\builder_sync_f_array_muxed1[0:0] end - attribute \src "ls180.v:735.11-735.68" - process $proc$ls180.v:735$3151 + attribute \src "ls180.v:74.11-74.52" + process $proc$ls180.v:74$3032 assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] 4'0000 + assign $0\main_libresocsim_libresoc_dbus_cti[2:0] 3'000 sync always + update \main_libresocsim_libresoc_dbus_cti $0\main_libresocsim_libresoc_dbus_cti[2:0] sync init - update \main_sdram_bankmachine3_cmd_buffer_lookahead_level $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] end - attribute \src "ls180.v:736.5-736.64" - process $proc$ls180.v:736$3152 + attribute \src "ls180.v:7466.1-7476.4" + process $proc$ls180.v:7466$2504 assign { } { } - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] 1'0 + assign $0\main_gpiotristateasic0_status[15:0] [15:8] 8'00000000 + assign $0\main_gpiotristateasic0_status[15:0] [0] \builder_multiregimpl1_regs1 + assign $0\main_gpiotristateasic0_status[15:0] [1] \builder_multiregimpl2_regs1 + assign $0\main_gpiotristateasic0_status[15:0] [2] \builder_multiregimpl3_regs1 + assign $0\main_gpiotristateasic0_status[15:0] [3] \builder_multiregimpl4_regs1 + assign $0\main_gpiotristateasic0_status[15:0] [4] \builder_multiregimpl5_regs1 + assign $0\main_gpiotristateasic0_status[15:0] [5] \builder_multiregimpl6_regs1 + assign $0\main_gpiotristateasic0_status[15:0] [6] \builder_multiregimpl7_regs1 + assign $0\main_gpiotristateasic0_status[15:0] [7] \builder_multiregimpl8_regs1 sync always - update \main_sdram_bankmachine3_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] - sync init + update \main_gpiotristateasic0_status $0\main_gpiotristateasic0_status[15:0] end - attribute \src "ls180.v:737.11-737.70" - process $proc$ls180.v:737$3153 + attribute \src "ls180.v:747.5-747.59" + process $proc$ls180.v:747$3276 assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] 3'000 + assign $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine3_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] + update \main_sdram_bankmachine3_cmd_buffer_source_valid $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] end - attribute \src "ls180.v:738.11-738.70" - process $proc$ls180.v:738$3154 + attribute \src "ls180.v:7477.1-7487.4" + process $proc$ls180.v:7477$2505 assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] 3'000 + assign $0\main_gpiotristateasic1_status[15:0] [7:0] 8'00000000 + assign $0\main_gpiotristateasic1_status[15:0] [8] \builder_multiregimpl9_regs1 + assign $0\main_gpiotristateasic1_status[15:0] [9] \builder_multiregimpl10_regs1 + assign $0\main_gpiotristateasic1_status[15:0] [10] \builder_multiregimpl11_regs1 + assign $0\main_gpiotristateasic1_status[15:0] [11] \builder_multiregimpl12_regs1 + assign $0\main_gpiotristateasic1_status[15:0] [12] \builder_multiregimpl13_regs1 + assign $0\main_gpiotristateasic1_status[15:0] [13] \builder_multiregimpl14_regs1 + assign $0\main_gpiotristateasic1_status[15:0] [14] \builder_multiregimpl15_regs1 + assign $0\main_gpiotristateasic1_status[15:0] [15] \builder_multiregimpl16_regs1 sync always - sync init - update \main_sdram_bankmachine3_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] + update \main_gpiotristateasic1_status $0\main_gpiotristateasic1_status[15:0] end - attribute \src "ls180.v:739.11-739.73" - process $proc$ls180.v:739$3155 + attribute \src "ls180.v:749.5-749.59" + process $proc$ls180.v:749$3277 assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + assign $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] + update \main_sdram_bankmachine3_cmd_buffer_source_first $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] end - attribute \src "ls180.v:74.5-74.46" - process $proc$ls180.v:74$2902 + attribute \src "ls180.v:75.11-75.52" + process $proc$ls180.v:75$3033 assign { } { } - assign $0\main_libresocsim_libresoc_dbus_err[0:0] 1'0 + assign $0\main_libresocsim_libresoc_dbus_bte[1:0] 2'00 sync always - update \main_libresocsim_libresoc_dbus_err $0\main_libresocsim_libresoc_dbus_err[0:0] + update \main_libresocsim_libresoc_dbus_bte $0\main_libresocsim_libresoc_dbus_bte[1:0] sync init end - attribute \src "ls180.v:7414.1-7432.4" - process $proc$ls180.v:7414$2438 - assign { } { } + attribute \src "ls180.v:750.5-750.58" + process $proc$ls180.v:750$3278 assign { } { } - assign $0\main_gpio_status[15:0] [0] \builder_multiregimpl1_regs1 - assign $0\main_gpio_status[15:0] [1] \builder_multiregimpl2_regs1 - assign $0\main_gpio_status[15:0] [2] \builder_multiregimpl3_regs1 - assign $0\main_gpio_status[15:0] [3] \builder_multiregimpl4_regs1 - assign $0\main_gpio_status[15:0] [4] \builder_multiregimpl5_regs1 - assign $0\main_gpio_status[15:0] [5] \builder_multiregimpl6_regs1 - assign $0\main_gpio_status[15:0] [6] \builder_multiregimpl7_regs1 - assign $0\main_gpio_status[15:0] [7] \builder_multiregimpl8_regs1 - assign $0\main_gpio_status[15:0] [8] \builder_multiregimpl9_regs1 - assign $0\main_gpio_status[15:0] [9] \builder_multiregimpl10_regs1 - assign $0\main_gpio_status[15:0] [10] \builder_multiregimpl11_regs1 - assign $0\main_gpio_status[15:0] [11] \builder_multiregimpl12_regs1 - assign $0\main_gpio_status[15:0] [12] \builder_multiregimpl13_regs1 - assign $0\main_gpio_status[15:0] [13] \builder_multiregimpl14_regs1 - assign $0\main_gpio_status[15:0] [14] \builder_multiregimpl15_regs1 - assign $0\main_gpio_status[15:0] [15] \builder_multiregimpl16_regs1 + assign $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] 1'0 sync always - update \main_gpio_status $0\main_gpio_status[15:0] + sync init + update \main_sdram_bankmachine3_cmd_buffer_source_last $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] end - attribute \src "ls180.v:7453.1-7455.4" - process $proc$ls180.v:7453$2439 + attribute \src "ls180.v:7508.1-7510.4" + process $proc$ls180.v:7508$2506 assign { } { } assign $0\main_int_rst[0:0] \sys_rst sync posedge \por_clk update \main_int_rst $0\main_int_rst[0:0] end - attribute \src "ls180.v:7457.1-7527.4" - process $proc$ls180.v:7457$2440 + attribute \src "ls180.v:751.5-751.64" + process $proc$ls180.v:751$3279 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_source_payload_we $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] + end + attribute \src "ls180.v:7512.1-7582.4" + process $proc$ls180.v:7512$2507 assign { } { } assign { } { } assign { } { } @@ -276468,7 +277853,7 @@ module \ls180 assign $0\sdram_dm[1:0] [0] \main_dfi_p0_wrdata_mask [0] assign $0\sdram_dm[1:0] [1] \main_dfi_p0_wrdata_mask [1] assign $0\sdram_clock[0:0] \sys_clk_1 - assign $0\sdcard_clk[0:0] $and$ls180.v:7514$2442_Y + assign $0\sdcard_clk[0:0] $and$ls180.v:7569$2509_Y assign $0\sdcard_cmd_oe[0:0] \main_sdphy_sdpads_cmd_oe assign $0\sdcard_cmd_o[0:0] \main_sdphy_sdpads_cmd_o assign $0\main_sdphy_sdpads_cmd_i[0:0] \sdcard_cmd_i @@ -276502,27 +277887,69 @@ module \ls180 update \main_sdphy_sdpads_cmd_i $0\main_sdphy_sdpads_cmd_i[0:0] update \main_sdphy_sdpads_data_i $0\main_sdphy_sdpads_data_i[3:0] end - attribute \src "ls180.v:7529.1-10156.4" - process $proc$ls180.v:7529$2443 + attribute \src "ls180.v:752.12-752.74" + process $proc$ls180.v:752$3280 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] + end + attribute \src "ls180.v:753.12-753.47" + process $proc$ls180.v:753$3281 + assign { } { } + assign $1\main_sdram_bankmachine3_row[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_bankmachine3_row $1\main_sdram_bankmachine3_row[12:0] + end + attribute \src "ls180.v:754.5-754.46" + process $proc$ls180.v:754$3282 + assign { } { } + assign $1\main_sdram_bankmachine3_row_opened[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_row_opened $1\main_sdram_bankmachine3_row_opened[0:0] + end + attribute \src "ls180.v:756.5-756.44" + process $proc$ls180.v:756$3283 + assign { } { } + assign $1\main_sdram_bankmachine3_row_open[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_row_open $1\main_sdram_bankmachine3_row_open[0:0] + end + attribute \src "ls180.v:757.5-757.45" + process $proc$ls180.v:757$3284 + assign { } { } + assign $1\main_sdram_bankmachine3_row_close[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_row_close $1\main_sdram_bankmachine3_row_close[0:0] + end + attribute \src "ls180.v:758.5-758.54" + process $proc$ls180.v:758$3285 + assign { } { } + assign $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_row_col_n_addr_sel $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] + end + attribute \src "ls180.v:7584.1-10223.4" + process $proc$ls180.v:7584$2510 assign $0\uart_tx[0:0] \uart_tx assign $0\spisdcard_clk[0:0] \spisdcard_clk assign $0\spisdcard_mosi[0:0] \spisdcard_mosi assign { } { } + assign $0\pwm[1:0] \pwm assign $0\spimaster_clk[0:0] \spimaster_clk assign $0\spimaster_mosi[0:0] \spimaster_mosi assign { } { } - assign $0\pwm[1:0] \pwm assign $0\main_libresocsim_reset_storage[0:0] \main_libresocsim_reset_storage assign { } { } assign $0\main_libresocsim_scratch_storage[31:0] \main_libresocsim_scratch_storage assign { } { } assign $0\main_libresocsim_bus_errors[31:0] \main_libresocsim_bus_errors - assign $0\main_libresocsim_converter0_counter[0:0] \main_libresocsim_converter0_counter - assign $0\main_libresocsim_converter0_dat_r[63:0] \main_libresocsim_converter0_dat_r - assign $0\main_libresocsim_converter1_counter[0:0] \main_libresocsim_converter1_counter - assign $0\main_libresocsim_converter1_dat_r[63:0] \main_libresocsim_converter1_dat_r - assign $0\main_libresocsim_converter2_counter[0:0] \main_libresocsim_converter2_counter - assign $0\main_libresocsim_converter2_dat_r[63:0] \main_libresocsim_converter2_dat_r assign { } { } assign $0\main_libresocsim_load_storage[31:0] \main_libresocsim_load_storage assign { } { } @@ -276541,6 +277968,10 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\main_converter0_counter[0:0] \main_converter0_counter + assign $0\main_converter0_dat_r[63:0] \main_converter0_dat_r + assign $0\main_converter1_counter[0:0] \main_converter1_counter + assign $0\main_converter1_dat_r[63:0] \main_converter1_dat_r assign { } { } assign { } { } assign $0\main_sdram_storage[3:0] \main_sdram_storage @@ -276629,6 +278060,8 @@ module \ls180 assign $0\main_sdram_twtrcon_count[2:0] \main_sdram_twtrcon_count assign $0\main_sdram_time0[4:0] \main_sdram_time0 assign $0\main_sdram_time1[3:0] \main_sdram_time1 + assign $0\main_socbushandler_counter[0:0] \main_socbushandler_counter + assign $0\main_socbushandler_dat_r[63:0] \main_socbushandler_dat_r assign $0\main_converter_counter[0:0] \main_converter_counter assign $0\main_converter_dat_r[31:0] \main_converter_dat_r assign $0\main_cmd_consumed[0:0] \main_cmd_consumed @@ -276663,9 +278096,9 @@ module \ls180 assign $0\main_uart_rx_fifo_level0[4:0] \main_uart_rx_fifo_level0 assign $0\main_uart_rx_fifo_produce[3:0] \main_uart_rx_fifo_produce assign $0\main_uart_rx_fifo_consume[3:0] \main_uart_rx_fifo_consume - assign $0\main_gpio_oe_storage[15:0] \main_gpio_oe_storage + assign $0\main_gpiotristateasic1_oe_storage[15:0] \main_gpiotristateasic1_oe_storage assign { } { } - assign $0\main_gpio_out_storage[15:0] \main_gpio_out_storage + assign $0\main_gpiotristateasic1_out_storage[15:0] \main_gpiotristateasic1_out_storage assign { } { } assign $0\main_spimaster5_miso[7:0] \main_spimaster5_miso assign $0\main_spimaster11_storage[15:0] \main_spimaster11_storage @@ -276808,9 +278241,9 @@ module \ls180 assign $0\main_sdblock2mem_fifo_consume[4:0] \main_sdblock2mem_fifo_consume assign $0\main_sdblock2mem_converter_source_first[0:0] \main_sdblock2mem_converter_source_first assign $0\main_sdblock2mem_converter_source_last[0:0] \main_sdblock2mem_converter_source_last - assign $0\main_sdblock2mem_converter_source_payload_data[31:0] \main_sdblock2mem_converter_source_payload_data - assign $0\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] \main_sdblock2mem_converter_source_payload_valid_token_count - assign $0\main_sdblock2mem_converter_demux[1:0] \main_sdblock2mem_converter_demux + assign $0\main_sdblock2mem_converter_source_payload_data[63:0] \main_sdblock2mem_converter_source_payload_data + assign $0\main_sdblock2mem_converter_source_payload_valid_token_count[3:0] \main_sdblock2mem_converter_source_payload_valid_token_count + assign $0\main_sdblock2mem_converter_demux[2:0] \main_sdblock2mem_converter_demux assign $0\main_sdblock2mem_converter_strobe_all[0:0] \main_sdblock2mem_converter_strobe_all assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] \main_sdblock2mem_wishbonedmawriter_base_storage assign { } { } @@ -276821,7 +278254,7 @@ module \ls180 assign $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] \main_sdblock2mem_wishbonedmawriter_loop_storage assign { } { } assign $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] \main_sdblock2mem_wishbonedmawriter_offset - assign $0\main_sdmem2block_dma_data[31:0] \main_sdmem2block_dma_data + assign $0\main_sdmem2block_dma_data[63:0] \main_sdmem2block_dma_data assign $0\main_sdmem2block_dma_base_storage[63:0] \main_sdmem2block_dma_base_storage assign { } { } assign $0\main_sdmem2block_dma_length_storage[31:0] \main_sdmem2block_dma_length_storage @@ -276831,7 +278264,7 @@ module \ls180 assign $0\main_sdmem2block_dma_loop_storage[0:0] \main_sdmem2block_dma_loop_storage assign { } { } assign $0\main_sdmem2block_dma_offset[31:0] \main_sdmem2block_dma_offset - assign $0\main_sdmem2block_converter_mux[1:0] \main_sdmem2block_converter_mux + assign $0\main_sdmem2block_converter_mux[2:0] \main_sdmem2block_converter_mux assign $0\main_sdmem2block_fifo_level[5:0] \main_sdmem2block_fifo_level assign $0\main_sdmem2block_fifo_produce[4:0] \main_sdmem2block_fifo_produce assign $0\main_sdmem2block_fifo_consume[4:0] \main_sdmem2block_fifo_consume @@ -276919,30 +278352,30 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_dummy[23:0] [0] $or$ls180.v:7530$2444_Y - assign $0\main_dummy[23:0] [1] $or$ls180.v:7531$2445_Y - assign $0\main_dummy[23:0] [2] $or$ls180.v:7532$2446_Y - assign $0\main_dummy[23:0] [3] $or$ls180.v:7533$2447_Y - assign $0\main_dummy[23:0] [4] $or$ls180.v:7534$2448_Y - assign $0\main_dummy[23:0] [5] $or$ls180.v:7535$2449_Y - assign $0\main_dummy[23:0] [6] $or$ls180.v:7536$2450_Y - assign $0\main_dummy[23:0] [7] $or$ls180.v:7537$2451_Y - assign $0\main_dummy[23:0] [8] $or$ls180.v:7538$2452_Y - assign $0\main_dummy[23:0] [9] $or$ls180.v:7539$2453_Y - assign $0\main_dummy[23:0] [10] $or$ls180.v:7540$2454_Y - assign $0\main_dummy[23:0] [11] $or$ls180.v:7541$2455_Y - assign $0\main_dummy[23:0] [12] $or$ls180.v:7542$2456_Y - assign $0\main_dummy[23:0] [13] $or$ls180.v:7543$2457_Y - assign $0\main_dummy[23:0] [14] $or$ls180.v:7544$2458_Y - assign $0\main_dummy[23:0] [15] $or$ls180.v:7545$2459_Y - assign $0\main_dummy[23:0] [16] $or$ls180.v:7546$2460_Y - assign $0\main_dummy[23:0] [17] $or$ls180.v:7547$2461_Y - assign $0\main_dummy[23:0] [18] $or$ls180.v:7548$2462_Y - assign $0\main_dummy[23:0] [19] $or$ls180.v:7549$2463_Y - assign $0\main_dummy[23:0] [20] $or$ls180.v:7550$2464_Y - assign $0\main_dummy[23:0] [21] $or$ls180.v:7551$2465_Y - assign $0\main_dummy[23:0] [22] $or$ls180.v:7552$2466_Y - assign $0\main_dummy[23:0] [23] $or$ls180.v:7553$2467_Y + assign $0\main_dummy[23:0] [0] $or$ls180.v:7585$2511_Y + assign $0\main_dummy[23:0] [1] $or$ls180.v:7586$2512_Y + assign $0\main_dummy[23:0] [2] $or$ls180.v:7587$2513_Y + assign $0\main_dummy[23:0] [3] $or$ls180.v:7588$2514_Y + assign $0\main_dummy[23:0] [4] $or$ls180.v:7589$2515_Y + assign $0\main_dummy[23:0] [5] $or$ls180.v:7590$2516_Y + assign $0\main_dummy[23:0] [6] $or$ls180.v:7591$2517_Y + assign $0\main_dummy[23:0] [7] $or$ls180.v:7592$2518_Y + assign $0\main_dummy[23:0] [8] $or$ls180.v:7593$2519_Y + assign $0\main_dummy[23:0] [9] $or$ls180.v:7594$2520_Y + assign $0\main_dummy[23:0] [10] $or$ls180.v:7595$2521_Y + assign $0\main_dummy[23:0] [11] $or$ls180.v:7596$2522_Y + assign $0\main_dummy[23:0] [12] $or$ls180.v:7597$2523_Y + assign $0\main_dummy[23:0] [13] $or$ls180.v:7598$2524_Y + assign $0\main_dummy[23:0] [14] $or$ls180.v:7599$2525_Y + assign $0\main_dummy[23:0] [15] $or$ls180.v:7600$2526_Y + assign $0\main_dummy[23:0] [16] $or$ls180.v:7601$2527_Y + assign $0\main_dummy[23:0] [17] $or$ls180.v:7602$2528_Y + assign $0\main_dummy[23:0] [18] $or$ls180.v:7603$2529_Y + assign $0\main_dummy[23:0] [19] $or$ls180.v:7604$2530_Y + assign $0\main_dummy[23:0] [20] $or$ls180.v:7605$2531_Y + assign $0\main_dummy[23:0] [21] $or$ls180.v:7606$2532_Y + assign $0\main_dummy[23:0] [22] $or$ls180.v:7607$2533_Y + assign $0\main_dummy[23:0] [23] $or$ls180.v:7608$2534_Y assign $0\builder_converter0_state[0:0] \builder_converter0_next_state assign $0\builder_converter1_state[0:0] \builder_converter1_next_state assign $0\builder_converter2_state[0:0] \builder_converter2_next_state @@ -276968,14 +278401,14 @@ module \ls180 assign $0\main_sdram_dfi_p0_cs_n[0:0] 1'0 assign $0\main_sdram_dfi_p0_bank[1:0] \builder_sync_rhs_array_muxed0 assign $0\main_sdram_dfi_p0_address[12:0] \builder_sync_rhs_array_muxed1 - assign $0\main_sdram_dfi_p0_cas_n[0:0] $not$ls180.v:8007$2573_Y - assign $0\main_sdram_dfi_p0_ras_n[0:0] $not$ls180.v:8008$2574_Y - assign $0\main_sdram_dfi_p0_we_n[0:0] $not$ls180.v:8009$2575_Y + assign $0\main_sdram_dfi_p0_cas_n[0:0] $not$ls180.v:8062$2640_Y + assign $0\main_sdram_dfi_p0_ras_n[0:0] $not$ls180.v:8063$2641_Y + assign $0\main_sdram_dfi_p0_we_n[0:0] $not$ls180.v:8064$2642_Y assign $0\main_sdram_dfi_p0_rddata_en[0:0] \builder_sync_rhs_array_muxed5 assign $0\main_sdram_dfi_p0_wrdata_en[0:0] \builder_sync_rhs_array_muxed6 assign $0\builder_multiplexer_state[2:0] \builder_multiplexer_next_state - assign $0\builder_new_master_wdata_ready[0:0] $or$ls180.v:8043$2593_Y - assign $0\builder_new_master_rdata_valid0[0:0] $or$ls180.v:8044$2605_Y + assign $0\builder_new_master_wdata_ready[0:0] $or$ls180.v:8098$2660_Y + assign $0\builder_new_master_rdata_valid0[0:0] $or$ls180.v:8099$2672_Y assign $0\builder_new_master_rdata_valid1[0:0] \builder_new_master_rdata_valid0 assign $0\builder_new_master_rdata_valid2[0:0] \builder_new_master_rdata_valid1 assign $0\builder_new_master_rdata_valid3[0:0] \builder_new_master_rdata_valid2 @@ -276985,11 +278418,11 @@ module \ls180 assign $0\main_uart_phy_rx_r[0:0] \main_uart_phy_rx assign $0\main_uart_tx_old_trigger[0:0] \main_uart_tx_trigger assign $0\main_uart_rx_old_trigger[0:0] \main_uart_rx_trigger - assign $0\main_spimaster30_clk_divider[15:0] $add$ls180.v:8202$2651_Y - assign $0\spisdcard_cs_n[0:0] $or$ls180.v:8211$2654_Y + assign $0\main_spimaster30_clk_divider[15:0] $add$ls180.v:8257$2718_Y + assign $0\spisdcard_cs_n[0:0] $or$ls180.v:8266$2721_Y assign $0\builder_spimaster0_state[1:0] \builder_spimaster0_next_state - assign $0\main_spisdcard_clk_divider1[15:0] $add$ls180.v:8237$2656_Y - assign $0\spimaster_cs_n[0:0] $or$ls180.v:8246$2659_Y + assign $0\main_spisdcard_clk_divider1[15:0] $add$ls180.v:8292$2723_Y + assign $0\spimaster_cs_n[0:0] $or$ls180.v:8301$2726_Y assign $0\builder_spimaster1_state[1:0] \builder_spimaster1_next_state assign $0\main_sdphy_clocker_clk_d[0:0] \main_sdphy_clocker_clk1 assign $0\main_sdphy_clocker_clk0[0:0] \main_sdphy_clocker_clk1 @@ -277010,8 +278443,8 @@ module \ls180 assign $0\main_libresocsim_reset_re[0:0] \builder_csrbank0_reset0_re assign $0\main_libresocsim_scratch_re[0:0] \builder_csrbank0_scratch0_re assign $0\builder_interface1_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_gpio_oe_re[0:0] \builder_csrbank1_oe0_re - assign $0\main_gpio_out_re[0:0] \builder_csrbank1_out0_re + assign $0\main_gpiotristateasic1_oe_re[0:0] \builder_csrbank1_oe0_re + assign $0\main_gpiotristateasic1_out_re[0:0] \builder_csrbank1_out0_re assign $0\builder_interface2_bank_bus_dat_r[7:0] 8'00000000 assign $0\main_i2c_re[0:0] \builder_csrbank2_w0_re assign $0\builder_interface3_bank_bus_dat_r[7:0] 8'00000000 @@ -277068,207 +278501,207 @@ module \ls180 assign $0\main_uart_phy_re[0:0] \builder_csrbank14_tuning_word0_re assign $0\builder_multiregimpl0_regs0[0:0] \uart_rx assign $0\builder_multiregimpl0_regs1[0:0] \builder_multiregimpl0_regs0 - assign $0\builder_multiregimpl1_regs0[0:0] \main_gpio_pads_i [0] + assign $0\builder_multiregimpl1_regs0[0:0] \main_gpiotristateasic0_pads_i [0] assign $0\builder_multiregimpl1_regs1[0:0] \builder_multiregimpl1_regs0 - assign $0\builder_multiregimpl2_regs0[0:0] \main_gpio_pads_i [1] + assign $0\builder_multiregimpl2_regs0[0:0] \main_gpiotristateasic0_pads_i [1] assign $0\builder_multiregimpl2_regs1[0:0] \builder_multiregimpl2_regs0 - assign $0\builder_multiregimpl3_regs0[0:0] \main_gpio_pads_i [2] + assign $0\builder_multiregimpl3_regs0[0:0] \main_gpiotristateasic0_pads_i [2] assign $0\builder_multiregimpl3_regs1[0:0] \builder_multiregimpl3_regs0 - assign $0\builder_multiregimpl4_regs0[0:0] \main_gpio_pads_i [3] + assign $0\builder_multiregimpl4_regs0[0:0] \main_gpiotristateasic0_pads_i [3] assign $0\builder_multiregimpl4_regs1[0:0] \builder_multiregimpl4_regs0 - assign $0\builder_multiregimpl5_regs0[0:0] \main_gpio_pads_i [4] + assign $0\builder_multiregimpl5_regs0[0:0] \main_gpiotristateasic0_pads_i [4] assign $0\builder_multiregimpl5_regs1[0:0] \builder_multiregimpl5_regs0 - assign $0\builder_multiregimpl6_regs0[0:0] \main_gpio_pads_i [5] + assign $0\builder_multiregimpl6_regs0[0:0] \main_gpiotristateasic0_pads_i [5] assign $0\builder_multiregimpl6_regs1[0:0] \builder_multiregimpl6_regs0 - assign $0\builder_multiregimpl7_regs0[0:0] \main_gpio_pads_i [6] + assign $0\builder_multiregimpl7_regs0[0:0] \main_gpiotristateasic0_pads_i [6] assign $0\builder_multiregimpl7_regs1[0:0] \builder_multiregimpl7_regs0 - assign $0\builder_multiregimpl8_regs0[0:0] \main_gpio_pads_i [7] + assign $0\builder_multiregimpl8_regs0[0:0] \main_gpiotristateasic0_pads_i [7] assign $0\builder_multiregimpl8_regs1[0:0] \builder_multiregimpl8_regs0 - assign $0\builder_multiregimpl9_regs0[0:0] \main_gpio_pads_i [8] + assign $0\builder_multiregimpl9_regs0[0:0] \main_gpiotristateasic1_pads_i [8] assign $0\builder_multiregimpl9_regs1[0:0] \builder_multiregimpl9_regs0 - assign $0\builder_multiregimpl10_regs0[0:0] \main_gpio_pads_i [9] + assign $0\builder_multiregimpl10_regs0[0:0] \main_gpiotristateasic1_pads_i [9] assign $0\builder_multiregimpl10_regs1[0:0] \builder_multiregimpl10_regs0 - assign $0\builder_multiregimpl11_regs0[0:0] \main_gpio_pads_i [10] + assign $0\builder_multiregimpl11_regs0[0:0] \main_gpiotristateasic1_pads_i [10] assign $0\builder_multiregimpl11_regs1[0:0] \builder_multiregimpl11_regs0 - assign $0\builder_multiregimpl12_regs0[0:0] \main_gpio_pads_i [11] + assign $0\builder_multiregimpl12_regs0[0:0] \main_gpiotristateasic1_pads_i [11] assign $0\builder_multiregimpl12_regs1[0:0] \builder_multiregimpl12_regs0 - assign $0\builder_multiregimpl13_regs0[0:0] \main_gpio_pads_i [12] + assign $0\builder_multiregimpl13_regs0[0:0] \main_gpiotristateasic1_pads_i [12] assign $0\builder_multiregimpl13_regs1[0:0] \builder_multiregimpl13_regs0 - assign $0\builder_multiregimpl14_regs0[0:0] \main_gpio_pads_i [13] + assign $0\builder_multiregimpl14_regs0[0:0] \main_gpiotristateasic1_pads_i [13] assign $0\builder_multiregimpl14_regs1[0:0] \builder_multiregimpl14_regs0 - assign $0\builder_multiregimpl15_regs0[0:0] \main_gpio_pads_i [14] + assign $0\builder_multiregimpl15_regs0[0:0] \main_gpiotristateasic1_pads_i [14] assign $0\builder_multiregimpl15_regs1[0:0] \builder_multiregimpl15_regs0 - assign $0\builder_multiregimpl16_regs0[0:0] \main_gpio_pads_i [15] + assign $0\builder_multiregimpl16_regs0[0:0] \main_gpiotristateasic1_pads_i [15] assign $0\builder_multiregimpl16_regs1[0:0] \builder_multiregimpl16_regs0 - attribute \src "ls180.v:7554.2-7556.5" - switch $or$ls180.v:7554$2468_Y - attribute \src "ls180.v:7554.6-7554.94" + attribute \src "ls180.v:7609.2-7611.5" + switch $or$ls180.v:7609$2535_Y + attribute \src "ls180.v:7609.6-7609.69" case 1'1 - assign $0\main_libresocsim_converter0_dat_r[63:0] \main_libresocsim_libresoc_ibus_dat_r + assign $0\main_converter0_dat_r[63:0] \main_interface0_converted_interface_dat_r case end - attribute \src "ls180.v:7558.2-7560.5" - switch \main_libresocsim_converter0_counter_converter0_next_value_ce - attribute \src "ls180.v:7558.6-7558.66" + attribute \src "ls180.v:7613.2-7615.5" + switch \main_converter0_counter_converter0_next_value_ce + attribute \src "ls180.v:7613.6-7613.54" case 1'1 - assign $0\main_libresocsim_converter0_counter[0:0] \main_libresocsim_converter0_counter_converter0_next_value + assign $0\main_converter0_counter[0:0] \main_converter0_counter_converter0_next_value case end - attribute \src "ls180.v:7561.2-7564.5" - switch \main_libresocsim_converter0_reset - attribute \src "ls180.v:7561.6-7561.39" + attribute \src "ls180.v:7616.2-7619.5" + switch \main_converter0_reset + attribute \src "ls180.v:7616.6-7616.27" case 1'1 - assign $0\main_libresocsim_converter0_counter[0:0] 1'0 + assign $0\main_converter0_counter[0:0] 1'0 assign $0\builder_converter0_state[0:0] 1'0 case end - attribute \src "ls180.v:7565.2-7567.5" - switch $or$ls180.v:7565$2469_Y - attribute \src "ls180.v:7565.6-7565.94" + attribute \src "ls180.v:7620.2-7622.5" + switch $or$ls180.v:7620$2536_Y + attribute \src "ls180.v:7620.6-7620.69" case 1'1 - assign $0\main_libresocsim_converter1_dat_r[63:0] \main_libresocsim_libresoc_dbus_dat_r + assign $0\main_converter1_dat_r[63:0] \main_interface1_converted_interface_dat_r case end - attribute \src "ls180.v:7569.2-7571.5" - switch \main_libresocsim_converter1_counter_converter1_next_value_ce - attribute \src "ls180.v:7569.6-7569.66" + attribute \src "ls180.v:7624.2-7626.5" + switch \main_converter1_counter_converter1_next_value_ce + attribute \src "ls180.v:7624.6-7624.54" case 1'1 - assign $0\main_libresocsim_converter1_counter[0:0] \main_libresocsim_converter1_counter_converter1_next_value + assign $0\main_converter1_counter[0:0] \main_converter1_counter_converter1_next_value case end - attribute \src "ls180.v:7572.2-7575.5" - switch \main_libresocsim_converter1_reset - attribute \src "ls180.v:7572.6-7572.39" + attribute \src "ls180.v:7627.2-7630.5" + switch \main_converter1_reset + attribute \src "ls180.v:7627.6-7627.27" case 1'1 - assign $0\main_libresocsim_converter1_counter[0:0] 1'0 + assign $0\main_converter1_counter[0:0] 1'0 assign $0\builder_converter1_state[0:0] 1'0 case end - attribute \src "ls180.v:7576.2-7578.5" - switch $or$ls180.v:7576$2470_Y - attribute \src "ls180.v:7576.6-7576.94" + attribute \src "ls180.v:7631.2-7633.5" + switch $or$ls180.v:7631$2537_Y + attribute \src "ls180.v:7631.6-7631.51" case 1'1 - assign $0\main_libresocsim_converter2_dat_r[63:0] \main_libresocsim_libresoc_jtag_wb_dat_r + assign $0\main_socbushandler_dat_r[63:0] \main_socbushandler_converted_interface_dat_r case end - attribute \src "ls180.v:7580.2-7582.5" - switch \main_libresocsim_converter2_counter_converter2_next_value_ce - attribute \src "ls180.v:7580.6-7580.66" + attribute \src "ls180.v:7635.2-7637.5" + switch \main_socbushandler_counter_converter2_next_value_ce + attribute \src "ls180.v:7635.6-7635.57" case 1'1 - assign $0\main_libresocsim_converter2_counter[0:0] \main_libresocsim_converter2_counter_converter2_next_value + assign $0\main_socbushandler_counter[0:0] \main_socbushandler_counter_converter2_next_value case end - attribute \src "ls180.v:7583.2-7586.5" - switch \main_libresocsim_converter2_reset - attribute \src "ls180.v:7583.6-7583.39" + attribute \src "ls180.v:7638.2-7641.5" + switch \main_socbushandler_reset + attribute \src "ls180.v:7638.6-7638.30" case 1'1 - assign $0\main_libresocsim_converter2_counter[0:0] 1'0 + assign $0\main_socbushandler_counter[0:0] 1'0 assign $0\builder_converter2_state[0:0] 1'0 case end - attribute \src "ls180.v:7587.2-7591.5" - switch $ne$ls180.v:7587$2471_Y - attribute \src "ls180.v:7587.6-7587.53" + attribute \src "ls180.v:7642.2-7646.5" + switch $ne$ls180.v:7642$2538_Y + attribute \src "ls180.v:7642.6-7642.53" case 1'1 - attribute \src "ls180.v:7588.3-7590.6" + attribute \src "ls180.v:7643.3-7645.6" switch \main_libresocsim_bus_error - attribute \src "ls180.v:7588.7-7588.33" + attribute \src "ls180.v:7643.7-7643.33" case 1'1 - assign $0\main_libresocsim_bus_errors[31:0] $add$ls180.v:7589$2472_Y + assign $0\main_libresocsim_bus_errors[31:0] $add$ls180.v:7644$2539_Y case end case end - attribute \src "ls180.v:7593.2-7595.5" - switch $and$ls180.v:7593$2475_Y - attribute \src "ls180.v:7593.6-7593.103" + attribute \src "ls180.v:7648.2-7650.5" + switch $and$ls180.v:7648$2542_Y + attribute \src "ls180.v:7648.6-7648.103" case 1'1 assign $0\main_libresocsim_ram_bus_ack[0:0] 1'1 case end - attribute \src "ls180.v:7596.2-7604.5" + attribute \src "ls180.v:7651.2-7659.5" switch \main_libresocsim_en_storage - attribute \src "ls180.v:7596.6-7596.33" + attribute \src "ls180.v:7651.6-7651.33" case 1'1 - attribute \src "ls180.v:7597.3-7601.6" - switch $eq$ls180.v:7597$2476_Y - attribute \src "ls180.v:7597.7-7597.39" + attribute \src "ls180.v:7652.3-7656.6" + switch $eq$ls180.v:7652$2543_Y + attribute \src "ls180.v:7652.7-7652.39" case 1'1 assign $0\main_libresocsim_value[31:0] \main_libresocsim_reload_storage - attribute \src "ls180.v:7599.7-7599.11" + attribute \src "ls180.v:7654.7-7654.11" case - assign $0\main_libresocsim_value[31:0] $sub$ls180.v:7600$2477_Y + assign $0\main_libresocsim_value[31:0] $sub$ls180.v:7655$2544_Y end - attribute \src "ls180.v:7602.6-7602.10" + attribute \src "ls180.v:7657.6-7657.10" case assign $0\main_libresocsim_value[31:0] \main_libresocsim_load_storage end - attribute \src "ls180.v:7605.2-7607.5" + attribute \src "ls180.v:7660.2-7662.5" switch \main_libresocsim_update_value_re - attribute \src "ls180.v:7605.6-7605.38" + attribute \src "ls180.v:7660.6-7660.38" case 1'1 assign $0\main_libresocsim_value_status[31:0] \main_libresocsim_value case end - attribute \src "ls180.v:7608.2-7610.5" + attribute \src "ls180.v:7663.2-7665.5" switch \main_libresocsim_zero_clear - attribute \src "ls180.v:7608.6-7608.33" + attribute \src "ls180.v:7663.6-7663.33" case 1'1 assign $0\main_libresocsim_zero_pending[0:0] 1'0 case end - attribute \src "ls180.v:7612.2-7614.5" - switch $and$ls180.v:7612$2479_Y - attribute \src "ls180.v:7612.6-7612.76" + attribute \src "ls180.v:7667.2-7669.5" + switch $and$ls180.v:7667$2546_Y + attribute \src "ls180.v:7667.6-7667.76" case 1'1 assign $0\main_libresocsim_zero_pending[0:0] 1'1 case end - attribute \src "ls180.v:7616.2-7618.5" - switch $and$ls180.v:7616$2482_Y - attribute \src "ls180.v:7616.6-7616.100" + attribute \src "ls180.v:7671.2-7673.5" + switch $and$ls180.v:7671$2549_Y + attribute \src "ls180.v:7671.6-7671.100" case 1'1 assign $0\main_interface0_ram_bus_ack[0:0] 1'1 case end - attribute \src "ls180.v:7620.2-7622.5" - switch $and$ls180.v:7620$2485_Y - attribute \src "ls180.v:7620.6-7620.100" + attribute \src "ls180.v:7675.2-7677.5" + switch $and$ls180.v:7675$2552_Y + attribute \src "ls180.v:7675.6-7675.100" case 1'1 assign $0\main_interface1_ram_bus_ack[0:0] 1'1 case end - attribute \src "ls180.v:7624.2-7626.5" - switch $and$ls180.v:7624$2488_Y - attribute \src "ls180.v:7624.6-7624.100" + attribute \src "ls180.v:7679.2-7681.5" + switch $and$ls180.v:7679$2555_Y + attribute \src "ls180.v:7679.6-7679.100" case 1'1 assign $0\main_interface2_ram_bus_ack[0:0] 1'1 case end - attribute \src "ls180.v:7629.2-7631.5" + attribute \src "ls180.v:7684.2-7686.5" switch \main_sdram_inti_p0_rddata_valid - attribute \src "ls180.v:7629.6-7629.37" + attribute \src "ls180.v:7684.6-7684.37" case 1'1 assign $0\main_sdram_status[15:0] \main_sdram_inti_p0_rddata case end - attribute \src "ls180.v:7632.2-7636.5" - switch $and$ls180.v:7632$2490_Y - attribute \src "ls180.v:7632.6-7632.57" + attribute \src "ls180.v:7687.2-7691.5" + switch $and$ls180.v:7687$2557_Y + attribute \src "ls180.v:7687.6-7687.57" case 1'1 - assign $0\main_sdram_timer_count1[9:0] $sub$ls180.v:7633$2491_Y - attribute \src "ls180.v:7634.6-7634.10" + assign $0\main_sdram_timer_count1[9:0] $sub$ls180.v:7688$2558_Y + attribute \src "ls180.v:7689.6-7689.10" case assign $0\main_sdram_timer_count1[9:0] 10'1100001101 end - attribute \src "ls180.v:7638.2-7644.5" + attribute \src "ls180.v:7693.2-7699.5" switch \main_sdram_postponer_req_i - attribute \src "ls180.v:7638.6-7638.32" + attribute \src "ls180.v:7693.6-7693.32" case 1'1 - assign $0\main_sdram_postponer_count[0:0] $sub$ls180.v:7639$2492_Y - attribute \src "ls180.v:7640.3-7643.6" - switch $eq$ls180.v:7640$2493_Y - attribute \src "ls180.v:7640.7-7640.43" + assign $0\main_sdram_postponer_count[0:0] $sub$ls180.v:7694$2559_Y + attribute \src "ls180.v:7695.3-7698.6" + switch $eq$ls180.v:7695$2560_Y + attribute \src "ls180.v:7695.7-7695.43" case 1'1 assign $0\main_sdram_postponer_count[0:0] 1'0 assign $0\main_sdram_postponer_req_o[0:0] 1'1 @@ -277276,30 +278709,30 @@ module \ls180 end case end - attribute \src "ls180.v:7645.2-7653.5" + attribute \src "ls180.v:7700.2-7708.5" switch \main_sdram_sequencer_start0 - attribute \src "ls180.v:7645.6-7645.33" + attribute \src "ls180.v:7700.6-7700.33" case 1'1 assign $0\main_sdram_sequencer_count[0:0] 1'0 - attribute \src "ls180.v:7647.6-7647.10" + attribute \src "ls180.v:7702.6-7702.10" case - attribute \src "ls180.v:7648.3-7652.6" + attribute \src "ls180.v:7703.3-7707.6" switch \main_sdram_sequencer_done1 - attribute \src "ls180.v:7648.7-7648.33" + attribute \src "ls180.v:7703.7-7703.33" case 1'1 - attribute \src "ls180.v:7649.4-7651.7" - switch $ne$ls180.v:7649$2494_Y - attribute \src "ls180.v:7649.8-7649.44" + attribute \src "ls180.v:7704.4-7706.7" + switch $ne$ls180.v:7704$2561_Y + attribute \src "ls180.v:7704.8-7704.44" case 1'1 - assign $0\main_sdram_sequencer_count[0:0] $sub$ls180.v:7650$2495_Y + assign $0\main_sdram_sequencer_count[0:0] $sub$ls180.v:7705$2562_Y case end case end end - attribute \src "ls180.v:7660.2-7666.5" - switch $and$ls180.v:7660$2497_Y - attribute \src "ls180.v:7660.6-7660.76" + attribute \src "ls180.v:7715.2-7721.5" + switch $and$ls180.v:7715$2564_Y + attribute \src "ls180.v:7715.6-7715.76" case 1'1 assign $0\main_sdram_cmd_payload_a[12:0] 13'0010000000000 assign $0\main_sdram_cmd_payload_ba[1:0] 2'00 @@ -277308,9 +278741,9 @@ module \ls180 assign $0\main_sdram_cmd_payload_we[0:0] 1'1 case end - attribute \src "ls180.v:7667.2-7673.5" - switch $eq$ls180.v:7667$2498_Y - attribute \src "ls180.v:7667.6-7667.44" + attribute \src "ls180.v:7722.2-7728.5" + switch $eq$ls180.v:7722$2565_Y + attribute \src "ls180.v:7722.6-7722.44" case 1'1 assign $0\main_sdram_cmd_payload_a[12:0] 13'0000000000000 assign $0\main_sdram_cmd_payload_ba[1:0] 2'00 @@ -277319,9 +278752,9 @@ module \ls180 assign $0\main_sdram_cmd_payload_we[0:0] 1'0 case end - attribute \src "ls180.v:7674.2-7681.5" - switch $eq$ls180.v:7674$2499_Y - attribute \src "ls180.v:7674.6-7674.44" + attribute \src "ls180.v:7729.2-7736.5" + switch $eq$ls180.v:7729$2566_Y + attribute \src "ls180.v:7729.6-7729.44" case 1'1 assign $0\main_sdram_cmd_payload_a[12:0] 13'0000000000000 assign $0\main_sdram_cmd_payload_ba[1:0] 2'00 @@ -277331,83 +278764,83 @@ module \ls180 assign $0\main_sdram_sequencer_done1[0:0] 1'1 case end - attribute \src "ls180.v:7682.2-7692.5" - switch $eq$ls180.v:7682$2500_Y - attribute \src "ls180.v:7682.6-7682.44" + attribute \src "ls180.v:7737.2-7747.5" + switch $eq$ls180.v:7737$2567_Y + attribute \src "ls180.v:7737.6-7737.44" case 1'1 assign $0\main_sdram_sequencer_counter[3:0] 4'0000 - attribute \src "ls180.v:7684.6-7684.10" + attribute \src "ls180.v:7739.6-7739.10" case - attribute \src "ls180.v:7685.3-7691.6" - switch $ne$ls180.v:7685$2501_Y - attribute \src "ls180.v:7685.7-7685.45" + attribute \src "ls180.v:7740.3-7746.6" + switch $ne$ls180.v:7740$2568_Y + attribute \src "ls180.v:7740.7-7740.45" case 1'1 - assign $0\main_sdram_sequencer_counter[3:0] $add$ls180.v:7686$2502_Y - attribute \src "ls180.v:7687.7-7687.11" + assign $0\main_sdram_sequencer_counter[3:0] $add$ls180.v:7741$2569_Y + attribute \src "ls180.v:7742.7-7742.11" case - attribute \src "ls180.v:7688.4-7690.7" + attribute \src "ls180.v:7743.4-7745.7" switch \main_sdram_sequencer_start1 - attribute \src "ls180.v:7688.8-7688.35" + attribute \src "ls180.v:7743.8-7743.35" case 1'1 assign $0\main_sdram_sequencer_counter[3:0] 4'0001 case end end end - attribute \src "ls180.v:7694.2-7701.5" + attribute \src "ls180.v:7749.2-7756.5" switch \main_sdram_bankmachine0_row_close - attribute \src "ls180.v:7694.6-7694.39" + attribute \src "ls180.v:7749.6-7749.39" case 1'1 assign $0\main_sdram_bankmachine0_row_opened[0:0] 1'0 - attribute \src "ls180.v:7696.6-7696.10" + attribute \src "ls180.v:7751.6-7751.10" case - attribute \src "ls180.v:7697.3-7700.6" + attribute \src "ls180.v:7752.3-7755.6" switch \main_sdram_bankmachine0_row_open - attribute \src "ls180.v:7697.7-7697.39" + attribute \src "ls180.v:7752.7-7752.39" case 1'1 assign $0\main_sdram_bankmachine0_row_opened[0:0] 1'1 assign $0\main_sdram_bankmachine0_row[12:0] \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] case end end - attribute \src "ls180.v:7702.2-7704.5" - switch $and$ls180.v:7702$2505_Y - attribute \src "ls180.v:7702.6-7702.191" + attribute \src "ls180.v:7757.2-7759.5" + switch $and$ls180.v:7757$2572_Y + attribute \src "ls180.v:7757.6-7757.191" case 1'1 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7703$2506_Y + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7758$2573_Y case end - attribute \src "ls180.v:7705.2-7707.5" + attribute \src "ls180.v:7760.2-7762.5" switch \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7705.6-7705.58" + attribute \src "ls180.v:7760.6-7760.58" case 1'1 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7706$2507_Y + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7761$2574_Y case end - attribute \src "ls180.v:7708.2-7716.5" - switch $and$ls180.v:7708$2510_Y - attribute \src "ls180.v:7708.6-7708.191" + attribute \src "ls180.v:7763.2-7771.5" + switch $and$ls180.v:7763$2577_Y + attribute \src "ls180.v:7763.6-7763.191" case 1'1 - attribute \src "ls180.v:7709.3-7711.6" - switch $not$ls180.v:7709$2511_Y - attribute \src "ls180.v:7709.7-7709.62" + attribute \src "ls180.v:7764.3-7766.6" + switch $not$ls180.v:7764$2578_Y + attribute \src "ls180.v:7764.7-7764.62" case 1'1 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7710$2512_Y + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7765$2579_Y case end - attribute \src "ls180.v:7712.6-7712.10" + attribute \src "ls180.v:7767.6-7767.10" case - attribute \src "ls180.v:7713.3-7715.6" + attribute \src "ls180.v:7768.3-7770.6" switch \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7713.7-7713.59" + attribute \src "ls180.v:7768.7-7768.59" case 1'1 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7714$2513_Y + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7769$2580_Y case end end - attribute \src "ls180.v:7717.2-7723.5" - switch $or$ls180.v:7717$2515_Y - attribute \src "ls180.v:7717.6-7717.108" + attribute \src "ls180.v:7772.2-7778.5" + switch $or$ls180.v:7772$2582_Y + attribute \src "ls180.v:7772.6-7772.108" case 1'1 assign $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_valid assign $0\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_first @@ -277416,27 +278849,27 @@ module \ls180 assign $0\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine0_cmd_buffer_sink_payload_addr case end - attribute \src "ls180.v:7724.2-7738.5" + attribute \src "ls180.v:7779.2-7793.5" switch \main_sdram_bankmachine0_twtpcon_valid - attribute \src "ls180.v:7724.6-7724.43" + attribute \src "ls180.v:7779.6-7779.43" case 1'1 assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] 3'100 - attribute \src "ls180.v:7726.3-7730.6" + attribute \src "ls180.v:7781.3-7785.6" switch 1'0 - attribute \src "ls180.v:7728.7-7728.11" + attribute \src "ls180.v:7783.7-7783.11" case assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'0 end - attribute \src "ls180.v:7731.6-7731.10" + attribute \src "ls180.v:7786.6-7786.10" case - attribute \src "ls180.v:7732.3-7737.6" - switch $not$ls180.v:7732$2516_Y - attribute \src "ls180.v:7732.7-7732.47" + attribute \src "ls180.v:7787.3-7792.6" + switch $not$ls180.v:7787$2583_Y + attribute \src "ls180.v:7787.7-7787.47" case 1'1 - assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] $sub$ls180.v:7733$2517_Y - attribute \src "ls180.v:7734.4-7736.7" - switch $eq$ls180.v:7734$2518_Y - attribute \src "ls180.v:7734.8-7734.55" + assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] $sub$ls180.v:7788$2584_Y + attribute \src "ls180.v:7789.4-7791.7" + switch $eq$ls180.v:7789$2585_Y + attribute \src "ls180.v:7789.8-7789.55" case 1'1 assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'1 case @@ -277444,60 +278877,60 @@ module \ls180 case end end - attribute \src "ls180.v:7740.2-7747.5" + attribute \src "ls180.v:7795.2-7802.5" switch \main_sdram_bankmachine1_row_close - attribute \src "ls180.v:7740.6-7740.39" + attribute \src "ls180.v:7795.6-7795.39" case 1'1 assign $0\main_sdram_bankmachine1_row_opened[0:0] 1'0 - attribute \src "ls180.v:7742.6-7742.10" + attribute \src "ls180.v:7797.6-7797.10" case - attribute \src "ls180.v:7743.3-7746.6" + attribute \src "ls180.v:7798.3-7801.6" switch \main_sdram_bankmachine1_row_open - attribute \src "ls180.v:7743.7-7743.39" + attribute \src "ls180.v:7798.7-7798.39" case 1'1 assign $0\main_sdram_bankmachine1_row_opened[0:0] 1'1 assign $0\main_sdram_bankmachine1_row[12:0] \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] case end end - attribute \src "ls180.v:7748.2-7750.5" - switch $and$ls180.v:7748$2521_Y - attribute \src "ls180.v:7748.6-7748.191" + attribute \src "ls180.v:7803.2-7805.5" + switch $and$ls180.v:7803$2588_Y + attribute \src "ls180.v:7803.6-7803.191" case 1'1 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7749$2522_Y + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7804$2589_Y case end - attribute \src "ls180.v:7751.2-7753.5" + attribute \src "ls180.v:7806.2-7808.5" switch \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7751.6-7751.58" + attribute \src "ls180.v:7806.6-7806.58" case 1'1 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7752$2523_Y + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7807$2590_Y case end - attribute \src "ls180.v:7754.2-7762.5" - switch $and$ls180.v:7754$2526_Y - attribute \src "ls180.v:7754.6-7754.191" + attribute \src "ls180.v:7809.2-7817.5" + switch $and$ls180.v:7809$2593_Y + attribute \src "ls180.v:7809.6-7809.191" case 1'1 - attribute \src "ls180.v:7755.3-7757.6" - switch $not$ls180.v:7755$2527_Y - attribute \src "ls180.v:7755.7-7755.62" + attribute \src "ls180.v:7810.3-7812.6" + switch $not$ls180.v:7810$2594_Y + attribute \src "ls180.v:7810.7-7810.62" case 1'1 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7756$2528_Y + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7811$2595_Y case end - attribute \src "ls180.v:7758.6-7758.10" + attribute \src "ls180.v:7813.6-7813.10" case - attribute \src "ls180.v:7759.3-7761.6" + attribute \src "ls180.v:7814.3-7816.6" switch \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7759.7-7759.59" + attribute \src "ls180.v:7814.7-7814.59" case 1'1 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7760$2529_Y + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7815$2596_Y case end end - attribute \src "ls180.v:7763.2-7769.5" - switch $or$ls180.v:7763$2531_Y - attribute \src "ls180.v:7763.6-7763.108" + attribute \src "ls180.v:7818.2-7824.5" + switch $or$ls180.v:7818$2598_Y + attribute \src "ls180.v:7818.6-7818.108" case 1'1 assign $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_valid assign $0\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_first @@ -277506,27 +278939,27 @@ module \ls180 assign $0\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine1_cmd_buffer_sink_payload_addr case end - attribute \src "ls180.v:7770.2-7784.5" + attribute \src "ls180.v:7825.2-7839.5" switch \main_sdram_bankmachine1_twtpcon_valid - attribute \src "ls180.v:7770.6-7770.43" + attribute \src "ls180.v:7825.6-7825.43" case 1'1 assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] 3'100 - attribute \src "ls180.v:7772.3-7776.6" + attribute \src "ls180.v:7827.3-7831.6" switch 1'0 - attribute \src "ls180.v:7774.7-7774.11" + attribute \src "ls180.v:7829.7-7829.11" case assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'0 end - attribute \src "ls180.v:7777.6-7777.10" + attribute \src "ls180.v:7832.6-7832.10" case - attribute \src "ls180.v:7778.3-7783.6" - switch $not$ls180.v:7778$2532_Y - attribute \src "ls180.v:7778.7-7778.47" + attribute \src "ls180.v:7833.3-7838.6" + switch $not$ls180.v:7833$2599_Y + attribute \src "ls180.v:7833.7-7833.47" case 1'1 - assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] $sub$ls180.v:7779$2533_Y - attribute \src "ls180.v:7780.4-7782.7" - switch $eq$ls180.v:7780$2534_Y - attribute \src "ls180.v:7780.8-7780.55" + assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] $sub$ls180.v:7834$2600_Y + attribute \src "ls180.v:7835.4-7837.7" + switch $eq$ls180.v:7835$2601_Y + attribute \src "ls180.v:7835.8-7835.55" case 1'1 assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'1 case @@ -277534,60 +278967,60 @@ module \ls180 case end end - attribute \src "ls180.v:7786.2-7793.5" + attribute \src "ls180.v:7841.2-7848.5" switch \main_sdram_bankmachine2_row_close - attribute \src "ls180.v:7786.6-7786.39" + attribute \src "ls180.v:7841.6-7841.39" case 1'1 assign $0\main_sdram_bankmachine2_row_opened[0:0] 1'0 - attribute \src "ls180.v:7788.6-7788.10" + attribute \src "ls180.v:7843.6-7843.10" case - attribute \src "ls180.v:7789.3-7792.6" + attribute \src "ls180.v:7844.3-7847.6" switch \main_sdram_bankmachine2_row_open - attribute \src "ls180.v:7789.7-7789.39" + attribute \src "ls180.v:7844.7-7844.39" case 1'1 assign $0\main_sdram_bankmachine2_row_opened[0:0] 1'1 assign $0\main_sdram_bankmachine2_row[12:0] \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] case end end - attribute \src "ls180.v:7794.2-7796.5" - switch $and$ls180.v:7794$2537_Y - attribute \src "ls180.v:7794.6-7794.191" + attribute \src "ls180.v:7849.2-7851.5" + switch $and$ls180.v:7849$2604_Y + attribute \src "ls180.v:7849.6-7849.191" case 1'1 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7795$2538_Y + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7850$2605_Y case end - attribute \src "ls180.v:7797.2-7799.5" + attribute \src "ls180.v:7852.2-7854.5" switch \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7797.6-7797.58" + attribute \src "ls180.v:7852.6-7852.58" case 1'1 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7798$2539_Y + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7853$2606_Y case end - attribute \src "ls180.v:7800.2-7808.5" - switch $and$ls180.v:7800$2542_Y - attribute \src "ls180.v:7800.6-7800.191" + attribute \src "ls180.v:7855.2-7863.5" + switch $and$ls180.v:7855$2609_Y + attribute \src "ls180.v:7855.6-7855.191" case 1'1 - attribute \src "ls180.v:7801.3-7803.6" - switch $not$ls180.v:7801$2543_Y - attribute \src "ls180.v:7801.7-7801.62" + attribute \src "ls180.v:7856.3-7858.6" + switch $not$ls180.v:7856$2610_Y + attribute \src "ls180.v:7856.7-7856.62" case 1'1 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7802$2544_Y + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7857$2611_Y case end - attribute \src "ls180.v:7804.6-7804.10" + attribute \src "ls180.v:7859.6-7859.10" case - attribute \src "ls180.v:7805.3-7807.6" + attribute \src "ls180.v:7860.3-7862.6" switch \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7805.7-7805.59" + attribute \src "ls180.v:7860.7-7860.59" case 1'1 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7806$2545_Y + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7861$2612_Y case end end - attribute \src "ls180.v:7809.2-7815.5" - switch $or$ls180.v:7809$2547_Y - attribute \src "ls180.v:7809.6-7809.108" + attribute \src "ls180.v:7864.2-7870.5" + switch $or$ls180.v:7864$2614_Y + attribute \src "ls180.v:7864.6-7864.108" case 1'1 assign $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_valid assign $0\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_first @@ -277596,27 +279029,27 @@ module \ls180 assign $0\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine2_cmd_buffer_sink_payload_addr case end - attribute \src "ls180.v:7816.2-7830.5" + attribute \src "ls180.v:7871.2-7885.5" switch \main_sdram_bankmachine2_twtpcon_valid - attribute \src "ls180.v:7816.6-7816.43" + attribute \src "ls180.v:7871.6-7871.43" case 1'1 assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] 3'100 - attribute \src "ls180.v:7818.3-7822.6" + attribute \src "ls180.v:7873.3-7877.6" switch 1'0 - attribute \src "ls180.v:7820.7-7820.11" + attribute \src "ls180.v:7875.7-7875.11" case assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'0 end - attribute \src "ls180.v:7823.6-7823.10" + attribute \src "ls180.v:7878.6-7878.10" case - attribute \src "ls180.v:7824.3-7829.6" - switch $not$ls180.v:7824$2548_Y - attribute \src "ls180.v:7824.7-7824.47" + attribute \src "ls180.v:7879.3-7884.6" + switch $not$ls180.v:7879$2615_Y + attribute \src "ls180.v:7879.7-7879.47" case 1'1 - assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] $sub$ls180.v:7825$2549_Y - attribute \src "ls180.v:7826.4-7828.7" - switch $eq$ls180.v:7826$2550_Y - attribute \src "ls180.v:7826.8-7826.55" + assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] $sub$ls180.v:7880$2616_Y + attribute \src "ls180.v:7881.4-7883.7" + switch $eq$ls180.v:7881$2617_Y + attribute \src "ls180.v:7881.8-7881.55" case 1'1 assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'1 case @@ -277624,60 +279057,60 @@ module \ls180 case end end - attribute \src "ls180.v:7832.2-7839.5" + attribute \src "ls180.v:7887.2-7894.5" switch \main_sdram_bankmachine3_row_close - attribute \src "ls180.v:7832.6-7832.39" + attribute \src "ls180.v:7887.6-7887.39" case 1'1 assign $0\main_sdram_bankmachine3_row_opened[0:0] 1'0 - attribute \src "ls180.v:7834.6-7834.10" + attribute \src "ls180.v:7889.6-7889.10" case - attribute \src "ls180.v:7835.3-7838.6" + attribute \src "ls180.v:7890.3-7893.6" switch \main_sdram_bankmachine3_row_open - attribute \src "ls180.v:7835.7-7835.39" + attribute \src "ls180.v:7890.7-7890.39" case 1'1 assign $0\main_sdram_bankmachine3_row_opened[0:0] 1'1 assign $0\main_sdram_bankmachine3_row[12:0] \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] case end end - attribute \src "ls180.v:7840.2-7842.5" - switch $and$ls180.v:7840$2553_Y - attribute \src "ls180.v:7840.6-7840.191" + attribute \src "ls180.v:7895.2-7897.5" + switch $and$ls180.v:7895$2620_Y + attribute \src "ls180.v:7895.6-7895.191" case 1'1 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7841$2554_Y + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7896$2621_Y case end - attribute \src "ls180.v:7843.2-7845.5" + attribute \src "ls180.v:7898.2-7900.5" switch \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7843.6-7843.58" + attribute \src "ls180.v:7898.6-7898.58" case 1'1 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7844$2555_Y + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7899$2622_Y case end - attribute \src "ls180.v:7846.2-7854.5" - switch $and$ls180.v:7846$2558_Y - attribute \src "ls180.v:7846.6-7846.191" + attribute \src "ls180.v:7901.2-7909.5" + switch $and$ls180.v:7901$2625_Y + attribute \src "ls180.v:7901.6-7901.191" case 1'1 - attribute \src "ls180.v:7847.3-7849.6" - switch $not$ls180.v:7847$2559_Y - attribute \src "ls180.v:7847.7-7847.62" + attribute \src "ls180.v:7902.3-7904.6" + switch $not$ls180.v:7902$2626_Y + attribute \src "ls180.v:7902.7-7902.62" case 1'1 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7848$2560_Y + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7903$2627_Y case end - attribute \src "ls180.v:7850.6-7850.10" + attribute \src "ls180.v:7905.6-7905.10" case - attribute \src "ls180.v:7851.3-7853.6" + attribute \src "ls180.v:7906.3-7908.6" switch \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7851.7-7851.59" + attribute \src "ls180.v:7906.7-7906.59" case 1'1 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7852$2561_Y + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7907$2628_Y case end end - attribute \src "ls180.v:7855.2-7861.5" - switch $or$ls180.v:7855$2563_Y - attribute \src "ls180.v:7855.6-7855.108" + attribute \src "ls180.v:7910.2-7916.5" + switch $or$ls180.v:7910$2630_Y + attribute \src "ls180.v:7910.6-7910.108" case 1'1 assign $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_valid assign $0\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_first @@ -277686,27 +279119,27 @@ module \ls180 assign $0\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine3_cmd_buffer_sink_payload_addr case end - attribute \src "ls180.v:7862.2-7876.5" + attribute \src "ls180.v:7917.2-7931.5" switch \main_sdram_bankmachine3_twtpcon_valid - attribute \src "ls180.v:7862.6-7862.43" + attribute \src "ls180.v:7917.6-7917.43" case 1'1 assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] 3'100 - attribute \src "ls180.v:7864.3-7868.6" + attribute \src "ls180.v:7919.3-7923.6" switch 1'0 - attribute \src "ls180.v:7866.7-7866.11" + attribute \src "ls180.v:7921.7-7921.11" case assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'0 end - attribute \src "ls180.v:7869.6-7869.10" + attribute \src "ls180.v:7924.6-7924.10" case - attribute \src "ls180.v:7870.3-7875.6" - switch $not$ls180.v:7870$2564_Y - attribute \src "ls180.v:7870.7-7870.47" + attribute \src "ls180.v:7925.3-7930.6" + switch $not$ls180.v:7925$2631_Y + attribute \src "ls180.v:7925.7-7925.47" case 1'1 - assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] $sub$ls180.v:7871$2565_Y - attribute \src "ls180.v:7872.4-7874.7" - switch $eq$ls180.v:7872$2566_Y - attribute \src "ls180.v:7872.8-7872.55" + assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] $sub$ls180.v:7926$2632_Y + attribute \src "ls180.v:7927.4-7929.7" + switch $eq$ls180.v:7927$2633_Y + attribute \src "ls180.v:7927.8-7927.55" case 1'1 assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'1 case @@ -277714,61 +279147,61 @@ module \ls180 case end end - attribute \src "ls180.v:7878.2-7884.5" - switch $not$ls180.v:7878$2567_Y - attribute \src "ls180.v:7878.6-7878.23" + attribute \src "ls180.v:7933.2-7939.5" + switch $not$ls180.v:7933$2634_Y + attribute \src "ls180.v:7933.6-7933.23" case 1'1 assign $0\main_sdram_time0[4:0] 5'11111 - attribute \src "ls180.v:7880.6-7880.10" + attribute \src "ls180.v:7935.6-7935.10" case - attribute \src "ls180.v:7881.3-7883.6" - switch $not$ls180.v:7881$2568_Y - attribute \src "ls180.v:7881.7-7881.30" + attribute \src "ls180.v:7936.3-7938.6" + switch $not$ls180.v:7936$2635_Y + attribute \src "ls180.v:7936.7-7936.30" case 1'1 - assign $0\main_sdram_time0[4:0] $sub$ls180.v:7882$2569_Y + assign $0\main_sdram_time0[4:0] $sub$ls180.v:7937$2636_Y case end end - attribute \src "ls180.v:7885.2-7891.5" - switch $not$ls180.v:7885$2570_Y - attribute \src "ls180.v:7885.6-7885.23" + attribute \src "ls180.v:7940.2-7946.5" + switch $not$ls180.v:7940$2637_Y + attribute \src "ls180.v:7940.6-7940.23" case 1'1 assign $0\main_sdram_time1[3:0] 4'1111 - attribute \src "ls180.v:7887.6-7887.10" + attribute \src "ls180.v:7942.6-7942.10" case - attribute \src "ls180.v:7888.3-7890.6" - switch $not$ls180.v:7888$2571_Y - attribute \src "ls180.v:7888.7-7888.30" + attribute \src "ls180.v:7943.3-7945.6" + switch $not$ls180.v:7943$2638_Y + attribute \src "ls180.v:7943.7-7943.30" case 1'1 - assign $0\main_sdram_time1[3:0] $sub$ls180.v:7889$2572_Y + assign $0\main_sdram_time1[3:0] $sub$ls180.v:7944$2639_Y case end end - attribute \src "ls180.v:7892.2-7947.5" + attribute \src "ls180.v:7947.2-8002.5" switch \main_sdram_choose_cmd_ce - attribute \src "ls180.v:7892.6-7892.30" + attribute \src "ls180.v:7947.6-7947.30" case 1'1 - attribute \src "ls180.v:7893.3-7946.10" + attribute \src "ls180.v:7948.3-8001.10" switch \main_sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 - attribute \src "ls180.v:7895.5-7905.8" + attribute \src "ls180.v:7950.5-7960.8" switch \main_sdram_choose_cmd_request [1] - attribute \src "ls180.v:7895.9-7895.41" + attribute \src "ls180.v:7950.9-7950.41" case 1'1 assign $0\main_sdram_choose_cmd_grant[1:0] 2'01 - attribute \src "ls180.v:7897.9-7897.13" + attribute \src "ls180.v:7952.9-7952.13" case - attribute \src "ls180.v:7898.6-7904.9" + attribute \src "ls180.v:7953.6-7959.9" switch \main_sdram_choose_cmd_request [2] - attribute \src "ls180.v:7898.10-7898.42" + attribute \src "ls180.v:7953.10-7953.42" case 1'1 assign $0\main_sdram_choose_cmd_grant[1:0] 2'10 - attribute \src "ls180.v:7900.10-7900.14" + attribute \src "ls180.v:7955.10-7955.14" case - attribute \src "ls180.v:7901.7-7903.10" + attribute \src "ls180.v:7956.7-7958.10" switch \main_sdram_choose_cmd_request [3] - attribute \src "ls180.v:7901.11-7901.43" + attribute \src "ls180.v:7956.11-7956.43" case 1'1 assign $0\main_sdram_choose_cmd_grant[1:0] 2'11 case @@ -277777,23 +279210,23 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case 2'01 - attribute \src "ls180.v:7908.5-7918.8" + attribute \src "ls180.v:7963.5-7973.8" switch \main_sdram_choose_cmd_request [2] - attribute \src "ls180.v:7908.9-7908.41" + attribute \src "ls180.v:7963.9-7963.41" case 1'1 assign $0\main_sdram_choose_cmd_grant[1:0] 2'10 - attribute \src "ls180.v:7910.9-7910.13" + attribute \src "ls180.v:7965.9-7965.13" case - attribute \src "ls180.v:7911.6-7917.9" + attribute \src "ls180.v:7966.6-7972.9" switch \main_sdram_choose_cmd_request [3] - attribute \src "ls180.v:7911.10-7911.42" + attribute \src "ls180.v:7966.10-7966.42" case 1'1 assign $0\main_sdram_choose_cmd_grant[1:0] 2'11 - attribute \src "ls180.v:7913.10-7913.14" + attribute \src "ls180.v:7968.10-7968.14" case - attribute \src "ls180.v:7914.7-7916.10" + attribute \src "ls180.v:7969.7-7971.10" switch \main_sdram_choose_cmd_request [0] - attribute \src "ls180.v:7914.11-7914.43" + attribute \src "ls180.v:7969.11-7969.43" case 1'1 assign $0\main_sdram_choose_cmd_grant[1:0] 2'00 case @@ -277802,23 +279235,23 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case 2'10 - attribute \src "ls180.v:7921.5-7931.8" + attribute \src "ls180.v:7976.5-7986.8" switch \main_sdram_choose_cmd_request [3] - attribute \src "ls180.v:7921.9-7921.41" + attribute \src "ls180.v:7976.9-7976.41" case 1'1 assign $0\main_sdram_choose_cmd_grant[1:0] 2'11 - attribute \src "ls180.v:7923.9-7923.13" + attribute \src "ls180.v:7978.9-7978.13" case - attribute \src "ls180.v:7924.6-7930.9" + attribute \src "ls180.v:7979.6-7985.9" switch \main_sdram_choose_cmd_request [0] - attribute \src "ls180.v:7924.10-7924.42" + attribute \src "ls180.v:7979.10-7979.42" case 1'1 assign $0\main_sdram_choose_cmd_grant[1:0] 2'00 - attribute \src "ls180.v:7926.10-7926.14" + attribute \src "ls180.v:7981.10-7981.14" case - attribute \src "ls180.v:7927.7-7929.10" + attribute \src "ls180.v:7982.7-7984.10" switch \main_sdram_choose_cmd_request [1] - attribute \src "ls180.v:7927.11-7927.43" + attribute \src "ls180.v:7982.11-7982.43" case 1'1 assign $0\main_sdram_choose_cmd_grant[1:0] 2'01 case @@ -277827,23 +279260,23 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case 2'11 - attribute \src "ls180.v:7934.5-7944.8" + attribute \src "ls180.v:7989.5-7999.8" switch \main_sdram_choose_cmd_request [0] - attribute \src "ls180.v:7934.9-7934.41" + attribute \src "ls180.v:7989.9-7989.41" case 1'1 assign $0\main_sdram_choose_cmd_grant[1:0] 2'00 - attribute \src "ls180.v:7936.9-7936.13" + attribute \src "ls180.v:7991.9-7991.13" case - attribute \src "ls180.v:7937.6-7943.9" + attribute \src "ls180.v:7992.6-7998.9" switch \main_sdram_choose_cmd_request [1] - attribute \src "ls180.v:7937.10-7937.42" + attribute \src "ls180.v:7992.10-7992.42" case 1'1 assign $0\main_sdram_choose_cmd_grant[1:0] 2'01 - attribute \src "ls180.v:7939.10-7939.14" + attribute \src "ls180.v:7994.10-7994.14" case - attribute \src "ls180.v:7940.7-7942.10" + attribute \src "ls180.v:7995.7-7997.10" switch \main_sdram_choose_cmd_request [2] - attribute \src "ls180.v:7940.11-7940.43" + attribute \src "ls180.v:7995.11-7995.43" case 1'1 assign $0\main_sdram_choose_cmd_grant[1:0] 2'10 case @@ -277854,31 +279287,31 @@ module \ls180 end case end - attribute \src "ls180.v:7948.2-8003.5" + attribute \src "ls180.v:8003.2-8058.5" switch \main_sdram_choose_req_ce - attribute \src "ls180.v:7948.6-7948.30" + attribute \src "ls180.v:8003.6-8003.30" case 1'1 - attribute \src "ls180.v:7949.3-8002.10" + attribute \src "ls180.v:8004.3-8057.10" switch \main_sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 - attribute \src "ls180.v:7951.5-7961.8" + attribute \src "ls180.v:8006.5-8016.8" switch \main_sdram_choose_req_request [1] - attribute \src "ls180.v:7951.9-7951.41" + attribute \src "ls180.v:8006.9-8006.41" case 1'1 assign $0\main_sdram_choose_req_grant[1:0] 2'01 - attribute \src "ls180.v:7953.9-7953.13" + attribute \src "ls180.v:8008.9-8008.13" case - attribute \src "ls180.v:7954.6-7960.9" + attribute \src "ls180.v:8009.6-8015.9" switch \main_sdram_choose_req_request [2] - attribute \src "ls180.v:7954.10-7954.42" + attribute \src "ls180.v:8009.10-8009.42" case 1'1 assign $0\main_sdram_choose_req_grant[1:0] 2'10 - attribute \src "ls180.v:7956.10-7956.14" + attribute \src "ls180.v:8011.10-8011.14" case - attribute \src "ls180.v:7957.7-7959.10" + attribute \src "ls180.v:8012.7-8014.10" switch \main_sdram_choose_req_request [3] - attribute \src "ls180.v:7957.11-7957.43" + attribute \src "ls180.v:8012.11-8012.43" case 1'1 assign $0\main_sdram_choose_req_grant[1:0] 2'11 case @@ -277887,23 +279320,23 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case 2'01 - attribute \src "ls180.v:7964.5-7974.8" + attribute \src "ls180.v:8019.5-8029.8" switch \main_sdram_choose_req_request [2] - attribute \src "ls180.v:7964.9-7964.41" + attribute \src "ls180.v:8019.9-8019.41" case 1'1 assign $0\main_sdram_choose_req_grant[1:0] 2'10 - attribute \src "ls180.v:7966.9-7966.13" + attribute \src "ls180.v:8021.9-8021.13" case - attribute \src "ls180.v:7967.6-7973.9" + attribute \src "ls180.v:8022.6-8028.9" switch \main_sdram_choose_req_request [3] - attribute \src "ls180.v:7967.10-7967.42" + attribute \src "ls180.v:8022.10-8022.42" case 1'1 assign $0\main_sdram_choose_req_grant[1:0] 2'11 - attribute \src "ls180.v:7969.10-7969.14" + attribute \src "ls180.v:8024.10-8024.14" case - attribute \src "ls180.v:7970.7-7972.10" + attribute \src "ls180.v:8025.7-8027.10" switch \main_sdram_choose_req_request [0] - attribute \src "ls180.v:7970.11-7970.43" + attribute \src "ls180.v:8025.11-8025.43" case 1'1 assign $0\main_sdram_choose_req_grant[1:0] 2'00 case @@ -277912,23 +279345,23 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case 2'10 - attribute \src "ls180.v:7977.5-7987.8" + attribute \src "ls180.v:8032.5-8042.8" switch \main_sdram_choose_req_request [3] - attribute \src "ls180.v:7977.9-7977.41" + attribute \src "ls180.v:8032.9-8032.41" case 1'1 assign $0\main_sdram_choose_req_grant[1:0] 2'11 - attribute \src "ls180.v:7979.9-7979.13" + attribute \src "ls180.v:8034.9-8034.13" case - attribute \src "ls180.v:7980.6-7986.9" + attribute \src "ls180.v:8035.6-8041.9" switch \main_sdram_choose_req_request [0] - attribute \src "ls180.v:7980.10-7980.42" + attribute \src "ls180.v:8035.10-8035.42" case 1'1 assign $0\main_sdram_choose_req_grant[1:0] 2'00 - attribute \src "ls180.v:7982.10-7982.14" + attribute \src "ls180.v:8037.10-8037.14" case - attribute \src "ls180.v:7983.7-7985.10" + attribute \src "ls180.v:8038.7-8040.10" switch \main_sdram_choose_req_request [1] - attribute \src "ls180.v:7983.11-7983.43" + attribute \src "ls180.v:8038.11-8038.43" case 1'1 assign $0\main_sdram_choose_req_grant[1:0] 2'01 case @@ -277937,23 +279370,23 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case 2'11 - attribute \src "ls180.v:7990.5-8000.8" + attribute \src "ls180.v:8045.5-8055.8" switch \main_sdram_choose_req_request [0] - attribute \src "ls180.v:7990.9-7990.41" + attribute \src "ls180.v:8045.9-8045.41" case 1'1 assign $0\main_sdram_choose_req_grant[1:0] 2'00 - attribute \src "ls180.v:7992.9-7992.13" + attribute \src "ls180.v:8047.9-8047.13" case - attribute \src "ls180.v:7993.6-7999.9" + attribute \src "ls180.v:8048.6-8054.9" switch \main_sdram_choose_req_request [1] - attribute \src "ls180.v:7993.10-7993.42" + attribute \src "ls180.v:8048.10-8048.42" case 1'1 assign $0\main_sdram_choose_req_grant[1:0] 2'01 - attribute \src "ls180.v:7995.10-7995.14" + attribute \src "ls180.v:8050.10-8050.14" case - attribute \src "ls180.v:7996.7-7998.10" + attribute \src "ls180.v:8051.7-8053.10" switch \main_sdram_choose_req_request [2] - attribute \src "ls180.v:7996.11-7996.43" + attribute \src "ls180.v:8051.11-8051.43" case 1'1 assign $0\main_sdram_choose_req_grant[1:0] 2'10 case @@ -277964,28 +279397,28 @@ module \ls180 end case end - attribute \src "ls180.v:8012.2-8026.5" + attribute \src "ls180.v:8067.2-8081.5" switch \main_sdram_tccdcon_valid - attribute \src "ls180.v:8012.6-8012.30" + attribute \src "ls180.v:8067.6-8067.30" case 1'1 assign $0\main_sdram_tccdcon_count[0:0] 1'0 - attribute \src "ls180.v:8014.3-8018.6" + attribute \src "ls180.v:8069.3-8073.6" switch 1'1 - attribute \src "ls180.v:8014.7-8014.11" + attribute \src "ls180.v:8069.7-8069.11" case 1'1 assign $0\main_sdram_tccdcon_ready[0:0] 1'1 case end - attribute \src "ls180.v:8019.6-8019.10" + attribute \src "ls180.v:8074.6-8074.10" case - attribute \src "ls180.v:8020.3-8025.6" - switch $not$ls180.v:8020$2576_Y - attribute \src "ls180.v:8020.7-8020.34" + attribute \src "ls180.v:8075.3-8080.6" + switch $not$ls180.v:8075$2643_Y + attribute \src "ls180.v:8075.7-8075.34" case 1'1 - assign $0\main_sdram_tccdcon_count[0:0] $sub$ls180.v:8021$2577_Y - attribute \src "ls180.v:8022.4-8024.7" - switch $eq$ls180.v:8022$2578_Y - attribute \src "ls180.v:8022.8-8022.42" + assign $0\main_sdram_tccdcon_count[0:0] $sub$ls180.v:8076$2644_Y + attribute \src "ls180.v:8077.4-8079.7" + switch $eq$ls180.v:8077$2645_Y + attribute \src "ls180.v:8077.8-8077.42" case 1'1 assign $0\main_sdram_tccdcon_ready[0:0] 1'1 case @@ -277993,27 +279426,27 @@ module \ls180 case end end - attribute \src "ls180.v:8027.2-8041.5" + attribute \src "ls180.v:8082.2-8096.5" switch \main_sdram_twtrcon_valid - attribute \src "ls180.v:8027.6-8027.30" + attribute \src "ls180.v:8082.6-8082.30" case 1'1 assign $0\main_sdram_twtrcon_count[2:0] 3'100 - attribute \src "ls180.v:8029.3-8033.6" + attribute \src "ls180.v:8084.3-8088.6" switch 1'0 - attribute \src "ls180.v:8031.7-8031.11" + attribute \src "ls180.v:8086.7-8086.11" case assign $0\main_sdram_twtrcon_ready[0:0] 1'0 end - attribute \src "ls180.v:8034.6-8034.10" + attribute \src "ls180.v:8089.6-8089.10" case - attribute \src "ls180.v:8035.3-8040.6" - switch $not$ls180.v:8035$2579_Y - attribute \src "ls180.v:8035.7-8035.34" + attribute \src "ls180.v:8090.3-8095.6" + switch $not$ls180.v:8090$2646_Y + attribute \src "ls180.v:8090.7-8090.34" case 1'1 - assign $0\main_sdram_twtrcon_count[2:0] $sub$ls180.v:8036$2580_Y - attribute \src "ls180.v:8037.4-8039.7" - switch $eq$ls180.v:8037$2581_Y - attribute \src "ls180.v:8037.8-8037.42" + assign $0\main_sdram_twtrcon_count[2:0] $sub$ls180.v:8091$2647_Y + attribute \src "ls180.v:8092.4-8094.7" + switch $eq$ls180.v:8092$2648_Y + attribute \src "ls180.v:8092.8-8092.42" case 1'1 assign $0\main_sdram_twtrcon_ready[0:0] 1'1 case @@ -278021,81 +279454,81 @@ module \ls180 case end end - attribute \src "ls180.v:8048.2-8050.5" - switch $or$ls180.v:8048$2606_Y - attribute \src "ls180.v:8048.6-8048.50" + attribute \src "ls180.v:8103.2-8105.5" + switch $or$ls180.v:8103$2673_Y + attribute \src "ls180.v:8103.6-8103.50" case 1'1 assign $0\main_converter_dat_r[31:0] \main_wb_sdram_dat_r case end - attribute \src "ls180.v:8052.2-8054.5" + attribute \src "ls180.v:8107.2-8109.5" switch \main_converter_counter_converter_next_value_ce - attribute \src "ls180.v:8052.6-8052.52" + attribute \src "ls180.v:8107.6-8107.52" case 1'1 assign $0\main_converter_counter[0:0] \main_converter_counter_converter_next_value case end - attribute \src "ls180.v:8055.2-8058.5" + attribute \src "ls180.v:8110.2-8113.5" switch \main_converter_reset - attribute \src "ls180.v:8055.6-8055.26" + attribute \src "ls180.v:8110.6-8110.26" case 1'1 assign $0\main_converter_counter[0:0] 1'0 assign $0\builder_converter_state[0:0] 1'0 case end - attribute \src "ls180.v:8059.2-8069.5" + attribute \src "ls180.v:8114.2-8124.5" switch \main_litedram_wb_ack - attribute \src "ls180.v:8059.6-8059.26" + attribute \src "ls180.v:8114.6-8114.26" case 1'1 assign $0\main_cmd_consumed[0:0] 1'0 assign $0\main_wdata_consumed[0:0] 1'0 - attribute \src "ls180.v:8062.6-8062.10" + attribute \src "ls180.v:8117.6-8117.10" case - attribute \src "ls180.v:8063.3-8065.6" - switch $and$ls180.v:8063$2607_Y - attribute \src "ls180.v:8063.7-8063.50" + attribute \src "ls180.v:8118.3-8120.6" + switch $and$ls180.v:8118$2674_Y + attribute \src "ls180.v:8118.7-8118.50" case 1'1 assign $0\main_cmd_consumed[0:0] 1'1 case end - attribute \src "ls180.v:8066.3-8068.6" - switch $and$ls180.v:8066$2608_Y - attribute \src "ls180.v:8066.7-8066.54" + attribute \src "ls180.v:8121.3-8123.6" + switch $and$ls180.v:8121$2675_Y + attribute \src "ls180.v:8121.7-8121.54" case 1'1 assign $0\main_wdata_consumed[0:0] 1'1 case end end - attribute \src "ls180.v:8071.2-8092.5" - switch $and$ls180.v:8071$2612_Y - attribute \src "ls180.v:8071.6-8071.91" + attribute \src "ls180.v:8126.2-8147.5" + switch $and$ls180.v:8126$2679_Y + attribute \src "ls180.v:8126.6-8126.91" case 1'1 assign $0\main_uart_phy_tx_reg[7:0] \main_uart_phy_sink_payload_data assign $0\main_uart_phy_tx_bitcount[3:0] 4'0000 assign $0\main_uart_phy_tx_busy[0:0] 1'1 assign $0\uart_tx[0:0] 1'0 - attribute \src "ls180.v:8076.6-8076.10" + attribute \src "ls180.v:8131.6-8131.10" case - attribute \src "ls180.v:8077.3-8091.6" - switch $and$ls180.v:8077$2613_Y - attribute \src "ls180.v:8077.7-8077.60" + attribute \src "ls180.v:8132.3-8146.6" + switch $and$ls180.v:8132$2680_Y + attribute \src "ls180.v:8132.7-8132.60" case 1'1 - assign $0\main_uart_phy_tx_bitcount[3:0] $add$ls180.v:8078$2614_Y - attribute \src "ls180.v:8079.4-8090.7" - switch $eq$ls180.v:8079$2615_Y - attribute \src "ls180.v:8079.8-8079.43" + assign $0\main_uart_phy_tx_bitcount[3:0] $add$ls180.v:8133$2681_Y + attribute \src "ls180.v:8134.4-8145.7" + switch $eq$ls180.v:8134$2682_Y + attribute \src "ls180.v:8134.8-8134.43" case 1'1 assign $0\uart_tx[0:0] 1'1 - attribute \src "ls180.v:8081.8-8081.12" + attribute \src "ls180.v:8136.8-8136.12" case - attribute \src "ls180.v:8082.5-8089.8" - switch $eq$ls180.v:8082$2616_Y - attribute \src "ls180.v:8082.9-8082.44" + attribute \src "ls180.v:8137.5-8144.8" + switch $eq$ls180.v:8137$2683_Y + attribute \src "ls180.v:8137.9-8137.44" case 1'1 assign $0\uart_tx[0:0] 1'1 assign $0\main_uart_phy_tx_busy[0:0] 1'0 assign $0\main_uart_phy_sink_ready[0:0] 1'1 - attribute \src "ls180.v:8086.9-8086.13" + attribute \src "ls180.v:8141.9-8141.13" case assign $0\uart_tx[0:0] \main_uart_phy_tx_reg [0] assign $0\main_uart_phy_tx_reg[7:0] { 1'0 \main_uart_phy_tx_reg [7:1] } @@ -278104,61 +279537,61 @@ module \ls180 case end end - attribute \src "ls180.v:8093.2-8097.5" + attribute \src "ls180.v:8148.2-8152.5" switch \main_uart_phy_tx_busy - attribute \src "ls180.v:8093.6-8093.27" + attribute \src "ls180.v:8148.6-8148.27" case 1'1 - assign { $0\main_uart_phy_uart_clk_txen[0:0] $0\main_uart_phy_phase_accumulator_tx[31:0] } $add$ls180.v:8094$2617_Y - attribute \src "ls180.v:8095.6-8095.10" + assign { $0\main_uart_phy_uart_clk_txen[0:0] $0\main_uart_phy_phase_accumulator_tx[31:0] } $add$ls180.v:8149$2684_Y + attribute \src "ls180.v:8150.6-8150.10" case assign { $0\main_uart_phy_uart_clk_txen[0:0] $0\main_uart_phy_phase_accumulator_tx[31:0] } { 1'0 \main_uart_phy_storage } end - attribute \src "ls180.v:8100.2-8124.5" - switch $not$ls180.v:8100$2618_Y - attribute \src "ls180.v:8100.6-8100.30" + attribute \src "ls180.v:8155.2-8179.5" + switch $not$ls180.v:8155$2685_Y + attribute \src "ls180.v:8155.6-8155.30" case 1'1 - attribute \src "ls180.v:8101.3-8104.6" - switch $and$ls180.v:8101$2620_Y - attribute \src "ls180.v:8101.7-8101.49" + attribute \src "ls180.v:8156.3-8159.6" + switch $and$ls180.v:8156$2687_Y + attribute \src "ls180.v:8156.7-8156.49" case 1'1 assign $0\main_uart_phy_rx_busy[0:0] 1'1 assign $0\main_uart_phy_rx_bitcount[3:0] 4'0000 case end - attribute \src "ls180.v:8105.6-8105.10" + attribute \src "ls180.v:8160.6-8160.10" case - attribute \src "ls180.v:8106.3-8123.6" + attribute \src "ls180.v:8161.3-8178.6" switch \main_uart_phy_uart_clk_rxen - attribute \src "ls180.v:8106.7-8106.34" + attribute \src "ls180.v:8161.7-8161.34" case 1'1 - assign $0\main_uart_phy_rx_bitcount[3:0] $add$ls180.v:8107$2621_Y - attribute \src "ls180.v:8108.4-8122.7" - switch $eq$ls180.v:8108$2622_Y - attribute \src "ls180.v:8108.8-8108.43" + assign $0\main_uart_phy_rx_bitcount[3:0] $add$ls180.v:8162$2688_Y + attribute \src "ls180.v:8163.4-8177.7" + switch $eq$ls180.v:8163$2689_Y + attribute \src "ls180.v:8163.8-8163.43" case 1'1 - attribute \src "ls180.v:8109.5-8111.8" + attribute \src "ls180.v:8164.5-8166.8" switch \main_uart_phy_rx - attribute \src "ls180.v:8109.9-8109.25" + attribute \src "ls180.v:8164.9-8164.25" case 1'1 assign $0\main_uart_phy_rx_busy[0:0] 1'0 case end - attribute \src "ls180.v:8112.8-8112.12" + attribute \src "ls180.v:8167.8-8167.12" case - attribute \src "ls180.v:8113.5-8121.8" - switch $eq$ls180.v:8113$2623_Y - attribute \src "ls180.v:8113.9-8113.44" + attribute \src "ls180.v:8168.5-8176.8" + switch $eq$ls180.v:8168$2690_Y + attribute \src "ls180.v:8168.9-8168.44" case 1'1 assign $0\main_uart_phy_rx_busy[0:0] 1'0 - attribute \src "ls180.v:8115.6-8118.9" + attribute \src "ls180.v:8170.6-8173.9" switch \main_uart_phy_rx - attribute \src "ls180.v:8115.10-8115.26" + attribute \src "ls180.v:8170.10-8170.26" case 1'1 assign $0\main_uart_phy_source_payload_data[7:0] \main_uart_phy_rx_reg assign $0\main_uart_phy_source_valid[0:0] 1'1 case end - attribute \src "ls180.v:8119.9-8119.13" + attribute \src "ls180.v:8174.9-8174.13" case assign $0\main_uart_phy_rx_reg[7:0] { \main_uart_phy_rx \main_uart_phy_rx_reg [7:1] } end @@ -278166,146 +279599,146 @@ module \ls180 case end end - attribute \src "ls180.v:8125.2-8129.5" + attribute \src "ls180.v:8180.2-8184.5" switch \main_uart_phy_rx_busy - attribute \src "ls180.v:8125.6-8125.27" + attribute \src "ls180.v:8180.6-8180.27" case 1'1 - assign { $0\main_uart_phy_uart_clk_rxen[0:0] $0\main_uart_phy_phase_accumulator_rx[31:0] } $add$ls180.v:8126$2624_Y - attribute \src "ls180.v:8127.6-8127.10" + assign { $0\main_uart_phy_uart_clk_rxen[0:0] $0\main_uart_phy_phase_accumulator_rx[31:0] } $add$ls180.v:8181$2691_Y + attribute \src "ls180.v:8182.6-8182.10" case assign { $0\main_uart_phy_uart_clk_rxen[0:0] $0\main_uart_phy_phase_accumulator_rx[31:0] } 33'010000000000000000000000000000000 end - attribute \src "ls180.v:8130.2-8132.5" + attribute \src "ls180.v:8185.2-8187.5" switch \main_uart_tx_clear - attribute \src "ls180.v:8130.6-8130.24" + attribute \src "ls180.v:8185.6-8185.24" case 1'1 assign $0\main_uart_tx_pending[0:0] 1'0 case end - attribute \src "ls180.v:8134.2-8136.5" - switch $and$ls180.v:8134$2626_Y - attribute \src "ls180.v:8134.6-8134.58" + attribute \src "ls180.v:8189.2-8191.5" + switch $and$ls180.v:8189$2693_Y + attribute \src "ls180.v:8189.6-8189.58" case 1'1 assign $0\main_uart_tx_pending[0:0] 1'1 case end - attribute \src "ls180.v:8137.2-8139.5" + attribute \src "ls180.v:8192.2-8194.5" switch \main_uart_rx_clear - attribute \src "ls180.v:8137.6-8137.24" + attribute \src "ls180.v:8192.6-8192.24" case 1'1 assign $0\main_uart_rx_pending[0:0] 1'0 case end - attribute \src "ls180.v:8141.2-8143.5" - switch $and$ls180.v:8141$2628_Y - attribute \src "ls180.v:8141.6-8141.58" + attribute \src "ls180.v:8196.2-8198.5" + switch $and$ls180.v:8196$2695_Y + attribute \src "ls180.v:8196.6-8196.58" case 1'1 assign $0\main_uart_rx_pending[0:0] 1'1 case end - attribute \src "ls180.v:8144.2-8150.5" + attribute \src "ls180.v:8199.2-8205.5" switch \main_uart_tx_fifo_syncfifo_re - attribute \src "ls180.v:8144.6-8144.35" + attribute \src "ls180.v:8199.6-8199.35" case 1'1 assign $0\main_uart_tx_fifo_readable[0:0] 1'1 - attribute \src "ls180.v:8146.6-8146.10" + attribute \src "ls180.v:8201.6-8201.10" case - attribute \src "ls180.v:8147.3-8149.6" + attribute \src "ls180.v:8202.3-8204.6" switch \main_uart_tx_fifo_re - attribute \src "ls180.v:8147.7-8147.27" + attribute \src "ls180.v:8202.7-8202.27" case 1'1 assign $0\main_uart_tx_fifo_readable[0:0] 1'0 case end end - attribute \src "ls180.v:8151.2-8153.5" - switch $and$ls180.v:8151$2631_Y - attribute \src "ls180.v:8151.6-8151.108" + attribute \src "ls180.v:8206.2-8208.5" + switch $and$ls180.v:8206$2698_Y + attribute \src "ls180.v:8206.6-8206.108" case 1'1 - assign $0\main_uart_tx_fifo_produce[3:0] $add$ls180.v:8152$2632_Y + assign $0\main_uart_tx_fifo_produce[3:0] $add$ls180.v:8207$2699_Y case end - attribute \src "ls180.v:8154.2-8156.5" + attribute \src "ls180.v:8209.2-8211.5" switch \main_uart_tx_fifo_do_read - attribute \src "ls180.v:8154.6-8154.31" + attribute \src "ls180.v:8209.6-8209.31" case 1'1 - assign $0\main_uart_tx_fifo_consume[3:0] $add$ls180.v:8155$2633_Y + assign $0\main_uart_tx_fifo_consume[3:0] $add$ls180.v:8210$2700_Y case end - attribute \src "ls180.v:8157.2-8165.5" - switch $and$ls180.v:8157$2636_Y - attribute \src "ls180.v:8157.6-8157.108" + attribute \src "ls180.v:8212.2-8220.5" + switch $and$ls180.v:8212$2703_Y + attribute \src "ls180.v:8212.6-8212.108" case 1'1 - attribute \src "ls180.v:8158.3-8160.6" - switch $not$ls180.v:8158$2637_Y - attribute \src "ls180.v:8158.7-8158.35" + attribute \src "ls180.v:8213.3-8215.6" + switch $not$ls180.v:8213$2704_Y + attribute \src "ls180.v:8213.7-8213.35" case 1'1 - assign $0\main_uart_tx_fifo_level0[4:0] $add$ls180.v:8159$2638_Y + assign $0\main_uart_tx_fifo_level0[4:0] $add$ls180.v:8214$2705_Y case end - attribute \src "ls180.v:8161.6-8161.10" + attribute \src "ls180.v:8216.6-8216.10" case - attribute \src "ls180.v:8162.3-8164.6" + attribute \src "ls180.v:8217.3-8219.6" switch \main_uart_tx_fifo_do_read - attribute \src "ls180.v:8162.7-8162.32" + attribute \src "ls180.v:8217.7-8217.32" case 1'1 - assign $0\main_uart_tx_fifo_level0[4:0] $sub$ls180.v:8163$2639_Y + assign $0\main_uart_tx_fifo_level0[4:0] $sub$ls180.v:8218$2706_Y case end end - attribute \src "ls180.v:8166.2-8172.5" + attribute \src "ls180.v:8221.2-8227.5" switch \main_uart_rx_fifo_syncfifo_re - attribute \src "ls180.v:8166.6-8166.35" + attribute \src "ls180.v:8221.6-8221.35" case 1'1 assign $0\main_uart_rx_fifo_readable[0:0] 1'1 - attribute \src "ls180.v:8168.6-8168.10" + attribute \src "ls180.v:8223.6-8223.10" case - attribute \src "ls180.v:8169.3-8171.6" + attribute \src "ls180.v:8224.3-8226.6" switch \main_uart_rx_fifo_re - attribute \src "ls180.v:8169.7-8169.27" + attribute \src "ls180.v:8224.7-8224.27" case 1'1 assign $0\main_uart_rx_fifo_readable[0:0] 1'0 case end end - attribute \src "ls180.v:8173.2-8175.5" - switch $and$ls180.v:8173$2642_Y - attribute \src "ls180.v:8173.6-8173.108" + attribute \src "ls180.v:8228.2-8230.5" + switch $and$ls180.v:8228$2709_Y + attribute \src "ls180.v:8228.6-8228.108" case 1'1 - assign $0\main_uart_rx_fifo_produce[3:0] $add$ls180.v:8174$2643_Y + assign $0\main_uart_rx_fifo_produce[3:0] $add$ls180.v:8229$2710_Y case end - attribute \src "ls180.v:8176.2-8178.5" + attribute \src "ls180.v:8231.2-8233.5" switch \main_uart_rx_fifo_do_read - attribute \src "ls180.v:8176.6-8176.31" + attribute \src "ls180.v:8231.6-8231.31" case 1'1 - assign $0\main_uart_rx_fifo_consume[3:0] $add$ls180.v:8177$2644_Y + assign $0\main_uart_rx_fifo_consume[3:0] $add$ls180.v:8232$2711_Y case end - attribute \src "ls180.v:8179.2-8187.5" - switch $and$ls180.v:8179$2647_Y - attribute \src "ls180.v:8179.6-8179.108" + attribute \src "ls180.v:8234.2-8242.5" + switch $and$ls180.v:8234$2714_Y + attribute \src "ls180.v:8234.6-8234.108" case 1'1 - attribute \src "ls180.v:8180.3-8182.6" - switch $not$ls180.v:8180$2648_Y - attribute \src "ls180.v:8180.7-8180.35" + attribute \src "ls180.v:8235.3-8237.6" + switch $not$ls180.v:8235$2715_Y + attribute \src "ls180.v:8235.7-8235.35" case 1'1 - assign $0\main_uart_rx_fifo_level0[4:0] $add$ls180.v:8181$2649_Y + assign $0\main_uart_rx_fifo_level0[4:0] $add$ls180.v:8236$2716_Y case end - attribute \src "ls180.v:8183.6-8183.10" + attribute \src "ls180.v:8238.6-8238.10" case - attribute \src "ls180.v:8184.3-8186.6" + attribute \src "ls180.v:8239.3-8241.6" switch \main_uart_rx_fifo_do_read - attribute \src "ls180.v:8184.7-8184.32" + attribute \src "ls180.v:8239.7-8239.32" case 1'1 - assign $0\main_uart_rx_fifo_level0[4:0] $sub$ls180.v:8185$2650_Y + assign $0\main_uart_rx_fifo_level0[4:0] $sub$ls180.v:8240$2717_Y case end end - attribute \src "ls180.v:8188.2-8201.5" + attribute \src "ls180.v:8243.2-8256.5" switch \main_uart_reset - attribute \src "ls180.v:8188.6-8188.21" + attribute \src "ls180.v:8243.6-8243.21" case 1'1 assign $0\main_uart_tx_pending[0:0] 1'0 assign $0\main_uart_tx_old_trigger[0:0] 1'0 @@ -278321,38 +279754,38 @@ module \ls180 assign $0\main_uart_rx_fifo_consume[3:0] 4'0000 case end - attribute \src "ls180.v:8203.2-8210.5" + attribute \src "ls180.v:8258.2-8265.5" switch \main_spimaster31_clk_rise - attribute \src "ls180.v:8203.6-8203.31" + attribute \src "ls180.v:8258.6-8258.31" case 1'1 assign $0\spisdcard_clk[0:0] \main_spimaster25_clk_enable - attribute \src "ls180.v:8205.6-8205.10" + attribute \src "ls180.v:8260.6-8260.10" case - attribute \src "ls180.v:8206.3-8209.6" + attribute \src "ls180.v:8261.3-8264.6" switch \main_spimaster32_clk_fall - attribute \src "ls180.v:8206.7-8206.32" + attribute \src "ls180.v:8261.7-8261.32" case 1'1 assign $0\main_spimaster30_clk_divider[15:0] 16'0000000000000000 assign $0\spisdcard_clk[0:0] 1'0 case end end - attribute \src "ls180.v:8212.2-8222.5" + attribute \src "ls180.v:8267.2-8277.5" switch \main_spimaster28_mosi_latch - attribute \src "ls180.v:8212.6-8212.33" + attribute \src "ls180.v:8267.6-8267.33" case 1'1 assign $0\main_spimaster33_mosi_data[7:0] \main_spimaster4_mosi assign $0\main_spimaster34_mosi_sel[2:0] 3'111 - attribute \src "ls180.v:8215.6-8215.10" + attribute \src "ls180.v:8270.6-8270.10" case - attribute \src "ls180.v:8216.3-8221.6" + attribute \src "ls180.v:8271.3-8276.6" switch \main_spimaster32_clk_fall - attribute \src "ls180.v:8216.7-8216.32" + attribute \src "ls180.v:8271.7-8271.32" case 1'1 - assign $0\main_spimaster34_mosi_sel[2:0] $sub$ls180.v:8220$2655_Y - attribute \src "ls180.v:8217.4-8219.7" + assign $0\main_spimaster34_mosi_sel[2:0] $sub$ls180.v:8275$2722_Y + attribute \src "ls180.v:8272.4-8274.7" switch \main_spimaster26_cs_enable - attribute \src "ls180.v:8217.8-8217.34" + attribute \src "ls180.v:8272.8-8272.34" case 1'1 assign $0\spisdcard_mosi[0:0] \builder_sync_f_array_muxed0 case @@ -278360,67 +279793,67 @@ module \ls180 case end end - attribute \src "ls180.v:8223.2-8229.5" + attribute \src "ls180.v:8278.2-8284.5" switch \main_spimaster31_clk_rise - attribute \src "ls180.v:8223.6-8223.31" + attribute \src "ls180.v:8278.6-8278.31" case 1'1 - attribute \src "ls180.v:8224.3-8228.6" + attribute \src "ls180.v:8279.3-8283.6" switch \main_spimaster7_loopback - attribute \src "ls180.v:8224.7-8224.31" + attribute \src "ls180.v:8279.7-8279.31" case 1'1 assign $0\main_spimaster35_miso_data[7:0] { \main_spimaster35_miso_data [6:0] \spisdcard_mosi } - attribute \src "ls180.v:8226.7-8226.11" + attribute \src "ls180.v:8281.7-8281.11" case assign $0\main_spimaster35_miso_data[7:0] { \main_spimaster35_miso_data [6:0] \spisdcard_miso } end case end - attribute \src "ls180.v:8230.2-8232.5" + attribute \src "ls180.v:8285.2-8287.5" switch \main_spimaster29_miso_latch - attribute \src "ls180.v:8230.6-8230.33" + attribute \src "ls180.v:8285.6-8285.33" case 1'1 assign $0\main_spimaster5_miso[7:0] \main_spimaster35_miso_data case end - attribute \src "ls180.v:8234.2-8236.5" + attribute \src "ls180.v:8289.2-8291.5" switch \main_spimaster27_count_spimaster0_next_value_ce - attribute \src "ls180.v:8234.6-8234.53" + attribute \src "ls180.v:8289.6-8289.53" case 1'1 assign $0\main_spimaster27_count[2:0] \main_spimaster27_count_spimaster0_next_value case end - attribute \src "ls180.v:8238.2-8245.5" + attribute \src "ls180.v:8293.2-8300.5" switch \main_spisdcard_clk_rise - attribute \src "ls180.v:8238.6-8238.29" + attribute \src "ls180.v:8293.6-8293.29" case 1'1 assign $0\spimaster_clk[0:0] \main_spisdcard_clk_enable - attribute \src "ls180.v:8240.6-8240.10" + attribute \src "ls180.v:8295.6-8295.10" case - attribute \src "ls180.v:8241.3-8244.6" + attribute \src "ls180.v:8296.3-8299.6" switch \main_spisdcard_clk_fall - attribute \src "ls180.v:8241.7-8241.30" + attribute \src "ls180.v:8296.7-8296.30" case 1'1 assign $0\main_spisdcard_clk_divider1[15:0] 16'0000000000000000 assign $0\spimaster_clk[0:0] 1'0 case end end - attribute \src "ls180.v:8247.2-8257.5" + attribute \src "ls180.v:8302.2-8312.5" switch \main_spisdcard_mosi_latch - attribute \src "ls180.v:8247.6-8247.31" + attribute \src "ls180.v:8302.6-8302.31" case 1'1 assign $0\main_spisdcard_mosi_data[7:0] \main_spisdcard_mosi assign $0\main_spisdcard_mosi_sel[2:0] 3'111 - attribute \src "ls180.v:8250.6-8250.10" + attribute \src "ls180.v:8305.6-8305.10" case - attribute \src "ls180.v:8251.3-8256.6" + attribute \src "ls180.v:8306.3-8311.6" switch \main_spisdcard_clk_fall - attribute \src "ls180.v:8251.7-8251.30" + attribute \src "ls180.v:8306.7-8306.30" case 1'1 - assign $0\main_spisdcard_mosi_sel[2:0] $sub$ls180.v:8255$2660_Y - attribute \src "ls180.v:8252.4-8254.7" + assign $0\main_spisdcard_mosi_sel[2:0] $sub$ls180.v:8310$2727_Y + attribute \src "ls180.v:8307.4-8309.7" switch \main_spisdcard_cs_enable - attribute \src "ls180.v:8252.8-8252.32" + attribute \src "ls180.v:8307.8-8307.32" case 1'1 assign $0\spimaster_mosi[0:0] \builder_sync_f_array_muxed1 case @@ -278428,169 +279861,169 @@ module \ls180 case end end - attribute \src "ls180.v:8258.2-8264.5" + attribute \src "ls180.v:8313.2-8319.5" switch \main_spisdcard_clk_rise - attribute \src "ls180.v:8258.6-8258.29" + attribute \src "ls180.v:8313.6-8313.29" case 1'1 - attribute \src "ls180.v:8259.3-8263.6" + attribute \src "ls180.v:8314.3-8318.6" switch \main_spisdcard_loopback - attribute \src "ls180.v:8259.7-8259.30" + attribute \src "ls180.v:8314.7-8314.30" case 1'1 assign $0\main_spisdcard_miso_data[7:0] { \main_spisdcard_miso_data [6:0] \spimaster_mosi } - attribute \src "ls180.v:8261.7-8261.11" + attribute \src "ls180.v:8316.7-8316.11" case assign $0\main_spisdcard_miso_data[7:0] { \main_spisdcard_miso_data [6:0] \spimaster_miso } end case end - attribute \src "ls180.v:8265.2-8267.5" + attribute \src "ls180.v:8320.2-8322.5" switch \main_spisdcard_miso_latch - attribute \src "ls180.v:8265.6-8265.31" + attribute \src "ls180.v:8320.6-8320.31" case 1'1 assign $0\main_spisdcard_miso[7:0] \main_spisdcard_miso_data case end - attribute \src "ls180.v:8269.2-8271.5" + attribute \src "ls180.v:8324.2-8326.5" switch \main_spisdcard_count_spimaster1_next_value_ce - attribute \src "ls180.v:8269.6-8269.51" + attribute \src "ls180.v:8324.6-8324.51" case 1'1 assign $0\main_spisdcard_count[2:0] \main_spisdcard_count_spimaster1_next_value case end - attribute \src "ls180.v:8272.2-8285.5" + attribute \src "ls180.v:8327.2-8340.5" switch \main_pwm0_enable - attribute \src "ls180.v:8272.6-8272.22" + attribute \src "ls180.v:8327.6-8327.22" case 1'1 - assign $0\main_pwm0_counter[31:0] $add$ls180.v:8273$2661_Y - attribute \src "ls180.v:8274.3-8278.6" - switch $lt$ls180.v:8274$2662_Y - attribute \src "ls180.v:8274.7-8274.44" + assign $0\main_pwm0_counter[31:0] $add$ls180.v:8328$2728_Y + attribute \src "ls180.v:8329.3-8333.6" + switch $lt$ls180.v:8329$2729_Y + attribute \src "ls180.v:8329.7-8329.44" case 1'1 assign $0\pwm[1:0] [0] 1'1 - attribute \src "ls180.v:8276.7-8276.11" + attribute \src "ls180.v:8331.7-8331.11" case assign $0\pwm[1:0] [0] 1'0 end - attribute \src "ls180.v:8279.3-8281.6" - switch $ge$ls180.v:8279$2664_Y - attribute \src "ls180.v:8279.7-8279.55" + attribute \src "ls180.v:8334.3-8336.6" + switch $ge$ls180.v:8334$2731_Y + attribute \src "ls180.v:8334.7-8334.55" case 1'1 assign $0\main_pwm0_counter[31:0] 0 case end - attribute \src "ls180.v:8282.6-8282.10" + attribute \src "ls180.v:8337.6-8337.10" case assign $0\main_pwm0_counter[31:0] 0 assign $0\pwm[1:0] [0] 1'0 end - attribute \src "ls180.v:8286.2-8299.5" + attribute \src "ls180.v:8341.2-8354.5" switch \main_pwm1_enable - attribute \src "ls180.v:8286.6-8286.22" + attribute \src "ls180.v:8341.6-8341.22" case 1'1 - assign $0\main_pwm1_counter[31:0] $add$ls180.v:8287$2665_Y - attribute \src "ls180.v:8288.3-8292.6" - switch $lt$ls180.v:8288$2666_Y - attribute \src "ls180.v:8288.7-8288.44" + assign $0\main_pwm1_counter[31:0] $add$ls180.v:8342$2732_Y + attribute \src "ls180.v:8343.3-8347.6" + switch $lt$ls180.v:8343$2733_Y + attribute \src "ls180.v:8343.7-8343.44" case 1'1 assign $0\pwm[1:0] [1] 1'1 - attribute \src "ls180.v:8290.7-8290.11" + attribute \src "ls180.v:8345.7-8345.11" case assign $0\pwm[1:0] [1] 1'0 end - attribute \src "ls180.v:8293.3-8295.6" - switch $ge$ls180.v:8293$2668_Y - attribute \src "ls180.v:8293.7-8293.55" + attribute \src "ls180.v:8348.3-8350.6" + switch $ge$ls180.v:8348$2735_Y + attribute \src "ls180.v:8348.7-8348.55" case 1'1 assign $0\main_pwm1_counter[31:0] 0 case end - attribute \src "ls180.v:8296.6-8296.10" + attribute \src "ls180.v:8351.6-8351.10" case assign $0\main_pwm1_counter[31:0] 0 assign $0\pwm[1:0] [1] 1'0 end - attribute \src "ls180.v:8300.2-8302.5" - switch $not$ls180.v:8300$2669_Y - attribute \src "ls180.v:8300.6-8300.32" + attribute \src "ls180.v:8355.2-8357.5" + switch $not$ls180.v:8355$2736_Y + attribute \src "ls180.v:8355.6-8355.32" case 1'1 - assign $0\main_sdphy_clocker_clks[8:0] $add$ls180.v:8301$2670_Y + assign $0\main_sdphy_clocker_clks[8:0] $add$ls180.v:8356$2737_Y case end - attribute \src "ls180.v:8306.2-8308.5" + attribute \src "ls180.v:8361.2-8363.5" switch \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce - attribute \src "ls180.v:8306.6-8306.57" + attribute \src "ls180.v:8361.6-8361.57" case 1'1 assign $0\main_sdphy_init_count[7:0] \main_sdphy_init_count_sdphy_sdphyinit_next_value case end - attribute \src "ls180.v:8310.2-8312.5" + attribute \src "ls180.v:8365.2-8367.5" switch \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce - attribute \src "ls180.v:8310.6-8310.57" + attribute \src "ls180.v:8365.6-8365.57" case 1'1 assign $0\main_sdphy_cmdw_count[7:0] \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value case end - attribute \src "ls180.v:8313.2-8315.5" + attribute \src "ls180.v:8368.2-8370.5" switch \main_sdphy_cmdr_cmdr_pads_in_valid - attribute \src "ls180.v:8313.6-8313.40" + attribute \src "ls180.v:8368.6-8368.40" case 1'1 - assign $0\main_sdphy_cmdr_cmdr_run[0:0] $or$ls180.v:8314$2671_Y + assign $0\main_sdphy_cmdr_cmdr_run[0:0] $or$ls180.v:8369$2738_Y case end - attribute \src "ls180.v:8316.2-8318.5" + attribute \src "ls180.v:8371.2-8373.5" switch \main_sdphy_cmdr_cmdr_converter_source_ready - attribute \src "ls180.v:8316.6-8316.49" + attribute \src "ls180.v:8371.6-8371.49" case 1'1 assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'0 case end - attribute \src "ls180.v:8319.2-8326.5" + attribute \src "ls180.v:8374.2-8381.5" switch \main_sdphy_cmdr_cmdr_converter_load_part - attribute \src "ls180.v:8319.6-8319.46" + attribute \src "ls180.v:8374.6-8374.46" case 1'1 - attribute \src "ls180.v:8320.3-8325.6" - switch $or$ls180.v:8320$2673_Y - attribute \src "ls180.v:8320.7-8320.98" + attribute \src "ls180.v:8375.3-8380.6" + switch $or$ls180.v:8375$2740_Y + attribute \src "ls180.v:8375.7-8375.98" case 1'1 assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000 assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'1 - attribute \src "ls180.v:8323.7-8323.11" + attribute \src "ls180.v:8378.7-8378.11" case - assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] $add$ls180.v:8324$2674_Y + assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] $add$ls180.v:8379$2741_Y end case end - attribute \src "ls180.v:8327.2-8340.5" - switch $and$ls180.v:8327$2675_Y - attribute \src "ls180.v:8327.6-8327.97" + attribute \src "ls180.v:8382.2-8395.5" + switch $and$ls180.v:8382$2742_Y + attribute \src "ls180.v:8382.6-8382.97" case 1'1 - attribute \src "ls180.v:8328.3-8334.6" - switch $and$ls180.v:8328$2676_Y - attribute \src "ls180.v:8328.7-8328.94" + attribute \src "ls180.v:8383.3-8389.6" + switch $and$ls180.v:8383$2743_Y + attribute \src "ls180.v:8383.7-8383.94" case 1'1 assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] \main_sdphy_cmdr_cmdr_converter_sink_first assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] \main_sdphy_cmdr_cmdr_converter_sink_last - attribute \src "ls180.v:8331.7-8331.11" + attribute \src "ls180.v:8386.7-8386.11" case assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] 1'0 assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] 1'0 end - attribute \src "ls180.v:8335.6-8335.10" + attribute \src "ls180.v:8390.6-8390.10" case - attribute \src "ls180.v:8336.3-8339.6" - switch $and$ls180.v:8336$2677_Y - attribute \src "ls180.v:8336.7-8336.94" + attribute \src "ls180.v:8391.3-8394.6" + switch $and$ls180.v:8391$2744_Y + attribute \src "ls180.v:8391.7-8391.94" case 1'1 - assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] $or$ls180.v:8337$2678_Y - assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] $or$ls180.v:8338$2679_Y + assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] $or$ls180.v:8392$2745_Y + assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] $or$ls180.v:8393$2746_Y case end end - attribute \src "ls180.v:8341.2-8368.5" + attribute \src "ls180.v:8396.2-8423.5" switch \main_sdphy_cmdr_cmdr_converter_load_part - attribute \src "ls180.v:8341.6-8341.46" + attribute \src "ls180.v:8396.6-8396.46" case 1'1 - attribute \src "ls180.v:8342.3-8367.10" + attribute \src "ls180.v:8397.3-8422.10" switch \main_sdphy_cmdr_cmdr_converter_demux attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -278620,16 +280053,16 @@ module \ls180 end case end - attribute \src "ls180.v:8369.2-8371.5" + attribute \src "ls180.v:8424.2-8426.5" switch \main_sdphy_cmdr_cmdr_converter_load_part - attribute \src "ls180.v:8369.6-8369.46" + attribute \src "ls180.v:8424.6-8424.46" case 1'1 - assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8370$2680_Y + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8425$2747_Y case end - attribute \src "ls180.v:8372.2-8377.5" - switch $or$ls180.v:8372$2682_Y - attribute \src "ls180.v:8372.6-8372.88" + attribute \src "ls180.v:8427.2-8432.5" + switch $or$ls180.v:8427$2749_Y + attribute \src "ls180.v:8427.6-8427.88" case 1'1 assign $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] \main_sdphy_cmdr_cmdr_buf_sink_valid assign $0\main_sdphy_cmdr_cmdr_buf_source_first[0:0] \main_sdphy_cmdr_cmdr_buf_sink_first @@ -278637,9 +280070,9 @@ module \ls180 assign $0\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] \main_sdphy_cmdr_cmdr_buf_sink_payload_data case end - attribute \src "ls180.v:8378.2-8383.5" + attribute \src "ls180.v:8433.2-8438.5" switch \main_sdphy_cmdr_cmdr_reset - attribute \src "ls180.v:8378.6-8378.32" + attribute \src "ls180.v:8433.6-8433.32" case 1'1 assign $0\main_sdphy_cmdr_cmdr_run[0:0] 1'0 assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000 @@ -278647,88 +280080,88 @@ module \ls180 assign $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] 1'0 case end - attribute \src "ls180.v:8385.2-8387.5" + attribute \src "ls180.v:8440.2-8442.5" switch \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0 - attribute \src "ls180.v:8385.6-8385.58" + attribute \src "ls180.v:8440.6-8440.58" case 1'1 assign $0\main_sdphy_cmdr_count[7:0] \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0 case end - attribute \src "ls180.v:8388.2-8390.5" + attribute \src "ls180.v:8443.2-8445.5" switch \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 - attribute \src "ls180.v:8388.6-8388.60" + attribute \src "ls180.v:8443.6-8443.60" case 1'1 assign $0\main_sdphy_cmdr_timeout[31:0] \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1 case end - attribute \src "ls180.v:8391.2-8393.5" + attribute \src "ls180.v:8446.2-8448.5" switch \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 - attribute \src "ls180.v:8391.6-8391.63" + attribute \src "ls180.v:8446.6-8446.63" case 1'1 assign $0\main_sdphy_cmdr_cmdr_reset[0:0] \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 case end - attribute \src "ls180.v:8394.2-8396.5" + attribute \src "ls180.v:8449.2-8451.5" switch \main_sdphy_dataw_crcr_pads_in_valid - attribute \src "ls180.v:8394.6-8394.41" + attribute \src "ls180.v:8449.6-8449.41" case 1'1 - assign $0\main_sdphy_dataw_crcr_run[0:0] $or$ls180.v:8395$2683_Y + assign $0\main_sdphy_dataw_crcr_run[0:0] $or$ls180.v:8450$2750_Y case end - attribute \src "ls180.v:8397.2-8399.5" + attribute \src "ls180.v:8452.2-8454.5" switch \main_sdphy_dataw_crcr_converter_source_ready - attribute \src "ls180.v:8397.6-8397.50" + attribute \src "ls180.v:8452.6-8452.50" case 1'1 assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'0 case end - attribute \src "ls180.v:8400.2-8407.5" + attribute \src "ls180.v:8455.2-8462.5" switch \main_sdphy_dataw_crcr_converter_load_part - attribute \src "ls180.v:8400.6-8400.47" + attribute \src "ls180.v:8455.6-8455.47" case 1'1 - attribute \src "ls180.v:8401.3-8406.6" - switch $or$ls180.v:8401$2685_Y - attribute \src "ls180.v:8401.7-8401.100" + attribute \src "ls180.v:8456.3-8461.6" + switch $or$ls180.v:8456$2752_Y + attribute \src "ls180.v:8456.7-8456.100" case 1'1 assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000 assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'1 - attribute \src "ls180.v:8404.7-8404.11" + attribute \src "ls180.v:8459.7-8459.11" case - assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] $add$ls180.v:8405$2686_Y + assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] $add$ls180.v:8460$2753_Y end case end - attribute \src "ls180.v:8408.2-8421.5" - switch $and$ls180.v:8408$2687_Y - attribute \src "ls180.v:8408.6-8408.99" + attribute \src "ls180.v:8463.2-8476.5" + switch $and$ls180.v:8463$2754_Y + attribute \src "ls180.v:8463.6-8463.99" case 1'1 - attribute \src "ls180.v:8409.3-8415.6" - switch $and$ls180.v:8409$2688_Y - attribute \src "ls180.v:8409.7-8409.96" + attribute \src "ls180.v:8464.3-8470.6" + switch $and$ls180.v:8464$2755_Y + attribute \src "ls180.v:8464.7-8464.96" case 1'1 assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] \main_sdphy_dataw_crcr_converter_sink_first assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] \main_sdphy_dataw_crcr_converter_sink_last - attribute \src "ls180.v:8412.7-8412.11" + attribute \src "ls180.v:8467.7-8467.11" case assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] 1'0 assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] 1'0 end - attribute \src "ls180.v:8416.6-8416.10" + attribute \src "ls180.v:8471.6-8471.10" case - attribute \src "ls180.v:8417.3-8420.6" - switch $and$ls180.v:8417$2689_Y - attribute \src "ls180.v:8417.7-8417.96" + attribute \src "ls180.v:8472.3-8475.6" + switch $and$ls180.v:8472$2756_Y + attribute \src "ls180.v:8472.7-8472.96" case 1'1 - assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] $or$ls180.v:8418$2690_Y - assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] $or$ls180.v:8419$2691_Y + assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] $or$ls180.v:8473$2757_Y + assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] $or$ls180.v:8474$2758_Y case end end - attribute \src "ls180.v:8422.2-8449.5" + attribute \src "ls180.v:8477.2-8504.5" switch \main_sdphy_dataw_crcr_converter_load_part - attribute \src "ls180.v:8422.6-8422.47" + attribute \src "ls180.v:8477.6-8477.47" case 1'1 - attribute \src "ls180.v:8423.3-8448.10" + attribute \src "ls180.v:8478.3-8503.10" switch \main_sdphy_dataw_crcr_converter_demux attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -278758,16 +280191,16 @@ module \ls180 end case end - attribute \src "ls180.v:8450.2-8452.5" + attribute \src "ls180.v:8505.2-8507.5" switch \main_sdphy_dataw_crcr_converter_load_part - attribute \src "ls180.v:8450.6-8450.47" + attribute \src "ls180.v:8505.6-8505.47" case 1'1 - assign $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8451$2692_Y + assign $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8506$2759_Y case end - attribute \src "ls180.v:8453.2-8458.5" - switch $or$ls180.v:8453$2694_Y - attribute \src "ls180.v:8453.6-8453.90" + attribute \src "ls180.v:8508.2-8513.5" + switch $or$ls180.v:8508$2761_Y + attribute \src "ls180.v:8508.6-8508.90" case 1'1 assign $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] \main_sdphy_dataw_crcr_buf_sink_valid assign $0\main_sdphy_dataw_crcr_buf_source_first[0:0] \main_sdphy_dataw_crcr_buf_sink_first @@ -278775,9 +280208,9 @@ module \ls180 assign $0\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] \main_sdphy_dataw_crcr_buf_sink_payload_data case end - attribute \src "ls180.v:8459.2-8464.5" + attribute \src "ls180.v:8514.2-8519.5" switch \main_sdphy_dataw_crcr_reset - attribute \src "ls180.v:8459.6-8459.33" + attribute \src "ls180.v:8514.6-8514.33" case 1'1 assign $0\main_sdphy_dataw_crcr_run[0:0] 1'0 assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000 @@ -278785,81 +280218,81 @@ module \ls180 assign $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] 1'0 case end - attribute \src "ls180.v:8466.2-8468.5" + attribute \src "ls180.v:8521.2-8523.5" switch \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce - attribute \src "ls180.v:8466.6-8466.63" + attribute \src "ls180.v:8521.6-8521.63" case 1'1 assign $0\main_sdphy_dataw_crcr_reset[0:0] \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value case end - attribute \src "ls180.v:8470.2-8472.5" + attribute \src "ls180.v:8525.2-8527.5" switch \main_sdphy_dataw_count_sdphy_fsm_next_value_ce - attribute \src "ls180.v:8470.6-8470.52" + attribute \src "ls180.v:8525.6-8525.52" case 1'1 assign $0\main_sdphy_dataw_count[7:0] \main_sdphy_dataw_count_sdphy_fsm_next_value case end - attribute \src "ls180.v:8473.2-8475.5" + attribute \src "ls180.v:8528.2-8530.5" switch \main_sdphy_datar_datar_pads_in_valid - attribute \src "ls180.v:8473.6-8473.42" + attribute \src "ls180.v:8528.6-8528.42" case 1'1 - assign $0\main_sdphy_datar_datar_run[0:0] $or$ls180.v:8474$2695_Y + assign $0\main_sdphy_datar_datar_run[0:0] $or$ls180.v:8529$2762_Y case end - attribute \src "ls180.v:8476.2-8478.5" + attribute \src "ls180.v:8531.2-8533.5" switch \main_sdphy_datar_datar_converter_source_ready - attribute \src "ls180.v:8476.6-8476.51" + attribute \src "ls180.v:8531.6-8531.51" case 1'1 assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'0 case end - attribute \src "ls180.v:8479.2-8486.5" + attribute \src "ls180.v:8534.2-8541.5" switch \main_sdphy_datar_datar_converter_load_part - attribute \src "ls180.v:8479.6-8479.48" + attribute \src "ls180.v:8534.6-8534.48" case 1'1 - attribute \src "ls180.v:8480.3-8485.6" - switch $or$ls180.v:8480$2697_Y - attribute \src "ls180.v:8480.7-8480.102" + attribute \src "ls180.v:8535.3-8540.6" + switch $or$ls180.v:8535$2764_Y + attribute \src "ls180.v:8535.7-8535.102" case 1'1 assign $0\main_sdphy_datar_datar_converter_demux[0:0] 1'0 assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'1 - attribute \src "ls180.v:8483.7-8483.11" + attribute \src "ls180.v:8538.7-8538.11" case - assign $0\main_sdphy_datar_datar_converter_demux[0:0] $add$ls180.v:8484$2698_Y + assign $0\main_sdphy_datar_datar_converter_demux[0:0] $add$ls180.v:8539$2765_Y end case end - attribute \src "ls180.v:8487.2-8500.5" - switch $and$ls180.v:8487$2699_Y - attribute \src "ls180.v:8487.6-8487.101" + attribute \src "ls180.v:8542.2-8555.5" + switch $and$ls180.v:8542$2766_Y + attribute \src "ls180.v:8542.6-8542.101" case 1'1 - attribute \src "ls180.v:8488.3-8494.6" - switch $and$ls180.v:8488$2700_Y - attribute \src "ls180.v:8488.7-8488.98" + attribute \src "ls180.v:8543.3-8549.6" + switch $and$ls180.v:8543$2767_Y + attribute \src "ls180.v:8543.7-8543.98" case 1'1 assign $0\main_sdphy_datar_datar_converter_source_first[0:0] \main_sdphy_datar_datar_converter_sink_first assign $0\main_sdphy_datar_datar_converter_source_last[0:0] \main_sdphy_datar_datar_converter_sink_last - attribute \src "ls180.v:8491.7-8491.11" + attribute \src "ls180.v:8546.7-8546.11" case assign $0\main_sdphy_datar_datar_converter_source_first[0:0] 1'0 assign $0\main_sdphy_datar_datar_converter_source_last[0:0] 1'0 end - attribute \src "ls180.v:8495.6-8495.10" + attribute \src "ls180.v:8550.6-8550.10" case - attribute \src "ls180.v:8496.3-8499.6" - switch $and$ls180.v:8496$2701_Y - attribute \src "ls180.v:8496.7-8496.98" + attribute \src "ls180.v:8551.3-8554.6" + switch $and$ls180.v:8551$2768_Y + attribute \src "ls180.v:8551.7-8551.98" case 1'1 - assign $0\main_sdphy_datar_datar_converter_source_first[0:0] $or$ls180.v:8497$2702_Y - assign $0\main_sdphy_datar_datar_converter_source_last[0:0] $or$ls180.v:8498$2703_Y + assign $0\main_sdphy_datar_datar_converter_source_first[0:0] $or$ls180.v:8552$2769_Y + assign $0\main_sdphy_datar_datar_converter_source_last[0:0] $or$ls180.v:8553$2770_Y case end end - attribute \src "ls180.v:8501.2-8510.5" + attribute \src "ls180.v:8556.2-8565.5" switch \main_sdphy_datar_datar_converter_load_part - attribute \src "ls180.v:8501.6-8501.48" + attribute \src "ls180.v:8556.6-8556.48" case 1'1 - attribute \src "ls180.v:8502.3-8509.10" + attribute \src "ls180.v:8557.3-8564.10" switch \main_sdphy_datar_datar_converter_demux attribute \src "ls180.v:0.0-0.0" case 1'0 @@ -278871,16 +280304,16 @@ module \ls180 end case end - attribute \src "ls180.v:8511.2-8513.5" + attribute \src "ls180.v:8566.2-8568.5" switch \main_sdphy_datar_datar_converter_load_part - attribute \src "ls180.v:8511.6-8511.48" + attribute \src "ls180.v:8566.6-8566.48" case 1'1 - assign $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] $add$ls180.v:8512$2704_Y + assign $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] $add$ls180.v:8567$2771_Y case end - attribute \src "ls180.v:8514.2-8519.5" - switch $or$ls180.v:8514$2706_Y - attribute \src "ls180.v:8514.6-8514.92" + attribute \src "ls180.v:8569.2-8574.5" + switch $or$ls180.v:8569$2773_Y + attribute \src "ls180.v:8569.6-8569.92" case 1'1 assign $0\main_sdphy_datar_datar_buf_source_valid[0:0] \main_sdphy_datar_datar_buf_sink_valid assign $0\main_sdphy_datar_datar_buf_source_first[0:0] \main_sdphy_datar_datar_buf_sink_first @@ -278888,9 +280321,9 @@ module \ls180 assign $0\main_sdphy_datar_datar_buf_source_payload_data[7:0] \main_sdphy_datar_datar_buf_sink_payload_data case end - attribute \src "ls180.v:8520.2-8525.5" + attribute \src "ls180.v:8575.2-8580.5" switch \main_sdphy_datar_datar_reset - attribute \src "ls180.v:8520.6-8520.34" + attribute \src "ls180.v:8575.6-8575.34" case 1'1 assign $0\main_sdphy_datar_datar_run[0:0] 1'0 assign $0\main_sdphy_datar_datar_converter_demux[0:0] 1'0 @@ -278898,598 +280331,610 @@ module \ls180 assign $0\main_sdphy_datar_datar_buf_source_valid[0:0] 1'0 case end - attribute \src "ls180.v:8527.2-8529.5" + attribute \src "ls180.v:8582.2-8584.5" switch \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0 - attribute \src "ls180.v:8527.6-8527.60" + attribute \src "ls180.v:8582.6-8582.60" case 1'1 assign $0\main_sdphy_datar_count[9:0] \main_sdphy_datar_count_sdphy_sdphydatar_next_value0 case end - attribute \src "ls180.v:8530.2-8532.5" + attribute \src "ls180.v:8585.2-8587.5" switch \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1 - attribute \src "ls180.v:8530.6-8530.62" + attribute \src "ls180.v:8585.6-8585.62" case 1'1 assign $0\main_sdphy_datar_timeout[31:0] \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1 case end - attribute \src "ls180.v:8533.2-8535.5" + attribute \src "ls180.v:8588.2-8590.5" switch \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 - attribute \src "ls180.v:8533.6-8533.66" + attribute \src "ls180.v:8588.6-8588.66" case 1'1 assign $0\main_sdphy_datar_datar_reset[0:0] \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 case end - attribute \src "ls180.v:8536.2-8542.5" + attribute \src "ls180.v:8591.2-8597.5" switch \main_sdcore_crc7_inserter_clr - attribute \src "ls180.v:8536.6-8536.35" + attribute \src "ls180.v:8591.6-8591.35" case 1'1 assign $0\main_sdcore_crc7_inserter_crcreg0[6:0] 7'0000000 - attribute \src "ls180.v:8538.6-8538.10" + attribute \src "ls180.v:8593.6-8593.10" case - attribute \src "ls180.v:8539.3-8541.6" + attribute \src "ls180.v:8594.3-8596.6" switch \main_sdcore_crc7_inserter_enable - attribute \src "ls180.v:8539.7-8539.39" + attribute \src "ls180.v:8594.7-8594.39" case 1'1 assign $0\main_sdcore_crc7_inserter_crcreg0[6:0] \main_sdcore_crc7_inserter_crcreg40 case end end - attribute \src "ls180.v:8543.2-8549.5" + attribute \src "ls180.v:8598.2-8604.5" switch \main_sdcore_crc16_inserter_crc0_clr - attribute \src "ls180.v:8543.6-8543.41" + attribute \src "ls180.v:8598.6-8598.41" case 1'1 assign $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8545.6-8545.10" + attribute \src "ls180.v:8600.6-8600.10" case - attribute \src "ls180.v:8546.3-8548.6" + attribute \src "ls180.v:8601.3-8603.6" switch \main_sdcore_crc16_inserter_crc0_enable - attribute \src "ls180.v:8546.7-8546.45" + attribute \src "ls180.v:8601.7-8601.45" case 1'1 assign $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] \main_sdcore_crc16_inserter_crc0_crcreg2 case end end - attribute \src "ls180.v:8550.2-8556.5" + attribute \src "ls180.v:8605.2-8611.5" switch \main_sdcore_crc16_inserter_crc1_clr - attribute \src "ls180.v:8550.6-8550.41" + attribute \src "ls180.v:8605.6-8605.41" case 1'1 assign $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8552.6-8552.10" + attribute \src "ls180.v:8607.6-8607.10" case - attribute \src "ls180.v:8553.3-8555.6" + attribute \src "ls180.v:8608.3-8610.6" switch \main_sdcore_crc16_inserter_crc1_enable - attribute \src "ls180.v:8553.7-8553.45" + attribute \src "ls180.v:8608.7-8608.45" case 1'1 assign $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] \main_sdcore_crc16_inserter_crc1_crcreg2 case end end - attribute \src "ls180.v:8557.2-8563.5" + attribute \src "ls180.v:8612.2-8618.5" switch \main_sdcore_crc16_inserter_crc2_clr - attribute \src "ls180.v:8557.6-8557.41" + attribute \src "ls180.v:8612.6-8612.41" case 1'1 assign $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8559.6-8559.10" + attribute \src "ls180.v:8614.6-8614.10" case - attribute \src "ls180.v:8560.3-8562.6" + attribute \src "ls180.v:8615.3-8617.6" switch \main_sdcore_crc16_inserter_crc2_enable - attribute \src "ls180.v:8560.7-8560.45" + attribute \src "ls180.v:8615.7-8615.45" case 1'1 assign $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] \main_sdcore_crc16_inserter_crc2_crcreg2 case end end - attribute \src "ls180.v:8564.2-8570.5" + attribute \src "ls180.v:8619.2-8625.5" switch \main_sdcore_crc16_inserter_crc3_clr - attribute \src "ls180.v:8564.6-8564.41" + attribute \src "ls180.v:8619.6-8619.41" case 1'1 assign $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8566.6-8566.10" + attribute \src "ls180.v:8621.6-8621.10" case - attribute \src "ls180.v:8567.3-8569.6" + attribute \src "ls180.v:8622.3-8624.6" switch \main_sdcore_crc16_inserter_crc3_enable - attribute \src "ls180.v:8567.7-8567.45" + attribute \src "ls180.v:8622.7-8622.45" case 1'1 assign $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] \main_sdcore_crc16_inserter_crc3_crcreg2 case end end - attribute \src "ls180.v:8572.2-8574.5" + attribute \src "ls180.v:8627.2-8629.5" switch \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 - attribute \src "ls180.v:8572.6-8572.82" + attribute \src "ls180.v:8627.6-8627.82" case 1'1 assign $0\main_sdcore_crc16_inserter_crctmp0[15:0] \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 case end - attribute \src "ls180.v:8575.2-8577.5" + attribute \src "ls180.v:8630.2-8632.5" switch \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 - attribute \src "ls180.v:8575.6-8575.82" + attribute \src "ls180.v:8630.6-8630.82" case 1'1 assign $0\main_sdcore_crc16_inserter_crctmp1[15:0] \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 case end - attribute \src "ls180.v:8578.2-8580.5" + attribute \src "ls180.v:8633.2-8635.5" switch \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 - attribute \src "ls180.v:8578.6-8578.82" + attribute \src "ls180.v:8633.6-8633.82" case 1'1 assign $0\main_sdcore_crc16_inserter_crctmp2[15:0] \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 case end - attribute \src "ls180.v:8581.2-8583.5" + attribute \src "ls180.v:8636.2-8638.5" switch \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 - attribute \src "ls180.v:8581.6-8581.82" + attribute \src "ls180.v:8636.6-8636.82" case 1'1 assign $0\main_sdcore_crc16_inserter_crctmp3[15:0] \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 case end - attribute \src "ls180.v:8584.2-8586.5" + attribute \src "ls180.v:8639.2-8641.5" switch \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 - attribute \src "ls180.v:8584.6-8584.78" + attribute \src "ls180.v:8639.6-8639.78" case 1'1 assign $0\main_sdcore_crc16_inserter_cnt[2:0] \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 case end - attribute \src "ls180.v:8587.2-8589.5" - switch $and$ls180.v:8587$2707_Y - attribute \src "ls180.v:8587.6-8587.83" + attribute \src "ls180.v:8642.2-8644.5" + switch $and$ls180.v:8642$2774_Y + attribute \src "ls180.v:8642.6-8642.83" case 1'1 assign $0\main_sdcore_crc16_checker_crctmp0[15:0] \main_sdcore_crc16_checker_crc0_crc case end - attribute \src "ls180.v:8590.2-8592.5" - switch $and$ls180.v:8590$2708_Y - attribute \src "ls180.v:8590.6-8590.83" + attribute \src "ls180.v:8645.2-8647.5" + switch $and$ls180.v:8645$2775_Y + attribute \src "ls180.v:8645.6-8645.83" case 1'1 assign $0\main_sdcore_crc16_checker_crctmp1[15:0] \main_sdcore_crc16_checker_crc1_crc case end - attribute \src "ls180.v:8593.2-8595.5" - switch $and$ls180.v:8593$2709_Y - attribute \src "ls180.v:8593.6-8593.83" + attribute \src "ls180.v:8648.2-8650.5" + switch $and$ls180.v:8648$2776_Y + attribute \src "ls180.v:8648.6-8648.83" case 1'1 assign $0\main_sdcore_crc16_checker_crctmp2[15:0] \main_sdcore_crc16_checker_crc2_crc case end - attribute \src "ls180.v:8596.2-8598.5" - switch $and$ls180.v:8596$2710_Y - attribute \src "ls180.v:8596.6-8596.83" + attribute \src "ls180.v:8651.2-8653.5" + switch $and$ls180.v:8651$2777_Y + attribute \src "ls180.v:8651.6-8651.83" case 1'1 assign $0\main_sdcore_crc16_checker_crctmp3[15:0] \main_sdcore_crc16_checker_crc3_crc case end - attribute \src "ls180.v:8599.2-8603.5" - switch $and$ls180.v:8599$2711_Y - attribute \src "ls180.v:8599.6-8599.83" + attribute \src "ls180.v:8654.2-8658.5" + switch $and$ls180.v:8654$2778_Y + attribute \src "ls180.v:8654.6-8654.83" case 1'1 assign $0\main_sdcore_crc16_checker_fifo0[15:0] { \main_sdcore_crc16_checker_fifo0 [13:0] \main_sdcore_crc16_checker_sink_payload_data [7] \main_sdcore_crc16_checker_sink_payload_data [3] } assign $0\main_sdcore_crc16_checker_val[7:0] [7] \main_sdcore_crc16_checker_fifo0 [13] assign $0\main_sdcore_crc16_checker_val[7:0] [3] \main_sdcore_crc16_checker_fifo0 [12] case end - attribute \src "ls180.v:8604.2-8608.5" - switch $and$ls180.v:8604$2712_Y - attribute \src "ls180.v:8604.6-8604.83" + attribute \src "ls180.v:8659.2-8663.5" + switch $and$ls180.v:8659$2779_Y + attribute \src "ls180.v:8659.6-8659.83" case 1'1 assign $0\main_sdcore_crc16_checker_fifo1[15:0] { \main_sdcore_crc16_checker_fifo1 [13:0] \main_sdcore_crc16_checker_sink_payload_data [6] \main_sdcore_crc16_checker_sink_payload_data [2] } assign $0\main_sdcore_crc16_checker_val[7:0] [6] \main_sdcore_crc16_checker_fifo1 [13] assign $0\main_sdcore_crc16_checker_val[7:0] [2] \main_sdcore_crc16_checker_fifo1 [12] case end - attribute \src "ls180.v:8609.2-8613.5" - switch $and$ls180.v:8609$2713_Y - attribute \src "ls180.v:8609.6-8609.83" + attribute \src "ls180.v:8664.2-8668.5" + switch $and$ls180.v:8664$2780_Y + attribute \src "ls180.v:8664.6-8664.83" case 1'1 assign $0\main_sdcore_crc16_checker_fifo2[15:0] { \main_sdcore_crc16_checker_fifo2 [13:0] \main_sdcore_crc16_checker_sink_payload_data [5] \main_sdcore_crc16_checker_sink_payload_data [1] } assign $0\main_sdcore_crc16_checker_val[7:0] [5] \main_sdcore_crc16_checker_fifo2 [13] assign $0\main_sdcore_crc16_checker_val[7:0] [1] \main_sdcore_crc16_checker_fifo2 [12] case end - attribute \src "ls180.v:8614.2-8618.5" - switch $and$ls180.v:8614$2714_Y - attribute \src "ls180.v:8614.6-8614.83" + attribute \src "ls180.v:8669.2-8673.5" + switch $and$ls180.v:8669$2781_Y + attribute \src "ls180.v:8669.6-8669.83" case 1'1 assign $0\main_sdcore_crc16_checker_fifo3[15:0] { \main_sdcore_crc16_checker_fifo3 [13:0] \main_sdcore_crc16_checker_sink_payload_data [4] \main_sdcore_crc16_checker_sink_payload_data [0] } assign $0\main_sdcore_crc16_checker_val[7:0] [4] \main_sdcore_crc16_checker_fifo3 [13] assign $0\main_sdcore_crc16_checker_val[7:0] [0] \main_sdcore_crc16_checker_fifo3 [12] case end - attribute \src "ls180.v:8619.2-8627.5" - switch $and$ls180.v:8619$2715_Y - attribute \src "ls180.v:8619.6-8619.83" + attribute \src "ls180.v:8674.2-8682.5" + switch $and$ls180.v:8674$2782_Y + attribute \src "ls180.v:8674.6-8674.83" case 1'1 - attribute \src "ls180.v:8620.3-8626.6" + attribute \src "ls180.v:8675.3-8681.6" switch \main_sdcore_crc16_checker_sink_last - attribute \src "ls180.v:8620.7-8620.42" + attribute \src "ls180.v:8675.7-8675.42" case 1'1 assign $0\main_sdcore_crc16_checker_cnt[3:0] 4'0000 - attribute \src "ls180.v:8622.7-8622.11" + attribute \src "ls180.v:8677.7-8677.11" case - attribute \src "ls180.v:8623.4-8625.7" - switch $ne$ls180.v:8623$2716_Y - attribute \src "ls180.v:8623.8-8623.48" + attribute \src "ls180.v:8678.4-8680.7" + switch $ne$ls180.v:8678$2783_Y + attribute \src "ls180.v:8678.8-8678.48" case 1'1 - assign $0\main_sdcore_crc16_checker_cnt[3:0] $add$ls180.v:8624$2717_Y + assign $0\main_sdcore_crc16_checker_cnt[3:0] $add$ls180.v:8679$2784_Y case end end case end - attribute \src "ls180.v:8628.2-8634.5" + attribute \src "ls180.v:8683.2-8689.5" switch \main_sdcore_crc16_checker_crc0_clr - attribute \src "ls180.v:8628.6-8628.40" + attribute \src "ls180.v:8683.6-8683.40" case 1'1 assign $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8630.6-8630.10" + attribute \src "ls180.v:8685.6-8685.10" case - attribute \src "ls180.v:8631.3-8633.6" + attribute \src "ls180.v:8686.3-8688.6" switch \main_sdcore_crc16_checker_crc0_enable - attribute \src "ls180.v:8631.7-8631.44" + attribute \src "ls180.v:8686.7-8686.44" case 1'1 assign $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] \main_sdcore_crc16_checker_crc0_crcreg2 case end end - attribute \src "ls180.v:8635.2-8641.5" + attribute \src "ls180.v:8690.2-8696.5" switch \main_sdcore_crc16_checker_crc1_clr - attribute \src "ls180.v:8635.6-8635.40" + attribute \src "ls180.v:8690.6-8690.40" case 1'1 assign $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8637.6-8637.10" + attribute \src "ls180.v:8692.6-8692.10" case - attribute \src "ls180.v:8638.3-8640.6" + attribute \src "ls180.v:8693.3-8695.6" switch \main_sdcore_crc16_checker_crc1_enable - attribute \src "ls180.v:8638.7-8638.44" + attribute \src "ls180.v:8693.7-8693.44" case 1'1 assign $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] \main_sdcore_crc16_checker_crc1_crcreg2 case end end - attribute \src "ls180.v:8642.2-8648.5" + attribute \src "ls180.v:8697.2-8703.5" switch \main_sdcore_crc16_checker_crc2_clr - attribute \src "ls180.v:8642.6-8642.40" + attribute \src "ls180.v:8697.6-8697.40" case 1'1 assign $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8644.6-8644.10" + attribute \src "ls180.v:8699.6-8699.10" case - attribute \src "ls180.v:8645.3-8647.6" + attribute \src "ls180.v:8700.3-8702.6" switch \main_sdcore_crc16_checker_crc2_enable - attribute \src "ls180.v:8645.7-8645.44" + attribute \src "ls180.v:8700.7-8700.44" case 1'1 assign $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] \main_sdcore_crc16_checker_crc2_crcreg2 case end end - attribute \src "ls180.v:8649.2-8655.5" + attribute \src "ls180.v:8704.2-8710.5" switch \main_sdcore_crc16_checker_crc3_clr - attribute \src "ls180.v:8649.6-8649.40" + attribute \src "ls180.v:8704.6-8704.40" case 1'1 assign $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8651.6-8651.10" + attribute \src "ls180.v:8706.6-8706.10" case - attribute \src "ls180.v:8652.3-8654.6" + attribute \src "ls180.v:8707.3-8709.6" switch \main_sdcore_crc16_checker_crc3_enable - attribute \src "ls180.v:8652.7-8652.44" + attribute \src "ls180.v:8707.7-8707.44" case 1'1 assign $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] \main_sdcore_crc16_checker_crc3_crcreg2 case end end - attribute \src "ls180.v:8657.2-8659.5" + attribute \src "ls180.v:8712.2-8714.5" switch \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0 - attribute \src "ls180.v:8657.6-8657.52" + attribute \src "ls180.v:8712.6-8712.52" case 1'1 assign $0\main_sdcore_cmd_done[0:0] \main_sdcore_cmd_done_sdcore_fsm_next_value0 case end - attribute \src "ls180.v:8660.2-8662.5" + attribute \src "ls180.v:8715.2-8717.5" switch \main_sdcore_data_done_sdcore_fsm_next_value_ce1 - attribute \src "ls180.v:8660.6-8660.53" + attribute \src "ls180.v:8715.6-8715.53" case 1'1 assign $0\main_sdcore_data_done[0:0] \main_sdcore_data_done_sdcore_fsm_next_value1 case end - attribute \src "ls180.v:8663.2-8665.5" + attribute \src "ls180.v:8718.2-8720.5" switch \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2 - attribute \src "ls180.v:8663.6-8663.53" + attribute \src "ls180.v:8718.6-8718.53" case 1'1 assign $0\main_sdcore_cmd_count[2:0] \main_sdcore_cmd_count_sdcore_fsm_next_value2 case end - attribute \src "ls180.v:8666.2-8668.5" + attribute \src "ls180.v:8721.2-8723.5" switch \main_sdcore_data_count_sdcore_fsm_next_value_ce3 - attribute \src "ls180.v:8666.6-8666.54" + attribute \src "ls180.v:8721.6-8721.54" case 1'1 assign $0\main_sdcore_data_count[31:0] \main_sdcore_data_count_sdcore_fsm_next_value3 case end - attribute \src "ls180.v:8669.2-8671.5" + attribute \src "ls180.v:8724.2-8726.5" switch \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4 - attribute \src "ls180.v:8669.6-8669.53" + attribute \src "ls180.v:8724.6-8724.53" case 1'1 assign $0\main_sdcore_cmd_error[0:0] \main_sdcore_cmd_error_sdcore_fsm_next_value4 case end - attribute \src "ls180.v:8672.2-8674.5" + attribute \src "ls180.v:8727.2-8729.5" switch \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 - attribute \src "ls180.v:8672.6-8672.55" + attribute \src "ls180.v:8727.6-8727.55" case 1'1 assign $0\main_sdcore_cmd_timeout[0:0] \main_sdcore_cmd_timeout_sdcore_fsm_next_value5 case end - attribute \src "ls180.v:8675.2-8677.5" + attribute \src "ls180.v:8730.2-8732.5" switch \main_sdcore_data_error_sdcore_fsm_next_value_ce6 - attribute \src "ls180.v:8675.6-8675.54" + attribute \src "ls180.v:8730.6-8730.54" case 1'1 assign $0\main_sdcore_data_error[0:0] \main_sdcore_data_error_sdcore_fsm_next_value6 case end - attribute \src "ls180.v:8678.2-8680.5" + attribute \src "ls180.v:8733.2-8735.5" switch \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7 - attribute \src "ls180.v:8678.6-8678.56" + attribute \src "ls180.v:8733.6-8733.56" case 1'1 assign $0\main_sdcore_data_timeout[0:0] \main_sdcore_data_timeout_sdcore_fsm_next_value7 case end - attribute \src "ls180.v:8681.2-8683.5" + attribute \src "ls180.v:8736.2-8738.5" switch \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 - attribute \src "ls180.v:8681.6-8681.63" + attribute \src "ls180.v:8736.6-8736.63" case 1'1 assign $0\main_sdcore_cmd_response_status[127:0] \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 case end - attribute \src "ls180.v:8684.2-8686.5" - switch $and$ls180.v:8684$2720_Y - attribute \src "ls180.v:8684.6-8684.120" + attribute \src "ls180.v:8739.2-8741.5" + switch $and$ls180.v:8739$2787_Y + attribute \src "ls180.v:8739.6-8739.120" case 1'1 - assign $0\main_sdblock2mem_fifo_produce[4:0] $add$ls180.v:8685$2721_Y + assign $0\main_sdblock2mem_fifo_produce[4:0] $add$ls180.v:8740$2788_Y case end - attribute \src "ls180.v:8687.2-8689.5" + attribute \src "ls180.v:8742.2-8744.5" switch \main_sdblock2mem_fifo_do_read - attribute \src "ls180.v:8687.6-8687.35" + attribute \src "ls180.v:8742.6-8742.35" case 1'1 - assign $0\main_sdblock2mem_fifo_consume[4:0] $add$ls180.v:8688$2722_Y + assign $0\main_sdblock2mem_fifo_consume[4:0] $add$ls180.v:8743$2789_Y case end - attribute \src "ls180.v:8690.2-8698.5" - switch $and$ls180.v:8690$2725_Y - attribute \src "ls180.v:8690.6-8690.120" + attribute \src "ls180.v:8745.2-8753.5" + switch $and$ls180.v:8745$2792_Y + attribute \src "ls180.v:8745.6-8745.120" case 1'1 - attribute \src "ls180.v:8691.3-8693.6" - switch $not$ls180.v:8691$2726_Y - attribute \src "ls180.v:8691.7-8691.39" + attribute \src "ls180.v:8746.3-8748.6" + switch $not$ls180.v:8746$2793_Y + attribute \src "ls180.v:8746.7-8746.39" case 1'1 - assign $0\main_sdblock2mem_fifo_level[5:0] $add$ls180.v:8692$2727_Y + assign $0\main_sdblock2mem_fifo_level[5:0] $add$ls180.v:8747$2794_Y case end - attribute \src "ls180.v:8694.6-8694.10" + attribute \src "ls180.v:8749.6-8749.10" case - attribute \src "ls180.v:8695.3-8697.6" + attribute \src "ls180.v:8750.3-8752.6" switch \main_sdblock2mem_fifo_do_read - attribute \src "ls180.v:8695.7-8695.36" + attribute \src "ls180.v:8750.7-8750.36" case 1'1 - assign $0\main_sdblock2mem_fifo_level[5:0] $sub$ls180.v:8696$2728_Y + assign $0\main_sdblock2mem_fifo_level[5:0] $sub$ls180.v:8751$2795_Y case end end - attribute \src "ls180.v:8699.2-8701.5" + attribute \src "ls180.v:8754.2-8756.5" switch \main_sdblock2mem_converter_source_ready - attribute \src "ls180.v:8699.6-8699.45" + attribute \src "ls180.v:8754.6-8754.45" case 1'1 assign $0\main_sdblock2mem_converter_strobe_all[0:0] 1'0 case end - attribute \src "ls180.v:8702.2-8709.5" + attribute \src "ls180.v:8757.2-8764.5" switch \main_sdblock2mem_converter_load_part - attribute \src "ls180.v:8702.6-8702.42" + attribute \src "ls180.v:8757.6-8757.42" case 1'1 - attribute \src "ls180.v:8703.3-8708.6" - switch $or$ls180.v:8703$2730_Y - attribute \src "ls180.v:8703.7-8703.90" + attribute \src "ls180.v:8758.3-8763.6" + switch $or$ls180.v:8758$2797_Y + attribute \src "ls180.v:8758.7-8758.90" case 1'1 - assign $0\main_sdblock2mem_converter_demux[1:0] 2'00 + assign $0\main_sdblock2mem_converter_demux[2:0] 3'000 assign $0\main_sdblock2mem_converter_strobe_all[0:0] 1'1 - attribute \src "ls180.v:8706.7-8706.11" + attribute \src "ls180.v:8761.7-8761.11" case - assign $0\main_sdblock2mem_converter_demux[1:0] $add$ls180.v:8707$2731_Y + assign $0\main_sdblock2mem_converter_demux[2:0] $add$ls180.v:8762$2798_Y end case end - attribute \src "ls180.v:8710.2-8723.5" - switch $and$ls180.v:8710$2732_Y - attribute \src "ls180.v:8710.6-8710.89" + attribute \src "ls180.v:8765.2-8778.5" + switch $and$ls180.v:8765$2799_Y + attribute \src "ls180.v:8765.6-8765.89" case 1'1 - attribute \src "ls180.v:8711.3-8717.6" - switch $and$ls180.v:8711$2733_Y - attribute \src "ls180.v:8711.7-8711.86" + attribute \src "ls180.v:8766.3-8772.6" + switch $and$ls180.v:8766$2800_Y + attribute \src "ls180.v:8766.7-8766.86" case 1'1 assign $0\main_sdblock2mem_converter_source_first[0:0] \main_sdblock2mem_converter_sink_first assign $0\main_sdblock2mem_converter_source_last[0:0] \main_sdblock2mem_converter_sink_last - attribute \src "ls180.v:8714.7-8714.11" + attribute \src "ls180.v:8769.7-8769.11" case assign $0\main_sdblock2mem_converter_source_first[0:0] 1'0 assign $0\main_sdblock2mem_converter_source_last[0:0] 1'0 end - attribute \src "ls180.v:8718.6-8718.10" + attribute \src "ls180.v:8773.6-8773.10" case - attribute \src "ls180.v:8719.3-8722.6" - switch $and$ls180.v:8719$2734_Y - attribute \src "ls180.v:8719.7-8719.86" + attribute \src "ls180.v:8774.3-8777.6" + switch $and$ls180.v:8774$2801_Y + attribute \src "ls180.v:8774.7-8774.86" case 1'1 - assign $0\main_sdblock2mem_converter_source_first[0:0] $or$ls180.v:8720$2735_Y - assign $0\main_sdblock2mem_converter_source_last[0:0] $or$ls180.v:8721$2736_Y + assign $0\main_sdblock2mem_converter_source_first[0:0] $or$ls180.v:8775$2802_Y + assign $0\main_sdblock2mem_converter_source_last[0:0] $or$ls180.v:8776$2803_Y case end end - attribute \src "ls180.v:8724.2-8739.5" + attribute \src "ls180.v:8779.2-8806.5" switch \main_sdblock2mem_converter_load_part - attribute \src "ls180.v:8724.6-8724.42" + attribute \src "ls180.v:8779.6-8779.42" case 1'1 - attribute \src "ls180.v:8725.3-8738.10" + attribute \src "ls180.v:8780.3-8805.10" switch \main_sdblock2mem_converter_demux attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\main_sdblock2mem_converter_source_payload_data[31:0] [31:24] \main_sdblock2mem_converter_sink_payload_data + case 3'000 + assign $0\main_sdblock2mem_converter_source_payload_data[63:0] [63:56] \main_sdblock2mem_converter_sink_payload_data attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\main_sdblock2mem_converter_source_payload_data[31:0] [23:16] \main_sdblock2mem_converter_sink_payload_data + case 3'001 + assign $0\main_sdblock2mem_converter_source_payload_data[63:0] [55:48] \main_sdblock2mem_converter_sink_payload_data attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\main_sdblock2mem_converter_source_payload_data[31:0] [15:8] \main_sdblock2mem_converter_sink_payload_data + case 3'010 + assign $0\main_sdblock2mem_converter_source_payload_data[63:0] [47:40] \main_sdblock2mem_converter_sink_payload_data attribute \src "ls180.v:0.0-0.0" - case 2'11 - assign $0\main_sdblock2mem_converter_source_payload_data[31:0] [7:0] \main_sdblock2mem_converter_sink_payload_data + case 3'011 + assign $0\main_sdblock2mem_converter_source_payload_data[63:0] [39:32] \main_sdblock2mem_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdblock2mem_converter_source_payload_data[63:0] [31:24] \main_sdblock2mem_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\main_sdblock2mem_converter_source_payload_data[63:0] [23:16] \main_sdblock2mem_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\main_sdblock2mem_converter_source_payload_data[63:0] [15:8] \main_sdblock2mem_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'111 + assign $0\main_sdblock2mem_converter_source_payload_data[63:0] [7:0] \main_sdblock2mem_converter_sink_payload_data case end case end - attribute \src "ls180.v:8740.2-8742.5" + attribute \src "ls180.v:8807.2-8809.5" switch \main_sdblock2mem_converter_load_part - attribute \src "ls180.v:8740.6-8740.42" + attribute \src "ls180.v:8807.6-8807.42" case 1'1 - assign $0\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] $add$ls180.v:8741$2737_Y + assign $0\main_sdblock2mem_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8808$2804_Y case end - attribute \src "ls180.v:8744.2-8746.5" + attribute \src "ls180.v:8811.2-8813.5" switch \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce - attribute \src "ls180.v:8744.6-8744.76" + attribute \src "ls180.v:8811.6-8811.76" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value case end - attribute \src "ls180.v:8747.2-8750.5" + attribute \src "ls180.v:8814.2-8817.5" switch \main_sdblock2mem_wishbonedmawriter_reset - attribute \src "ls180.v:8747.6-8747.46" + attribute \src "ls180.v:8814.6-8814.46" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] 0 assign $0\builder_sdblock2memdma_state[1:0] 2'00 case end - attribute \src "ls180.v:8752.2-8754.5" + attribute \src "ls180.v:8819.2-8821.5" switch \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce - attribute \src "ls180.v:8752.6-8752.64" + attribute \src "ls180.v:8819.6-8819.64" case 1'1 - assign $0\main_sdmem2block_dma_data[31:0] \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value + assign $0\main_sdmem2block_dma_data[63:0] \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value case end - attribute \src "ls180.v:8756.2-8758.5" + attribute \src "ls180.v:8823.2-8825.5" switch \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce - attribute \src "ls180.v:8756.6-8756.76" + attribute \src "ls180.v:8823.6-8823.76" case 1'1 assign $0\main_sdmem2block_dma_offset[31:0] \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value case end - attribute \src "ls180.v:8759.2-8762.5" + attribute \src "ls180.v:8826.2-8829.5" switch \main_sdmem2block_dma_reset - attribute \src "ls180.v:8759.6-8759.32" + attribute \src "ls180.v:8826.6-8826.32" case 1'1 assign $0\main_sdmem2block_dma_offset[31:0] 0 assign $0\builder_sdmem2blockdma_resetinserter_state[1:0] 2'00 case end - attribute \src "ls180.v:8763.2-8769.5" - switch $and$ls180.v:8763$2738_Y - attribute \src "ls180.v:8763.6-8763.89" + attribute \src "ls180.v:8830.2-8836.5" + switch $and$ls180.v:8830$2805_Y + attribute \src "ls180.v:8830.6-8830.89" case 1'1 - attribute \src "ls180.v:8764.3-8768.6" + attribute \src "ls180.v:8831.3-8835.6" switch \main_sdmem2block_converter_last - attribute \src "ls180.v:8764.7-8764.38" + attribute \src "ls180.v:8831.7-8831.38" case 1'1 - assign $0\main_sdmem2block_converter_mux[1:0] 2'00 - attribute \src "ls180.v:8766.7-8766.11" + assign $0\main_sdmem2block_converter_mux[2:0] 3'000 + attribute \src "ls180.v:8833.7-8833.11" case - assign $0\main_sdmem2block_converter_mux[1:0] $add$ls180.v:8767$2739_Y + assign $0\main_sdmem2block_converter_mux[2:0] $add$ls180.v:8834$2806_Y end case end - attribute \src "ls180.v:8770.2-8772.5" - switch $and$ls180.v:8770$2742_Y - attribute \src "ls180.v:8770.6-8770.120" + attribute \src "ls180.v:8837.2-8839.5" + switch $and$ls180.v:8837$2809_Y + attribute \src "ls180.v:8837.6-8837.120" case 1'1 - assign $0\main_sdmem2block_fifo_produce[4:0] $add$ls180.v:8771$2743_Y + assign $0\main_sdmem2block_fifo_produce[4:0] $add$ls180.v:8838$2810_Y case end - attribute \src "ls180.v:8773.2-8775.5" + attribute \src "ls180.v:8840.2-8842.5" switch \main_sdmem2block_fifo_do_read - attribute \src "ls180.v:8773.6-8773.35" + attribute \src "ls180.v:8840.6-8840.35" case 1'1 - assign $0\main_sdmem2block_fifo_consume[4:0] $add$ls180.v:8774$2744_Y + assign $0\main_sdmem2block_fifo_consume[4:0] $add$ls180.v:8841$2811_Y case end - attribute \src "ls180.v:8776.2-8784.5" - switch $and$ls180.v:8776$2747_Y - attribute \src "ls180.v:8776.6-8776.120" + attribute \src "ls180.v:8843.2-8851.5" + switch $and$ls180.v:8843$2814_Y + attribute \src "ls180.v:8843.6-8843.120" case 1'1 - attribute \src "ls180.v:8777.3-8779.6" - switch $not$ls180.v:8777$2748_Y - attribute \src "ls180.v:8777.7-8777.39" + attribute \src "ls180.v:8844.3-8846.6" + switch $not$ls180.v:8844$2815_Y + attribute \src "ls180.v:8844.7-8844.39" case 1'1 - assign $0\main_sdmem2block_fifo_level[5:0] $add$ls180.v:8778$2749_Y + assign $0\main_sdmem2block_fifo_level[5:0] $add$ls180.v:8845$2816_Y case end - attribute \src "ls180.v:8780.6-8780.10" + attribute \src "ls180.v:8847.6-8847.10" case - attribute \src "ls180.v:8781.3-8783.6" + attribute \src "ls180.v:8848.3-8850.6" switch \main_sdmem2block_fifo_do_read - attribute \src "ls180.v:8781.7-8781.36" + attribute \src "ls180.v:8848.7-8848.36" case 1'1 - assign $0\main_sdmem2block_fifo_level[5:0] $sub$ls180.v:8782$2750_Y + assign $0\main_sdmem2block_fifo_level[5:0] $sub$ls180.v:8849$2817_Y case end end - attribute \src "ls180.v:8786.2-8788.5" + attribute \src "ls180.v:8853.2-8855.5" switch \builder_libresocsim_dat_w_next_value_ce0 - attribute \src "ls180.v:8786.6-8786.46" + attribute \src "ls180.v:8853.6-8853.46" case 1'1 assign $0\builder_libresocsim_dat_w[7:0] \builder_libresocsim_dat_w_next_value0 case end - attribute \src "ls180.v:8789.2-8791.5" + attribute \src "ls180.v:8856.2-8858.5" switch \builder_libresocsim_adr_next_value_ce1 - attribute \src "ls180.v:8789.6-8789.44" + attribute \src "ls180.v:8856.6-8856.44" case 1'1 assign $0\builder_libresocsim_adr[13:0] \builder_libresocsim_adr_next_value1 case end - attribute \src "ls180.v:8792.2-8794.5" + attribute \src "ls180.v:8859.2-8861.5" switch \builder_libresocsim_we_next_value_ce2 - attribute \src "ls180.v:8792.6-8792.43" + attribute \src "ls180.v:8859.6-8859.43" case 1'1 assign $0\builder_libresocsim_we[0:0] \builder_libresocsim_we_next_value2 case end - attribute \src "ls180.v:8795.2-8891.9" + attribute \src "ls180.v:8862.2-8958.9" switch \builder_grant attribute \src "ls180.v:0.0-0.0" case 3'000 - attribute \src "ls180.v:8797.4-8813.7" - switch $not$ls180.v:8797$2751_Y - attribute \src "ls180.v:8797.8-8797.29" + attribute \src "ls180.v:8864.4-8880.7" + switch $not$ls180.v:8864$2818_Y + attribute \src "ls180.v:8864.8-8864.29" case 1'1 - attribute \src "ls180.v:8798.5-8812.8" + attribute \src "ls180.v:8865.5-8879.8" switch \builder_request [1] - attribute \src "ls180.v:8798.9-8798.27" + attribute \src "ls180.v:8865.9-8865.27" case 1'1 assign $0\builder_grant[2:0] 3'001 - attribute \src "ls180.v:8800.9-8800.13" + attribute \src "ls180.v:8867.9-8867.13" case - attribute \src "ls180.v:8801.6-8811.9" + attribute \src "ls180.v:8868.6-8878.9" switch \builder_request [2] - attribute \src "ls180.v:8801.10-8801.28" + attribute \src "ls180.v:8868.10-8868.28" case 1'1 assign $0\builder_grant[2:0] 3'010 - attribute \src "ls180.v:8803.10-8803.14" + attribute \src "ls180.v:8870.10-8870.14" case - attribute \src "ls180.v:8804.7-8810.10" + attribute \src "ls180.v:8871.7-8877.10" switch \builder_request [3] - attribute \src "ls180.v:8804.11-8804.29" + attribute \src "ls180.v:8871.11-8871.29" case 1'1 assign $0\builder_grant[2:0] 3'011 - attribute \src "ls180.v:8806.11-8806.15" + attribute \src "ls180.v:8873.11-8873.15" case - attribute \src "ls180.v:8807.8-8809.11" + attribute \src "ls180.v:8874.8-8876.11" switch \builder_request [4] - attribute \src "ls180.v:8807.12-8807.30" + attribute \src "ls180.v:8874.12-8874.30" case 1'1 assign $0\builder_grant[2:0] 3'100 case @@ -279501,34 +280946,34 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case 3'001 - attribute \src "ls180.v:8816.4-8832.7" - switch $not$ls180.v:8816$2752_Y - attribute \src "ls180.v:8816.8-8816.29" + attribute \src "ls180.v:8883.4-8899.7" + switch $not$ls180.v:8883$2819_Y + attribute \src "ls180.v:8883.8-8883.29" case 1'1 - attribute \src "ls180.v:8817.5-8831.8" + attribute \src "ls180.v:8884.5-8898.8" switch \builder_request [2] - attribute \src "ls180.v:8817.9-8817.27" + attribute \src "ls180.v:8884.9-8884.27" case 1'1 assign $0\builder_grant[2:0] 3'010 - attribute \src "ls180.v:8819.9-8819.13" + attribute \src "ls180.v:8886.9-8886.13" case - attribute \src "ls180.v:8820.6-8830.9" + attribute \src "ls180.v:8887.6-8897.9" switch \builder_request [3] - attribute \src "ls180.v:8820.10-8820.28" + attribute \src "ls180.v:8887.10-8887.28" case 1'1 assign $0\builder_grant[2:0] 3'011 - attribute \src "ls180.v:8822.10-8822.14" + attribute \src "ls180.v:8889.10-8889.14" case - attribute \src "ls180.v:8823.7-8829.10" + attribute \src "ls180.v:8890.7-8896.10" switch \builder_request [4] - attribute \src "ls180.v:8823.11-8823.29" + attribute \src "ls180.v:8890.11-8890.29" case 1'1 assign $0\builder_grant[2:0] 3'100 - attribute \src "ls180.v:8825.11-8825.15" + attribute \src "ls180.v:8892.11-8892.15" case - attribute \src "ls180.v:8826.8-8828.11" + attribute \src "ls180.v:8893.8-8895.11" switch \builder_request [0] - attribute \src "ls180.v:8826.12-8826.30" + attribute \src "ls180.v:8893.12-8893.30" case 1'1 assign $0\builder_grant[2:0] 3'000 case @@ -279540,34 +280985,34 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case 3'010 - attribute \src "ls180.v:8835.4-8851.7" - switch $not$ls180.v:8835$2753_Y - attribute \src "ls180.v:8835.8-8835.29" + attribute \src "ls180.v:8902.4-8918.7" + switch $not$ls180.v:8902$2820_Y + attribute \src "ls180.v:8902.8-8902.29" case 1'1 - attribute \src "ls180.v:8836.5-8850.8" + attribute \src "ls180.v:8903.5-8917.8" switch \builder_request [3] - attribute \src "ls180.v:8836.9-8836.27" + attribute \src "ls180.v:8903.9-8903.27" case 1'1 assign $0\builder_grant[2:0] 3'011 - attribute \src "ls180.v:8838.9-8838.13" + attribute \src "ls180.v:8905.9-8905.13" case - attribute \src "ls180.v:8839.6-8849.9" + attribute \src "ls180.v:8906.6-8916.9" switch \builder_request [4] - attribute \src "ls180.v:8839.10-8839.28" + attribute \src "ls180.v:8906.10-8906.28" case 1'1 assign $0\builder_grant[2:0] 3'100 - attribute \src "ls180.v:8841.10-8841.14" + attribute \src "ls180.v:8908.10-8908.14" case - attribute \src "ls180.v:8842.7-8848.10" + attribute \src "ls180.v:8909.7-8915.10" switch \builder_request [0] - attribute \src "ls180.v:8842.11-8842.29" + attribute \src "ls180.v:8909.11-8909.29" case 1'1 assign $0\builder_grant[2:0] 3'000 - attribute \src "ls180.v:8844.11-8844.15" + attribute \src "ls180.v:8911.11-8911.15" case - attribute \src "ls180.v:8845.8-8847.11" + attribute \src "ls180.v:8912.8-8914.11" switch \builder_request [1] - attribute \src "ls180.v:8845.12-8845.30" + attribute \src "ls180.v:8912.12-8912.30" case 1'1 assign $0\builder_grant[2:0] 3'001 case @@ -279579,34 +281024,34 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case 3'011 - attribute \src "ls180.v:8854.4-8870.7" - switch $not$ls180.v:8854$2754_Y - attribute \src "ls180.v:8854.8-8854.29" + attribute \src "ls180.v:8921.4-8937.7" + switch $not$ls180.v:8921$2821_Y + attribute \src "ls180.v:8921.8-8921.29" case 1'1 - attribute \src "ls180.v:8855.5-8869.8" + attribute \src "ls180.v:8922.5-8936.8" switch \builder_request [4] - attribute \src "ls180.v:8855.9-8855.27" + attribute \src "ls180.v:8922.9-8922.27" case 1'1 assign $0\builder_grant[2:0] 3'100 - attribute \src "ls180.v:8857.9-8857.13" + attribute \src "ls180.v:8924.9-8924.13" case - attribute \src "ls180.v:8858.6-8868.9" + attribute \src "ls180.v:8925.6-8935.9" switch \builder_request [0] - attribute \src "ls180.v:8858.10-8858.28" + attribute \src "ls180.v:8925.10-8925.28" case 1'1 assign $0\builder_grant[2:0] 3'000 - attribute \src "ls180.v:8860.10-8860.14" + attribute \src "ls180.v:8927.10-8927.14" case - attribute \src "ls180.v:8861.7-8867.10" + attribute \src "ls180.v:8928.7-8934.10" switch \builder_request [1] - attribute \src "ls180.v:8861.11-8861.29" + attribute \src "ls180.v:8928.11-8928.29" case 1'1 assign $0\builder_grant[2:0] 3'001 - attribute \src "ls180.v:8863.11-8863.15" + attribute \src "ls180.v:8930.11-8930.15" case - attribute \src "ls180.v:8864.8-8866.11" + attribute \src "ls180.v:8931.8-8933.11" switch \builder_request [2] - attribute \src "ls180.v:8864.12-8864.30" + attribute \src "ls180.v:8931.12-8931.30" case 1'1 assign $0\builder_grant[2:0] 3'010 case @@ -279618,34 +281063,34 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case 3'100 - attribute \src "ls180.v:8873.4-8889.7" - switch $not$ls180.v:8873$2755_Y - attribute \src "ls180.v:8873.8-8873.29" + attribute \src "ls180.v:8940.4-8956.7" + switch $not$ls180.v:8940$2822_Y + attribute \src "ls180.v:8940.8-8940.29" case 1'1 - attribute \src "ls180.v:8874.5-8888.8" + attribute \src "ls180.v:8941.5-8955.8" switch \builder_request [0] - attribute \src "ls180.v:8874.9-8874.27" + attribute \src "ls180.v:8941.9-8941.27" case 1'1 assign $0\builder_grant[2:0] 3'000 - attribute \src "ls180.v:8876.9-8876.13" + attribute \src "ls180.v:8943.9-8943.13" case - attribute \src "ls180.v:8877.6-8887.9" + attribute \src "ls180.v:8944.6-8954.9" switch \builder_request [1] - attribute \src "ls180.v:8877.10-8877.28" + attribute \src "ls180.v:8944.10-8944.28" case 1'1 assign $0\builder_grant[2:0] 3'001 - attribute \src "ls180.v:8879.10-8879.14" + attribute \src "ls180.v:8946.10-8946.14" case - attribute \src "ls180.v:8880.7-8886.10" + attribute \src "ls180.v:8947.7-8953.10" switch \builder_request [2] - attribute \src "ls180.v:8880.11-8880.29" + attribute \src "ls180.v:8947.11-8947.29" case 1'1 assign $0\builder_grant[2:0] 3'010 - attribute \src "ls180.v:8882.11-8882.15" + attribute \src "ls180.v:8949.11-8949.15" case - attribute \src "ls180.v:8883.8-8885.11" + attribute \src "ls180.v:8950.8-8952.11" switch \builder_request [3] - attribute \src "ls180.v:8883.12-8883.30" + attribute \src "ls180.v:8950.12-8950.30" case 1'1 assign $0\builder_grant[2:0] 3'011 case @@ -279657,26 +281102,26 @@ module \ls180 end case end - attribute \src "ls180.v:8893.2-8899.5" + attribute \src "ls180.v:8960.2-8966.5" switch \builder_wait - attribute \src "ls180.v:8893.6-8893.18" + attribute \src "ls180.v:8960.6-8960.18" case 1'1 - attribute \src "ls180.v:8894.3-8896.6" - switch $not$ls180.v:8894$2756_Y - attribute \src "ls180.v:8894.7-8894.22" + attribute \src "ls180.v:8961.3-8963.6" + switch $not$ls180.v:8961$2823_Y + attribute \src "ls180.v:8961.7-8961.22" case 1'1 - assign $0\builder_count[19:0] $sub$ls180.v:8895$2757_Y + assign $0\builder_count[19:0] $sub$ls180.v:8962$2824_Y case end - attribute \src "ls180.v:8897.6-8897.10" + attribute \src "ls180.v:8964.6-8964.10" case assign $0\builder_count[19:0] 20'11110100001001000000 end - attribute \src "ls180.v:8901.2-8931.5" + attribute \src "ls180.v:8968.2-8998.5" switch \builder_csrbank0_sel - attribute \src "ls180.v:8901.6-8901.26" + attribute \src "ls180.v:8968.6-8968.26" case 1'1 - attribute \src "ls180.v:8902.3-8930.10" + attribute \src "ls180.v:8969.3-8997.10" switch \builder_interface0_bank_bus_adr [3:0] attribute \src "ls180.v:0.0-0.0" case 4'0000 @@ -279709,46 +281154,46 @@ module \ls180 end case end - attribute \src "ls180.v:8932.2-8934.5" + attribute \src "ls180.v:8999.2-9001.5" switch \builder_csrbank0_reset0_re - attribute \src "ls180.v:8932.6-8932.32" + attribute \src "ls180.v:8999.6-8999.32" case 1'1 assign $0\main_libresocsim_reset_storage[0:0] \builder_csrbank0_reset0_r case end - attribute \src "ls180.v:8936.2-8938.5" + attribute \src "ls180.v:9003.2-9005.5" switch \builder_csrbank0_scratch3_re - attribute \src "ls180.v:8936.6-8936.34" + attribute \src "ls180.v:9003.6-9003.34" case 1'1 assign $0\main_libresocsim_scratch_storage[31:0] [31:24] \builder_csrbank0_scratch3_r case end - attribute \src "ls180.v:8939.2-8941.5" + attribute \src "ls180.v:9006.2-9008.5" switch \builder_csrbank0_scratch2_re - attribute \src "ls180.v:8939.6-8939.34" + attribute \src "ls180.v:9006.6-9006.34" case 1'1 assign $0\main_libresocsim_scratch_storage[31:0] [23:16] \builder_csrbank0_scratch2_r case end - attribute \src "ls180.v:8942.2-8944.5" + attribute \src "ls180.v:9009.2-9011.5" switch \builder_csrbank0_scratch1_re - attribute \src "ls180.v:8942.6-8942.34" + attribute \src "ls180.v:9009.6-9009.34" case 1'1 assign $0\main_libresocsim_scratch_storage[31:0] [15:8] \builder_csrbank0_scratch1_r case end - attribute \src "ls180.v:8945.2-8947.5" + attribute \src "ls180.v:9012.2-9014.5" switch \builder_csrbank0_scratch0_re - attribute \src "ls180.v:8945.6-8945.34" + attribute \src "ls180.v:9012.6-9012.34" case 1'1 assign $0\main_libresocsim_scratch_storage[31:0] [7:0] \builder_csrbank0_scratch0_r case end - attribute \src "ls180.v:8950.2-8971.5" + attribute \src "ls180.v:9017.2-9038.5" switch \builder_csrbank1_sel - attribute \src "ls180.v:8950.6-8950.26" + attribute \src "ls180.v:9017.6-9017.26" case 1'1 - attribute \src "ls180.v:8951.3-8970.10" + attribute \src "ls180.v:9018.3-9037.10" switch \builder_interface1_bank_bus_adr [2:0] attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -279772,39 +281217,39 @@ module \ls180 end case end - attribute \src "ls180.v:8972.2-8974.5" + attribute \src "ls180.v:9039.2-9041.5" switch \builder_csrbank1_oe1_re - attribute \src "ls180.v:8972.6-8972.29" + attribute \src "ls180.v:9039.6-9039.29" case 1'1 - assign $0\main_gpio_oe_storage[15:0] [15:8] \builder_csrbank1_oe1_r + assign $0\main_gpiotristateasic1_oe_storage[15:0] [15:8] \builder_csrbank1_oe1_r case end - attribute \src "ls180.v:8975.2-8977.5" + attribute \src "ls180.v:9042.2-9044.5" switch \builder_csrbank1_oe0_re - attribute \src "ls180.v:8975.6-8975.29" + attribute \src "ls180.v:9042.6-9042.29" case 1'1 - assign $0\main_gpio_oe_storage[15:0] [7:0] \builder_csrbank1_oe0_r + assign $0\main_gpiotristateasic1_oe_storage[15:0] [7:0] \builder_csrbank1_oe0_r case end - attribute \src "ls180.v:8979.2-8981.5" + attribute \src "ls180.v:9046.2-9048.5" switch \builder_csrbank1_out1_re - attribute \src "ls180.v:8979.6-8979.30" + attribute \src "ls180.v:9046.6-9046.30" case 1'1 - assign $0\main_gpio_out_storage[15:0] [15:8] \builder_csrbank1_out1_r + assign $0\main_gpiotristateasic1_out_storage[15:0] [15:8] \builder_csrbank1_out1_r case end - attribute \src "ls180.v:8982.2-8984.5" + attribute \src "ls180.v:9049.2-9051.5" switch \builder_csrbank1_out0_re - attribute \src "ls180.v:8982.6-8982.30" + attribute \src "ls180.v:9049.6-9049.30" case 1'1 - assign $0\main_gpio_out_storage[15:0] [7:0] \builder_csrbank1_out0_r + assign $0\main_gpiotristateasic1_out_storage[15:0] [7:0] \builder_csrbank1_out0_r case end - attribute \src "ls180.v:8987.2-8996.5" + attribute \src "ls180.v:9054.2-9063.5" switch \builder_csrbank2_sel - attribute \src "ls180.v:8987.6-8987.26" + attribute \src "ls180.v:9054.6-9054.26" case 1'1 - attribute \src "ls180.v:8988.3-8995.10" + attribute \src "ls180.v:9055.3-9062.10" switch \builder_interface2_bank_bus_adr [0] attribute \src "ls180.v:0.0-0.0" case 1'0 @@ -279816,18 +281261,18 @@ module \ls180 end case end - attribute \src "ls180.v:8997.2-8999.5" + attribute \src "ls180.v:9064.2-9066.5" switch \builder_csrbank2_w0_re - attribute \src "ls180.v:8997.6-8997.28" + attribute \src "ls180.v:9064.6-9064.28" case 1'1 assign $0\main_i2c_storage[2:0] \builder_csrbank2_w0_r case end - attribute \src "ls180.v:9002.2-9032.5" + attribute \src "ls180.v:9069.2-9099.5" switch \builder_csrbank3_sel - attribute \src "ls180.v:9002.6-9002.26" + attribute \src "ls180.v:9069.6-9069.26" case 1'1 - attribute \src "ls180.v:9003.3-9031.10" + attribute \src "ls180.v:9070.3-9098.10" switch \builder_interface3_bank_bus_adr [3:0] attribute \src "ls180.v:0.0-0.0" case 4'0000 @@ -279860,74 +281305,74 @@ module \ls180 end case end - attribute \src "ls180.v:9033.2-9035.5" + attribute \src "ls180.v:9100.2-9102.5" switch \builder_csrbank3_enable0_re - attribute \src "ls180.v:9033.6-9033.33" + attribute \src "ls180.v:9100.6-9100.33" case 1'1 assign $0\main_pwm0_enable_storage[0:0] \builder_csrbank3_enable0_r case end - attribute \src "ls180.v:9037.2-9039.5" + attribute \src "ls180.v:9104.2-9106.5" switch \builder_csrbank3_width3_re - attribute \src "ls180.v:9037.6-9037.32" + attribute \src "ls180.v:9104.6-9104.32" case 1'1 assign $0\main_pwm0_width_storage[31:0] [31:24] \builder_csrbank3_width3_r case end - attribute \src "ls180.v:9040.2-9042.5" + attribute \src "ls180.v:9107.2-9109.5" switch \builder_csrbank3_width2_re - attribute \src "ls180.v:9040.6-9040.32" + attribute \src "ls180.v:9107.6-9107.32" case 1'1 assign $0\main_pwm0_width_storage[31:0] [23:16] \builder_csrbank3_width2_r case end - attribute \src "ls180.v:9043.2-9045.5" + attribute \src "ls180.v:9110.2-9112.5" switch \builder_csrbank3_width1_re - attribute \src "ls180.v:9043.6-9043.32" + attribute \src "ls180.v:9110.6-9110.32" case 1'1 assign $0\main_pwm0_width_storage[31:0] [15:8] \builder_csrbank3_width1_r case end - attribute \src "ls180.v:9046.2-9048.5" + attribute \src "ls180.v:9113.2-9115.5" switch \builder_csrbank3_width0_re - attribute \src "ls180.v:9046.6-9046.32" + attribute \src "ls180.v:9113.6-9113.32" case 1'1 assign $0\main_pwm0_width_storage[31:0] [7:0] \builder_csrbank3_width0_r case end - attribute \src "ls180.v:9050.2-9052.5" + attribute \src "ls180.v:9117.2-9119.5" switch \builder_csrbank3_period3_re - attribute \src "ls180.v:9050.6-9050.33" + attribute \src "ls180.v:9117.6-9117.33" case 1'1 assign $0\main_pwm0_period_storage[31:0] [31:24] \builder_csrbank3_period3_r case end - attribute \src "ls180.v:9053.2-9055.5" + attribute \src "ls180.v:9120.2-9122.5" switch \builder_csrbank3_period2_re - attribute \src "ls180.v:9053.6-9053.33" + attribute \src "ls180.v:9120.6-9120.33" case 1'1 assign $0\main_pwm0_period_storage[31:0] [23:16] \builder_csrbank3_period2_r case end - attribute \src "ls180.v:9056.2-9058.5" + attribute \src "ls180.v:9123.2-9125.5" switch \builder_csrbank3_period1_re - attribute \src "ls180.v:9056.6-9056.33" + attribute \src "ls180.v:9123.6-9123.33" case 1'1 assign $0\main_pwm0_period_storage[31:0] [15:8] \builder_csrbank3_period1_r case end - attribute \src "ls180.v:9059.2-9061.5" + attribute \src "ls180.v:9126.2-9128.5" switch \builder_csrbank3_period0_re - attribute \src "ls180.v:9059.6-9059.33" + attribute \src "ls180.v:9126.6-9126.33" case 1'1 assign $0\main_pwm0_period_storage[31:0] [7:0] \builder_csrbank3_period0_r case end - attribute \src "ls180.v:9064.2-9094.5" + attribute \src "ls180.v:9131.2-9161.5" switch \builder_csrbank4_sel - attribute \src "ls180.v:9064.6-9064.26" + attribute \src "ls180.v:9131.6-9131.26" case 1'1 - attribute \src "ls180.v:9065.3-9093.10" + attribute \src "ls180.v:9132.3-9160.10" switch \builder_interface4_bank_bus_adr [3:0] attribute \src "ls180.v:0.0-0.0" case 4'0000 @@ -279960,74 +281405,74 @@ module \ls180 end case end - attribute \src "ls180.v:9095.2-9097.5" + attribute \src "ls180.v:9162.2-9164.5" switch \builder_csrbank4_enable0_re - attribute \src "ls180.v:9095.6-9095.33" + attribute \src "ls180.v:9162.6-9162.33" case 1'1 assign $0\main_pwm1_enable_storage[0:0] \builder_csrbank4_enable0_r case end - attribute \src "ls180.v:9099.2-9101.5" + attribute \src "ls180.v:9166.2-9168.5" switch \builder_csrbank4_width3_re - attribute \src "ls180.v:9099.6-9099.32" + attribute \src "ls180.v:9166.6-9166.32" case 1'1 assign $0\main_pwm1_width_storage[31:0] [31:24] \builder_csrbank4_width3_r case end - attribute \src "ls180.v:9102.2-9104.5" + attribute \src "ls180.v:9169.2-9171.5" switch \builder_csrbank4_width2_re - attribute \src "ls180.v:9102.6-9102.32" + attribute \src "ls180.v:9169.6-9169.32" case 1'1 assign $0\main_pwm1_width_storage[31:0] [23:16] \builder_csrbank4_width2_r case end - attribute \src "ls180.v:9105.2-9107.5" + attribute \src "ls180.v:9172.2-9174.5" switch \builder_csrbank4_width1_re - attribute \src "ls180.v:9105.6-9105.32" + attribute \src "ls180.v:9172.6-9172.32" case 1'1 assign $0\main_pwm1_width_storage[31:0] [15:8] \builder_csrbank4_width1_r case end - attribute \src "ls180.v:9108.2-9110.5" + attribute \src "ls180.v:9175.2-9177.5" switch \builder_csrbank4_width0_re - attribute \src "ls180.v:9108.6-9108.32" + attribute \src "ls180.v:9175.6-9175.32" case 1'1 assign $0\main_pwm1_width_storage[31:0] [7:0] \builder_csrbank4_width0_r case end - attribute \src "ls180.v:9112.2-9114.5" + attribute \src "ls180.v:9179.2-9181.5" switch \builder_csrbank4_period3_re - attribute \src "ls180.v:9112.6-9112.33" + attribute \src "ls180.v:9179.6-9179.33" case 1'1 assign $0\main_pwm1_period_storage[31:0] [31:24] \builder_csrbank4_period3_r case end - attribute \src "ls180.v:9115.2-9117.5" + attribute \src "ls180.v:9182.2-9184.5" switch \builder_csrbank4_period2_re - attribute \src "ls180.v:9115.6-9115.33" + attribute \src "ls180.v:9182.6-9182.33" case 1'1 assign $0\main_pwm1_period_storage[31:0] [23:16] \builder_csrbank4_period2_r case end - attribute \src "ls180.v:9118.2-9120.5" + attribute \src "ls180.v:9185.2-9187.5" switch \builder_csrbank4_period1_re - attribute \src "ls180.v:9118.6-9118.33" + attribute \src "ls180.v:9185.6-9185.33" case 1'1 assign $0\main_pwm1_period_storage[31:0] [15:8] \builder_csrbank4_period1_r case end - attribute \src "ls180.v:9121.2-9123.5" + attribute \src "ls180.v:9188.2-9190.5" switch \builder_csrbank4_period0_re - attribute \src "ls180.v:9121.6-9121.33" + attribute \src "ls180.v:9188.6-9188.33" case 1'1 assign $0\main_pwm1_period_storage[31:0] [7:0] \builder_csrbank4_period0_r case end - attribute \src "ls180.v:9126.2-9174.5" + attribute \src "ls180.v:9193.2-9241.5" switch \builder_csrbank5_sel - attribute \src "ls180.v:9126.6-9126.26" + attribute \src "ls180.v:9193.6-9193.26" case 1'1 - attribute \src "ls180.v:9127.3-9173.10" + attribute \src "ls180.v:9194.3-9240.10" switch \builder_interface5_bank_bus_adr [3:0] attribute \src "ls180.v:0.0-0.0" case 4'0000 @@ -280078,109 +281523,109 @@ module \ls180 end case end - attribute \src "ls180.v:9175.2-9177.5" + attribute \src "ls180.v:9242.2-9244.5" switch \builder_csrbank5_dma_base7_re - attribute \src "ls180.v:9175.6-9175.35" + attribute \src "ls180.v:9242.6-9242.35" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [63:56] \builder_csrbank5_dma_base7_r case end - attribute \src "ls180.v:9178.2-9180.5" + attribute \src "ls180.v:9245.2-9247.5" switch \builder_csrbank5_dma_base6_re - attribute \src "ls180.v:9178.6-9178.35" + attribute \src "ls180.v:9245.6-9245.35" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [55:48] \builder_csrbank5_dma_base6_r case end - attribute \src "ls180.v:9181.2-9183.5" + attribute \src "ls180.v:9248.2-9250.5" switch \builder_csrbank5_dma_base5_re - attribute \src "ls180.v:9181.6-9181.35" + attribute \src "ls180.v:9248.6-9248.35" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [47:40] \builder_csrbank5_dma_base5_r case end - attribute \src "ls180.v:9184.2-9186.5" + attribute \src "ls180.v:9251.2-9253.5" switch \builder_csrbank5_dma_base4_re - attribute \src "ls180.v:9184.6-9184.35" + attribute \src "ls180.v:9251.6-9251.35" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [39:32] \builder_csrbank5_dma_base4_r case end - attribute \src "ls180.v:9187.2-9189.5" + attribute \src "ls180.v:9254.2-9256.5" switch \builder_csrbank5_dma_base3_re - attribute \src "ls180.v:9187.6-9187.35" + attribute \src "ls180.v:9254.6-9254.35" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [31:24] \builder_csrbank5_dma_base3_r case end - attribute \src "ls180.v:9190.2-9192.5" + attribute \src "ls180.v:9257.2-9259.5" switch \builder_csrbank5_dma_base2_re - attribute \src "ls180.v:9190.6-9190.35" + attribute \src "ls180.v:9257.6-9257.35" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [23:16] \builder_csrbank5_dma_base2_r case end - attribute \src "ls180.v:9193.2-9195.5" + attribute \src "ls180.v:9260.2-9262.5" switch \builder_csrbank5_dma_base1_re - attribute \src "ls180.v:9193.6-9193.35" + attribute \src "ls180.v:9260.6-9260.35" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [15:8] \builder_csrbank5_dma_base1_r case end - attribute \src "ls180.v:9196.2-9198.5" + attribute \src "ls180.v:9263.2-9265.5" switch \builder_csrbank5_dma_base0_re - attribute \src "ls180.v:9196.6-9196.35" + attribute \src "ls180.v:9263.6-9263.35" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [7:0] \builder_csrbank5_dma_base0_r case end - attribute \src "ls180.v:9200.2-9202.5" + attribute \src "ls180.v:9267.2-9269.5" switch \builder_csrbank5_dma_length3_re - attribute \src "ls180.v:9200.6-9200.37" + attribute \src "ls180.v:9267.6-9267.37" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [31:24] \builder_csrbank5_dma_length3_r case end - attribute \src "ls180.v:9203.2-9205.5" + attribute \src "ls180.v:9270.2-9272.5" switch \builder_csrbank5_dma_length2_re - attribute \src "ls180.v:9203.6-9203.37" + attribute \src "ls180.v:9270.6-9270.37" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [23:16] \builder_csrbank5_dma_length2_r case end - attribute \src "ls180.v:9206.2-9208.5" + attribute \src "ls180.v:9273.2-9275.5" switch \builder_csrbank5_dma_length1_re - attribute \src "ls180.v:9206.6-9206.37" + attribute \src "ls180.v:9273.6-9273.37" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [15:8] \builder_csrbank5_dma_length1_r case end - attribute \src "ls180.v:9209.2-9211.5" + attribute \src "ls180.v:9276.2-9278.5" switch \builder_csrbank5_dma_length0_re - attribute \src "ls180.v:9209.6-9209.37" + attribute \src "ls180.v:9276.6-9276.37" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [7:0] \builder_csrbank5_dma_length0_r case end - attribute \src "ls180.v:9213.2-9215.5" + attribute \src "ls180.v:9280.2-9282.5" switch \builder_csrbank5_dma_enable0_re - attribute \src "ls180.v:9213.6-9213.37" + attribute \src "ls180.v:9280.6-9280.37" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] \builder_csrbank5_dma_enable0_r case end - attribute \src "ls180.v:9217.2-9219.5" + attribute \src "ls180.v:9284.2-9286.5" switch \builder_csrbank5_dma_loop0_re - attribute \src "ls180.v:9217.6-9217.35" + attribute \src "ls180.v:9284.6-9284.35" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] \builder_csrbank5_dma_loop0_r case end - attribute \src "ls180.v:9222.2-9324.5" + attribute \src "ls180.v:9289.2-9391.5" switch \builder_csrbank6_sel - attribute \src "ls180.v:9222.6-9222.26" + attribute \src "ls180.v:9289.6-9289.26" case 1'1 - attribute \src "ls180.v:9223.3-9323.10" + attribute \src "ls180.v:9290.3-9390.10" switch \builder_interface6_bank_bus_adr [5:0] attribute \src "ls180.v:0.0-0.0" case 6'000000 @@ -280285,109 +281730,109 @@ module \ls180 end case end - attribute \src "ls180.v:9325.2-9327.5" + attribute \src "ls180.v:9392.2-9394.5" switch \builder_csrbank6_cmd_argument3_re - attribute \src "ls180.v:9325.6-9325.39" + attribute \src "ls180.v:9392.6-9392.39" case 1'1 assign $0\main_sdcore_cmd_argument_storage[31:0] [31:24] \builder_csrbank6_cmd_argument3_r case end - attribute \src "ls180.v:9328.2-9330.5" + attribute \src "ls180.v:9395.2-9397.5" switch \builder_csrbank6_cmd_argument2_re - attribute \src "ls180.v:9328.6-9328.39" + attribute \src "ls180.v:9395.6-9395.39" case 1'1 assign $0\main_sdcore_cmd_argument_storage[31:0] [23:16] \builder_csrbank6_cmd_argument2_r case end - attribute \src "ls180.v:9331.2-9333.5" + attribute \src "ls180.v:9398.2-9400.5" switch \builder_csrbank6_cmd_argument1_re - attribute \src "ls180.v:9331.6-9331.39" + attribute \src "ls180.v:9398.6-9398.39" case 1'1 assign $0\main_sdcore_cmd_argument_storage[31:0] [15:8] \builder_csrbank6_cmd_argument1_r case end - attribute \src "ls180.v:9334.2-9336.5" + attribute \src "ls180.v:9401.2-9403.5" switch \builder_csrbank6_cmd_argument0_re - attribute \src "ls180.v:9334.6-9334.39" + attribute \src "ls180.v:9401.6-9401.39" case 1'1 assign $0\main_sdcore_cmd_argument_storage[31:0] [7:0] \builder_csrbank6_cmd_argument0_r case end - attribute \src "ls180.v:9338.2-9340.5" + attribute \src "ls180.v:9405.2-9407.5" switch \builder_csrbank6_cmd_command3_re - attribute \src "ls180.v:9338.6-9338.38" + attribute \src "ls180.v:9405.6-9405.38" case 1'1 assign $0\main_sdcore_cmd_command_storage[31:0] [31:24] \builder_csrbank6_cmd_command3_r case end - attribute \src "ls180.v:9341.2-9343.5" + attribute \src "ls180.v:9408.2-9410.5" switch \builder_csrbank6_cmd_command2_re - attribute \src "ls180.v:9341.6-9341.38" + attribute \src "ls180.v:9408.6-9408.38" case 1'1 assign $0\main_sdcore_cmd_command_storage[31:0] [23:16] \builder_csrbank6_cmd_command2_r case end - attribute \src "ls180.v:9344.2-9346.5" + attribute \src "ls180.v:9411.2-9413.5" switch \builder_csrbank6_cmd_command1_re - attribute \src "ls180.v:9344.6-9344.38" + attribute \src "ls180.v:9411.6-9411.38" case 1'1 assign $0\main_sdcore_cmd_command_storage[31:0] [15:8] \builder_csrbank6_cmd_command1_r case end - attribute \src "ls180.v:9347.2-9349.5" + attribute \src "ls180.v:9414.2-9416.5" switch \builder_csrbank6_cmd_command0_re - attribute \src "ls180.v:9347.6-9347.38" + attribute \src "ls180.v:9414.6-9414.38" case 1'1 assign $0\main_sdcore_cmd_command_storage[31:0] [7:0] \builder_csrbank6_cmd_command0_r case end - attribute \src "ls180.v:9351.2-9353.5" + attribute \src "ls180.v:9418.2-9420.5" switch \builder_csrbank6_block_length1_re - attribute \src "ls180.v:9351.6-9351.39" + attribute \src "ls180.v:9418.6-9418.39" case 1'1 assign $0\main_sdcore_block_length_storage[9:0] [9:8] \builder_csrbank6_block_length1_r case end - attribute \src "ls180.v:9354.2-9356.5" + attribute \src "ls180.v:9421.2-9423.5" switch \builder_csrbank6_block_length0_re - attribute \src "ls180.v:9354.6-9354.39" + attribute \src "ls180.v:9421.6-9421.39" case 1'1 assign $0\main_sdcore_block_length_storage[9:0] [7:0] \builder_csrbank6_block_length0_r case end - attribute \src "ls180.v:9358.2-9360.5" + attribute \src "ls180.v:9425.2-9427.5" switch \builder_csrbank6_block_count3_re - attribute \src "ls180.v:9358.6-9358.38" + attribute \src "ls180.v:9425.6-9425.38" case 1'1 assign $0\main_sdcore_block_count_storage[31:0] [31:24] \builder_csrbank6_block_count3_r case end - attribute \src "ls180.v:9361.2-9363.5" + attribute \src "ls180.v:9428.2-9430.5" switch \builder_csrbank6_block_count2_re - attribute \src "ls180.v:9361.6-9361.38" + attribute \src "ls180.v:9428.6-9428.38" case 1'1 assign $0\main_sdcore_block_count_storage[31:0] [23:16] \builder_csrbank6_block_count2_r case end - attribute \src "ls180.v:9364.2-9366.5" + attribute \src "ls180.v:9431.2-9433.5" switch \builder_csrbank6_block_count1_re - attribute \src "ls180.v:9364.6-9364.38" + attribute \src "ls180.v:9431.6-9431.38" case 1'1 assign $0\main_sdcore_block_count_storage[31:0] [15:8] \builder_csrbank6_block_count1_r case end - attribute \src "ls180.v:9367.2-9369.5" + attribute \src "ls180.v:9434.2-9436.5" switch \builder_csrbank6_block_count0_re - attribute \src "ls180.v:9367.6-9367.38" + attribute \src "ls180.v:9434.6-9434.38" case 1'1 assign $0\main_sdcore_block_count_storage[31:0] [7:0] \builder_csrbank6_block_count0_r case end - attribute \src "ls180.v:9372.2-9432.5" + attribute \src "ls180.v:9439.2-9499.5" switch \builder_csrbank7_sel - attribute \src "ls180.v:9372.6-9372.26" + attribute \src "ls180.v:9439.6-9439.26" case 1'1 - attribute \src "ls180.v:9373.3-9431.10" + attribute \src "ls180.v:9440.3-9498.10" switch \builder_interface7_bank_bus_adr [4:0] attribute \src "ls180.v:0.0-0.0" case 5'00000 @@ -280450,109 +281895,109 @@ module \ls180 end case end - attribute \src "ls180.v:9433.2-9435.5" + attribute \src "ls180.v:9500.2-9502.5" switch \builder_csrbank7_dma_base7_re - attribute \src "ls180.v:9433.6-9433.35" + attribute \src "ls180.v:9500.6-9500.35" case 1'1 assign $0\main_sdmem2block_dma_base_storage[63:0] [63:56] \builder_csrbank7_dma_base7_r case end - attribute \src "ls180.v:9436.2-9438.5" + attribute \src "ls180.v:9503.2-9505.5" switch \builder_csrbank7_dma_base6_re - attribute \src "ls180.v:9436.6-9436.35" + attribute \src "ls180.v:9503.6-9503.35" case 1'1 assign $0\main_sdmem2block_dma_base_storage[63:0] [55:48] \builder_csrbank7_dma_base6_r case end - attribute \src "ls180.v:9439.2-9441.5" + attribute \src "ls180.v:9506.2-9508.5" switch \builder_csrbank7_dma_base5_re - attribute \src "ls180.v:9439.6-9439.35" + attribute \src "ls180.v:9506.6-9506.35" case 1'1 assign $0\main_sdmem2block_dma_base_storage[63:0] [47:40] \builder_csrbank7_dma_base5_r case end - attribute \src "ls180.v:9442.2-9444.5" + attribute \src "ls180.v:9509.2-9511.5" switch \builder_csrbank7_dma_base4_re - attribute \src "ls180.v:9442.6-9442.35" + attribute \src "ls180.v:9509.6-9509.35" case 1'1 assign $0\main_sdmem2block_dma_base_storage[63:0] [39:32] \builder_csrbank7_dma_base4_r case end - attribute \src "ls180.v:9445.2-9447.5" + attribute \src "ls180.v:9512.2-9514.5" switch \builder_csrbank7_dma_base3_re - attribute \src "ls180.v:9445.6-9445.35" + attribute \src "ls180.v:9512.6-9512.35" case 1'1 assign $0\main_sdmem2block_dma_base_storage[63:0] [31:24] \builder_csrbank7_dma_base3_r case end - attribute \src "ls180.v:9448.2-9450.5" + attribute \src "ls180.v:9515.2-9517.5" switch \builder_csrbank7_dma_base2_re - attribute \src "ls180.v:9448.6-9448.35" + attribute \src "ls180.v:9515.6-9515.35" case 1'1 assign $0\main_sdmem2block_dma_base_storage[63:0] [23:16] \builder_csrbank7_dma_base2_r case end - attribute \src "ls180.v:9451.2-9453.5" + attribute \src "ls180.v:9518.2-9520.5" switch \builder_csrbank7_dma_base1_re - attribute \src "ls180.v:9451.6-9451.35" + attribute \src "ls180.v:9518.6-9518.35" case 1'1 assign $0\main_sdmem2block_dma_base_storage[63:0] [15:8] \builder_csrbank7_dma_base1_r case end - attribute \src "ls180.v:9454.2-9456.5" + attribute \src "ls180.v:9521.2-9523.5" switch \builder_csrbank7_dma_base0_re - attribute \src "ls180.v:9454.6-9454.35" + attribute \src "ls180.v:9521.6-9521.35" case 1'1 assign $0\main_sdmem2block_dma_base_storage[63:0] [7:0] \builder_csrbank7_dma_base0_r case end - attribute \src "ls180.v:9458.2-9460.5" + attribute \src "ls180.v:9525.2-9527.5" switch \builder_csrbank7_dma_length3_re - attribute \src "ls180.v:9458.6-9458.37" + attribute \src "ls180.v:9525.6-9525.37" case 1'1 assign $0\main_sdmem2block_dma_length_storage[31:0] [31:24] \builder_csrbank7_dma_length3_r case end - attribute \src "ls180.v:9461.2-9463.5" + attribute \src "ls180.v:9528.2-9530.5" switch \builder_csrbank7_dma_length2_re - attribute \src "ls180.v:9461.6-9461.37" + attribute \src "ls180.v:9528.6-9528.37" case 1'1 assign $0\main_sdmem2block_dma_length_storage[31:0] [23:16] \builder_csrbank7_dma_length2_r case end - attribute \src "ls180.v:9464.2-9466.5" + attribute \src "ls180.v:9531.2-9533.5" switch \builder_csrbank7_dma_length1_re - attribute \src "ls180.v:9464.6-9464.37" + attribute \src "ls180.v:9531.6-9531.37" case 1'1 assign $0\main_sdmem2block_dma_length_storage[31:0] [15:8] \builder_csrbank7_dma_length1_r case end - attribute \src "ls180.v:9467.2-9469.5" + attribute \src "ls180.v:9534.2-9536.5" switch \builder_csrbank7_dma_length0_re - attribute \src "ls180.v:9467.6-9467.37" + attribute \src "ls180.v:9534.6-9534.37" case 1'1 assign $0\main_sdmem2block_dma_length_storage[31:0] [7:0] \builder_csrbank7_dma_length0_r case end - attribute \src "ls180.v:9471.2-9473.5" + attribute \src "ls180.v:9538.2-9540.5" switch \builder_csrbank7_dma_enable0_re - attribute \src "ls180.v:9471.6-9471.37" + attribute \src "ls180.v:9538.6-9538.37" case 1'1 assign $0\main_sdmem2block_dma_enable_storage[0:0] \builder_csrbank7_dma_enable0_r case end - attribute \src "ls180.v:9475.2-9477.5" + attribute \src "ls180.v:9542.2-9544.5" switch \builder_csrbank7_dma_loop0_re - attribute \src "ls180.v:9475.6-9475.35" + attribute \src "ls180.v:9542.6-9542.35" case 1'1 assign $0\main_sdmem2block_dma_loop_storage[0:0] \builder_csrbank7_dma_loop0_r case end - attribute \src "ls180.v:9480.2-9495.5" + attribute \src "ls180.v:9547.2-9562.5" switch \builder_csrbank8_sel - attribute \src "ls180.v:9480.6-9480.26" + attribute \src "ls180.v:9547.6-9547.26" case 1'1 - attribute \src "ls180.v:9481.3-9494.10" + attribute \src "ls180.v:9548.3-9561.10" switch \builder_interface8_bank_bus_adr [1:0] attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -280570,25 +282015,25 @@ module \ls180 end case end - attribute \src "ls180.v:9496.2-9498.5" + attribute \src "ls180.v:9563.2-9565.5" switch \builder_csrbank8_clocker_divider1_re - attribute \src "ls180.v:9496.6-9496.42" + attribute \src "ls180.v:9563.6-9563.42" case 1'1 assign $0\main_sdphy_clocker_storage[8:0] [8] \builder_csrbank8_clocker_divider1_r case end - attribute \src "ls180.v:9499.2-9501.5" + attribute \src "ls180.v:9566.2-9568.5" switch \builder_csrbank8_clocker_divider0_re - attribute \src "ls180.v:9499.6-9499.42" + attribute \src "ls180.v:9566.6-9566.42" case 1'1 assign $0\main_sdphy_clocker_storage[8:0] [7:0] \builder_csrbank8_clocker_divider0_r case end - attribute \src "ls180.v:9504.2-9537.5" + attribute \src "ls180.v:9571.2-9604.5" switch \builder_csrbank9_sel - attribute \src "ls180.v:9504.6-9504.26" + attribute \src "ls180.v:9571.6-9571.26" case 1'1 - attribute \src "ls180.v:9505.3-9536.10" + attribute \src "ls180.v:9572.3-9603.10" switch \builder_interface9_bank_bus_adr [3:0] attribute \src "ls180.v:0.0-0.0" case 4'0000 @@ -280624,60 +282069,60 @@ module \ls180 end case end - attribute \src "ls180.v:9538.2-9540.5" + attribute \src "ls180.v:9605.2-9607.5" switch \builder_csrbank9_dfii_control0_re - attribute \src "ls180.v:9538.6-9538.39" + attribute \src "ls180.v:9605.6-9605.39" case 1'1 assign $0\main_sdram_storage[3:0] \builder_csrbank9_dfii_control0_r case end - attribute \src "ls180.v:9542.2-9544.5" + attribute \src "ls180.v:9609.2-9611.5" switch \builder_csrbank9_dfii_pi0_command0_re - attribute \src "ls180.v:9542.6-9542.43" + attribute \src "ls180.v:9609.6-9609.43" case 1'1 assign $0\main_sdram_command_storage[5:0] \builder_csrbank9_dfii_pi0_command0_r case end - attribute \src "ls180.v:9546.2-9548.5" + attribute \src "ls180.v:9613.2-9615.5" switch \builder_csrbank9_dfii_pi0_address1_re - attribute \src "ls180.v:9546.6-9546.43" + attribute \src "ls180.v:9613.6-9613.43" case 1'1 assign $0\main_sdram_address_storage[12:0] [12:8] \builder_csrbank9_dfii_pi0_address1_r case end - attribute \src "ls180.v:9549.2-9551.5" + attribute \src "ls180.v:9616.2-9618.5" switch \builder_csrbank9_dfii_pi0_address0_re - attribute \src "ls180.v:9549.6-9549.43" + attribute \src "ls180.v:9616.6-9616.43" case 1'1 assign $0\main_sdram_address_storage[12:0] [7:0] \builder_csrbank9_dfii_pi0_address0_r case end - attribute \src "ls180.v:9553.2-9555.5" + attribute \src "ls180.v:9620.2-9622.5" switch \builder_csrbank9_dfii_pi0_baddress0_re - attribute \src "ls180.v:9553.6-9553.44" + attribute \src "ls180.v:9620.6-9620.44" case 1'1 assign $0\main_sdram_baddress_storage[1:0] \builder_csrbank9_dfii_pi0_baddress0_r case end - attribute \src "ls180.v:9557.2-9559.5" + attribute \src "ls180.v:9624.2-9626.5" switch \builder_csrbank9_dfii_pi0_wrdata1_re - attribute \src "ls180.v:9557.6-9557.42" + attribute \src "ls180.v:9624.6-9624.42" case 1'1 assign $0\main_sdram_wrdata_storage[15:0] [15:8] \builder_csrbank9_dfii_pi0_wrdata1_r case end - attribute \src "ls180.v:9560.2-9562.5" + attribute \src "ls180.v:9627.2-9629.5" switch \builder_csrbank9_dfii_pi0_wrdata0_re - attribute \src "ls180.v:9560.6-9560.42" + attribute \src "ls180.v:9627.6-9627.42" case 1'1 assign $0\main_sdram_wrdata_storage[15:0] [7:0] \builder_csrbank9_dfii_pi0_wrdata0_r case end - attribute \src "ls180.v:9565.2-9589.5" + attribute \src "ls180.v:9632.2-9656.5" switch \builder_csrbank10_sel - attribute \src "ls180.v:9565.6-9565.27" + attribute \src "ls180.v:9632.6-9632.27" case 1'1 - attribute \src "ls180.v:9566.3-9588.10" + attribute \src "ls180.v:9633.3-9655.10" switch \builder_interface10_bank_bus_adr [2:0] attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -280704,46 +282149,46 @@ module \ls180 end case end - attribute \src "ls180.v:9590.2-9592.5" + attribute \src "ls180.v:9657.2-9659.5" switch \builder_csrbank10_control1_re - attribute \src "ls180.v:9590.6-9590.35" + attribute \src "ls180.v:9657.6-9657.35" case 1'1 assign $0\main_spimaster11_storage[15:0] [15:8] \builder_csrbank10_control1_r case end - attribute \src "ls180.v:9593.2-9595.5" + attribute \src "ls180.v:9660.2-9662.5" switch \builder_csrbank10_control0_re - attribute \src "ls180.v:9593.6-9593.35" + attribute \src "ls180.v:9660.6-9660.35" case 1'1 assign $0\main_spimaster11_storage[15:0] [7:0] \builder_csrbank10_control0_r case end - attribute \src "ls180.v:9597.2-9599.5" + attribute \src "ls180.v:9664.2-9666.5" switch \builder_csrbank10_mosi0_re - attribute \src "ls180.v:9597.6-9597.32" + attribute \src "ls180.v:9664.6-9664.32" case 1'1 assign $0\main_spimaster16_storage[7:0] \builder_csrbank10_mosi0_r case end - attribute \src "ls180.v:9601.2-9603.5" + attribute \src "ls180.v:9668.2-9670.5" switch \builder_csrbank10_cs0_re - attribute \src "ls180.v:9601.6-9601.30" + attribute \src "ls180.v:9668.6-9668.30" case 1'1 assign $0\main_spimaster21_storage[0:0] \builder_csrbank10_cs0_r case end - attribute \src "ls180.v:9605.2-9607.5" + attribute \src "ls180.v:9672.2-9674.5" switch \builder_csrbank10_loopback0_re - attribute \src "ls180.v:9605.6-9605.36" + attribute \src "ls180.v:9672.6-9672.36" case 1'1 assign $0\main_spimaster23_storage[0:0] \builder_csrbank10_loopback0_r case end - attribute \src "ls180.v:9610.2-9640.5" + attribute \src "ls180.v:9677.2-9707.5" switch \builder_csrbank11_sel - attribute \src "ls180.v:9610.6-9610.27" + attribute \src "ls180.v:9677.6-9677.27" case 1'1 - attribute \src "ls180.v:9611.3-9639.10" + attribute \src "ls180.v:9678.3-9706.10" switch \builder_interface11_bank_bus_adr [3:0] attribute \src "ls180.v:0.0-0.0" case 4'0000 @@ -280776,60 +282221,60 @@ module \ls180 end case end - attribute \src "ls180.v:9641.2-9643.5" + attribute \src "ls180.v:9708.2-9710.5" switch \builder_csrbank11_control1_re - attribute \src "ls180.v:9641.6-9641.35" + attribute \src "ls180.v:9708.6-9708.35" case 1'1 assign $0\main_spisdcard_control_storage[15:0] [15:8] \builder_csrbank11_control1_r case end - attribute \src "ls180.v:9644.2-9646.5" + attribute \src "ls180.v:9711.2-9713.5" switch \builder_csrbank11_control0_re - attribute \src "ls180.v:9644.6-9644.35" + attribute \src "ls180.v:9711.6-9711.35" case 1'1 assign $0\main_spisdcard_control_storage[15:0] [7:0] \builder_csrbank11_control0_r case end - attribute \src "ls180.v:9648.2-9650.5" + attribute \src "ls180.v:9715.2-9717.5" switch \builder_csrbank11_mosi0_re - attribute \src "ls180.v:9648.6-9648.32" + attribute \src "ls180.v:9715.6-9715.32" case 1'1 assign $0\main_spisdcard_mosi_storage[7:0] \builder_csrbank11_mosi0_r case end - attribute \src "ls180.v:9652.2-9654.5" + attribute \src "ls180.v:9719.2-9721.5" switch \builder_csrbank11_cs0_re - attribute \src "ls180.v:9652.6-9652.30" + attribute \src "ls180.v:9719.6-9719.30" case 1'1 assign $0\main_spisdcard_cs_storage[0:0] \builder_csrbank11_cs0_r case end - attribute \src "ls180.v:9656.2-9658.5" + attribute \src "ls180.v:9723.2-9725.5" switch \builder_csrbank11_loopback0_re - attribute \src "ls180.v:9656.6-9656.36" + attribute \src "ls180.v:9723.6-9723.36" case 1'1 assign $0\main_spisdcard_loopback_storage[0:0] \builder_csrbank11_loopback0_r case end - attribute \src "ls180.v:9660.2-9662.5" + attribute \src "ls180.v:9727.2-9729.5" switch \builder_csrbank11_clk_divider1_re - attribute \src "ls180.v:9660.6-9660.39" + attribute \src "ls180.v:9727.6-9727.39" case 1'1 assign $0\main_spimaster1_storage[15:0] [15:8] \builder_csrbank11_clk_divider1_r case end - attribute \src "ls180.v:9663.2-9665.5" + attribute \src "ls180.v:9730.2-9732.5" switch \builder_csrbank11_clk_divider0_re - attribute \src "ls180.v:9663.6-9663.39" + attribute \src "ls180.v:9730.6-9730.39" case 1'1 assign $0\main_spimaster1_storage[15:0] [7:0] \builder_csrbank11_clk_divider0_r case end - attribute \src "ls180.v:9668.2-9722.5" + attribute \src "ls180.v:9735.2-9789.5" switch \builder_csrbank12_sel - attribute \src "ls180.v:9668.6-9668.27" + attribute \src "ls180.v:9735.6-9735.27" case 1'1 - attribute \src "ls180.v:9669.3-9721.10" + attribute \src "ls180.v:9736.3-9788.10" switch \builder_interface12_bank_bus_adr [4:0] attribute \src "ls180.v:0.0-0.0" case 5'00000 @@ -280886,88 +282331,88 @@ module \ls180 end case end - attribute \src "ls180.v:9723.2-9725.5" + attribute \src "ls180.v:9790.2-9792.5" switch \builder_csrbank12_load3_re - attribute \src "ls180.v:9723.6-9723.32" + attribute \src "ls180.v:9790.6-9790.32" case 1'1 assign $0\main_libresocsim_load_storage[31:0] [31:24] \builder_csrbank12_load3_r case end - attribute \src "ls180.v:9726.2-9728.5" + attribute \src "ls180.v:9793.2-9795.5" switch \builder_csrbank12_load2_re - attribute \src "ls180.v:9726.6-9726.32" + attribute \src "ls180.v:9793.6-9793.32" case 1'1 assign $0\main_libresocsim_load_storage[31:0] [23:16] \builder_csrbank12_load2_r case end - attribute \src "ls180.v:9729.2-9731.5" + attribute \src "ls180.v:9796.2-9798.5" switch \builder_csrbank12_load1_re - attribute \src "ls180.v:9729.6-9729.32" + attribute \src "ls180.v:9796.6-9796.32" case 1'1 assign $0\main_libresocsim_load_storage[31:0] [15:8] \builder_csrbank12_load1_r case end - attribute \src "ls180.v:9732.2-9734.5" + attribute \src "ls180.v:9799.2-9801.5" switch \builder_csrbank12_load0_re - attribute \src "ls180.v:9732.6-9732.32" + attribute \src "ls180.v:9799.6-9799.32" case 1'1 assign $0\main_libresocsim_load_storage[31:0] [7:0] \builder_csrbank12_load0_r case end - attribute \src "ls180.v:9736.2-9738.5" + attribute \src "ls180.v:9803.2-9805.5" switch \builder_csrbank12_reload3_re - attribute \src "ls180.v:9736.6-9736.34" + attribute \src "ls180.v:9803.6-9803.34" case 1'1 assign $0\main_libresocsim_reload_storage[31:0] [31:24] \builder_csrbank12_reload3_r case end - attribute \src "ls180.v:9739.2-9741.5" + attribute \src "ls180.v:9806.2-9808.5" switch \builder_csrbank12_reload2_re - attribute \src "ls180.v:9739.6-9739.34" + attribute \src "ls180.v:9806.6-9806.34" case 1'1 assign $0\main_libresocsim_reload_storage[31:0] [23:16] \builder_csrbank12_reload2_r case end - attribute \src "ls180.v:9742.2-9744.5" + attribute \src "ls180.v:9809.2-9811.5" switch \builder_csrbank12_reload1_re - attribute \src "ls180.v:9742.6-9742.34" + attribute \src "ls180.v:9809.6-9809.34" case 1'1 assign $0\main_libresocsim_reload_storage[31:0] [15:8] \builder_csrbank12_reload1_r case end - attribute \src "ls180.v:9745.2-9747.5" + attribute \src "ls180.v:9812.2-9814.5" switch \builder_csrbank12_reload0_re - attribute \src "ls180.v:9745.6-9745.34" + attribute \src "ls180.v:9812.6-9812.34" case 1'1 assign $0\main_libresocsim_reload_storage[31:0] [7:0] \builder_csrbank12_reload0_r case end - attribute \src "ls180.v:9749.2-9751.5" + attribute \src "ls180.v:9816.2-9818.5" switch \builder_csrbank12_en0_re - attribute \src "ls180.v:9749.6-9749.30" + attribute \src "ls180.v:9816.6-9816.30" case 1'1 assign $0\main_libresocsim_en_storage[0:0] \builder_csrbank12_en0_r case end - attribute \src "ls180.v:9753.2-9755.5" + attribute \src "ls180.v:9820.2-9822.5" switch \builder_csrbank12_update_value0_re - attribute \src "ls180.v:9753.6-9753.40" + attribute \src "ls180.v:9820.6-9820.40" case 1'1 assign $0\main_libresocsim_update_value_storage[0:0] \builder_csrbank12_update_value0_r case end - attribute \src "ls180.v:9757.2-9759.5" + attribute \src "ls180.v:9824.2-9826.5" switch \builder_csrbank12_ev_enable0_re - attribute \src "ls180.v:9757.6-9757.37" + attribute \src "ls180.v:9824.6-9824.37" case 1'1 assign $0\main_libresocsim_eventmanager_storage[0:0] \builder_csrbank12_ev_enable0_r case end - attribute \src "ls180.v:9762.2-9789.5" + attribute \src "ls180.v:9829.2-9856.5" switch \builder_csrbank13_sel - attribute \src "ls180.v:9762.6-9762.27" + attribute \src "ls180.v:9829.6-9829.27" case 1'1 - attribute \src "ls180.v:9763.3-9788.10" + attribute \src "ls180.v:9830.3-9855.10" switch \builder_interface13_bank_bus_adr [2:0] attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -280997,18 +282442,18 @@ module \ls180 end case end - attribute \src "ls180.v:9790.2-9792.5" + attribute \src "ls180.v:9857.2-9859.5" switch \builder_csrbank13_ev_enable0_re - attribute \src "ls180.v:9790.6-9790.37" + attribute \src "ls180.v:9857.6-9857.37" case 1'1 assign $0\main_uart_eventmanager_storage[1:0] \builder_csrbank13_ev_enable0_r case end - attribute \src "ls180.v:9795.2-9810.5" + attribute \src "ls180.v:9862.2-9877.5" switch \builder_csrbank14_sel - attribute \src "ls180.v:9795.6-9795.27" + attribute \src "ls180.v:9862.6-9862.27" case 1'1 - attribute \src "ls180.v:9796.3-9809.10" + attribute \src "ls180.v:9863.3-9876.10" switch \builder_interface14_bank_bus_adr [1:0] attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -281026,37 +282471,37 @@ module \ls180 end case end - attribute \src "ls180.v:9811.2-9813.5" + attribute \src "ls180.v:9878.2-9880.5" switch \builder_csrbank14_tuning_word3_re - attribute \src "ls180.v:9811.6-9811.39" + attribute \src "ls180.v:9878.6-9878.39" case 1'1 assign $0\main_uart_phy_storage[31:0] [31:24] \builder_csrbank14_tuning_word3_r case end - attribute \src "ls180.v:9814.2-9816.5" + attribute \src "ls180.v:9881.2-9883.5" switch \builder_csrbank14_tuning_word2_re - attribute \src "ls180.v:9814.6-9814.39" + attribute \src "ls180.v:9881.6-9881.39" case 1'1 assign $0\main_uart_phy_storage[31:0] [23:16] \builder_csrbank14_tuning_word2_r case end - attribute \src "ls180.v:9817.2-9819.5" + attribute \src "ls180.v:9884.2-9886.5" switch \builder_csrbank14_tuning_word1_re - attribute \src "ls180.v:9817.6-9817.39" + attribute \src "ls180.v:9884.6-9884.39" case 1'1 assign $0\main_uart_phy_storage[31:0] [15:8] \builder_csrbank14_tuning_word1_r case end - attribute \src "ls180.v:9820.2-9822.5" + attribute \src "ls180.v:9887.2-9889.5" switch \builder_csrbank14_tuning_word0_re - attribute \src "ls180.v:9820.6-9820.39" + attribute \src "ls180.v:9887.6-9887.39" case 1'1 assign $0\main_uart_phy_storage[31:0] [7:0] \builder_csrbank14_tuning_word0_r case end - attribute \src "ls180.v:9824.2-10121.5" + attribute \src "ls180.v:9891.2-10188.5" switch \sys_rst_1 - attribute \src "ls180.v:9824.6-9824.15" + attribute \src "ls180.v:9891.6-9891.15" case 1'1 assign $0\main_libresocsim_reset_storage[0:0] 1'0 assign $0\main_libresocsim_reset_re[0:0] 1'0 @@ -281067,13 +282512,10 @@ module \ls180 assign $0\spisdcard_clk[0:0] 1'0 assign $0\spisdcard_mosi[0:0] 1'0 assign $0\spisdcard_cs_n[0:0] 1'0 + assign $0\pwm[1:0] 2'00 assign $0\spimaster_clk[0:0] 1'0 assign $0\spimaster_mosi[0:0] 1'0 assign $0\spimaster_cs_n[0:0] 1'0 - assign $0\pwm[1:0] 2'00 - assign $0\main_libresocsim_converter0_counter[0:0] 1'0 - assign $0\main_libresocsim_converter1_counter[0:0] 1'0 - assign $0\main_libresocsim_converter2_counter[0:0] 1'0 assign $0\main_libresocsim_ram_bus_ack[0:0] 1'0 assign $0\main_libresocsim_load_storage[31:0] 0 assign $0\main_libresocsim_load_re[0:0] 1'0 @@ -281092,6 +282534,8 @@ module \ls180 assign $0\main_interface0_ram_bus_ack[0:0] 1'0 assign $0\main_interface1_ram_bus_ack[0:0] 1'0 assign $0\main_interface2_ram_bus_ack[0:0] 1'0 + assign $0\main_converter0_counter[0:0] 1'0 + assign $0\main_converter1_counter[0:0] 1'0 assign $0\main_dfi_p0_rddata_valid[0:0] 1'0 assign $0\main_rddata_en[2:0] 3'000 assign $0\main_sdram_storage[3:0] 4'0001 @@ -281156,6 +282600,7 @@ module \ls180 assign $0\main_sdram_twtrcon_count[2:0] 3'000 assign $0\main_sdram_time0[4:0] 5'00000 assign $0\main_sdram_time1[3:0] 4'0000 + assign $0\main_socbushandler_counter[0:0] 1'0 assign $0\main_converter_counter[0:0] 1'0 assign $0\main_cmd_consumed[0:0] 1'0 assign $0\main_wdata_consumed[0:0] 1'0 @@ -281182,10 +282627,10 @@ module \ls180 assign $0\main_uart_rx_fifo_level0[4:0] 5'00000 assign $0\main_uart_rx_fifo_produce[3:0] 4'0000 assign $0\main_uart_rx_fifo_consume[3:0] 4'0000 - assign $0\main_gpio_oe_storage[15:0] 16'0000000000000000 - assign $0\main_gpio_oe_re[0:0] 1'0 - assign $0\main_gpio_out_storage[15:0] 16'0000000000000000 - assign $0\main_gpio_out_re[0:0] 1'0 + assign $0\main_gpiotristateasic1_oe_storage[15:0] 16'0000000000000000 + assign $0\main_gpiotristateasic1_oe_re[0:0] 1'0 + assign $0\main_gpiotristateasic1_out_storage[15:0] 16'0000000000000000 + assign $0\main_gpiotristateasic1_out_re[0:0] 1'0 assign $0\main_spimaster5_miso[7:0] 8'00000000 assign $0\main_spimaster11_storage[15:0] 16'0000000000000000 assign $0\main_spimaster12_re[0:0] 1'0 @@ -281296,7 +282741,7 @@ module \ls180 assign $0\main_sdblock2mem_fifo_level[5:0] 6'000000 assign $0\main_sdblock2mem_fifo_produce[4:0] 5'00000 assign $0\main_sdblock2mem_fifo_consume[4:0] 5'00000 - assign $0\main_sdblock2mem_converter_demux[1:0] 2'00 + assign $0\main_sdblock2mem_converter_demux[2:0] 3'000 assign $0\main_sdblock2mem_converter_strobe_all[0:0] 1'0 assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 assign $0\main_sdblock2mem_wishbonedmawriter_base_re[0:0] 1'0 @@ -281307,7 +282752,7 @@ module \ls180 assign $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] 1'0 assign $0\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] 1'0 assign $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] 0 - assign $0\main_sdmem2block_dma_data[31:0] 0 + assign $0\main_sdmem2block_dma_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 assign $0\main_sdmem2block_dma_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 assign $0\main_sdmem2block_dma_base_re[0:0] 1'0 assign $0\main_sdmem2block_dma_length_storage[31:0] 0 @@ -281317,7 +282762,7 @@ module \ls180 assign $0\main_sdmem2block_dma_loop_storage[0:0] 1'0 assign $0\main_sdmem2block_dma_loop_re[0:0] 1'0 assign $0\main_sdmem2block_dma_offset[31:0] 0 - assign $0\main_sdmem2block_converter_mux[1:0] 2'00 + assign $0\main_sdmem2block_converter_mux[2:0] 3'000 assign $0\main_sdmem2block_fifo_level[5:0] 6'000000 assign $0\main_sdmem2block_fifo_produce[4:0] 5'00000 assign $0\main_sdmem2block_fifo_consume[4:0] 5'00000 @@ -281361,21 +282806,15 @@ module \ls180 update \spisdcard_clk $0\spisdcard_clk[0:0] update \spisdcard_mosi $0\spisdcard_mosi[0:0] update \spisdcard_cs_n $0\spisdcard_cs_n[0:0] + update \pwm $0\pwm[1:0] update \spimaster_clk $0\spimaster_clk[0:0] update \spimaster_mosi $0\spimaster_mosi[0:0] update \spimaster_cs_n $0\spimaster_cs_n[0:0] - update \pwm $0\pwm[1:0] update \main_libresocsim_reset_storage $0\main_libresocsim_reset_storage[0:0] update \main_libresocsim_reset_re $0\main_libresocsim_reset_re[0:0] update \main_libresocsim_scratch_storage $0\main_libresocsim_scratch_storage[31:0] update \main_libresocsim_scratch_re $0\main_libresocsim_scratch_re[0:0] update \main_libresocsim_bus_errors $0\main_libresocsim_bus_errors[31:0] - update \main_libresocsim_converter0_counter $0\main_libresocsim_converter0_counter[0:0] - update \main_libresocsim_converter0_dat_r $0\main_libresocsim_converter0_dat_r[63:0] - update \main_libresocsim_converter1_counter $0\main_libresocsim_converter1_counter[0:0] - update \main_libresocsim_converter1_dat_r $0\main_libresocsim_converter1_dat_r[63:0] - update \main_libresocsim_converter2_counter $0\main_libresocsim_converter2_counter[0:0] - update \main_libresocsim_converter2_dat_r $0\main_libresocsim_converter2_dat_r[63:0] update \main_libresocsim_ram_bus_ack $0\main_libresocsim_ram_bus_ack[0:0] update \main_libresocsim_load_storage $0\main_libresocsim_load_storage[31:0] update \main_libresocsim_load_re $0\main_libresocsim_load_re[0:0] @@ -281394,6 +282833,10 @@ module \ls180 update \main_interface0_ram_bus_ack $0\main_interface0_ram_bus_ack[0:0] update \main_interface1_ram_bus_ack $0\main_interface1_ram_bus_ack[0:0] update \main_interface2_ram_bus_ack $0\main_interface2_ram_bus_ack[0:0] + update \main_converter0_counter $0\main_converter0_counter[0:0] + update \main_converter0_dat_r $0\main_converter0_dat_r[63:0] + update \main_converter1_counter $0\main_converter1_counter[0:0] + update \main_converter1_dat_r $0\main_converter1_dat_r[63:0] update \main_dfi_p0_rddata_valid $0\main_dfi_p0_rddata_valid[0:0] update \main_rddata_en $0\main_rddata_en[2:0] update \main_sdram_storage $0\main_sdram_storage[3:0] @@ -281482,6 +282925,8 @@ module \ls180 update \main_sdram_twtrcon_count $0\main_sdram_twtrcon_count[2:0] update \main_sdram_time0 $0\main_sdram_time0[4:0] update \main_sdram_time1 $0\main_sdram_time1[3:0] + update \main_socbushandler_counter $0\main_socbushandler_counter[0:0] + update \main_socbushandler_dat_r $0\main_socbushandler_dat_r[63:0] update \main_converter_counter $0\main_converter_counter[0:0] update \main_converter_dat_r $0\main_converter_dat_r[31:0] update \main_cmd_consumed $0\main_cmd_consumed[0:0] @@ -281516,10 +282961,10 @@ module \ls180 update \main_uart_rx_fifo_level0 $0\main_uart_rx_fifo_level0[4:0] update \main_uart_rx_fifo_produce $0\main_uart_rx_fifo_produce[3:0] update \main_uart_rx_fifo_consume $0\main_uart_rx_fifo_consume[3:0] - update \main_gpio_oe_storage $0\main_gpio_oe_storage[15:0] - update \main_gpio_oe_re $0\main_gpio_oe_re[0:0] - update \main_gpio_out_storage $0\main_gpio_out_storage[15:0] - update \main_gpio_out_re $0\main_gpio_out_re[0:0] + update \main_gpiotristateasic1_oe_storage $0\main_gpiotristateasic1_oe_storage[15:0] + update \main_gpiotristateasic1_oe_re $0\main_gpiotristateasic1_oe_re[0:0] + update \main_gpiotristateasic1_out_storage $0\main_gpiotristateasic1_out_storage[15:0] + update \main_gpiotristateasic1_out_re $0\main_gpiotristateasic1_out_re[0:0] update \main_spimaster5_miso $0\main_spimaster5_miso[7:0] update \main_spimaster11_storage $0\main_spimaster11_storage[15:0] update \main_spimaster12_re $0\main_spimaster12_re[0:0] @@ -281661,9 +283106,9 @@ module \ls180 update \main_sdblock2mem_fifo_consume $0\main_sdblock2mem_fifo_consume[4:0] update \main_sdblock2mem_converter_source_first $0\main_sdblock2mem_converter_source_first[0:0] update \main_sdblock2mem_converter_source_last $0\main_sdblock2mem_converter_source_last[0:0] - update \main_sdblock2mem_converter_source_payload_data $0\main_sdblock2mem_converter_source_payload_data[31:0] - update \main_sdblock2mem_converter_source_payload_valid_token_count $0\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] - update \main_sdblock2mem_converter_demux $0\main_sdblock2mem_converter_demux[1:0] + update \main_sdblock2mem_converter_source_payload_data $0\main_sdblock2mem_converter_source_payload_data[63:0] + update \main_sdblock2mem_converter_source_payload_valid_token_count $0\main_sdblock2mem_converter_source_payload_valid_token_count[3:0] + update \main_sdblock2mem_converter_demux $0\main_sdblock2mem_converter_demux[2:0] update \main_sdblock2mem_converter_strobe_all $0\main_sdblock2mem_converter_strobe_all[0:0] update \main_sdblock2mem_wishbonedmawriter_base_storage $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] update \main_sdblock2mem_wishbonedmawriter_base_re $0\main_sdblock2mem_wishbonedmawriter_base_re[0:0] @@ -281674,7 +283119,7 @@ module \ls180 update \main_sdblock2mem_wishbonedmawriter_loop_storage $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] update \main_sdblock2mem_wishbonedmawriter_loop_re $0\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] update \main_sdblock2mem_wishbonedmawriter_offset $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] - update \main_sdmem2block_dma_data $0\main_sdmem2block_dma_data[31:0] + update \main_sdmem2block_dma_data $0\main_sdmem2block_dma_data[63:0] update \main_sdmem2block_dma_base_storage $0\main_sdmem2block_dma_base_storage[63:0] update \main_sdmem2block_dma_base_re $0\main_sdmem2block_dma_base_re[0:0] update \main_sdmem2block_dma_length_storage $0\main_sdmem2block_dma_length_storage[31:0] @@ -281684,7 +283129,7 @@ module \ls180 update \main_sdmem2block_dma_loop_storage $0\main_sdmem2block_dma_loop_storage[0:0] update \main_sdmem2block_dma_loop_re $0\main_sdmem2block_dma_loop_re[0:0] update \main_sdmem2block_dma_offset $0\main_sdmem2block_dma_offset[31:0] - update \main_sdmem2block_converter_mux $0\main_sdmem2block_converter_mux[1:0] + update \main_sdmem2block_converter_mux $0\main_sdmem2block_converter_mux[2:0] update \main_sdmem2block_fifo_level $0\main_sdmem2block_fifo_level[5:0] update \main_sdmem2block_fifo_produce $0\main_sdmem2block_fifo_produce[4:0] update \main_sdmem2block_fifo_consume $0\main_sdmem2block_fifo_consume[4:0] @@ -281773,800 +283218,864 @@ module \ls180 update \builder_multiregimpl16_regs0 $0\builder_multiregimpl16_regs0[0:0] update \builder_multiregimpl16_regs1 $0\builder_multiregimpl16_regs1[0:0] end - attribute \src "ls180.v:760.5-760.59" - process $proc$ls180.v:760$3156 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_buffer_source_valid $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] - end - attribute \src "ls180.v:762.5-762.59" - process $proc$ls180.v:762$3157 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_buffer_source_first $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] - end - attribute \src "ls180.v:763.5-763.58" - process $proc$ls180.v:763$3158 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_buffer_source_last $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] - end - attribute \src "ls180.v:764.5-764.64" - process $proc$ls180.v:764$3159 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_buffer_source_payload_we $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] - end - attribute \src "ls180.v:765.12-765.74" - process $proc$ls180.v:765$3160 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 - sync always - sync init - update \main_sdram_bankmachine3_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] - end - attribute \src "ls180.v:766.12-766.47" - process $proc$ls180.v:766$3161 - assign { } { } - assign $1\main_sdram_bankmachine3_row[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_bankmachine3_row $1\main_sdram_bankmachine3_row[12:0] - end - attribute \src "ls180.v:767.5-767.46" - process $proc$ls180.v:767$3162 - assign { } { } - assign $1\main_sdram_bankmachine3_row_opened[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_row_opened $1\main_sdram_bankmachine3_row_opened[0:0] - end - attribute \src "ls180.v:769.5-769.44" - process $proc$ls180.v:769$3163 - assign { } { } - assign $1\main_sdram_bankmachine3_row_open[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_row_open $1\main_sdram_bankmachine3_row_open[0:0] - end - attribute \src "ls180.v:770.5-770.45" - process $proc$ls180.v:770$3164 - assign { } { } - assign $1\main_sdram_bankmachine3_row_close[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_row_close $1\main_sdram_bankmachine3_row_close[0:0] - end - attribute \src "ls180.v:771.5-771.54" - process $proc$ls180.v:771$3165 - assign { } { } - assign $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_row_col_n_addr_sel $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] - end - attribute \src "ls180.v:773.32-773.76" - process $proc$ls180.v:773$3166 + attribute \src "ls180.v:760.32-760.76" + process $proc$ls180.v:760$3286 assign { } { } assign $1\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'0 sync always sync init update \main_sdram_bankmachine3_twtpcon_ready $1\main_sdram_bankmachine3_twtpcon_ready[0:0] end - attribute \src "ls180.v:774.11-774.55" - process $proc$ls180.v:774$3167 + attribute \src "ls180.v:761.11-761.55" + process $proc$ls180.v:761$3287 assign { } { } assign $1\main_sdram_bankmachine3_twtpcon_count[2:0] 3'000 sync always sync init update \main_sdram_bankmachine3_twtpcon_count $1\main_sdram_bankmachine3_twtpcon_count[2:0] end - attribute \src "ls180.v:776.32-776.75" - process $proc$ls180.v:776$3168 + attribute \src "ls180.v:763.32-763.75" + process $proc$ls180.v:763$3288 assign { } { } assign $0\main_sdram_bankmachine3_trccon_ready[0:0] 1'1 sync always update \main_sdram_bankmachine3_trccon_ready $0\main_sdram_bankmachine3_trccon_ready[0:0] sync init end - attribute \src "ls180.v:778.32-778.76" - process $proc$ls180.v:778$3169 + attribute \src "ls180.v:765.32-765.76" + process $proc$ls180.v:765$3289 assign { } { } assign $0\main_sdram_bankmachine3_trascon_ready[0:0] 1'1 sync always update \main_sdram_bankmachine3_trascon_ready $0\main_sdram_bankmachine3_trascon_ready[0:0] sync init end - attribute \src "ls180.v:781.5-781.44" - process $proc$ls180.v:781$3170 + attribute \src "ls180.v:768.5-768.44" + process $proc$ls180.v:768$3290 assign { } { } assign $0\main_sdram_choose_cmd_want_reads[0:0] 1'0 sync always update \main_sdram_choose_cmd_want_reads $0\main_sdram_choose_cmd_want_reads[0:0] sync init end - attribute \src "ls180.v:782.5-782.45" - process $proc$ls180.v:782$3171 + attribute \src "ls180.v:769.5-769.45" + process $proc$ls180.v:769$3291 assign { } { } assign $0\main_sdram_choose_cmd_want_writes[0:0] 1'0 sync always update \main_sdram_choose_cmd_want_writes $0\main_sdram_choose_cmd_want_writes[0:0] sync init end - attribute \src "ls180.v:783.5-783.43" - process $proc$ls180.v:783$3172 + attribute \src "ls180.v:770.5-770.43" + process $proc$ls180.v:770$3292 assign { } { } assign $0\main_sdram_choose_cmd_want_cmds[0:0] 1'0 sync always update \main_sdram_choose_cmd_want_cmds $0\main_sdram_choose_cmd_want_cmds[0:0] sync init end - attribute \src "ls180.v:784.5-784.48" - process $proc$ls180.v:784$3173 + attribute \src "ls180.v:771.5-771.48" + process $proc$ls180.v:771$3293 assign { } { } assign $0\main_sdram_choose_cmd_want_activates[0:0] 1'0 sync always update \main_sdram_choose_cmd_want_activates $0\main_sdram_choose_cmd_want_activates[0:0] sync init end - attribute \src "ls180.v:786.5-786.43" - process $proc$ls180.v:786$3174 + attribute \src "ls180.v:773.5-773.43" + process $proc$ls180.v:773$3294 assign { } { } assign $0\main_sdram_choose_cmd_cmd_ready[0:0] 1'0 sync always update \main_sdram_choose_cmd_cmd_ready $0\main_sdram_choose_cmd_cmd_ready[0:0] sync init end - attribute \src "ls180.v:789.5-789.49" - process $proc$ls180.v:789$3175 + attribute \src "ls180.v:776.5-776.49" + process $proc$ls180.v:776$3295 assign { } { } assign $1\main_sdram_choose_cmd_cmd_payload_cas[0:0] 1'0 sync always sync init update \main_sdram_choose_cmd_cmd_payload_cas $1\main_sdram_choose_cmd_cmd_payload_cas[0:0] end - attribute \src "ls180.v:790.5-790.49" - process $proc$ls180.v:790$3176 + attribute \src "ls180.v:777.5-777.49" + process $proc$ls180.v:777$3296 assign { } { } assign $1\main_sdram_choose_cmd_cmd_payload_ras[0:0] 1'0 sync always sync init update \main_sdram_choose_cmd_cmd_payload_ras $1\main_sdram_choose_cmd_cmd_payload_ras[0:0] end - attribute \src "ls180.v:791.5-791.48" - process $proc$ls180.v:791$3177 + attribute \src "ls180.v:778.5-778.48" + process $proc$ls180.v:778$3297 assign { } { } assign $1\main_sdram_choose_cmd_cmd_payload_we[0:0] 1'0 sync always sync init update \main_sdram_choose_cmd_cmd_payload_we $1\main_sdram_choose_cmd_cmd_payload_we[0:0] end - attribute \src "ls180.v:795.11-795.46" - process $proc$ls180.v:795$3178 + attribute \src "ls180.v:782.11-782.46" + process $proc$ls180.v:782$3298 assign { } { } assign $1\main_sdram_choose_cmd_valids[3:0] 4'0000 sync always sync init update \main_sdram_choose_cmd_valids $1\main_sdram_choose_cmd_valids[3:0] end - attribute \src "ls180.v:797.11-797.45" - process $proc$ls180.v:797$3179 + attribute \src "ls180.v:784.11-784.45" + process $proc$ls180.v:784$3299 assign { } { } assign $1\main_sdram_choose_cmd_grant[1:0] 2'00 sync always sync init update \main_sdram_choose_cmd_grant $1\main_sdram_choose_cmd_grant[1:0] end - attribute \src "ls180.v:799.5-799.44" - process $proc$ls180.v:799$3180 + attribute \src "ls180.v:786.5-786.44" + process $proc$ls180.v:786$3300 assign { } { } assign $1\main_sdram_choose_req_want_reads[0:0] 1'0 sync always sync init update \main_sdram_choose_req_want_reads $1\main_sdram_choose_req_want_reads[0:0] end - attribute \src "ls180.v:800.5-800.45" - process $proc$ls180.v:800$3181 + attribute \src "ls180.v:787.5-787.45" + process $proc$ls180.v:787$3301 assign { } { } assign $1\main_sdram_choose_req_want_writes[0:0] 1'0 sync always sync init update \main_sdram_choose_req_want_writes $1\main_sdram_choose_req_want_writes[0:0] end - attribute \src "ls180.v:802.5-802.48" - process $proc$ls180.v:802$3182 + attribute \src "ls180.v:789.5-789.48" + process $proc$ls180.v:789$3302 assign { } { } assign $1\main_sdram_choose_req_want_activates[0:0] 1'0 sync always sync init update \main_sdram_choose_req_want_activates $1\main_sdram_choose_req_want_activates[0:0] end - attribute \src "ls180.v:804.5-804.43" - process $proc$ls180.v:804$3183 + attribute \src "ls180.v:791.5-791.43" + process $proc$ls180.v:791$3303 assign { } { } assign $1\main_sdram_choose_req_cmd_ready[0:0] 1'0 sync always sync init update \main_sdram_choose_req_cmd_ready $1\main_sdram_choose_req_cmd_ready[0:0] end - attribute \src "ls180.v:807.5-807.49" - process $proc$ls180.v:807$3184 + attribute \src "ls180.v:794.5-794.49" + process $proc$ls180.v:794$3304 assign { } { } assign $1\main_sdram_choose_req_cmd_payload_cas[0:0] 1'0 sync always sync init update \main_sdram_choose_req_cmd_payload_cas $1\main_sdram_choose_req_cmd_payload_cas[0:0] end - attribute \src "ls180.v:808.5-808.49" - process $proc$ls180.v:808$3185 + attribute \src "ls180.v:795.5-795.49" + process $proc$ls180.v:795$3305 assign { } { } assign $1\main_sdram_choose_req_cmd_payload_ras[0:0] 1'0 sync always sync init update \main_sdram_choose_req_cmd_payload_ras $1\main_sdram_choose_req_cmd_payload_ras[0:0] end - attribute \src "ls180.v:809.5-809.48" - process $proc$ls180.v:809$3186 + attribute \src "ls180.v:796.5-796.48" + process $proc$ls180.v:796$3306 assign { } { } assign $1\main_sdram_choose_req_cmd_payload_we[0:0] 1'0 sync always sync init update \main_sdram_choose_req_cmd_payload_we $1\main_sdram_choose_req_cmd_payload_we[0:0] end - attribute \src "ls180.v:81.5-81.46" - process $proc$ls180.v:81$2903 - assign { } { } - assign $1\main_libresocsim_libresoc_ibus_ack[0:0] 1'0 - sync always - sync init - update \main_libresocsim_libresoc_ibus_ack $1\main_libresocsim_libresoc_ibus_ack[0:0] - end - attribute \src "ls180.v:813.11-813.46" - process $proc$ls180.v:813$3187 + attribute \src "ls180.v:800.11-800.46" + process $proc$ls180.v:800$3307 assign { } { } assign $1\main_sdram_choose_req_valids[3:0] 4'0000 sync always sync init update \main_sdram_choose_req_valids $1\main_sdram_choose_req_valids[3:0] end - attribute \src "ls180.v:815.11-815.45" - process $proc$ls180.v:815$3188 + attribute \src "ls180.v:802.11-802.45" + process $proc$ls180.v:802$3308 assign { } { } assign $1\main_sdram_choose_req_grant[1:0] 2'00 sync always sync init update \main_sdram_choose_req_grant $1\main_sdram_choose_req_grant[1:0] end - attribute \src "ls180.v:817.12-817.36" - process $proc$ls180.v:817$3189 + attribute \src "ls180.v:804.12-804.36" + process $proc$ls180.v:804$3309 assign { } { } assign $0\main_sdram_nop_a[12:0] 13'0000000000000 sync always update \main_sdram_nop_a $0\main_sdram_nop_a[12:0] sync init end - attribute \src "ls180.v:818.11-818.35" - process $proc$ls180.v:818$3190 + attribute \src "ls180.v:805.11-805.35" + process $proc$ls180.v:805$3310 assign { } { } assign $0\main_sdram_nop_ba[1:0] 2'00 sync always update \main_sdram_nop_ba $0\main_sdram_nop_ba[1:0] sync init end - attribute \src "ls180.v:819.11-819.40" - process $proc$ls180.v:819$3191 + attribute \src "ls180.v:806.11-806.40" + process $proc$ls180.v:806$3311 assign { } { } assign $1\main_sdram_steerer_sel[1:0] 2'00 sync always sync init update \main_sdram_steerer_sel $1\main_sdram_steerer_sel[1:0] end - attribute \src "ls180.v:820.5-820.31" - process $proc$ls180.v:820$3192 + attribute \src "ls180.v:807.5-807.31" + process $proc$ls180.v:807$3312 assign { } { } assign $0\main_sdram_steerer0[0:0] 1'1 sync always update \main_sdram_steerer0 $0\main_sdram_steerer0[0:0] sync init end - attribute \src "ls180.v:821.5-821.31" - process $proc$ls180.v:821$3193 + attribute \src "ls180.v:808.5-808.31" + process $proc$ls180.v:808$3313 assign { } { } assign $0\main_sdram_steerer1[0:0] 1'1 sync always update \main_sdram_steerer1 $0\main_sdram_steerer1[0:0] sync init end - attribute \src "ls180.v:823.32-823.63" - process $proc$ls180.v:823$3194 + attribute \src "ls180.v:810.32-810.63" + process $proc$ls180.v:810$3314 assign { } { } assign $0\main_sdram_trrdcon_ready[0:0] 1'1 sync always update \main_sdram_trrdcon_ready $0\main_sdram_trrdcon_ready[0:0] sync init end - attribute \src "ls180.v:825.32-825.63" - process $proc$ls180.v:825$3195 + attribute \src "ls180.v:812.32-812.63" + process $proc$ls180.v:812$3315 assign { } { } assign $0\main_sdram_tfawcon_ready[0:0] 1'1 sync always update \main_sdram_tfawcon_ready $0\main_sdram_tfawcon_ready[0:0] sync init end - attribute \src "ls180.v:827.32-827.63" - process $proc$ls180.v:827$3196 + attribute \src "ls180.v:814.32-814.63" + process $proc$ls180.v:814$3316 assign { } { } assign $1\main_sdram_tccdcon_ready[0:0] 1'0 sync always sync init update \main_sdram_tccdcon_ready $1\main_sdram_tccdcon_ready[0:0] end - attribute \src "ls180.v:828.5-828.36" - process $proc$ls180.v:828$3197 + attribute \src "ls180.v:815.5-815.36" + process $proc$ls180.v:815$3317 assign { } { } assign $1\main_sdram_tccdcon_count[0:0] 1'0 sync always sync init update \main_sdram_tccdcon_count $1\main_sdram_tccdcon_count[0:0] end - attribute \src "ls180.v:83.5-83.46" - process $proc$ls180.v:83$2904 - assign { } { } - assign $0\main_libresocsim_libresoc_ibus_err[0:0] 1'0 - sync always - update \main_libresocsim_libresoc_ibus_err $0\main_libresocsim_libresoc_ibus_err[0:0] - sync init - end - attribute \src "ls180.v:830.32-830.63" - process $proc$ls180.v:830$3198 + attribute \src "ls180.v:817.32-817.63" + process $proc$ls180.v:817$3318 assign { } { } assign $1\main_sdram_twtrcon_ready[0:0] 1'0 sync always sync init update \main_sdram_twtrcon_ready $1\main_sdram_twtrcon_ready[0:0] end - attribute \src "ls180.v:831.11-831.42" - process $proc$ls180.v:831$3199 + attribute \src "ls180.v:818.11-818.42" + process $proc$ls180.v:818$3319 assign { } { } assign $1\main_sdram_twtrcon_count[2:0] 3'000 sync always sync init update \main_sdram_twtrcon_count $1\main_sdram_twtrcon_count[2:0] end - attribute \src "ls180.v:834.5-834.26" - process $proc$ls180.v:834$3200 + attribute \src "ls180.v:821.5-821.26" + process $proc$ls180.v:821$3320 assign { } { } assign $1\main_sdram_en0[0:0] 1'0 sync always sync init update \main_sdram_en0 $1\main_sdram_en0[0:0] end - attribute \src "ls180.v:836.11-836.34" - process $proc$ls180.v:836$3201 + attribute \src "ls180.v:823.11-823.34" + process $proc$ls180.v:823$3321 assign { } { } assign $1\main_sdram_time0[4:0] 5'00000 sync always sync init update \main_sdram_time0 $1\main_sdram_time0[4:0] end - attribute \src "ls180.v:837.5-837.26" - process $proc$ls180.v:837$3202 + attribute \src "ls180.v:824.5-824.26" + process $proc$ls180.v:824$3322 assign { } { } assign $1\main_sdram_en1[0:0] 1'0 sync always sync init update \main_sdram_en1 $1\main_sdram_en1[0:0] end - attribute \src "ls180.v:839.11-839.34" - process $proc$ls180.v:839$3203 + attribute \src "ls180.v:826.11-826.34" + process $proc$ls180.v:826$3323 assign { } { } assign $1\main_sdram_time1[3:0] 4'0000 sync always sync init update \main_sdram_time1 $1\main_sdram_time1[3:0] end - attribute \src "ls180.v:860.5-860.29" - process $proc$ls180.v:860$3204 + attribute \src "ls180.v:841.12-841.37" + process $proc$ls180.v:841$3324 + assign { } { } + assign $1\main_wb_sdram_adr[29:0] 30'000000000000000000000000000000 + sync always + sync init + update \main_wb_sdram_adr $1\main_wb_sdram_adr[29:0] + end + attribute \src "ls180.v:842.12-842.39" + process $proc$ls180.v:842$3325 + assign { } { } + assign $1\main_wb_sdram_dat_w[31:0] 0 + sync always + sync init + update \main_wb_sdram_dat_w $1\main_wb_sdram_dat_w[31:0] + end + attribute \src "ls180.v:844.11-844.35" + process $proc$ls180.v:844$3326 + assign { } { } + assign $1\main_wb_sdram_sel[3:0] 4'0000 + sync always + sync init + update \main_wb_sdram_sel $1\main_wb_sdram_sel[3:0] + end + attribute \src "ls180.v:845.5-845.29" + process $proc$ls180.v:845$3327 + assign { } { } + assign $1\main_wb_sdram_cyc[0:0] 1'0 + sync always + sync init + update \main_wb_sdram_cyc $1\main_wb_sdram_cyc[0:0] + end + attribute \src "ls180.v:846.5-846.29" + process $proc$ls180.v:846$3328 + assign { } { } + assign $1\main_wb_sdram_stb[0:0] 1'0 + sync always + sync init + update \main_wb_sdram_stb $1\main_wb_sdram_stb[0:0] + end + attribute \src "ls180.v:847.5-847.29" + process $proc$ls180.v:847$3329 assign { } { } assign $1\main_wb_sdram_ack[0:0] 1'0 sync always sync init update \main_wb_sdram_ack $1\main_wb_sdram_ack[0:0] end - attribute \src "ls180.v:864.5-864.29" - process $proc$ls180.v:864$3205 + attribute \src "ls180.v:848.5-848.28" + process $proc$ls180.v:848$3330 assign { } { } - assign $0\main_wb_sdram_err[0:0] 1'0 + assign $1\main_wb_sdram_we[0:0] 1'0 sync always - update \main_wb_sdram_err $0\main_wb_sdram_err[0:0] sync init + update \main_wb_sdram_we $1\main_wb_sdram_we[0:0] end - attribute \src "ls180.v:865.12-865.40" - process $proc$ls180.v:865$3206 + attribute \src "ls180.v:85.11-85.52" + process $proc$ls180.v:85$3034 + assign { } { } + assign $0\main_libresocsim_libresoc_ibus_cti[2:0] 3'000 + sync always + update \main_libresocsim_libresoc_ibus_cti $0\main_libresocsim_libresoc_ibus_cti[2:0] + sync init + end + attribute \src "ls180.v:855.5-855.54" + process $proc$ls180.v:855$3331 + assign { } { } + assign $1\main_socbushandler_converted_interface_ack[0:0] 1'0 + sync always + sync init + update \main_socbushandler_converted_interface_ack $1\main_socbushandler_converted_interface_ack[0:0] + end + attribute \src "ls180.v:859.5-859.54" + process $proc$ls180.v:859$3332 + assign { } { } + assign $0\main_socbushandler_converted_interface_err[0:0] 1'0 + sync always + update \main_socbushandler_converted_interface_err $0\main_socbushandler_converted_interface_err[0:0] + sync init + end + attribute \src "ls180.v:86.11-86.52" + process $proc$ls180.v:86$3035 + assign { } { } + assign $0\main_libresocsim_libresoc_ibus_bte[1:0] 2'00 + sync always + update \main_libresocsim_libresoc_ibus_bte $0\main_libresocsim_libresoc_ibus_bte[1:0] + sync init + end + attribute \src "ls180.v:860.5-860.35" + process $proc$ls180.v:860$3333 + assign { } { } + assign $1\main_socbushandler_skip[0:0] 1'0 + sync always + sync init + update \main_socbushandler_skip $1\main_socbushandler_skip[0:0] + end + attribute \src "ls180.v:861.5-861.38" + process $proc$ls180.v:861$3334 + assign { } { } + assign $1\main_socbushandler_counter[0:0] 1'0 + sync always + sync init + update \main_socbushandler_counter $1\main_socbushandler_counter[0:0] + end + attribute \src "ls180.v:863.12-863.44" + process $proc$ls180.v:863$3335 + assign { } { } + assign $1\main_socbushandler_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \main_socbushandler_dat_r $1\main_socbushandler_dat_r[63:0] + end + attribute \src "ls180.v:864.12-864.40" + process $proc$ls180.v:864$3336 assign { } { } assign $1\main_litedram_wb_adr[29:0] 30'000000000000000000000000000000 sync always sync init update \main_litedram_wb_adr $1\main_litedram_wb_adr[29:0] end - attribute \src "ls180.v:866.12-866.42" - process $proc$ls180.v:866$3207 + attribute \src "ls180.v:865.12-865.42" + process $proc$ls180.v:865$3337 assign { } { } assign $1\main_litedram_wb_dat_w[15:0] 16'0000000000000000 sync always sync init update \main_litedram_wb_dat_w $1\main_litedram_wb_dat_w[15:0] end - attribute \src "ls180.v:868.11-868.38" - process $proc$ls180.v:868$3208 + attribute \src "ls180.v:867.11-867.38" + process $proc$ls180.v:867$3338 assign { } { } assign $1\main_litedram_wb_sel[1:0] 2'00 sync always sync init update \main_litedram_wb_sel $1\main_litedram_wb_sel[1:0] end - attribute \src "ls180.v:869.5-869.32" - process $proc$ls180.v:869$3209 + attribute \src "ls180.v:868.5-868.32" + process $proc$ls180.v:868$3339 assign { } { } assign $1\main_litedram_wb_cyc[0:0] 1'0 sync always sync init update \main_litedram_wb_cyc $1\main_litedram_wb_cyc[0:0] end - attribute \src "ls180.v:870.5-870.32" - process $proc$ls180.v:870$3210 + attribute \src "ls180.v:869.5-869.32" + process $proc$ls180.v:869$3340 assign { } { } assign $1\main_litedram_wb_stb[0:0] 1'0 sync always sync init update \main_litedram_wb_stb $1\main_litedram_wb_stb[0:0] end - attribute \src "ls180.v:872.5-872.31" - process $proc$ls180.v:872$3211 + attribute \src "ls180.v:871.5-871.31" + process $proc$ls180.v:871$3341 assign { } { } assign $1\main_litedram_wb_we[0:0] 1'0 sync always sync init update \main_litedram_wb_we $1\main_litedram_wb_we[0:0] end - attribute \src "ls180.v:873.5-873.31" - process $proc$ls180.v:873$3212 + attribute \src "ls180.v:872.5-872.31" + process $proc$ls180.v:872$3342 assign { } { } assign $1\main_converter_skip[0:0] 1'0 sync always sync init update \main_converter_skip $1\main_converter_skip[0:0] end - attribute \src "ls180.v:874.5-874.34" - process $proc$ls180.v:874$3213 + attribute \src "ls180.v:873.5-873.34" + process $proc$ls180.v:873$3343 assign { } { } assign $1\main_converter_counter[0:0] 1'0 sync always sync init update \main_converter_counter $1\main_converter_counter[0:0] end - attribute \src "ls180.v:876.12-876.40" - process $proc$ls180.v:876$3214 + attribute \src "ls180.v:875.12-875.40" + process $proc$ls180.v:875$3344 assign { } { } assign $1\main_converter_dat_r[31:0] 0 sync always sync init update \main_converter_dat_r $1\main_converter_dat_r[31:0] end - attribute \src "ls180.v:877.5-877.29" - process $proc$ls180.v:877$3215 + attribute \src "ls180.v:876.5-876.29" + process $proc$ls180.v:876$3345 assign { } { } assign $1\main_cmd_consumed[0:0] 1'0 sync always sync init update \main_cmd_consumed $1\main_cmd_consumed[0:0] end - attribute \src "ls180.v:878.5-878.31" - process $proc$ls180.v:878$3216 + attribute \src "ls180.v:877.5-877.31" + process $proc$ls180.v:877$3346 assign { } { } assign $1\main_wdata_consumed[0:0] 1'0 sync always sync init update \main_wdata_consumed $1\main_wdata_consumed[0:0] end - attribute \src "ls180.v:882.12-882.47" - process $proc$ls180.v:882$3217 + attribute \src "ls180.v:88.12-88.58" + process $proc$ls180.v:88$3036 + assign { } { } + assign $1\main_libresocsim_libresoc_xics_icp_adr[29:0] 30'000000000000000000000000000000 + sync always + sync init + update \main_libresocsim_libresoc_xics_icp_adr $1\main_libresocsim_libresoc_xics_icp_adr[29:0] + end + attribute \src "ls180.v:881.12-881.47" + process $proc$ls180.v:881$3347 assign { } { } assign $1\main_uart_phy_storage[31:0] 9895604 sync always sync init update \main_uart_phy_storage $1\main_uart_phy_storage[31:0] end - attribute \src "ls180.v:883.5-883.28" - process $proc$ls180.v:883$3218 + attribute \src "ls180.v:882.5-882.28" + process $proc$ls180.v:882$3348 assign { } { } assign $1\main_uart_phy_re[0:0] 1'0 sync always sync init update \main_uart_phy_re $1\main_uart_phy_re[0:0] end - attribute \src "ls180.v:885.5-885.36" - process $proc$ls180.v:885$3219 + attribute \src "ls180.v:884.5-884.36" + process $proc$ls180.v:884$3349 assign { } { } assign $1\main_uart_phy_sink_ready[0:0] 1'0 sync always sync init update \main_uart_phy_sink_ready $1\main_uart_phy_sink_ready[0:0] end - attribute \src "ls180.v:889.5-889.39" - process $proc$ls180.v:889$3220 + attribute \src "ls180.v:888.5-888.39" + process $proc$ls180.v:888$3350 assign { } { } assign $1\main_uart_phy_uart_clk_txen[0:0] 1'0 sync always sync init update \main_uart_phy_uart_clk_txen $1\main_uart_phy_uart_clk_txen[0:0] end - attribute \src "ls180.v:890.12-890.54" - process $proc$ls180.v:890$3221 + attribute \src "ls180.v:889.12-889.54" + process $proc$ls180.v:889$3351 assign { } { } assign $1\main_uart_phy_phase_accumulator_tx[31:0] 0 sync always sync init update \main_uart_phy_phase_accumulator_tx $1\main_uart_phy_phase_accumulator_tx[31:0] end - attribute \src "ls180.v:891.11-891.38" - process $proc$ls180.v:891$3222 + attribute \src "ls180.v:89.12-89.60" + process $proc$ls180.v:89$3037 + assign { } { } + assign $1\main_libresocsim_libresoc_xics_icp_dat_w[31:0] 0 + sync always + sync init + update \main_libresocsim_libresoc_xics_icp_dat_w $1\main_libresocsim_libresoc_xics_icp_dat_w[31:0] + end + attribute \src "ls180.v:890.11-890.38" + process $proc$ls180.v:890$3352 assign { } { } assign $1\main_uart_phy_tx_reg[7:0] 8'00000000 sync always sync init update \main_uart_phy_tx_reg $1\main_uart_phy_tx_reg[7:0] end - attribute \src "ls180.v:892.11-892.43" - process $proc$ls180.v:892$3223 + attribute \src "ls180.v:891.11-891.43" + process $proc$ls180.v:891$3353 assign { } { } assign $1\main_uart_phy_tx_bitcount[3:0] 4'0000 sync always sync init update \main_uart_phy_tx_bitcount $1\main_uart_phy_tx_bitcount[3:0] end - attribute \src "ls180.v:893.5-893.33" - process $proc$ls180.v:893$3224 + attribute \src "ls180.v:892.5-892.33" + process $proc$ls180.v:892$3354 assign { } { } assign $1\main_uart_phy_tx_busy[0:0] 1'0 sync always sync init update \main_uart_phy_tx_busy $1\main_uart_phy_tx_busy[0:0] end - attribute \src "ls180.v:894.5-894.38" - process $proc$ls180.v:894$3225 + attribute \src "ls180.v:893.5-893.38" + process $proc$ls180.v:893$3355 assign { } { } assign $1\main_uart_phy_source_valid[0:0] 1'0 sync always sync init update \main_uart_phy_source_valid $1\main_uart_phy_source_valid[0:0] end - attribute \src "ls180.v:896.5-896.38" - process $proc$ls180.v:896$3226 + attribute \src "ls180.v:895.5-895.38" + process $proc$ls180.v:895$3356 assign { } { } assign $0\main_uart_phy_source_first[0:0] 1'0 sync always update \main_uart_phy_source_first $0\main_uart_phy_source_first[0:0] sync init end - attribute \src "ls180.v:897.5-897.37" - process $proc$ls180.v:897$3227 + attribute \src "ls180.v:896.5-896.37" + process $proc$ls180.v:896$3357 assign { } { } assign $0\main_uart_phy_source_last[0:0] 1'0 sync always update \main_uart_phy_source_last $0\main_uart_phy_source_last[0:0] sync init end - attribute \src "ls180.v:898.11-898.51" - process $proc$ls180.v:898$3228 + attribute \src "ls180.v:897.11-897.51" + process $proc$ls180.v:897$3358 assign { } { } assign $1\main_uart_phy_source_payload_data[7:0] 8'00000000 sync always sync init update \main_uart_phy_source_payload_data $1\main_uart_phy_source_payload_data[7:0] end - attribute \src "ls180.v:899.5-899.39" - process $proc$ls180.v:899$3229 + attribute \src "ls180.v:898.5-898.39" + process $proc$ls180.v:898$3359 assign { } { } assign $1\main_uart_phy_uart_clk_rxen[0:0] 1'0 sync always sync init update \main_uart_phy_uart_clk_rxen $1\main_uart_phy_uart_clk_rxen[0:0] end - attribute \src "ls180.v:900.12-900.54" - process $proc$ls180.v:900$3230 + attribute \src "ls180.v:899.12-899.54" + process $proc$ls180.v:899$3360 assign { } { } assign $1\main_uart_phy_phase_accumulator_rx[31:0] 0 sync always sync init update \main_uart_phy_phase_accumulator_rx $1\main_uart_phy_phase_accumulator_rx[31:0] end - attribute \src "ls180.v:902.5-902.30" - process $proc$ls180.v:902$3231 + attribute \src "ls180.v:901.5-901.30" + process $proc$ls180.v:901$3361 assign { } { } assign $1\main_uart_phy_rx_r[0:0] 1'0 sync always sync init update \main_uart_phy_rx_r $1\main_uart_phy_rx_r[0:0] end - attribute \src "ls180.v:903.11-903.38" - process $proc$ls180.v:903$3232 + attribute \src "ls180.v:902.11-902.38" + process $proc$ls180.v:902$3362 assign { } { } assign $1\main_uart_phy_rx_reg[7:0] 8'00000000 sync always sync init update \main_uart_phy_rx_reg $1\main_uart_phy_rx_reg[7:0] end - attribute \src "ls180.v:904.11-904.43" - process $proc$ls180.v:904$3233 + attribute \src "ls180.v:903.11-903.43" + process $proc$ls180.v:903$3363 assign { } { } assign $1\main_uart_phy_rx_bitcount[3:0] 4'0000 sync always sync init update \main_uart_phy_rx_bitcount $1\main_uart_phy_rx_bitcount[3:0] end - attribute \src "ls180.v:905.5-905.33" - process $proc$ls180.v:905$3234 + attribute \src "ls180.v:904.5-904.33" + process $proc$ls180.v:904$3364 assign { } { } assign $1\main_uart_phy_rx_busy[0:0] 1'0 sync always sync init update \main_uart_phy_rx_busy $1\main_uart_phy_rx_busy[0:0] end - attribute \src "ls180.v:916.5-916.32" - process $proc$ls180.v:916$3235 + attribute \src "ls180.v:91.11-91.56" + process $proc$ls180.v:91$3038 + assign { } { } + assign $1\main_libresocsim_libresoc_xics_icp_sel[3:0] 4'0000 + sync always + sync init + update \main_libresocsim_libresoc_xics_icp_sel $1\main_libresocsim_libresoc_xics_icp_sel[3:0] + end + attribute \src "ls180.v:915.5-915.32" + process $proc$ls180.v:915$3365 assign { } { } assign $1\main_uart_tx_pending[0:0] 1'0 sync always sync init update \main_uart_tx_pending $1\main_uart_tx_pending[0:0] end - attribute \src "ls180.v:918.5-918.30" - process $proc$ls180.v:918$3236 + attribute \src "ls180.v:917.5-917.30" + process $proc$ls180.v:917$3366 assign { } { } assign $1\main_uart_tx_clear[0:0] 1'0 sync always sync init update \main_uart_tx_clear $1\main_uart_tx_clear[0:0] end - attribute \src "ls180.v:919.5-919.36" - process $proc$ls180.v:919$3237 + attribute \src "ls180.v:918.5-918.36" + process $proc$ls180.v:918$3367 assign { } { } assign $1\main_uart_tx_old_trigger[0:0] 1'0 sync always sync init update \main_uart_tx_old_trigger $1\main_uart_tx_old_trigger[0:0] end - attribute \src "ls180.v:921.5-921.32" - process $proc$ls180.v:921$3238 + attribute \src "ls180.v:92.5-92.50" + process $proc$ls180.v:92$3039 + assign { } { } + assign $1\main_libresocsim_libresoc_xics_icp_cyc[0:0] 1'0 + sync always + sync init + update \main_libresocsim_libresoc_xics_icp_cyc $1\main_libresocsim_libresoc_xics_icp_cyc[0:0] + end + attribute \src "ls180.v:920.5-920.32" + process $proc$ls180.v:920$3368 assign { } { } assign $1\main_uart_rx_pending[0:0] 1'0 sync always sync init update \main_uart_rx_pending $1\main_uart_rx_pending[0:0] end - attribute \src "ls180.v:923.5-923.30" - process $proc$ls180.v:923$3239 + attribute \src "ls180.v:922.5-922.30" + process $proc$ls180.v:922$3369 assign { } { } assign $1\main_uart_rx_clear[0:0] 1'0 sync always sync init update \main_uart_rx_clear $1\main_uart_rx_clear[0:0] end - attribute \src "ls180.v:924.5-924.36" - process $proc$ls180.v:924$3240 + attribute \src "ls180.v:923.5-923.36" + process $proc$ls180.v:923$3370 assign { } { } assign $1\main_uart_rx_old_trigger[0:0] 1'0 sync always sync init update \main_uart_rx_old_trigger $1\main_uart_rx_old_trigger[0:0] end - attribute \src "ls180.v:928.11-928.49" - process $proc$ls180.v:928$3241 + attribute \src "ls180.v:927.11-927.49" + process $proc$ls180.v:927$3371 assign { } { } assign $1\main_uart_eventmanager_status_w[1:0] 2'00 sync always sync init update \main_uart_eventmanager_status_w $1\main_uart_eventmanager_status_w[1:0] end - attribute \src "ls180.v:932.11-932.50" - process $proc$ls180.v:932$3242 + attribute \src "ls180.v:93.5-93.50" + process $proc$ls180.v:93$3040 + assign { } { } + assign $1\main_libresocsim_libresoc_xics_icp_stb[0:0] 1'0 + sync always + sync init + update \main_libresocsim_libresoc_xics_icp_stb $1\main_libresocsim_libresoc_xics_icp_stb[0:0] + end + attribute \src "ls180.v:931.11-931.50" + process $proc$ls180.v:931$3372 assign { } { } assign $1\main_uart_eventmanager_pending_w[1:0] 2'00 sync always sync init update \main_uart_eventmanager_pending_w $1\main_uart_eventmanager_pending_w[1:0] end - attribute \src "ls180.v:933.11-933.48" - process $proc$ls180.v:933$3243 + attribute \src "ls180.v:932.11-932.48" + process $proc$ls180.v:932$3373 assign { } { } assign $1\main_uart_eventmanager_storage[1:0] 2'00 sync always sync init update \main_uart_eventmanager_storage $1\main_uart_eventmanager_storage[1:0] end - attribute \src "ls180.v:934.5-934.37" - process $proc$ls180.v:934$3244 + attribute \src "ls180.v:933.5-933.37" + process $proc$ls180.v:933$3374 assign { } { } assign $1\main_uart_eventmanager_re[0:0] 1'0 sync always sync init update \main_uart_eventmanager_re $1\main_uart_eventmanager_re[0:0] end - attribute \src "ls180.v:951.5-951.40" - process $proc$ls180.v:951$3245 + attribute \src "ls180.v:95.5-95.49" + process $proc$ls180.v:95$3041 + assign { } { } + assign $1\main_libresocsim_libresoc_xics_icp_we[0:0] 1'0 + sync always + sync init + update \main_libresocsim_libresoc_xics_icp_we $1\main_libresocsim_libresoc_xics_icp_we[0:0] + end + attribute \src "ls180.v:950.5-950.40" + process $proc$ls180.v:950$3375 assign { } { } assign $0\main_uart_tx_fifo_sink_first[0:0] 1'0 sync always update \main_uart_tx_fifo_sink_first $0\main_uart_tx_fifo_sink_first[0:0] sync init end - attribute \src "ls180.v:952.5-952.39" - process $proc$ls180.v:952$3246 + attribute \src "ls180.v:951.5-951.39" + process $proc$ls180.v:951$3376 assign { } { } assign $0\main_uart_tx_fifo_sink_last[0:0] 1'0 sync always update \main_uart_tx_fifo_sink_last $0\main_uart_tx_fifo_sink_last[0:0] sync init end - attribute \src "ls180.v:960.5-960.38" - process $proc$ls180.v:960$3247 + attribute \src "ls180.v:959.5-959.38" + process $proc$ls180.v:959$3377 assign { } { } assign $1\main_uart_tx_fifo_readable[0:0] 1'0 sync always sync init update \main_uart_tx_fifo_readable $1\main_uart_tx_fifo_readable[0:0] end - attribute \src "ls180.v:967.11-967.42" - process $proc$ls180.v:967$3248 + attribute \src "ls180.v:966.11-966.42" + process $proc$ls180.v:966$3378 assign { } { } assign $1\main_uart_tx_fifo_level0[4:0] 5'00000 sync always sync init update \main_uart_tx_fifo_level0 $1\main_uart_tx_fifo_level0[4:0] end - attribute \src "ls180.v:968.5-968.37" - process $proc$ls180.v:968$3249 + attribute \src "ls180.v:967.5-967.37" + process $proc$ls180.v:967$3379 assign { } { } assign $0\main_uart_tx_fifo_replace[0:0] 1'0 sync always update \main_uart_tx_fifo_replace $0\main_uart_tx_fifo_replace[0:0] sync init end - attribute \src "ls180.v:969.11-969.43" - process $proc$ls180.v:969$3250 + attribute \src "ls180.v:968.11-968.43" + process $proc$ls180.v:968$3380 assign { } { } assign $1\main_uart_tx_fifo_produce[3:0] 4'0000 sync always sync init update \main_uart_tx_fifo_produce $1\main_uart_tx_fifo_produce[3:0] end - attribute \src "ls180.v:970.11-970.43" - process $proc$ls180.v:970$3251 + attribute \src "ls180.v:969.11-969.43" + process $proc$ls180.v:969$3381 assign { } { } assign $1\main_uart_tx_fifo_consume[3:0] 4'0000 sync always sync init update \main_uart_tx_fifo_consume $1\main_uart_tx_fifo_consume[3:0] end - attribute \src "ls180.v:971.11-971.46" - process $proc$ls180.v:971$3252 + attribute \src "ls180.v:97.12-97.58" + process $proc$ls180.v:97$3042 + assign { } { } + assign $1\main_libresocsim_libresoc_xics_ics_adr[29:0] 30'000000000000000000000000000000 + sync always + sync init + update \main_libresocsim_libresoc_xics_ics_adr $1\main_libresocsim_libresoc_xics_ics_adr[29:0] + end + attribute \src "ls180.v:970.11-970.46" + process $proc$ls180.v:970$3382 assign { } { } assign $1\main_uart_tx_fifo_wrport_adr[3:0] 4'0000 sync always sync init update \main_uart_tx_fifo_wrport_adr $1\main_uart_tx_fifo_wrport_adr[3:0] end - attribute \src "ls180.v:997.5-997.38" - process $proc$ls180.v:997$3253 + attribute \src "ls180.v:98.12-98.60" + process $proc$ls180.v:98$3043 + assign { } { } + assign $1\main_libresocsim_libresoc_xics_ics_dat_w[31:0] 0 + sync always + sync init + update \main_libresocsim_libresoc_xics_ics_dat_w $1\main_libresocsim_libresoc_xics_ics_dat_w[31:0] + end + attribute \src "ls180.v:996.5-996.38" + process $proc$ls180.v:996$3383 assign { } { } assign $1\main_uart_rx_fifo_readable[0:0] 1'0 sync always @@ -282593,29 +284102,29 @@ module \ls180 connect \main_sdcore_sink_sink_last \main_sdmem2block_source_source_last0 connect \main_sdcore_sink_sink_payload_data \main_sdmem2block_source_source_payload_data0 connect \main_libresocsim_bus_error \builder_error - connect \main_libresocsim_converter0_reset $not$ls180.v:2818$26_Y - connect \main_libresocsim_libresoc_ibus_dat_r { \main_libresocsim_interface0_converted_interface_dat_r \main_libresocsim_converter0_dat_r [63:32] } - connect \main_libresocsim_converter1_reset $not$ls180.v:2878$37_Y - connect \main_libresocsim_libresoc_dbus_dat_r { \main_libresocsim_interface1_converted_interface_dat_r \main_libresocsim_converter1_dat_r [63:32] } - connect \main_libresocsim_converter2_reset $not$ls180.v:2938$48_Y - connect \main_libresocsim_libresoc_jtag_wb_dat_r { \main_libresocsim_interface2_converted_interface_dat_r \main_libresocsim_converter2_dat_r [63:32] } + connect \main_converter0_reset $not$ls180.v:2831$42_Y + connect \main_interface0_converted_interface_dat_r { \main_libresocsim_libresoc_xics_icp_dat_r \main_converter0_dat_r [63:32] } + connect \main_converter1_reset $not$ls180.v:2891$53_Y + connect \main_interface1_converted_interface_dat_r { \main_libresocsim_libresoc_xics_ics_dat_r \main_converter1_dat_r [63:32] } + connect \main_socbushandler_reset $not$ls180.v:2951$64_Y + connect \main_socbushandler_converted_interface_dat_r { \main_wb_sdram_dat_r \main_socbushandler_dat_r [63:32] } connect \main_libresocsim_reset \main_libresocsim_reset_re connect \main_libresocsim_bus_errors_status \main_libresocsim_bus_errors - connect \main_libresocsim_adr \main_libresocsim_ram_bus_adr [6:0] + connect \main_libresocsim_adr \main_libresocsim_ram_bus_adr [5:0] connect \main_libresocsim_ram_bus_dat_r \main_libresocsim_dat_r connect \main_libresocsim_dat_w \main_libresocsim_ram_bus_dat_w - connect \main_libresocsim_zero_trigger $ne$ls180.v:3010$72_Y + connect \main_libresocsim_zero_trigger $ne$ls180.v:3027$100_Y connect \main_libresocsim_eventmanager_status_w \main_libresocsim_zero_status connect \main_libresocsim_eventmanager_pending_w \main_libresocsim_zero_pending - connect \main_libresocsim_irq $and$ls180.v:3019$75_Y + connect \main_libresocsim_irq $and$ls180.v:3036$103_Y connect \main_libresocsim_zero_status \main_libresocsim_zero_trigger - connect \main_sram0_adr \main_interface0_ram_bus_adr [6:0] + connect \main_sram0_adr \main_interface0_ram_bus_adr [5:0] connect \main_interface0_ram_bus_dat_r \main_sram0_dat_r connect \main_sram0_dat_w \main_interface0_ram_bus_dat_w - connect \main_sram1_adr \main_interface1_ram_bus_adr [6:0] + connect \main_sram1_adr \main_interface1_ram_bus_adr [5:0] connect \main_interface1_ram_bus_dat_r \main_sram1_dat_r connect \main_sram1_dat_w \main_interface1_ram_bus_dat_w - connect \main_sram2_adr \main_interface2_ram_bus_adr [6:0] + connect \main_sram2_adr \main_interface2_ram_bus_adr [5:0] connect \main_interface2_ram_bus_dat_r \main_sram2_dat_r connect \main_sram2_dat_w \main_interface2_ram_bus_dat_w connect \sys_clk_1 \sys_clk @@ -282658,8 +284167,8 @@ module \ls180 connect \main_sdram_inti_p0_reset_n \main_sdram_reset_n connect \main_sdram_inti_p0_address \main_sdram_address_storage connect \main_sdram_inti_p0_bank \main_sdram_baddress_storage - connect \main_sdram_inti_p0_wrdata_en $and$ls180.v:3163$121_Y - connect \main_sdram_inti_p0_rddata_en $and$ls180.v:3164$122_Y + connect \main_sdram_inti_p0_wrdata_en $and$ls180.v:3192$185_Y + connect \main_sdram_inti_p0_rddata_en $and$ls180.v:3193$186_Y connect \main_sdram_inti_p0_wrdata \main_sdram_wrdata_storage connect \main_sdram_inti_p0_wrdata_mask 2'00 connect \main_sdram_bankmachine0_req_valid \main_sdram_interface_bank0_valid @@ -282690,14 +284199,14 @@ module \ls180 connect \main_sdram_interface_bank3_lock \main_sdram_bankmachine3_req_lock connect \main_sdram_interface_bank3_wdata_ready \main_sdram_bankmachine3_req_wdata_ready connect \main_sdram_interface_bank3_rdata_valid \main_sdram_bankmachine3_req_rdata_valid - connect \main_sdram_timer_wait $not$ls180.v:3195$123_Y + connect \main_sdram_timer_wait $not$ls180.v:3224$187_Y connect \main_sdram_postponer_req_i \main_sdram_timer_done0 connect \main_sdram_wants_refresh \main_sdram_postponer_req_o - connect \main_sdram_timer_done1 $eq$ls180.v:3198$124_Y + connect \main_sdram_timer_done1 $eq$ls180.v:3227$188_Y connect \main_sdram_timer_done0 \main_sdram_timer_done1 connect \main_sdram_timer_count0 \main_sdram_timer_count1 - connect \main_sdram_sequencer_start1 $or$ls180.v:3201$126_Y - connect \main_sdram_sequencer_done0 $and$ls180.v:3202$128_Y + connect \main_sdram_sequencer_start1 $or$ls180.v:3230$190_Y + connect \main_sdram_sequencer_done0 $and$ls180.v:3231$192_Y connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine0_req_valid connect \main_sdram_bankmachine0_req_ready \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine0_req_we @@ -282708,13 +284217,13 @@ module \ls180 connect \main_sdram_bankmachine0_cmd_buffer_sink_last \main_sdram_bankmachine0_cmd_buffer_lookahead_source_last connect \main_sdram_bankmachine0_cmd_buffer_sink_payload_we \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we connect \main_sdram_bankmachine0_cmd_buffer_sink_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr - connect \main_sdram_bankmachine0_cmd_buffer_source_ready $or$ls180.v:3244$130_Y - connect \main_sdram_bankmachine0_req_lock $or$ls180.v:3245$131_Y - connect \main_sdram_bankmachine0_row_hit $eq$ls180.v:3246$132_Y + connect \main_sdram_bankmachine0_cmd_buffer_source_ready $or$ls180.v:3273$194_Y + connect \main_sdram_bankmachine0_req_lock $or$ls180.v:3274$195_Y + connect \main_sdram_bankmachine0_row_hit $eq$ls180.v:3275$196_Y connect \main_sdram_bankmachine0_cmd_payload_ba 2'00 - connect \main_sdram_bankmachine0_twtpcon_valid $and$ls180.v:3256$137_Y - connect \main_sdram_bankmachine0_trccon_valid $and$ls180.v:3257$139_Y - connect \main_sdram_bankmachine0_trascon_valid $and$ls180.v:3258$141_Y + connect \main_sdram_bankmachine0_twtpcon_valid $and$ls180.v:3285$201_Y + connect \main_sdram_bankmachine0_trccon_valid $and$ls180.v:3286$203_Y + connect \main_sdram_bankmachine0_trascon_valid $and$ls180.v:3287$205_Y connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din { \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we } connect { \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable @@ -282730,13 +284239,13 @@ module \ls180 connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re \main_sdram_bankmachine0_cmd_buffer_lookahead_source_ready connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we $and$ls180.v:3290$149_Y - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read $and$ls180.v:3291$150_Y + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we $and$ls180.v:3319$213_Y + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read $and$ls180.v:3320$214_Y connect \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine0_cmd_buffer_lookahead_consume connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable $ne$ls180.v:3294$151_Y - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable $ne$ls180.v:3295$152_Y - connect \main_sdram_bankmachine0_cmd_buffer_sink_ready $or$ls180.v:3296$154_Y + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable $ne$ls180.v:3323$215_Y + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable $ne$ls180.v:3324$216_Y + connect \main_sdram_bankmachine0_cmd_buffer_sink_ready $or$ls180.v:3325$218_Y connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine1_req_valid connect \main_sdram_bankmachine1_req_ready \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine1_req_we @@ -282747,13 +284256,13 @@ module \ls180 connect \main_sdram_bankmachine1_cmd_buffer_sink_last \main_sdram_bankmachine1_cmd_buffer_lookahead_source_last connect \main_sdram_bankmachine1_cmd_buffer_sink_payload_we \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we connect \main_sdram_bankmachine1_cmd_buffer_sink_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr - connect \main_sdram_bankmachine1_cmd_buffer_source_ready $or$ls180.v:3401$160_Y - connect \main_sdram_bankmachine1_req_lock $or$ls180.v:3402$161_Y - connect \main_sdram_bankmachine1_row_hit $eq$ls180.v:3403$162_Y + connect \main_sdram_bankmachine1_cmd_buffer_source_ready $or$ls180.v:3430$224_Y + connect \main_sdram_bankmachine1_req_lock $or$ls180.v:3431$225_Y + connect \main_sdram_bankmachine1_row_hit $eq$ls180.v:3432$226_Y connect \main_sdram_bankmachine1_cmd_payload_ba 2'01 - connect \main_sdram_bankmachine1_twtpcon_valid $and$ls180.v:3413$167_Y - connect \main_sdram_bankmachine1_trccon_valid $and$ls180.v:3414$169_Y - connect \main_sdram_bankmachine1_trascon_valid $and$ls180.v:3415$171_Y + connect \main_sdram_bankmachine1_twtpcon_valid $and$ls180.v:3442$231_Y + connect \main_sdram_bankmachine1_trccon_valid $and$ls180.v:3443$233_Y + connect \main_sdram_bankmachine1_trascon_valid $and$ls180.v:3444$235_Y connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din { \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we } connect { \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable @@ -282769,13 +284278,13 @@ module \ls180 connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re \main_sdram_bankmachine1_cmd_buffer_lookahead_source_ready connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we $and$ls180.v:3447$179_Y - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read $and$ls180.v:3448$180_Y + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we $and$ls180.v:3476$243_Y + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read $and$ls180.v:3477$244_Y connect \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine1_cmd_buffer_lookahead_consume connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable $ne$ls180.v:3451$181_Y - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable $ne$ls180.v:3452$182_Y - connect \main_sdram_bankmachine1_cmd_buffer_sink_ready $or$ls180.v:3453$184_Y + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable $ne$ls180.v:3480$245_Y + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable $ne$ls180.v:3481$246_Y + connect \main_sdram_bankmachine1_cmd_buffer_sink_ready $or$ls180.v:3482$248_Y connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine2_req_valid connect \main_sdram_bankmachine2_req_ready \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine2_req_we @@ -282786,13 +284295,13 @@ module \ls180 connect \main_sdram_bankmachine2_cmd_buffer_sink_last \main_sdram_bankmachine2_cmd_buffer_lookahead_source_last connect \main_sdram_bankmachine2_cmd_buffer_sink_payload_we \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we connect \main_sdram_bankmachine2_cmd_buffer_sink_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr - connect \main_sdram_bankmachine2_cmd_buffer_source_ready $or$ls180.v:3558$190_Y - connect \main_sdram_bankmachine2_req_lock $or$ls180.v:3559$191_Y - connect \main_sdram_bankmachine2_row_hit $eq$ls180.v:3560$192_Y + connect \main_sdram_bankmachine2_cmd_buffer_source_ready $or$ls180.v:3587$254_Y + connect \main_sdram_bankmachine2_req_lock $or$ls180.v:3588$255_Y + connect \main_sdram_bankmachine2_row_hit $eq$ls180.v:3589$256_Y connect \main_sdram_bankmachine2_cmd_payload_ba 2'10 - connect \main_sdram_bankmachine2_twtpcon_valid $and$ls180.v:3570$197_Y - connect \main_sdram_bankmachine2_trccon_valid $and$ls180.v:3571$199_Y - connect \main_sdram_bankmachine2_trascon_valid $and$ls180.v:3572$201_Y + connect \main_sdram_bankmachine2_twtpcon_valid $and$ls180.v:3599$261_Y + connect \main_sdram_bankmachine2_trccon_valid $and$ls180.v:3600$263_Y + connect \main_sdram_bankmachine2_trascon_valid $and$ls180.v:3601$265_Y connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din { \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we } connect { \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable @@ -282808,13 +284317,13 @@ module \ls180 connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re \main_sdram_bankmachine2_cmd_buffer_lookahead_source_ready connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we $and$ls180.v:3604$209_Y - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read $and$ls180.v:3605$210_Y + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we $and$ls180.v:3633$273_Y + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read $and$ls180.v:3634$274_Y connect \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine2_cmd_buffer_lookahead_consume connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable $ne$ls180.v:3608$211_Y - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable $ne$ls180.v:3609$212_Y - connect \main_sdram_bankmachine2_cmd_buffer_sink_ready $or$ls180.v:3610$214_Y + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable $ne$ls180.v:3637$275_Y + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable $ne$ls180.v:3638$276_Y + connect \main_sdram_bankmachine2_cmd_buffer_sink_ready $or$ls180.v:3639$278_Y connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine3_req_valid connect \main_sdram_bankmachine3_req_ready \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine3_req_we @@ -282825,13 +284334,13 @@ module \ls180 connect \main_sdram_bankmachine3_cmd_buffer_sink_last \main_sdram_bankmachine3_cmd_buffer_lookahead_source_last connect \main_sdram_bankmachine3_cmd_buffer_sink_payload_we \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we connect \main_sdram_bankmachine3_cmd_buffer_sink_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr - connect \main_sdram_bankmachine3_cmd_buffer_source_ready $or$ls180.v:3715$220_Y - connect \main_sdram_bankmachine3_req_lock $or$ls180.v:3716$221_Y - connect \main_sdram_bankmachine3_row_hit $eq$ls180.v:3717$222_Y + connect \main_sdram_bankmachine3_cmd_buffer_source_ready $or$ls180.v:3744$284_Y + connect \main_sdram_bankmachine3_req_lock $or$ls180.v:3745$285_Y + connect \main_sdram_bankmachine3_row_hit $eq$ls180.v:3746$286_Y connect \main_sdram_bankmachine3_cmd_payload_ba 2'11 - connect \main_sdram_bankmachine3_twtpcon_valid $and$ls180.v:3727$227_Y - connect \main_sdram_bankmachine3_trccon_valid $and$ls180.v:3728$229_Y - connect \main_sdram_bankmachine3_trascon_valid $and$ls180.v:3729$231_Y + connect \main_sdram_bankmachine3_twtpcon_valid $and$ls180.v:3756$291_Y + connect \main_sdram_bankmachine3_trccon_valid $and$ls180.v:3757$293_Y + connect \main_sdram_bankmachine3_trascon_valid $and$ls180.v:3758$295_Y connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din { \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we } connect { \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable @@ -282847,32 +284356,32 @@ module \ls180 connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re \main_sdram_bankmachine3_cmd_buffer_lookahead_source_ready connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we $and$ls180.v:3761$239_Y - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read $and$ls180.v:3762$240_Y + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we $and$ls180.v:3790$303_Y + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read $and$ls180.v:3791$304_Y connect \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine3_cmd_buffer_lookahead_consume connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable $ne$ls180.v:3765$241_Y - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable $ne$ls180.v:3766$242_Y - connect \main_sdram_bankmachine3_cmd_buffer_sink_ready $or$ls180.v:3767$244_Y + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable $ne$ls180.v:3794$305_Y + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable $ne$ls180.v:3795$306_Y + connect \main_sdram_bankmachine3_cmd_buffer_sink_ready $or$ls180.v:3796$308_Y connect \main_sdram_choose_req_want_cmds 1'1 - connect \main_sdram_trrdcon_valid $and$ls180.v:3863$255_Y - connect \main_sdram_tfawcon_valid $and$ls180.v:3864$261_Y - connect \main_sdram_ras_allowed $and$ls180.v:3865$262_Y - connect \main_sdram_tccdcon_valid $and$ls180.v:3866$265_Y + connect \main_sdram_trrdcon_valid $and$ls180.v:3892$319_Y + connect \main_sdram_tfawcon_valid $and$ls180.v:3893$325_Y + connect \main_sdram_ras_allowed $and$ls180.v:3894$326_Y + connect \main_sdram_tccdcon_valid $and$ls180.v:3895$329_Y connect \main_sdram_cas_allowed \main_sdram_tccdcon_ready - connect \main_sdram_twtrcon_valid $and$ls180.v:3868$267_Y - connect \main_sdram_read_available $or$ls180.v:3869$274_Y - connect \main_sdram_write_available $or$ls180.v:3870$281_Y - connect \main_sdram_max_time0 $eq$ls180.v:3871$282_Y - connect \main_sdram_max_time1 $eq$ls180.v:3872$283_Y + connect \main_sdram_twtrcon_valid $and$ls180.v:3897$331_Y + connect \main_sdram_read_available $or$ls180.v:3898$338_Y + connect \main_sdram_write_available $or$ls180.v:3899$345_Y + connect \main_sdram_max_time0 $eq$ls180.v:3900$346_Y + connect \main_sdram_max_time1 $eq$ls180.v:3901$347_Y connect \main_sdram_bankmachine0_refresh_req \main_sdram_cmd_valid connect \main_sdram_bankmachine1_refresh_req \main_sdram_cmd_valid connect \main_sdram_bankmachine2_refresh_req \main_sdram_cmd_valid connect \main_sdram_bankmachine3_refresh_req \main_sdram_cmd_valid - connect \main_sdram_go_to_refresh $and$ls180.v:3877$286_Y + connect \main_sdram_go_to_refresh $and$ls180.v:3906$350_Y connect \main_sdram_interface_rdata \main_sdram_dfi_p0_rddata connect \main_sdram_dfi_p0_wrdata \main_sdram_interface_wdata - connect \main_sdram_dfi_p0_wrdata_mask $not$ls180.v:3880$287_Y + connect \main_sdram_dfi_p0_wrdata_mask $not$ls180.v:3909$351_Y connect \main_sdram_choose_cmd_request \main_sdram_choose_cmd_valids connect \main_sdram_choose_cmd_cmd_valid \builder_comb_rhs_array_muxed0 connect \main_sdram_choose_cmd_cmd_payload_a \builder_comb_rhs_array_muxed1 @@ -282880,7 +284389,7 @@ module \ls180 connect \main_sdram_choose_cmd_cmd_payload_is_read \builder_comb_rhs_array_muxed3 connect \main_sdram_choose_cmd_cmd_payload_is_write \builder_comb_rhs_array_muxed4 connect \main_sdram_choose_cmd_cmd_payload_is_cmd \builder_comb_rhs_array_muxed5 - connect \main_sdram_choose_cmd_ce $or$ls180.v:3913$345_Y + connect \main_sdram_choose_cmd_ce $or$ls180.v:3942$409_Y connect \main_sdram_choose_req_request \main_sdram_choose_req_valids connect \main_sdram_choose_req_cmd_valid \builder_comb_rhs_array_muxed6 connect \main_sdram_choose_req_cmd_payload_a \builder_comb_rhs_array_muxed7 @@ -282888,31 +284397,31 @@ module \ls180 connect \main_sdram_choose_req_cmd_payload_is_read \builder_comb_rhs_array_muxed9 connect \main_sdram_choose_req_cmd_payload_is_write \builder_comb_rhs_array_muxed10 connect \main_sdram_choose_req_cmd_payload_is_cmd \builder_comb_rhs_array_muxed11 - connect \main_sdram_choose_req_ce $or$ls180.v:3982$431_Y + connect \main_sdram_choose_req_ce $or$ls180.v:4011$495_Y connect \main_sdram_dfi_p0_reset_n 1'1 connect \main_sdram_dfi_p0_cke \main_sdram_steerer0 connect \main_sdram_dfi_p0_odt \main_sdram_steerer1 - connect \builder_roundrobin0_request $and$ls180.v:4059$463_Y - connect \builder_roundrobin0_ce $and$ls180.v:4060$466_Y + connect \builder_roundrobin0_request $and$ls180.v:4088$527_Y + connect \builder_roundrobin0_ce $and$ls180.v:4089$530_Y connect \main_sdram_interface_bank0_addr \builder_comb_rhs_array_muxed12 connect \main_sdram_interface_bank0_we \builder_comb_rhs_array_muxed13 connect \main_sdram_interface_bank0_valid \builder_comb_rhs_array_muxed14 - connect \builder_roundrobin1_request $and$ls180.v:4064$479_Y - connect \builder_roundrobin1_ce $and$ls180.v:4065$482_Y + connect \builder_roundrobin1_request $and$ls180.v:4093$543_Y + connect \builder_roundrobin1_ce $and$ls180.v:4094$546_Y connect \main_sdram_interface_bank1_addr \builder_comb_rhs_array_muxed15 connect \main_sdram_interface_bank1_we \builder_comb_rhs_array_muxed16 connect \main_sdram_interface_bank1_valid \builder_comb_rhs_array_muxed17 - connect \builder_roundrobin2_request $and$ls180.v:4069$495_Y - connect \builder_roundrobin2_ce $and$ls180.v:4070$498_Y + connect \builder_roundrobin2_request $and$ls180.v:4098$559_Y + connect \builder_roundrobin2_ce $and$ls180.v:4099$562_Y connect \main_sdram_interface_bank2_addr \builder_comb_rhs_array_muxed18 connect \main_sdram_interface_bank2_we \builder_comb_rhs_array_muxed19 connect \main_sdram_interface_bank2_valid \builder_comb_rhs_array_muxed20 - connect \builder_roundrobin3_request $and$ls180.v:4074$511_Y - connect \builder_roundrobin3_ce $and$ls180.v:4075$514_Y + connect \builder_roundrobin3_request $and$ls180.v:4103$575_Y + connect \builder_roundrobin3_ce $and$ls180.v:4104$578_Y connect \main_sdram_interface_bank3_addr \builder_comb_rhs_array_muxed21 connect \main_sdram_interface_bank3_we \builder_comb_rhs_array_muxed22 connect \main_sdram_interface_bank3_valid \builder_comb_rhs_array_muxed23 - connect \main_port_cmd_ready $or$ls180.v:4079$578_Y + connect \main_port_cmd_ready $or$ls180.v:4108$642_Y connect \main_port_wdata_ready \builder_new_master_wdata_ready connect \main_port_rdata_valid \builder_new_master_rdata_valid3 connect \main_port_rdata_payload_data \main_sdram_interface_rdata @@ -282920,22 +284429,22 @@ module \ls180 connect \builder_roundrobin1_grant 1'0 connect \builder_roundrobin2_grant 1'0 connect \builder_roundrobin3_grant 1'0 - connect \main_converter_reset $not$ls180.v:4101$580_Y + connect \main_converter_reset $not$ls180.v:4130$644_Y connect \main_wb_sdram_dat_r { \main_litedram_wb_dat_r \main_converter_dat_r [31:16] } - connect \main_port_cmd_payload_addr $sub$ls180.v:4161$591_Y [23:0] + connect \main_port_cmd_payload_addr $sub$ls180.v:4190$655_Y [23:0] connect \main_port_cmd_payload_we \main_litedram_wb_we connect \main_port_wdata_payload_data \main_litedram_wb_dat_w connect \main_port_wdata_payload_we \main_litedram_wb_sel connect \main_litedram_wb_dat_r \main_port_rdata_payload_data - connect \main_port_flush $not$ls180.v:4166$592_Y - connect \main_port_cmd_last $not$ls180.v:4167$593_Y - connect \main_port_cmd_valid $and$ls180.v:4168$596_Y - connect \main_port_wdata_valid $and$ls180.v:4169$600_Y - connect \main_port_rdata_ready $and$ls180.v:4170$603_Y - connect \main_litedram_wb_ack $and$ls180.v:4171$608_Y - connect \main_ack_cmd $or$ls180.v:4172$610_Y - connect \main_ack_wdata $or$ls180.v:4173$612_Y - connect \main_ack_rdata $and$ls180.v:4174$613_Y + connect \main_port_flush $not$ls180.v:4195$656_Y + connect \main_port_cmd_last $not$ls180.v:4196$657_Y + connect \main_port_cmd_valid $and$ls180.v:4197$660_Y + connect \main_port_wdata_valid $and$ls180.v:4198$664_Y + connect \main_port_rdata_ready $and$ls180.v:4199$667_Y + connect \main_litedram_wb_ack $and$ls180.v:4200$672_Y + connect \main_ack_cmd $or$ls180.v:4201$674_Y + connect \main_ack_wdata $or$ls180.v:4202$676_Y + connect \main_ack_rdata $and$ls180.v:4203$677_Y connect \main_uart_uart_sink_valid \main_uart_phy_source_valid connect \main_uart_phy_source_ready \main_uart_uart_sink_ready connect \main_uart_uart_sink_first \main_uart_phy_source_first @@ -282948,25 +284457,25 @@ module \ls180 connect \main_uart_phy_sink_payload_data \main_uart_uart_source_payload_data connect \main_uart_tx_fifo_sink_valid \main_uart_rxtx_re connect \main_uart_tx_fifo_sink_payload_data \main_uart_rxtx_r - connect \main_uart_txfull_status $not$ls180.v:4187$614_Y - connect \main_uart_txempty_status $not$ls180.v:4188$615_Y + connect \main_uart_txfull_status $not$ls180.v:4216$678_Y + connect \main_uart_txempty_status $not$ls180.v:4217$679_Y connect \main_uart_uart_source_valid \main_uart_tx_fifo_source_valid connect \main_uart_tx_fifo_source_ready \main_uart_uart_source_ready connect \main_uart_uart_source_first \main_uart_tx_fifo_source_first connect \main_uart_uart_source_last \main_uart_tx_fifo_source_last connect \main_uart_uart_source_payload_data \main_uart_tx_fifo_source_payload_data - connect \main_uart_tx_trigger $not$ls180.v:4194$616_Y + connect \main_uart_tx_trigger $not$ls180.v:4223$680_Y connect \main_uart_rx_fifo_sink_valid \main_uart_uart_sink_valid connect \main_uart_uart_sink_ready \main_uart_rx_fifo_sink_ready connect \main_uart_rx_fifo_sink_first \main_uart_uart_sink_first connect \main_uart_rx_fifo_sink_last \main_uart_uart_sink_last connect \main_uart_rx_fifo_sink_payload_data \main_uart_uart_sink_payload_data - connect \main_uart_rxempty_status $not$ls180.v:4200$617_Y - connect \main_uart_rxfull_status $not$ls180.v:4201$618_Y + connect \main_uart_rxempty_status $not$ls180.v:4229$681_Y + connect \main_uart_rxfull_status $not$ls180.v:4230$682_Y connect \main_uart_rxtx_w \main_uart_rx_fifo_source_payload_data - connect \main_uart_rx_fifo_source_ready $or$ls180.v:4203$620_Y - connect \main_uart_rx_trigger $not$ls180.v:4204$621_Y - connect \main_uart_irq $or$ls180.v:4227$630_Y + connect \main_uart_rx_fifo_source_ready $or$ls180.v:4232$684_Y + connect \main_uart_rx_trigger $not$ls180.v:4233$685_Y + connect \main_uart_irq $or$ls180.v:4256$694_Y connect \main_uart_tx_status \main_uart_tx_trigger connect \main_uart_rx_status \main_uart_rx_trigger connect \main_uart_tx_fifo_syncfifo_din { \main_uart_tx_fifo_fifo_in_last \main_uart_tx_fifo_fifo_in_first \main_uart_tx_fifo_fifo_in_payload_data } @@ -282981,16 +284490,16 @@ module \ls180 connect \main_uart_tx_fifo_source_last \main_uart_tx_fifo_fifo_out_last connect \main_uart_tx_fifo_source_payload_data \main_uart_tx_fifo_fifo_out_payload_data connect \main_uart_tx_fifo_re \main_uart_tx_fifo_source_ready - connect \main_uart_tx_fifo_syncfifo_re $and$ls180.v:4242$633_Y - connect \main_uart_tx_fifo_level1 $add$ls180.v:4243$634_Y + connect \main_uart_tx_fifo_syncfifo_re $and$ls180.v:4271$697_Y + connect \main_uart_tx_fifo_level1 $add$ls180.v:4272$698_Y connect \main_uart_tx_fifo_wrport_dat_w \main_uart_tx_fifo_syncfifo_din - connect \main_uart_tx_fifo_wrport_we $and$ls180.v:4253$638_Y - connect \main_uart_tx_fifo_do_read $and$ls180.v:4254$639_Y + connect \main_uart_tx_fifo_wrport_we $and$ls180.v:4282$702_Y + connect \main_uart_tx_fifo_do_read $and$ls180.v:4283$703_Y connect \main_uart_tx_fifo_rdport_adr \main_uart_tx_fifo_consume connect \main_uart_tx_fifo_syncfifo_dout \main_uart_tx_fifo_rdport_dat_r connect \main_uart_tx_fifo_rdport_re \main_uart_tx_fifo_do_read - connect \main_uart_tx_fifo_syncfifo_writable $ne$ls180.v:4258$640_Y - connect \main_uart_tx_fifo_syncfifo_readable $ne$ls180.v:4259$641_Y + connect \main_uart_tx_fifo_syncfifo_writable $ne$ls180.v:4287$704_Y + connect \main_uart_tx_fifo_syncfifo_readable $ne$ls180.v:4288$705_Y connect \main_uart_rx_fifo_syncfifo_din { \main_uart_rx_fifo_fifo_in_last \main_uart_rx_fifo_fifo_in_first \main_uart_rx_fifo_fifo_in_payload_data } connect { \main_uart_rx_fifo_fifo_out_last \main_uart_rx_fifo_fifo_out_first \main_uart_rx_fifo_fifo_out_payload_data } \main_uart_rx_fifo_syncfifo_dout connect \main_uart_rx_fifo_sink_ready \main_uart_rx_fifo_syncfifo_writable @@ -283003,21 +284512,22 @@ module \ls180 connect \main_uart_rx_fifo_source_last \main_uart_rx_fifo_fifo_out_last connect \main_uart_rx_fifo_source_payload_data \main_uart_rx_fifo_fifo_out_payload_data connect \main_uart_rx_fifo_re \main_uart_rx_fifo_source_ready - connect \main_uart_rx_fifo_syncfifo_re $and$ls180.v:4272$644_Y - connect \main_uart_rx_fifo_level1 $add$ls180.v:4273$645_Y + connect \main_uart_rx_fifo_syncfifo_re $and$ls180.v:4301$708_Y + connect \main_uart_rx_fifo_level1 $add$ls180.v:4302$709_Y connect \main_uart_rx_fifo_wrport_dat_w \main_uart_rx_fifo_syncfifo_din - connect \main_uart_rx_fifo_wrport_we $and$ls180.v:4283$649_Y - connect \main_uart_rx_fifo_do_read $and$ls180.v:4284$650_Y + connect \main_uart_rx_fifo_wrport_we $and$ls180.v:4312$713_Y + connect \main_uart_rx_fifo_do_read $and$ls180.v:4313$714_Y connect \main_uart_rx_fifo_rdport_adr \main_uart_rx_fifo_consume connect \main_uart_rx_fifo_syncfifo_dout \main_uart_rx_fifo_rdport_dat_r connect \main_uart_rx_fifo_rdport_re \main_uart_rx_fifo_do_read - connect \main_uart_rx_fifo_syncfifo_writable $ne$ls180.v:4288$651_Y - connect \main_uart_rx_fifo_syncfifo_readable $ne$ls180.v:4289$652_Y - connect \main_gpio_pads_i \gpio_i - connect \gpio_o \main_gpio_pads_o - connect \gpio_oe \main_gpio_pads_oe - connect \main_gpio_pads_oe \main_gpio_oe_storage - connect \main_gpio_pads_o \main_gpio_out_storage + connect \main_uart_rx_fifo_syncfifo_writable $ne$ls180.v:4317$715_Y + connect \main_uart_rx_fifo_syncfifo_readable $ne$ls180.v:4318$716_Y + connect \main_gpiotristateasic0_pads_i \gpio_i + connect \main_gpiotristateasic0_pads_oe \main_gpiotristateasic0_oe_storage + connect \main_gpiotristateasic0_pads_o \main_gpiotristateasic0_out_storage + connect \main_gpiotristateasic1_pads_i \gpio_i + connect \main_gpiotristateasic1_pads_oe \main_gpiotristateasic1_oe_storage + connect \main_gpiotristateasic1_pads_o \main_gpiotristateasic1_out_storage connect \main_spimaster0_start \main_spimaster9_start connect \main_spimaster1_length \main_spimaster10_length connect \main_spimaster4_mosi \main_spimaster16_storage @@ -283025,8 +284535,8 @@ module \ls180 connect \main_spimaster18_status \main_spimaster5_miso connect \main_spimaster6_cs \main_spimaster21_storage connect \main_spimaster7_loopback \main_spimaster23_storage - connect \main_spimaster31_clk_rise $eq$ls180.v:4302$654_Y - connect \main_spimaster32_clk_fall $eq$ls180.v:4303$656_Y + connect \main_spimaster31_clk_rise $eq$ls180.v:4342$720_Y + connect \main_spimaster32_clk_fall $eq$ls180.v:4343$722_Y connect \main_spisdcard_start0 \main_spisdcard_start1 connect \main_spisdcard_length0 \main_spisdcard_length1 connect \main_spisdcard_mosi \main_spisdcard_mosi_storage @@ -283034,19 +284544,19 @@ module \ls180 connect \main_spisdcard_miso_status \main_spisdcard_miso connect \main_spisdcard_cs \main_spisdcard_cs_storage connect \main_spisdcard_loopback \main_spisdcard_loopback_storage - connect \main_spisdcard_clk_rise $eq$ls180.v:4360$662_Y - connect \main_spisdcard_clk_fall $eq$ls180.v:4361$664_Y + connect \main_spisdcard_clk_rise $eq$ls180.v:4400$728_Y + connect \main_spisdcard_clk_fall $eq$ls180.v:4401$730_Y connect \main_spisdcard_clk_divider0 \main_spimaster1_storage connect \i2c_scl \main_i2c_scl connect \i2c_sda_oe \main_i2c_oe connect \i2c_sda_o \main_i2c_sda0 connect \main_i2c_sda1 \i2c_sda_i connect \main_sdphy_status 1'0 - connect \main_sdphy_sdpads_clk $or$ls180.v:4417$672_Y - connect \main_sdphy_sdpads_cmd_oe $or$ls180.v:4418$676_Y - connect \main_sdphy_sdpads_cmd_o $or$ls180.v:4419$680_Y - connect \main_sdphy_sdpads_data_oe $or$ls180.v:4420$684_Y - connect \main_sdphy_sdpads_data_o $or$ls180.v:4421$688_Y + connect \main_sdphy_sdpads_clk $or$ls180.v:4457$738_Y + connect \main_sdphy_sdpads_cmd_oe $or$ls180.v:4458$742_Y + connect \main_sdphy_sdpads_cmd_o $or$ls180.v:4459$746_Y + connect \main_sdphy_sdpads_data_oe $or$ls180.v:4460$750_Y + connect \main_sdphy_sdpads_data_o $or$ls180.v:4461$754_Y connect \main_sdphy_init_pads_out_ready \main_sdphy_clocker_ce connect \main_sdphy_cmdw_pads_out_ready \main_sdphy_clocker_ce connect \main_sdphy_cmdr_pads_out_ready \main_sdphy_clocker_ce @@ -283067,8 +284577,8 @@ module \ls180 connect \main_sdphy_datar_pads_in_pads_in_valid \main_sdphy_clocker_ce connect \main_sdphy_datar_pads_in_pads_in_payload_cmd_i \main_sdphy_sdpads_cmd_i connect \main_sdphy_datar_pads_in_pads_in_payload_data_i \main_sdphy_sdpads_data_i - connect \main_sdphy_clocker_stop $or$ls180.v:4442$689_Y - connect \main_sdphy_clocker_ce $and$ls180.v:4472$692_Y + connect \main_sdphy_clocker_stop $or$ls180.v:4482$755_Y + connect \main_sdphy_clocker_ce $and$ls180.v:4512$758_Y connect \main_sdphy_cmdr_cmdr_pads_in_valid \main_sdphy_cmdr_pads_in_pads_in_valid connect \main_sdphy_cmdr_pads_in_pads_in_ready \main_sdphy_cmdr_cmdr_pads_in_ready connect \main_sdphy_cmdr_cmdr_pads_in_first \main_sdphy_cmdr_pads_in_pads_in_first @@ -283080,8 +284590,8 @@ module \ls180 connect \main_sdphy_cmdr_cmdr_pads_in_payload_data_i \main_sdphy_cmdr_pads_in_pads_in_payload_data_i connect \main_sdphy_cmdr_cmdr_pads_in_payload_data_o \main_sdphy_cmdr_pads_in_pads_in_payload_data_o connect \main_sdphy_cmdr_cmdr_pads_in_payload_data_oe \main_sdphy_cmdr_pads_in_pads_in_payload_data_oe - connect \main_sdphy_cmdr_cmdr_start $eq$ls180.v:4595$702_Y - connect \main_sdphy_cmdr_cmdr_converter_sink_valid $and$ls180.v:4596$704_Y + connect \main_sdphy_cmdr_cmdr_start $eq$ls180.v:4635$768_Y + connect \main_sdphy_cmdr_cmdr_converter_sink_valid $and$ls180.v:4636$770_Y connect \main_sdphy_cmdr_cmdr_converter_sink_payload_data \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_i connect \main_sdphy_cmdr_cmdr_buf_sink_valid \main_sdphy_cmdr_cmdr_source_source_valid1 connect \main_sdphy_cmdr_cmdr_source_source_ready1 \main_sdphy_cmdr_cmdr_buf_sink_ready @@ -283098,10 +284608,10 @@ module \ls180 connect \main_sdphy_cmdr_cmdr_source_source_first1 \main_sdphy_cmdr_cmdr_converter_source_first connect \main_sdphy_cmdr_cmdr_source_source_last1 \main_sdphy_cmdr_cmdr_converter_source_last connect \main_sdphy_cmdr_cmdr_source_source_payload_data1 \main_sdphy_cmdr_cmdr_converter_source_payload_data - connect \main_sdphy_cmdr_cmdr_converter_sink_ready $or$ls180.v:4613$706_Y + connect \main_sdphy_cmdr_cmdr_converter_sink_ready $or$ls180.v:4653$772_Y connect \main_sdphy_cmdr_cmdr_converter_source_valid \main_sdphy_cmdr_cmdr_converter_strobe_all - connect \main_sdphy_cmdr_cmdr_converter_load_part $and$ls180.v:4615$707_Y - connect \main_sdphy_cmdr_cmdr_buf_sink_ready $or$ls180.v:4616$709_Y + connect \main_sdphy_cmdr_cmdr_converter_load_part $and$ls180.v:4655$773_Y + connect \main_sdphy_cmdr_cmdr_buf_sink_ready $or$ls180.v:4656$775_Y connect \main_sdphy_dataw_crcr_pads_in_valid \main_sdphy_dataw_pads_in_pads_in_valid connect \main_sdphy_dataw_pads_in_pads_in_ready \main_sdphy_dataw_crcr_pads_in_ready connect \main_sdphy_dataw_crcr_pads_in_first \main_sdphy_dataw_pads_in_pads_in_first @@ -283113,8 +284623,8 @@ module \ls180 connect \main_sdphy_dataw_crcr_pads_in_payload_data_i \main_sdphy_dataw_pads_in_pads_in_payload_data_i connect \main_sdphy_dataw_crcr_pads_in_payload_data_o \main_sdphy_dataw_pads_in_pads_in_payload_data_o connect \main_sdphy_dataw_crcr_pads_in_payload_data_oe \main_sdphy_dataw_pads_in_pads_in_payload_data_oe - connect \main_sdphy_dataw_crcr_start $eq$ls180.v:4722$724_Y - connect \main_sdphy_dataw_crcr_converter_sink_valid $and$ls180.v:4723$725_Y + connect \main_sdphy_dataw_crcr_start $eq$ls180.v:4762$790_Y + connect \main_sdphy_dataw_crcr_converter_sink_valid $and$ls180.v:4763$791_Y connect \main_sdphy_dataw_crcr_converter_sink_payload_data \main_sdphy_dataw_crcr_pads_in_payload_data_i [0] connect \main_sdphy_dataw_crcr_buf_sink_valid \main_sdphy_dataw_crcr_source_source_valid1 connect \main_sdphy_dataw_crcr_source_source_ready1 \main_sdphy_dataw_crcr_buf_sink_ready @@ -283131,10 +284641,10 @@ module \ls180 connect \main_sdphy_dataw_crcr_source_source_first1 \main_sdphy_dataw_crcr_converter_source_first connect \main_sdphy_dataw_crcr_source_source_last1 \main_sdphy_dataw_crcr_converter_source_last connect \main_sdphy_dataw_crcr_source_source_payload_data1 \main_sdphy_dataw_crcr_converter_source_payload_data - connect \main_sdphy_dataw_crcr_converter_sink_ready $or$ls180.v:4740$727_Y + connect \main_sdphy_dataw_crcr_converter_sink_ready $or$ls180.v:4780$793_Y connect \main_sdphy_dataw_crcr_converter_source_valid \main_sdphy_dataw_crcr_converter_strobe_all - connect \main_sdphy_dataw_crcr_converter_load_part $and$ls180.v:4742$728_Y - connect \main_sdphy_dataw_crcr_buf_sink_ready $or$ls180.v:4743$730_Y + connect \main_sdphy_dataw_crcr_converter_load_part $and$ls180.v:4782$794_Y + connect \main_sdphy_dataw_crcr_buf_sink_ready $or$ls180.v:4783$796_Y connect \main_sdphy_datar_datar_pads_in_valid \main_sdphy_datar_pads_in_pads_in_valid connect \main_sdphy_datar_pads_in_pads_in_ready \main_sdphy_datar_datar_pads_in_ready connect \main_sdphy_datar_datar_pads_in_first \main_sdphy_datar_pads_in_pads_in_first @@ -283146,8 +284656,8 @@ module \ls180 connect \main_sdphy_datar_datar_pads_in_payload_data_i \main_sdphy_datar_pads_in_pads_in_payload_data_i connect \main_sdphy_datar_datar_pads_in_payload_data_o \main_sdphy_datar_pads_in_pads_in_payload_data_o connect \main_sdphy_datar_datar_pads_in_payload_data_oe \main_sdphy_datar_pads_in_pads_in_payload_data_oe - connect \main_sdphy_datar_datar_start $eq$ls180.v:4856$739_Y - connect \main_sdphy_datar_datar_converter_sink_valid $and$ls180.v:4857$740_Y + connect \main_sdphy_datar_datar_start $eq$ls180.v:4896$805_Y + connect \main_sdphy_datar_datar_converter_sink_valid $and$ls180.v:4897$806_Y connect \main_sdphy_datar_datar_converter_sink_payload_data \main_sdphy_datar_datar_pads_in_payload_data_i connect \main_sdphy_datar_datar_buf_sink_valid \main_sdphy_datar_datar_source_source_valid1 connect \main_sdphy_datar_datar_source_source_ready1 \main_sdphy_datar_datar_buf_sink_ready @@ -283164,10 +284674,10 @@ module \ls180 connect \main_sdphy_datar_datar_source_source_first1 \main_sdphy_datar_datar_converter_source_first connect \main_sdphy_datar_datar_source_source_last1 \main_sdphy_datar_datar_converter_source_last connect \main_sdphy_datar_datar_source_source_payload_data1 \main_sdphy_datar_datar_converter_source_payload_data - connect \main_sdphy_datar_datar_converter_sink_ready $or$ls180.v:4874$742_Y + connect \main_sdphy_datar_datar_converter_sink_ready $or$ls180.v:4914$808_Y connect \main_sdphy_datar_datar_converter_source_valid \main_sdphy_datar_datar_converter_strobe_all - connect \main_sdphy_datar_datar_converter_load_part $and$ls180.v:4876$743_Y - connect \main_sdphy_datar_datar_buf_sink_ready $or$ls180.v:4877$745_Y + connect \main_sdphy_datar_datar_converter_load_part $and$ls180.v:4916$809_Y + connect \main_sdphy_datar_datar_buf_sink_ready $or$ls180.v:4917$811_Y connect \main_sdcore_crc16_inserter_sink_valid \main_sdcore_sink_sink_valid connect \main_sdcore_sink_sink_ready \main_sdcore_crc16_inserter_sink_ready connect \main_sdcore_crc16_inserter_sink_first \main_sdcore_sink_sink_first @@ -283181,88 +284691,88 @@ module \ls180 connect \main_sdcore_cmd_type \main_sdcore_cmd_command_storage [1:0] connect \main_sdcore_data_type \main_sdcore_cmd_command_storage [6:5] connect \main_sdcore_cmd_event_status { 1'0 \main_sdcore_cmd_timeout \main_sdcore_cmd_error \main_sdcore_cmd_done } - connect \main_sdcore_data_event_status { $not$ls180.v:4993$760_Y \main_sdcore_data_timeout \main_sdcore_data_error \main_sdcore_data_done } + connect \main_sdcore_data_event_status { $not$ls180.v:5033$826_Y \main_sdcore_data_timeout \main_sdcore_data_error \main_sdcore_data_done } connect \main_sdcore_crc7_inserter_val { 2'01 \main_sdcore_cmd_command_storage [13:8] \main_sdcore_cmd_argument_storage } connect \main_sdcore_crc7_inserter_clr 1'1 connect \main_sdcore_crc7_inserter_enable 1'1 - connect \main_sdcore_crc7_inserter_crcreg1 { \main_sdcore_crc7_inserter_crcreg0 [5:3] $xor$ls180.v:4997$763_Y \main_sdcore_crc7_inserter_crcreg0 [1:0] $xor$ls180.v:4997$761_Y } - connect \main_sdcore_crc7_inserter_crcreg2 { \main_sdcore_crc7_inserter_crcreg1 [5:3] $xor$ls180.v:4998$766_Y \main_sdcore_crc7_inserter_crcreg1 [1:0] $xor$ls180.v:4998$764_Y } - connect \main_sdcore_crc7_inserter_crcreg3 { \main_sdcore_crc7_inserter_crcreg2 [5:3] $xor$ls180.v:4999$769_Y \main_sdcore_crc7_inserter_crcreg2 [1:0] $xor$ls180.v:4999$767_Y } - connect \main_sdcore_crc7_inserter_crcreg4 { \main_sdcore_crc7_inserter_crcreg3 [5:3] $xor$ls180.v:5000$772_Y \main_sdcore_crc7_inserter_crcreg3 [1:0] $xor$ls180.v:5000$770_Y } - connect \main_sdcore_crc7_inserter_crcreg5 { \main_sdcore_crc7_inserter_crcreg4 [5:3] $xor$ls180.v:5001$775_Y \main_sdcore_crc7_inserter_crcreg4 [1:0] $xor$ls180.v:5001$773_Y } - connect \main_sdcore_crc7_inserter_crcreg6 { \main_sdcore_crc7_inserter_crcreg5 [5:3] $xor$ls180.v:5002$778_Y \main_sdcore_crc7_inserter_crcreg5 [1:0] $xor$ls180.v:5002$776_Y } - connect \main_sdcore_crc7_inserter_crcreg7 { \main_sdcore_crc7_inserter_crcreg6 [5:3] $xor$ls180.v:5003$781_Y \main_sdcore_crc7_inserter_crcreg6 [1:0] $xor$ls180.v:5003$779_Y } - connect \main_sdcore_crc7_inserter_crcreg8 { \main_sdcore_crc7_inserter_crcreg7 [5:3] $xor$ls180.v:5004$784_Y \main_sdcore_crc7_inserter_crcreg7 [1:0] $xor$ls180.v:5004$782_Y } - connect \main_sdcore_crc7_inserter_crcreg9 { \main_sdcore_crc7_inserter_crcreg8 [5:3] $xor$ls180.v:5005$787_Y \main_sdcore_crc7_inserter_crcreg8 [1:0] $xor$ls180.v:5005$785_Y } - connect \main_sdcore_crc7_inserter_crcreg10 { \main_sdcore_crc7_inserter_crcreg9 [5:3] $xor$ls180.v:5006$790_Y \main_sdcore_crc7_inserter_crcreg9 [1:0] $xor$ls180.v:5006$788_Y } - connect \main_sdcore_crc7_inserter_crcreg11 { \main_sdcore_crc7_inserter_crcreg10 [5:3] $xor$ls180.v:5007$793_Y \main_sdcore_crc7_inserter_crcreg10 [1:0] $xor$ls180.v:5007$791_Y } - connect \main_sdcore_crc7_inserter_crcreg12 { \main_sdcore_crc7_inserter_crcreg11 [5:3] $xor$ls180.v:5008$796_Y \main_sdcore_crc7_inserter_crcreg11 [1:0] $xor$ls180.v:5008$794_Y } - connect \main_sdcore_crc7_inserter_crcreg13 { \main_sdcore_crc7_inserter_crcreg12 [5:3] $xor$ls180.v:5009$799_Y \main_sdcore_crc7_inserter_crcreg12 [1:0] $xor$ls180.v:5009$797_Y } - connect \main_sdcore_crc7_inserter_crcreg14 { \main_sdcore_crc7_inserter_crcreg13 [5:3] $xor$ls180.v:5010$802_Y \main_sdcore_crc7_inserter_crcreg13 [1:0] $xor$ls180.v:5010$800_Y } - connect \main_sdcore_crc7_inserter_crcreg15 { \main_sdcore_crc7_inserter_crcreg14 [5:3] $xor$ls180.v:5011$805_Y \main_sdcore_crc7_inserter_crcreg14 [1:0] $xor$ls180.v:5011$803_Y } - connect \main_sdcore_crc7_inserter_crcreg16 { \main_sdcore_crc7_inserter_crcreg15 [5:3] $xor$ls180.v:5012$808_Y \main_sdcore_crc7_inserter_crcreg15 [1:0] $xor$ls180.v:5012$806_Y } - connect \main_sdcore_crc7_inserter_crcreg17 { \main_sdcore_crc7_inserter_crcreg16 [5:3] $xor$ls180.v:5013$811_Y \main_sdcore_crc7_inserter_crcreg16 [1:0] $xor$ls180.v:5013$809_Y } - connect \main_sdcore_crc7_inserter_crcreg18 { \main_sdcore_crc7_inserter_crcreg17 [5:3] $xor$ls180.v:5014$814_Y \main_sdcore_crc7_inserter_crcreg17 [1:0] $xor$ls180.v:5014$812_Y } - connect \main_sdcore_crc7_inserter_crcreg19 { \main_sdcore_crc7_inserter_crcreg18 [5:3] $xor$ls180.v:5015$817_Y \main_sdcore_crc7_inserter_crcreg18 [1:0] $xor$ls180.v:5015$815_Y } - connect \main_sdcore_crc7_inserter_crcreg20 { \main_sdcore_crc7_inserter_crcreg19 [5:3] $xor$ls180.v:5016$820_Y \main_sdcore_crc7_inserter_crcreg19 [1:0] $xor$ls180.v:5016$818_Y } - connect \main_sdcore_crc7_inserter_crcreg21 { \main_sdcore_crc7_inserter_crcreg20 [5:3] $xor$ls180.v:5017$823_Y \main_sdcore_crc7_inserter_crcreg20 [1:0] $xor$ls180.v:5017$821_Y } - connect \main_sdcore_crc7_inserter_crcreg22 { \main_sdcore_crc7_inserter_crcreg21 [5:3] $xor$ls180.v:5018$826_Y \main_sdcore_crc7_inserter_crcreg21 [1:0] $xor$ls180.v:5018$824_Y } - connect \main_sdcore_crc7_inserter_crcreg23 { \main_sdcore_crc7_inserter_crcreg22 [5:3] $xor$ls180.v:5019$829_Y \main_sdcore_crc7_inserter_crcreg22 [1:0] $xor$ls180.v:5019$827_Y } - connect \main_sdcore_crc7_inserter_crcreg24 { \main_sdcore_crc7_inserter_crcreg23 [5:3] $xor$ls180.v:5020$832_Y \main_sdcore_crc7_inserter_crcreg23 [1:0] $xor$ls180.v:5020$830_Y } - connect \main_sdcore_crc7_inserter_crcreg25 { \main_sdcore_crc7_inserter_crcreg24 [5:3] $xor$ls180.v:5021$835_Y \main_sdcore_crc7_inserter_crcreg24 [1:0] $xor$ls180.v:5021$833_Y } - connect \main_sdcore_crc7_inserter_crcreg26 { \main_sdcore_crc7_inserter_crcreg25 [5:3] $xor$ls180.v:5022$838_Y \main_sdcore_crc7_inserter_crcreg25 [1:0] $xor$ls180.v:5022$836_Y } - connect \main_sdcore_crc7_inserter_crcreg27 { \main_sdcore_crc7_inserter_crcreg26 [5:3] $xor$ls180.v:5023$841_Y \main_sdcore_crc7_inserter_crcreg26 [1:0] $xor$ls180.v:5023$839_Y } - connect \main_sdcore_crc7_inserter_crcreg28 { \main_sdcore_crc7_inserter_crcreg27 [5:3] $xor$ls180.v:5024$844_Y \main_sdcore_crc7_inserter_crcreg27 [1:0] $xor$ls180.v:5024$842_Y } - connect \main_sdcore_crc7_inserter_crcreg29 { \main_sdcore_crc7_inserter_crcreg28 [5:3] $xor$ls180.v:5025$847_Y \main_sdcore_crc7_inserter_crcreg28 [1:0] $xor$ls180.v:5025$845_Y } - connect \main_sdcore_crc7_inserter_crcreg30 { \main_sdcore_crc7_inserter_crcreg29 [5:3] $xor$ls180.v:5026$850_Y \main_sdcore_crc7_inserter_crcreg29 [1:0] $xor$ls180.v:5026$848_Y } - connect \main_sdcore_crc7_inserter_crcreg31 { \main_sdcore_crc7_inserter_crcreg30 [5:3] $xor$ls180.v:5027$853_Y \main_sdcore_crc7_inserter_crcreg30 [1:0] $xor$ls180.v:5027$851_Y } - connect \main_sdcore_crc7_inserter_crcreg32 { \main_sdcore_crc7_inserter_crcreg31 [5:3] $xor$ls180.v:5028$856_Y \main_sdcore_crc7_inserter_crcreg31 [1:0] $xor$ls180.v:5028$854_Y } - connect \main_sdcore_crc7_inserter_crcreg33 { \main_sdcore_crc7_inserter_crcreg32 [5:3] $xor$ls180.v:5029$859_Y \main_sdcore_crc7_inserter_crcreg32 [1:0] $xor$ls180.v:5029$857_Y } - connect \main_sdcore_crc7_inserter_crcreg34 { \main_sdcore_crc7_inserter_crcreg33 [5:3] $xor$ls180.v:5030$862_Y \main_sdcore_crc7_inserter_crcreg33 [1:0] $xor$ls180.v:5030$860_Y } - connect \main_sdcore_crc7_inserter_crcreg35 { \main_sdcore_crc7_inserter_crcreg34 [5:3] $xor$ls180.v:5031$865_Y \main_sdcore_crc7_inserter_crcreg34 [1:0] $xor$ls180.v:5031$863_Y } - connect \main_sdcore_crc7_inserter_crcreg36 { \main_sdcore_crc7_inserter_crcreg35 [5:3] $xor$ls180.v:5032$868_Y \main_sdcore_crc7_inserter_crcreg35 [1:0] $xor$ls180.v:5032$866_Y } - connect \main_sdcore_crc7_inserter_crcreg37 { \main_sdcore_crc7_inserter_crcreg36 [5:3] $xor$ls180.v:5033$871_Y \main_sdcore_crc7_inserter_crcreg36 [1:0] $xor$ls180.v:5033$869_Y } - connect \main_sdcore_crc7_inserter_crcreg38 { \main_sdcore_crc7_inserter_crcreg37 [5:3] $xor$ls180.v:5034$874_Y \main_sdcore_crc7_inserter_crcreg37 [1:0] $xor$ls180.v:5034$872_Y } - connect \main_sdcore_crc7_inserter_crcreg39 { \main_sdcore_crc7_inserter_crcreg38 [5:3] $xor$ls180.v:5035$877_Y \main_sdcore_crc7_inserter_crcreg38 [1:0] $xor$ls180.v:5035$875_Y } - connect \main_sdcore_crc7_inserter_crcreg40 { \main_sdcore_crc7_inserter_crcreg39 [5:3] $xor$ls180.v:5036$880_Y \main_sdcore_crc7_inserter_crcreg39 [1:0] $xor$ls180.v:5036$878_Y } + connect \main_sdcore_crc7_inserter_crcreg1 { \main_sdcore_crc7_inserter_crcreg0 [5:3] $xor$ls180.v:5037$829_Y \main_sdcore_crc7_inserter_crcreg0 [1:0] $xor$ls180.v:5037$827_Y } + connect \main_sdcore_crc7_inserter_crcreg2 { \main_sdcore_crc7_inserter_crcreg1 [5:3] $xor$ls180.v:5038$832_Y \main_sdcore_crc7_inserter_crcreg1 [1:0] $xor$ls180.v:5038$830_Y } + connect \main_sdcore_crc7_inserter_crcreg3 { \main_sdcore_crc7_inserter_crcreg2 [5:3] $xor$ls180.v:5039$835_Y \main_sdcore_crc7_inserter_crcreg2 [1:0] $xor$ls180.v:5039$833_Y } + connect \main_sdcore_crc7_inserter_crcreg4 { \main_sdcore_crc7_inserter_crcreg3 [5:3] $xor$ls180.v:5040$838_Y \main_sdcore_crc7_inserter_crcreg3 [1:0] $xor$ls180.v:5040$836_Y } + connect \main_sdcore_crc7_inserter_crcreg5 { \main_sdcore_crc7_inserter_crcreg4 [5:3] $xor$ls180.v:5041$841_Y \main_sdcore_crc7_inserter_crcreg4 [1:0] $xor$ls180.v:5041$839_Y } + connect \main_sdcore_crc7_inserter_crcreg6 { \main_sdcore_crc7_inserter_crcreg5 [5:3] $xor$ls180.v:5042$844_Y \main_sdcore_crc7_inserter_crcreg5 [1:0] $xor$ls180.v:5042$842_Y } + connect \main_sdcore_crc7_inserter_crcreg7 { \main_sdcore_crc7_inserter_crcreg6 [5:3] $xor$ls180.v:5043$847_Y \main_sdcore_crc7_inserter_crcreg6 [1:0] $xor$ls180.v:5043$845_Y } + connect \main_sdcore_crc7_inserter_crcreg8 { \main_sdcore_crc7_inserter_crcreg7 [5:3] $xor$ls180.v:5044$850_Y \main_sdcore_crc7_inserter_crcreg7 [1:0] $xor$ls180.v:5044$848_Y } + connect \main_sdcore_crc7_inserter_crcreg9 { \main_sdcore_crc7_inserter_crcreg8 [5:3] $xor$ls180.v:5045$853_Y \main_sdcore_crc7_inserter_crcreg8 [1:0] $xor$ls180.v:5045$851_Y } + connect \main_sdcore_crc7_inserter_crcreg10 { \main_sdcore_crc7_inserter_crcreg9 [5:3] $xor$ls180.v:5046$856_Y \main_sdcore_crc7_inserter_crcreg9 [1:0] $xor$ls180.v:5046$854_Y } + connect \main_sdcore_crc7_inserter_crcreg11 { \main_sdcore_crc7_inserter_crcreg10 [5:3] $xor$ls180.v:5047$859_Y \main_sdcore_crc7_inserter_crcreg10 [1:0] $xor$ls180.v:5047$857_Y } + connect \main_sdcore_crc7_inserter_crcreg12 { \main_sdcore_crc7_inserter_crcreg11 [5:3] $xor$ls180.v:5048$862_Y \main_sdcore_crc7_inserter_crcreg11 [1:0] $xor$ls180.v:5048$860_Y } + connect \main_sdcore_crc7_inserter_crcreg13 { \main_sdcore_crc7_inserter_crcreg12 [5:3] $xor$ls180.v:5049$865_Y \main_sdcore_crc7_inserter_crcreg12 [1:0] $xor$ls180.v:5049$863_Y } + connect \main_sdcore_crc7_inserter_crcreg14 { \main_sdcore_crc7_inserter_crcreg13 [5:3] $xor$ls180.v:5050$868_Y \main_sdcore_crc7_inserter_crcreg13 [1:0] $xor$ls180.v:5050$866_Y } + connect \main_sdcore_crc7_inserter_crcreg15 { \main_sdcore_crc7_inserter_crcreg14 [5:3] $xor$ls180.v:5051$871_Y \main_sdcore_crc7_inserter_crcreg14 [1:0] $xor$ls180.v:5051$869_Y } + connect \main_sdcore_crc7_inserter_crcreg16 { \main_sdcore_crc7_inserter_crcreg15 [5:3] $xor$ls180.v:5052$874_Y \main_sdcore_crc7_inserter_crcreg15 [1:0] $xor$ls180.v:5052$872_Y } + connect \main_sdcore_crc7_inserter_crcreg17 { \main_sdcore_crc7_inserter_crcreg16 [5:3] $xor$ls180.v:5053$877_Y \main_sdcore_crc7_inserter_crcreg16 [1:0] $xor$ls180.v:5053$875_Y } + connect \main_sdcore_crc7_inserter_crcreg18 { \main_sdcore_crc7_inserter_crcreg17 [5:3] $xor$ls180.v:5054$880_Y \main_sdcore_crc7_inserter_crcreg17 [1:0] $xor$ls180.v:5054$878_Y } + connect \main_sdcore_crc7_inserter_crcreg19 { \main_sdcore_crc7_inserter_crcreg18 [5:3] $xor$ls180.v:5055$883_Y \main_sdcore_crc7_inserter_crcreg18 [1:0] $xor$ls180.v:5055$881_Y } + connect \main_sdcore_crc7_inserter_crcreg20 { \main_sdcore_crc7_inserter_crcreg19 [5:3] $xor$ls180.v:5056$886_Y \main_sdcore_crc7_inserter_crcreg19 [1:0] $xor$ls180.v:5056$884_Y } + connect \main_sdcore_crc7_inserter_crcreg21 { \main_sdcore_crc7_inserter_crcreg20 [5:3] $xor$ls180.v:5057$889_Y \main_sdcore_crc7_inserter_crcreg20 [1:0] $xor$ls180.v:5057$887_Y } + connect \main_sdcore_crc7_inserter_crcreg22 { \main_sdcore_crc7_inserter_crcreg21 [5:3] $xor$ls180.v:5058$892_Y \main_sdcore_crc7_inserter_crcreg21 [1:0] $xor$ls180.v:5058$890_Y } + connect \main_sdcore_crc7_inserter_crcreg23 { \main_sdcore_crc7_inserter_crcreg22 [5:3] $xor$ls180.v:5059$895_Y \main_sdcore_crc7_inserter_crcreg22 [1:0] $xor$ls180.v:5059$893_Y } + connect \main_sdcore_crc7_inserter_crcreg24 { \main_sdcore_crc7_inserter_crcreg23 [5:3] $xor$ls180.v:5060$898_Y \main_sdcore_crc7_inserter_crcreg23 [1:0] $xor$ls180.v:5060$896_Y } + connect \main_sdcore_crc7_inserter_crcreg25 { \main_sdcore_crc7_inserter_crcreg24 [5:3] $xor$ls180.v:5061$901_Y \main_sdcore_crc7_inserter_crcreg24 [1:0] $xor$ls180.v:5061$899_Y } + connect \main_sdcore_crc7_inserter_crcreg26 { \main_sdcore_crc7_inserter_crcreg25 [5:3] $xor$ls180.v:5062$904_Y \main_sdcore_crc7_inserter_crcreg25 [1:0] $xor$ls180.v:5062$902_Y } + connect \main_sdcore_crc7_inserter_crcreg27 { \main_sdcore_crc7_inserter_crcreg26 [5:3] $xor$ls180.v:5063$907_Y \main_sdcore_crc7_inserter_crcreg26 [1:0] $xor$ls180.v:5063$905_Y } + connect \main_sdcore_crc7_inserter_crcreg28 { \main_sdcore_crc7_inserter_crcreg27 [5:3] $xor$ls180.v:5064$910_Y \main_sdcore_crc7_inserter_crcreg27 [1:0] $xor$ls180.v:5064$908_Y } + connect \main_sdcore_crc7_inserter_crcreg29 { \main_sdcore_crc7_inserter_crcreg28 [5:3] $xor$ls180.v:5065$913_Y \main_sdcore_crc7_inserter_crcreg28 [1:0] $xor$ls180.v:5065$911_Y } + connect \main_sdcore_crc7_inserter_crcreg30 { \main_sdcore_crc7_inserter_crcreg29 [5:3] $xor$ls180.v:5066$916_Y \main_sdcore_crc7_inserter_crcreg29 [1:0] $xor$ls180.v:5066$914_Y } + connect \main_sdcore_crc7_inserter_crcreg31 { \main_sdcore_crc7_inserter_crcreg30 [5:3] $xor$ls180.v:5067$919_Y \main_sdcore_crc7_inserter_crcreg30 [1:0] $xor$ls180.v:5067$917_Y } + connect \main_sdcore_crc7_inserter_crcreg32 { \main_sdcore_crc7_inserter_crcreg31 [5:3] $xor$ls180.v:5068$922_Y \main_sdcore_crc7_inserter_crcreg31 [1:0] $xor$ls180.v:5068$920_Y } + connect \main_sdcore_crc7_inserter_crcreg33 { \main_sdcore_crc7_inserter_crcreg32 [5:3] $xor$ls180.v:5069$925_Y \main_sdcore_crc7_inserter_crcreg32 [1:0] $xor$ls180.v:5069$923_Y } + connect \main_sdcore_crc7_inserter_crcreg34 { \main_sdcore_crc7_inserter_crcreg33 [5:3] $xor$ls180.v:5070$928_Y \main_sdcore_crc7_inserter_crcreg33 [1:0] $xor$ls180.v:5070$926_Y } + connect \main_sdcore_crc7_inserter_crcreg35 { \main_sdcore_crc7_inserter_crcreg34 [5:3] $xor$ls180.v:5071$931_Y \main_sdcore_crc7_inserter_crcreg34 [1:0] $xor$ls180.v:5071$929_Y } + connect \main_sdcore_crc7_inserter_crcreg36 { \main_sdcore_crc7_inserter_crcreg35 [5:3] $xor$ls180.v:5072$934_Y \main_sdcore_crc7_inserter_crcreg35 [1:0] $xor$ls180.v:5072$932_Y } + connect \main_sdcore_crc7_inserter_crcreg37 { \main_sdcore_crc7_inserter_crcreg36 [5:3] $xor$ls180.v:5073$937_Y \main_sdcore_crc7_inserter_crcreg36 [1:0] $xor$ls180.v:5073$935_Y } + connect \main_sdcore_crc7_inserter_crcreg38 { \main_sdcore_crc7_inserter_crcreg37 [5:3] $xor$ls180.v:5074$940_Y \main_sdcore_crc7_inserter_crcreg37 [1:0] $xor$ls180.v:5074$938_Y } + connect \main_sdcore_crc7_inserter_crcreg39 { \main_sdcore_crc7_inserter_crcreg38 [5:3] $xor$ls180.v:5075$943_Y \main_sdcore_crc7_inserter_crcreg38 [1:0] $xor$ls180.v:5075$941_Y } + connect \main_sdcore_crc7_inserter_crcreg40 { \main_sdcore_crc7_inserter_crcreg39 [5:3] $xor$ls180.v:5076$946_Y \main_sdcore_crc7_inserter_crcreg39 [1:0] $xor$ls180.v:5076$944_Y } connect \main_sdcore_crc16_inserter_crc0_val { \main_sdcore_crc16_inserter_sink_payload_data [4] \main_sdcore_crc16_inserter_sink_payload_data [0] } - connect \main_sdcore_crc16_inserter_crc0_clr $and$ls180.v:5046$883_Y - connect \main_sdcore_crc16_inserter_crc0_enable $and$ls180.v:5047$884_Y + connect \main_sdcore_crc16_inserter_crc0_clr $and$ls180.v:5086$949_Y + connect \main_sdcore_crc16_inserter_crc0_enable $and$ls180.v:5087$950_Y connect \main_sdcore_crc16_inserter_crc1_val { \main_sdcore_crc16_inserter_sink_payload_data [5] \main_sdcore_crc16_inserter_sink_payload_data [1] } - connect \main_sdcore_crc16_inserter_crc1_clr $and$ls180.v:5049$886_Y - connect \main_sdcore_crc16_inserter_crc1_enable $and$ls180.v:5050$887_Y + connect \main_sdcore_crc16_inserter_crc1_clr $and$ls180.v:5089$952_Y + connect \main_sdcore_crc16_inserter_crc1_enable $and$ls180.v:5090$953_Y connect \main_sdcore_crc16_inserter_crc2_val { \main_sdcore_crc16_inserter_sink_payload_data [6] \main_sdcore_crc16_inserter_sink_payload_data [2] } - connect \main_sdcore_crc16_inserter_crc2_clr $and$ls180.v:5052$889_Y - connect \main_sdcore_crc16_inserter_crc2_enable $and$ls180.v:5053$890_Y + connect \main_sdcore_crc16_inserter_crc2_clr $and$ls180.v:5092$955_Y + connect \main_sdcore_crc16_inserter_crc2_enable $and$ls180.v:5093$956_Y connect \main_sdcore_crc16_inserter_crc3_val { \main_sdcore_crc16_inserter_sink_payload_data [7] \main_sdcore_crc16_inserter_sink_payload_data [3] } - connect \main_sdcore_crc16_inserter_crc3_clr $and$ls180.v:5055$892_Y - connect \main_sdcore_crc16_inserter_crc3_enable $and$ls180.v:5056$893_Y - connect \main_sdcore_crc16_inserter_crc0_crcreg1 { \main_sdcore_crc16_inserter_crc0_crcreg0 [14:12] $xor$ls180.v:5057$898_Y \main_sdcore_crc16_inserter_crc0_crcreg0 [10:5] $xor$ls180.v:5057$896_Y \main_sdcore_crc16_inserter_crc0_crcreg0 [3:0] $xor$ls180.v:5057$894_Y } - connect \main_sdcore_crc16_inserter_crc0_crcreg2 { \main_sdcore_crc16_inserter_crc0_crcreg1 [14:12] $xor$ls180.v:5058$903_Y \main_sdcore_crc16_inserter_crc0_crcreg1 [10:5] $xor$ls180.v:5058$901_Y \main_sdcore_crc16_inserter_crc0_crcreg1 [3:0] $xor$ls180.v:5058$899_Y } - connect \main_sdcore_crc16_inserter_crc1_crcreg1 { \main_sdcore_crc16_inserter_crc1_crcreg0 [14:12] $xor$ls180.v:5067$909_Y \main_sdcore_crc16_inserter_crc1_crcreg0 [10:5] $xor$ls180.v:5067$907_Y \main_sdcore_crc16_inserter_crc1_crcreg0 [3:0] $xor$ls180.v:5067$905_Y } - connect \main_sdcore_crc16_inserter_crc1_crcreg2 { \main_sdcore_crc16_inserter_crc1_crcreg1 [14:12] $xor$ls180.v:5068$914_Y \main_sdcore_crc16_inserter_crc1_crcreg1 [10:5] $xor$ls180.v:5068$912_Y \main_sdcore_crc16_inserter_crc1_crcreg1 [3:0] $xor$ls180.v:5068$910_Y } - connect \main_sdcore_crc16_inserter_crc2_crcreg1 { \main_sdcore_crc16_inserter_crc2_crcreg0 [14:12] $xor$ls180.v:5077$920_Y \main_sdcore_crc16_inserter_crc2_crcreg0 [10:5] $xor$ls180.v:5077$918_Y \main_sdcore_crc16_inserter_crc2_crcreg0 [3:0] $xor$ls180.v:5077$916_Y } - connect \main_sdcore_crc16_inserter_crc2_crcreg2 { \main_sdcore_crc16_inserter_crc2_crcreg1 [14:12] $xor$ls180.v:5078$925_Y \main_sdcore_crc16_inserter_crc2_crcreg1 [10:5] $xor$ls180.v:5078$923_Y \main_sdcore_crc16_inserter_crc2_crcreg1 [3:0] $xor$ls180.v:5078$921_Y } - connect \main_sdcore_crc16_inserter_crc3_crcreg1 { \main_sdcore_crc16_inserter_crc3_crcreg0 [14:12] $xor$ls180.v:5087$931_Y \main_sdcore_crc16_inserter_crc3_crcreg0 [10:5] $xor$ls180.v:5087$929_Y \main_sdcore_crc16_inserter_crc3_crcreg0 [3:0] $xor$ls180.v:5087$927_Y } - connect \main_sdcore_crc16_inserter_crc3_crcreg2 { \main_sdcore_crc16_inserter_crc3_crcreg1 [14:12] $xor$ls180.v:5088$936_Y \main_sdcore_crc16_inserter_crc3_crcreg1 [10:5] $xor$ls180.v:5088$934_Y \main_sdcore_crc16_inserter_crc3_crcreg1 [3:0] $xor$ls180.v:5088$932_Y } + connect \main_sdcore_crc16_inserter_crc3_clr $and$ls180.v:5095$958_Y + connect \main_sdcore_crc16_inserter_crc3_enable $and$ls180.v:5096$959_Y + connect \main_sdcore_crc16_inserter_crc0_crcreg1 { \main_sdcore_crc16_inserter_crc0_crcreg0 [14:12] $xor$ls180.v:5097$964_Y \main_sdcore_crc16_inserter_crc0_crcreg0 [10:5] $xor$ls180.v:5097$962_Y \main_sdcore_crc16_inserter_crc0_crcreg0 [3:0] $xor$ls180.v:5097$960_Y } + connect \main_sdcore_crc16_inserter_crc0_crcreg2 { \main_sdcore_crc16_inserter_crc0_crcreg1 [14:12] $xor$ls180.v:5098$969_Y \main_sdcore_crc16_inserter_crc0_crcreg1 [10:5] $xor$ls180.v:5098$967_Y \main_sdcore_crc16_inserter_crc0_crcreg1 [3:0] $xor$ls180.v:5098$965_Y } + connect \main_sdcore_crc16_inserter_crc1_crcreg1 { \main_sdcore_crc16_inserter_crc1_crcreg0 [14:12] $xor$ls180.v:5107$975_Y \main_sdcore_crc16_inserter_crc1_crcreg0 [10:5] $xor$ls180.v:5107$973_Y \main_sdcore_crc16_inserter_crc1_crcreg0 [3:0] $xor$ls180.v:5107$971_Y } + connect \main_sdcore_crc16_inserter_crc1_crcreg2 { \main_sdcore_crc16_inserter_crc1_crcreg1 [14:12] $xor$ls180.v:5108$980_Y \main_sdcore_crc16_inserter_crc1_crcreg1 [10:5] $xor$ls180.v:5108$978_Y \main_sdcore_crc16_inserter_crc1_crcreg1 [3:0] $xor$ls180.v:5108$976_Y } + connect \main_sdcore_crc16_inserter_crc2_crcreg1 { \main_sdcore_crc16_inserter_crc2_crcreg0 [14:12] $xor$ls180.v:5117$986_Y \main_sdcore_crc16_inserter_crc2_crcreg0 [10:5] $xor$ls180.v:5117$984_Y \main_sdcore_crc16_inserter_crc2_crcreg0 [3:0] $xor$ls180.v:5117$982_Y } + connect \main_sdcore_crc16_inserter_crc2_crcreg2 { \main_sdcore_crc16_inserter_crc2_crcreg1 [14:12] $xor$ls180.v:5118$991_Y \main_sdcore_crc16_inserter_crc2_crcreg1 [10:5] $xor$ls180.v:5118$989_Y \main_sdcore_crc16_inserter_crc2_crcreg1 [3:0] $xor$ls180.v:5118$987_Y } + connect \main_sdcore_crc16_inserter_crc3_crcreg1 { \main_sdcore_crc16_inserter_crc3_crcreg0 [14:12] $xor$ls180.v:5127$997_Y \main_sdcore_crc16_inserter_crc3_crcreg0 [10:5] $xor$ls180.v:5127$995_Y \main_sdcore_crc16_inserter_crc3_crcreg0 [3:0] $xor$ls180.v:5127$993_Y } + connect \main_sdcore_crc16_inserter_crc3_crcreg2 { \main_sdcore_crc16_inserter_crc3_crcreg1 [14:12] $xor$ls180.v:5128$1002_Y \main_sdcore_crc16_inserter_crc3_crcreg1 [10:5] $xor$ls180.v:5128$1000_Y \main_sdcore_crc16_inserter_crc3_crcreg1 [3:0] $xor$ls180.v:5128$998_Y } connect \main_sdcore_crc16_checker_crc0_val { \main_sdcore_crc16_checker_val [7] \main_sdcore_crc16_checker_val [3] } - connect \main_sdcore_crc16_checker_crc0_enable $and$ls180.v:5184$952_Y + connect \main_sdcore_crc16_checker_crc0_enable $and$ls180.v:5224$1018_Y connect \main_sdcore_crc16_checker_crc1_val { \main_sdcore_crc16_checker_val [6] \main_sdcore_crc16_checker_val [2] } - connect \main_sdcore_crc16_checker_crc1_enable $and$ls180.v:5194$955_Y + connect \main_sdcore_crc16_checker_crc1_enable $and$ls180.v:5234$1021_Y connect \main_sdcore_crc16_checker_crc2_val { \main_sdcore_crc16_checker_val [5] \main_sdcore_crc16_checker_val [1] } - connect \main_sdcore_crc16_checker_crc2_enable $and$ls180.v:5204$958_Y + connect \main_sdcore_crc16_checker_crc2_enable $and$ls180.v:5244$1024_Y connect \main_sdcore_crc16_checker_crc3_val { \main_sdcore_crc16_checker_val [4] \main_sdcore_crc16_checker_val [0] } - connect \main_sdcore_crc16_checker_crc3_enable $and$ls180.v:5214$961_Y + connect \main_sdcore_crc16_checker_crc3_enable $and$ls180.v:5254$1027_Y connect \main_sdcore_crc16_checker_source_payload_data \main_sdcore_crc16_checker_val connect \main_sdcore_crc16_checker_source_last \main_sdcore_crc16_checker_sink_last - connect \main_sdcore_crc16_checker_crc0_crcreg1 { \main_sdcore_crc16_checker_crc0_crcreg0 [14:12] $xor$ls180.v:5239$973_Y \main_sdcore_crc16_checker_crc0_crcreg0 [10:5] $xor$ls180.v:5239$971_Y \main_sdcore_crc16_checker_crc0_crcreg0 [3:0] $xor$ls180.v:5239$969_Y } - connect \main_sdcore_crc16_checker_crc0_crcreg2 { \main_sdcore_crc16_checker_crc0_crcreg1 [14:12] $xor$ls180.v:5240$978_Y \main_sdcore_crc16_checker_crc0_crcreg1 [10:5] $xor$ls180.v:5240$976_Y \main_sdcore_crc16_checker_crc0_crcreg1 [3:0] $xor$ls180.v:5240$974_Y } - connect \main_sdcore_crc16_checker_crc1_crcreg1 { \main_sdcore_crc16_checker_crc1_crcreg0 [14:12] $xor$ls180.v:5249$984_Y \main_sdcore_crc16_checker_crc1_crcreg0 [10:5] $xor$ls180.v:5249$982_Y \main_sdcore_crc16_checker_crc1_crcreg0 [3:0] $xor$ls180.v:5249$980_Y } - connect \main_sdcore_crc16_checker_crc1_crcreg2 { \main_sdcore_crc16_checker_crc1_crcreg1 [14:12] $xor$ls180.v:5250$989_Y \main_sdcore_crc16_checker_crc1_crcreg1 [10:5] $xor$ls180.v:5250$987_Y \main_sdcore_crc16_checker_crc1_crcreg1 [3:0] $xor$ls180.v:5250$985_Y } - connect \main_sdcore_crc16_checker_crc2_crcreg1 { \main_sdcore_crc16_checker_crc2_crcreg0 [14:12] $xor$ls180.v:5259$995_Y \main_sdcore_crc16_checker_crc2_crcreg0 [10:5] $xor$ls180.v:5259$993_Y \main_sdcore_crc16_checker_crc2_crcreg0 [3:0] $xor$ls180.v:5259$991_Y } - connect \main_sdcore_crc16_checker_crc2_crcreg2 { \main_sdcore_crc16_checker_crc2_crcreg1 [14:12] $xor$ls180.v:5260$1000_Y \main_sdcore_crc16_checker_crc2_crcreg1 [10:5] $xor$ls180.v:5260$998_Y \main_sdcore_crc16_checker_crc2_crcreg1 [3:0] $xor$ls180.v:5260$996_Y } - connect \main_sdcore_crc16_checker_crc3_crcreg1 { \main_sdcore_crc16_checker_crc3_crcreg0 [14:12] $xor$ls180.v:5269$1006_Y \main_sdcore_crc16_checker_crc3_crcreg0 [10:5] $xor$ls180.v:5269$1004_Y \main_sdcore_crc16_checker_crc3_crcreg0 [3:0] $xor$ls180.v:5269$1002_Y } - connect \main_sdcore_crc16_checker_crc3_crcreg2 { \main_sdcore_crc16_checker_crc3_crcreg1 [14:12] $xor$ls180.v:5270$1011_Y \main_sdcore_crc16_checker_crc3_crcreg1 [10:5] $xor$ls180.v:5270$1009_Y \main_sdcore_crc16_checker_crc3_crcreg1 [3:0] $xor$ls180.v:5270$1007_Y } + connect \main_sdcore_crc16_checker_crc0_crcreg1 { \main_sdcore_crc16_checker_crc0_crcreg0 [14:12] $xor$ls180.v:5279$1039_Y \main_sdcore_crc16_checker_crc0_crcreg0 [10:5] $xor$ls180.v:5279$1037_Y \main_sdcore_crc16_checker_crc0_crcreg0 [3:0] $xor$ls180.v:5279$1035_Y } + connect \main_sdcore_crc16_checker_crc0_crcreg2 { \main_sdcore_crc16_checker_crc0_crcreg1 [14:12] $xor$ls180.v:5280$1044_Y \main_sdcore_crc16_checker_crc0_crcreg1 [10:5] $xor$ls180.v:5280$1042_Y \main_sdcore_crc16_checker_crc0_crcreg1 [3:0] $xor$ls180.v:5280$1040_Y } + connect \main_sdcore_crc16_checker_crc1_crcreg1 { \main_sdcore_crc16_checker_crc1_crcreg0 [14:12] $xor$ls180.v:5289$1050_Y \main_sdcore_crc16_checker_crc1_crcreg0 [10:5] $xor$ls180.v:5289$1048_Y \main_sdcore_crc16_checker_crc1_crcreg0 [3:0] $xor$ls180.v:5289$1046_Y } + connect \main_sdcore_crc16_checker_crc1_crcreg2 { \main_sdcore_crc16_checker_crc1_crcreg1 [14:12] $xor$ls180.v:5290$1055_Y \main_sdcore_crc16_checker_crc1_crcreg1 [10:5] $xor$ls180.v:5290$1053_Y \main_sdcore_crc16_checker_crc1_crcreg1 [3:0] $xor$ls180.v:5290$1051_Y } + connect \main_sdcore_crc16_checker_crc2_crcreg1 { \main_sdcore_crc16_checker_crc2_crcreg0 [14:12] $xor$ls180.v:5299$1061_Y \main_sdcore_crc16_checker_crc2_crcreg0 [10:5] $xor$ls180.v:5299$1059_Y \main_sdcore_crc16_checker_crc2_crcreg0 [3:0] $xor$ls180.v:5299$1057_Y } + connect \main_sdcore_crc16_checker_crc2_crcreg2 { \main_sdcore_crc16_checker_crc2_crcreg1 [14:12] $xor$ls180.v:5300$1066_Y \main_sdcore_crc16_checker_crc2_crcreg1 [10:5] $xor$ls180.v:5300$1064_Y \main_sdcore_crc16_checker_crc2_crcreg1 [3:0] $xor$ls180.v:5300$1062_Y } + connect \main_sdcore_crc16_checker_crc3_crcreg1 { \main_sdcore_crc16_checker_crc3_crcreg0 [14:12] $xor$ls180.v:5309$1072_Y \main_sdcore_crc16_checker_crc3_crcreg0 [10:5] $xor$ls180.v:5309$1070_Y \main_sdcore_crc16_checker_crc3_crcreg0 [3:0] $xor$ls180.v:5309$1068_Y } + connect \main_sdcore_crc16_checker_crc3_crcreg2 { \main_sdcore_crc16_checker_crc3_crcreg1 [14:12] $xor$ls180.v:5310$1077_Y \main_sdcore_crc16_checker_crc3_crcreg1 [10:5] $xor$ls180.v:5310$1075_Y \main_sdcore_crc16_checker_crc3_crcreg1 [3:0] $xor$ls180.v:5310$1073_Y } connect \main_sdblock2mem_fifo_sink_valid \main_sdblock2mem_sink_sink_valid0 connect \main_sdblock2mem_sink_sink_ready0 \main_sdblock2mem_fifo_sink_ready connect \main_sdblock2mem_fifo_sink_first \main_sdblock2mem_sink_sink_first @@ -283291,30 +284801,30 @@ module \ls180 connect \main_sdblock2mem_fifo_source_payload_data \main_sdblock2mem_fifo_fifo_out_payload_data connect \main_sdblock2mem_fifo_syncfifo_re \main_sdblock2mem_fifo_source_ready connect \main_sdblock2mem_fifo_wrport_dat_w \main_sdblock2mem_fifo_syncfifo_din - connect \main_sdblock2mem_fifo_wrport_we $and$ls180.v:5506$1041_Y - connect \main_sdblock2mem_fifo_do_read $and$ls180.v:5507$1042_Y + connect \main_sdblock2mem_fifo_wrport_we $and$ls180.v:5546$1107_Y + connect \main_sdblock2mem_fifo_do_read $and$ls180.v:5547$1108_Y connect \main_sdblock2mem_fifo_rdport_adr \main_sdblock2mem_fifo_consume connect \main_sdblock2mem_fifo_syncfifo_dout \main_sdblock2mem_fifo_rdport_dat_r - connect \main_sdblock2mem_fifo_syncfifo_writable $ne$ls180.v:5510$1043_Y - connect \main_sdblock2mem_fifo_syncfifo_readable $ne$ls180.v:5511$1044_Y + connect \main_sdblock2mem_fifo_syncfifo_writable $ne$ls180.v:5550$1109_Y + connect \main_sdblock2mem_fifo_syncfifo_readable $ne$ls180.v:5551$1110_Y connect \main_sdblock2mem_source_source_valid \main_sdblock2mem_converter_source_valid connect \main_sdblock2mem_converter_source_ready \main_sdblock2mem_source_source_ready connect \main_sdblock2mem_source_source_first \main_sdblock2mem_converter_source_first connect \main_sdblock2mem_source_source_last \main_sdblock2mem_converter_source_last connect \main_sdblock2mem_source_source_payload_data \main_sdblock2mem_converter_source_payload_data - connect \main_sdblock2mem_converter_sink_ready $or$ls180.v:5517$1046_Y + connect \main_sdblock2mem_converter_sink_ready $or$ls180.v:5557$1112_Y connect \main_sdblock2mem_converter_source_valid \main_sdblock2mem_converter_strobe_all - connect \main_sdblock2mem_converter_load_part $and$ls180.v:5519$1047_Y + connect \main_sdblock2mem_converter_load_part $and$ls180.v:5559$1113_Y connect \main_interface0_bus_stb \main_sdblock2mem_sink_sink_valid1 connect \main_interface0_bus_cyc \main_sdblock2mem_sink_sink_valid1 connect \main_interface0_bus_we 1'1 - connect \main_interface0_bus_sel 4'1111 + connect \main_interface0_bus_sel 8'11111111 connect \main_interface0_bus_adr \main_sdblock2mem_sink_sink_payload_address - connect \main_interface0_bus_dat_w { \main_sdblock2mem_sink_sink_payload_data1 [7:0] \main_sdblock2mem_sink_sink_payload_data1 [15:8] \main_sdblock2mem_sink_sink_payload_data1 [23:16] \main_sdblock2mem_sink_sink_payload_data1 [31:24] } + connect \main_interface0_bus_dat_w { \main_sdblock2mem_sink_sink_payload_data1 [7:0] \main_sdblock2mem_sink_sink_payload_data1 [15:8] \main_sdblock2mem_sink_sink_payload_data1 [23:16] \main_sdblock2mem_sink_sink_payload_data1 [31:24] \main_sdblock2mem_sink_sink_payload_data1 [39:32] \main_sdblock2mem_sink_sink_payload_data1 [47:40] \main_sdblock2mem_sink_sink_payload_data1 [55:48] \main_sdblock2mem_sink_sink_payload_data1 [63:56] } connect \main_sdblock2mem_sink_sink_ready1 \main_interface0_bus_ack - connect \main_sdblock2mem_wishbonedmawriter_base \main_sdblock2mem_wishbonedmawriter_base_storage [33:2] - connect \main_sdblock2mem_wishbonedmawriter_length { 2'00 \main_sdblock2mem_wishbonedmawriter_length_storage [31:2] } - connect \main_sdblock2mem_wishbonedmawriter_reset $not$ls180.v:5529$1048_Y + connect \main_sdblock2mem_wishbonedmawriter_base \main_sdblock2mem_wishbonedmawriter_base_storage [34:3] + connect \main_sdblock2mem_wishbonedmawriter_length { 3'000 \main_sdblock2mem_wishbonedmawriter_length_storage [31:3] } + connect \main_sdblock2mem_wishbonedmawriter_reset $not$ls180.v:5569$1114_Y connect \main_sdmem2block_converter_sink_valid \main_sdmem2block_dma_source_valid connect \main_sdmem2block_dma_source_ready \main_sdmem2block_converter_sink_ready connect \main_sdmem2block_converter_sink_first \main_sdmem2block_dma_source_first @@ -283330,21 +284840,21 @@ module \ls180 connect \main_sdmem2block_source_source_first0 \main_sdmem2block_fifo_source_first connect \main_sdmem2block_source_source_last0 \main_sdmem2block_fifo_source_last connect \main_sdmem2block_source_source_payload_data0 \main_sdmem2block_fifo_source_payload_data - connect \main_sdmem2block_dma_base \main_sdmem2block_dma_base_storage [33:2] - connect \main_sdmem2block_dma_length { 2'00 \main_sdmem2block_dma_length_storage [31:2] } + connect \main_sdmem2block_dma_base \main_sdmem2block_dma_base_storage [34:3] + connect \main_sdmem2block_dma_length { 3'000 \main_sdmem2block_dma_length_storage [31:3] } connect \main_sdmem2block_dma_offset_status \main_sdmem2block_dma_offset - connect \main_sdmem2block_dma_reset $not$ls180.v:5588$1055_Y + connect \main_sdmem2block_dma_reset $not$ls180.v:5628$1121_Y connect \main_sdmem2block_source_source_valid1 \main_sdmem2block_converter_source_valid connect \main_sdmem2block_converter_source_ready \main_sdmem2block_source_source_ready1 connect \main_sdmem2block_source_source_first1 \main_sdmem2block_converter_source_first connect \main_sdmem2block_source_source_last1 \main_sdmem2block_converter_source_last connect \main_sdmem2block_source_source_payload_data1 \main_sdmem2block_converter_source_payload_data - connect \main_sdmem2block_converter_first $eq$ls180.v:5669$1063_Y - connect \main_sdmem2block_converter_last $eq$ls180.v:5670$1064_Y + connect \main_sdmem2block_converter_first $eq$ls180.v:5709$1129_Y + connect \main_sdmem2block_converter_last $eq$ls180.v:5710$1130_Y connect \main_sdmem2block_converter_source_valid \main_sdmem2block_converter_sink_valid - connect \main_sdmem2block_converter_source_first $and$ls180.v:5672$1065_Y - connect \main_sdmem2block_converter_source_last $and$ls180.v:5673$1066_Y - connect \main_sdmem2block_converter_sink_ready $and$ls180.v:5674$1067_Y + connect \main_sdmem2block_converter_source_first $and$ls180.v:5712$1131_Y + connect \main_sdmem2block_converter_source_last $and$ls180.v:5713$1132_Y + connect \main_sdmem2block_converter_sink_ready $and$ls180.v:5714$1133_Y connect \main_sdmem2block_converter_source_payload_valid_token_count \main_sdmem2block_converter_last connect \main_sdmem2block_fifo_syncfifo_din { \main_sdmem2block_fifo_fifo_in_last \main_sdmem2block_fifo_fifo_in_first \main_sdmem2block_fifo_fifo_in_payload_data } connect { \main_sdmem2block_fifo_fifo_out_last \main_sdmem2block_fifo_fifo_out_first \main_sdmem2block_fifo_fifo_out_payload_data } \main_sdmem2block_fifo_syncfifo_dout @@ -283359,131 +284869,131 @@ module \ls180 connect \main_sdmem2block_fifo_source_payload_data \main_sdmem2block_fifo_fifo_out_payload_data connect \main_sdmem2block_fifo_syncfifo_re \main_sdmem2block_fifo_source_ready connect \main_sdmem2block_fifo_wrport_dat_w \main_sdmem2block_fifo_syncfifo_din - connect \main_sdmem2block_fifo_wrport_we $and$ls180.v:5714$1072_Y - connect \main_sdmem2block_fifo_do_read $and$ls180.v:5715$1073_Y + connect \main_sdmem2block_fifo_wrport_we $and$ls180.v:5766$1138_Y + connect \main_sdmem2block_fifo_do_read $and$ls180.v:5767$1139_Y connect \main_sdmem2block_fifo_rdport_adr \main_sdmem2block_fifo_consume connect \main_sdmem2block_fifo_syncfifo_dout \main_sdmem2block_fifo_rdport_dat_r - connect \main_sdmem2block_fifo_syncfifo_writable $ne$ls180.v:5718$1074_Y - connect \main_sdmem2block_fifo_syncfifo_readable $ne$ls180.v:5719$1075_Y + connect \main_sdmem2block_fifo_syncfifo_writable $ne$ls180.v:5770$1140_Y + connect \main_sdmem2block_fifo_syncfifo_readable $ne$ls180.v:5771$1141_Y connect \builder_shared_adr \builder_comb_rhs_array_muxed24 [29:0] - connect \builder_shared_dat_w \builder_comb_rhs_array_muxed25 - connect \builder_shared_sel \builder_comb_rhs_array_muxed26 + connect \builder_shared_dat_w \builder_comb_rhs_array_muxed25 [31:0] + connect \builder_shared_sel \builder_comb_rhs_array_muxed26 [3:0] connect \builder_shared_cyc \builder_comb_rhs_array_muxed27 connect \builder_shared_stb \builder_comb_rhs_array_muxed28 connect \builder_shared_we \builder_comb_rhs_array_muxed29 connect \builder_shared_cti \builder_comb_rhs_array_muxed30 connect \builder_shared_bte \builder_comb_rhs_array_muxed31 - connect \main_libresocsim_interface0_converted_interface_dat_r \builder_shared_dat_r - connect \main_libresocsim_interface1_converted_interface_dat_r \builder_shared_dat_r - connect \main_libresocsim_interface2_converted_interface_dat_r \builder_shared_dat_r - connect \main_interface0_bus_dat_r \builder_shared_dat_r - connect \main_interface1_bus_dat_r \builder_shared_dat_r - connect \main_libresocsim_interface0_converted_interface_ack $and$ls180.v:5770$1081_Y - connect \main_libresocsim_interface1_converted_interface_ack $and$ls180.v:5771$1083_Y - connect \main_libresocsim_interface2_converted_interface_ack $and$ls180.v:5772$1085_Y - connect \main_interface0_bus_ack $and$ls180.v:5773$1087_Y - connect \main_interface1_bus_ack $and$ls180.v:5774$1089_Y - connect \main_libresocsim_interface0_converted_interface_err $and$ls180.v:5775$1091_Y - connect \main_libresocsim_interface1_converted_interface_err $and$ls180.v:5776$1093_Y - connect \main_libresocsim_interface2_converted_interface_err $and$ls180.v:5777$1095_Y - connect \main_interface0_bus_err $and$ls180.v:5778$1097_Y - connect \main_interface1_bus_err $and$ls180.v:5779$1099_Y - connect \builder_request { \main_interface1_bus_cyc \main_interface0_bus_cyc \main_libresocsim_interface2_converted_interface_cyc \main_libresocsim_interface1_converted_interface_cyc \main_libresocsim_interface0_converted_interface_cyc } + connect \main_libresocsim_libresoc_ibus_dat_r { 32'00000000000000000000000000000000 \builder_shared_dat_r } + connect \main_libresocsim_libresoc_dbus_dat_r { 32'00000000000000000000000000000000 \builder_shared_dat_r } + connect \main_libresocsim_libresoc_jtag_wb_dat_r { 32'00000000000000000000000000000000 \builder_shared_dat_r } + connect \main_interface0_bus_dat_r { 32'00000000000000000000000000000000 \builder_shared_dat_r } + connect \main_interface1_bus_dat_r { 32'00000000000000000000000000000000 \builder_shared_dat_r } + connect \main_libresocsim_libresoc_ibus_ack $and$ls180.v:5822$1147_Y + connect \main_libresocsim_libresoc_dbus_ack $and$ls180.v:5823$1149_Y + connect \main_libresocsim_libresoc_jtag_wb_ack $and$ls180.v:5824$1151_Y + connect \main_interface0_bus_ack $and$ls180.v:5825$1153_Y + connect \main_interface1_bus_ack $and$ls180.v:5826$1155_Y + connect \main_libresocsim_libresoc_ibus_err $and$ls180.v:5827$1157_Y + connect \main_libresocsim_libresoc_dbus_err $and$ls180.v:5828$1159_Y + connect \main_libresocsim_libresoc_jtag_wb_err $and$ls180.v:5829$1161_Y + connect \main_interface0_bus_err $and$ls180.v:5830$1163_Y + connect \main_interface1_bus_err $and$ls180.v:5831$1165_Y + connect \builder_request { \main_interface1_bus_cyc \main_interface0_bus_cyc \main_libresocsim_libresoc_jtag_wb_cyc \main_libresocsim_libresoc_dbus_cyc \main_libresocsim_libresoc_ibus_cyc } connect \main_libresocsim_ram_bus_adr \builder_shared_adr - connect \main_libresocsim_ram_bus_dat_w \builder_shared_dat_w - connect \main_libresocsim_ram_bus_sel \builder_shared_sel + connect \main_libresocsim_ram_bus_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } + connect \main_libresocsim_ram_bus_sel { 4'0000 \builder_shared_sel } connect \main_libresocsim_ram_bus_stb \builder_shared_stb connect \main_libresocsim_ram_bus_we \builder_shared_we connect \main_libresocsim_ram_bus_cti \builder_shared_cti connect \main_libresocsim_ram_bus_bte \builder_shared_bte connect \main_interface0_ram_bus_adr \builder_shared_adr - connect \main_interface0_ram_bus_dat_w \builder_shared_dat_w - connect \main_interface0_ram_bus_sel \builder_shared_sel + connect \main_interface0_ram_bus_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } + connect \main_interface0_ram_bus_sel { 4'0000 \builder_shared_sel } connect \main_interface0_ram_bus_stb \builder_shared_stb connect \main_interface0_ram_bus_we \builder_shared_we connect \main_interface0_ram_bus_cti \builder_shared_cti connect \main_interface0_ram_bus_bte \builder_shared_bte connect \main_interface1_ram_bus_adr \builder_shared_adr - connect \main_interface1_ram_bus_dat_w \builder_shared_dat_w - connect \main_interface1_ram_bus_sel \builder_shared_sel + connect \main_interface1_ram_bus_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } + connect \main_interface1_ram_bus_sel { 4'0000 \builder_shared_sel } connect \main_interface1_ram_bus_stb \builder_shared_stb connect \main_interface1_ram_bus_we \builder_shared_we connect \main_interface1_ram_bus_cti \builder_shared_cti connect \main_interface1_ram_bus_bte \builder_shared_bte connect \main_interface2_ram_bus_adr \builder_shared_adr - connect \main_interface2_ram_bus_dat_w \builder_shared_dat_w - connect \main_interface2_ram_bus_sel \builder_shared_sel + connect \main_interface2_ram_bus_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } + connect \main_interface2_ram_bus_sel { 4'0000 \builder_shared_sel } connect \main_interface2_ram_bus_stb \builder_shared_stb connect \main_interface2_ram_bus_we \builder_shared_we connect \main_interface2_ram_bus_cti \builder_shared_cti connect \main_interface2_ram_bus_bte \builder_shared_bte - connect \main_libresocsim_libresoc_xics_icp_adr \builder_shared_adr - connect \main_libresocsim_libresoc_xics_icp_dat_w \builder_shared_dat_w - connect \main_libresocsim_libresoc_xics_icp_sel \builder_shared_sel - connect \main_libresocsim_libresoc_xics_icp_stb \builder_shared_stb - connect \main_libresocsim_libresoc_xics_icp_we \builder_shared_we - connect \main_libresocsim_libresoc_xics_icp_cti \builder_shared_cti - connect \main_libresocsim_libresoc_xics_icp_bte \builder_shared_bte - connect \main_libresocsim_libresoc_xics_ics_adr \builder_shared_adr - connect \main_libresocsim_libresoc_xics_ics_dat_w \builder_shared_dat_w - connect \main_libresocsim_libresoc_xics_ics_sel \builder_shared_sel - connect \main_libresocsim_libresoc_xics_ics_stb \builder_shared_stb - connect \main_libresocsim_libresoc_xics_ics_we \builder_shared_we - connect \main_libresocsim_libresoc_xics_ics_cti \builder_shared_cti - connect \main_libresocsim_libresoc_xics_ics_bte \builder_shared_bte - connect \main_wb_sdram_adr \builder_shared_adr - connect \main_wb_sdram_dat_w \builder_shared_dat_w - connect \main_wb_sdram_sel \builder_shared_sel - connect \main_wb_sdram_stb \builder_shared_stb - connect \main_wb_sdram_we \builder_shared_we - connect \main_wb_sdram_cti \builder_shared_cti - connect \main_wb_sdram_bte \builder_shared_bte - connect \builder_libresocsim_wishbone_adr \builder_shared_adr - connect \builder_libresocsim_wishbone_dat_w \builder_shared_dat_w - connect \builder_libresocsim_wishbone_sel \builder_shared_sel - connect \builder_libresocsim_wishbone_stb \builder_shared_stb - connect \builder_libresocsim_wishbone_we \builder_shared_we - connect \builder_libresocsim_wishbone_cti \builder_shared_cti - connect \builder_libresocsim_wishbone_bte \builder_shared_bte - connect \main_libresocsim_ram_bus_cyc $and$ls180.v:5848$1109_Y - connect \main_interface0_ram_bus_cyc $and$ls180.v:5849$1110_Y - connect \main_interface1_ram_bus_cyc $and$ls180.v:5850$1111_Y - connect \main_interface2_ram_bus_cyc $and$ls180.v:5851$1112_Y - connect \main_libresocsim_libresoc_xics_icp_cyc $and$ls180.v:5852$1113_Y - connect \main_libresocsim_libresoc_xics_ics_cyc $and$ls180.v:5853$1114_Y - connect \main_wb_sdram_cyc $and$ls180.v:5854$1115_Y - connect \builder_libresocsim_wishbone_cyc $and$ls180.v:5855$1116_Y - connect \builder_shared_err $or$ls180.v:5856$1123_Y - connect \builder_wait $and$ls180.v:5857$1126_Y - connect \builder_done $eq$ls180.v:5870$1150_Y - connect \builder_csrbank0_sel $eq$ls180.v:5871$1151_Y + connect \main_interface0_converted_interface_adr \builder_shared_adr + connect \main_interface0_converted_interface_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } + connect \main_interface0_converted_interface_sel { 4'0000 \builder_shared_sel } + connect \main_interface0_converted_interface_stb \builder_shared_stb + connect \main_interface0_converted_interface_we \builder_shared_we + connect \main_interface0_converted_interface_cti \builder_shared_cti + connect \main_interface0_converted_interface_bte \builder_shared_bte + connect \main_interface1_converted_interface_adr \builder_shared_adr + connect \main_interface1_converted_interface_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } + connect \main_interface1_converted_interface_sel { 4'0000 \builder_shared_sel } + connect \main_interface1_converted_interface_stb \builder_shared_stb + connect \main_interface1_converted_interface_we \builder_shared_we + connect \main_interface1_converted_interface_cti \builder_shared_cti + connect \main_interface1_converted_interface_bte \builder_shared_bte + connect \main_socbushandler_converted_interface_adr \builder_shared_adr + connect \main_socbushandler_converted_interface_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } + connect \main_socbushandler_converted_interface_sel { 4'0000 \builder_shared_sel } + connect \main_socbushandler_converted_interface_stb \builder_shared_stb + connect \main_socbushandler_converted_interface_we \builder_shared_we + connect \main_socbushandler_converted_interface_cti \builder_shared_cti + connect \main_socbushandler_converted_interface_bte \builder_shared_bte + connect \builder_libresocsim_converted_interface_adr \builder_shared_adr + connect \builder_libresocsim_converted_interface_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } + connect \builder_libresocsim_converted_interface_sel { 4'0000 \builder_shared_sel } + connect \builder_libresocsim_converted_interface_stb \builder_shared_stb + connect \builder_libresocsim_converted_interface_we \builder_shared_we + connect \builder_libresocsim_converted_interface_cti \builder_shared_cti + connect \builder_libresocsim_converted_interface_bte \builder_shared_bte + connect \main_libresocsim_ram_bus_cyc $and$ls180.v:5900$1175_Y + connect \main_interface0_ram_bus_cyc $and$ls180.v:5901$1176_Y + connect \main_interface1_ram_bus_cyc $and$ls180.v:5902$1177_Y + connect \main_interface2_ram_bus_cyc $and$ls180.v:5903$1178_Y + connect \main_interface0_converted_interface_cyc $and$ls180.v:5904$1179_Y + connect \main_interface1_converted_interface_cyc $and$ls180.v:5905$1180_Y + connect \main_socbushandler_converted_interface_cyc $and$ls180.v:5906$1181_Y + connect \builder_libresocsim_converted_interface_cyc $and$ls180.v:5907$1182_Y + connect \builder_shared_err $or$ls180.v:5908$1189_Y + connect \builder_wait $and$ls180.v:5909$1192_Y + connect \builder_done $eq$ls180.v:5922$1216_Y + connect \builder_csrbank0_sel $eq$ls180.v:5923$1217_Y connect \builder_csrbank0_reset0_r \builder_interface0_bank_bus_dat_w [0] - connect \builder_csrbank0_reset0_re $and$ls180.v:5873$1154_Y - connect \builder_csrbank0_reset0_we $and$ls180.v:5874$1158_Y + connect \builder_csrbank0_reset0_re $and$ls180.v:5925$1220_Y + connect \builder_csrbank0_reset0_we $and$ls180.v:5926$1224_Y connect \builder_csrbank0_scratch3_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_scratch3_re $and$ls180.v:5876$1161_Y - connect \builder_csrbank0_scratch3_we $and$ls180.v:5877$1165_Y + connect \builder_csrbank0_scratch3_re $and$ls180.v:5928$1227_Y + connect \builder_csrbank0_scratch3_we $and$ls180.v:5929$1231_Y connect \builder_csrbank0_scratch2_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_scratch2_re $and$ls180.v:5879$1168_Y - connect \builder_csrbank0_scratch2_we $and$ls180.v:5880$1172_Y + connect \builder_csrbank0_scratch2_re $and$ls180.v:5931$1234_Y + connect \builder_csrbank0_scratch2_we $and$ls180.v:5932$1238_Y connect \builder_csrbank0_scratch1_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_scratch1_re $and$ls180.v:5882$1175_Y - connect \builder_csrbank0_scratch1_we $and$ls180.v:5883$1179_Y + connect \builder_csrbank0_scratch1_re $and$ls180.v:5934$1241_Y + connect \builder_csrbank0_scratch1_we $and$ls180.v:5935$1245_Y connect \builder_csrbank0_scratch0_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_scratch0_re $and$ls180.v:5885$1182_Y - connect \builder_csrbank0_scratch0_we $and$ls180.v:5886$1186_Y + connect \builder_csrbank0_scratch0_re $and$ls180.v:5937$1248_Y + connect \builder_csrbank0_scratch0_we $and$ls180.v:5938$1252_Y connect \builder_csrbank0_bus_errors3_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_bus_errors3_re $and$ls180.v:5888$1189_Y - connect \builder_csrbank0_bus_errors3_we $and$ls180.v:5889$1193_Y + connect \builder_csrbank0_bus_errors3_re $and$ls180.v:5940$1255_Y + connect \builder_csrbank0_bus_errors3_we $and$ls180.v:5941$1259_Y connect \builder_csrbank0_bus_errors2_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_bus_errors2_re $and$ls180.v:5891$1196_Y - connect \builder_csrbank0_bus_errors2_we $and$ls180.v:5892$1200_Y + connect \builder_csrbank0_bus_errors2_re $and$ls180.v:5943$1262_Y + connect \builder_csrbank0_bus_errors2_we $and$ls180.v:5944$1266_Y connect \builder_csrbank0_bus_errors1_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_bus_errors1_re $and$ls180.v:5894$1203_Y - connect \builder_csrbank0_bus_errors1_we $and$ls180.v:5895$1207_Y + connect \builder_csrbank0_bus_errors1_re $and$ls180.v:5946$1269_Y + connect \builder_csrbank0_bus_errors1_we $and$ls180.v:5947$1273_Y connect \builder_csrbank0_bus_errors0_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_bus_errors0_re $and$ls180.v:5897$1210_Y - connect \builder_csrbank0_bus_errors0_we $and$ls180.v:5898$1214_Y + connect \builder_csrbank0_bus_errors0_re $and$ls180.v:5949$1276_Y + connect \builder_csrbank0_bus_errors0_we $and$ls180.v:5950$1280_Y connect \builder_csrbank0_reset0_w \main_libresocsim_reset_storage connect \builder_csrbank0_scratch3_w \main_libresocsim_scratch_storage [31:24] connect \builder_csrbank0_scratch2_w \main_libresocsim_scratch_storage [23:16] @@ -283494,39 +285004,39 @@ module \ls180 connect \builder_csrbank0_bus_errors1_w \main_libresocsim_bus_errors_status [15:8] connect \builder_csrbank0_bus_errors0_w \main_libresocsim_bus_errors_status [7:0] connect \main_libresocsim_bus_errors_we \builder_csrbank0_bus_errors0_we - connect \builder_csrbank1_sel $eq$ls180.v:5909$1215_Y + connect \builder_csrbank1_sel $eq$ls180.v:5961$1281_Y connect \builder_csrbank1_oe1_r \builder_interface1_bank_bus_dat_w - connect \builder_csrbank1_oe1_re $and$ls180.v:5911$1218_Y - connect \builder_csrbank1_oe1_we $and$ls180.v:5912$1222_Y + connect \builder_csrbank1_oe1_re $and$ls180.v:5963$1284_Y + connect \builder_csrbank1_oe1_we $and$ls180.v:5964$1288_Y connect \builder_csrbank1_oe0_r \builder_interface1_bank_bus_dat_w - connect \builder_csrbank1_oe0_re $and$ls180.v:5914$1225_Y - connect \builder_csrbank1_oe0_we $and$ls180.v:5915$1229_Y + connect \builder_csrbank1_oe0_re $and$ls180.v:5966$1291_Y + connect \builder_csrbank1_oe0_we $and$ls180.v:5967$1295_Y connect \builder_csrbank1_in1_r \builder_interface1_bank_bus_dat_w - connect \builder_csrbank1_in1_re $and$ls180.v:5917$1232_Y - connect \builder_csrbank1_in1_we $and$ls180.v:5918$1236_Y + connect \builder_csrbank1_in1_re $and$ls180.v:5969$1298_Y + connect \builder_csrbank1_in1_we $and$ls180.v:5970$1302_Y connect \builder_csrbank1_in0_r \builder_interface1_bank_bus_dat_w - connect \builder_csrbank1_in0_re $and$ls180.v:5920$1239_Y - connect \builder_csrbank1_in0_we $and$ls180.v:5921$1243_Y + connect \builder_csrbank1_in0_re $and$ls180.v:5972$1305_Y + connect \builder_csrbank1_in0_we $and$ls180.v:5973$1309_Y connect \builder_csrbank1_out1_r \builder_interface1_bank_bus_dat_w - connect \builder_csrbank1_out1_re $and$ls180.v:5923$1246_Y - connect \builder_csrbank1_out1_we $and$ls180.v:5924$1250_Y + connect \builder_csrbank1_out1_re $and$ls180.v:5975$1312_Y + connect \builder_csrbank1_out1_we $and$ls180.v:5976$1316_Y connect \builder_csrbank1_out0_r \builder_interface1_bank_bus_dat_w - connect \builder_csrbank1_out0_re $and$ls180.v:5926$1253_Y - connect \builder_csrbank1_out0_we $and$ls180.v:5927$1257_Y - connect \builder_csrbank1_oe1_w \main_gpio_oe_storage [15:8] - connect \builder_csrbank1_oe0_w \main_gpio_oe_storage [7:0] - connect \builder_csrbank1_in1_w \main_gpio_status [15:8] - connect \builder_csrbank1_in0_w \main_gpio_status [7:0] - connect \main_gpio_we \builder_csrbank1_in0_we - connect \builder_csrbank1_out1_w \main_gpio_out_storage [15:8] - connect \builder_csrbank1_out0_w \main_gpio_out_storage [7:0] - connect \builder_csrbank2_sel $eq$ls180.v:5935$1258_Y + connect \builder_csrbank1_out0_re $and$ls180.v:5978$1319_Y + connect \builder_csrbank1_out0_we $and$ls180.v:5979$1323_Y + connect \builder_csrbank1_oe1_w \main_gpiotristateasic1_oe_storage [15:8] + connect \builder_csrbank1_oe0_w \main_gpiotristateasic1_oe_storage [7:0] + connect \builder_csrbank1_in1_w \main_gpiotristateasic1_status [15:8] + connect \builder_csrbank1_in0_w \main_gpiotristateasic1_status [7:0] + connect \main_gpiotristateasic1_we \builder_csrbank1_in0_we + connect \builder_csrbank1_out1_w \main_gpiotristateasic1_out_storage [15:8] + connect \builder_csrbank1_out0_w \main_gpiotristateasic1_out_storage [7:0] + connect \builder_csrbank2_sel $eq$ls180.v:5987$1324_Y connect \builder_csrbank2_w0_r \builder_interface2_bank_bus_dat_w [2:0] - connect \builder_csrbank2_w0_re $and$ls180.v:5937$1261_Y - connect \builder_csrbank2_w0_we $and$ls180.v:5938$1265_Y + connect \builder_csrbank2_w0_re $and$ls180.v:5989$1327_Y + connect \builder_csrbank2_w0_we $and$ls180.v:5990$1331_Y connect \builder_csrbank2_r_r \builder_interface2_bank_bus_dat_w [0] - connect \builder_csrbank2_r_re $and$ls180.v:5940$1268_Y - connect \builder_csrbank2_r_we $and$ls180.v:5941$1272_Y + connect \builder_csrbank2_r_re $and$ls180.v:5992$1334_Y + connect \builder_csrbank2_r_we $and$ls180.v:5993$1338_Y connect \main_i2c_scl \main_i2c_storage [0] connect \main_i2c_oe \main_i2c_storage [1] connect \main_i2c_sda0 \main_i2c_storage [2] @@ -283534,34 +285044,34 @@ module \ls180 connect \main_i2c_status \main_i2c_sda1 connect \builder_csrbank2_r_w \main_i2c_status connect \main_i2c_we \builder_csrbank2_r_we - connect \builder_csrbank3_sel $eq$ls180.v:5949$1273_Y + connect \builder_csrbank3_sel $eq$ls180.v:6001$1339_Y connect \builder_csrbank3_enable0_r \builder_interface3_bank_bus_dat_w [0] - connect \builder_csrbank3_enable0_re $and$ls180.v:5951$1276_Y - connect \builder_csrbank3_enable0_we $and$ls180.v:5952$1280_Y + connect \builder_csrbank3_enable0_re $and$ls180.v:6003$1342_Y + connect \builder_csrbank3_enable0_we $and$ls180.v:6004$1346_Y connect \builder_csrbank3_width3_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_width3_re $and$ls180.v:5954$1283_Y - connect \builder_csrbank3_width3_we $and$ls180.v:5955$1287_Y + connect \builder_csrbank3_width3_re $and$ls180.v:6006$1349_Y + connect \builder_csrbank3_width3_we $and$ls180.v:6007$1353_Y connect \builder_csrbank3_width2_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_width2_re $and$ls180.v:5957$1290_Y - connect \builder_csrbank3_width2_we $and$ls180.v:5958$1294_Y + connect \builder_csrbank3_width2_re $and$ls180.v:6009$1356_Y + connect \builder_csrbank3_width2_we $and$ls180.v:6010$1360_Y connect \builder_csrbank3_width1_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_width1_re $and$ls180.v:5960$1297_Y - connect \builder_csrbank3_width1_we $and$ls180.v:5961$1301_Y + connect \builder_csrbank3_width1_re $and$ls180.v:6012$1363_Y + connect \builder_csrbank3_width1_we $and$ls180.v:6013$1367_Y connect \builder_csrbank3_width0_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_width0_re $and$ls180.v:5963$1304_Y - connect \builder_csrbank3_width0_we $and$ls180.v:5964$1308_Y + connect \builder_csrbank3_width0_re $and$ls180.v:6015$1370_Y + connect \builder_csrbank3_width0_we $and$ls180.v:6016$1374_Y connect \builder_csrbank3_period3_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_period3_re $and$ls180.v:5966$1311_Y - connect \builder_csrbank3_period3_we $and$ls180.v:5967$1315_Y + connect \builder_csrbank3_period3_re $and$ls180.v:6018$1377_Y + connect \builder_csrbank3_period3_we $and$ls180.v:6019$1381_Y connect \builder_csrbank3_period2_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_period2_re $and$ls180.v:5969$1318_Y - connect \builder_csrbank3_period2_we $and$ls180.v:5970$1322_Y + connect \builder_csrbank3_period2_re $and$ls180.v:6021$1384_Y + connect \builder_csrbank3_period2_we $and$ls180.v:6022$1388_Y connect \builder_csrbank3_period1_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_period1_re $and$ls180.v:5972$1325_Y - connect \builder_csrbank3_period1_we $and$ls180.v:5973$1329_Y + connect \builder_csrbank3_period1_re $and$ls180.v:6024$1391_Y + connect \builder_csrbank3_period1_we $and$ls180.v:6025$1395_Y connect \builder_csrbank3_period0_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_period0_re $and$ls180.v:5975$1332_Y - connect \builder_csrbank3_period0_we $and$ls180.v:5976$1336_Y + connect \builder_csrbank3_period0_re $and$ls180.v:6027$1398_Y + connect \builder_csrbank3_period0_we $and$ls180.v:6028$1402_Y connect \builder_csrbank3_enable0_w \main_pwm0_enable_storage connect \builder_csrbank3_width3_w \main_pwm0_width_storage [31:24] connect \builder_csrbank3_width2_w \main_pwm0_width_storage [23:16] @@ -283571,34 +285081,34 @@ module \ls180 connect \builder_csrbank3_period2_w \main_pwm0_period_storage [23:16] connect \builder_csrbank3_period1_w \main_pwm0_period_storage [15:8] connect \builder_csrbank3_period0_w \main_pwm0_period_storage [7:0] - connect \builder_csrbank4_sel $eq$ls180.v:5986$1337_Y + connect \builder_csrbank4_sel $eq$ls180.v:6038$1403_Y connect \builder_csrbank4_enable0_r \builder_interface4_bank_bus_dat_w [0] - connect \builder_csrbank4_enable0_re $and$ls180.v:5988$1340_Y - connect \builder_csrbank4_enable0_we $and$ls180.v:5989$1344_Y + connect \builder_csrbank4_enable0_re $and$ls180.v:6040$1406_Y + connect \builder_csrbank4_enable0_we $and$ls180.v:6041$1410_Y connect \builder_csrbank4_width3_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_width3_re $and$ls180.v:5991$1347_Y - connect \builder_csrbank4_width3_we $and$ls180.v:5992$1351_Y + connect \builder_csrbank4_width3_re $and$ls180.v:6043$1413_Y + connect \builder_csrbank4_width3_we $and$ls180.v:6044$1417_Y connect \builder_csrbank4_width2_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_width2_re $and$ls180.v:5994$1354_Y - connect \builder_csrbank4_width2_we $and$ls180.v:5995$1358_Y + connect \builder_csrbank4_width2_re $and$ls180.v:6046$1420_Y + connect \builder_csrbank4_width2_we $and$ls180.v:6047$1424_Y connect \builder_csrbank4_width1_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_width1_re $and$ls180.v:5997$1361_Y - connect \builder_csrbank4_width1_we $and$ls180.v:5998$1365_Y + connect \builder_csrbank4_width1_re $and$ls180.v:6049$1427_Y + connect \builder_csrbank4_width1_we $and$ls180.v:6050$1431_Y connect \builder_csrbank4_width0_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_width0_re $and$ls180.v:6000$1368_Y - connect \builder_csrbank4_width0_we $and$ls180.v:6001$1372_Y + connect \builder_csrbank4_width0_re $and$ls180.v:6052$1434_Y + connect \builder_csrbank4_width0_we $and$ls180.v:6053$1438_Y connect \builder_csrbank4_period3_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_period3_re $and$ls180.v:6003$1375_Y - connect \builder_csrbank4_period3_we $and$ls180.v:6004$1379_Y + connect \builder_csrbank4_period3_re $and$ls180.v:6055$1441_Y + connect \builder_csrbank4_period3_we $and$ls180.v:6056$1445_Y connect \builder_csrbank4_period2_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_period2_re $and$ls180.v:6006$1382_Y - connect \builder_csrbank4_period2_we $and$ls180.v:6007$1386_Y + connect \builder_csrbank4_period2_re $and$ls180.v:6058$1448_Y + connect \builder_csrbank4_period2_we $and$ls180.v:6059$1452_Y connect \builder_csrbank4_period1_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_period1_re $and$ls180.v:6009$1389_Y - connect \builder_csrbank4_period1_we $and$ls180.v:6010$1393_Y + connect \builder_csrbank4_period1_re $and$ls180.v:6061$1455_Y + connect \builder_csrbank4_period1_we $and$ls180.v:6062$1459_Y connect \builder_csrbank4_period0_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_period0_re $and$ls180.v:6012$1396_Y - connect \builder_csrbank4_period0_we $and$ls180.v:6013$1400_Y + connect \builder_csrbank4_period0_re $and$ls180.v:6064$1462_Y + connect \builder_csrbank4_period0_we $and$ls180.v:6065$1466_Y connect \builder_csrbank4_enable0_w \main_pwm1_enable_storage connect \builder_csrbank4_width3_w \main_pwm1_width_storage [31:24] connect \builder_csrbank4_width2_w \main_pwm1_width_storage [23:16] @@ -283608,52 +285118,52 @@ module \ls180 connect \builder_csrbank4_period2_w \main_pwm1_period_storage [23:16] connect \builder_csrbank4_period1_w \main_pwm1_period_storage [15:8] connect \builder_csrbank4_period0_w \main_pwm1_period_storage [7:0] - connect \builder_csrbank5_sel $eq$ls180.v:6023$1401_Y + connect \builder_csrbank5_sel $eq$ls180.v:6075$1467_Y connect \builder_csrbank5_dma_base7_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base7_re $and$ls180.v:6025$1404_Y - connect \builder_csrbank5_dma_base7_we $and$ls180.v:6026$1408_Y + connect \builder_csrbank5_dma_base7_re $and$ls180.v:6077$1470_Y + connect \builder_csrbank5_dma_base7_we $and$ls180.v:6078$1474_Y connect \builder_csrbank5_dma_base6_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base6_re $and$ls180.v:6028$1411_Y - connect \builder_csrbank5_dma_base6_we $and$ls180.v:6029$1415_Y + connect \builder_csrbank5_dma_base6_re $and$ls180.v:6080$1477_Y + connect \builder_csrbank5_dma_base6_we $and$ls180.v:6081$1481_Y connect \builder_csrbank5_dma_base5_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base5_re $and$ls180.v:6031$1418_Y - connect \builder_csrbank5_dma_base5_we $and$ls180.v:6032$1422_Y + connect \builder_csrbank5_dma_base5_re $and$ls180.v:6083$1484_Y + connect \builder_csrbank5_dma_base5_we $and$ls180.v:6084$1488_Y connect \builder_csrbank5_dma_base4_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base4_re $and$ls180.v:6034$1425_Y - connect \builder_csrbank5_dma_base4_we $and$ls180.v:6035$1429_Y + connect \builder_csrbank5_dma_base4_re $and$ls180.v:6086$1491_Y + connect \builder_csrbank5_dma_base4_we $and$ls180.v:6087$1495_Y connect \builder_csrbank5_dma_base3_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base3_re $and$ls180.v:6037$1432_Y - connect \builder_csrbank5_dma_base3_we $and$ls180.v:6038$1436_Y + connect \builder_csrbank5_dma_base3_re $and$ls180.v:6089$1498_Y + connect \builder_csrbank5_dma_base3_we $and$ls180.v:6090$1502_Y connect \builder_csrbank5_dma_base2_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base2_re $and$ls180.v:6040$1439_Y - connect \builder_csrbank5_dma_base2_we $and$ls180.v:6041$1443_Y + connect \builder_csrbank5_dma_base2_re $and$ls180.v:6092$1505_Y + connect \builder_csrbank5_dma_base2_we $and$ls180.v:6093$1509_Y connect \builder_csrbank5_dma_base1_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base1_re $and$ls180.v:6043$1446_Y - connect \builder_csrbank5_dma_base1_we $and$ls180.v:6044$1450_Y + connect \builder_csrbank5_dma_base1_re $and$ls180.v:6095$1512_Y + connect \builder_csrbank5_dma_base1_we $and$ls180.v:6096$1516_Y connect \builder_csrbank5_dma_base0_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base0_re $and$ls180.v:6046$1453_Y - connect \builder_csrbank5_dma_base0_we $and$ls180.v:6047$1457_Y + connect \builder_csrbank5_dma_base0_re $and$ls180.v:6098$1519_Y + connect \builder_csrbank5_dma_base0_we $and$ls180.v:6099$1523_Y connect \builder_csrbank5_dma_length3_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_length3_re $and$ls180.v:6049$1460_Y - connect \builder_csrbank5_dma_length3_we $and$ls180.v:6050$1464_Y + connect \builder_csrbank5_dma_length3_re $and$ls180.v:6101$1526_Y + connect \builder_csrbank5_dma_length3_we $and$ls180.v:6102$1530_Y connect \builder_csrbank5_dma_length2_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_length2_re $and$ls180.v:6052$1467_Y - connect \builder_csrbank5_dma_length2_we $and$ls180.v:6053$1471_Y + connect \builder_csrbank5_dma_length2_re $and$ls180.v:6104$1533_Y + connect \builder_csrbank5_dma_length2_we $and$ls180.v:6105$1537_Y connect \builder_csrbank5_dma_length1_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_length1_re $and$ls180.v:6055$1474_Y - connect \builder_csrbank5_dma_length1_we $and$ls180.v:6056$1478_Y + connect \builder_csrbank5_dma_length1_re $and$ls180.v:6107$1540_Y + connect \builder_csrbank5_dma_length1_we $and$ls180.v:6108$1544_Y connect \builder_csrbank5_dma_length0_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_length0_re $and$ls180.v:6058$1481_Y - connect \builder_csrbank5_dma_length0_we $and$ls180.v:6059$1485_Y + connect \builder_csrbank5_dma_length0_re $and$ls180.v:6110$1547_Y + connect \builder_csrbank5_dma_length0_we $and$ls180.v:6111$1551_Y connect \builder_csrbank5_dma_enable0_r \builder_interface5_bank_bus_dat_w [0] - connect \builder_csrbank5_dma_enable0_re $and$ls180.v:6061$1488_Y - connect \builder_csrbank5_dma_enable0_we $and$ls180.v:6062$1492_Y + connect \builder_csrbank5_dma_enable0_re $and$ls180.v:6113$1554_Y + connect \builder_csrbank5_dma_enable0_we $and$ls180.v:6114$1558_Y connect \builder_csrbank5_dma_done_r \builder_interface5_bank_bus_dat_w [0] - connect \builder_csrbank5_dma_done_re $and$ls180.v:6064$1495_Y - connect \builder_csrbank5_dma_done_we $and$ls180.v:6065$1499_Y + connect \builder_csrbank5_dma_done_re $and$ls180.v:6116$1561_Y + connect \builder_csrbank5_dma_done_we $and$ls180.v:6117$1565_Y connect \builder_csrbank5_dma_loop0_r \builder_interface5_bank_bus_dat_w [0] - connect \builder_csrbank5_dma_loop0_re $and$ls180.v:6067$1502_Y - connect \builder_csrbank5_dma_loop0_we $and$ls180.v:6068$1506_Y + connect \builder_csrbank5_dma_loop0_re $and$ls180.v:6119$1568_Y + connect \builder_csrbank5_dma_loop0_we $and$ls180.v:6120$1572_Y connect \builder_csrbank5_dma_base7_w \main_sdblock2mem_wishbonedmawriter_base_storage [63:56] connect \builder_csrbank5_dma_base6_w \main_sdblock2mem_wishbonedmawriter_base_storage [55:48] connect \builder_csrbank5_dma_base5_w \main_sdblock2mem_wishbonedmawriter_base_storage [47:40] @@ -283670,106 +285180,106 @@ module \ls180 connect \builder_csrbank5_dma_done_w \main_sdblock2mem_wishbonedmawriter_status connect \main_sdblock2mem_wishbonedmawriter_we \builder_csrbank5_dma_done_we connect \builder_csrbank5_dma_loop0_w \main_sdblock2mem_wishbonedmawriter_loop_storage - connect \builder_csrbank6_sel $eq$ls180.v:6085$1507_Y + connect \builder_csrbank6_sel $eq$ls180.v:6137$1573_Y connect \builder_csrbank6_cmd_argument3_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_argument3_re $and$ls180.v:6087$1510_Y - connect \builder_csrbank6_cmd_argument3_we $and$ls180.v:6088$1514_Y + connect \builder_csrbank6_cmd_argument3_re $and$ls180.v:6139$1576_Y + connect \builder_csrbank6_cmd_argument3_we $and$ls180.v:6140$1580_Y connect \builder_csrbank6_cmd_argument2_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_argument2_re $and$ls180.v:6090$1517_Y - connect \builder_csrbank6_cmd_argument2_we $and$ls180.v:6091$1521_Y + connect \builder_csrbank6_cmd_argument2_re $and$ls180.v:6142$1583_Y + connect \builder_csrbank6_cmd_argument2_we $and$ls180.v:6143$1587_Y connect \builder_csrbank6_cmd_argument1_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_argument1_re $and$ls180.v:6093$1524_Y - connect \builder_csrbank6_cmd_argument1_we $and$ls180.v:6094$1528_Y + connect \builder_csrbank6_cmd_argument1_re $and$ls180.v:6145$1590_Y + connect \builder_csrbank6_cmd_argument1_we $and$ls180.v:6146$1594_Y connect \builder_csrbank6_cmd_argument0_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_argument0_re $and$ls180.v:6096$1531_Y - connect \builder_csrbank6_cmd_argument0_we $and$ls180.v:6097$1535_Y + connect \builder_csrbank6_cmd_argument0_re $and$ls180.v:6148$1597_Y + connect \builder_csrbank6_cmd_argument0_we $and$ls180.v:6149$1601_Y connect \builder_csrbank6_cmd_command3_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_command3_re $and$ls180.v:6099$1538_Y - connect \builder_csrbank6_cmd_command3_we $and$ls180.v:6100$1542_Y + connect \builder_csrbank6_cmd_command3_re $and$ls180.v:6151$1604_Y + connect \builder_csrbank6_cmd_command3_we $and$ls180.v:6152$1608_Y connect \builder_csrbank6_cmd_command2_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_command2_re $and$ls180.v:6102$1545_Y - connect \builder_csrbank6_cmd_command2_we $and$ls180.v:6103$1549_Y + connect \builder_csrbank6_cmd_command2_re $and$ls180.v:6154$1611_Y + connect \builder_csrbank6_cmd_command2_we $and$ls180.v:6155$1615_Y connect \builder_csrbank6_cmd_command1_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_command1_re $and$ls180.v:6105$1552_Y - connect \builder_csrbank6_cmd_command1_we $and$ls180.v:6106$1556_Y + connect \builder_csrbank6_cmd_command1_re $and$ls180.v:6157$1618_Y + connect \builder_csrbank6_cmd_command1_we $and$ls180.v:6158$1622_Y connect \builder_csrbank6_cmd_command0_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_command0_re $and$ls180.v:6108$1559_Y - connect \builder_csrbank6_cmd_command0_we $and$ls180.v:6109$1563_Y + connect \builder_csrbank6_cmd_command0_re $and$ls180.v:6160$1625_Y + connect \builder_csrbank6_cmd_command0_we $and$ls180.v:6161$1629_Y connect \main_sdcore_cmd_send_r \builder_interface6_bank_bus_dat_w [0] - connect \main_sdcore_cmd_send_re $and$ls180.v:6111$1566_Y - connect \main_sdcore_cmd_send_we $and$ls180.v:6112$1570_Y + connect \main_sdcore_cmd_send_re $and$ls180.v:6163$1632_Y + connect \main_sdcore_cmd_send_we $and$ls180.v:6164$1636_Y connect \builder_csrbank6_cmd_response15_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response15_re $and$ls180.v:6114$1573_Y - connect \builder_csrbank6_cmd_response15_we $and$ls180.v:6115$1577_Y + connect \builder_csrbank6_cmd_response15_re $and$ls180.v:6166$1639_Y + connect \builder_csrbank6_cmd_response15_we $and$ls180.v:6167$1643_Y connect \builder_csrbank6_cmd_response14_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response14_re $and$ls180.v:6117$1580_Y - connect \builder_csrbank6_cmd_response14_we $and$ls180.v:6118$1584_Y + connect \builder_csrbank6_cmd_response14_re $and$ls180.v:6169$1646_Y + connect \builder_csrbank6_cmd_response14_we $and$ls180.v:6170$1650_Y connect \builder_csrbank6_cmd_response13_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response13_re $and$ls180.v:6120$1587_Y - connect \builder_csrbank6_cmd_response13_we $and$ls180.v:6121$1591_Y + connect \builder_csrbank6_cmd_response13_re $and$ls180.v:6172$1653_Y + connect \builder_csrbank6_cmd_response13_we $and$ls180.v:6173$1657_Y connect \builder_csrbank6_cmd_response12_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response12_re $and$ls180.v:6123$1594_Y - connect \builder_csrbank6_cmd_response12_we $and$ls180.v:6124$1598_Y + connect \builder_csrbank6_cmd_response12_re $and$ls180.v:6175$1660_Y + connect \builder_csrbank6_cmd_response12_we $and$ls180.v:6176$1664_Y connect \builder_csrbank6_cmd_response11_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response11_re $and$ls180.v:6126$1601_Y - connect \builder_csrbank6_cmd_response11_we $and$ls180.v:6127$1605_Y + connect \builder_csrbank6_cmd_response11_re $and$ls180.v:6178$1667_Y + connect \builder_csrbank6_cmd_response11_we $and$ls180.v:6179$1671_Y connect \builder_csrbank6_cmd_response10_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response10_re $and$ls180.v:6129$1608_Y - connect \builder_csrbank6_cmd_response10_we $and$ls180.v:6130$1612_Y + connect \builder_csrbank6_cmd_response10_re $and$ls180.v:6181$1674_Y + connect \builder_csrbank6_cmd_response10_we $and$ls180.v:6182$1678_Y connect \builder_csrbank6_cmd_response9_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response9_re $and$ls180.v:6132$1615_Y - connect \builder_csrbank6_cmd_response9_we $and$ls180.v:6133$1619_Y + connect \builder_csrbank6_cmd_response9_re $and$ls180.v:6184$1681_Y + connect \builder_csrbank6_cmd_response9_we $and$ls180.v:6185$1685_Y connect \builder_csrbank6_cmd_response8_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response8_re $and$ls180.v:6135$1622_Y - connect \builder_csrbank6_cmd_response8_we $and$ls180.v:6136$1626_Y + connect \builder_csrbank6_cmd_response8_re $and$ls180.v:6187$1688_Y + connect \builder_csrbank6_cmd_response8_we $and$ls180.v:6188$1692_Y connect \builder_csrbank6_cmd_response7_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response7_re $and$ls180.v:6138$1629_Y - connect \builder_csrbank6_cmd_response7_we $and$ls180.v:6139$1633_Y + connect \builder_csrbank6_cmd_response7_re $and$ls180.v:6190$1695_Y + connect \builder_csrbank6_cmd_response7_we $and$ls180.v:6191$1699_Y connect \builder_csrbank6_cmd_response6_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response6_re $and$ls180.v:6141$1636_Y - connect \builder_csrbank6_cmd_response6_we $and$ls180.v:6142$1640_Y + connect \builder_csrbank6_cmd_response6_re $and$ls180.v:6193$1702_Y + connect \builder_csrbank6_cmd_response6_we $and$ls180.v:6194$1706_Y connect \builder_csrbank6_cmd_response5_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response5_re $and$ls180.v:6144$1643_Y - connect \builder_csrbank6_cmd_response5_we $and$ls180.v:6145$1647_Y + connect \builder_csrbank6_cmd_response5_re $and$ls180.v:6196$1709_Y + connect \builder_csrbank6_cmd_response5_we $and$ls180.v:6197$1713_Y connect \builder_csrbank6_cmd_response4_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response4_re $and$ls180.v:6147$1650_Y - connect \builder_csrbank6_cmd_response4_we $and$ls180.v:6148$1654_Y + connect \builder_csrbank6_cmd_response4_re $and$ls180.v:6199$1716_Y + connect \builder_csrbank6_cmd_response4_we $and$ls180.v:6200$1720_Y connect \builder_csrbank6_cmd_response3_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response3_re $and$ls180.v:6150$1657_Y - connect \builder_csrbank6_cmd_response3_we $and$ls180.v:6151$1661_Y + connect \builder_csrbank6_cmd_response3_re $and$ls180.v:6202$1723_Y + connect \builder_csrbank6_cmd_response3_we $and$ls180.v:6203$1727_Y connect \builder_csrbank6_cmd_response2_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response2_re $and$ls180.v:6153$1664_Y - connect \builder_csrbank6_cmd_response2_we $and$ls180.v:6154$1668_Y + connect \builder_csrbank6_cmd_response2_re $and$ls180.v:6205$1730_Y + connect \builder_csrbank6_cmd_response2_we $and$ls180.v:6206$1734_Y connect \builder_csrbank6_cmd_response1_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response1_re $and$ls180.v:6156$1671_Y - connect \builder_csrbank6_cmd_response1_we $and$ls180.v:6157$1675_Y + connect \builder_csrbank6_cmd_response1_re $and$ls180.v:6208$1737_Y + connect \builder_csrbank6_cmd_response1_we $and$ls180.v:6209$1741_Y connect \builder_csrbank6_cmd_response0_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response0_re $and$ls180.v:6159$1678_Y - connect \builder_csrbank6_cmd_response0_we $and$ls180.v:6160$1682_Y + connect \builder_csrbank6_cmd_response0_re $and$ls180.v:6211$1744_Y + connect \builder_csrbank6_cmd_response0_we $and$ls180.v:6212$1748_Y connect \builder_csrbank6_cmd_event_r \builder_interface6_bank_bus_dat_w [3:0] - connect \builder_csrbank6_cmd_event_re $and$ls180.v:6162$1685_Y - connect \builder_csrbank6_cmd_event_we $and$ls180.v:6163$1689_Y + connect \builder_csrbank6_cmd_event_re $and$ls180.v:6214$1751_Y + connect \builder_csrbank6_cmd_event_we $and$ls180.v:6215$1755_Y connect \builder_csrbank6_data_event_r \builder_interface6_bank_bus_dat_w [3:0] - connect \builder_csrbank6_data_event_re $and$ls180.v:6165$1692_Y - connect \builder_csrbank6_data_event_we $and$ls180.v:6166$1696_Y + connect \builder_csrbank6_data_event_re $and$ls180.v:6217$1758_Y + connect \builder_csrbank6_data_event_we $and$ls180.v:6218$1762_Y connect \builder_csrbank6_block_length1_r \builder_interface6_bank_bus_dat_w [1:0] - connect \builder_csrbank6_block_length1_re $and$ls180.v:6168$1699_Y - connect \builder_csrbank6_block_length1_we $and$ls180.v:6169$1703_Y + connect \builder_csrbank6_block_length1_re $and$ls180.v:6220$1765_Y + connect \builder_csrbank6_block_length1_we $and$ls180.v:6221$1769_Y connect \builder_csrbank6_block_length0_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_block_length0_re $and$ls180.v:6171$1706_Y - connect \builder_csrbank6_block_length0_we $and$ls180.v:6172$1710_Y + connect \builder_csrbank6_block_length0_re $and$ls180.v:6223$1772_Y + connect \builder_csrbank6_block_length0_we $and$ls180.v:6224$1776_Y connect \builder_csrbank6_block_count3_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_block_count3_re $and$ls180.v:6174$1713_Y - connect \builder_csrbank6_block_count3_we $and$ls180.v:6175$1717_Y + connect \builder_csrbank6_block_count3_re $and$ls180.v:6226$1779_Y + connect \builder_csrbank6_block_count3_we $and$ls180.v:6227$1783_Y connect \builder_csrbank6_block_count2_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_block_count2_re $and$ls180.v:6177$1720_Y - connect \builder_csrbank6_block_count2_we $and$ls180.v:6178$1724_Y + connect \builder_csrbank6_block_count2_re $and$ls180.v:6229$1786_Y + connect \builder_csrbank6_block_count2_we $and$ls180.v:6230$1790_Y connect \builder_csrbank6_block_count1_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_block_count1_re $and$ls180.v:6180$1727_Y - connect \builder_csrbank6_block_count1_we $and$ls180.v:6181$1731_Y + connect \builder_csrbank6_block_count1_re $and$ls180.v:6232$1793_Y + connect \builder_csrbank6_block_count1_we $and$ls180.v:6233$1797_Y connect \builder_csrbank6_block_count0_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_block_count0_re $and$ls180.v:6183$1734_Y - connect \builder_csrbank6_block_count0_we $and$ls180.v:6184$1738_Y + connect \builder_csrbank6_block_count0_re $and$ls180.v:6235$1800_Y + connect \builder_csrbank6_block_count0_we $and$ls180.v:6236$1804_Y connect \builder_csrbank6_cmd_argument3_w \main_sdcore_cmd_argument_storage [31:24] connect \builder_csrbank6_cmd_argument2_w \main_sdcore_cmd_argument_storage [23:16] connect \builder_csrbank6_cmd_argument1_w \main_sdcore_cmd_argument_storage [15:8] @@ -283805,64 +285315,64 @@ module \ls180 connect \builder_csrbank6_block_count2_w \main_sdcore_block_count_storage [23:16] connect \builder_csrbank6_block_count1_w \main_sdcore_block_count_storage [15:8] connect \builder_csrbank6_block_count0_w \main_sdcore_block_count_storage [7:0] - connect \builder_csrbank7_sel $eq$ls180.v:6220$1739_Y + connect \builder_csrbank7_sel $eq$ls180.v:6272$1805_Y connect \builder_csrbank7_dma_base7_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_base7_re $and$ls180.v:6222$1742_Y - connect \builder_csrbank7_dma_base7_we $and$ls180.v:6223$1746_Y + connect \builder_csrbank7_dma_base7_re $and$ls180.v:6274$1808_Y + connect \builder_csrbank7_dma_base7_we $and$ls180.v:6275$1812_Y connect \builder_csrbank7_dma_base6_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_base6_re $and$ls180.v:6225$1749_Y - connect \builder_csrbank7_dma_base6_we $and$ls180.v:6226$1753_Y + connect \builder_csrbank7_dma_base6_re $and$ls180.v:6277$1815_Y + connect \builder_csrbank7_dma_base6_we $and$ls180.v:6278$1819_Y connect \builder_csrbank7_dma_base5_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_base5_re $and$ls180.v:6228$1756_Y - connect \builder_csrbank7_dma_base5_we $and$ls180.v:6229$1760_Y + connect \builder_csrbank7_dma_base5_re $and$ls180.v:6280$1822_Y + connect \builder_csrbank7_dma_base5_we $and$ls180.v:6281$1826_Y connect \builder_csrbank7_dma_base4_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_base4_re $and$ls180.v:6231$1763_Y - connect \builder_csrbank7_dma_base4_we $and$ls180.v:6232$1767_Y + connect \builder_csrbank7_dma_base4_re $and$ls180.v:6283$1829_Y + connect \builder_csrbank7_dma_base4_we $and$ls180.v:6284$1833_Y connect \builder_csrbank7_dma_base3_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_base3_re $and$ls180.v:6234$1770_Y - connect \builder_csrbank7_dma_base3_we $and$ls180.v:6235$1774_Y + connect \builder_csrbank7_dma_base3_re $and$ls180.v:6286$1836_Y + connect \builder_csrbank7_dma_base3_we $and$ls180.v:6287$1840_Y connect \builder_csrbank7_dma_base2_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_base2_re $and$ls180.v:6237$1777_Y - connect \builder_csrbank7_dma_base2_we $and$ls180.v:6238$1781_Y + connect \builder_csrbank7_dma_base2_re $and$ls180.v:6289$1843_Y + connect \builder_csrbank7_dma_base2_we $and$ls180.v:6290$1847_Y connect \builder_csrbank7_dma_base1_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_base1_re $and$ls180.v:6240$1784_Y - connect \builder_csrbank7_dma_base1_we $and$ls180.v:6241$1788_Y + connect \builder_csrbank7_dma_base1_re $and$ls180.v:6292$1850_Y + connect \builder_csrbank7_dma_base1_we $and$ls180.v:6293$1854_Y connect \builder_csrbank7_dma_base0_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_base0_re $and$ls180.v:6243$1791_Y - connect \builder_csrbank7_dma_base0_we $and$ls180.v:6244$1795_Y + connect \builder_csrbank7_dma_base0_re $and$ls180.v:6295$1857_Y + connect \builder_csrbank7_dma_base0_we $and$ls180.v:6296$1861_Y connect \builder_csrbank7_dma_length3_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_length3_re $and$ls180.v:6246$1798_Y - connect \builder_csrbank7_dma_length3_we $and$ls180.v:6247$1802_Y + connect \builder_csrbank7_dma_length3_re $and$ls180.v:6298$1864_Y + connect \builder_csrbank7_dma_length3_we $and$ls180.v:6299$1868_Y connect \builder_csrbank7_dma_length2_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_length2_re $and$ls180.v:6249$1805_Y - connect \builder_csrbank7_dma_length2_we $and$ls180.v:6250$1809_Y + connect \builder_csrbank7_dma_length2_re $and$ls180.v:6301$1871_Y + connect \builder_csrbank7_dma_length2_we $and$ls180.v:6302$1875_Y connect \builder_csrbank7_dma_length1_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_length1_re $and$ls180.v:6252$1812_Y - connect \builder_csrbank7_dma_length1_we $and$ls180.v:6253$1816_Y + connect \builder_csrbank7_dma_length1_re $and$ls180.v:6304$1878_Y + connect \builder_csrbank7_dma_length1_we $and$ls180.v:6305$1882_Y connect \builder_csrbank7_dma_length0_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_length0_re $and$ls180.v:6255$1819_Y - connect \builder_csrbank7_dma_length0_we $and$ls180.v:6256$1823_Y + connect \builder_csrbank7_dma_length0_re $and$ls180.v:6307$1885_Y + connect \builder_csrbank7_dma_length0_we $and$ls180.v:6308$1889_Y connect \builder_csrbank7_dma_enable0_r \builder_interface7_bank_bus_dat_w [0] - connect \builder_csrbank7_dma_enable0_re $and$ls180.v:6258$1826_Y - connect \builder_csrbank7_dma_enable0_we $and$ls180.v:6259$1830_Y + connect \builder_csrbank7_dma_enable0_re $and$ls180.v:6310$1892_Y + connect \builder_csrbank7_dma_enable0_we $and$ls180.v:6311$1896_Y connect \builder_csrbank7_dma_done_r \builder_interface7_bank_bus_dat_w [0] - connect \builder_csrbank7_dma_done_re $and$ls180.v:6261$1833_Y - connect \builder_csrbank7_dma_done_we $and$ls180.v:6262$1837_Y + connect \builder_csrbank7_dma_done_re $and$ls180.v:6313$1899_Y + connect \builder_csrbank7_dma_done_we $and$ls180.v:6314$1903_Y connect \builder_csrbank7_dma_loop0_r \builder_interface7_bank_bus_dat_w [0] - connect \builder_csrbank7_dma_loop0_re $and$ls180.v:6264$1840_Y - connect \builder_csrbank7_dma_loop0_we $and$ls180.v:6265$1844_Y + connect \builder_csrbank7_dma_loop0_re $and$ls180.v:6316$1906_Y + connect \builder_csrbank7_dma_loop0_we $and$ls180.v:6317$1910_Y connect \builder_csrbank7_dma_offset3_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_offset3_re $and$ls180.v:6267$1847_Y - connect \builder_csrbank7_dma_offset3_we $and$ls180.v:6268$1851_Y + connect \builder_csrbank7_dma_offset3_re $and$ls180.v:6319$1913_Y + connect \builder_csrbank7_dma_offset3_we $and$ls180.v:6320$1917_Y connect \builder_csrbank7_dma_offset2_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_offset2_re $and$ls180.v:6270$1854_Y - connect \builder_csrbank7_dma_offset2_we $and$ls180.v:6271$1858_Y + connect \builder_csrbank7_dma_offset2_re $and$ls180.v:6322$1920_Y + connect \builder_csrbank7_dma_offset2_we $and$ls180.v:6323$1924_Y connect \builder_csrbank7_dma_offset1_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_offset1_re $and$ls180.v:6273$1861_Y - connect \builder_csrbank7_dma_offset1_we $and$ls180.v:6274$1865_Y + connect \builder_csrbank7_dma_offset1_re $and$ls180.v:6325$1927_Y + connect \builder_csrbank7_dma_offset1_we $and$ls180.v:6326$1931_Y connect \builder_csrbank7_dma_offset0_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_offset0_re $and$ls180.v:6276$1868_Y - connect \builder_csrbank7_dma_offset0_we $and$ls180.v:6277$1872_Y + connect \builder_csrbank7_dma_offset0_re $and$ls180.v:6328$1934_Y + connect \builder_csrbank7_dma_offset0_we $and$ls180.v:6329$1938_Y connect \builder_csrbank7_dma_base7_w \main_sdmem2block_dma_base_storage [63:56] connect \builder_csrbank7_dma_base6_w \main_sdmem2block_dma_base_storage [55:48] connect \builder_csrbank7_dma_base5_w \main_sdmem2block_dma_base_storage [47:40] @@ -283884,54 +285394,54 @@ module \ls180 connect \builder_csrbank7_dma_offset1_w \main_sdmem2block_dma_offset_status [15:8] connect \builder_csrbank7_dma_offset0_w \main_sdmem2block_dma_offset_status [7:0] connect \main_sdmem2block_dma_offset_we \builder_csrbank7_dma_offset0_we - connect \builder_csrbank8_sel $eq$ls180.v:6299$1873_Y + connect \builder_csrbank8_sel $eq$ls180.v:6351$1939_Y connect \builder_csrbank8_card_detect_r \builder_interface8_bank_bus_dat_w [0] - connect \builder_csrbank8_card_detect_re $and$ls180.v:6301$1876_Y - connect \builder_csrbank8_card_detect_we $and$ls180.v:6302$1880_Y + connect \builder_csrbank8_card_detect_re $and$ls180.v:6353$1942_Y + connect \builder_csrbank8_card_detect_we $and$ls180.v:6354$1946_Y connect \builder_csrbank8_clocker_divider1_r \builder_interface8_bank_bus_dat_w [0] - connect \builder_csrbank8_clocker_divider1_re $and$ls180.v:6304$1883_Y - connect \builder_csrbank8_clocker_divider1_we $and$ls180.v:6305$1887_Y + connect \builder_csrbank8_clocker_divider1_re $and$ls180.v:6356$1949_Y + connect \builder_csrbank8_clocker_divider1_we $and$ls180.v:6357$1953_Y connect \builder_csrbank8_clocker_divider0_r \builder_interface8_bank_bus_dat_w - connect \builder_csrbank8_clocker_divider0_re $and$ls180.v:6307$1890_Y - connect \builder_csrbank8_clocker_divider0_we $and$ls180.v:6308$1894_Y + connect \builder_csrbank8_clocker_divider0_re $and$ls180.v:6359$1956_Y + connect \builder_csrbank8_clocker_divider0_we $and$ls180.v:6360$1960_Y connect \main_sdphy_init_initialize_r \builder_interface8_bank_bus_dat_w [0] - connect \main_sdphy_init_initialize_re $and$ls180.v:6310$1897_Y - connect \main_sdphy_init_initialize_we $and$ls180.v:6311$1901_Y + connect \main_sdphy_init_initialize_re $and$ls180.v:6362$1963_Y + connect \main_sdphy_init_initialize_we $and$ls180.v:6363$1967_Y connect \builder_csrbank8_card_detect_w \main_sdphy_status connect \main_sdphy_we \builder_csrbank8_card_detect_we connect \builder_csrbank8_clocker_divider1_w \main_sdphy_clocker_storage [8] connect \builder_csrbank8_clocker_divider0_w \main_sdphy_clocker_storage [7:0] - connect \builder_csrbank9_sel $eq$ls180.v:6316$1902_Y + connect \builder_csrbank9_sel $eq$ls180.v:6368$1968_Y connect \builder_csrbank9_dfii_control0_r \builder_interface9_bank_bus_dat_w [3:0] - connect \builder_csrbank9_dfii_control0_re $and$ls180.v:6318$1905_Y - connect \builder_csrbank9_dfii_control0_we $and$ls180.v:6319$1909_Y + connect \builder_csrbank9_dfii_control0_re $and$ls180.v:6370$1971_Y + connect \builder_csrbank9_dfii_control0_we $and$ls180.v:6371$1975_Y connect \builder_csrbank9_dfii_pi0_command0_r \builder_interface9_bank_bus_dat_w [5:0] - connect \builder_csrbank9_dfii_pi0_command0_re $and$ls180.v:6321$1912_Y - connect \builder_csrbank9_dfii_pi0_command0_we $and$ls180.v:6322$1916_Y + connect \builder_csrbank9_dfii_pi0_command0_re $and$ls180.v:6373$1978_Y + connect \builder_csrbank9_dfii_pi0_command0_we $and$ls180.v:6374$1982_Y connect \main_sdram_command_issue_r \builder_interface9_bank_bus_dat_w [0] - connect \main_sdram_command_issue_re $and$ls180.v:6324$1919_Y - connect \main_sdram_command_issue_we $and$ls180.v:6325$1923_Y + connect \main_sdram_command_issue_re $and$ls180.v:6376$1985_Y + connect \main_sdram_command_issue_we $and$ls180.v:6377$1989_Y connect \builder_csrbank9_dfii_pi0_address1_r \builder_interface9_bank_bus_dat_w [4:0] - connect \builder_csrbank9_dfii_pi0_address1_re $and$ls180.v:6327$1926_Y - connect \builder_csrbank9_dfii_pi0_address1_we $and$ls180.v:6328$1930_Y + connect \builder_csrbank9_dfii_pi0_address1_re $and$ls180.v:6379$1992_Y + connect \builder_csrbank9_dfii_pi0_address1_we $and$ls180.v:6380$1996_Y connect \builder_csrbank9_dfii_pi0_address0_r \builder_interface9_bank_bus_dat_w - connect \builder_csrbank9_dfii_pi0_address0_re $and$ls180.v:6330$1933_Y - connect \builder_csrbank9_dfii_pi0_address0_we $and$ls180.v:6331$1937_Y + connect \builder_csrbank9_dfii_pi0_address0_re $and$ls180.v:6382$1999_Y + connect \builder_csrbank9_dfii_pi0_address0_we $and$ls180.v:6383$2003_Y connect \builder_csrbank9_dfii_pi0_baddress0_r \builder_interface9_bank_bus_dat_w [1:0] - connect \builder_csrbank9_dfii_pi0_baddress0_re $and$ls180.v:6333$1940_Y - connect \builder_csrbank9_dfii_pi0_baddress0_we $and$ls180.v:6334$1944_Y + connect \builder_csrbank9_dfii_pi0_baddress0_re $and$ls180.v:6385$2006_Y + connect \builder_csrbank9_dfii_pi0_baddress0_we $and$ls180.v:6386$2010_Y connect \builder_csrbank9_dfii_pi0_wrdata1_r \builder_interface9_bank_bus_dat_w - connect \builder_csrbank9_dfii_pi0_wrdata1_re $and$ls180.v:6336$1947_Y - connect \builder_csrbank9_dfii_pi0_wrdata1_we $and$ls180.v:6337$1951_Y + connect \builder_csrbank9_dfii_pi0_wrdata1_re $and$ls180.v:6388$2013_Y + connect \builder_csrbank9_dfii_pi0_wrdata1_we $and$ls180.v:6389$2017_Y connect \builder_csrbank9_dfii_pi0_wrdata0_r \builder_interface9_bank_bus_dat_w - connect \builder_csrbank9_dfii_pi0_wrdata0_re $and$ls180.v:6339$1954_Y - connect \builder_csrbank9_dfii_pi0_wrdata0_we $and$ls180.v:6340$1958_Y + connect \builder_csrbank9_dfii_pi0_wrdata0_re $and$ls180.v:6391$2020_Y + connect \builder_csrbank9_dfii_pi0_wrdata0_we $and$ls180.v:6392$2024_Y connect \builder_csrbank9_dfii_pi0_rddata1_r \builder_interface9_bank_bus_dat_w - connect \builder_csrbank9_dfii_pi0_rddata1_re $and$ls180.v:6342$1961_Y - connect \builder_csrbank9_dfii_pi0_rddata1_we $and$ls180.v:6343$1965_Y + connect \builder_csrbank9_dfii_pi0_rddata1_re $and$ls180.v:6394$2027_Y + connect \builder_csrbank9_dfii_pi0_rddata1_we $and$ls180.v:6395$2031_Y connect \builder_csrbank9_dfii_pi0_rddata0_r \builder_interface9_bank_bus_dat_w - connect \builder_csrbank9_dfii_pi0_rddata0_re $and$ls180.v:6345$1968_Y - connect \builder_csrbank9_dfii_pi0_rddata0_we $and$ls180.v:6346$1972_Y + connect \builder_csrbank9_dfii_pi0_rddata0_re $and$ls180.v:6397$2034_Y + connect \builder_csrbank9_dfii_pi0_rddata0_we $and$ls180.v:6398$2038_Y connect \main_sdram_sel \main_sdram_storage [0] connect \main_sdram_cke \main_sdram_storage [1] connect \main_sdram_odt \main_sdram_storage [2] @@ -283946,28 +285456,28 @@ module \ls180 connect \builder_csrbank9_dfii_pi0_rddata1_w \main_sdram_status [15:8] connect \builder_csrbank9_dfii_pi0_rddata0_w \main_sdram_status [7:0] connect \main_sdram_we \builder_csrbank9_dfii_pi0_rddata0_we - connect \builder_csrbank10_sel $eq$ls180.v:6361$1973_Y + connect \builder_csrbank10_sel $eq$ls180.v:6413$2039_Y connect \builder_csrbank10_control1_r \builder_interface10_bank_bus_dat_w - connect \builder_csrbank10_control1_re $and$ls180.v:6363$1976_Y - connect \builder_csrbank10_control1_we $and$ls180.v:6364$1980_Y + connect \builder_csrbank10_control1_re $and$ls180.v:6415$2042_Y + connect \builder_csrbank10_control1_we $and$ls180.v:6416$2046_Y connect \builder_csrbank10_control0_r \builder_interface10_bank_bus_dat_w - connect \builder_csrbank10_control0_re $and$ls180.v:6366$1983_Y - connect \builder_csrbank10_control0_we $and$ls180.v:6367$1987_Y + connect \builder_csrbank10_control0_re $and$ls180.v:6418$2049_Y + connect \builder_csrbank10_control0_we $and$ls180.v:6419$2053_Y connect \builder_csrbank10_status_r \builder_interface10_bank_bus_dat_w [0] - connect \builder_csrbank10_status_re $and$ls180.v:6369$1990_Y - connect \builder_csrbank10_status_we $and$ls180.v:6370$1994_Y + connect \builder_csrbank10_status_re $and$ls180.v:6421$2056_Y + connect \builder_csrbank10_status_we $and$ls180.v:6422$2060_Y connect \builder_csrbank10_mosi0_r \builder_interface10_bank_bus_dat_w - connect \builder_csrbank10_mosi0_re $and$ls180.v:6372$1997_Y - connect \builder_csrbank10_mosi0_we $and$ls180.v:6373$2001_Y + connect \builder_csrbank10_mosi0_re $and$ls180.v:6424$2063_Y + connect \builder_csrbank10_mosi0_we $and$ls180.v:6425$2067_Y connect \builder_csrbank10_miso_r \builder_interface10_bank_bus_dat_w - connect \builder_csrbank10_miso_re $and$ls180.v:6375$2004_Y - connect \builder_csrbank10_miso_we $and$ls180.v:6376$2008_Y + connect \builder_csrbank10_miso_re $and$ls180.v:6427$2070_Y + connect \builder_csrbank10_miso_we $and$ls180.v:6428$2074_Y connect \builder_csrbank10_cs0_r \builder_interface10_bank_bus_dat_w [0] - connect \builder_csrbank10_cs0_re $and$ls180.v:6378$2011_Y - connect \builder_csrbank10_cs0_we $and$ls180.v:6379$2015_Y + connect \builder_csrbank10_cs0_re $and$ls180.v:6430$2077_Y + connect \builder_csrbank10_cs0_we $and$ls180.v:6431$2081_Y connect \builder_csrbank10_loopback0_r \builder_interface10_bank_bus_dat_w [0] - connect \builder_csrbank10_loopback0_re $and$ls180.v:6381$2018_Y - connect \builder_csrbank10_loopback0_we $and$ls180.v:6382$2022_Y + connect \builder_csrbank10_loopback0_re $and$ls180.v:6433$2084_Y + connect \builder_csrbank10_loopback0_we $and$ls180.v:6434$2088_Y connect \main_spimaster10_length \main_spimaster11_storage [15:8] connect \builder_csrbank10_control1_w \main_spimaster11_storage [15:8] connect \builder_csrbank10_control0_w \main_spimaster11_storage [7:0] @@ -283980,34 +285490,34 @@ module \ls180 connect \main_spimaster20_sel \main_spimaster21_storage connect \builder_csrbank10_cs0_w \main_spimaster21_storage connect \builder_csrbank10_loopback0_w \main_spimaster23_storage - connect \builder_csrbank11_sel $eq$ls180.v:6401$2024_Y + connect \builder_csrbank11_sel $eq$ls180.v:6453$2090_Y connect \builder_csrbank11_control1_r \builder_interface11_bank_bus_dat_w - connect \builder_csrbank11_control1_re $and$ls180.v:6403$2027_Y - connect \builder_csrbank11_control1_we $and$ls180.v:6404$2031_Y + connect \builder_csrbank11_control1_re $and$ls180.v:6455$2093_Y + connect \builder_csrbank11_control1_we $and$ls180.v:6456$2097_Y connect \builder_csrbank11_control0_r \builder_interface11_bank_bus_dat_w - connect \builder_csrbank11_control0_re $and$ls180.v:6406$2034_Y - connect \builder_csrbank11_control0_we $and$ls180.v:6407$2038_Y + connect \builder_csrbank11_control0_re $and$ls180.v:6458$2100_Y + connect \builder_csrbank11_control0_we $and$ls180.v:6459$2104_Y connect \builder_csrbank11_status_r \builder_interface11_bank_bus_dat_w [0] - connect \builder_csrbank11_status_re $and$ls180.v:6409$2041_Y - connect \builder_csrbank11_status_we $and$ls180.v:6410$2045_Y + connect \builder_csrbank11_status_re $and$ls180.v:6461$2107_Y + connect \builder_csrbank11_status_we $and$ls180.v:6462$2111_Y connect \builder_csrbank11_mosi0_r \builder_interface11_bank_bus_dat_w - connect \builder_csrbank11_mosi0_re $and$ls180.v:6412$2048_Y - connect \builder_csrbank11_mosi0_we $and$ls180.v:6413$2052_Y + connect \builder_csrbank11_mosi0_re $and$ls180.v:6464$2114_Y + connect \builder_csrbank11_mosi0_we $and$ls180.v:6465$2118_Y connect \builder_csrbank11_miso_r \builder_interface11_bank_bus_dat_w - connect \builder_csrbank11_miso_re $and$ls180.v:6415$2055_Y - connect \builder_csrbank11_miso_we $and$ls180.v:6416$2059_Y + connect \builder_csrbank11_miso_re $and$ls180.v:6467$2121_Y + connect \builder_csrbank11_miso_we $and$ls180.v:6468$2125_Y connect \builder_csrbank11_cs0_r \builder_interface11_bank_bus_dat_w [0] - connect \builder_csrbank11_cs0_re $and$ls180.v:6418$2062_Y - connect \builder_csrbank11_cs0_we $and$ls180.v:6419$2066_Y + connect \builder_csrbank11_cs0_re $and$ls180.v:6470$2128_Y + connect \builder_csrbank11_cs0_we $and$ls180.v:6471$2132_Y connect \builder_csrbank11_loopback0_r \builder_interface11_bank_bus_dat_w [0] - connect \builder_csrbank11_loopback0_re $and$ls180.v:6421$2069_Y - connect \builder_csrbank11_loopback0_we $and$ls180.v:6422$2073_Y + connect \builder_csrbank11_loopback0_re $and$ls180.v:6473$2135_Y + connect \builder_csrbank11_loopback0_we $and$ls180.v:6474$2139_Y connect \builder_csrbank11_clk_divider1_r \builder_interface11_bank_bus_dat_w - connect \builder_csrbank11_clk_divider1_re $and$ls180.v:6424$2076_Y - connect \builder_csrbank11_clk_divider1_we $and$ls180.v:6425$2080_Y + connect \builder_csrbank11_clk_divider1_re $and$ls180.v:6476$2142_Y + connect \builder_csrbank11_clk_divider1_we $and$ls180.v:6477$2146_Y connect \builder_csrbank11_clk_divider0_r \builder_interface11_bank_bus_dat_w - connect \builder_csrbank11_clk_divider0_re $and$ls180.v:6427$2083_Y - connect \builder_csrbank11_clk_divider0_we $and$ls180.v:6428$2087_Y + connect \builder_csrbank11_clk_divider0_re $and$ls180.v:6479$2149_Y + connect \builder_csrbank11_clk_divider0_we $and$ls180.v:6480$2153_Y connect \main_spisdcard_length1 \main_spisdcard_control_storage [15:8] connect \builder_csrbank11_control1_w \main_spisdcard_control_storage [15:8] connect \builder_csrbank11_control0_w \main_spisdcard_control_storage [7:0] @@ -284022,58 +285532,58 @@ module \ls180 connect \builder_csrbank11_loopback0_w \main_spisdcard_loopback_storage connect \builder_csrbank11_clk_divider1_w \main_spimaster1_storage [15:8] connect \builder_csrbank11_clk_divider0_w \main_spimaster1_storage [7:0] - connect \builder_csrbank12_sel $eq$ls180.v:6449$2089_Y + connect \builder_csrbank12_sel $eq$ls180.v:6501$2155_Y connect \builder_csrbank12_load3_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_load3_re $and$ls180.v:6451$2092_Y - connect \builder_csrbank12_load3_we $and$ls180.v:6452$2096_Y + connect \builder_csrbank12_load3_re $and$ls180.v:6503$2158_Y + connect \builder_csrbank12_load3_we $and$ls180.v:6504$2162_Y connect \builder_csrbank12_load2_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_load2_re $and$ls180.v:6454$2099_Y - connect \builder_csrbank12_load2_we $and$ls180.v:6455$2103_Y + connect \builder_csrbank12_load2_re $and$ls180.v:6506$2165_Y + connect \builder_csrbank12_load2_we $and$ls180.v:6507$2169_Y connect \builder_csrbank12_load1_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_load1_re $and$ls180.v:6457$2106_Y - connect \builder_csrbank12_load1_we $and$ls180.v:6458$2110_Y + connect \builder_csrbank12_load1_re $and$ls180.v:6509$2172_Y + connect \builder_csrbank12_load1_we $and$ls180.v:6510$2176_Y connect \builder_csrbank12_load0_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_load0_re $and$ls180.v:6460$2113_Y - connect \builder_csrbank12_load0_we $and$ls180.v:6461$2117_Y + connect \builder_csrbank12_load0_re $and$ls180.v:6512$2179_Y + connect \builder_csrbank12_load0_we $and$ls180.v:6513$2183_Y connect \builder_csrbank12_reload3_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_reload3_re $and$ls180.v:6463$2120_Y - connect \builder_csrbank12_reload3_we $and$ls180.v:6464$2124_Y + connect \builder_csrbank12_reload3_re $and$ls180.v:6515$2186_Y + connect \builder_csrbank12_reload3_we $and$ls180.v:6516$2190_Y connect \builder_csrbank12_reload2_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_reload2_re $and$ls180.v:6466$2127_Y - connect \builder_csrbank12_reload2_we $and$ls180.v:6467$2131_Y + connect \builder_csrbank12_reload2_re $and$ls180.v:6518$2193_Y + connect \builder_csrbank12_reload2_we $and$ls180.v:6519$2197_Y connect \builder_csrbank12_reload1_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_reload1_re $and$ls180.v:6469$2134_Y - connect \builder_csrbank12_reload1_we $and$ls180.v:6470$2138_Y + connect \builder_csrbank12_reload1_re $and$ls180.v:6521$2200_Y + connect \builder_csrbank12_reload1_we $and$ls180.v:6522$2204_Y connect \builder_csrbank12_reload0_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_reload0_re $and$ls180.v:6472$2141_Y - connect \builder_csrbank12_reload0_we $and$ls180.v:6473$2145_Y + connect \builder_csrbank12_reload0_re $and$ls180.v:6524$2207_Y + connect \builder_csrbank12_reload0_we $and$ls180.v:6525$2211_Y connect \builder_csrbank12_en0_r \builder_interface12_bank_bus_dat_w [0] - connect \builder_csrbank12_en0_re $and$ls180.v:6475$2148_Y - connect \builder_csrbank12_en0_we $and$ls180.v:6476$2152_Y + connect \builder_csrbank12_en0_re $and$ls180.v:6527$2214_Y + connect \builder_csrbank12_en0_we $and$ls180.v:6528$2218_Y connect \builder_csrbank12_update_value0_r \builder_interface12_bank_bus_dat_w [0] - connect \builder_csrbank12_update_value0_re $and$ls180.v:6478$2155_Y - connect \builder_csrbank12_update_value0_we $and$ls180.v:6479$2159_Y + connect \builder_csrbank12_update_value0_re $and$ls180.v:6530$2221_Y + connect \builder_csrbank12_update_value0_we $and$ls180.v:6531$2225_Y connect \builder_csrbank12_value3_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_value3_re $and$ls180.v:6481$2162_Y - connect \builder_csrbank12_value3_we $and$ls180.v:6482$2166_Y + connect \builder_csrbank12_value3_re $and$ls180.v:6533$2228_Y + connect \builder_csrbank12_value3_we $and$ls180.v:6534$2232_Y connect \builder_csrbank12_value2_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_value2_re $and$ls180.v:6484$2169_Y - connect \builder_csrbank12_value2_we $and$ls180.v:6485$2173_Y + connect \builder_csrbank12_value2_re $and$ls180.v:6536$2235_Y + connect \builder_csrbank12_value2_we $and$ls180.v:6537$2239_Y connect \builder_csrbank12_value1_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_value1_re $and$ls180.v:6487$2176_Y - connect \builder_csrbank12_value1_we $and$ls180.v:6488$2180_Y + connect \builder_csrbank12_value1_re $and$ls180.v:6539$2242_Y + connect \builder_csrbank12_value1_we $and$ls180.v:6540$2246_Y connect \builder_csrbank12_value0_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_value0_re $and$ls180.v:6490$2183_Y - connect \builder_csrbank12_value0_we $and$ls180.v:6491$2187_Y + connect \builder_csrbank12_value0_re $and$ls180.v:6542$2249_Y + connect \builder_csrbank12_value0_we $and$ls180.v:6543$2253_Y connect \main_libresocsim_eventmanager_status_r \builder_interface12_bank_bus_dat_w [0] - connect \main_libresocsim_eventmanager_status_re $and$ls180.v:6493$2190_Y - connect \main_libresocsim_eventmanager_status_we $and$ls180.v:6494$2194_Y + connect \main_libresocsim_eventmanager_status_re $and$ls180.v:6545$2256_Y + connect \main_libresocsim_eventmanager_status_we $and$ls180.v:6546$2260_Y connect \main_libresocsim_eventmanager_pending_r \builder_interface12_bank_bus_dat_w [0] - connect \main_libresocsim_eventmanager_pending_re $and$ls180.v:6496$2197_Y - connect \main_libresocsim_eventmanager_pending_we $and$ls180.v:6497$2201_Y + connect \main_libresocsim_eventmanager_pending_re $and$ls180.v:6548$2263_Y + connect \main_libresocsim_eventmanager_pending_we $and$ls180.v:6549$2267_Y connect \builder_csrbank12_ev_enable0_r \builder_interface12_bank_bus_dat_w [0] - connect \builder_csrbank12_ev_enable0_re $and$ls180.v:6499$2204_Y - connect \builder_csrbank12_ev_enable0_we $and$ls180.v:6500$2208_Y + connect \builder_csrbank12_ev_enable0_re $and$ls180.v:6551$2270_Y + connect \builder_csrbank12_ev_enable0_we $and$ls180.v:6552$2274_Y connect \builder_csrbank12_load3_w \main_libresocsim_load_storage [31:24] connect \builder_csrbank12_load2_w \main_libresocsim_load_storage [23:16] connect \builder_csrbank12_load1_w \main_libresocsim_load_storage [15:8] @@ -284090,31 +285600,31 @@ module \ls180 connect \builder_csrbank12_value0_w \main_libresocsim_value_status [7:0] connect \main_libresocsim_value_we \builder_csrbank12_value0_we connect \builder_csrbank12_ev_enable0_w \main_libresocsim_eventmanager_storage - connect \builder_csrbank13_sel $eq$ls180.v:6517$2209_Y + connect \builder_csrbank13_sel $eq$ls180.v:6569$2275_Y connect \main_uart_rxtx_r \builder_interface13_bank_bus_dat_w - connect \main_uart_rxtx_re $and$ls180.v:6519$2212_Y - connect \main_uart_rxtx_we $and$ls180.v:6520$2216_Y + connect \main_uart_rxtx_re $and$ls180.v:6571$2278_Y + connect \main_uart_rxtx_we $and$ls180.v:6572$2282_Y connect \builder_csrbank13_txfull_r \builder_interface13_bank_bus_dat_w [0] - connect \builder_csrbank13_txfull_re $and$ls180.v:6522$2219_Y - connect \builder_csrbank13_txfull_we $and$ls180.v:6523$2223_Y + connect \builder_csrbank13_txfull_re $and$ls180.v:6574$2285_Y + connect \builder_csrbank13_txfull_we $and$ls180.v:6575$2289_Y connect \builder_csrbank13_rxempty_r \builder_interface13_bank_bus_dat_w [0] - connect \builder_csrbank13_rxempty_re $and$ls180.v:6525$2226_Y - connect \builder_csrbank13_rxempty_we $and$ls180.v:6526$2230_Y + connect \builder_csrbank13_rxempty_re $and$ls180.v:6577$2292_Y + connect \builder_csrbank13_rxempty_we $and$ls180.v:6578$2296_Y connect \main_uart_eventmanager_status_r \builder_interface13_bank_bus_dat_w [1:0] - connect \main_uart_eventmanager_status_re $and$ls180.v:6528$2233_Y - connect \main_uart_eventmanager_status_we $and$ls180.v:6529$2237_Y + connect \main_uart_eventmanager_status_re $and$ls180.v:6580$2299_Y + connect \main_uart_eventmanager_status_we $and$ls180.v:6581$2303_Y connect \main_uart_eventmanager_pending_r \builder_interface13_bank_bus_dat_w [1:0] - connect \main_uart_eventmanager_pending_re $and$ls180.v:6531$2240_Y - connect \main_uart_eventmanager_pending_we $and$ls180.v:6532$2244_Y + connect \main_uart_eventmanager_pending_re $and$ls180.v:6583$2306_Y + connect \main_uart_eventmanager_pending_we $and$ls180.v:6584$2310_Y connect \builder_csrbank13_ev_enable0_r \builder_interface13_bank_bus_dat_w [1:0] - connect \builder_csrbank13_ev_enable0_re $and$ls180.v:6534$2247_Y - connect \builder_csrbank13_ev_enable0_we $and$ls180.v:6535$2251_Y + connect \builder_csrbank13_ev_enable0_re $and$ls180.v:6586$2313_Y + connect \builder_csrbank13_ev_enable0_we $and$ls180.v:6587$2317_Y connect \builder_csrbank13_txempty_r \builder_interface13_bank_bus_dat_w [0] - connect \builder_csrbank13_txempty_re $and$ls180.v:6537$2254_Y - connect \builder_csrbank13_txempty_we $and$ls180.v:6538$2258_Y + connect \builder_csrbank13_txempty_re $and$ls180.v:6589$2320_Y + connect \builder_csrbank13_txempty_we $and$ls180.v:6590$2324_Y connect \builder_csrbank13_rxfull_r \builder_interface13_bank_bus_dat_w [0] - connect \builder_csrbank13_rxfull_re $and$ls180.v:6540$2261_Y - connect \builder_csrbank13_rxfull_we $and$ls180.v:6541$2265_Y + connect \builder_csrbank13_rxfull_re $and$ls180.v:6592$2327_Y + connect \builder_csrbank13_rxfull_we $and$ls180.v:6593$2331_Y connect \builder_csrbank13_txfull_w \main_uart_txfull_status connect \main_uart_txfull_we \builder_csrbank13_txfull_we connect \builder_csrbank13_rxempty_w \main_uart_rxempty_status @@ -284124,19 +285634,19 @@ module \ls180 connect \main_uart_txempty_we \builder_csrbank13_txempty_we connect \builder_csrbank13_rxfull_w \main_uart_rxfull_status connect \main_uart_rxfull_we \builder_csrbank13_rxfull_we - connect \builder_csrbank14_sel $eq$ls180.v:6551$2266_Y + connect \builder_csrbank14_sel $eq$ls180.v:6603$2332_Y connect \builder_csrbank14_tuning_word3_r \builder_interface14_bank_bus_dat_w - connect \builder_csrbank14_tuning_word3_re $and$ls180.v:6553$2269_Y - connect \builder_csrbank14_tuning_word3_we $and$ls180.v:6554$2273_Y + connect \builder_csrbank14_tuning_word3_re $and$ls180.v:6605$2335_Y + connect \builder_csrbank14_tuning_word3_we $and$ls180.v:6606$2339_Y connect \builder_csrbank14_tuning_word2_r \builder_interface14_bank_bus_dat_w - connect \builder_csrbank14_tuning_word2_re $and$ls180.v:6556$2276_Y - connect \builder_csrbank14_tuning_word2_we $and$ls180.v:6557$2280_Y + connect \builder_csrbank14_tuning_word2_re $and$ls180.v:6608$2342_Y + connect \builder_csrbank14_tuning_word2_we $and$ls180.v:6609$2346_Y connect \builder_csrbank14_tuning_word1_r \builder_interface14_bank_bus_dat_w - connect \builder_csrbank14_tuning_word1_re $and$ls180.v:6559$2283_Y - connect \builder_csrbank14_tuning_word1_we $and$ls180.v:6560$2287_Y + connect \builder_csrbank14_tuning_word1_re $and$ls180.v:6611$2349_Y + connect \builder_csrbank14_tuning_word1_we $and$ls180.v:6612$2353_Y connect \builder_csrbank14_tuning_word0_r \builder_interface14_bank_bus_dat_w - connect \builder_csrbank14_tuning_word0_re $and$ls180.v:6562$2290_Y - connect \builder_csrbank14_tuning_word0_we $and$ls180.v:6563$2294_Y + connect \builder_csrbank14_tuning_word0_re $and$ls180.v:6614$2356_Y + connect \builder_csrbank14_tuning_word0_we $and$ls180.v:6615$2360_Y connect \builder_csrbank14_tuning_word3_w \main_uart_phy_storage [31:24] connect \builder_csrbank14_tuning_word2_w \main_uart_phy_storage [23:16] connect \builder_csrbank14_tuning_word1_w \main_uart_phy_storage [15:8] @@ -284190,7 +285700,7 @@ module \ls180 connect \builder_interface12_bank_bus_dat_w \builder_csr_interconnect_dat_w connect \builder_interface13_bank_bus_dat_w \builder_csr_interconnect_dat_w connect \builder_interface14_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_csr_interconnect_dat_r $or$ls180.v:6617$2308_Y + connect \builder_csr_interconnect_dat_r $or$ls180.v:6669$2374_Y connect \sdrio_clk \sys_clk_1 connect \sdrio_clk_1 \sys_clk_1 connect \sdrio_clk_2 \sys_clk_1 @@ -284267,26 +285777,26 @@ module \ls180 connect \sdrio_clk_66 \sys_clk_1 connect \sdrio_clk_67 \sys_clk_1 connect \sdrio_clk_68 \sys_clk_1 - connect \main_libresocsim_dat_r $memrd$\mem$ls180.v:10172$2771_DATA - connect \main_sram0_dat_r $memrd$\mem_1$ls180.v:10192$2785_DATA - connect \main_sram1_dat_r $memrd$\mem_2$ls180.v:10212$2799_DATA - connect \main_sram2_dat_r $memrd$\mem_3$ls180.v:10232$2813_DATA + connect \main_libresocsim_dat_r $memrd$\mem$ls180.v:10247$2850_DATA + connect \main_sram0_dat_r $memrd$\mem_1$ls180.v:10275$2876_DATA + connect \main_sram1_dat_r $memrd$\mem_2$ls180.v:10303$2902_DATA + connect \main_sram2_dat_r $memrd$\mem_3$ls180.v:10331$2928_DATA connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r \memdat - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage$ls180.v:10250$2820_DATA + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage$ls180.v:10349$2935_DATA connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r \memdat_1 - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_1$ls180.v:10264$2827_DATA + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_1$ls180.v:10363$2942_DATA connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r \memdat_2 - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_2$ls180.v:10278$2834_DATA + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_2$ls180.v:10377$2949_DATA connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r \memdat_3 - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_3$ls180.v:10292$2841_DATA + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_3$ls180.v:10391$2956_DATA connect \main_uart_tx_fifo_wrport_dat_r \memdat_4 connect \main_uart_tx_fifo_rdport_dat_r \memdat_5 connect \main_uart_rx_fifo_wrport_dat_r \memdat_6 connect \main_uart_rx_fifo_rdport_dat_r \memdat_7 connect \main_sdblock2mem_fifo_wrport_dat_r \memdat_8 - connect \main_sdblock2mem_fifo_rdport_dat_r $memrd$\storage_6$ls180.v:10340$2862_DATA + connect \main_sdblock2mem_fifo_rdport_dat_r $memrd$\storage_6$ls180.v:10439$2977_DATA connect \main_sdmem2block_fifo_wrport_dat_r \memdat_9 - connect \main_sdmem2block_fifo_rdport_dat_r $memrd$\storage_7$ls180.v:10354$2869_DATA + connect \main_sdmem2block_fifo_rdport_dat_r $memrd$\storage_7$ls180.v:10453$2984_DATA end attribute \src "libresoc.v:135159.1-135217.10" attribute \cells_not_processed 1 -- 2.30.2