From a4d4e704dbebe72d46c0a2dd9137a6746f7abc55 Mon Sep 17 00:00:00 2001
From: Dmitry Selyutin <ghostmansd@gmail.com>
Date: Sun, 18 Sep 2022 11:46:49 +0300
Subject: [PATCH] power_insn: decouple cr_op modes

---
 src/openpower/decoder/power_insn.py | 200 +++++++++++++++-------------
 1 file changed, 105 insertions(+), 95 deletions(-)

diff --git a/src/openpower/decoder/power_insn.py b/src/openpower/decoder/power_insn.py
index a0fcf49c..02028a36 100644
--- a/src/openpower/decoder/power_insn.py
+++ b/src/openpower/decoder/power_insn.py
@@ -1589,101 +1589,111 @@ class LDSTIdxRM(LDSTIdxBaseRM):
     prrc0: LDSTIdxPredResultRc0RM
 
 
-class CROpRM(BaseRM):
-    class simple(BaseRM):
-        """cr_op: simple mode"""
-        sz: BaseRM[6]
-        SNZ: BaseRM[7]
-        RG: BaseRM[20]
-        dz: BaseRM[22]
-
-        @property
-        def specifiers(self):
-            if self.dz:
-                yield f"dz"
-            if self.sz:
-                yield f"sz"
-            yield from super().specifiers
-
-    class smr(BaseRM):
-        """cr_op: scalar reduce mode (mapreduce), SUBVL=1"""
-        sz: BaseRM[6]
-        SNZ: BaseRM[7]
-        RG: BaseRM[20]
-
-        @property
-        def specifiers(self):
-            if self.sz:
-                yield f"sz"
-            yield from super().specifiers
-
-    class svmr(BaseRM):
-        """cr_op: subvector reduce mode, SUBVL>1"""
-        zz: BaseRM[6]
-        SNZ: BaseRM[7]
-        RG: BaseRM[20]
-        SVM: BaseRM[22]
-        dz: BaseRM[6]
-        sz: BaseRM[6]
-
-        @property
-        def specifiers(self):
-            if self.zz:
-                yield f"zz"
-            yield from super().specifiers
-
-    class reserved(BaseRM):
-        """cr_op: reserved"""
-        zz: BaseRM[6]
-        SNZ: BaseRM[7]
-        RG: BaseRM[20]
-        dz: BaseRM[6]
-        sz: BaseRM[6]
-
-        @property
-        def specifiers(self):
-            if self.zz:
-                yield f"zz"
-            yield from super().specifiers
-
-    class ff3(BaseRM):
-        """cr_op: ffirst 3-bit mode"""
-        zz: BaseRM[6]
-        SNZ: BaseRM[7]
-        VLI: BaseRM[20]
-        inv: BaseRM[21]
-        CR: BaseRM[22, 23]
-        dz: BaseRM[6]
-        sz: BaseRM[6]
-
-        @property
-        def specifiers(self):
-            if self.zz:
-                yield f"zz"
-            yield from super().specifiers
-
-    class ff5(BaseRM):
-        """cr_op: ffirst 5-bit mode"""
-        sz: BaseRM[6]
-        SNZ: BaseRM[7]
-        VLI: BaseRM[20]
-        inv: BaseRM[21]
-        dz: BaseRM[22]
-
-        @property
-        def specifiers(self):
-            if self.dz:
-                yield f"dz"
-            if self.sz:
-                yield f"sz"
-            yield from super().specifiers
-
-    simple: simple
-    smr: smr
-    svmr: svmr
-    reserved: reserved
-    ff3: ff3
-    ff5: ff5
+class CROpBaseRM(BaseRM):
+    pass
+
+
+class CROpSimpleRM(CROpBaseRM):
+    """cr_op: simple mode"""
+    sz: BaseRM[6]
+    SNZ: BaseRM[7]
+    RG: BaseRM[20]
+    dz: BaseRM[22]
+
+    @property
+    def specifiers(self):
+        if self.dz:
+            yield f"dz"
+        if self.sz:
+            yield f"sz"
+        yield from super().specifiers
+
+
+class CROpScalarReduceRM(CROpBaseRM):
+    """cr_op: scalar reduce mode (mapreduce), SUBVL=1"""
+    sz: BaseRM[6]
+    SNZ: BaseRM[7]
+    RG: BaseRM[20]
+
+    @property
+    def specifiers(self):
+        if self.sz:
+            yield f"sz"
+        yield from super().specifiers
+
+
+class CROpSubvectorReduceRM(CROpBaseRM):
+    """cr_op: subvector reduce mode, SUBVL>1"""
+    zz: BaseRM[6]
+    SNZ: BaseRM[7]
+    RG: BaseRM[20]
+    SVM: BaseRM[22]
+    dz: BaseRM[6]
+    sz: BaseRM[6]
+
+    @property
+    def specifiers(self):
+        if self.zz:
+            yield f"zz"
+        yield from super().specifiers
+
+
+class CROpReservedRM(CROpBaseRM):
+    """cr_op: reserved"""
+    zz: BaseRM[6]
+    SNZ: BaseRM[7]
+    RG: BaseRM[20]
+    dz: BaseRM[6]
+    sz: BaseRM[6]
+
+    @property
+    def specifiers(self):
+        if self.zz:
+            yield f"zz"
+        yield from super().specifiers
+
+
+class CROpFailFirst3RM(CROpBaseRM):
+    """cr_op: ffirst 3-bit mode"""
+    zz: BaseRM[6]
+    SNZ: BaseRM[7]
+    VLI: BaseRM[20]
+    inv: BaseRM[21]
+    CR: BaseRM[22, 23]
+    dz: BaseRM[6]
+    sz: BaseRM[6]
+
+    @property
+    def specifiers(self):
+        if self.zz:
+            yield f"zz"
+        yield from super().specifiers
+
+
+class CROpFailFirst5RM(CROpBaseRM):
+    """cr_op: ffirst 5-bit mode"""
+    sz: BaseRM[6]
+    SNZ: BaseRM[7]
+    VLI: BaseRM[20]
+    inv: BaseRM[21]
+    dz: BaseRM[22]
+
+    @property
+    def specifiers(self):
+        if self.dz:
+            yield f"dz"
+        if self.sz:
+            yield f"sz"
+        yield from super().specifiers
+
+
+class CROpRM(CROpBaseRM):
+    simple: CROpSimpleRM
+    smr: CROpScalarReduceRM
+    svmr: CROpSubvectorReduceRM
+    reserved: CROpReservedRM
+    ff3: CROpFailFirst3RM
+    ff5: CROpFailFirst5RM
 
 
 class BranchBaseRM(BaseRM):
-- 
2.30.2