From a4e7b721f9457cc359512806d6703d7cc222e8f2 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 21 Mar 2021 18:03:29 +0000 Subject: [PATCH] more TODO comments --- src/soc/simple/issuer.py | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py index 4d8638aa..0fca861b 100644 --- a/src/soc/simple/issuer.py +++ b/src/soc/simple/issuer.py @@ -387,10 +387,17 @@ class TestIssuerInternal(Elaboratable): # INT-src sregread, sinvert, sunary = get_predint(m, srcpred) # INT-dst dregread, dinvert, dunary = get_predint(m, dstpred) # TODO read INT-src and INT-dst into self.srcmask+dstmask + # has to cope with first one then the other + # FSM-triggered-int-read + # comb += int_pred.addr.eq(d_reg.addr) + # comb += int_pred.ren.eq(1) + # FSM-1-clock-later + # comb += d_reg.data.eq(self.int_r.data_o) # elif predmode == CR: # CR-src sidx, sinvert = get_predcr(m, srcpred) # CR-dst didx, dinvert = get_predcr(m, dstpred) # TODO read CR-src and CR-dst into self.srcmask+dstmask with loop + # has to cope with first one then the other # for cr_idx = FSM-state-loop(0..VL-1): # FSM-state-trigger-CR-read: # cr_ren = (1<<7-(cr_idx+SVP64CROffs.CRPred)) -- 2.30.2