From a4f7613fd1b07ef070252822bc6be0b030fedf96 Mon Sep 17 00:00:00 2001
From: Michael Nolan <mtnolan2640@gmail.com>
Date: Sat, 29 Feb 2020 14:32:18 -0500
Subject: [PATCH] Move decoder.py to power_major_decoder.py

---
 .gitignore                                               | 1 +
 src/decoder/{decoder.py => power_major_decoder.py}       | 2 +-
 .../{test_decoder.py => test_power_major_decoder.py}     | 9 +++++----
 3 files changed, 7 insertions(+), 5 deletions(-)
 rename src/decoder/{decoder.py => power_major_decoder.py} (96%)
 rename src/decoder/test/{test_decoder.py => test_power_major_decoder.py} (84%)

diff --git a/.gitignore b/.gitignore
index 54746077..c5947d94 100644
--- a/.gitignore
+++ b/.gitignore
@@ -8,3 +8,4 @@ Waveforms
 !**/Waveforms/.gitkeep
 *.egg-info
 *.il
+**/*.gtkw
diff --git a/src/decoder/decoder.py b/src/decoder/power_major_decoder.py
similarity index 96%
rename from src/decoder/decoder.py
rename to src/decoder/power_major_decoder.py
index 6aa96d61..c71fa155 100644
--- a/src/decoder/decoder.py
+++ b/src/decoder/power_major_decoder.py
@@ -31,7 +31,7 @@ def get_csv(name):
 
 major_opcodes = get_csv("major.csv")
 
-class PowerDecoder(Elaboratable):
+class PowerMajorDecoder(Elaboratable):
     def __init__(self):
         self.opcode_in = Signal(6, reset_less=True)
 
diff --git a/src/decoder/test/test_decoder.py b/src/decoder/test/test_power_major_decoder.py
similarity index 84%
rename from src/decoder/test/test_decoder.py
rename to src/decoder/test/test_power_major_decoder.py
index 222dedab..05d9b13c 100644
--- a/src/decoder/test/test_decoder.py
+++ b/src/decoder/test/test_power_major_decoder.py
@@ -5,7 +5,8 @@ from nmigen.cli import rtlil
 import sys
 import unittest
 sys.path.append("../")
-from decoder import PowerDecoder, Function, InternalOp, major_opcodes
+from power_major_decoder import (PowerMajorDecoder, Function,
+                                InternalOp, major_opcodes)
 
 class DecoderTestCase(FHDLTestCase):
     def test_function_unit(self):
@@ -15,7 +16,7 @@ class DecoderTestCase(FHDLTestCase):
         function_unit = Signal(Function)
         internal_op = Signal(InternalOp)
 
-        m.submodules.dut = dut = PowerDecoder()
+        m.submodules.dut = dut = PowerMajorDecoder()
         comb += [dut.opcode_in.eq(opcode),
                  function_unit.eq(dut.function_unit),
                  internal_op.eq(dut.internal_op)]
@@ -37,9 +38,9 @@ class DecoderTestCase(FHDLTestCase):
             sim.run()
 
     def test_ilang(self):
-        dut = PowerDecoder()
+        dut = PowerMajorDecoder()
         vl = rtlil.convert(dut, ports=[dut.opcode_in, dut.function_unit])
-        with open("power_decoder.il", "w") as f:
+        with open("power_major_decoder.il", "w") as f:
             f.write(vl)
 
 if __name__ == "__main__":
-- 
2.30.2