From a4fd3cde8cb93f43f5fa0082cf244eb280a2581c Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 4 Jul 2013 14:17:25 +0200
Subject: [PATCH] Documentation updates

---
 README | 7 ++-----
 1 file changed, 2 insertions(+), 5 deletions(-)

diff --git a/README b/README
index 699b83ba6..9521fd6a8 100644
--- a/README
+++ b/README
@@ -245,7 +245,6 @@ TODOs / Open Bugs
   - Indexed part selects
   - Multi-dimensional arrays
   - ROM modeling using "initial" blocks
-  - The "defparam <cell_name>.<parameter_name> = <value>;" syntax
   - Built-in primitive gates (and, nand, cmos, nmos, pmos, etc..)
   - Ignore what needs to be ignored (e.g. drive and charge strengths)
   - Check standard vs. implementation to identify missing features
@@ -255,11 +254,9 @@ TODOs / Open Bugs
   - Actually use range information on parameters
   - Add brief source code documentation to most passes and kernel code
   - Implement mux-to-tribuf pass and rebalance mixed mux/tribuf trees
-  - Add 'edit' command for changing the design (delete, add, modify objects)
-  - Improve TCL support and add 'list' command for inspecting the design from TCL
+  - Add edit commands for changing the design (delete, add, modify objects)
+  - Improve TCL support (add mechanism for inspecting the design from TCL)
   - Additional internal cell types: $pla and $lut
   - Support for registering designs (as collection of modules) to CellTypes
   - Smarter resource sharing pass (add MUXes and get rid of duplicated cells)
-  - For pass' "fsm_detect" help: add notes what criteria lets it detect an FSM
-  - Better FSM state encoding
 
-- 
2.30.2