From a4fe64ee206a1dba471b3e5f5bae095cf93d7d2b Mon Sep 17 00:00:00 2001 From: Alexander Monakov Date: Thu, 8 Jun 2017 00:51:51 +0300 Subject: [PATCH] doc: update x86 -mcx16 option description * doc/invoke.texi (mcx16): Rewrite. From-SVN: r248995 --- gcc/ChangeLog | 4 ++++ gcc/doc/invoke.texi | 13 ++++++------- 2 files changed, 10 insertions(+), 7 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 30a197488e8..efe7d11a5e5 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,7 @@ +2017-06-07 Alexander Monakov + + * doc/invoke.texi (mcx16): Rewrite. + 2017-06-07 Segher Boessenkool * config/rs6000/predicates.md (rs6000_nonimmediate_operand): Delete. diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 456fa85d40a..c1168823af7 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -25262,13 +25262,12 @@ This option instructs GCC to use 128-bit AVX instructions instead of @item -mcx16 @opindex mcx16 -This option enables GCC to generate @code{CMPXCHG16B} instructions. -@code{CMPXCHG16B} allows for atomic operations on 128-bit double quadword -(or oword) data types. -This is useful for high-resolution counters that can be updated -by multiple processors (or cores). This instruction is generated as part of -atomic built-in functions: see @ref{__sync Builtins} or -@ref{__atomic Builtins} for details. +This option enables GCC to generate @code{CMPXCHG16B} instructions in 64-bit +code to implement compare-and-exchange operations on 16-byte aligned 128-bit +objects. This is useful for atomic updates of data structures exceeding one +machine word in size. The compiler uses this instruction to implement +@ref{__sync Builtins}. However, for @ref{__atomic Builtins} operating on +128-bit integers, a library call is always used. @item -msahf @opindex msahf -- 2.30.2