From a50f6abffc3353fa4f246cb18d6d04978d60abad Mon Sep 17 00:00:00 2001 From: Srinath Parvathaneni Date: Tue, 17 Mar 2020 11:50:54 +0000 Subject: [PATCH] [ARM][GCC][1/1x]: Patch to support MVE ACLE intrinsics with unary operand. This patch supports MVE ACLE intrinsics vcvtq_f16_s16, vcvtq_f32_s32, vcvtq_f16_u16, vcvtq_f32_u32n vrndxq_f16, vrndxq_f32, vrndq_f16, vrndq_f32, vrndpq_f16, vrndpq_f32, vrndnq_f16, vrndnq_f32, vrndmq_f16, vrndmq_f32, vrndaq_f16, vrndaq_f32, vrev64q_f16, vrev64q_f32, vnegq_f16, vnegq_f32, vdupq_n_f16, vdupq_n_f32, vabsq_f16, vabsq_f32, vrev32q_f16, vcvttq_f32_f16, vcvtbq_f32_f16. Please refer to M-profile Vector Extension (MVE) intrinsics [1] for more details. [1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics 2020-03-17 Andre Vieira Mihail Ionescu Srinath Parvathaneni * config/arm/arm-builtins.c (UNOP_NONE_NONE_QUALIFIERS): Define macro. (UNOP_NONE_SNONE_QUALIFIERS): Likewise. (UNOP_NONE_UNONE_QUALIFIERS): Likewise. * config/arm/arm_mve.h (vrndxq_f16): Define macro. (vrndxq_f32): Likewise. (vrndq_f16) Likewise. (vrndq_f32): Likewise. (vrndpq_f16): Likewise. (vrndpq_f32): Likewise. (vrndnq_f16): Likewise. (vrndnq_f32): Likewise. (vrndmq_f16): Likewise. (vrndmq_f32): Likewise. (vrndaq_f16): Likewise. (vrndaq_f32): Likewise. (vrev64q_f16): Likewise. (vrev64q_f32): Likewise. (vnegq_f16): Likewise. (vnegq_f32): Likewise. (vdupq_n_f16): Likewise. (vdupq_n_f32): Likewise. (vabsq_f16): Likewise. (vabsq_f32): Likewise. (vrev32q_f16): Likewise. (vcvttq_f32_f16): Likewise. (vcvtbq_f32_f16): Likewise. (vcvtq_f16_s16): Likewise. (vcvtq_f32_s32): Likewise. (vcvtq_f16_u16): Likewise. (vcvtq_f32_u32): Likewise. (__arm_vrndxq_f16): Define intrinsic. (__arm_vrndxq_f32): Likewise. (__arm_vrndq_f16): Likewise. (__arm_vrndq_f32): Likewise. (__arm_vrndpq_f16): Likewise. (__arm_vrndpq_f32): Likewise. (__arm_vrndnq_f16): Likewise. (__arm_vrndnq_f32): Likewise. (__arm_vrndmq_f16): Likewise. (__arm_vrndmq_f32): Likewise. (__arm_vrndaq_f16): Likewise. (__arm_vrndaq_f32): Likewise. (__arm_vrev64q_f16): Likewise. (__arm_vrev64q_f32): Likewise. (__arm_vnegq_f16): Likewise. (__arm_vnegq_f32): Likewise. (__arm_vdupq_n_f16): Likewise. (__arm_vdupq_n_f32): Likewise. (__arm_vabsq_f16): Likewise. (__arm_vabsq_f32): Likewise. (__arm_vrev32q_f16): Likewise. (__arm_vcvttq_f32_f16): Likewise. (__arm_vcvtbq_f32_f16): Likewise. (__arm_vcvtq_f16_s16): Likewise. (__arm_vcvtq_f32_s32): Likewise. (__arm_vcvtq_f16_u16): Likewise. (__arm_vcvtq_f32_u32): Likewise. (vrndxq): Define polymorphic variants. (vrndq): Likewise. (vrndpq): Likewise. (vrndnq): Likewise. (vrndmq): Likewise. (vrndaq): Likewise. (vrev64q): Likewise. (vnegq): Likewise. (vabsq): Likewise. (vrev32q): Likewise. (vcvtbq_f32): Likewise. (vcvttq_f32): Likewise. (vcvtq): Likewise. * config/arm/arm_mve_builtins.def (VAR2): Define. (VAR1): Define. * config/arm/mve.md (mve_vrndxq_f): Add RTL pattern. (mve_vrndq_f): Likewise. (mve_vrndpq_f): Likewise. (mve_vrndnq_f): Likewise. (mve_vrndmq_f): Likewise. (mve_vrndaq_f): Likewise. (mve_vrev64q_f): Likewise. (mve_vnegq_f): Likewise. (mve_vdupq_n_f): Likewise. (mve_vabsq_f): Likewise. (mve_vrev32q_fv8hf): Likewise. (mve_vcvttq_f32_f16v4sf): Likewise. (mve_vcvtbq_f32_f16v4sf): Likewise. (mve_vcvtq_to_f_): Likewise. gcc/testsuite/ChangeLog: 2020-03-17 Andre Vieira Mihail Ionescu Srinath Parvathaneni * gcc.target/arm/mve/intrinsics/vabsq_f16.c: New test. * gcc.target/arm/mve/intrinsics/vabsq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtbq_f32_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtq_f16_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtq_f16_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtq_f32_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtq_f32_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvttq_f32_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vdupq_n_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vdupq_n_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vnegq_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vnegq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrev32q_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrev64q_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrev64q_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrndaq_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrndaq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrndmq_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrndmq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrndnq_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrndnq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrndpq_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrndpq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrndq_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrndq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrndxq_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrndxq_f32.c: Likewise. --- gcc/ChangeLog | 91 ++++++ gcc/config/arm/arm-builtins.c | 22 ++ gcc/config/arm/arm_mve.h | 293 ++++++++++++++++++ gcc/config/arm/arm_mve_builtins.def | 15 + gcc/config/arm/mve.md | 207 ++++++++++++- gcc/testsuite/ChangeLog | 32 ++ .../gcc.target/arm/mve/intrinsics/vabsq_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vabsq_f32.c | 14 + .../arm/mve/intrinsics/vcvtbq_f32_f16.c | 14 + .../arm/mve/intrinsics/vcvtq_f16_s16.c | 14 + .../arm/mve/intrinsics/vcvtq_f16_u16.c | 14 + .../arm/mve/intrinsics/vcvtq_f32_s32.c | 14 + .../arm/mve/intrinsics/vcvtq_f32_u32.c | 14 + .../arm/mve/intrinsics/vcvttq_f32_f16.c | 14 + .../arm/mve/intrinsics/vdupq_n_f16.c | 14 + .../arm/mve/intrinsics/vdupq_n_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vnegq_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vnegq_f32.c | 14 + .../arm/mve/intrinsics/vrev32q_f16.c | 14 + .../arm/mve/intrinsics/vrev64q_f16.c | 14 + .../arm/mve/intrinsics/vrev64q_f32.c | 14 + .../arm/mve/intrinsics/vrndaq_f16.c | 14 + .../arm/mve/intrinsics/vrndaq_f32.c | 14 + .../arm/mve/intrinsics/vrndmq_f16.c | 14 + .../arm/mve/intrinsics/vrndmq_f32.c | 14 + .../arm/mve/intrinsics/vrndnq_f16.c | 14 + .../arm/mve/intrinsics/vrndnq_f32.c | 14 + .../arm/mve/intrinsics/vrndpq_f16.c | 14 + .../arm/mve/intrinsics/vrndpq_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vrndq_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vrndq_f32.c | 14 + .../arm/mve/intrinsics/vrndxq_f16.c | 14 + .../arm/mve/intrinsics/vrndxq_f32.c | 14 + 33 files changed, 1037 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_f32_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_f32_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f32.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 21afda74470..65b3645d263 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,94 @@ +2020-03-17 Andre Vieira + Mihail Ionescu + Srinath Parvathaneni + + * config/arm/arm-builtins.c (UNOP_NONE_NONE_QUALIFIERS): Define macro. + (UNOP_NONE_SNONE_QUALIFIERS): Likewise. + (UNOP_NONE_UNONE_QUALIFIERS): Likewise. + * config/arm/arm_mve.h (vrndxq_f16): Define macro. + (vrndxq_f32): Likewise. + (vrndq_f16) Likewise. + (vrndq_f32): Likewise. + (vrndpq_f16): Likewise. + (vrndpq_f32): Likewise. + (vrndnq_f16): Likewise. + (vrndnq_f32): Likewise. + (vrndmq_f16): Likewise. + (vrndmq_f32): Likewise. + (vrndaq_f16): Likewise. + (vrndaq_f32): Likewise. + (vrev64q_f16): Likewise. + (vrev64q_f32): Likewise. + (vnegq_f16): Likewise. + (vnegq_f32): Likewise. + (vdupq_n_f16): Likewise. + (vdupq_n_f32): Likewise. + (vabsq_f16): Likewise. + (vabsq_f32): Likewise. + (vrev32q_f16): Likewise. + (vcvttq_f32_f16): Likewise. + (vcvtbq_f32_f16): Likewise. + (vcvtq_f16_s16): Likewise. + (vcvtq_f32_s32): Likewise. + (vcvtq_f16_u16): Likewise. + (vcvtq_f32_u32): Likewise. + (__arm_vrndxq_f16): Define intrinsic. + (__arm_vrndxq_f32): Likewise. + (__arm_vrndq_f16): Likewise. + (__arm_vrndq_f32): Likewise. + (__arm_vrndpq_f16): Likewise. + (__arm_vrndpq_f32): Likewise. + (__arm_vrndnq_f16): Likewise. + (__arm_vrndnq_f32): Likewise. + (__arm_vrndmq_f16): Likewise. + (__arm_vrndmq_f32): Likewise. + (__arm_vrndaq_f16): Likewise. + (__arm_vrndaq_f32): Likewise. + (__arm_vrev64q_f16): Likewise. + (__arm_vrev64q_f32): Likewise. + (__arm_vnegq_f16): Likewise. + (__arm_vnegq_f32): Likewise. + (__arm_vdupq_n_f16): Likewise. + (__arm_vdupq_n_f32): Likewise. + (__arm_vabsq_f16): Likewise. + (__arm_vabsq_f32): Likewise. + (__arm_vrev32q_f16): Likewise. + (__arm_vcvttq_f32_f16): Likewise. + (__arm_vcvtbq_f32_f16): Likewise. + (__arm_vcvtq_f16_s16): Likewise. + (__arm_vcvtq_f32_s32): Likewise. + (__arm_vcvtq_f16_u16): Likewise. + (__arm_vcvtq_f32_u32): Likewise. + (vrndxq): Define polymorphic variants. + (vrndq): Likewise. + (vrndpq): Likewise. + (vrndnq): Likewise. + (vrndmq): Likewise. + (vrndaq): Likewise. + (vrev64q): Likewise. + (vnegq): Likewise. + (vabsq): Likewise. + (vrev32q): Likewise. + (vcvtbq_f32): Likewise. + (vcvttq_f32): Likewise. + (vcvtq): Likewise. + * config/arm/arm_mve_builtins.def (VAR2): Define. + (VAR1): Define. + * config/arm/mve.md (mve_vrndxq_f): Add RTL pattern. + (mve_vrndq_f): Likewise. + (mve_vrndpq_f): Likewise. + (mve_vrndnq_f): Likewise. + (mve_vrndmq_f): Likewise. + (mve_vrndaq_f): Likewise. + (mve_vrev64q_f): Likewise. + (mve_vnegq_f): Likewise. + (mve_vdupq_n_f): Likewise. + (mve_vabsq_f): Likewise. + (mve_vrev32q_fv8hf): Likewise. + (mve_vcvttq_f32_f16v4sf): Likewise. + (mve_vcvtbq_f32_f16v4sf): Likewise. + (mve_vcvtq_to_f_): Likewise. + 2020-03-16 Andre Vieira Mihail Ionescu Srinath Parvathaneni diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c index 2f1b1258c13..38bf82cfe75 100644 --- a/gcc/config/arm/arm-builtins.c +++ b/gcc/config/arm/arm-builtins.c @@ -317,6 +317,28 @@ arm_store1_qualifiers[SIMD_MAX_BUILTIN_ARGS] = { qualifier_void, qualifier_pointer_map_mode, qualifier_none }; #define STORE1_QUALIFIERS (arm_store1_qualifiers) +/* Qualifiers for MVE builtins. */ + +static enum arm_type_qualifiers +arm_unop_none_none_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_none, qualifier_none }; +#define UNOP_NONE_NONE_QUALIFIERS \ + (arm_unop_none_none_qualifiers) + +static enum arm_type_qualifiers +arm_unop_none_snone_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_none, qualifier_none }; +#define UNOP_NONE_SNONE_QUALIFIERS \ + (arm_unop_none_snone_qualifiers) + +static enum arm_type_qualifiers +arm_unop_none_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_none, qualifier_unsigned }; +#define UNOP_NONE_UNONE_QUALIFIERS \ + (arm_unop_none_unone_qualifiers) + +/* End of Qualifier for MVE builtins. */ + /* void ([T element type] *, T, immediate). */ static enum arm_type_qualifiers arm_storestruct_lane_qualifiers[SIMD_MAX_BUILTIN_ARGS] diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h index 807a0d289c1..e256c1ecde3 100644 --- a/gcc/config/arm/arm_mve.h +++ b/gcc/config/arm/arm_mve.h @@ -81,6 +81,33 @@ typedef struct { uint8x16_t val[4]; } uint8x16x4_t; #define vst4q_u32( __addr, __value) __arm_vst4q_u32( __addr, __value) #define vst4q_f16( __addr, __value) __arm_vst4q_f16( __addr, __value) #define vst4q_f32( __addr, __value) __arm_vst4q_f32( __addr, __value) +#define vrndxq_f16(__a) __arm_vrndxq_f16(__a) +#define vrndxq_f32(__a) __arm_vrndxq_f32(__a) +#define vrndq_f16(__a) __arm_vrndq_f16(__a) +#define vrndq_f32(__a) __arm_vrndq_f32(__a) +#define vrndpq_f16(__a) __arm_vrndpq_f16(__a) +#define vrndpq_f32(__a) __arm_vrndpq_f32(__a) +#define vrndnq_f16(__a) __arm_vrndnq_f16(__a) +#define vrndnq_f32(__a) __arm_vrndnq_f32(__a) +#define vrndmq_f16(__a) __arm_vrndmq_f16(__a) +#define vrndmq_f32(__a) __arm_vrndmq_f32(__a) +#define vrndaq_f16(__a) __arm_vrndaq_f16(__a) +#define vrndaq_f32(__a) __arm_vrndaq_f32(__a) +#define vrev64q_f16(__a) __arm_vrev64q_f16(__a) +#define vrev64q_f32(__a) __arm_vrev64q_f32(__a) +#define vnegq_f16(__a) __arm_vnegq_f16(__a) +#define vnegq_f32(__a) __arm_vnegq_f32(__a) +#define vdupq_n_f16(__a) __arm_vdupq_n_f16(__a) +#define vdupq_n_f32(__a) __arm_vdupq_n_f32(__a) +#define vabsq_f16(__a) __arm_vabsq_f16(__a) +#define vabsq_f32(__a) __arm_vabsq_f32(__a) +#define vrev32q_f16(__a) __arm_vrev32q_f16(__a) +#define vcvttq_f32_f16(__a) __arm_vcvttq_f32_f16(__a) +#define vcvtbq_f32_f16(__a) __arm_vcvtbq_f32_f16(__a) +#define vcvtq_f16_s16(__a) __arm_vcvtq_f16_s16(__a) +#define vcvtq_f32_s32(__a) __arm_vcvtq_f32_s32(__a) +#define vcvtq_f16_u16(__a) __arm_vcvtq_f16_u16(__a) +#define vcvtq_f32_u32(__a) __arm_vcvtq_f32_u32(__a) #endif __extension__ extern __inline void @@ -157,6 +184,195 @@ __arm_vst4q_f32 (float32_t * __addr, float32x4x4_t __value) __builtin_mve_vst4qv4sf (__addr, __rv.__o); } +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrndxq_f16 (float16x8_t __a) +{ + return __builtin_mve_vrndxq_fv8hf (__a); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrndxq_f32 (float32x4_t __a) +{ + return __builtin_mve_vrndxq_fv4sf (__a); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrndq_f16 (float16x8_t __a) +{ + return __builtin_mve_vrndq_fv8hf (__a); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrndq_f32 (float32x4_t __a) +{ + return __builtin_mve_vrndq_fv4sf (__a); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrndpq_f16 (float16x8_t __a) +{ + return __builtin_mve_vrndpq_fv8hf (__a); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrndpq_f32 (float32x4_t __a) +{ + return __builtin_mve_vrndpq_fv4sf (__a); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrndnq_f16 (float16x8_t __a) +{ + return __builtin_mve_vrndnq_fv8hf (__a); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrndnq_f32 (float32x4_t __a) +{ + return __builtin_mve_vrndnq_fv4sf (__a); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrndmq_f16 (float16x8_t __a) +{ + return __builtin_mve_vrndmq_fv8hf (__a); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrndmq_f32 (float32x4_t __a) +{ + return __builtin_mve_vrndmq_fv4sf (__a); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrndaq_f16 (float16x8_t __a) +{ + return __builtin_mve_vrndaq_fv8hf (__a); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrndaq_f32 (float32x4_t __a) +{ + return __builtin_mve_vrndaq_fv4sf (__a); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrev64q_f16 (float16x8_t __a) +{ + return __builtin_mve_vrev64q_fv8hf (__a); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrev64q_f32 (float32x4_t __a) +{ + return __builtin_mve_vrev64q_fv4sf (__a); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vnegq_f16 (float16x8_t __a) +{ + return __builtin_mve_vnegq_fv8hf (__a); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vnegq_f32 (float32x4_t __a) +{ + return __builtin_mve_vnegq_fv4sf (__a); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vdupq_n_f16 (float16_t __a) +{ + return __builtin_mve_vdupq_n_fv8hf (__a); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vdupq_n_f32 (float32_t __a) +{ + return __builtin_mve_vdupq_n_fv4sf (__a); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vabsq_f16 (float16x8_t __a) +{ + return __builtin_mve_vabsq_fv8hf (__a); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vabsq_f32 (float32x4_t __a) +{ + return __builtin_mve_vabsq_fv4sf (__a); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrev32q_f16 (float16x8_t __a) +{ + return __builtin_mve_vrev32q_fv8hf (__a); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvttq_f32_f16 (float16x8_t __a) +{ + return __builtin_mve_vcvttq_f32_f16v4sf (__a); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtbq_f32_f16 (float16x8_t __a) +{ + return __builtin_mve_vcvtbq_f32_f16v4sf (__a); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_f16_s16 (int16x8_t __a) +{ + return __builtin_mve_vcvtq_to_f_sv8hf (__a); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_f32_s32 (int32x4_t __a) +{ + return __builtin_mve_vcvtq_to_f_sv4sf (__a); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_f16_u16 (uint16x8_t __a) +{ + return __builtin_mve_vcvtq_to_f_uv8hf (__a); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_f32_u32 (uint32x4_t __a) +{ + return __builtin_mve_vcvtq_to_f_uv4sf (__a); +} + #endif enum { @@ -368,6 +584,83 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_float16_t_ptr][__ARM_mve_type_float16x8x4_t]: __arm_vst4q_f16 (__ARM_mve_coerce(__p0, float16_t *), __ARM_mve_coerce(__p1, float16x8x4_t)), \ int (*)[__ARM_mve_type_float32_t_ptr][__ARM_mve_type_float32x4x4_t]: __arm_vst4q_f32 (__ARM_mve_coerce(__p0, float32_t *), __ARM_mve_coerce(__p1, float32x4x4_t)));}) +#define vrndxq(p0) __arm_vrndxq(p0) +#define __arm_vrndxq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vrndxq_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t]: __arm_vrndxq_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) + +#define vrndq(p0) __arm_vrndq(p0) +#define __arm_vrndq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vrndq_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t]: __arm_vrndq_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) + +#define vrndpq(p0) __arm_vrndpq(p0) +#define __arm_vrndpq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vrndpq_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t]: __arm_vrndpq_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) + +#define vrndnq(p0) __arm_vrndnq(p0) +#define __arm_vrndnq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vrndnq_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t]: __arm_vrndnq_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) + +#define vrndmq(p0) __arm_vrndmq(p0) +#define __arm_vrndmq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vrndmq_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t]: __arm_vrndmq_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) + +#define vrndaq(p0) __arm_vrndaq(p0) +#define __arm_vrndaq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vrndaq_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t]: __arm_vrndaq_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) + +#define vrev64q(p0) __arm_vrev64q(p0) +#define __arm_vrev64q(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vrev64q_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t]: __arm_vrev64q_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) + +#define vnegq(p0) __arm_vnegq(p0) +#define __arm_vnegq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vnegq_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t]: __arm_vnegq_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) + +#define vabsq(p0) __arm_vabsq(p0) +#define __arm_vabsq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vabsq_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t]: __arm_vabsq_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) + +#define vrev32q(p0) __arm_vrev32q(p0) +#define __arm_vrev32q(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vrev32q_f16 (__ARM_mve_coerce(__p0, float16x8_t)));}) + +#define vcvtbq_f32(p0) __arm_vcvtbq_f32(p0) +#define __arm_vcvtbq_f32(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vcvtbq_f32_f16 (__ARM_mve_coerce(__p0, float16x8_t)));}) + +#define vcvttq_f32(p0) __arm_vcvttq_f32(p0) +#define __arm_vcvttq_f32(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_float16x8_t]: __arm_vcvttq_f32_f16 (__ARM_mve_coerce(__p0, float16x8_t)));}) + +#define vcvtq(p0) __arm_vcvtq(p0) +#define __arm_vcvtq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vcvtq_f16_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vcvtq_f32_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vcvtq_f16_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vcvtq_f32_u32 (__ARM_mve_coerce(__p0, uint32x4_t)));}) + #else /* MVE Interger. */ #define vst4q(p0,p1) __arm_vst4q(p0,p1) diff --git a/gcc/config/arm/arm_mve_builtins.def b/gcc/config/arm/arm_mve_builtins.def index 4a7e4d06f0a..78fe7c4eb88 100644 --- a/gcc/config/arm/arm_mve_builtins.def +++ b/gcc/config/arm/arm_mve_builtins.def @@ -19,3 +19,18 @@ . */ VAR5 (STORE1, vst4q, v16qi, v8hi, v4si, v8hf, v4sf) +VAR2 (UNOP_NONE_NONE, vrndxq_f, v8hf, v4sf) +VAR2 (UNOP_NONE_NONE, vrndq_f, v8hf, v4sf) +VAR2 (UNOP_NONE_NONE, vrndpq_f, v8hf, v4sf) +VAR2 (UNOP_NONE_NONE, vrndnq_f, v8hf, v4sf) +VAR2 (UNOP_NONE_NONE, vrndmq_f, v8hf, v4sf) +VAR2 (UNOP_NONE_NONE, vrndaq_f, v8hf, v4sf) +VAR2 (UNOP_NONE_NONE, vrev64q_f, v8hf, v4sf) +VAR2 (UNOP_NONE_NONE, vnegq_f, v8hf, v4sf) +VAR2 (UNOP_NONE_NONE, vdupq_n_f, v8hf, v4sf) +VAR2 (UNOP_NONE_NONE, vabsq_f, v8hf, v4sf) +VAR1 (UNOP_NONE_NONE, vrev32q_f, v8hf) +VAR1 (UNOP_NONE_NONE, vcvttq_f32_f16, v4sf) +VAR1 (UNOP_NONE_NONE, vcvtbq_f32_f16, v4sf) +VAR2 (UNOP_NONE_SNONE, vcvtq_to_f_s, v8hf, v4sf) +VAR2 (UNOP_NONE_UNONE, vcvtq_to_f_u, v8hf, v4sf) diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index b41deb078e6..9f2c7f426f1 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -21,8 +21,18 @@ (V2DI "u64")]) (define_mode_iterator MVE_types [V16QI V8HI V4SI V2DI TI V8HF V4SF V2DF]) (define_mode_iterator MVE_VLD_ST [V16QI V8HI V4SI V8HF V4SF]) +(define_mode_iterator MVE_0 [V8HF V4SF]) -(define_c_enum "unspec" [VST4Q]) +(define_c_enum "unspec" [VST4Q VRNDXQ_F VRNDQ_F VRNDPQ_F VRNDNQ_F VRNDMQ_F + VRNDAQ_F VREV64Q_F VNEGQ_F VDUPQ_N_F VABSQ_F VREV32Q_F + VCVTTQ_F32_F16 VCVTBQ_F32_F16 VCVTQ_TO_F_S + VCVTQ_TO_F_U]) + +(define_mode_attr MVE_CNVT [(V8HI "V8HF") (V4SI "V4SF") + (V8HF "V8HI") (V4SF "V4SI")]) + +(define_int_attr supf [(VCVTQ_TO_F_S "s") (VCVTQ_TO_F_U "u")]) +(define_int_iterator VCVTQ_TO_F [VCVTQ_TO_F_S VCVTQ_TO_F_U]) (define_insn "*mve_mov" [(set (match_operand:MVE_types 0 "nonimmediate_operand" "=w,w,r,w,w,r,w,Us") @@ -120,3 +130,198 @@ return ""; } [(set_attr "length" "16")]) + +;; +;; [vrndxq_f]) +;; +(define_insn "mve_vrndxq_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")] + VRNDXQ_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vrintx.f%# %q0, %q1" + [(set_attr "type" "mve_move") +]) + +;; +;; [vrndq_f]) +;; +(define_insn "mve_vrndq_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")] + VRNDQ_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vrintz.f%# %q0, %q1" + [(set_attr "type" "mve_move") +]) + +;; +;; [vrndpq_f]) +;; +(define_insn "mve_vrndpq_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")] + VRNDPQ_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vrintp.f%# %q0, %q1" + [(set_attr "type" "mve_move") +]) + +;; +;; [vrndnq_f]) +;; +(define_insn "mve_vrndnq_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")] + VRNDNQ_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vrintn.f%# %q0, %q1" + [(set_attr "type" "mve_move") +]) + +;; +;; [vrndmq_f]) +;; +(define_insn "mve_vrndmq_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")] + VRNDMQ_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vrintm.f%# %q0, %q1" + [(set_attr "type" "mve_move") +]) + +;; +;; [vrndaq_f]) +;; +(define_insn "mve_vrndaq_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")] + VRNDAQ_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vrinta.f%# %q0, %q1" + [(set_attr "type" "mve_move") +]) + +;; +;; [vrev64q_f]) +;; +(define_insn "mve_vrev64q_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")] + VREV64Q_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vrev64.%# %q0, %q1" + [(set_attr "type" "mve_move") +]) + +;; +;; [vnegq_f]) +;; +(define_insn "mve_vnegq_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")] + VNEGQ_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vneg.f%# %q0, %q1" + [(set_attr "type" "mve_move") +]) + +;; +;; [vdupq_n_f]) +;; +(define_insn "mve_vdupq_n_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand: 1 "s_register_operand" "r")] + VDUPQ_N_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vdup.%# %q0, %1" + [(set_attr "type" "mve_move") +]) + +;; +;; [vabsq_f]) +;; +(define_insn "mve_vabsq_f" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")] + VABSQ_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vabs.f%# %q0, %q1" + [(set_attr "type" "mve_move") +]) + +;; +;; [vrev32q_f]) +;; +(define_insn "mve_vrev32q_fv8hf" + [ + (set (match_operand:V8HF 0 "s_register_operand" "=w") + (unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "w")] + VREV32Q_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vrev32.16 %q0, %q1" + [(set_attr "type" "mve_move") +]) +;; +;; [vcvttq_f32_f16]) +;; +(define_insn "mve_vcvttq_f32_f16v4sf" + [ + (set (match_operand:V4SF 0 "s_register_operand" "=w") + (unspec:V4SF [(match_operand:V8HF 1 "s_register_operand" "w")] + VCVTTQ_F32_F16)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vcvtt.f32.f16 %q0, %q1" + [(set_attr "type" "mve_move") +]) + +;; +;; [vcvtbq_f32_f16]) +;; +(define_insn "mve_vcvtbq_f32_f16v4sf" + [ + (set (match_operand:V4SF 0 "s_register_operand" "=w") + (unspec:V4SF [(match_operand:V8HF 1 "s_register_operand" "w")] + VCVTBQ_F32_F16)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vcvtb.f32.f16 %q0, %q1" + [(set_attr "type" "mve_move") +]) + +;; +;; [vcvtq_to_f_s, vcvtq_to_f_u]) +;; +(define_insn "mve_vcvtq_to_f_" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand: 1 "s_register_operand" "w")] + VCVTQ_TO_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vcvt.f%#.%# %q0, %q1" + [(set_attr "type" "mve_move") +]) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 24272017f80..6b836c1062f 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,35 @@ +2020-03-17 Andre Vieira + Mihail Ionescu + Srinath Parvathaneni + + * gcc.target/arm/mve/intrinsics/vabsq_f16.c: New test. + * gcc.target/arm/mve/intrinsics/vabsq_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtbq_f32_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtq_f16_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtq_f16_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtq_f32_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtq_f32_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvttq_f32_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vdupq_n_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vdupq_n_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vnegq_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vnegq_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrev32q_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrev64q_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrev64q_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrndaq_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrndaq_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrndmq_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrndmq_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrndnq_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrndnq_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrndpq_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrndpq_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrndq_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrndq_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrndxq_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrndxq_f32.c: Likewise. + 2020-03-16 Andre Vieira Mihail Ionescu Srinath Parvathaneni diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f16.c new file mode 100644 index 00000000000..f49807cb863 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a) +{ + return vabsq_f16 (a); +} + +/* { dg-final { scan-assembler "vabs.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f32.c new file mode 100644 index 00000000000..ab44b314c38 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a) +{ + return vabsq_f32 (a); +} + +/* { dg-final { scan-assembler "vabs.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_f32_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_f32_f16.c new file mode 100644 index 00000000000..bc57f261f2c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_f32_f16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float16x8_t a) +{ + return vcvtbq_f32_f16 (a); +} + +/* { dg-final { scan-assembler "vcvtb.f32.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_s16.c new file mode 100644 index 00000000000..9a7d9c2cf7e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_s16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (int16x8_t a) +{ + return vcvtq_f16_s16 (a); +} + +/* { dg-final { scan-assembler "vcvt.f16.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_u16.c new file mode 100644 index 00000000000..6aae96862c4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_u16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (uint16x8_t a) +{ + return vcvtq_f16_u16 (a); +} + +/* { dg-final { scan-assembler "vcvt.f16.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_s32.c new file mode 100644 index 00000000000..b563fe972bd --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_s32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (int32x4_t a) +{ + return vcvtq_f32_s32 (a); +} + +/* { dg-final { scan-assembler "vcvt.f32.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_u32.c new file mode 100644 index 00000000000..f5354a4a02f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_u32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (uint32x4_t a) +{ + return vcvtq_f32_u32 (a); +} + +/* { dg-final { scan-assembler "vcvt.f32.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_f32_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_f32_f16.c new file mode 100644 index 00000000000..2c0f4fda6be --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_f32_f16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float16x8_t a) +{ + return vcvttq_f32_f16 (a); +} + +/* { dg-final { scan-assembler "vcvtt.f32.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f16.c new file mode 100644 index 00000000000..616c24fd3aa --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16_t a) +{ + return vdupq_n_f16 (a); +} + +/* { dg-final { scan-assembler "vdup.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f32.c new file mode 100644 index 00000000000..570dfde905f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32_t a) +{ + return vdupq_n_f32 (a); +} + +/* { dg-final { scan-assembler "vdup.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f16.c new file mode 100644 index 00000000000..89d0162c274 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a) +{ + return vnegq_f16 (a); +} + +/* { dg-final { scan-assembler "vneg.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f32.c new file mode 100644 index 00000000000..8cbdd16342d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a) +{ + return vnegq_f32 (a); +} + +/* { dg-final { scan-assembler "vneg.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_f16.c new file mode 100644 index 00000000000..86bf47dea54 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_f16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a) +{ + return vrev32q_f16 (a); +} + +/* { dg-final { scan-assembler "vrev32.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f16.c new file mode 100644 index 00000000000..d7f75fd9d3d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a) +{ + return vrev64q_f16 (a); +} + +/* { dg-final { scan-assembler "vrev64.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f32.c new file mode 100644 index 00000000000..131ec461b0e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a) +{ + return vrev64q_f32 (a); +} + +/* { dg-final { scan-assembler "vrev64.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f16.c new file mode 100644 index 00000000000..d647d31ac70 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a) +{ + return vrndaq_f16 (a); +} + +/* { dg-final { scan-assembler "vrinta.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f32.c new file mode 100644 index 00000000000..4d5ba502bc5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a) +{ + return vrndaq_f32 (a); +} + +/* { dg-final { scan-assembler "vrinta.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f16.c new file mode 100644 index 00000000000..996b0b27c15 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a) +{ + return vrndmq_f16 (a); +} + +/* { dg-final { scan-assembler "vrintm.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f32.c new file mode 100644 index 00000000000..fae0a5ca2f1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a) +{ + return vrndmq_f32 (a); +} + +/* { dg-final { scan-assembler "vrintm.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f16.c new file mode 100644 index 00000000000..cc00b6eb613 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a) +{ + return vrndnq_f16 (a); +} + +/* { dg-final { scan-assembler "vrintn.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f32.c new file mode 100644 index 00000000000..150e9d38342 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a) +{ + return vrndnq_f32 (a); +} + +/* { dg-final { scan-assembler "vrintn.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f16.c new file mode 100644 index 00000000000..d75ea35c02c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a) +{ + return vrndpq_f16 (a); +} + +/* { dg-final { scan-assembler "vrintp.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f32.c new file mode 100644 index 00000000000..45de7fb5c59 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a) +{ + return vrndpq_f32 (a); +} + +/* { dg-final { scan-assembler "vrintp.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f16.c new file mode 100644 index 00000000000..b3a96540508 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a) +{ + return vrndq_f16 (a); +} + +/* { dg-final { scan-assembler "vrintz.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f32.c new file mode 100644 index 00000000000..c8a723ae4d7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a) +{ + return vrndq_f32 (a); +} + +/* { dg-final { scan-assembler "vrintz.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f16.c new file mode 100644 index 00000000000..aa364f0671f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t a) +{ + return vrndxq_f16 (a); +} + +/* { dg-final { scan-assembler "vrintx.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f32.c new file mode 100644 index 00000000000..99a758110c7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t a) +{ + return vrndxq_f32 (a); +} + +/* { dg-final { scan-assembler "vrintx.f32" } } */ -- 2.30.2