From a51fb17f48428e7cfc96a72a9f9f87901363bb6b Mon Sep 17 00:00:00 2001 From: Bin Cheng Date: Wed, 21 Nov 2012 03:44:21 +0000 Subject: [PATCH] * config/arm/arm-cores.def (cortex-m1, cortex-m0) (cortex-m0plus): Use v6m. * config/arm/arm-protos.h (tune_params): Add logical_op_non_short_circuit. * config/arm/arm.c (arm_slowmul_tune, arm_fastmul_tune) (arm_strongarm_tune, arm_xscale_tune, arm_9e_tune, arm_v6t2_tune) (arm_cortex_tune, arm_cortex_a15_tune, arm_cortex_a5_tune) (arm_cortex_a9_tune, arm_fa726te_tune): Set logical_op_non_short_circuit field. (arm_v6m_tune): New tune_params struct. * config/arm/arm.h (LOGICAL_OP_NON_SHORT_CIRCUIT): Define. * gcc.dg/tree-ssa/ssa-dom-thread-4.c: Skip on ARM Cortex-M0. * gcc.dg/tree-ssa/vrp47.c: Ditto. From-SVN: r193687 --- gcc/ChangeLog | 14 ++++++ gcc/config/arm/arm-cores.def | 6 +-- gcc/config/arm/arm-protos.h | 4 ++ gcc/config/arm/arm.c | 48 ++++++++++++++----- gcc/config/arm/arm.h | 8 +++- gcc/testsuite/ChangeLog | 5 ++ .../gcc.dg/tree-ssa/ssa-dom-thread-4.c | 4 +- gcc/testsuite/gcc.dg/tree-ssa/vrp47.c | 4 ++ 8 files changed, 77 insertions(+), 16 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index c19eac0867f..1e76e8a53ca 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,17 @@ +2012-11-21 Bin Cheng + + * config/arm/arm-cores.def (cortex-m1, cortex-m0) + (cortex-m0plus): Use v6m. + * config/arm/arm-protos.h (tune_params): Add + logical_op_non_short_circuit. + * config/arm/arm.c (arm_slowmul_tune, arm_fastmul_tune) + (arm_strongarm_tune, arm_xscale_tune, arm_9e_tune, arm_v6t2_tune) + (arm_cortex_tune, arm_cortex_a15_tune, arm_cortex_a5_tune) + (arm_cortex_a9_tune, arm_fa726te_tune): Set + logical_op_non_short_circuit field. + (arm_v6m_tune): New tune_params struct. + * config/arm/arm.h (LOGICAL_OP_NON_SHORT_CIRCUIT): Define. + 2012-11-20 Matthias Klose * configure.ac: Substitute `with_cpu'. diff --git a/gcc/config/arm/arm-cores.def b/gcc/config/arm/arm-cores.def index 9eb42628693..ac6612bb91a 100644 --- a/gcc/config/arm/arm-cores.def +++ b/gcc/config/arm/arm-cores.def @@ -135,6 +135,6 @@ ARM_CORE("cortex-r4f", cortexr4f, 7R, FL_LDSCHED, cortex) ARM_CORE("cortex-r5", cortexr5, 7R, FL_LDSCHED | FL_ARM_DIV, cortex) ARM_CORE("cortex-m4", cortexm4, 7EM, FL_LDSCHED, cortex) ARM_CORE("cortex-m3", cortexm3, 7M, FL_LDSCHED, cortex) -ARM_CORE("cortex-m1", cortexm1, 6M, FL_LDSCHED, cortex) -ARM_CORE("cortex-m0", cortexm0, 6M, FL_LDSCHED, cortex) -ARM_CORE("cortex-m0plus", cortexm0plus, 6M, FL_LDSCHED, cortex) +ARM_CORE("cortex-m1", cortexm1, 6M, FL_LDSCHED, v6m) +ARM_CORE("cortex-m0", cortexm0, 6M, FL_LDSCHED, v6m) +ARM_CORE("cortex-m0plus", cortexm0plus, 6M, FL_LDSCHED, v6m) diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h index bfe96ead1eb..d942c5b07a1 100644 --- a/gcc/config/arm/arm-protos.h +++ b/gcc/config/arm/arm-protos.h @@ -243,6 +243,10 @@ struct tune_params int (*branch_cost) (bool, bool); /* Prefer STRD/LDRD instructions over PUSH/POP/LDM/STM. */ bool prefer_ldrd_strd; + /* The preference for non short cirtcuit operation when optimizing for + performance. The first element covers Thumb state and the second one + is for ARM state. */ + bool logical_op_non_short_circuit[2]; }; extern const struct tune_params *current_tune; diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 3bec7c57421..50dcff5ea40 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -893,7 +893,8 @@ const struct tune_params arm_slowmul_tune = ARM_PREFETCH_NOT_BENEFICIAL, true, /* Prefer constant pool. */ arm_default_branch_cost, - false /* Prefer LDRD/STRD. */ + false, /* Prefer LDRD/STRD. */ + {true, true}, /* Prefer non short circuit. */ }; const struct tune_params arm_fastmul_tune = @@ -905,7 +906,8 @@ const struct tune_params arm_fastmul_tune = ARM_PREFETCH_NOT_BENEFICIAL, true, /* Prefer constant pool. */ arm_default_branch_cost, - false /* Prefer LDRD/STRD. */ + false, /* Prefer LDRD/STRD. */ + {true, true}, /* Prefer non short circuit. */ }; /* StrongARM has early execution of branches, so a sequence that is worth @@ -920,7 +922,8 @@ const struct tune_params arm_strongarm_tune = ARM_PREFETCH_NOT_BENEFICIAL, true, /* Prefer constant pool. */ arm_default_branch_cost, - false /* Prefer LDRD/STRD. */ + false, /* Prefer LDRD/STRD. */ + {true, true}, /* Prefer non short circuit. */ }; const struct tune_params arm_xscale_tune = @@ -932,7 +935,8 @@ const struct tune_params arm_xscale_tune = ARM_PREFETCH_NOT_BENEFICIAL, true, /* Prefer constant pool. */ arm_default_branch_cost, - false /* Prefer LDRD/STRD. */ + false, /* Prefer LDRD/STRD. */ + {true, true}, /* Prefer non short circuit. */ }; const struct tune_params arm_9e_tune = @@ -944,7 +948,8 @@ const struct tune_params arm_9e_tune = ARM_PREFETCH_NOT_BENEFICIAL, true, /* Prefer constant pool. */ arm_default_branch_cost, - false /* Prefer LDRD/STRD. */ + false, /* Prefer LDRD/STRD. */ + {true, true}, /* Prefer non short circuit. */ }; const struct tune_params arm_v6t2_tune = @@ -956,7 +961,8 @@ const struct tune_params arm_v6t2_tune = ARM_PREFETCH_NOT_BENEFICIAL, false, /* Prefer constant pool. */ arm_default_branch_cost, - false /* Prefer LDRD/STRD. */ + false, /* Prefer LDRD/STRD. */ + {true, true}, /* Prefer non short circuit. */ }; /* Generic Cortex tuning. Use more specific tunings if appropriate. */ @@ -969,7 +975,8 @@ const struct tune_params arm_cortex_tune = ARM_PREFETCH_NOT_BENEFICIAL, false, /* Prefer constant pool. */ arm_default_branch_cost, - false /* Prefer LDRD/STRD. */ + false, /* Prefer LDRD/STRD. */ + {true, true}, /* Prefer non short circuit. */ }; const struct tune_params arm_cortex_a15_tune = @@ -981,7 +988,8 @@ const struct tune_params arm_cortex_a15_tune = ARM_PREFETCH_NOT_BENEFICIAL, false, /* Prefer constant pool. */ arm_default_branch_cost, - true /* Prefer LDRD/STRD. */ + true, /* Prefer LDRD/STRD. */ + {true, true}, /* Prefer non short circuit. */ }; /* Branches can be dual-issued on Cortex-A5, so conditional execution is @@ -996,7 +1004,8 @@ const struct tune_params arm_cortex_a5_tune = ARM_PREFETCH_NOT_BENEFICIAL, false, /* Prefer constant pool. */ arm_cortex_a5_branch_cost, - false /* Prefer LDRD/STRD. */ + false, /* Prefer LDRD/STRD. */ + {false, false}, /* Prefer non short circuit. */ }; const struct tune_params arm_cortex_a9_tune = @@ -1008,7 +1017,23 @@ const struct tune_params arm_cortex_a9_tune = ARM_PREFETCH_BENEFICIAL(4,32,32), false, /* Prefer constant pool. */ arm_default_branch_cost, - false /* Prefer LDRD/STRD. */ + false, /* Prefer LDRD/STRD. */ + {true, true}, /* Prefer non short circuit. */ +}; + +/* The arm_v6m_tune is duplicated from arm_cortex_tune, rather than + arm_v6t2_tune. It is used for cortex-m0, cortex-m1 and cortex-m0plus. */ +const struct tune_params arm_v6m_tune = +{ + arm_9e_rtx_costs, + NULL, + 1, /* Constant limit. */ + 5, /* Max cond insns. */ + ARM_PREFETCH_NOT_BENEFICIAL, + false, /* Prefer constant pool. */ + arm_default_branch_cost, + false, /* Prefer LDRD/STRD. */ + {false, false}, /* Prefer non short circuit. */ }; const struct tune_params arm_fa726te_tune = @@ -1020,7 +1045,8 @@ const struct tune_params arm_fa726te_tune = ARM_PREFETCH_NOT_BENEFICIAL, true, /* Prefer constant pool. */ arm_default_branch_cost, - false /* Prefer LDRD/STRD. */ + false, /* Prefer LDRD/STRD. */ + {true, true}, /* Prefer non short circuit. */ }; diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index 08eeff5c8d3..2df36cbdcb9 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -2012,10 +2012,16 @@ enum arm_auto_incmodes || (X) == arg_pointer_rtx) /* Try to generate sequences that don't involve branches, we can then use - conditional instructions */ + conditional instructions. */ #define BRANCH_COST(speed_p, predictable_p) \ (current_tune->branch_cost (speed_p, predictable_p)) +/* False if short circuit operation is preferred. */ +#define LOGICAL_OP_NON_SHORT_CIRCUIT \ + ((optimize_size) \ + ? (TARGET_THUMB ? false : true) \ + : (current_tune->logical_op_non_short_circuit[TARGET_ARM])) + /* Position Independent Code. */ /* We decide which register to use based on the compilation options and diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 0cff70940d6..8cbad25a5e3 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2012-11-21 Bin Cheng + + * gcc.dg/tree-ssa/ssa-dom-thread-4.c: Skip on ARM Cortex-M0. + * gcc.dg/tree-ssa/vrp47.c: Ditto. + 2012-11-20 Uros Bizjak PR target/19398 diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-dom-thread-4.c b/gcc/testsuite/gcc.dg/tree-ssa/ssa-dom-thread-4.c index 1396831ac15..1cf3f0bf571 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/ssa-dom-thread-4.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-dom-thread-4.c @@ -59,7 +59,9 @@ bitmap_ior_and_compl (bitmap dst, const_bitmap a, const_bitmap b, code we missed the edge when the first conditional is false (b_elt is zero, which means the second conditional is always zero. */ -/* { dg-final { scan-tree-dump-times "Threaded" 3 "dom1" { target { ! mips*-*-* } } } } */ +/* ARM Cortex-M0 defined LOGICAL_OP_NON_SHORT_CIRCUIT to false, + so skip below test. */ +/* { dg-final { scan-tree-dump-times "Threaded" 3 "dom1" { target { ! { mips*-*-* || { arm_cortex_m && arm_thumb1 } } } } } } */ /* MIPS defines LOGICAL_OP_NON_SHORT_CIRCUIT to 0, so we split var1 || var2 into two conditions, rather than use (var1 != 0) | (var2 != 0). */ /* { dg-final { scan-tree-dump-times "Threaded" 4 "dom1" { target mips*-*-* } } } */ diff --git a/gcc/testsuite/gcc.dg/tree-ssa/vrp47.c b/gcc/testsuite/gcc.dg/tree-ssa/vrp47.c index 08b788abaf3..bf4f0f39e1e 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/vrp47.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/vrp47.c @@ -6,6 +6,10 @@ /* { dg-do compile { target { ! "mips*-*-* s390*-*-* avr-*-* mn10300-*-*" } } } */ /* { dg-options "-O2 -fdump-tree-vrp1 -fdump-tree-dom1 -fdump-tree-dom2" } */ /* { dg-additional-options "-march=i586" { target { { i?86-*-* x86_64-*-* } && ia32 } } } */ +/* Skip on ARM Cortex-M0, where LOGICAL_OP_NON_SHORT_CIRCUIT is set to false, + leading to two conditional jumps when evaluating an && condition. VRP is + not able to optimize this. */ +/* { dg-skip-if "" { arm_cortex_m && arm_thumb1} } */ int h(int x, int y) { -- 2.30.2