From a53feba8a15aa7d5b02b291bf700c5cf7f41ad93 Mon Sep 17 00:00:00 2001 From: Fabien Marteau Date: Fri, 11 Jul 2014 11:07:39 -0600 Subject: [PATCH] mibuild/platforms: add APF27 and APF51 Armadeus platforms --- mibuild/platforms/apf27.py | 153 +++++++++++++++++++++++++++++++ mibuild/platforms/apf51.py | 181 +++++++++++++++++++++++++++++++++++++ 2 files changed, 334 insertions(+) create mode 100644 mibuild/platforms/apf27.py create mode 100644 mibuild/platforms/apf51.py diff --git a/mibuild/platforms/apf27.py b/mibuild/platforms/apf27.py new file mode 100644 index 00000000..23c99cdd --- /dev/null +++ b/mibuild/platforms/apf27.py @@ -0,0 +1,153 @@ +from mibuild.generic_platform import * +from mibuild.crg import SimpleCRG +from mibuild.xilinx_ise import XilinxISEPlatform + +_ios = [ + ("clk0", 0, Pins("N9"), IOStandard("LVCMOS18")), + ("fpga_reset", 0, Pins("T9"), IOStandard("LVCMOS18"), Drive("8")), + ("fpga_initb", 0, Pins("T12"), IOStandard("LVCMOS18"), Drive("8")), + ("weim", 0, + Subsignal("cs4_dtack", Pins("R3"), IOStandard("LVCMOS18"), Drive("8")), + Subsignal("cs5n", Pins("P10"), IOStandard("LVCMOS18")), + Subsignal("eb0n", Pins("P9"), IOStandard("LVCMOS18")), + Subsignal("oen", Pins("R9"), IOStandard("LVCMOS18")), + Subsignal("data", + Pins("T5 T6 P7 N8 P12 T13 R13 T14 P5 N6 T3 T11 T4 R5 M10 T10"), + IOStandard("LVCMOS18"), Drive("8")), + Subsignal("addr", + Pins("N5 L7 M7 M8 L8 L9 L10 M11 P11 N11 N12 P13"), + IOStandard("LVCMOS18")) + ) +] + +_connectors = [ + ("J2", + "None", # no 0 pin + "None", # 1 +3v3 + "None", # 2 +3v3 + "None", # 3 GND + "None", # 4 GND + "None", # 5 DP USB_OTG_PHY +3V3 + "None", # 6 DM USB_OTG_PHY +3V3 + "None", # 7 VBUS USB_OTG_ PHY +3V3 + "None", # 8 PSW_N USB_OTG_PHY +3V3 + "None", # 9 ID USB_OTG_PHY +3V3 + "None", # 10 FAULT USB_OTG_PHY +3V3 + "None", # 11 RXP Ethernet_PHY +3V3 + "None", # 12 RXN Ethernet_PHY +3V3 + "None", # 13 ETH_LINK Ethernet_PHY +2V8 + "None", # 14 PC_VS2 PC +2V8 PF13 + "None", # 15 PC_VS1 PC +2V8 PF14 + "None", # 16 PC_PWRON PC +2V8 PF16 + "None", # 17 PC_READY PC +2V8 PF17 + "None", # 18 PWM0 PWM0 +2V8 PE5 + "None", # 19 TOUT GPT +2V8 PC14 + "None", # 20 GND POWER + "None", # 21 VCC01 (IN) BANK1 SUPPLY VCCO1 + "C16", # 22 IO_L24P_1 FPGA_BANK1 VCC01 + "C15", # 23 IO_L24N_1 FPGA_BANK1 VCC01 + "D16", # 24 IO_L22_P1 FPGA_BANK1 VCC01 + "None", # 25 GND POWER + "B14", # 26 IO_L02N_0 FPGA_BANK0 VCCO0 + "B15", # 27 IO_L02P_0 FPGA_BANK0 + "A13", # 28 IO_L04N_0 FPGA_BANK0 + "A14", # 29 IO_L04P_0 FPGA_BANK0 VCCO0 + "D11", # 30 IO_L03N_0 FPGA_BANK0 VCCO0 + "C12", # 31 IO_L03P_0 FPGA_BANK0 VCCO0 + "A10", # 32 IO_L08N_0 FPGA_BANK0 VCCO0 + "B10", # 33 IO_L08P_0 FPGA_BANK0 VCCO0 + "A9", # 34 IO_L10N_0 / GLCK7 FPGA_BANK0 VCCO0 + "C9", # 35 IO_L10P_0 / GCLK6 FPGA_BANK0 VCCO0 + "B8", # 36 IO_L12N_0 / GCLK11 FPGA_BANK0 VCCO0 + "A8", # 37 IO_L12P_0 / GCLK10 FPGA_BANK0 VCCO0 + "B6", # 38 IO_L15N_0 FPGA_BANK0 VCCO0 + "A6", # 39 IO_L15P_0 FPGA_BANK0 VCCO0 + "B4", # 40 IO_L18N_0 FPGA_BANK0 VCCO0 + "A4", # 41 IO_L18P_0 FPGA_BANK0 VCCO0 + "None", # 42 GND POWER + "N3", # 43 IO_L24P_3 FPGA_BANK3 VCCO3 + "R1", # 44 IO_L23P_3 FPGA_BANK3 VCCO3 + "P1", # 45 IO_L22N_3 FPGA_BANK3 VCCO3 + "N1", # 46 IO_L20N_3 FPGA_BANK3 VCCO3 + "M1", # 47 IO_L20P_3 FPGA_BANK3 VCCO3 + "H3", # 48 IO_L12P_3 FPGA_BANK3 VCCO3 + "K1", # 49 IO_L15N_3 FPGA_BANK3 VCCO3 + "J1", # 50 IO_L14N_3 FPGA_BANK3 VCCO3 + "H1", # 51 IO_L11N_3 FPGA_BANK3 VCCO3 + "G1", # 52 IO_L08N_3 FPGA_BANK3 VCCO3 + "F1", # 53 IO_L08P_3 FPGA_BANK3 VCCO3 + "E1", # 54 IO_L03N_3 FPGA_BANK3 VCCO3 + "D1", # 55 IO_LO3P_3 FPGA_BANK3 VCCO3 + "C1", # 56 IO_L01N_3 FPGA_BANK3 VCCO3 + "None", # 57 GND POWER + "None", # 58 TRSTN JTAG +2V8 + "None", # 59 TDI JTAG +2V8 + "None", # 60 TCK JTAG +2V8 + "None", # 61 TDO JTAG +2V8 + "None", # 62 TMS JTAG +2V8 + "None", # 63 GND POWER + "C2", # 64 IO_L01P_3 FPGA_BANK3 VCCO3 + "D3", # 65 IO_L02N_3 FPGA_BANK3 VCCO3 + "D4", # 66 IO_L02P_3 FPGA_BANK3 VCCO3 + "F4", # 67 IP_LO4N_3 FPGA_BANK3 VCCO3 + "G2", # 68 IO_L11P_3 FPGA_BANK3 VCCO3 + "J2", # 69 IO_L14P_3 FPGA_BANK3 VCCO3 + "K3", # 70 IO_L15P_3 FPGA_BANK3 VCCO3 + "J3", # 71 IO_L12N_3 FPGA_BANK3 VCCO3 + "N2", # 72 IO_L22P_3 FPGA_BANK3 VCCO3 + "P2", # 73 IO_L23N_3 FPGA_BANK3 VCCO3 + "M4", # 74 IO_L24N_3 FPGA_BANK3 VCCO3 + "L6", # 75 IP_L25N_3 FPGA_BANK3 VCCO3 + "None", # 76 VCCO3 (IN) BANK3 SUPPLY VCCO3 (3.3Vmax) + "None", # 77 VCCO3 (IN) BANK3 SUPPLY VCCO3 (3.3Vmax) + "A3", # 78 IO_L19P_0 FPGA_BANK0 VCCO0 + "B3", # 79 IO_L19N_0 FPGA_BANK0 VCCO0 + "A5", # 80 IO_L17P_0 FPGA_BANK0 VCCO0 + "C5", # 81 IO_L17N_0 FPGA_BANK0 VCCO0 + "D7", # 82 IO_L16P_0 FPGA_BANK0 VCCO0 + "C6", # 83 IO_L16N_0 FPGA_BANK0 VCCO0 + "C8", # 84 IO_L11P_0 / GCLK8 FPGA_BANK0 VCCO0 + "D8", # 85 IO_L11N_0 / GCLK9 FPGA_BANK0 VCCO0 + "C10", # 86 IO_L09P_0 / GCLK4 FPGA_BANK0 VCCO0 + "D9", # 87 IO_L09N_0 / GCLK5 FPGA_BANK0 VCCO0 + "C11", # 88 IO_L07P_0 FPGA_BANK0 VCCO0 + "A11", # 89 IO_L07N_0 FPGA_BANK0 VCCO0 + "D13", # 90 IO_L01P_0 FPGA_BANK0 VCCO0 + "C13", # 91 IO_L01N_0 FPGA_BANK0 VCCO0 + "None", # 92 VCCO0 (IN) BANK0 SUPPLY VCCO0 (3.3Vmax) + "None", # 93 VCCO0 (IN) BANK0 SUPPLY VCCO0 (3.3Vmax) + "None", # 94 GND POWER VCCO0 A13 + "D15", # 95 IO_L22N_1 FPGA_BANK1 VCC01 + "E13", # 96 IO_L23P_1 FPGA_BANK1 VCC01 + "D14", # 97 IO_L23N_1 FPGA_BANK1 VCC01 + "E14", # 98 IO_L20P_1 FPGA_BANK1 VCC01 + "F13", # 99 IO_L20N_1 FPGA_BANK1 VCC01 + "None", # 100 GND POWER (3.3Vmax) + "None", # 101 USR_RESETN (open CONFIG Pos PC15 +2V8 drain with pullup) + "None", # 102 TIN GPT +2V8 + "None", # 103 EXTAL_26M CONFIG +2V5 + "None", # 104 RX3 RS232_3 RS232 + "None", # 105 TX3 RS232_3 RS232 + "None", # 106 RX1 RS232_1 RS232 + "None", # 107 TX1 RS232_1 RS232 + "None", # 108 BOOT CONFIG +2V8 + "None", # 109 TXN Ethernet_PHY +3V3 + "None", # 110 TXP Ethernet_PHY +3V3 + "None", # 111 ETH_ACTIVITY Ethernet_PHY +2V8 + "None", # 112 USBH2_NXT USB_HOST2 +2V5 PA3 + "None", # 113 USBH2_DIR USB_HOST2 +2V5 PA1 + "None", # 114 USBH2_DATA7 USB_HOST2 +2V5 PA2 + "None", # 115 USBH2_STP USB_HOST2 +2V5 PA4 + "None") # 116 USBH2_CLK USB_HOST2 +2V5 PA0 +] + +class Platform(XilinxISEPlatform): + def __init__(self): + XilinxISEPlatform.__init__(self, "xc3s200a-ft256-4", _ios, + lambda p: SimpleCRG(p, "clk0", None), _connectors) + + def do_finalize(self, fragment): + try: + self.add_period_constraint(self.lookup_request("clk0"), 10) + except ConstraintError: + pass diff --git a/mibuild/platforms/apf51.py b/mibuild/platforms/apf51.py new file mode 100644 index 00000000..78c8dc1f --- /dev/null +++ b/mibuild/platforms/apf51.py @@ -0,0 +1,181 @@ +from mibuild.generic_platform import * +from mibuild.crg import SimpleCRG +from mibuild.xilinx_ise import XilinxISEPlatform + +_ios = [ + ("clk3", 0, Pins("N8"), IOStandard("LVCMOS33")), + ("clko", 0, Pins("N7"), IOStandard("LVCMOS33")), + ("fpga_initb", 0, Pins("P3"), IOStandard("LVCMOS33")), + ("fpga_program", 0, Pins("R2"), IOStandard("LVCMOS33")), + ("eim", 0, + Subsignal("bclk", Pins("N12")), + Subsignal("eb1", Pins("P13")), + Subsignal("cs1", Pins("R11")), + Subsignal("cs2", Pins("N9")), + Subsignal("lba", Pins("R9")), + Subsignal("eb0", Pins("P7")), + Subsignal("oe", Pins("R7")), + Subsignal("rw", Pins("R6")), + Subsignal("dtack", Pins("N4")), + Subsignal("wait", Pins("R4")), + Subsignal("da", Pins("N6 L5 L6 R5 P5 N11 M11 P11 L8 K8 M8 M10 L9 R10 N5 M5")), + IOStandard("LVCMOS33") + ) +] + +_connectors = [ + ("J2", + "None", # No 0 pin + "None", # 1 FPGA Bank1 power + "None", # 2 FPGA Bank1 power + "None", # 3 GND + "B14", # 4 IO_L1P_A25_1 + "B15", # 5 IO_L1N_A24_VREF_1 + "C14", # 6 IO_L33P_A15_M1A10_1 + "C15", # 7 IO_L33N_A14_M1A4_1 + "D13", # 8 IO_L35P_A11_M1A7_1 + "D15", # 9 IO_L35N_A10_M1A2_1 + "E14", # 10 IO_L37P_A7_M1A0_1 + "E15", # 11 IO_L37N_A6_M1A1_1 + "None", # 12 GND + "F13", # 13 IO_L39P_M1A3_1 + "F15", # 14 IO_L39N_M1ODT_1 + "G14", # 15 IO_L41P_GCLK9_IRDY1_M1RASN_1 + "G15", # 16 IO_L41N_GCLK8_M1CASN_1 + "H13", # 17 IO_L42P_GCLK7_M1UDM_1 + "H15", # 18 IO_L42N_GCLK6_TRDY1_M1LDM + "J14", # 19 IO_L43P_GCLK5_M1DQ4_1 + "J15", # 20 IO_L43N_GCLK4_M1DQ5_1 + "K13", # 21 IO_L44P_A3_M1DQ6_1 + "K15", # 22 IO_L44N_A2_M1DQ7_1 + "L14", # 23 IO_L45P_A1_M1LDQS_1 + "L15", # 24 IO_L45N_A0_M1LDQSN_1 + "None", # 25 GND + "E2", # 26 IO_L52P_M3A8_3 + "E1", # 27 IO_L52N_M3A9_3 + "D3", # 28 IO_L54P_M3RESET_3 + "D1", # 29 IO_L54N_M3A11_3 + "F3", # 30 IO_L46P_M3CLK_3 + "F1", # 31 IO_L46N_M3CLKN_3 + "G2", # 32 IO_L44P_GCLK21_M3A5_3 + "G1", # 33 IO_L44N_GCLK20_M3A6_3 + "H3", # 34 IO_L42P_GCLK25_TRDY2_M3UDM_3 + "H1", # 35 IO_L42N_GCLK24_M3LDM_3 + "K3", # 36 IO_L40P_M3DQ6_3 + "K1", # 37 IO_L40N_M3DQ7_3 + "None", # 38 GND + "None", # 39 GPIO4_16 + "None", # 40 GPIO4_17 + "None", # 41 BOOT_MODE0 + "None", # 42 AUD5_RXFS + "None", # 43 AUD5_RXC + "None", # 44 GND + "None", # 45 AUD5_RXD + "None", # 46 AUD5_TXC + "None", # 47 AUD5_TXFS + "None", # 48 GND + "None", # 49 SPI2_SCLK_GPT_CMPOUT3 + "None", # 50 SPI2_MISO + "None", # 51 SPI2_MOSI + "None", # 52 SPI2_SS1 + "None", # 53 SPI2_SS2 + "None", # 54 SPI2_SS3 + "None", # 55 SPI2_RDY + "None", # 56 OWIRE + "None", # 57 GND + "None", # 58 SPI1_SCLK + "None", # 59 SPI1_MISO + "None", # 60 SPI1_MOSI + "None", # 61 SPI1_SS0 + "None", # 62 SPI1_SS1 + "None", # 63 SPI1_RDY + "None", # 64 RESET# + "None", # 65 VIO_H2 + "None", # 66 PMIC_GPIO6 + "None", # 67 TOUCH_X+ + "None", # 68 TOUCH_X- + "None", # 69 TOUCH_Y+ + "None", # 70 TOUCH_Y- + "None", # 71 AUXADCIN4 + "None", # 72 AUXADCIN3 + "None", # 73 AUXADCIN2 + "None", # 74 AUXADCIN1 + "None", # 75 PMIC_GPIO7 + "None", # 76 +1v8 + "None", # 77 RESERVED + "None", # 78 UART3_TXD + "None", # 79 UART_3_RXD + "None", # 80 UART2_TXD + "None", # 81 UART2_RXD + "None", # 82 UART2_RTS_KEY_COL7 + "None", # 83 UART2_CTS_KEY_COL6 + "None", # 84 UART1_TXD + "None", # 85 UART1_RXD + "None", # 86 UART1_RTS + "None", # 87 UART1_CTS + "None", # 88 GND + "None", # 89 AUD3_TXD + "None", # 90 AUD3_RXD + "None", # 91 AUD3_FS + "None", # 92 AUD3_CK + "None", # 93 GND + "None", # 94 AUD6_TXFS_KEY_ROW7 + "None", # 95 AUD6_TXC_KEY_ROW6 + "None", # 96 AUD6_RXD_KEY_ROW5 + "None", # 97 AUD6_TXD_KEY_ROW4 + "None", # 98 I2C2_SDA_UART3_CTS + "None", # 99 I2C2_SCL_UART3_RTS + "None", # 100 BOOT_MODE1 + "None", # 101 PWM2 + "None", # 102 PWM1 + "None", # 103 GND + "L1", # 104 IO_L39N_M3LDQSN_3 + "L2", # 105 IO_L39P_M3LDQS_3 + "J1", # 106 IO_L41N_GCLK26_M3DQ5_3 + "J2", # 107 IO_L41P_GCLK27_M3DQ4_3 + "J3", # 108 IO_L43N_GCLK22_IRDY2_M3CASN_3 + "K4", # 109 IO_L43P_GCLK23_M3RASN_3 + "J4", # 110 IO_L45N_M3ODT_3 + "K5", # 111 IO_L45P_M3A3_3 + "C1", # 112 IO_L83N_VREF_3 + "C2", # 113 IO_L83P_3 + "E3", # 114 IO_L53N_M3A12_3 + "D4", # 115 IO_L53P_M3CKE_3 + "None", # 116 GND + "P15", # 117 IO_L74N_DOUT_BUSY_1 + "P14", # 118 IO_L74P_AWAKE_1 + "N15", # 119 IO_L47N_LDC_M1DQ1_1 + "N14", # 120 IO_L47P_FWE_B_M1DQ0_1 + "M15", # 121 IO_L46N_FOE_B_M1DQ3_1 + "M13", # 122 IO_L46P_FCS_B_M1DQS2_1 + "L12", # 123 IO_L40N_GCLK10_M1A6_1 + "K12", # 124 IO_L40P_GCLK11_M1A5_1 + "K11", # 125 IO_L38N_A4_M1CLKN_1 + "K10", # 126 IO_L38P_A5_M1CLK_1 + "J13", # 127 IO_L36N_A8_M1BA1_1 + "J11", # 128 IO_L36P_A9_M1BA0_1 + "None", # 129 GND + "G13", # 130 IO_L34N_A12_M1BA2_1_NOTLX4 + "H12", # 131 IO_L34P_A13_M1WE_1_NOTLX4 + "H11", # 132 IO_L32N_A16_M1A9_1_NOTLX4 + "H10", # 133 IO_L32P_A17_M1A8_1_NOTLX4 + "F12", # 134 IO_L31N_A18_M1A12_1_NOTLX4 + "F11", # 135 IO_L31P_A19_M1CKE_1_NOTLX4 + "G12", # 136 IO_L30N_A20_M1A11_1_NOTLX4 + "G11", # 137 IO_L30P_A21_M1RESET_1_NOTLX4 + "None", # 138 GND + "None", # 139 FPGA_BANK3_POWER + "None") # 140 FPGA_BANK3_POWER +] + +class Platform(XilinxISEPlatform): + def __init__(self): + XilinxISEPlatform.__init__(self, "xc6slx9-2csg225", _ios, + lambda p: SimpleCRG(p, "clk3", None), _connectors) + + def do_finalize(self, fragment): + try: + self.add_period_constraint(self.lookup_request("clk3"), 10.526) + except ConstraintError: + pass + -- 2.30.2