From a54132fd3598cadc9e66bae441936d1ee0d66137 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 9 Jul 2020 21:10:37 +0100 Subject: [PATCH] test top bit 31 in 32-bit mode for CR0 creation --- src/soc/fu/common_output_stage.py | 5 ++++- src/soc/fu/div/test/test_pipe_caller.py | 8 ++++++++ 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/src/soc/fu/common_output_stage.py b/src/soc/fu/common_output_stage.py index 5d5f0cb4..fb1310ca 100644 --- a/src/soc/fu/common_output_stage.py +++ b/src/soc/fu/common_output_stage.py @@ -55,7 +55,10 @@ class CommonOutputStage(PipeModBase): comb += is_cmp.eq(op.insn_type == InternalOp.OP_CMP) comb += is_cmpeqb.eq(op.insn_type == InternalOp.OP_CMPEQB) - comb += msb_test.eq(target[-1] ^ is_cmp) + with m.If(op.is_32bit): + comb += msb_test.eq(target[-1] ^ is_cmp) # 64-bit MSB + with m.Else(): + comb += msb_test.eq(target[31] ^ is_cmp) # 32-bit MSB comb += is_nzero.eq(target.bool()) comb += is_positive.eq(is_nzero & ~msb_test) comb += is_negative.eq(is_nzero & msb_test) diff --git a/src/soc/fu/div/test/test_pipe_caller.py b/src/soc/fu/div/test/test_pipe_caller.py index 4b7fea86..2814669c 100644 --- a/src/soc/fu/div/test/test_pipe_caller.py +++ b/src/soc/fu/div/test/test_pipe_caller.py @@ -121,6 +121,14 @@ class DIVTestCase(FHDLTestCase): initial_regs[5] = 0x6b8aee2ccf7d62e9 self.run_tst_program(Program(lst), initial_regs) + def test_6_regression(self): + # CR0 not getting set properly for this one + lst = ["divw. 3, 1, 2"] + initial_regs = [0] * 32 + initial_regs[1] = 0x61c1cc3b80f2a6af + initial_regs[2] = 0x9dc66a7622c32bc0 + self.run_tst_program(Program(lst), initial_regs) + def test_rand_divw(self): insns = ["divw", "divw.", "divwo", "divwo."] for i in range(40): -- 2.30.2