From a545da74f67ee93054606eb6f9d2c832b64ee1db Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 21 Jun 2019 07:25:18 +0100 Subject: [PATCH] whitespace --- simple_v_extension/specification.mdwn | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/simple_v_extension/specification.mdwn b/simple_v_extension/specification.mdwn index 70a7ab0a0..f76d8b8a9 100644 --- a/simple_v_extension/specification.mdwn +++ b/simple_v_extension/specification.mdwn @@ -2308,8 +2308,9 @@ and VL need to be set. By contrast, the VLIW prefix is only 16 bits, the VL/MAX/SubVL block is only 16 bits, and as long as not too many predicates and register vector -qualifiers are specified, several 32-bit and 16-bit opcodes can fit into the -format. If the full flexibility of the 16 bit block formats are not needed, more space is saved by using the 8 bit formats. +qualifiers are specified, several 32-bit and 16-bit opcodes can fit into +the format. If the full flexibility of the 16 bit block formats are not +needed, more space is saved by using the 8 bit formats. In this light, embedding the VL/MAXVL, PredCam and RegCam CSR entries into a VLIW format makes a lot of sense. -- 2.30.2