From a54adcb65bad37b398b11e33a824c7d08c5fe509 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 8 May 2020 22:29:55 +0100 Subject: [PATCH] send address to memory only for one cycle and acknowledge LD immediately in test-L0CacheBuffer --- src/soc/experiment/l0_cache.py | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/src/soc/experiment/l0_cache.py b/src/soc/experiment/l0_cache.py index 204d4ec4..5dc6daae 100644 --- a/src/soc/experiment/l0_cache.py +++ b/src/soc/experiment/l0_cache.py @@ -272,11 +272,10 @@ class L0CacheBuffer(Elaboratable): # if now in "LD" mode: wait for addr_ok, then send the address out # to memory, acknowledge address, and send out LD data with m.If(ld_active.q): - with m.If(ldport.addr.ok): + with m.If(ldport.addr.ok & adrok_l.qn): comb += rdport.addr.eq(ldport.addr.data) # addr ok, send thru - with m.If(adrok_l.qn): - comb += ldport.addr_ok_o.eq(1) # acknowledge addr ok - sync += adrok_l.s.eq(1) # and pull "ack" latch + comb += ldport.addr_ok_o.eq(1) # acknowledge addr ok + sync += adrok_l.s.eq(1) # and pull "ack" latch # if now in "ST" mode: likewise do the same but with "ST" # to memory, acknowledge address, and send out LD data -- 2.30.2