From a570331459896c6d7a7c5c24e0d534797ca7a2a1 Mon Sep 17 00:00:00 2001 From: lkcl Date: Sat, 9 Jul 2022 15:13:47 +0100 Subject: [PATCH] --- openpower/sv/svp64_quirks.mdwn | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/openpower/sv/svp64_quirks.mdwn b/openpower/sv/svp64_quirks.mdwn index 935325989..e94681854 100644 --- a/openpower/sv/svp64_quirks.mdwn +++ b/openpower/sv/svp64_quirks.mdwn @@ -535,7 +535,7 @@ In several places in the Power ISA there are operations that are on 32-bit quantities in 64-bit registers. The best example is FP which has 64-bit operations (`fadd`) and 32-bit operations (`fadds` or FP Add "single"). Element-width overrides it would seem to -be unnecessary, under these circunstances. +be unnecessary, under these circumstances. However, it is not possible for `fadds` to fit two elements into 64-bit: that breaks the simplicity of SVP64. @@ -548,8 +548,8 @@ element, in FP32 format, where `sv.fadd/ew=32` stores a full FP32 result into the full 32 bits. Where this breaks down is when attempting to do half-width on -BF16 or FP16 operations: there does not exist a BF8 or an IEE754 FP8 -format, so these should be avoided. +BF16 or FP16 operations: there does not exist a BF8 or an IEEE754 FP8 +format, so these (`sv.fadds/ew=8`) should be avoided. # Vertical-First and Subvectors -- 2.30.2