From a574480267c1ac561c171a3885777beef567ce1e Mon Sep 17 00:00:00 2001 From: klehman Date: Mon, 25 Oct 2021 08:41:25 -0400 Subject: [PATCH] added dump_state_tofile for code creation --- src/openpower/test/runner.py | 8 +++++++- src/openpower/test/state.py | 30 ++++++++++++++++++++++++++++++ 2 files changed, 37 insertions(+), 1 deletion(-) diff --git a/src/openpower/test/runner.py b/src/openpower/test/runner.py index dcd14e49..9215f0f5 100644 --- a/src/openpower/test/runner.py +++ b/src/openpower/test/runner.py @@ -31,7 +31,7 @@ from openpower.decoder.power_decoder2 import PowerDecode2 from soc.config.test.test_loadstore import TestMemPspec from nmutil.util import wrap from soc.experiment.test.test_mmu_dcache import wb_get -from openpower.test.state import TestState, StateRunner +from openpower.test.state import TestState, StateRunner, ExpectedState class SimRunner(StateRunner): @@ -255,6 +255,12 @@ class TestRunnerBase(FHDLTestCase): simstate.compare(hdlstate) # register check simstate.compare_mem(hdlstate) # memory check + # if no expected, create /tmp/case_name.py with code + # setting expected state to last_sim + if test.expected is None: + e = ExpectedState() + e.dump_state_tofile(last_sim, test.name) + # compare against expected results if test.expected is not None: # have to put these in manually diff --git a/src/openpower/test/state.py b/src/openpower/test/state.py index 72199196..f1eb8ef2 100644 --- a/src/openpower/test/state.py +++ b/src/openpower/test/state.py @@ -215,6 +215,36 @@ class ExpectedState(State): def get_mem(self): if False: yield + def dump_state_tofile(self, state, testname): + """dump_state_tofile: Takes a passed in teststate object along + with a test name and generates a code file located at /tmp/testname + to set an expected state object + """ + lindent = ' '*8 # indent for code + with open("/tmp/{0}.py".format(testname), "w") as sout: + # pc and intregs + sout.write(f"{lindent}e = ExpectedState(pc={state.pc})\n") + for i in range(32): + if(state.intregs[i] != 0): + sout.write("{0}e.intregs[{1}] = 0x{2:x}\n".format( + lindent, + i, + state.intregs[i])) + # cr + for i in range(8): + if(state.crregs[i] != 0): + sout.write("{0}e.crregs[{1}] = 0x{2:x}\n".format( + lindent, + i, + state.crregs[i])) + # XER + if(state.so != 0): + sout.write(f"{lindent}e.so = 0x{state.so}\n") + if(state.ov != 0): + sout.write(f"{lindent}e.sv = 0x{state.ov}\n") + if(state.ca != 0): + sout.write(f"{lindent}e.ca = 0x{state.ca}\n") + global state_factory state_factory = {'sim': SimState, 'expected': ExpectedState} -- 2.30.2