From a575b24544aecbab9fbaa4e4ba5eb743ab4932c7 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 22 Sep 2021 16:56:09 +0100 Subject: [PATCH] alter setup_tst_memory to take a test.mem rather than take a Sim object *containing* a Mem --- src/soc/fu/compunits/test/test_compunit.py | 11 +++++++---- src/soc/simple/test/test_core.py | 2 +- src/soc/simple/test/test_microwatt.py | 4 +--- src/soc/simple/test/test_runner.py | 2 +- 4 files changed, 10 insertions(+), 9 deletions(-) diff --git a/src/soc/fu/compunits/test/test_compunit.py b/src/soc/fu/compunits/test/test_compunit.py index 9882a47e..7885b9f7 100644 --- a/src/soc/fu/compunits/test/test_compunit.py +++ b/src/soc/fu/compunits/test/test_compunit.py @@ -11,6 +11,7 @@ from openpower.decoder.power_decoder import create_pdecode from openpower.decoder.power_decoder2 import PowerDecode2, get_rdflags from openpower.decoder.power_enums import Function from openpower.decoder.isa.all import ISA +from openpower.decoder.isa.mem import Mem from soc.experiment.compalu_multi import find_ok # hack from soc.config.test.test_loadstore import TestMemPspec @@ -137,15 +138,17 @@ def get_l0_mem(l0): # BLECH! this is awful! hunting around through structures return mem.mem -def setup_tst_memory(l0, sim): +def setup_tst_memory(l0, test_mem): + # create independent Sim Mem from test values + sim_mem = Mem(initial_mem=test_mem) mem = get_l0_mem(l0) print("before, init mem", mem.depth, mem.width, mem) for i in range(mem.depth): - data = sim.mem.ld(i*8, 8, False) + data = sim_mem.ld(i*8, 8, False) print("init ", i, hex(data)) yield mem._array[i].eq(data) yield Settle() - for k, v in sim.mem.mem.items(): + for k, v in sim_mem.mem.items(): print(" %6x %016x" % (k, v)) print("before, nmigen mem dump") for i in range(mem.depth): @@ -199,7 +202,7 @@ class TestRunner(FHDLTestCase): # initialise memory if self.funit == Function.LDST: - yield from setup_tst_memory(l0, sim) + yield from setup_tst_memory(l0, test.mem) pc = sim.pc.CIA.value index = pc//4 diff --git a/src/soc/simple/test/test_core.py b/src/soc/simple/test/test_core.py index b77ff942..c15732d1 100644 --- a/src/soc/simple/test/test_core.py +++ b/src/soc/simple/test/test_core.py @@ -240,7 +240,7 @@ class TestRunner(FHDLTestCase): gen = program.generate_instructions() instructions = list(zip(gen, program.assembly.splitlines())) - yield from setup_tst_memory(l0, sim) + yield from setup_tst_memory(l0, test.mem) yield from setup_regs(core, test) index = sim.pc.CIA.value // 4 diff --git a/src/soc/simple/test/test_microwatt.py b/src/soc/simple/test/test_microwatt.py index 7e501365..1dd89c53 100644 --- a/src/soc/simple/test/test_microwatt.py +++ b/src/soc/simple/test/test_microwatt.py @@ -15,8 +15,7 @@ from soc.config.test.test_loadstore import TestMemPspec from soc.simple.test.test_core import (setup_regs, check_regs, wait_for_busy_clear, wait_for_busy_hi) -from soc.fu.compunits.test.test_compunit import (setup_tst_memory, - check_sim_memory, +from soc.fu.compunits.test.test_compunit import (check_sim_memory, get_l0_mem) from soc.simple.test.test_runner import setup_i_memory @@ -112,7 +111,6 @@ class TestRunner(FHDLTestCase): # blech! put the same listing into the data memory data_mem = get_l0_mem(l0) yield from setup_i_memory(data_mem, pc, instructions) - # yield from setup_tst_memory(l0, sim) yield from setup_regs(core, test) yield pc_i.eq(pc) diff --git a/src/soc/simple/test/test_runner.py b/src/soc/simple/test/test_runner.py index 934736ac..e1e572be 100644 --- a/src/soc/simple/test/test_runner.py +++ b/src/soc/simple/test/test_runner.py @@ -231,7 +231,7 @@ class TestRunner(FHDLTestCase): counter = 0 # test to pause/start yield from setup_i_memory(imem, pc, instructions) - yield from setup_tst_memory(l0, sim) + yield from setup_tst_memory(l0, test.mem) yield from setup_regs(pdecode2, core, test) # set PC and SVSTATE -- 2.30.2