From a595ff02e53681f37fd6fa8a438343c8d50f62e2 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 3 May 2022 15:23:48 +0100 Subject: [PATCH] Revert "" This reverts commit 6438319ad3b599185c3f17a90821d6bb3c6213e6. --- openpower/sv/bitmanip.mdwn | 27 +++++++++++++++++---------- 1 file changed, 17 insertions(+), 10 deletions(-) diff --git a/openpower/sv/bitmanip.mdwn b/openpower/sv/bitmanip.mdwn index e71903c3a..4dc08e0ea 100644 --- a/openpower/sv/bitmanip.mdwn +++ b/openpower/sv/bitmanip.mdwn @@ -120,7 +120,7 @@ double check that instructions didn't need 3 inputs. | NN | RS | RB | sh | SH | 0 1 | nn00 110 |Rc| bmopsi | | NN | RT | RA | RB | 1 | 00 | 0001 110 |Rc| cldiv | | NN | RT | RA | RB | 1 | 01 | 0001 110 |Rc| clmod | -| NN | RT | RA | RB | 1 | 10 | 0001 110 |Rc| clmul | +| NN | RT | RA | RB | 1 | 10 | 0001 110 |Rc| | | NN | RT | RB | RB | 1 | 11 | 0001 110 |Rc| clinv | | NN | RA | RB | RC | 0 | 00 | 0001 110 |Rc| vec sbfm | | NN | RA | RB | RC | 0 | 01 | 0001 110 |Rc| vec sofm | @@ -131,16 +131,23 @@ double check that instructions didn't need 3 inputs. | NN | RA | RB | RC | 1 | 00 | 0101 110 |Rc| av abss | | NN | RA | RB | RC | 1 | 01 | 0101 110 |Rc| av absu| | NN | RA | RB | | 1 | 10 | 0101 110 |Rc| av avgadd | -| NN | RA | RB | RC | 1 | 11 | 0101 110 |Rc| grevw | +| NN | RA | RB | | 1 | 11 | 0101 110 |Rc| rsvd | | NN | RA | RB | | | | 1001 110 |Rc| rsvd | -| NN | RA | RB | RC | 0 | 00 | 1101 110 |Rc| bmator | -| NN | RA | RB | RC | 1 | 00 | 1101 110 |Rc| bmatxor | -| NN | RA | RB | sh | 0 | 01 | 1101 110 |Rc| grevwi | -| NN | RA | RB | RC | 1 | 01 | 1101 110 |Rc| grev | -| NN | RA | RB | sh | SH | 10 | 1101 110 |Rc| grevi | -| NN | RA | RB | RC | 0 | 11 | 1101 110 |Rc| clmulr | -| NN | RA | RB | RC | 1 | 11 | 1101 110 |Rc| clmulh | -| NN | RA | RB | RC | | | --10 110 |Rc| rsvd | +| NN | RA | RB | | | | 1101 110 |Rc| rsvd | +| NN | RA | RB | RC | 0 | 00 | 0010 110 |Rc| gorc | +| NN | RA | RB | sh | SH | 00 | 1010 110 |Rc| gorci | +| NN | RA | RB | RC | 0 | 00 | 0110 110 |Rc| gorcw | +| NN | RA | RB | sh | 0 | 00 | 1110 110 |Rc| gorcwi | +| NN | RA | RB | RC | 1 | 00 | 1110 110 |Rc| bmator | +| NN | RA | RB | RC | 0 | 01 | 0010 110 |Rc| grev | +| NN | RA | RB | RC | 1 | 01 | 0010 110 |Rc| clmul | +| NN | RA | RB | sh | SH | 01 | 1010 110 |Rc| grevi | +| NN | RA | RB | RC | 0 | 01 | 0110 110 |Rc| grevw | +| NN | RA | RB | sh | 0 | 01 | 1110 110 |Rc| grevwi | +| NN | RA | RB | RC | 1 | 01 | 1110 110 |Rc| bmatxor | +| NN | RA | RB | RC | | 10 | --10 110 |Rc| rsvd | +| NN | RA | RB | RC | 0 | 11 | 1110 110 |Rc| clmulr | +| NN | RA | RB | RC | 1 | 11 | 1110 110 |Rc| clmulh | | NN | | | | | | --11 110 |Rc| setvl | # ternlog bitops -- 2.30.2