From a5965b52876dded2c1bd7d743ad4b1f47708d41f Mon Sep 17 00:00:00 2001 From: Michael Meissner Date: Wed, 29 May 2013 20:48:29 +0000 Subject: [PATCH] vector.md (VEC_I): Add support for new power8 V2DI instructions. 2013-05-29 Michael Meissner Pat Haugen Peter Bergner * config/rs6000/vector.md (VEC_I): Add support for new power8 V2DI instructions. (VEC_A): Likewise. (VEC_C): Likewise. (vrotl3): Likewise. (vashl3): Likewise. (vlshr3): Likewise. (vashr3): Likewise. * config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add support for power8 V2DI builtins. * config/rs6000/rs6000-builtin.def (abs_v2di): Add support for power8 V2DI builtins. (vupkhsw): Likewise. (vupklsw): Likewise. (vaddudm): Likewise. (vminsd): Likewise. (vmaxsd): Likewise. (vminud): Likewise. (vmaxud): Likewise. (vpkudum): Likewise. (vpksdss): Likewise. (vpkudus): Likewise. (vpksdus): Likewise. (vrld): Likewise. (vsld): Likewise. (vsrd): Likewise. (vsrad): Likewise. (vsubudm): Likewise. (vcmpequd): Likewise. (vcmpgtsd): Likewise. (vcmpgtud): Likewise. (vcmpequd_p): Likewise. (vcmpgtsd_p): Likewise. (vcmpgtud_p): Likewise. (vupkhsw): Likewise. (vupklsw): Likewise. (vaddudm): Likewise. (vmaxsd): Likewise. (vmaxud): Likewise. (vminsd): Likewise. (vminud): Likewise. (vpksdss): Likewise. (vpksdus): Likewise. (vpkudum): Likewise. (vpkudus): Likewise. (vrld): Likewise. (vsld): Likewise. (vsrad): Likewise. (vsrd): Likewise. (vsubudm): Likewise. * config/rs6000/rs6000.c (rs6000_init_hard_regno_mode_ok): Add support for power8 V2DI instructions. * config/rs6000/altivec.md (UNSPEC_VPKUHUM): Add support for power8 V2DI instructions. Combine pack and unpack insns to use an iterator for each mode. Check whether a particular mode supports Altivec instructions instead of just checking TARGET_ALTIVEC. (UNSPEC_VPKUWUM): Likewise. (UNSPEC_VPKSHSS): Likewise. (UNSPEC_VPKSWSS): Likewise. (UNSPEC_VPKUHUS): Likewise. (UNSPEC_VPKSHUS): Likewise. (UNSPEC_VPKUWUS): Likewise. (UNSPEC_VPKSWUS): Likewise. (UNSPEC_VPACK_SIGN_SIGN_SAT): Likewise. (UNSPEC_VPACK_SIGN_UNS_SAT): Likewise. (UNSPEC_VPACK_UNS_UNS_SAT): Likewise. (UNSPEC_VPACK_UNS_UNS_MOD): Likewise. (UNSPEC_VUPKHSB): Likewise. (UNSPEC_VUNPACK_HI_SIGN): Likewise. (UNSPEC_VUNPACK_LO_SIGN): Likewise. (UNSPEC_VUPKHSH): Likewise. (UNSPEC_VUPKLSB): Likewise. (UNSPEC_VUPKLSH): Likewise. (VI2): Likewise. (VI_char): Likewise. (VI_scalar): Likewise. (VI_unit): Likewise. (VP): Likewise. (VP_small): Likewise. (VP_small_lc): Likewise. (VU_char): Likewise. (add3): Likewise. (altivec_vaddcuw): Likewise. (altivec_vaddus): Likewise. (altivec_vaddss): Likewise. (sub3): Likewise. (altivec_vsubcuw): Likewise. (altivec_vsubus): Likewise. (altivec_vsubss): Likewise. (altivec_vavgs): Likewise. (altivec_vcmpbfp): Likewise. (altivec_eq): Likewise. (altivec_gt): Likewise. (altivec_gtu): Likewise. (umax3): Likewise. (smax3): Likewise. (umin3): Likewise. (smin3): Likewise. (altivec_vpkuhum): Likewise. (altivec_vpkuwum): Likewise. (altivec_vpkshss): Likewise. (altivec_vpkswss): Likewise. (altivec_vpkuhus): Likewise. (altivec_vpkshus): Likewise. (altivec_vpkuwus): Likewise. (altivec_vpkswus): Likewise. (altivec_vpksss): Likewise. (altivec_vpksus): Likewise. (altivec_vpkuus): Likewise. (altivec_vpkuum): Likewise. (altivec_vrl): Likewise. (altivec_vsl): Likewise. (altivec_vsr): Likewise. (altivec_vsra): Likewise. (altivec_vsldoi_): Likewise. (altivec_vupkhsb): Likewise. (altivec_vupkhs): Likewise. (altivec_vupkls): Likewise. (altivec_vupkhsh): Likewise. (altivec_vupklsb): Likewise. (altivec_vupklsh): Likewise. (altivec_vcmpequ_p): Likewise. (altivec_vcmpgts_p): Likewise. (altivec_vcmpgtu_p): Likewise. (abs2): Likewise. (vec_unpacks_hi_v16qi): Likewise. (vec_unpacks_hi_v8hi): Likewise. (vec_unpacks_lo_v16qi): Likewise. (vec_unpacks_hi_): Likewise. (vec_unpacks_lo_v8hi): Likewise. (vec_unpacks_lo_): Likewise. (vec_pack_trunc_v8h): Likewise. (vec_pack_trunc_v4si): Likewise. (vec_pack_trunc_): Likewise. * config/rs6000/altivec.h (vec_vaddudm): Add defines for power8 V2DI builtins. (vec_vmaxsd): Likewise. (vec_vmaxud): Likewise. (vec_vminsd): Likewise. (vec_vminud): Likewise. (vec_vpksdss): Likewise. (vec_vpksdus): Likewise. (vec_vpkudum): Likewise. (vec_vpkudus): Likewise. (vec_vrld): Likewise. (vec_vsld): Likewise. (vec_vsrad): Likewise. (vec_vsrd): Likewise. (vec_vsubudm): Likewise. (vec_vupkhsw): Likewise. (vec_vupklsw): Likewise. Co-Authored-By: Pat Haugen Co-Authored-By: Peter Bergner From-SVN: r199423 --- gcc/ChangeLog | 161 ++++++++++ gcc/config/rs6000/altivec.h | 20 ++ gcc/config/rs6000/altivec.md | 446 +++++++++++---------------- gcc/config/rs6000/rs6000-builtin.def | 56 +++- gcc/config/rs6000/rs6000-c.c | 132 ++++++++ gcc/config/rs6000/rs6000.c | 7 +- gcc/config/rs6000/vector.md | 14 +- gcc/doc/extend.texi | 137 ++++++++ 8 files changed, 693 insertions(+), 280 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 54f944a50ec..c40662a22c8 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,164 @@ +2013-05-29 Michael Meissner + Pat Haugen + Peter Bergner + + * config/rs6000/vector.md (VEC_I): Add support for new power8 V2DI + instructions. + (VEC_A): Likewise. + (VEC_C): Likewise. + (vrotl3): Likewise. + (vashl3): Likewise. + (vlshr3): Likewise. + (vashr3): Likewise. + + * config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add + support for power8 V2DI builtins. + + * config/rs6000/rs6000-builtin.def (abs_v2di): Add support for + power8 V2DI builtins. + (vupkhsw): Likewise. + (vupklsw): Likewise. + (vaddudm): Likewise. + (vminsd): Likewise. + (vmaxsd): Likewise. + (vminud): Likewise. + (vmaxud): Likewise. + (vpkudum): Likewise. + (vpksdss): Likewise. + (vpkudus): Likewise. + (vpksdus): Likewise. + (vrld): Likewise. + (vsld): Likewise. + (vsrd): Likewise. + (vsrad): Likewise. + (vsubudm): Likewise. + (vcmpequd): Likewise. + (vcmpgtsd): Likewise. + (vcmpgtud): Likewise. + (vcmpequd_p): Likewise. + (vcmpgtsd_p): Likewise. + (vcmpgtud_p): Likewise. + (vupkhsw): Likewise. + (vupklsw): Likewise. + (vaddudm): Likewise. + (vmaxsd): Likewise. + (vmaxud): Likewise. + (vminsd): Likewise. + (vminud): Likewise. + (vpksdss): Likewise. + (vpksdus): Likewise. + (vpkudum): Likewise. + (vpkudus): Likewise. + (vrld): Likewise. + (vsld): Likewise. + (vsrad): Likewise. + (vsrd): Likewise. + (vsubudm): Likewise. + + * config/rs6000/rs6000.c (rs6000_init_hard_regno_mode_ok): Add + support for power8 V2DI instructions. + + * config/rs6000/altivec.md (UNSPEC_VPKUHUM): Add support for + power8 V2DI instructions. Combine pack and unpack insns to use an + iterator for each mode. Check whether a particular mode supports + Altivec instructions instead of just checking TARGET_ALTIVEC. + (UNSPEC_VPKUWUM): Likewise. + (UNSPEC_VPKSHSS): Likewise. + (UNSPEC_VPKSWSS): Likewise. + (UNSPEC_VPKUHUS): Likewise. + (UNSPEC_VPKSHUS): Likewise. + (UNSPEC_VPKUWUS): Likewise. + (UNSPEC_VPKSWUS): Likewise. + (UNSPEC_VPACK_SIGN_SIGN_SAT): Likewise. + (UNSPEC_VPACK_SIGN_UNS_SAT): Likewise. + (UNSPEC_VPACK_UNS_UNS_SAT): Likewise. + (UNSPEC_VPACK_UNS_UNS_MOD): Likewise. + (UNSPEC_VUPKHSB): Likewise. + (UNSPEC_VUNPACK_HI_SIGN): Likewise. + (UNSPEC_VUNPACK_LO_SIGN): Likewise. + (UNSPEC_VUPKHSH): Likewise. + (UNSPEC_VUPKLSB): Likewise. + (UNSPEC_VUPKLSH): Likewise. + (VI2): Likewise. + (VI_char): Likewise. + (VI_scalar): Likewise. + (VI_unit): Likewise. + (VP): Likewise. + (VP_small): Likewise. + (VP_small_lc): Likewise. + (VU_char): Likewise. + (add3): Likewise. + (altivec_vaddcuw): Likewise. + (altivec_vaddus): Likewise. + (altivec_vaddss): Likewise. + (sub3): Likewise. + (altivec_vsubcuw): Likewise. + (altivec_vsubus): Likewise. + (altivec_vsubss): Likewise. + (altivec_vavgs): Likewise. + (altivec_vcmpbfp): Likewise. + (altivec_eq): Likewise. + (altivec_gt): Likewise. + (altivec_gtu): Likewise. + (umax3): Likewise. + (smax3): Likewise. + (umin3): Likewise. + (smin3): Likewise. + (altivec_vpkuhum): Likewise. + (altivec_vpkuwum): Likewise. + (altivec_vpkshss): Likewise. + (altivec_vpkswss): Likewise. + (altivec_vpkuhus): Likewise. + (altivec_vpkshus): Likewise. + (altivec_vpkuwus): Likewise. + (altivec_vpkswus): Likewise. + (altivec_vpksss): Likewise. + (altivec_vpksus): Likewise. + (altivec_vpkuus): Likewise. + (altivec_vpkuum): Likewise. + (altivec_vrl): Likewise. + (altivec_vsl): Likewise. + (altivec_vsr): Likewise. + (altivec_vsra): Likewise. + (altivec_vsldoi_): Likewise. + (altivec_vupkhsb): Likewise. + (altivec_vupkhs): Likewise. + (altivec_vupkls): Likewise. + (altivec_vupkhsh): Likewise. + (altivec_vupklsb): Likewise. + (altivec_vupklsh): Likewise. + (altivec_vcmpequ_p): Likewise. + (altivec_vcmpgts_p): Likewise. + (altivec_vcmpgtu_p): Likewise. + (abs2): Likewise. + (vec_unpacks_hi_v16qi): Likewise. + (vec_unpacks_hi_v8hi): Likewise. + (vec_unpacks_lo_v16qi): Likewise. + (vec_unpacks_hi_): Likewise. + (vec_unpacks_lo_v8hi): Likewise. + (vec_unpacks_lo_): Likewise. + (vec_pack_trunc_v8h): Likewise. + (vec_pack_trunc_v4si): Likewise. + (vec_pack_trunc_): Likewise. + + * config/rs6000/altivec.h (vec_vaddudm): Add defines for power8 + V2DI builtins. + (vec_vmaxsd): Likewise. + (vec_vmaxud): Likewise. + (vec_vminsd): Likewise. + (vec_vminud): Likewise. + (vec_vpksdss): Likewise. + (vec_vpksdus): Likewise. + (vec_vpkudum): Likewise. + (vec_vpkudus): Likewise. + (vec_vrld): Likewise. + (vec_vsld): Likewise. + (vec_vsrad): Likewise. + (vec_vsrd): Likewise. + (vec_vsubudm): Likewise. + (vec_vupkhsw): Likewise. + (vec_vupklsw): Likewise. + 2013-05-29 Jan Hubicka * cgraph.h (symtab_node_base): Add definition, alias and analyzed diff --git a/gcc/config/rs6000/altivec.h b/gcc/config/rs6000/altivec.h index fd6d07f50ff..19a4ae9297d 100644 --- a/gcc/config/rs6000/altivec.h +++ b/gcc/config/rs6000/altivec.h @@ -321,6 +321,26 @@ #define vec_vsx_st __builtin_vec_vsx_st #endif +#ifdef _ARCH_PWR8 +/* Vector additions added in ISA 2.07. */ +#define vec_vaddudm __builtin_vec_vaddudm +#define vec_vmaxsd __builtin_vec_vmaxsd +#define vec_vmaxud __builtin_vec_vmaxud +#define vec_vminsd __builtin_vec_vminsd +#define vec_vminud __builtin_vec_vminud +#define vec_vpksdss __builtin_vec_vpksdss +#define vec_vpksdus __builtin_vec_vpksdus +#define vec_vpkudum __builtin_vec_vpkudum +#define vec_vpkudus __builtin_vec_vpkudus +#define vec_vrld __builtin_vec_vrld +#define vec_vsld __builtin_vec_vsld +#define vec_vsrad __builtin_vec_vsrad +#define vec_vsrd __builtin_vec_vsrd +#define vec_vsubudm __builtin_vec_vsubudm +#define vec_vupkhsw __builtin_vec_vupkhsw +#define vec_vupklsw __builtin_vec_vupklsw +#endif + /* Predicates. For C++, we use templates in order to allow non-parenthesized arguments. For C, instead, we use macros since non-parenthesized arguments were diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index 1b0b5c3fb13..78d29001440 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -41,15 +41,11 @@ UNSPEC_VMULOSB UNSPEC_VMULOUH UNSPEC_VMULOSH - UNSPEC_VPKUHUM - UNSPEC_VPKUWUM UNSPEC_VPKPX - UNSPEC_VPKSHSS - UNSPEC_VPKSWSS - UNSPEC_VPKUHUS - UNSPEC_VPKSHUS - UNSPEC_VPKUWUS - UNSPEC_VPKSWUS + UNSPEC_VPACK_SIGN_SIGN_SAT + UNSPEC_VPACK_SIGN_UNS_SAT + UNSPEC_VPACK_UNS_UNS_SAT + UNSPEC_VPACK_UNS_UNS_MOD UNSPEC_VSLV4SI UNSPEC_VSLO UNSPEC_VSR @@ -71,12 +67,10 @@ UNSPEC_VLOGEFP UNSPEC_VEXPTEFP UNSPEC_VLSDOI - UNSPEC_VUPKHSB + UNSPEC_VUNPACK_HI_SIGN + UNSPEC_VUNPACK_LO_SIGN UNSPEC_VUPKHPX - UNSPEC_VUPKHSH - UNSPEC_VUPKLSB UNSPEC_VUPKLPX - UNSPEC_VUPKLSH UNSPEC_DST UNSPEC_DSTT UNSPEC_DSTST @@ -146,6 +140,8 @@ ;; Vec int modes (define_mode_iterator VI [V4SI V8HI V16QI]) +;; Like VI, but add ISA 2.07 integer vector ops +(define_mode_iterator VI2 [V4SI V8HI V16QI V2DI]) ;; Short vec in modes (define_mode_iterator VIshort [V8HI V16QI]) ;; Vec float modes @@ -159,8 +155,18 @@ ;; Like VM, except don't do TImode (define_mode_iterator VM2 [V4SI V8HI V16QI V4SF V2DF V2DI]) -(define_mode_attr VI_char [(V4SI "w") (V8HI "h") (V16QI "b")]) -(define_mode_attr VI_scalar [(V4SI "SI") (V8HI "HI") (V16QI "QI")]) +(define_mode_attr VI_char [(V2DI "d") (V4SI "w") (V8HI "h") (V16QI "b")]) +(define_mode_attr VI_scalar [(V2DI "DI") (V4SI "SI") (V8HI "HI") (V16QI "QI")]) +(define_mode_attr VI_unit [(V16QI "VECTOR_UNIT_ALTIVEC_P (V16QImode)") + (V8HI "VECTOR_UNIT_ALTIVEC_P (V8HImode)") + (V4SI "VECTOR_UNIT_ALTIVEC_P (V4SImode)") + (V2DI "VECTOR_UNIT_P8_VECTOR_P (V2DImode)")]) + +;; Vector pack/unpack +(define_mode_iterator VP [V2DI V4SI V8HI]) +(define_mode_attr VP_small [(V2DI "V4SI") (V4SI "V8HI") (V8HI "V16QI")]) +(define_mode_attr VP_small_lc [(V2DI "v4si") (V4SI "v8hi") (V8HI "v16qi")]) +(define_mode_attr VU_char [(V2DI "w") (V4SI "h") (V8HI "b")]) ;; Vector move instructions. (define_insn "*altivec_mov" @@ -378,10 +384,10 @@ ;; add (define_insn "add3" - [(set (match_operand:VI 0 "register_operand" "=v") - (plus:VI (match_operand:VI 1 "register_operand" "v") - (match_operand:VI 2 "register_operand" "v")))] - "TARGET_ALTIVEC" + [(set (match_operand:VI2 0 "register_operand" "=v") + (plus:VI2 (match_operand:VI2 1 "register_operand" "v") + (match_operand:VI2 2 "register_operand" "v")))] + "" "vaddum %0,%1,%2" [(set_attr "type" "vecsimple")]) @@ -398,17 +404,17 @@ (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") (match_operand:V4SI 2 "register_operand" "v")] UNSPEC_VADDCUW))] - "TARGET_ALTIVEC" + "VECTOR_UNIT_ALTIVEC_P (V4SImode)" "vaddcuw %0,%1,%2" [(set_attr "type" "vecsimple")]) (define_insn "altivec_vaddus" [(set (match_operand:VI 0 "register_operand" "=v") (unspec:VI [(match_operand:VI 1 "register_operand" "v") - (match_operand:VI 2 "register_operand" "v")] + (match_operand:VI 2 "register_operand" "v")] UNSPEC_VADDU)) (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] - "TARGET_ALTIVEC" + "" "vaddus %0,%1,%2" [(set_attr "type" "vecsimple")]) @@ -418,16 +424,16 @@ (match_operand:VI 2 "register_operand" "v")] UNSPEC_VADDS)) (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] - "TARGET_ALTIVEC" + "VECTOR_UNIT_ALTIVEC_P (mode)" "vaddss %0,%1,%2" [(set_attr "type" "vecsimple")]) ;; sub (define_insn "sub3" - [(set (match_operand:VI 0 "register_operand" "=v") - (minus:VI (match_operand:VI 1 "register_operand" "v") - (match_operand:VI 2 "register_operand" "v")))] - "TARGET_ALTIVEC" + [(set (match_operand:VI2 0 "register_operand" "=v") + (minus:VI2 (match_operand:VI2 1 "register_operand" "v") + (match_operand:VI2 2 "register_operand" "v")))] + "" "vsubum %0,%1,%2" [(set_attr "type" "vecsimple")]) @@ -444,7 +450,7 @@ (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") (match_operand:V4SI 2 "register_operand" "v")] UNSPEC_VSUBCUW))] - "TARGET_ALTIVEC" + "VECTOR_UNIT_ALTIVEC_P (V4SImode)" "vsubcuw %0,%1,%2" [(set_attr "type" "vecsimple")]) @@ -454,7 +460,7 @@ (match_operand:VI 2 "register_operand" "v")] UNSPEC_VSUBU)) (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] - "TARGET_ALTIVEC" + "VECTOR_UNIT_ALTIVEC_P (mode)" "vsubus %0,%1,%2" [(set_attr "type" "vecsimple")]) @@ -464,7 +470,7 @@ (match_operand:VI 2 "register_operand" "v")] UNSPEC_VSUBS)) (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] - "TARGET_ALTIVEC" + "VECTOR_UNIT_ALTIVEC_P (mode)" "vsubss %0,%1,%2" [(set_attr "type" "vecsimple")]) @@ -483,7 +489,7 @@ (unspec:VI [(match_operand:VI 1 "register_operand" "v") (match_operand:VI 2 "register_operand" "v")] UNSPEC_VAVGS))] - "TARGET_ALTIVEC" + "VECTOR_UNIT_ALTIVEC_P (mode)" "vavgs %0,%1,%2" [(set_attr "type" "vecsimple")]) @@ -492,31 +498,31 @@ (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v") (match_operand:V4SF 2 "register_operand" "v")] UNSPEC_VCMPBFP))] - "TARGET_ALTIVEC" + "VECTOR_UNIT_ALTIVEC_P (V4SImode)" "vcmpbfp %0,%1,%2" [(set_attr "type" "veccmp")]) (define_insn "*altivec_eq" - [(set (match_operand:VI 0 "altivec_register_operand" "=v") - (eq:VI (match_operand:VI 1 "altivec_register_operand" "v") - (match_operand:VI 2 "altivec_register_operand" "v")))] - "TARGET_ALTIVEC" + [(set (match_operand:VI2 0 "altivec_register_operand" "=v") + (eq:VI2 (match_operand:VI2 1 "altivec_register_operand" "v") + (match_operand:VI2 2 "altivec_register_operand" "v")))] + "" "vcmpequ %0,%1,%2" [(set_attr "type" "veccmp")]) (define_insn "*altivec_gt" - [(set (match_operand:VI 0 "altivec_register_operand" "=v") - (gt:VI (match_operand:VI 1 "altivec_register_operand" "v") - (match_operand:VI 2 "altivec_register_operand" "v")))] - "TARGET_ALTIVEC" + [(set (match_operand:VI2 0 "altivec_register_operand" "=v") + (gt:VI2 (match_operand:VI2 1 "altivec_register_operand" "v") + (match_operand:VI2 2 "altivec_register_operand" "v")))] + "" "vcmpgts %0,%1,%2" [(set_attr "type" "veccmp")]) (define_insn "*altivec_gtu" - [(set (match_operand:VI 0 "altivec_register_operand" "=v") - (gtu:VI (match_operand:VI 1 "altivec_register_operand" "v") - (match_operand:VI 2 "altivec_register_operand" "v")))] - "TARGET_ALTIVEC" + [(set (match_operand:VI2 0 "altivec_register_operand" "=v") + (gtu:VI2 (match_operand:VI2 1 "altivec_register_operand" "v") + (match_operand:VI2 2 "altivec_register_operand" "v")))] + "" "vcmpgtu %0,%1,%2" [(set_attr "type" "veccmp")]) @@ -744,18 +750,18 @@ ;; max (define_insn "umax3" - [(set (match_operand:VI 0 "register_operand" "=v") - (umax:VI (match_operand:VI 1 "register_operand" "v") - (match_operand:VI 2 "register_operand" "v")))] - "TARGET_ALTIVEC" + [(set (match_operand:VI2 0 "register_operand" "=v") + (umax:VI2 (match_operand:VI2 1 "register_operand" "v") + (match_operand:VI2 2 "register_operand" "v")))] + "" "vmaxu %0,%1,%2" [(set_attr "type" "vecsimple")]) (define_insn "smax3" - [(set (match_operand:VI 0 "register_operand" "=v") - (smax:VI (match_operand:VI 1 "register_operand" "v") - (match_operand:VI 2 "register_operand" "v")))] - "TARGET_ALTIVEC" + [(set (match_operand:VI2 0 "register_operand" "=v") + (smax:VI2 (match_operand:VI2 1 "register_operand" "v") + (match_operand:VI2 2 "register_operand" "v")))] + "" "vmaxs %0,%1,%2" [(set_attr "type" "vecsimple")]) @@ -768,18 +774,18 @@ [(set_attr "type" "veccmp")]) (define_insn "umin3" - [(set (match_operand:VI 0 "register_operand" "=v") - (umin:VI (match_operand:VI 1 "register_operand" "v") - (match_operand:VI 2 "register_operand" "v")))] - "TARGET_ALTIVEC" + [(set (match_operand:VI2 0 "register_operand" "=v") + (umin:VI2 (match_operand:VI2 1 "register_operand" "v") + (match_operand:VI2 2 "register_operand" "v")))] + "" "vminu %0,%1,%2" [(set_attr "type" "vecsimple")]) (define_insn "smin3" - [(set (match_operand:VI 0 "register_operand" "=v") - (smin:VI (match_operand:VI 1 "register_operand" "v") - (match_operand:VI 2 "register_operand" "v")))] - "TARGET_ALTIVEC" + [(set (match_operand:VI2 0 "register_operand" "=v") + (smin:VI2 (match_operand:VI2 1 "register_operand" "v") + (match_operand:VI2 2 "register_operand" "v")))] + "" "vmins %0,%1,%2" [(set_attr "type" "vecsimple")]) @@ -1058,24 +1064,6 @@ "vandc %0,%1,%2" [(set_attr "type" "vecsimple")]) -(define_insn "altivec_vpkuhum" - [(set (match_operand:V16QI 0 "register_operand" "=v") - (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v") - (match_operand:V8HI 2 "register_operand" "v")] - UNSPEC_VPKUHUM))] - "TARGET_ALTIVEC" - "vpkuhum %0,%1,%2" - [(set_attr "type" "vecperm")]) - -(define_insn "altivec_vpkuwum" - [(set (match_operand:V8HI 0 "register_operand" "=v") - (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v") - (match_operand:V4SI 2 "register_operand" "v")] - UNSPEC_VPKUWUM))] - "TARGET_ALTIVEC" - "vpkuwum %0,%1,%2" - [(set_attr "type" "vecperm")]) - (define_insn "altivec_vpkpx" [(set (match_operand:V8HI 0 "register_operand" "=v") (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v") @@ -1085,71 +1073,47 @@ "vpkpx %0,%1,%2" [(set_attr "type" "vecperm")]) -(define_insn "altivec_vpkshss" - [(set (match_operand:V16QI 0 "register_operand" "=v") - (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v") - (match_operand:V8HI 2 "register_operand" "v")] - UNSPEC_VPKSHSS)) - (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] - "TARGET_ALTIVEC" - "vpkshss %0,%1,%2" - [(set_attr "type" "vecperm")]) - -(define_insn "altivec_vpkswss" - [(set (match_operand:V8HI 0 "register_operand" "=v") - (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v") - (match_operand:V4SI 2 "register_operand" "v")] - UNSPEC_VPKSWSS)) - (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] - "TARGET_ALTIVEC" - "vpkswss %0,%1,%2" - [(set_attr "type" "vecperm")]) - -(define_insn "altivec_vpkuhus" - [(set (match_operand:V16QI 0 "register_operand" "=v") - (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v") - (match_operand:V8HI 2 "register_operand" "v")] - UNSPEC_VPKUHUS)) - (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] - "TARGET_ALTIVEC" - "vpkuhus %0,%1,%2" +(define_insn "altivec_vpksss" + [(set (match_operand: 0 "register_operand" "=v") + (unspec: [(match_operand:VP 1 "register_operand" "v") + (match_operand:VP 2 "register_operand" "v")] + UNSPEC_VPACK_SIGN_SIGN_SAT))] + "" + "vpksss %0,%1,%2" [(set_attr "type" "vecperm")]) -(define_insn "altivec_vpkshus" - [(set (match_operand:V16QI 0 "register_operand" "=v") - (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v") - (match_operand:V8HI 2 "register_operand" "v")] - UNSPEC_VPKSHUS)) - (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] - "TARGET_ALTIVEC" - "vpkshus %0,%1,%2" +(define_insn "altivec_vpksus" + [(set (match_operand: 0 "register_operand" "=v") + (unspec: [(match_operand:VP 1 "register_operand" "v") + (match_operand:VP 2 "register_operand" "v")] + UNSPEC_VPACK_SIGN_UNS_SAT))] + "" + "vpksus %0,%1,%2" [(set_attr "type" "vecperm")]) -(define_insn "altivec_vpkuwus" - [(set (match_operand:V8HI 0 "register_operand" "=v") - (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v") - (match_operand:V4SI 2 "register_operand" "v")] - UNSPEC_VPKUWUS)) - (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] - "TARGET_ALTIVEC" - "vpkuwus %0,%1,%2" +(define_insn "altivec_vpkuus" + [(set (match_operand: 0 "register_operand" "=v") + (unspec: [(match_operand:VP 1 "register_operand" "v") + (match_operand:VP 2 "register_operand" "v")] + UNSPEC_VPACK_UNS_UNS_SAT))] + "" + "vpkuus %0,%1,%2" [(set_attr "type" "vecperm")]) -(define_insn "altivec_vpkswus" - [(set (match_operand:V8HI 0 "register_operand" "=v") - (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v") - (match_operand:V4SI 2 "register_operand" "v")] - UNSPEC_VPKSWUS)) - (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] - "TARGET_ALTIVEC" - "vpkswus %0,%1,%2" +(define_insn "altivec_vpkuum" + [(set (match_operand: 0 "register_operand" "=v") + (unspec: [(match_operand:VP 1 "register_operand" "v") + (match_operand:VP 2 "register_operand" "v")] + UNSPEC_VPACK_UNS_UNS_MOD))] + "" + "vpkuum %0,%1,%2" [(set_attr "type" "vecperm")]) (define_insn "*altivec_vrl" - [(set (match_operand:VI 0 "register_operand" "=v") - (rotate:VI (match_operand:VI 1 "register_operand" "v") - (match_operand:VI 2 "register_operand" "v")))] - "TARGET_ALTIVEC" + [(set (match_operand:VI2 0 "register_operand" "=v") + (rotate:VI2 (match_operand:VI2 1 "register_operand" "v") + (match_operand:VI2 2 "register_operand" "v")))] + "" "vrl %0,%1,%2" [(set_attr "type" "vecsimple")]) @@ -1172,26 +1136,26 @@ [(set_attr "type" "vecperm")]) (define_insn "*altivec_vsl" - [(set (match_operand:VI 0 "register_operand" "=v") - (ashift:VI (match_operand:VI 1 "register_operand" "v") - (match_operand:VI 2 "register_operand" "v")))] - "TARGET_ALTIVEC" + [(set (match_operand:VI2 0 "register_operand" "=v") + (ashift:VI2 (match_operand:VI2 1 "register_operand" "v") + (match_operand:VI2 2 "register_operand" "v")))] + "" "vsl %0,%1,%2" [(set_attr "type" "vecsimple")]) (define_insn "*altivec_vsr" - [(set (match_operand:VI 0 "register_operand" "=v") - (lshiftrt:VI (match_operand:VI 1 "register_operand" "v") - (match_operand:VI 2 "register_operand" "v")))] - "TARGET_ALTIVEC" + [(set (match_operand:VI2 0 "register_operand" "=v") + (lshiftrt:VI2 (match_operand:VI2 1 "register_operand" "v") + (match_operand:VI2 2 "register_operand" "v")))] + "" "vsr %0,%1,%2" [(set_attr "type" "vecsimple")]) (define_insn "*altivec_vsra" - [(set (match_operand:VI 0 "register_operand" "=v") - (ashiftrt:VI (match_operand:VI 1 "register_operand" "v") - (match_operand:VI 2 "register_operand" "v")))] - "TARGET_ALTIVEC" + [(set (match_operand:VI2 0 "register_operand" "=v") + (ashiftrt:VI2 (match_operand:VI2 1 "register_operand" "v") + (match_operand:VI2 2 "register_operand" "v")))] + "" "vsra %0,%1,%2" [(set_attr "type" "vecsimple")]) @@ -1476,12 +1440,20 @@ "vsldoi %0,%1,%2,%3" [(set_attr "type" "vecperm")]) -(define_insn "altivec_vupkhsb" - [(set (match_operand:V8HI 0 "register_operand" "=v") - (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")] - UNSPEC_VUPKHSB))] - "TARGET_ALTIVEC" - "vupkhsb %0,%1" +(define_insn "altivec_vupkhs" + [(set (match_operand:VP 0 "register_operand" "=v") + (unspec:VP [(match_operand: 1 "register_operand" "v")] + UNSPEC_VUNPACK_HI_SIGN))] + "" + "vupkhs %0,%1" + [(set_attr "type" "vecperm")]) + +(define_insn "altivec_vupkls" + [(set (match_operand:VP 0 "register_operand" "=v") + (unspec:VP [(match_operand: 1 "register_operand" "v")] + UNSPEC_VUNPACK_LO_SIGN))] + "" + "vupkls %0,%1" [(set_attr "type" "vecperm")]) (define_insn "altivec_vupkhpx" @@ -1492,22 +1464,6 @@ "vupkhpx %0,%1" [(set_attr "type" "vecperm")]) -(define_insn "altivec_vupkhsh" - [(set (match_operand:V4SI 0 "register_operand" "=v") - (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] - UNSPEC_VUPKHSH))] - "TARGET_ALTIVEC" - "vupkhsh %0,%1" - [(set_attr "type" "vecperm")]) - -(define_insn "altivec_vupklsb" - [(set (match_operand:V8HI 0 "register_operand" "=v") - (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")] - UNSPEC_VUPKLSB))] - "TARGET_ALTIVEC" - "vupklsb %0,%1" - [(set_attr "type" "vecperm")]) - (define_insn "altivec_vupklpx" [(set (match_operand:V4SI 0 "register_operand" "=v") (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] @@ -1516,49 +1472,41 @@ "vupklpx %0,%1" [(set_attr "type" "vecperm")]) -(define_insn "altivec_vupklsh" - [(set (match_operand:V4SI 0 "register_operand" "=v") - (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] - UNSPEC_VUPKLSH))] - "TARGET_ALTIVEC" - "vupklsh %0,%1" - [(set_attr "type" "vecperm")]) - ;; Compare vectors producing a vector result and a predicate, setting CR6 to ;; indicate a combined status (define_insn "*altivec_vcmpequ_p" [(set (reg:CC 74) - (unspec:CC [(eq:CC (match_operand:VI 1 "register_operand" "v") - (match_operand:VI 2 "register_operand" "v"))] + (unspec:CC [(eq:CC (match_operand:VI2 1 "register_operand" "v") + (match_operand:VI2 2 "register_operand" "v"))] UNSPEC_PREDICATE)) - (set (match_operand:VI 0 "register_operand" "=v") - (eq:VI (match_dup 1) - (match_dup 2)))] - "VECTOR_UNIT_ALTIVEC_P (mode)" + (set (match_operand:VI2 0 "register_operand" "=v") + (eq:VI2 (match_dup 1) + (match_dup 2)))] + "" "vcmpequ. %0,%1,%2" [(set_attr "type" "veccmp")]) (define_insn "*altivec_vcmpgts_p" [(set (reg:CC 74) - (unspec:CC [(gt:CC (match_operand:VI 1 "register_operand" "v") - (match_operand:VI 2 "register_operand" "v"))] + (unspec:CC [(gt:CC (match_operand:VI2 1 "register_operand" "v") + (match_operand:VI2 2 "register_operand" "v"))] UNSPEC_PREDICATE)) - (set (match_operand:VI 0 "register_operand" "=v") - (gt:VI (match_dup 1) - (match_dup 2)))] - "VECTOR_UNIT_ALTIVEC_P (mode)" + (set (match_operand:VI2 0 "register_operand" "=v") + (gt:VI2 (match_dup 1) + (match_dup 2)))] + "" "vcmpgts. %0,%1,%2" [(set_attr "type" "veccmp")]) (define_insn "*altivec_vcmpgtu_p" [(set (reg:CC 74) - (unspec:CC [(gtu:CC (match_operand:VI 1 "register_operand" "v") - (match_operand:VI 2 "register_operand" "v"))] + (unspec:CC [(gtu:CC (match_operand:VI2 1 "register_operand" "v") + (match_operand:VI2 2 "register_operand" "v"))] UNSPEC_PREDICATE)) - (set (match_operand:VI 0 "register_operand" "=v") - (gtu:VI (match_dup 1) - (match_dup 2)))] - "VECTOR_UNIT_ALTIVEC_P (mode)" + (set (match_operand:VI2 0 "register_operand" "=v") + (gtu:VI2 (match_dup 1) + (match_dup 2)))] + "" "vcmpgtu. %0,%1,%2" [(set_attr "type" "veccmp")]) @@ -1779,20 +1727,28 @@ [(set_attr "type" "vecstore")]) ;; Generate -;; vspltis? SCRATCH0,0 +;; xxlxor/vxor SCRATCH0,SCRATCH0,SCRATCH0 ;; vsubu?m SCRATCH2,SCRATCH1,%1 ;; vmaxs? %0,%1,SCRATCH2" (define_expand "abs2" - [(set (match_dup 2) (vec_duplicate:VI (const_int 0))) - (set (match_dup 3) - (minus:VI (match_dup 2) - (match_operand:VI 1 "register_operand" "v"))) - (set (match_operand:VI 0 "register_operand" "=v") - (smax:VI (match_dup 1) (match_dup 3)))] - "TARGET_ALTIVEC" + [(set (match_dup 2) (match_dup 3)) + (set (match_dup 4) + (minus:VI2 (match_dup 2) + (match_operand:VI2 1 "register_operand" "v"))) + (set (match_operand:VI2 0 "register_operand" "=v") + (smax:VI2 (match_dup 1) (match_dup 4)))] + "" { - operands[2] = gen_reg_rtx (GET_MODE (operands[0])); - operands[3] = gen_reg_rtx (GET_MODE (operands[0])); + int i, n_elt = GET_MODE_NUNITS (mode); + rtvec v = rtvec_alloc (n_elt); + + /* Create an all 0 constant. */ + for (i = 0; i < n_elt; ++i) + RTVEC_ELT (v, i) = const0_rtx; + + operands[2] = gen_reg_rtx (mode); + operands[3] = gen_rtx_CONST_VECTOR (mode, v); + operands[4] = gen_reg_rtx (mode); }) ;; Generate @@ -1950,49 +1906,19 @@ DONE; }") -(define_expand "vec_unpacks_hi_v16qi" - [(set (match_operand:V8HI 0 "register_operand" "=v") - (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")] - UNSPEC_VUPKHSB))] - "TARGET_ALTIVEC" - " -{ - emit_insn (gen_altivec_vupkhsb (operands[0], operands[1])); - DONE; -}") - -(define_expand "vec_unpacks_hi_v8hi" - [(set (match_operand:V4SI 0 "register_operand" "=v") - (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] - UNSPEC_VUPKHSH))] - "TARGET_ALTIVEC" - " -{ - emit_insn (gen_altivec_vupkhsh (operands[0], operands[1])); - DONE; -}") - -(define_expand "vec_unpacks_lo_v16qi" - [(set (match_operand:V8HI 0 "register_operand" "=v") - (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")] - UNSPEC_VUPKLSB))] - "TARGET_ALTIVEC" - " -{ - emit_insn (gen_altivec_vupklsb (operands[0], operands[1])); - DONE; -}") +(define_expand "vec_unpacks_hi_" + [(set (match_operand:VP 0 "register_operand" "=v") + (unspec:VP [(match_operand: 1 "register_operand" "v")] + UNSPEC_VUNPACK_HI_SIGN))] + "" + "") -(define_expand "vec_unpacks_lo_v8hi" - [(set (match_operand:V4SI 0 "register_operand" "=v") - (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] - UNSPEC_VUPKLSH))] - "TARGET_ALTIVEC" - " -{ - emit_insn (gen_altivec_vupklsh (operands[0], operands[1])); - DONE; -}") +(define_expand "vec_unpacks_lo_" + [(set (match_operand:VP 0 "register_operand" "=v") + (unspec:VP [(match_operand: 1 "register_operand" "v")] + UNSPEC_VUNPACK_LO_SIGN))] + "" + "") (define_insn "vperm_v8hiv4si" [(set (match_operand:V4SI 0 "register_operand" "=v") @@ -2291,29 +2217,13 @@ DONE; }") -(define_expand "vec_pack_trunc_v8hi" - [(set (match_operand:V16QI 0 "register_operand" "=v") - (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v") - (match_operand:V8HI 2 "register_operand" "v")] - UNSPEC_VPKUHUM))] - "TARGET_ALTIVEC" - " -{ - emit_insn (gen_altivec_vpkuhum (operands[0], operands[1], operands[2])); - DONE; -}") - -(define_expand "vec_pack_trunc_v4si" - [(set (match_operand:V8HI 0 "register_operand" "=v") - (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v") - (match_operand:V4SI 2 "register_operand" "v")] - UNSPEC_VPKUWUM))] - "TARGET_ALTIVEC" - " -{ - emit_insn (gen_altivec_vpkuwum (operands[0], operands[1], operands[2])); - DONE; -}") +(define_expand "vec_pack_trunc_" + [(set (match_operand: 0 "register_operand" "=v") + (unspec: [(match_operand:VP 1 "register_operand" "v") + (match_operand:VP 2 "register_operand" "v")] + UNSPEC_VPACK_UNS_UNS_MOD))] + "" + "") (define_expand "altivec_negv4sf2" [(use (match_operand:V4SF 0 "register_operand" "")) diff --git a/gcc/config/rs6000/rs6000-builtin.def b/gcc/config/rs6000/rs6000-builtin.def index b41f53314c6..7a80eff8924 100644 --- a/gcc/config/rs6000/rs6000-builtin.def +++ b/gcc/config/rs6000/rs6000-builtin.def @@ -30,7 +30,7 @@ RS6000_BUILTIN_A -- ABS builtins RS6000_BUILTIN_D -- DST builtins RS6000_BUILTIN_E -- SPE EVSEL builtins. - RS6000_BUILTIN_P -- Altivec, VSX, Power8 vector predicate builtins + RS6000_BUILTIN_P -- Altivec, VSX, ISA 2.07 vector predicate builtins RS6000_BUILTIN_Q -- Paired floating point VSX predicate builtins RS6000_BUILTIN_S -- SPE predicate builtins RS6000_BUILTIN_X -- special builtins @@ -301,7 +301,7 @@ | RS6000_BTC_SPECIAL), \ CODE_FOR_nothing) /* ICODE */ -/* Power8 vector convenience macros. */ +/* ISA 2.07 (power8) vector convenience macros. */ /* For the instructions that are encoded as altivec instructions use __builtin_altivec_ as the builtin name. */ #define BU_P8V_AV_1(ENUM, NAME, ATTR, ICODE) \ @@ -1233,6 +1233,58 @@ BU_VSX_OVERLOAD_2 (XXSPLTW, "xxspltw") /* VSX builtins that are handled as special cases. */ BU_VSX_OVERLOAD_X (LD, "ld") BU_VSX_OVERLOAD_X (ST, "st") + +/* 1 argument altivec instructions added in ISA 2.07. */ +BU_P8V_AV_1 (ABS_V2DI, "abs_v2di", CONST, absv2di2) +BU_P8V_AV_1 (VUPKHSW, "vupkhsw", CONST, altivec_vupkhsw) +BU_P8V_AV_1 (VUPKLSW, "vupklsw", CONST, altivec_vupklsw) + +/* 2 argument altivec instructions added in ISA 2.07. */ +BU_P8V_AV_2 (VADDUDM, "vaddudm", CONST, addv2di3) +BU_P8V_AV_2 (VMINSD, "vminsd", CONST, sminv2di3) +BU_P8V_AV_2 (VMAXSD, "vmaxsd", CONST, smaxv2di3) +BU_P8V_AV_2 (VMINUD, "vminud", CONST, uminv2di3) +BU_P8V_AV_2 (VMAXUD, "vmaxud", CONST, umaxv2di3) +BU_P8V_AV_2 (VPKUDUM, "vpkudum", CONST, altivec_vpkudum) +BU_P8V_AV_2 (VPKSDSS, "vpksdss", CONST, altivec_vpksdss) +BU_P8V_AV_2 (VPKUDUS, "vpkudus", CONST, altivec_vpkudus) +BU_P8V_AV_2 (VPKSDUS, "vpksdus", CONST, altivec_vpkswus) +BU_P8V_AV_2 (VRLD, "vrld", CONST, vrotlv2di3) +BU_P8V_AV_2 (VSLD, "vsld", CONST, vashlv2di3) +BU_P8V_AV_2 (VSRD, "vsrd", CONST, vlshrv2di3) +BU_P8V_AV_2 (VSRAD, "vsrad", CONST, vashrv2di3) +BU_P8V_AV_2 (VSUBUDM, "vsubudm", CONST, subv2di3) + +/* Vector comparison instructions added in ISA 2.07. */ +BU_P8V_AV_2 (VCMPEQUD, "vcmpequd", CONST, vector_eqv2di) +BU_P8V_AV_2 (VCMPGTSD, "vcmpgtsd", CONST, vector_gtv2di) +BU_P8V_AV_2 (VCMPGTUD, "vcmpgtud", CONST, vector_gtuv2di) + +/* Vector comparison predicate instructions added in ISA 2.07. */ +BU_P8V_AV_P (VCMPEQUD_P, "vcmpequd_p", CONST, vector_eq_v2di_p) +BU_P8V_AV_P (VCMPGTSD_P, "vcmpgtsd_p", CONST, vector_gt_v2di_p) +BU_P8V_AV_P (VCMPGTUD_P, "vcmpgtud_p", CONST, vector_gtu_v2di_p) + +/* ISA 2.07 vector overloaded 1 argument functions. */ +BU_P8V_OVERLOAD_1 (VUPKHSW, "vupkhsw") +BU_P8V_OVERLOAD_1 (VUPKLSW, "vupklsw") + +/* ISA 2.07 vector overloaded 2 argument functions. */ +BU_P8V_OVERLOAD_2 (VADDUDM, "vaddudm") +BU_P8V_OVERLOAD_2 (VMAXSD, "vmaxsd") +BU_P8V_OVERLOAD_2 (VMAXUD, "vmaxud") +BU_P8V_OVERLOAD_2 (VMINSD, "vminsd") +BU_P8V_OVERLOAD_2 (VMINUD, "vminud") +BU_P8V_OVERLOAD_2 (VPKSDSS, "vpksdss") +BU_P8V_OVERLOAD_2 (VPKSDUS, "vpksdus") +BU_P8V_OVERLOAD_2 (VPKUDUM, "vpkudum") +BU_P8V_OVERLOAD_2 (VPKUDUS, "vpkudus") +BU_P8V_OVERLOAD_2 (VRLD, "vrld") +BU_P8V_OVERLOAD_2 (VSLD, "vsld") +BU_P8V_OVERLOAD_2 (VSRAD, "vsrad") +BU_P8V_OVERLOAD_2 (VSRD, "vsrd") +BU_P8V_OVERLOAD_2 (VSUBUDM, "vsubudm") + /* 1 argument crypto functions. */ BU_CRYPTO_1 (VSBOX, "vsbox", CONST, crypto_vsbox) diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c index c6c584d8183..801b5bb225d 100644 --- a/gcc/config/rs6000/rs6000-c.c +++ b/gcc/config/rs6000/rs6000-c.c @@ -511,6 +511,8 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 }, { ALTIVEC_BUILTIN_VEC_ABS, ALTIVEC_BUILTIN_ABS_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 }, + { ALTIVEC_BUILTIN_VEC_ABS, P8V_BUILTIN_ABS_V2DI, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 }, { ALTIVEC_BUILTIN_VEC_ABS, ALTIVEC_BUILTIN_ABS_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, { ALTIVEC_BUILTIN_VEC_ABS, VSX_BUILTIN_XVABSDP, @@ -583,12 +585,24 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 }, { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHSH, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 }, + { ALTIVEC_BUILTIN_VEC_UNPACKH, P8V_BUILTIN_VUPKHSW, + RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 }, + { ALTIVEC_BUILTIN_VEC_UNPACKH, P8V_BUILTIN_VUPKHSW, + RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 }, { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHPX, RS6000_BTI_unsigned_V4SI, RS6000_BTI_pixel_V8HI, 0, 0 }, { ALTIVEC_BUILTIN_VEC_VUPKHSH, ALTIVEC_BUILTIN_VUPKHSH, RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 }, { ALTIVEC_BUILTIN_VEC_VUPKHSH, ALTIVEC_BUILTIN_VUPKHSH, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 }, + { ALTIVEC_BUILTIN_VEC_UNPACKH, P8V_BUILTIN_VUPKHSW, + RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 }, + { ALTIVEC_BUILTIN_VEC_UNPACKH, P8V_BUILTIN_VUPKHSW, + RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 }, + { ALTIVEC_BUILTIN_VEC_VUPKHSH, P8V_BUILTIN_VUPKHSW, + RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 }, + { ALTIVEC_BUILTIN_VEC_VUPKHSH, P8V_BUILTIN_VUPKHSW, + RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 }, { ALTIVEC_BUILTIN_VEC_VUPKHPX, ALTIVEC_BUILTIN_VUPKHPX, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0, 0 }, { ALTIVEC_BUILTIN_VEC_VUPKHPX, ALTIVEC_BUILTIN_VUPKHPX, @@ -607,6 +621,10 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 }, { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLSH, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 }, + { ALTIVEC_BUILTIN_VEC_UNPACKL, P8V_BUILTIN_VUPKLSW, + RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 }, + { ALTIVEC_BUILTIN_VEC_UNPACKL, P8V_BUILTIN_VUPKLSW, + RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 }, { ALTIVEC_BUILTIN_VEC_VUPKLPX, ALTIVEC_BUILTIN_VUPKLPX, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0, 0 }, { ALTIVEC_BUILTIN_VEC_VUPKLPX, ALTIVEC_BUILTIN_VUPKLPX, @@ -657,6 +675,18 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, + { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM, + RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDFP, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, { ALTIVEC_BUILTIN_VEC_ADD, VSX_BUILTIN_XVADDDP, @@ -943,6 +973,10 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUW, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, + { ALTIVEC_BUILTIN_VEC_CMPEQ, P8V_BUILTIN_VCMPEQUD, + RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_CMPEQ, P8V_BUILTIN_VCMPEQUD, + RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQFP, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, { ALTIVEC_BUILTIN_VEC_CMPEQ, VSX_BUILTIN_XVCMPEQDP, @@ -981,6 +1015,10 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTSW, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, + { ALTIVEC_BUILTIN_VEC_CMPGT, P8V_BUILTIN_VCMPGTUD, + RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_CMPGT, P8V_BUILTIN_VCMPGTSD, + RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTFP, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, { ALTIVEC_BUILTIN_VEC_CMPGT, VSX_BUILTIN_XVCMPGTDP, @@ -1027,6 +1065,10 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTSW, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, + { ALTIVEC_BUILTIN_VEC_CMPLT, P8V_BUILTIN_VCMPGTUD, + RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_CMPLT, P8V_BUILTIN_VCMPGTSD, + RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTFP, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, { ALTIVEC_BUILTIN_VEC_CMPLT, VSX_BUILTIN_XVCMPGTDP, @@ -1424,6 +1466,18 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSW, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, + { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXUD, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXUD, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXUD, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXSD, + RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXSD, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXSD, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXFP, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, { ALTIVEC_BUILTIN_VEC_MAX, VSX_BUILTIN_XVMAXDP, @@ -1610,6 +1664,18 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSW, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, + { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINUD, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINUD, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINUD, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINSD, + RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINSD, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINSD, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINFP, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, { ALTIVEC_BUILTIN_VEC_MIN, VSX_BUILTIN_XVMINDP, @@ -1792,6 +1858,12 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUWUM, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, + { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_VPKUDUM, + RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_VPKUDUM, + RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_VPKUDUM, + RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 }, { ALTIVEC_BUILTIN_VEC_VPKUWUM, ALTIVEC_BUILTIN_VPKUWUM, RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_VPKUWUM, ALTIVEC_BUILTIN_VPKUWUM, @@ -1818,6 +1890,10 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_VPKUWUS, ALTIVEC_BUILTIN_VPKUWUS, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, + { ALTIVEC_BUILTIN_VEC_PACKS, P8V_BUILTIN_VPKUDUS, + RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_PACKS, P8V_BUILTIN_VPKSDSS, + RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, { ALTIVEC_BUILTIN_VEC_VPKSHSS, ALTIVEC_BUILTIN_VPKSHSS, RS6000_BTI_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, { ALTIVEC_BUILTIN_VEC_VPKUHUS, ALTIVEC_BUILTIN_VPKUHUS, @@ -1830,6 +1906,8 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_PACKSU, ALTIVEC_BUILTIN_VPKSWUS, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, + { ALTIVEC_BUILTIN_VEC_PACKSU, P8V_BUILTIN_VPKSDUS, + RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, { ALTIVEC_BUILTIN_VEC_VPKSWUS, ALTIVEC_BUILTIN_VPKSWUS, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_VPKSHUS, ALTIVEC_BUILTIN_VPKSHUS, @@ -1850,6 +1928,10 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLW, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, + { ALTIVEC_BUILTIN_VEC_RL, P8V_BUILTIN_VRLD, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_RL, P8V_BUILTIN_VRLD, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, { ALTIVEC_BUILTIN_VEC_VRLW, ALTIVEC_BUILTIN_VRLW, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_VRLW, ALTIVEC_BUILTIN_VRLW, @@ -1874,6 +1956,10 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLW, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, + { ALTIVEC_BUILTIN_VEC_SL, P8V_BUILTIN_VSLD, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_SL, P8V_BUILTIN_VSLD, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, { ALTIVEC_BUILTIN_VEC_SQRT, VSX_BUILTIN_XVSQRTDP, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, { ALTIVEC_BUILTIN_VEC_SQRT, VSX_BUILTIN_XVSQRTSP, @@ -2038,6 +2124,10 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRW, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, + { ALTIVEC_BUILTIN_VEC_SR, P8V_BUILTIN_VSRD, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_SR, P8V_BUILTIN_VSRD, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, { ALTIVEC_BUILTIN_VEC_VSRW, ALTIVEC_BUILTIN_VSRW, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_VSRW, ALTIVEC_BUILTIN_VSRW, @@ -2062,6 +2152,10 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAW, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, + { ALTIVEC_BUILTIN_VEC_SRA, P8V_BUILTIN_VSRAD, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_SRA, P8V_BUILTIN_VSRD, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, { ALTIVEC_BUILTIN_VEC_VSRAW, ALTIVEC_BUILTIN_VSRAW, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_VSRAW, ALTIVEC_BUILTIN_VSRAW, @@ -2202,6 +2296,18 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, + { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM, + RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBFP, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, { ALTIVEC_BUILTIN_VEC_SUB, VSX_BUILTIN_XVSUBDP, @@ -3333,6 +3439,20 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI }, { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P, RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI }, + { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P, + RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI }, + { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P, + RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI }, + { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P, + RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI }, + { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P, + RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI }, + { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P, + RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI }, + { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P, + RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI }, + { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P, + RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI }, { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQFP_P, RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF }, { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, VSX_BUILTIN_XVCMPEQDP_P, @@ -3378,6 +3498,18 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI }, { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSW_P, RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI }, + { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTUD_P, + RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI }, + { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTUD_P, + RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI }, + { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTUD_P, + RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI }, + { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTSD_P, + RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI }, + { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTSD_P, + RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI }, + { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTSD_P, + RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI }, { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGEFP_P, RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF }, { ALTIVEC_BUILTIN_VEC_VCMPGE_P, VSX_BUILTIN_XVCMPGEDP_P, diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 7963bf4d5c2..cb6876051d7 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -2226,12 +2226,13 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) } } - /* V2DImode, only allow under VSX, which can do V2DI insert/splat/extract. - Altivec doesn't have 64-bit support. */ + /* V2DImode, full mode depends on ISA 2.07 vector mode. Allow under VSX to + do insert/splat/extract. Altivec doesn't have 64-bit integer support. */ if (TARGET_VSX) { rs6000_vector_mem[V2DImode] = VECTOR_VSX; - rs6000_vector_unit[V2DImode] = VECTOR_NONE; + rs6000_vector_unit[V2DImode] + = (TARGET_P8_VECTOR) ? VECTOR_P8_VECTOR : VECTOR_NONE; rs6000_vector_align[V2DImode] = align64; } diff --git a/gcc/config/rs6000/vector.md b/gcc/config/rs6000/vector.md index c1d00ca2a9b..8b8b3427454 100644 --- a/gcc/config/rs6000/vector.md +++ b/gcc/config/rs6000/vector.md @@ -24,13 +24,13 @@ ;; Vector int modes -(define_mode_iterator VEC_I [V16QI V8HI V4SI]) +(define_mode_iterator VEC_I [V16QI V8HI V4SI V2DI]) ;; Vector float modes (define_mode_iterator VEC_F [V4SF V2DF]) ;; Vector arithmetic modes -(define_mode_iterator VEC_A [V16QI V8HI V4SI V4SF V2DF]) +(define_mode_iterator VEC_A [V16QI V8HI V4SI V2DI V4SF V2DF]) ;; Vector modes that need alginment via permutes (define_mode_iterator VEC_K [V16QI V8HI V4SI V4SF]) @@ -45,7 +45,7 @@ (define_mode_iterator VEC_N [V4SI V4SF V2DI V2DF]) ;; Vector comparison modes -(define_mode_iterator VEC_C [V16QI V8HI V4SI V4SF V2DF]) +(define_mode_iterator VEC_C [V16QI V8HI V4SI V2DI V4SF V2DF]) ;; Vector init/extract modes (define_mode_iterator VEC_E [V16QI V8HI V4SI V2DI V4SF V2DF]) @@ -1074,7 +1074,7 @@ [(set (match_operand:VEC_I 0 "vint_operand" "") (rotate:VEC_I (match_operand:VEC_I 1 "vint_operand" "") (match_operand:VEC_I 2 "vint_operand" "")))] - "TARGET_ALTIVEC" + "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)" "") ;; Expanders for arithmetic shift left on each vector element @@ -1082,7 +1082,7 @@ [(set (match_operand:VEC_I 0 "vint_operand" "") (ashift:VEC_I (match_operand:VEC_I 1 "vint_operand" "") (match_operand:VEC_I 2 "vint_operand" "")))] - "TARGET_ALTIVEC" + "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)" "") ;; Expanders for logical shift right on each vector element @@ -1090,7 +1090,7 @@ [(set (match_operand:VEC_I 0 "vint_operand" "") (lshiftrt:VEC_I (match_operand:VEC_I 1 "vint_operand" "") (match_operand:VEC_I 2 "vint_operand" "")))] - "TARGET_ALTIVEC" + "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)" "") ;; Expanders for arithmetic shift right on each vector element @@ -1098,7 +1098,7 @@ [(set (match_operand:VEC_I 0 "vint_operand" "") (ashiftrt:VEC_I (match_operand:VEC_I 1 "vint_operand" "") (match_operand:VEC_I 2 "vint_operand" "")))] - "TARGET_ALTIVEC" + "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)" "") ;; Vector reduction expanders for VSX diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index c71924ba6dd..e16222c5993 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -13964,6 +13964,143 @@ if the VSX instruction set is available. The @samp{vec_vsx_ld} and @samp{vec_vsx_st} built-in functions always generate the VSX @samp{LXVD2X}, @samp{LXVW4X}, @samp{STXVD2X}, and @samp{STXVW4X} instructions. +If the ISA 2.07 additions to the vector/scalar (power8-vector) +instruction set is available, the following additional functions are +available for both 32-bit and 64-bit targets. For 64-bit targets, you +can use @var{vector long} instead of @var{vector long long}, +@var{vector bool long} instead of @var{vector bool long long}, and +@var{vector unsigned long} instead of @var{vector unsigned long long}. + +@smallexample +vector long long vec_abs (vector long long); + +vector long long vec_add (vector long long, vector long long); +vector unsigned long long vec_add (vector unsigned long long, + vector unsigned long long); + +int vec_all_eq (vector long long, vector long long); +int vec_all_ge (vector long long, vector long long); +int vec_all_gt (vector long long, vector long long); +int vec_all_le (vector long long, vector long long); +int vec_all_lt (vector long long, vector long long); +int vec_all_ne (vector long long, vector long long); +int vec_any_eq (vector long long, vector long long); +int vec_any_ge (vector long long, vector long long); +int vec_any_gt (vector long long, vector long long); +int vec_any_le (vector long long, vector long long); +int vec_any_lt (vector long long, vector long long); +int vec_any_ne (vector long long, vector long long); + +vector long long vec_max (vector long long, vector long long); +vector unsigned long long vec_max (vector unsigned long long, + vector unsigned long long); + +vector long long vec_min (vector long long, vector long long); +vector unsigned long long vec_min (vector unsigned long long, + vector unsigned long long); + +vector int vec_pack (vector long long, vector long long); +vector unsigned int vec_pack (vector unsigned long long, + vector unsigned long long); +vector bool int vec_pack (vector bool long long, vector bool long long); + +vector int vec_packs (vector long long, vector long long); +vector unsigned int vec_packs (vector unsigned long long, + vector unsigned long long); + +vector unsigned int vec_packsu (vector long long, vector long long); + +vector long long vec_rl (vector long long, + vector unsigned long long); +vector long long vec_rl (vector unsigned long long, + vector unsigned long long); + +vector long long vec_sl (vector long long, vector unsigned long long); +vector long long vec_sl (vector unsigned long long, + vector unsigned long long); + +vector long long vec_sr (vector long long, vector unsigned long long); +vector unsigned long long char vec_sr (vector unsigned long long, + vector unsigned long long); + +vector long long vec_sra (vector long long, vector unsigned long long); +vector unsigned long long vec_sra (vector unsigned long long, + vector unsigned long long); + +vector long long vec_sub (vector long long, vector long long); +vector unsigned long long vec_sub (vector unsigned long long, + vector unsigned long long); + +vector long long vec_unpackh (vector int); +vector unsigned long long vec_unpackh (vector unsigned int); + +vector long long vec_unpackl (vector int); +vector unsigned long long vec_unpackl (vector unsigned int); + +vector long long vec_vaddudm (vector long long, vector long long); +vector long long vec_vaddudm (vector bool long long, vector long long); +vector long long vec_vaddudm (vector long long, vector bool long long); +vector unsigned long long vec_vaddudm (vector unsigned long long, + vector unsigned long long); +vector unsigned long long vec_vaddudm (vector bool unsigned long long, + vector unsigned long long); +vector unsigned long long vec_vaddudm (vector unsigned long long, + vector bool unsigned long long); + +vector long long vec_vmaxsd (vector long long, vector long long); + +vector unsigned long long vec_vmaxud (vector unsigned long long, + unsigned vector long long); + +vector long long vec_vminsd (vector long long, vector long long); + +vector unsigned long long vec_vminud (vector long long, + vector long long); + +vector int vec_vpksdss (vector long long, vector long long); +vector unsigned int vec_vpksdss (vector long long, vector long long); + +vector unsigned int vec_vpkudus (vector unsigned long long, + vector unsigned long long); + +vector int vec_vpkudum (vector long long, vector long long); +vector unsigned int vec_vpkudum (vector unsigned long long, + vector unsigned long long); +vector bool int vec_vpkudum (vector bool long long, vector bool long long); + +vector long long vec_vrld (vector long long, vector unsigned long long); +vector unsigned long long vec_vrld (vector unsigned long long, + vector unsigned long long); + +vector long long vec_vsld (vector long long, vector unsigned long long); +vector long long vec_vsld (vector unsigned long long, + vector unsigned long long); + +vector long long vec_vsrad (vector long long, vector unsigned long long); +vector unsigned long long vec_vsrad (vector unsigned long long, + vector unsigned long long); + +vector long long vec_vsrd (vector long long, vector unsigned long long); +vector unsigned long long char vec_vsrd (vector unsigned long long, + vector unsigned long long); + +vector long long vec_vsubudm (vector long long, vector long long); +vector long long vec_vsubudm (vector bool long long, vector long long); +vector long long vec_vsubudm (vector long long, vector bool long long); +vector unsigned long long vec_vsubudm (vector unsigned long long, + vector unsigned long long); +vector unsigned long long vec_vsubudm (vector bool long long, + vector unsigned long long); +vector unsigned long long vec_vsubudm (vector unsigned long long, + vector bool long long); + +vector long long vec_vupkhsw (vector int); +vector unsigned long long vec_vupkhsw (vector unsigned int); + +vector long long vec_vupklsw (vector int); +vector unsigned long long vec_vupklsw (vector int); +@end smallexample + If the cryptographic instructions are enabled (@option{-mcrypto} or @option{-mcpu=power8}), the following builtins are enabled. -- 2.30.2