From a5b120a103738c1f5ca9879c6f445a2a8edadb46 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 13 Apr 2021 15:32:37 +0100 Subject: [PATCH] update names of PLL connections for ls180 --- src/spec/ls180.py | 10 +++++----- src/spec/pinfunctions.py | 8 ++++++-- 2 files changed, 11 insertions(+), 7 deletions(-) diff --git a/src/spec/ls180.py b/src/spec/ls180.py index fb9a21b..e69a131 100644 --- a/src/spec/ls180.py +++ b/src/spec/ls180.py @@ -198,13 +198,13 @@ def pinparse(psp, pinspec): name = None elif name == 'sys_pllclk': name = None # ignore - elif name == 'sys_pllock': - name = 'sys_pll_lck_o' + elif name == 'sys_pllvcout': + name = 'sys_pll_vco_o' pad = ['p_' + name, name, name] - elif name == 'sys_pllout': - name = 'sys_pll_18_o' + elif name == 'sys_plltestout': + name = 'sys_pll_testout_o' pad = ['p_' + name, name, name] - elif name.startswith('sys_csel'): + elif name.startswith('sys_pllsel'): i = name[-1] name2 = 'sys_clksel_i(%s)' % i name = 'p_sys_clksel_' + i diff --git a/src/spec/pinfunctions.py b/src/spec/pinfunctions.py index da3b912..32f0e78 100644 --- a/src/spec/pinfunctions.py +++ b/src/spec/pinfunctions.py @@ -285,8 +285,12 @@ def vdd(suffix, bank): return (RangePin("-"), [], None) def sys(suffix, bank): - return (['CLK-', 'RST-', 'PLLCLK-', 'PLLOUT+', - 'CSEL0-', 'CSEL1-', 'PLLOCK+'], [], 'CLK') + return (['CLK-', 'RST-', + 'PLLCLK-', # PLL ref clock input + 'PLLSELA0-', 'PLLSELA1-', # PLL divider-selector + 'PLLTESTOUT+', # divided-output (for testing) + 'PLLVCOUT+', # PLL VCO analog out (for testing) + ], [], 'CLK') # list functions by name here -- 2.30.2