From a5bd4d6324e1c72a8e1e8874962aad6246061676 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 16 Jan 2022 16:29:13 +0000 Subject: [PATCH] raise interrupt on misaligned atomic LDST --- src/soc/fu/ldst/loadstore.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/soc/fu/ldst/loadstore.py b/src/soc/fu/ldst/loadstore.py index d13e525e..d0bedded 100644 --- a/src/soc/fu/ldst/loadstore.py +++ b/src/soc/fu/ldst/loadstore.py @@ -245,6 +245,8 @@ class LoadStore1(PortInterfaceBase): # check for LR/SC misalignment, used in set_rd/wr_addr above comb += self.lrsc_misalign.eq(((self.pi.data_len[0:3]-1) & self.req.raddr[0:3]).bool()) + with m.If(self.lrsc_misalign & self.req.reserve): + m.d.comb += self.req.align_intr.eq(1) # create a blip (single pulse) on valid read/write request # this can be over-ridden in the FSM to get dcache to re-run -- 2.30.2