From a5c42ce793e03f6abba4c12193df2cc2893fe64d Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 27 Jun 2019 07:36:56 +0100 Subject: [PATCH] add get on subvl --- riscv/processor.cc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/riscv/processor.cc b/riscv/processor.cc index c6d604a..c93c2e5 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -894,6 +894,8 @@ reg_t processor_t::get_csr(int which) (state.sv().ssvoffs<<26) | (state.sv().dsvoffs<<28); case CSR_USVMVL: return state.sv().mvl; + case CSR_USVSUBVL: + return state.sv().subvl; case CSR_SVREGTOP: case CSR_SVREGBOT: return 0;// XXX TODO: return correct entry -- 2.30.2