From a5d0785b97ca00f77678fabddb424ab7ae74e5ec Mon Sep 17 00:00:00 2001 From: Dmitry Selyutin Date: Tue, 8 Nov 2022 23:26:12 +0300 Subject: [PATCH] power_insn: support CR operands disassembly --- src/openpower/decoder/power_insn.py | 32 +++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/src/openpower/decoder/power_insn.py b/src/openpower/decoder/power_insn.py index 95f8f0f9..20bdbe72 100644 --- a/src/openpower/decoder/power_insn.py +++ b/src/openpower/decoder/power_insn.py @@ -1329,6 +1329,38 @@ class ConditionRegisterFieldOperand(ExtendableOperand): return super().assemble(value=value, insn=insn, prefix="cr") + def disassemble(self, insn, + verbosity=Verbosity.NORMAL, prefix="", indent=""): + (vector, value, span) = self.spec(insn=insn) + + if verbosity >= Verbosity.VERBOSE: + mode = "vector" if vector else "scalar" + yield f"{indent}{self.name} ({mode})" + yield f"{indent}{indent}{int(value):0{value.bits}b}" + yield f"{indent}{indent}{', '.join(span)}" + if isinstance(insn, SVP64Instruction): + extra_idx = self.extra_idx + if self.record.etype is _SVEtype.NONE: + yield f"{indent}{indent}extra[none]" + else: + etype = repr(self.record.etype).lower() + yield f"{indent}{indent}{etype}{extra_idx!r}" + else: + vector = "*" if vector else "" + cr = int(value >> 2) + cc = int(value & 3) + cond = ("lt", "gt", "eq", "so")[cc] + if verbosity >= Verbosity.NORMAL: + if cr != 0: + if isinstance(insn, SVP64Instruction): + yield f"{vector}cr{cr}.{cond}" + else: + yield f"4*cr{cr}+{cond}" + else: + yield cond + else: + yield f"{vector}{prefix}{int(value)}" + @_dataclasses.dataclass(eq=True, frozen=True) class CR3Operand(ConditionRegisterFieldOperand): -- 2.30.2