From a5d0a340c3b19c8c1eee7b2967db36199585461c Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 4 Aug 2020 09:37:53 +0200 Subject: [PATCH] test: specify wishbone adr_width on AXI(Lite)<-->Wishbone tests and remove debug traces. --- litex/soc/interconnect/axi.py | 6 ++---- test/test_axi.py | 2 +- test/test_axi_lite.py | 7 ++++--- 3 files changed, 7 insertions(+), 8 deletions(-) diff --git a/litex/soc/interconnect/axi.py b/litex/soc/interconnect/axi.py index 82d37f35..ec25bbae 100644 --- a/litex/soc/interconnect/axi.py +++ b/litex/soc/interconnect/axi.py @@ -496,8 +496,7 @@ class AXILite2Wishbone(Module): def __init__(self, axi_lite, wishbone, base_address=0x00000000): wishbone_adr_shift = log2_int(axi_lite.data_width//8) assert axi_lite.data_width == len(wishbone.dat_r) - assert axi_lite.address_width == len(wishbone.adr) + wishbone_adr_shift, "axi_addr_w={}; len_wb_adr={}; wb_adr_shift={};".format(axi_lite.address_width, len(wishbone.adr), wishbone_adr_shift) - print("####\n#### axi_addr_w={}; len_wb_adr={}; wb_adr_shift={};\n####".format(axi_lite.address_width, len(wishbone.adr), wishbone_adr_shift)) + assert axi_lite.address_width == len(wishbone.adr) + wishbone_adr_shift _data = Signal(axi_lite.data_width) _r_addr = Signal(axi_lite.address_width) @@ -581,8 +580,7 @@ class Wishbone2AXILite(Module): def __init__(self, wishbone, axi_lite, base_address=0x00000000): wishbone_adr_shift = log2_int(axi_lite.data_width//8) assert axi_lite.data_width == len(wishbone.dat_r) - assert axi_lite.address_width == len(wishbone.adr) + wishbone_adr_shift, "axi_addr_w={}; len_wb_adr={}; wb_adr_shift={};".format(axi_lite.address_width, len(wishbone.adr), wishbone_adr_shift) - print("####\n#### axi_addr_w={}; len_wb_adr={}; wb_adr_shift={};\n####".format(axi_lite.address_width, len(wishbone.adr), wishbone_adr_shift)) + assert axi_lite.address_width == len(wishbone.adr) + wishbone_adr_shift _cmd_done = Signal() _data_done = Signal() diff --git a/test/test_axi.py b/test/test_axi.py index d1963df0..256c0aea 100644 --- a/test/test_axi.py +++ b/test/test_axi.py @@ -237,7 +237,7 @@ class TestAXI(unittest.TestCase): class DUT(Module): def __init__(self): self.axi = AXIInterface(data_width=32, address_width=32, id_width=8) - self.wishbone = wishbone.Interface(data_width=32) + self.wishbone = wishbone.Interface(data_width=32, adr_width=30) axi2wishbone = AXI2Wishbone(self.axi, self.wishbone) self.submodules += axi2wishbone diff --git a/test/test_axi_lite.py b/test/test_axi_lite.py index 160f7e23..e24d9e8a 100644 --- a/test/test_axi_lite.py +++ b/test/test_axi_lite.py @@ -146,12 +146,12 @@ class TestAXILite(unittest.TestCase): def test_wishbone2axi2wishbone(self): class DUT(Module): def __init__(self): - self.wishbone = wishbone.Interface(data_width=32) + self.wishbone = wishbone.Interface(data_width=32, adr_width=30) # # # axi = AXILiteInterface(data_width=32, address_width=32) - wb = wishbone.Interface(data_width=32) + wb = wishbone.Interface(data_width=32, adr_width=30) wishbone2axi = Wishbone2AXILite(self.wishbone, axi) axi2wishbone = AXILite2Wishbone(axi, wb) @@ -190,7 +190,8 @@ class TestAXILite(unittest.TestCase): "axi_lite": (AXILiteInterface, AXI2AXILite, AXILiteSRAM), }[mem_bus] - bus = interface_cls() + bus_kwargs = {"adr_width" : 30} if mem_bus == "wishbone" else {} + bus = interface_cls(**bus_kwargs) self.submodules += converter_cls(axi, bus) sram = sram_cls(1024, init=[0x12345678, 0xa55aa55a]) self.submodules += sram -- 2.30.2