From a5df0fa0b1d821a3d3f6f483b0c712aff3dad364 Mon Sep 17 00:00:00 2001 From: Jose Maria Casanova Crespo Date: Wed, 24 Jul 2019 22:01:00 +0200 Subject: [PATCH] v3d: writes to magic registers aren't RF writes after THREND Shaders must not attempt to write to the register files in the last three instructions, but that doesn't include the magic registers: nop ; nop ; thrsw; ldtmu.- *** ERROR *** nop ; nop nop ; nop v2: Simplify validation rules. (Eric Anholt) v3: Adjust validation even more. (Eric Anholt) Reviewed-by: Eric Anholt --- src/broadcom/compiler/qpu_validate.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/broadcom/compiler/qpu_validate.c b/src/broadcom/compiler/qpu_validate.c index fb2ed123aba..24be4fd39e5 100644 --- a/src/broadcom/compiler/qpu_validate.c +++ b/src/broadcom/compiler/qpu_validate.c @@ -258,8 +258,10 @@ qpu_validate_inst(struct v3d_qpu_validate_state *state, struct qinst *qinst) fail_instr(state, "RF write after THREND"); } - if (v3d_qpu_sig_writes_address(devinfo, &inst->sig)) + if (v3d_qpu_sig_writes_address(devinfo, &inst->sig) && + !inst->sig_magic) { fail_instr(state, "RF write after THREND"); + } /* GFXH-1625: No TMUWT in the last instruction */ if (state->last_thrsw_ip - state->ip == 2 && -- 2.30.2