From a5e2e7f9a4bc813ce85f4a10bcd6086f21aa8a32 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Fri, 4 Oct 2013 17:46:04 -0700 Subject: [PATCH] i965: Add support for GL_ARB_texture_buffer_range. Supporting this extension turns out to simplify our code a bit over not supporting this extension, once the glBufferSubData() synchronization code lands. v2: Use 16 byte alignment like we do for uniform buffers, due to unaligned access penalties. Reviewed-by: Jordan Justen (v1) --- docs/GL3.txt | 2 +- src/mesa/drivers/dri/i965/brw_context.c | 11 +++++++++++ src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 15 +++++++++++---- src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 14 ++++++++++---- src/mesa/drivers/dri/i965/intel_extensions.c | 1 + 5 files changed, 34 insertions(+), 9 deletions(-) diff --git a/docs/GL3.txt b/docs/GL3.txt index af75b094619..ff28ea6a813 100644 --- a/docs/GL3.txt +++ b/docs/GL3.txt @@ -157,7 +157,7 @@ ARB_robust_buffer_access_behavior not started ARB_shader_image_size not started ARB_shader_storage_buffer_object not started ARB_stencil_texturing not started -ARB_texture_buffer_range DONE (nv50, nvc0) +ARB_texture_buffer_range DONE (nv50, nvc0, i965) ARB_texture_query_levels DONE (i965) ARB_texture_storage_multisample DONE (i965) ARB_texture_view not started diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c index 55856b36637..cb82fb042ef 100644 --- a/src/mesa/drivers/dri/i965/brw_context.c +++ b/src/mesa/drivers/dri/i965/brw_context.c @@ -394,7 +394,18 @@ brw_initialize_context_constants(struct brw_context *brw) ctx->Const.NativeIntegers = true; ctx->Const.UniformBooleanTrue = 1; + + /* From the gen4 PRM, volume 4 page 127: + * + * "For SURFTYPE_BUFFER non-rendertarget surfaces, this field specifies + * the base address of the first element of the surface, computed in + * software by adding the surface base address to the byte offset of + * the element in the buffer." + * + * However, unaligned accesses are slower, so enforce buffer alignment. + */ ctx->Const.UniformBufferOffsetAlignment = 16; + ctx->Const.TextureBufferOffsetAlignment = 16; if (brw->gen >= 6) { ctx->Const.MaxVarying = 32; diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index c7a0be59750..a78ebf00405 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c @@ -232,20 +232,27 @@ brw_update_buffer_texture_surface(struct gl_context *ctx, struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current; struct intel_buffer_object *intel_obj = intel_buffer_object(tObj->BufferObject); - drm_intel_bo *bo = intel_obj ? intel_obj->buffer : NULL; + uint32_t size = tObj->BufferSize; + drm_intel_bo *bo = NULL; gl_format format = tObj->_BufferObjectFormat; uint32_t brw_format = brw_format_for_mesa_format(format); int texel_size = _mesa_get_format_bytes(format); - int w = intel_obj ? intel_obj->Base.Size / texel_size : 0; + + if (intel_obj) { + bo = intel_obj->buffer; + size = MIN2(size, intel_obj->Base.Size); + } if (brw_format == 0 && format != MESA_FORMAT_RGBA_FLOAT32) { _mesa_problem(NULL, "bad format %s for texture buffer\n", _mesa_get_format_name(format)); } - gen4_emit_buffer_surface_state(brw, surf_offset, bo, 0, + gen4_emit_buffer_surface_state(brw, surf_offset, bo, + tObj->BufferOffset, brw_format, - w, texel_size); + size / texel_size, + texel_size); } static void diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c index 4488d48e59b..9880c14dd1b 100644 --- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c @@ -274,7 +274,14 @@ gen7_update_buffer_texture_surface(struct gl_context *ctx, struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current; struct intel_buffer_object *intel_obj = intel_buffer_object(tObj->BufferObject); - drm_intel_bo *bo = intel_obj ? intel_obj->buffer : NULL; + uint32_t size = tObj->BufferSize; + drm_intel_bo *bo = NULL; + + if (intel_obj) { + bo = intel_obj->buffer; + size = MIN2(size, intel_obj->Base.Size); + } + gl_format format = tObj->_BufferObjectFormat; uint32_t surface_format = brw_format_for_mesa_format(format); @@ -284,14 +291,13 @@ gen7_update_buffer_texture_surface(struct gl_context *ctx, } int texel_size = _mesa_get_format_bytes(format); - int w = intel_obj ? intel_obj->Base.Size / texel_size : 0; gen7_emit_buffer_surface_state(brw, surf_offset, bo, - 0, + tObj->BufferOffset, surface_format, - w, + size / texel_size, texel_size, 0 /* mocs */); } diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c b/src/mesa/drivers/dri/i965/intel_extensions.c index 87cc87d4f5f..22e4aa2c5ad 100644 --- a/src/mesa/drivers/dri/i965/intel_extensions.c +++ b/src/mesa/drivers/dri/i965/intel_extensions.c @@ -147,6 +147,7 @@ intelInitExtensions(struct gl_context *ctx) ctx->Extensions.ARB_shading_language_420pack = true; ctx->Extensions.ARB_texture_buffer_object = true; ctx->Extensions.ARB_texture_buffer_object_rgb32 = true; + ctx->Extensions.ARB_texture_buffer_range = true; ctx->Extensions.ARB_texture_cube_map_array = true; ctx->Extensions.OES_depth_texture_cube_map = true; ctx->Extensions.ARB_shading_language_packing = true; -- 2.30.2