From a5eaf172c5411902555b1f62ec1ffeaa57377ac3 Mon Sep 17 00:00:00 2001 From: Daniel Kucera Date: Tue, 13 Aug 2019 10:14:16 +0200 Subject: [PATCH] more understandable error when missing a memory --- litex/soc/integration/soc_core.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py index c70a9c90..f2a09627 100644 --- a/litex/soc/integration/soc_core.py +++ b/litex/soc/integration/soc_core.py @@ -501,7 +501,7 @@ class SoCCore(Module): if self.cpu_type is not None: for mem in "rom", "sram": if mem not in registered_mems: - raise FinalizeError("CPU needs a {} to be registered with SoC.register_mem()".format(mem)) + raise FinalizeError("CPU needs \"{}\" to be registered with SoC.register_mem()".format(mem)) # Add the Wishbone Masters/Slaves interconnect if len(self._wb_masters): -- 2.30.2