From a5eb66004cd0bef5dd9319c3449189f560b70230 Mon Sep 17 00:00:00 2001 From: lkcl Date: Sun, 20 Dec 2020 16:53:57 +0000 Subject: [PATCH] --- openpower/sv/svp_rewrite/svp64.mdwn | 30 ++++++++++++++--------------- 1 file changed, 14 insertions(+), 16 deletions(-) diff --git a/openpower/sv/svp_rewrite/svp64.mdwn b/openpower/sv/svp_rewrite/svp64.mdwn index fa64a93ac..8c7606d7c 100644 --- a/openpower/sv/svp_rewrite/svp64.mdwn +++ b/openpower/sv/svp_rewrite/svp64.mdwn @@ -278,7 +278,19 @@ or EXTRA3 field from the SV Prefix. The prefixing is arranged so that interoperability between prefixing and nonprefixing of scalar registers is direct and convenient (when the EXTRA field is all zeros). -## EXTRA3 +pseudocode algorithm for original version is identical to the 3 bit version except +that the spec is shifted up by one bit + + if extra3_mode: + spec = EXTRA3 + else: + spec = EXTRA2 << 1 # same as EXTRA3, shifted + if spec[2]: # vector + return RA << 2 | spec[0:1] + else: # scalar + return RA | spec[0:1] << 5 + +## INT/FP EXTRA3 alternative which is understandable and, if EXTRA3 is zero, maps to "no effect" (scalar OpenPOWER ISA field naming). also, these are the @@ -297,7 +309,7 @@ registers have access to the same 32 registers. | 110 | Vector | `r2-r126` | `RA 0b10` | | 111 | Vector | `r3-r127` | `RA 0b11` | -## EXTRA2 +## INT/FP EXTRA2 alternative which is understandable and, if EXTRA2 is zero will map to "no effect" i.e Scalar OpenPOWER register naming: @@ -309,20 +321,6 @@ alternative which is understandable and, if EXTRA2 is zero will map to | 10 | Vector | `r0-r124` | `RA 0b00` | | 11 | Vector | `r2-r126` | `RA 0b10` | -## Pseudocode - -algorithm for original version is identical to the 3 bit version except -that the spec is shifted up by one bit - - if extra3_mode: - spec = EXTRA3 - else: - spec = EXTRA2 << 1 # same as EXTRA3, shifted - if spec[2]: # vector - return RA << 2 | spec[0:1] - else: # scalar - return RA | spec[0:1] << 5 - ## CR EXTRA3 CR encoding is essentially the same but made more complex due to CRs being bit-based. See separate section for explanation and pseudocode. -- 2.30.2