From a613a073191df7ba12e445bb49817a18a1da6e90 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 2 Mar 2023 12:03:01 +0000 Subject: [PATCH] add section VA2-Form regs needed update descriptions of dsld and dsrd in ls003 --- openpower/sv/rfc/ls003.mdwn | 76 ++++++++++++++++++++++++++++--------- 1 file changed, 59 insertions(+), 17 deletions(-) diff --git a/openpower/sv/rfc/ls003.mdwn b/openpower/sv/rfc/ls003.mdwn index dfc546291..43e231ce3 100644 --- a/openpower/sv/rfc/ls003.mdwn +++ b/openpower/sv/rfc/ls003.mdwn @@ -262,7 +262,7 @@ Pseudo-code: n <- (RB)[58:63] # Use lower 6-bits for shift v <- ROTL64((RA), n) # Rotate RA 64-bit left by n bits - mask <- MASK(64, 63-n) # 1's mask in MSBs + mask <- MASK(64, 63-n) # 1s mask in MSBs RT <- (v[0:63] & mask) | ((RC) & ¬mask) # mask-in RC into RT RS <- v[0:63] & ¬mask # part normally lost into RC overflow = 0 # Clear overflow flag @@ -275,17 +275,19 @@ Special Registers Altered: The contents of register RA are shifted left the number of bits specified by (RB) 58:63. The same number of -shifted bits are taken from register RC and placed into -the LSBs of the result, RT. +shifted bits are taken from the **right** (MSB) end of register +RC and placed into the LSBs of the result, RT. Additionally, the MSB bits of register RA that would normally be discarded by a 64-bit left shift are placed into the -LSBs of RS. +MSBs of RS. -*Note: When Rc=1, and the value in RS is nonzero, -the overflow flag is raised in CR0.* +When Rc=1, and the value in RS is nonzero, +the overflow flag is raised in CR0. All other bits of CR0 +are set to zero. XER.OV and XER.SO remain unchanged. *Programmer's note: -similar to maddedu and divmod2du, dsld can be chained (using RC).* +similar to maddedu and divmod2du, dsld can be chained (using RC), +effectively using RC as a 64-bit carry-in and carry-out.* \newpage{} @@ -312,6 +314,22 @@ Special Registers Altered: CR0 (if Rc=1) +The contents of register RA are shifted right the number +of bits specified by (RB) 58:63. The same number of +shifted bits are taken from the **left** (LSB) end of register RC +and placed into the MSBs of the result, RT. +Additionally, the MSB bits of register RA that would normally +be discarded by a 64-bit right shift are placed into the +MSBs of RS. + +When Rc=1, and the value in RS is nonzero, +the overflow flag is raised in CR0. All other bits of CR0 +are set to zero. XER.OV and XER.SO remain unchanged. + +*Programmer's note: +similar to maddedu and divmod2du, dsrd can be chained (using RC), +effectively using RC as a 64-bit carry-in and carry-out.* + \newpage{} # VA2-Form @@ -323,18 +341,40 @@ Add the following to Book I, 1.6.21.1, VA2-Form | PO | RT | RA | RB | RC | XO | Rc | ``` -Add `RA` to `XO` Field in Book I, 1.6.2 +Add 'VA2-Form' to `RA` thru `XO` Field in Book I, 1.6.2 ``` RA (11:15) Field used to specify a GPR to be used as a source or as a target. - Formats: A, BM2, D, DQ, DQE, DS, M, MD, MDS, TX, VA, VA2, - VX, X, XO, XS, SVL, XB, TLI, Z23 -``` + Formats: ... VA2, ... + +RB (16:20) + Field used to specify a GPR to be used as a + source. + Formats: ... VA2, ... -*TODO* other fields `RT, RB, RC, XO, and Rc`, see - +RC (21:25) + Field used to specify a GPR to be used as a + source. + Formats: ... VA2, ... + +Rc (31) + RECORD bit. + 0 Do not alter the Condition Register. + 1 Set Condition Register Field 0 or Field 1 as + described in Section 2.3.1, 'Condition Regis- + ter' on page 30. + Formats: ... VA2, ... + +RT (6:10) + Field used to specify a GPR to be used as a target. + Formats: ... VA2, ... + +XO (26:30) + Extended opcode field. + Formats: ... VA2, ... +``` # Appendices @@ -343,10 +383,12 @@ RA (11:15) Appendix G Power ISA sorted by Compliancy Subset Appendix H Power ISA sorted by mnemonic -| Form | Book | Page | Version | mnemonic | Description | -|------|------|------|---------|----------|-------------| -| VA | I | # | 3.0B | maddedu | Multiply-Add Extend Double Unsigned | -| VA | I | # | 3.0B | divmod2du | Divide/Modulo Quad-Double Unsigned | +|Form| Book | Page | Version | mnemonic | Description | +|----|------|------|---------|----------|-------------| +|VA | I | # | 3.0B |maddedu | Multiply-Add Extend Double Unsigned | +|VA | I | # | 3.0B |divmod2du | Divide/Modulo Quad-Double Unsigned | +|VA2 | I | # | 3.0B |dsld | Double-Shift Left Doubleword | +|VA2 | I | # | 3.0B |dsrd | Double-Shift Right Doubleword | ---------------- -- 2.30.2