From a61c1834ea6d26b6761ac6ccb1c0db8f01e2b94b Mon Sep 17 00:00:00 2001 From: whitequark Date: Sat, 1 Feb 2020 02:15:45 +0000 Subject: [PATCH] hdl.dsl: don't allow inheriting from Module. `Module` is an object with a lot of complex and sometimes fragile behavior that overrides Python attribute accessors and so on. To prevent user designs from breaking when it is changed, it is not supposed to be inherited from (unlike in Migen), but rather returned from the elaborate() method. This commit makes sure it will not be inherited from by accident (most likely by users familiar with Migen). Fixes #286. --- nmigen/hdl/dsl.py | 5 +++++ nmigen/test/test_hdl_dsl.py | 7 +++++++ 2 files changed, 12 insertions(+) diff --git a/nmigen/hdl/dsl.py b/nmigen/hdl/dsl.py index 986ecc0..247e07e 100644 --- a/nmigen/hdl/dsl.py +++ b/nmigen/hdl/dsl.py @@ -148,6 +148,11 @@ class FSM: class Module(_ModuleBuilderRoot, Elaboratable): + @classmethod + def __init_subclass__(cls): + raise SyntaxError("Instead of inheriting from `Module`, inherit from `Elaboratable` " + "and return a `Module` from the `elaborate(self, platform)` method") + def __init__(self): _ModuleBuilderRoot.__init__(self, self, depth=0) self.submodules = _ModuleBuilderSubmodules(self) diff --git a/nmigen/test/test_hdl_dsl.py b/nmigen/test/test_hdl_dsl.py index 1ef32fa..7573941 100644 --- a/nmigen/test/test_hdl_dsl.py +++ b/nmigen/test/test_hdl_dsl.py @@ -19,6 +19,13 @@ class DSLTestCase(FHDLTestCase): self.c3 = Signal() self.w1 = Signal(4) + def test_cant_inherit(self): + with self.assertRaises(SyntaxError, + msg="Instead of inheriting from `Module`, inherit from `Elaboratable` and " + "return a `Module` from the `elaborate(self, platform)` method"): + class ORGate(Module): + pass + def test_d_comb(self): m = Module() m.d.comb += self.c1.eq(1) -- 2.30.2