From a645950fa2d3c64b63b187485034dbafd115a16d Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 6 Sep 2020 12:13:16 +0100 Subject: [PATCH] add DEC SPR to CoreState and PowerDecoder, activate 0x900 interrupt --- src/soc/config/state.py | 1 + src/soc/consts.py | 5 +++-- src/soc/decoder/power_decoder2.py | 7 ++++++- 3 files changed, 10 insertions(+), 3 deletions(-) diff --git a/src/soc/config/state.py b/src/soc/config/state.py index e4cef69c..3fc91967 100644 --- a/src/soc/config/state.py +++ b/src/soc/config/state.py @@ -8,3 +8,4 @@ class CoreState(RecordObject): self.pc = Signal(64) # Program Counter (CIA, NIA) self.msr = Signal(64) # Machine Status Register (MSR) self.eint = Signal() # External Interrupt + self.dec = Signal(64) # DEC SPR (again, for interrupt generation) diff --git a/src/soc/consts.py b/src/soc/consts.py index 505fce3d..f7e55f1a 100644 --- a/src/soc/consts.py +++ b/src/soc/consts.py @@ -142,6 +142,7 @@ class TT: TRAP = 1<<2 ADDR = 1<<3 EINT = 1<<4 # external interrupt - ILLEG = 1<<5 # currently the max, therefore traptype must be 5 bits + DEC = 1<<5 # decrement counter + ILLEG = 1<<6 # currently the max, therefore traptype must be 5 bits # TODO: support for TM_BAD_THING (not included yet in trap main_stage.py) - size = 6 # MUST update this to contain the full number of Trap Types + size = 7 # MUST update this to contain the full number of Trap Types diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py index f6b88a85..83238391 100644 --- a/src/soc/decoder/power_decoder2.py +++ b/src/soc/decoder/power_decoder2.py @@ -633,8 +633,9 @@ class PowerDecode2(Elaboratable): def elaborate(self, platform): m = Module() comb = m.d.comb + state = self.state e_out, op, do_out = self.e, self.dec.op, self.e.do - msr, cia, ext_irq = self.state.msr, self.state.pc, self.state.eint + dec_spr, msr, cia, ext_irq = state.dec, state.msr, state.pc, state.eint # fill in for a normal instruction (not an exception) # copy over if non-exception, non-privileged etc. is detected @@ -756,6 +757,10 @@ class PowerDecode2(Elaboratable): with m.If(ext_irq & msr[MSR.EE]): self.trap(m, TT.EINT, 0x500) + # decrement counter: TODO 32-bit version (MSR.LPCR) + with m.If(dec_spr[63] & msr[MSR.EE]): # v3.0B 6.5.11 p1076 + self.trap(m, TT.DEC, 0x900) # v3.0B 6.5 p1065 + # privileged instruction trap with m.Elif(is_priv_insn & msr[MSR.PR]): self.trap(m, TT.PRIV, 0x700) -- 2.30.2