From a66cb0e14098ff9cd20b9ce6cb6171757383981c Mon Sep 17 00:00:00 2001 From: Tobias Platen Date: Mon, 4 Apr 2022 17:48:01 +0200 Subject: [PATCH] correct wishbone data directions --- fpga/top-generic.vhdl | 5 +++-- soc.vhdl | 6 +++--- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/fpga/top-generic.vhdl b/fpga/top-generic.vhdl index 01dc9e5..75426e3 100644 --- a/fpga/top-generic.vhdl +++ b/fpga/top-generic.vhdl @@ -35,9 +35,10 @@ entity toplevel is bram_we : out std_ulogic; bram_re : out std_ulogic; bram_addr : out std_logic_vector(log2ceil(MEMORY_SIZE) - 3- 1 downto 0); - bram_di : inout std_logic_vector(63 downto 0); - bram_do : out std_logic_vector(63 downto 0); + bram_di : out std_logic_vector(63 downto 0); + bram_do : in std_logic_vector(63 downto 0); bram_sel : out std_logic_vector(7 downto 0); + -- for verilator debugging nia_req: out std_ulogic; diff --git a/soc.vhdl b/soc.vhdl index f46b353..ca22e6f 100644 --- a/soc.vhdl +++ b/soc.vhdl @@ -121,12 +121,12 @@ entity soc is ext_irq_eth : in std_ulogic := '0'; ext_irq_sdcard : in std_ulogic := '0'; - -- BRAM verilator access [FIXME] + -- BRAM verilator access [UNTESTED] bram_we : out std_ulogic; bram_re : out std_ulogic; bram_addr : out std_logic_vector(log2ceil(MEMORY_SIZE) - 3- 1 downto 0); - bram_di : inout std_logic_vector(63 downto 0); - bram_do : out std_logic_vector(63 downto 0); + bram_di : out std_logic_vector(63 downto 0); + bram_do : in std_logic_vector(63 downto 0); bram_sel : out std_logic_vector(7 downto 0); -- UART0 signals: -- 2.30.2